LM3204TLEV

User's Guide SNVA119C – September 2005 – Revised April 2013 AN-1391 LM3204 Evaluation Board 1 Introduction The LM3204 evaluation board is a working demonstration of a buck converter. This document contains information about the board. For further information on buck converter topology and component selection, see the device-specific data sheet. 2 General Description The LM3204 converts high input voltages to lower output voltages with high efficiency. It does this through a inductor based switching topology, applying the input voltage to the inductor for a certain portion of the cycle. The duty cycle in pulse width modulation (PWM) mode will be VOUT / VIN, which can be seen on the SW pin. There are three modes of operation. These are fixed frequency PWM, forced bypass, and shutdown mode. Setting the BYP pin low (1.2 V) places the device in forced bypass mode. Setting the EN pin low (1.2 V) enables normal operation. At the PWM mode, the output voltage is setting by the voltage of the VCON pin, as in Equation 1: VOUT = 3 x VCON 3 (1) Operating Conditions The board will operate under the following conditions: 2.7 V ≤ VIN ≤ 5.5 V 0.267 V ≤ VCON ≤ 1.2 V 0mA ≤ IOUT ≤ 300mA (PWM mode) 0mA ≤ IOUT ≤ 500mA (Bypass mode) 4 Schematic VIN C4 0.1 PF C1 PVIN 10 PF VDD BYPOUT EN L1 2.2 PH VOUT SW BYP LM3204 FB VCON VCON PGND SGND C2 4.7 PF 0.267V to 1.20V Figure 1. Typical Operating Circuit All trademarks are the property of their respective owners. SNVA119C – September 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1391 LM3204 Evaluation Board 1 Board Layout 5 www.ti.com Board Layout 2.2uH 4.7uF 10uF LM3204 0.1uF Vcon BYP EN Figure 2. Top Layer xxxxxxxxx-001 rev A LM3204 R7 R6 C3 R1 C5 R3 R2 Figure 3. Bottom Layer 2 AN-1391 LM3204 Evaluation Board SNVA119C – September 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Board Schematic www.ti.com 6 Board Schematic R4 R6 0: VIN VDD C4 0.1 PF BYPOUT PVIN C1 10 PF EN E R5 L1 2.2 PH LM3204 B BYP SW VCON FB VOUT R3 C R1 0: R2 C2 4.7 PF C3 C5 SGND R7 0: PGND GND Figure 4. Complete Evaluation Board Schematic 7 PCB Guidelines For your application circuit, proper layout for the buck regulator should be implemented by following a few simple guidelines. (Also, see the Board Layout Considerations section in the device-specific data sheet.) • Place C1 right next to the device between PVIN and PGND pin. • Place C4 right next to the device between VDD and SGND pin. • Make the traces drawn with heavy lines, which are Power lines, as short and as wide as possible. • Making the traces drawn with heavy lines on the same layer should be good. However, place as many vias as possible if traces are on multiple layers. SNVA119C – September 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1391 LM3204 Evaluation Board 3 Bill of Materials (BOM) 8 www.ti.com Bill of Materials (BOM) Table 1. Bill of Materials Designator Footprint Manufacture Manufacture # Description C1 (input C) 1206 (3216) TDK C3216JB1A106K 10 µF, 10 V, 20% C2 (output C) 1206 (3216) TDK C2012JB0J475K 4.7 µF, 6.3 V, 20% C3 0603 (1608) optional C4 (input C) 0402 (1005) 0.1 µF, 10 V, 20% C5 0805 (2012) optional L1 (inductor) Coilcraft DO3314-222 2.2 µH inductor, 1.6A Isat, 0.2 Ωmax. R1 0603 (1608) 0Ω R2 0603 (1608) optional R3 0603 (1608) optional R4 Do not use R5 0603 (1608) optional R6 0603 (1608) 0Ω R7 0603 (1608) 0Ω COMMON TO ALL VIN banana jack - red Johnson Components 108-0902-001 conn jack banana insul nylon red VOUT banana jack - yellow Johnson Components 108-0907-001 conn jack banana insul nylon yellow GND banana jack - black Johnson Components 108-0903-001 conn jack banana insul nylon black 9 Connection Diagrams SGND A2 SGND A2 A3 BYPOUT VDD A1 VCON B1 FB C1 B3 PVIN PVIN B3 C3 SW SW C3 D3 PGND BYP D1 A1 VDD BYPOUT A3 B1 VCON C1 FB D1 BYP PGND D3 D2 EN D2 EN Figure 5. Top View Figure 6. Bottom View Figure 7. 10–Bump Thin DSBGA Package, Large Bump 4 AN-1391 LM3204 Evaluation Board SNVA119C – September 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Connection Diagrams www.ti.com Table 2. Pin Descriptions Pin No Name Description A1 VDD Analog Supply Input. A 0.1µF ceramic capacitor is recommended to be placed as close to this pin as possible. B1 VCON Voltage Control Analog input. VCON controls VOUT in PWM mode. Set: VOUT = 3 x VCON. Do not leave floating. C1 FB D1 BYP Bypass. Use this digital input to command operation in Bypass mode. Set the BYP pin high (> 1.2 V ) for Bypass mode. Set BYP low (< 0.4 V ) for normal operation. D2 EN Enable Input. Set this digital input high (> 1.2 V) after VIN > 2.7 V for normal operation. For shutdown, set low (< 0.4 V). D3 PGND C3 SW Switching Node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit specification of the LM3204. B3 PVIN Power Supply Voltage Input to the internal PFET switch and Bypass FET. A3 BYPOUT Bypass FET Drain. Connect to the output capacitor. Do not leave floating. A2 SGND Feedback Analog Input. Connect to the output at the output filter capacitor. Power Ground Analog and Control Ground SNVA119C – September 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1391 LM3204 Evaluation Board 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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