User's Guide
SNVA179B – August 2006 – Revised April 2013
AN-1505 LM3207 Evaluation Board
1
Introduction
The LM3207 evaluation board is a working demonstration of a step down DC-DC converter. This user's
guide contains information about the evaluation board and board layout considerations. For further
information on buck converter topology, device electrical characteristics, and component selection, please
refer to LM3207 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers with
Integrated Vref LDO (SNVS400).
2
General Description
The LM3207 is a DC-DC converter optimized for powering RF power amplifiers (RFPAs) from a single
Lithium-Ion cell, however the device may be used in many other applications. The LM3207 steps down an
input voltage range from 2.7V to 5.5V to a variable output voltage range from 0.8V to 3.6V. Output voltage
is set using a VCON analog input for controlling power levels and efficiency of the RF PA.
The LM3207 also provides a regulated reference voltage(Vref) required by linear RF power amplifiers
through an integrated LDO with a nominal has a maximum Iref of 10 mA.
The LM3207 offers superior performance for powering WCMDA / CDMA RF power amplifiers and similar
applications. Fixed-frequency PWM operation minimizes RF interference. Shutdown function turns the
device off and reduces battery consumption to 0.01 µA (typ).
The LM3207 is available in a 9-pin lead free DSBGA package. A high switching frequency (2 MHz) allows
use of tiny surface-mount components. Only four small external components are required, an inductor and
three ceramic capacitors.
3
Operating Conditions
•
•
•
•
4
VIN range: 2.7V ≤ VIN ≤ 5.5V
VCON range: 0.32V ≤ VCON ≤ 1.44V
VOUT equation: VOUT = 2.5 x VCON
IOUT range: 0 mA≤ IOUT ≤ 650 mA
Typical Application
Vin
2.7V to 5.5V
VOUT
3.3 PH
PVIN
EN
0.8V to 3.6V
SW
FB
10 PF
VCON
4.7 PF
LM3207
LDO OUT
ENLDO
SGND
LDO
PGND
100 nF
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Connection Diagram and Package Mark Information
5
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Connection Diagram and Package Mark Information
SW
PVIN
A1
A2
A3
PGND
ENLDO
B1
EN
B2
B3
SGND
FB
C1
C2
C3
LDO
Vcon
Top View
Figure 1. 9–Bump Thin DSBGA Package, Large Bump
Table 1. Pin Descriptions
6
Pin #
Name
A1
PVIN
Description
B1
ENLDO
C1
FB
C2
VCON
Voltage Control Analog input. VCON controls VOUT in PWM mode.
C3
LDO
LDO Output Voltage.
B3
SGND
Analog and Control Ground
A3
PGND
Power Ground
A2
SW
Switch node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an
inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit
specification of the LM3207.
B2
EN
PWM enable Input. Set this digital input high for normal operation. For shutdown, set low.
Power Supply Voltage Input to the internal PFET switch.
LDO Enable Input. Set this digital input high to turn on LDO (EN pin must also be set high). For
shutdown, set low.
Feedback Analog Input. Connect to the output at the output filter capacitor.
Bill of Materials for Common Configurations
Manufacture
Description
TDK
C1608X5R0J106M
10 µF,6.3V,10%,0603
C2 (output C)
TDK
C1608X5R0J475M
4.7 µF,6.3V,10%,0603
C3 (optional, input C)
0.1 µF,25V , 0402 (1)
C4 (optional, filter for VCON)
10 - 100 pF, 25V , 0402 (1)
C7 (LDO Cap)
TDK
C1005X5R1A104KT
100nF,10V, 0402
L1 (inductor)
Taiyo-Yuden
NR3015T3R3M
3.3 µH, 1210mA, 3×3×1.5 mm
VIN banana jack - red
Johnson
Components
108-0902-001
connector, insulated banana jack (red)
Vout banana jack - yellow
Johnson
Components
108-0907-001
connector, insulated banana jack (yellow)
GND banana jack - black
Johnson
Components
108-0903-001
connector, insulated banana jack (black)
LDO Out banana jack - yellow
Johnson
Components
108-0907-001
connector, insulated banana jack (yellow)
(1)
2
Manufacture #
C1 (input C)
C3 and C4 are recommended for a better noise performance.
AN-1505 LM3207 Evaluation Board
SNVA179B – August 2006 – Revised April 2013
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Board Layout Considerations
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7
Board Layout Considerations
The LM3207 converts higher input voltage to lower output voltage with high efficiency. This is achieved
with an inductor-based switching topology. During the first half of the switching cycle, the internal PMOS
switch turns on, the input voltage is applied to the inductor, and the current flows from PVIN line to the
output capacitor (C2) through the inductor. During the second half cycle, the PMOS turns off and the
internal NMOS turns on. The inductor current continues to flow via the inductor from the device PGND line
to the output capacitor (C2). The inductor current continues to flow via the inductor from the device PGND
line to the output capacitor (C2) .
Referring to Figure 2, the LM3207 has two major current loops where pulse and ripple current flow. The
loop shown in the left hand side is important because pulse current flows in this path. In the loop on the
right hand side, the current waveform in this path is triangular. Pulse current has many high-frequency
components due to fast di/dt. Triangular ripple current also has wide high-frequency components. Board
layout and circuit pattern design of these two loops are key factors for reducing noise radiation and
achieving stable operation. Other lines, such as input and output terminals are DC current, therefore
pattern width (current capability) and DCR drop considerations are needed.
VIN
2.7V to 5.5V
Fosc = 2 MHz
i
i
L1
3.3 PH VOUT
PVIN
+ C1 E
- 10 PF
ENLDO
SW
EN
FB
ENLDO
VCON
LDO
PGND
C2
4.7 PF
SGND
+
-
LDOOUT
+
C
100 nF
C7
Figure 2. Current Loop
SNVA179B – August 2006 – Revised April 2013
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AN-1505 LM3207 Evaluation Board
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Board Layout Considerations
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Board Layout Flow
1. Minimize C1, PVIN, and PGND loop. These traces should be as wide and short as possible. This is
most important.
2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second
priority.
3. Above layout patterns should be placed on the component side of the PCB to minimize parasitic
inductance and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed
between C2(+) and C2(-) land patterns. If vias are used in these large current paths, multiple via-holes
should be used if possible.
4. Connect C1(-), C2(-) and PGND with wide GND pattern. This pattern should be short, so C1(-), C2(-),
and PGND should be as close as possible. Then connect to a PCB common GND pattern with as
many via-holes as possible.
5. SGND should not connect directly to PGND. Connecting these pins under the device should be
avoided. (If possible, connect SGND to the common port of C1(-), C2(-) and PGND.)
6. FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a
shield.
7. The LDO Cap C7 should be placed as close to the PA as possible and as far away from the switcher
to suppress high frequency switch noises.
NOTE: The evaluation board shown in Figure 3 and Figure 4 for the LM3207 was designed with the
considerations mentioned above, and it shows good performance. However some aspects
have not been optimized because of limitations due to evaluation-specific requirements. The
board can be used as a reference. For specific questions, please refer to Texas Instruments.
4
AN-1505 LM3207 Evaluation Board
SNVA179B – August 2006 – Revised April 2013
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Copyright © 2006–2013, Texas Instruments Incorporated
Evaluation Board Layout
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8
Evaluation Board Layout
3.3 PH
4.7 PF
10 PF
100 nF
Figure 3. Top Layer
Figure 4. Bottom Layer
SNVA179B – August 2006 – Revised April 2013
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AN-1505 LM3207 Evaluation Board
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