LM3280
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SNOSAU4B – OCTOBER 2006 – REVISED FEBRUARY 2013
LM3280 Adjustable Step-Down DC-DC Converter and 3 LDOs for RF Power Management
Check for Samples: LM3280
FEATURES
DESCRIPTION
•
•
The LM3280 is a multi-functional Power Management
Unit, optimized for low-power handheld applications
such as Cellular Phones.
1
2
•
•
•
•
•
•
•
•
•
2MHz (typ.) PWM Switching Frequency
Operates from a Single Li-Ion Cell (2.7V to
5.5V)
Adjustable Output Voltage (0.8V to 3.6V) DCDC
High-Efficiency Synchronous Buck Converter
300mA Maximum Load Capability (PWM Mode)
500mA Maximum Load Capability (Bypass
mode)
PWM, Forced and Automatic Bypass Mode
3 Low-Dropout and Fast Transient Response
LDOs
16-pin DSBGA Package
Current Overload Protection
Thermal Overload Protection
The LM3280 incorporates three low-dropout LDO
voltage regulators and one step down PWM DC-DC
converter with an internal Bypass FET. The step
down converter's output voltage can be set using an
analog input (VCON) for optimizing efficiency of the RF
PA at various power levels. The LDO operates a
nominal output voltage of 2.85V and maximum load
current capability of 20mA for a reference voltage
required by linear RF power amplifiers. The LM3280
additionally features a separate enable pin for each
output.
The LM3280 is available in a 16-pin lead free DSBGA
package.
APPLICATIONS
•
•
•
Cellular Phones
Hand-Held Radios
Battery Powered RF Devices
Typical Application
VIN :
2.7V to 5.5V
C3
1 éF
C1
10 éF
SVIN PVIN
VCON :
0.267V to 1.200V
L1
2.2 éH
BYPOUT
SW
VCON
C2
4.7 éF
FB
VOUT = 3 x VCON
BYP
DAC
ON/OFF
éPC
VOUT :
0.8V to 3.6V
ENBUCK
ON/OFF
ENLDO1
ON/OFF
ENLDO2
ON/OFF
ENLDO3
PA VCC
LM3280
LDO1
C5
1 éF
VLDO1 : 2.85V
VRE
F
VLDO2 :2.85V
LDO2
VRE
C6
1 éF
SGND
PGND
LDO3
C7
1 éF
PA
BAND1
PA
BAND2
F
VLDO3 : 2.85V
VRE
PA
BAND3
F
Figure 1. LM3280 Typical Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM3280
SNOSAU4B – OCTOBER 2006 – REVISED FEBRUARY 2013
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Connection Diagrams
A
LDO1
SVIN
SGND
BYPOUT
B
LDO2
FB
ENBUCK
PVIN
C
LDO3
ENLDO2
ENLDO1
SW
D
ENLDO3
VCON
BYP
PGND
1
2
3
4
Top View
Figure 2. 16–Bump DSBGA Package, Large Bump
See Package Number YZR0016QQA
Pin Descriptions
Pin #
Name
A1
LDO1
LDO1 Output.
Description
B1
LDO2
LDO2 Output.
C1
LDO3
LDO3 Output.
D1
ENLDO3
A2
SVIN
B2
FB
C2
ENLDO2
D2
VCON
Buck Converter Voltage Control Analog Input. This pin controls VOUT in PWM mode. Set: VOUT = 3 x VCON. Do
not leave floating.
A3
SGND
Analog, Signal, and LDO Ground.
B3
ENBUCK
Buck Converter Enable Input. Set this digital input high after Vin >2.7V for normal operation. For shutdown,
set low.
C3
ENLDO1
LDO1 Enable Input. Set this digital input high to turn on LDO1. (ENBUCK pin must be also set high.) For
turning LDO1 off, set low.
D3
BYP
A4
BYPOUT
B4
PVIN
C4
SW
D4
PGND
LDO3 Enable Input. Set this digital input high to turn on LDO3. (ENBUCK pin must be also set high.) For
turning LDO3 off, set low.
Analog, Signal, and LDO Supply Input.
Buck Converter Feedback Analog Input. Connect to the output at the output filter capacitor.
LDO2 Enable Input. Set this digital input high to turn on LDO2. (ENBUCK pin must be also set high.) For
turning LDO2 off, set low.
Forced Bypass Input. Use this digital input to command operation in Bypass mode. Set BYP low ( 0.94A)
25
µs
Time for VOUT to rise to 3.4V
in PWM Mode
VIN = 4.2V, COUT = 4.7µF,
RLOAD = 15Ω
L = 2.2µH (ISAT = 0.94A)
EN = Low to High
36
µs
CCON
VCON Input Capacitance
VIN = 3.6V, VCON = 1V,
Test Freq. = 100kHz
15
pF
TON_BYP
Bypass FET Turn On Time In
Bypass Mode
VIN = 3.6V, VCON = 0.267V,
COUT = 4.7µF, RLOAD = 15Ω
BYP = Low to High
30
µs
20
µs
TSTARTUP
(3)
TBYP
(1)
(2)
(3)
(4)
Auto Bypass Detect Delay
Time
(4)
10
15
All voltages are with respect to the potential at the GND pins.
Shutdown current includes leakage current of PFET and Bypass FET.
The startup time is the time to reach 90% of 3.4V nominal output voltage from the ENBUCK being low to high.
SVIN is compared to the programmed output voltage (VOUT). When SVIN – VOUT falls below VBYPASS− for longer than TBYP the Bypass
FET turns on and the switching FETs turn off. This is called the Bypass mode. The device comes out of Bypass mode when SVIN –
VOUT exceeds VBYPASS+ for longer than TBYP, and PWM mode returns. The hysteresis for the bypass detection threshold VBYPASS+ –
VBYPASS− will always be positive and will be approximately 200mV (typ.).
LDO1, 2, and 3 Electrical Characteristics (1) (2)
Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature
range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, specifications apply to the LM3280 with: VIN = 3.6V, ENBUCK =
3.6V, BYP = 0V, FB = 2V, VCON = 0.267V, ENLDOx = 3.6V (3).
Symbol
Parameter
Conditions
Min
Typ
VLDO
LDO Output Voltage
Accuracy
VLDO = 2.85V, IOUT = 1mA
ΔVLDO
Line Regulation
VIN = VLDO(nom) + 0.5V to 5.5V,
IOUT = 1mA
0.1
Load Regulation
IOUT = 1mA to 20mA
0.01
(1)
(2)
(3)
-1
-2
Max
Units
+1
+2
%
%
%/V
0.04
%/mA
All voltages are with respect to the potential at the GND pins.
Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the
most likely norm.
The ENLDOx means that the one of ENLDO1, ENLDO2, and ENLDO3 is set high (> 1.2V) and the others are set 0V.
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LDO1, 2, and 3 Electrical Characteristics(1)(2) (continued)
Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature
range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, specifications apply to the LM3280 with: VIN = 3.6V, ENBUCK =
3.6V, BYP = 0V, FB = 2V, VCON = 0.267V, ENLDOx = 3.6V (3).
Min
Typ
Max
Units
ILIM_LDO
Symbol
LDO Current Limit
(4)
30
40
55
mA
IPU
Pull-Up Current
(4)
40
60
80
mA
RPD
Pull-Down Resistance
IOUT = -50mA,
ENBUCK = all ENLDO = 0V
10
13.5
17
Ω
VDROP
Dropout Voltage
IOUT = 20mA
70
115
mV
(4)
(5)
Parameter
Conditions
(5)
The current is defined as the load current at which the LDOx voltage is 1.0V lower than the nominal output voltage.
Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below the
nominal voltage.
LDO1, 2, and 3 System Characteristics (1)
The following spec table entries are guaranteed by design if the component values in the typical application circuit are used.
Unless otherwise noted, specifications apply to the LM3280 with: VIN = 3.6V. These parameters are not guaranteed by
production testing.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PSRR
Power Supply Ripple Rejection
Ratio
Test Freq. = 1KHz, VRIPPLE = 0.5Vpp
COUT = 1µF, IOUT = 1mA, BYP = VIN
55
TLDO_ON
Time to reach 90% of VLDO(nom)
after ENLDO signal goes high.
VIN = ENBUCK = 3V,
COUT = 1µF,
ENLDOx = Low to High,
RLOAD = 270Ω
50
100
µs
VIN = 3V,
COUT = 1µF,
ENBUCK = ENLDOx = Low to High,
RLOAD = 270Ω
80
130
µs
VIN = 3V,
COUT = 1µF,
ENLDOx = High to Low,
IOUT = 0mA
50
200
µs
TLDO_OFF
(1)
6
Time to reach 0.1V of VLDO after
ENLDO signal goes low.
dB
All voltages are with respect to the potential at the GND pins.
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Typical Performance Characteristics
(VIN = ENBUCK = 3.6V, ENLDOx = BYP = 0V, TA = 25°C, unless otherwise noted)
Quiescent Current vs
Supply Voltage
(VCON = 0.267V, FB = 2V, No Switching, LDO Disabled)
Quiescent Current vs
Supply Voltage
(VCON = 0.267V, FB = 2V, No Switching, LDO Enabled)
1.00
TA = 85oC
0.80
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
0.84
TA = 85oC
0.76
0.72
0.68
TA = 25oC
0.64
0.96
0.92
0.88
TA = 25oC
0.84
0.80
TA = -30oC
0.60
2.5
3.0
3.5
4.0
TA = -30oC
4.5
5.0
5.5
0.76
2.5
6.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 3.
Figure 4.
Shutdown Current vs
Temperature
(all EN = BYPOUT = VCON = SW = FB = 0V)
LDO Line Transient Response
(RLOAD = 270Ω, COUT = 1µF)
1.0
SHUTDOWN CURRENT (PA)
3.6 V
VIN = 5.5V
0.9
VIN
0.8
3.0 V
VIN = 4.2V
0.7
0.6
VIN = 3.6V
0.5
0.4
0.3
10 mV/DIV
AC Coupled
LDO
0.2
0.1
0.0
-40 -20
VIN = 2.7V
0
20
40
60
20 Ps/DIV
80 100 120 140
JUNCTION TEMPERATURE (°C)
Figure 5.
Figure 6.
LDO Turn ON
(ENLDO = Low to High)
LDO Turn ON
(ENBUCK = ENLDO = Low to High)
5V/DIV
5V/DIV
500 mV/DIV
ENBUCK &
ENLDO
ENLDO
500 mV/DIV
500 mV/DIV
VOUT
VIN = 3.0V
VIN = 3.0V
COUT = 1 éF
LDO
RLOAD = 270:
COUT = 1 éF
LDO
RLOAD = 270:
20 Ps/DIV
20 Ps/DIV
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
(VIN = ENBUCK = 3.6V, ENLDOx = BYP = 0V, TA = 25°C, unless otherwise noted)
LDO Turn OFF
(ENLDO = High to Low)
LDO Load Transient Response
(COUT = 1µF)
ENLDO
5V/DIV
LDO
10 mV/DIV
AC Coupled
LDO
VIN = 3.0V
COUT = 1 éF
No Load
10 mA
IOUT
1 mA
500 mV/DIV
20 Ps/DIV
10 Ps/DIV
Figure 9.
Figure 10.
LDO Voltage
vs
Supply Voltage
LDO Voltage
vs
Temperature
2.865
2.865
IOUT = 1 mA
IOUT = 1 mA
2.860
2.860
2.855
2.855
LDO VOLTAGE (V)
LDO VOLTAGE (V)
IOUT = 10 mA
2.850
2.845
IOUT = 10 mA
2.840
2.850
2.845
2.840
IOUT = 20 mA
IOUT = 20 mA
2.835
2.830
2.5
2.835
3.0
3.5
4.0
4.5
5.0
5.5
2.830
-40
6.0
SUPPLY VOLTAGE (V)
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
Figure 12.
LDO Dropout Voltage
vs
Output Current
LDO Voltage vs
Output Current
(VIN = 3.6V)
3.5
o
TA = -30 C
3.0
TA = 25°C
20
LDO VOLTAGE (V)
LDO DROPOUT VOLTAGE (mV)
0
Figure 11.
0
40
60
TA = 25oC
2.5
2.0
TA = 85°C
1.5
1.0
TA = -30°C
80
0.5
TA = 85oC
100
0
4
8
12
16
20
OUTPUT CURRENT (mA)
0.0
0
10
20
30
40
50
60
OUTPUT CURRENT (V)
Figure 13.
8
-20
Figure 14.
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Typical Performance Characteristics (continued)
(VIN = ENBUCK = 3.6V, ENLDOx = BYP = 0V, TA = 25°C, unless otherwise noted)
PWM Startup
(VCON = 1.13V)
PWM Shutdown Response
(VCON = 1.08V)
VIN = 4.2V
500 mA/DIV
VOUT = 3.25V
VSW
IL
RLOAD = 15:
2V/DIV
1V/DIV
VIN = 4.2V
VOUT
VOUT
2V/DIV
VOUT = 3.4V
IL
RLOAD = 15:
200 mA/DIV
5V/DIV
VSW
5V/DIV
ENBUCK
EN
20 Ps/DIV
100 Ps/DIV
Figure 15.
Figure 16.
Automatic Bypass Operation
(VIN = 4.2V to 3.0V)
Forced Bypass Operation
(VIN = 3.0V)
VSW
VIN
5V/DIV
5V/DIV
VSW
2V/DIV
1V/DIV
VOUT
1V/DIV
VIN = 4.2V
VOUT
VCON = 0.5V
VIN = 3.0V
IL
IL
RLOAD = 15:
200 mA/DIV
200 mA/DIV
5V/DIV
BYP
RLOAD = 15:
VCON = 1.1V
100 Ps/DIV
100 Ps/DIV
Figure 17.
Figure 18.
Line Transient Response
(VIN = 3.0V to 3.6V)
Load Transient Response
(VCON = 0.5V)
VIN = 3.6V
3.6V
VIN
3.0V
VOUT = 1.5V
VOUT
100 mV/DIV
AC Coupled
VOUT = 1.5V
IOUT = 200 mA
VOUT
50 mV/DIV
AC Coupled
IL
IL
200 mA/DIV
IOUT
200 mA
250 mA
50 mA
40 Ps/DIV
20 Ps/DIV
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
(VIN = ENBUCK = 3.6V, ENLDOx = BYP = 0V, TA = 25°C, unless otherwise noted)
VCON Voltage Response
(VIN = 4.2V, VCON = 0.5V / 1.1V)
VSW
Timed Current Limit Response
(Normal Operation to Short Circuit)
VSW
2V/DIV
VOUT
1V/DIV
2V/DIV
3.25V
VOUT
VIN = 4.2V
1.5V
IL
RLOAD = 15:
500 mA/DIV
1.08V
0.5V
VCON
VOUT = 1.5V
100 Ps/DIV
10 Ps/DIV
Figure 21.
Figure 22.
Output Voltage Ripple
(VOUT = 1.5V)
Output Voltage Ripple in Dropout
(VIN = 3.75V, VOUT = 3.25V, IOUT = 200mA)
VSW
2V/DIV
VSW
2V/DIV
VOUT
10 mV/DIV
AC Coupled
VOUT
10 mV/DIV
AC Coupled
IL
200 mA/DIV
IL
200 mA/DIV
VIN = 3.57V
VIN = 3.6V
IOUT = 200 mA
VOUT = 1.5V
VOUT = 3.25V
Figure 23.
Figure 24.
Switching Frequency Variation
vs
Temperature (VOUT = 1.5V)
RDSON
vs
Temperature (Bypass FET)
120
2.0
1.5
IBYPOUT = 500 mA
VCON = 0.5V
IOUT = 200 mA
110
VIN = 4.2V
VIN = 3.6V
1.0
100
VIN = 3.6V
0.5
0.0
-0.5
VIN = 2.7V
90
80
70
-1.0
VIN = 2.7V
-20
0
20
40
VIN = 4.2V
60
-1.5
-2.0
-40
IOUT = 200 mA
400 ns/DIV
RDS(ON) (m:)
SWITCHING FREQUENCY VARIATION (%)
400 ns/DIV
60
80
100
50
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (oC)
AMBIENT TEMPERATURE (oC)
Figure 25.
10
RLOAD = 15:
Figure 26.
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Typical Performance Characteristics (continued)
(VIN = ENBUCK = 3.6V, ENLDOx = BYP = 0V, TA = 25°C, unless otherwise noted)
RDSON
vs
Temperature (P-FET)
RDSON
vs
Temperature (N-FET)
500
500
ISW = 500 mA
ISW = -200 mA
450
450
VIN = 2.7V
VIN = 3.6V
400
RDS(ON) (m:)
RDS(ON) (m:)
400
350
300
VIN = 2.7V
350
300
250
250
VIN = 4.2V
VIN = 4.2V
200
200
VIN = 3.6V
150
-40
-20
0
20
40
60
80
150
-40
100
AMBIENT TEMPERATURE ( C)
20
40
60
Figure 28.
PWM Output Voltage vs
Supply Voltage
(VOUT = 1.5V)
PWM Output Voltage vs
Temperature
(VOUT = 1.5V)
1.520
80
100
1.515
OUTPUT VOLTAGE (V)
1.515
IOUT = 300 mA
1.510
1.505
1.500
IOUT = 300 mA
1.510
IOUT = 100 mA
1.505
IOUT = 150 mA
1.495
1.500
1.495
IOUT = 50 mA
IOUT = 50 mA
1.490
2.5
0
Figure 27.
1.520
OUTPUT VOLTAGE (V)
-20
AMBIENT TEMPERATURE (oC)
o
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.490
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (oC)
SUPPLY VOLTAGE (V)
Figure 29.
Figure 30.
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Typical Performance Characteristics (continued)
(VIN = ENBUCK = 3.6V, ENLDOx = BYP = 0V, TA = 25°C, unless otherwise noted)
Open/Closed Loop Current Limit vs
Temperature
(PWM mode)
Dropout Voltage vs
Output Current
(Bypass mode, VIN = BYP = 3.6V)
860
0.0
VIN = 4.2V
CLOSED LOOP
VIN = 3.6V
DROPOUT VOLTAGE (V)
CURRENT LIMIT (mA)
840
VIN = 2.7V
820
800
VIN = 2.7V
VIN = 3.6V
780
VIN = 4.2V
760
-40
-20
0
20
40
0.2
TA = 85°C
0.4
TA = -30°C
0.6
TA = 25°C
0.8
Max Load
Capability
500 mA
OPEN LOOP
60
80
1.0
100
0
200
o
AMBIENT TEMPERATURE ( C)
4.0
800
1000
Figure 31.
Figure 32.
VCON Voltage vs
PWM Output Voltage
(IOUT = 200mA)
Low VCON Voltage vs
Output Voltage
(RLOAD = 15Ω)
1.4
OUTPUT VOLTAGE (V)
3.0
VIN = 3.0V
VIN = 2.7V
2.0
1200
1.6
VIN = 3.6V
VIN = 4.2V
OUTPUT VOLTAGE (V)
600
OUTPUT CURRENT (mA)
3.5
2.5
400
ILIM-BYP
= 965 mA
Bypass Mode
1.5
1.0
1.2
1.0
0.8
VIN = 5.5V
VIN = 5.0V
0.6
0.4
VIN = 4.7V
0.5
0.0
0.2
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VCON VOLTAGE (V)
0.1
0.2
0.3
0.4
0.5
VCON VOLTAGE (V)
Figure 33.
12
0.0
0.0
Figure 34.
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Typical Performance Characteristics (continued)
(VIN = ENBUCK = 3.6V, ENLDOx = BYP = 0V, TA = 25°C, unless otherwise noted)
Efficiency vs
Output Voltage
(VIN = 3.9V)
Efficiency vs
Output Current
(VOUT = 1.5V)
100
100
VIN = 2.7V
RLOAD = 15:
90
EFFICIENCY (%)
EFFICIENCY (%)
95
90
RLOAD = 10:
85
80
80
VIN = 4.2V
VIN = 3.6V
70
60
50
75
VIN = 3.9V
70
0.0
40
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
50
100
150
200
250
300
350
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
Figure 35.
Figure 36.
Efficiency vs
Output Current
(VOUT = 3.25V)
100
EFFICIENCY (%)
90
VIN = 3.6V
VIN = 3.9V
80
VIN = 4.2V
70
60
50
40
0
50
100
150
200
250
300
350
OUTPUT CURRENT (mA)
Figure 37.
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LM3280
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BLOCK DIAGRAM
SVIN
PVIN
BYPOUT
BYP
MAIN CONTROL
SHUTDOWN
CONTROL
ENBUCK
ERROR
AMPLIFIER
FB
ä
CURRENT
COMP
OSCILLATOR
SW
MOSFET
CONTROL
LOGIC
OVP COMP
VCON
VCON Low Voltage
DETECTOR
0.15V
PGND
SVIN
VREF
0.95V
-
Charge Control
+
LDOx
LDO Control
ENLDOx
Discharge Control
SGND
SGND
Figure 38. Functional Block Diagram
14
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DEVICE INFORMATION
The LM3280 a multi-functional Power Management Unit, optimized for low-power handheld applications such as
Cellular Phones. It incorporates one adjustable voltage PWM DC-DC converter with an internal Bypass FET and
three LDOs. It also provides a separate enable pin for each output. The buck converter output voltage can be
programmed from 0.8V to 3.6V in PWM mode. The buck converter is designed for a maximum load capability of
300mA in PWM mode and 500mA in Bypass mode. Maximum load range may vary from this depending on input
voltage, output voltage and the inductor chosen. The LDO operates a nominal output voltage of 2.85V and
maximum load current capability of 20mA.
The buck converter is designed to allow the RF PA (Power Amplifier) to operate at maximum efficiency over a
wide range of power levels from a single Li-Ion battery cell. It is based on current-mode buck architecture, with
synchronous rectification for high efficiency. It has three of pin-selectable operating modes. Fixed-frequency
PWM operation offers regulated output at high efficiency while minimizing interference with sensitive IF and data
acquisition circuits. Bypass mode (Forced or Automatic) turns on an internal FET bypass switch to power the PA
directly from the battery. This helps the RF PA maintain its operating power during low battery conditions by
reducing the dropout voltage across the buck converter. Shutdown mode turns the device off and reduces battery
consumption to 0.1µA (typ.).
DC PWM mode output voltage precision is +/-2% for 3.6VOUT. Efficiency is typically around 96% for a 120mA
load with 3.2V output, 3.6V input. PWM mode quiescent current is 0.72mA typ. The output voltage is dynamically
programmable from 0.8V to 3.6V by adjusting the voltage on the control pin (VCON) without the need for external
feedback resistors.
An LDO is used to provide a regulated 2.85V reference voltage supply to each RF PA. Since each LDO has its
own enable pin, it can be used to enable or disable its respective PA. The LDO can be enabled only after the
buck converter is activated. The LDO will automatically be disabled whenever the ENBUCK or ENLDOx is disabled.
Single LDO must be turned on at the same time. Each LDO provides an active charge circuit. The LDO output is
pulled to ground potential via an internal resistor when the ENBUCK or ENLDOx pin is low.
Additional features include current overload protection and thermal shutdown. The buck converter also provides
over voltage protection.
The LM3280 is constructed using a chip-scale 16-pin DSBGA package. This package offers the smallest
possible size, for space-critical applications such as cell phones, where board area is an important design
consideration. Use of a DSBGA package requires special design considerations for implementation. (See
DSBGA PACKAGE ASSEMBLY AND USE.) Its fine bump-pitch requires careful board design and precision
assembly equipment. Use of this package is best suited for opaque-case applications, where its edges are not
subject to high-intensity ambient red or infrared light. Also, the system controller should set ENBUCK low during
power-up and other low supply voltage conditions. (See Shutdown Mode.)
Buck Converter
CIRCUIT OPERATION
Referring to Figure 1 and Figure 38, the buck converter operates as follows. During the first part of each
switching cycle, the control block in the buck converter turns on the internal PFET (P-channel MOSFET) switch.
This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor
limits the current to a ramp with a slope of around (VIN - VOUT) / L, by storing energy in a magnetic field. During
the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and
then turns the NFET (N-channel MOSFET) synchronous rectifier on. In response, the inductor’s magnetic field
collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output
filter capacitor and load. As the stored energy is transferred back into the circuit and depleted, the inductor
current ramps down with a slope around VOUT / L. The output filter capacitor stores charge when the inductor
current is going high, and releases it when inductor current is going low, smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output
voltage is equal to the average voltage at the SW pin.
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PWM MODE
While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant
frequency (2MHz typ.) and then modulating the energy per cycle to control power to the load. Energy per cycle is
set by modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by
comparing the PFET drain current to a slope-compensated reference current generated by the error amplifier. At
the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to ramp up. When
the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch
and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the
output down, the error amplifier output increases, which allows the inductor current to ramp higher before the
comparator turns off the PFET. This increases the average current sent to the output and adjusts for the increase
in the load. The minimum on-time of PFET in PWM mode is 50ns (typ.).
BYPASS MODE
The buck converter contains an internal PFET switch for bypassing the PWM DC-DC converter during Bypass
mode. In Bypass mode, this PFET is turned on to power the PA directly from the battery for maximum RF output
power. Bypass mode is more efficient than operating in PWM mode at 100% duty cycle because the resistance
of the bypass PFET is less than the series resistance of the PWM PFET and inductor. This translates into higher
voltage available on the output in Bypass mode, for a given battery voltage. The part can be placed in bypass
mode by sending BYP pin high. This is called Forced Bypass Mode and it remains in bypass mode until BYP pin
goes low.
Alternatively the part can go into Bypass mode automatically. This is called Auto-bypass mode or Automatic
Bypass mode. The bypass switch turns on when the difference between the input voltage and programmed
output voltage is less than 250mV (typ.) for more than the bypass delay time of 15µs (typ.). The bypass switch
turns off when the input voltage is higher than the programmed output voltage by 450mV (typ.) for longer than
the bypass delay time. The bypass delay time is provided to prevent false triggering into Automatic Bypass mode
by either spikes or dips in VIN. This method is very system resource friendly in that the Bypass PFET is turned on
automatically when the input voltage gets close to the output voltage, typical scenario of a discharging battery. It
is also turned off automatically when the input voltage rises, typical scenario of a charger connected. Another
scenario could be changes made to VCON voltage causing Bypass PFET to turn on and off automatically. It is
recommended to connect BYPOUT pin directly to the output capacitor with a separate trace and not to the FB
pin.
OPERATING MODE SELECTION CONTROL
The BYP digital input pin is used to select between PWM/Auto-bypass and Bypass operating mode. Setting BYP
pin high (>1.2V) places the device in Forced Bypass mode. Setting BYP pin low (1.2V) after the buck converter has been enabled. The LDO will automatically be disabled whenever
the ENBUCK or ENLDOx is disabled. Only one LDO may be enabled on at a time. A 2µs period of time needs to
occur between disabled one LDO and enabling another. Otherwise, all LDOs are disabled.
CHARGE AND DISCHARGE
Each LDO includes an active charge circuit. 7.5us (typ.) after the LDO is enabled, the current limit of the LDO is
set to 60mA. A 1µF load capacitor will be charged to 90% of the nominal output voltage in approximately 50us
(typ.). (Note: This number is based on the assumption that the PWM loop has been enabled and given time to
stabilize before the LDO is enabled.) The current limit is then reduced to 40mA.
An internal pull-down resistor is also included in each LDO. The LDO discharges the output capacitor through the
pull-down resistor when LDO is disabled.
Shutdown Mode
Setting the ENBUCK digital pin low (1.2V) enables normal operation.
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ENBUCK should be set low to turn off the LM3280 during power-up and under voltage conditions when the power
supply is less than the 2.7V minimum operating voltage. The LM3280 is designed for compact portable
applications, such as cellular phones. In such applications, the system controller determines power supply
sequencing and requirements for small package size outweigh the benefit of including UVLO (Under Voltage
Lock-Out) circuitry.
Thermal Overload Protection
The LM3280 has a thermal overload protection function to protect the device from short-term misuse and
overload conditions. When the junction temperature exceeds around 150°C, the device inhibits operation. Both
the PFET and the NFET are turned off in PWM mode, and the Bypass PFET is turned off in Bypass mode. The
LDO is also turned off. When the temperature drops below 125°C, normal operation resumes. Prolonged
operation in thermal overload conditions may damage the device.
APPLICATION INFORMATION
BUCK CONVERTER SETTING THE OUTPUT VOLTAGE
The buck converter features a pin-controlled variable output voltage to eliminate the need for external feedback
resistors. It can be programmed for an output voltage from 0.8V to 3.6V by setting the voltage on the VCON pin,
as in the following formula:
VOUT = 3 x VCON
(1)
When VCON is between 0.267V and 1.20V, the output voltage will follow proportionally by 3 times of VCON.
If VCON is over 1.20V (VOUT = 3.6V), sub-harmonic oscillation may occur because of insufficient slope
compensation.
If VCON voltage is less than 0.267V (VOUT = 0.8V), the output voltage may not be regulated due to the required
on-time being less than the minimum on-time (50ns). The output voltage can go lower than 0.8V providing a
limited VIN range is used. Refer to the Typical Performance Characteristics (Low VCON Voltage vs. Output
Voltage) for details. This curve is for a typical part and there could be part to part variation for output voltages
less than 0.8V over the limited VIN range. In addition, if the VCON is less than approximately 0.15V, the PWM
mode output is turned off, but the internal bias circuits are still active.
INDUCTOR SELECTION
A 2.2μH inductor with saturation current rating over 940mA is recommended for almost all applications. The
inductor resistance should be less than 0.2Ω for better efficiency. Table 1 lists suggested inductors and
suppliers.
Table 1. Suggested Inductors and Their Suppliers
18
Model
Size (WxLxH) [mm]
Vendor
DO3314-222MX
3.3 x 3.3 x 1.4
Coilcraft
LPS3010-222MLC
3.1 x 3.1 x 1.0
Coilcraft
LPS3008-222MLC
3.1 x 3.1 x 0.8
Coilcraft
MIPSA2520D2R2**
2.5 x 2.0 x 1.2
FDK
KSLI252010AG2R2*
2.5 x 2.0 x 1.0
Hitachi-Metal
VLF3010AT-2R2M1R0
2.6 x 2.8 x 1.0
TDK
NR3010T2R2M
3.0 x 3.0 x 1.0
Taiyo-Yuden
NR3012T2R2M
3.0 x 3.0 x 1.2
Taiyo-Yuden
1117AS-2R2M(DE2810C)
2.8 x 3.0 x 1.0
Toko
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If a higher value inductor is used the LM3280 may become unstable and exhibit large under or over shoot during
line, load and VCON transients. If smaller inductance value is used, slope compensation maybe insufficient
causing sub-harmonic oscillations. The device has been tested with inductor values in the range 1.55μH to 3.1μH
to account for inductor tolerances.
For low-cost applications, an un-shielded bobbin inductor can be used. For noise-critical applications, an unshielded or shielded-bobbin inductor should be used. A good practice is to layout the board with footprints
accommodating both types for design flexibility. This allows substitution of an un-shielded inductor, in the event
that noise from low-cost bobbin models is unacceptable. Saturation occurs when the magnetic flux density from
current through the windings of the inductor exceeds what the inductor’s core material can support with a
corresponding magnetic field. This can cause poor efficiency, regulation errors or stress to a DC-DC converter
like the LM3280.
CAPACITOR SELECTION
The LM3280 is designed to be used with ceramic capacitors. Use a 10µF ceramic capacitor for the power input,
a 4.7µF ceramic capacitor for the buck converter output, and a 1µF ceramic capacitor for the LDO and the signal
input. Ceramic capacitors such as X5R, X7R and B are recommended for both filters. These provide an optimal
balance between small size, cost, reliability and performance for cell phones and similar applications. Table 2
lists suggested capacitors and suppliers.
Table 2. Suggested Capacitors and Their Suppliers
Model
Size (EIA)
Vendor
C1608X5R0J475M
1608 (0603)
TDK
C2012X5R0J106M
2012 (0805)
TDK
GRM188B10J105KA01
1608 (0603)
Murata
LMK107BJ105KA
1608 (0603)
Taiyo-Yuden
C1608JB1C105K
1608 (0603)
TDK
The DC bias characteristics of the capacitor must be considered when making the selection. If smaller case size
such as 1608 (0603) is selected, the DC bias could reduce the cap value by as much as 40%, in addition to the
20% tolerances and 15% temperature coefficients. Request DC bias curves from manufacturer when making
selection. The buck converter has been designed to be stable with output capacitors as low as 3μF to account
for capacitor tolerances. The LDO has been done with output capacitors as low as 0.5µF. These values include
DC bias reduction, manufacturing tolerances and temp coefficients.
The input filter capacitor supplies AC current drawn by the PFET switch of the LM3280 in the first part of each
cycle and reduces the voltage ripple imposed on the input power source. A 1µF capacitor is also recommended
close to SVIN pin. The output filter capacitor absorbs the AC inductor current, helps maintain a steady output
voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with
sufficient capacitance and sufficiently low ESR (Equivalent Series Resistance) to perform these functions. The
ESR of the filter capacitors is generally a major factor in voltage ripple.
DSBGA PACKAGE ASSEMBLY AND USE
Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow
techniques, as detailed in National Semiconductor Application Note 1112. Refer to the section, Surface Mount
Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board
should be used to facilitate placement of the device. The pad style used with DSBGA package must be the
NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size.
This prevents a lip that otherwise forms if the solder-mask and pad overlap, from holding the device off the
surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do
this. The 16-Bump package used for the LM3280 has 300 micron solder balls and requires 10.82 mil pads for
mounting on the circuit board. The trace to each pad should enter the pad with a 90° entry angle to prevent
debris from being caught in deep corners. Initially, the trace to each pad should be 6-7 mil wide, for a section
approximately 6 mil long or longer, as a thermal relief. Then each trace should neck up or down to its optimal
width. The important criterion is symmetry. This ensures the solder bumps on the LM3280 re-flow evenly and that
the device solders level to the board. In particular, special attention must be paid to the pads for bumps B4, C4
and D4. Because PVIN and PGND are typically connected to large copper planes, inadequate thermal relief can
result in inadequate re-flow of these bumps.
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The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque
cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is
vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed
circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, Thin Micro
DSBGA devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges.
Do not use or power-up the LM3280 while subjecting it to high intensity red or infrared light; otherwise degraded,
unpredictable or erratic operation may result. Examples of light sources with high red or infrared content include
the sun and halogen lamps. Place the device in a case opaque to red or infrared light.
BOARD LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter, resulting in poor regulation or
instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA
package and board pads. Poor solder joints can result in erratic or degraded performance. Good layout for the
LM3280 can by implemented by following a few simple design rules.
1. Place the LM3280 on 10.82 mil pads. As a thermal relief, connect to each pad with a 7 mil wide,
approximately 7 mil long traces, and when incrementally increase each trace to its optimal width. The
important criterion is symmetry to ensure the solder bumps on the LM3280 re-flow evenly (see DSBGA
PACKAGE ASSEMBLY AND USE).
2. Place the LM3280, inductor and filter capacitors close together and make the trace short. The traces
between these components carry relatively high switching currents and act as antennas. Following this rule
reduces radiated noise. Place the capacitors and inductor close to the LM3280. The input capacitor should
be placed right next to the device between PVIN and PGND pin.
3. Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor, through the LM3280 and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground, through the LM3280 by the inductor, to the output filter capacitor and then back through
ground, forming a second current loop. Routing these loops so the current curls in the same direction,
prevents magnetic field reversal between the two half-cycles and reduces radiated noise.
4. Connect the ground pins of the LM3280, and filter capacitors together using generous component side
copper fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several
vias. This reduces ground plane noise by preventing the switching currents from circulating through the
ground plane. It also reduces ground bounce at the LM3280 by giving it a low impedance ground connection.
5. Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces.
6. Route noise sensitive traces, such as the voltage feedback trace, away from noisy traces and components.
The voltage feedback trace must remain close to the LM3280 circuit and should be routed directly from FB
pin to VOUT at the output capacitor. A good approach is to route the feedback trace on another layer and to
have a ground plane between the top layer and the layer on which the feedback trace is routed. This reduces
EMI radiation on to the DC-DC converter’s own voltage feedback trace.
7. It is recommended to connect BYPOUT pin to VOUT at the output capacitor using a separate trace, instead of
connecting it directly to the FB pin for better noise immunity.
20
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REVISION HISTORY
Changes from Revision A (February 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM3280TL-275/NOPB
ACTIVE
DSBGA
YZR
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-30 to 85
V002
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
