LM3370SD-3021EV

User's Guide SNVA140D – April 2006 – Revised April 2013 AN-1428 LM3370 Evaluation Board 1 Introduction The LM3370 evaluation board is a working demonstration of a DUAL step down DC-DC converter. This application note contains information about the evaluation board. For more details and electrical characteristic on the dual buck converter operation, see the LM3370 Dual Synchronous Step-Down DCDC Converter with Dynamic Voltage Scaling Function Data Sheet (SNVS406). 2 General Description The LM3370 is a dual step-down DC-DC converter optimized for powering ultra-low voltage circuits from a single Li-Ion cell or 3 cell NiMH/NiCd batteries. Automatic intelligent switching between PWM low-noise and PFM low current mode offers improved system efficiency. The I2C compatible offers dynamic controls of the output voltages, Auto PFM/PWM mode selection and other enabling enchantment features such as power-on-reset (nPOR) and spread spectrum. 3 Operating Conditions • • • • • • VIN range: 2.7V ≤ VIN ≤ 5.5V Recommended load current: 0 to 600mA I2C Compatible Interface VOUT1 (1V to 2V at 50mV step increment) VOUT2 (1.8V to 3.3V at 100mV steps increment). Package TLA20CWA micro SMD, (3.0mm x 2.0mm x 0.6mm) LLP16 non-pullback, (4mm x 5mm x 0.8mm) All trademarks are the property of their respective owners. SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback AN-1428 LM3370 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 1 Typical Application 4 www.ti.com Typical Application CIN1 4.7 PF FB1 VIN1 SDA SW1 SCL PGND1 VIN1 nPOR1 VIN2 nPOR2 2.7V to 5.5V VOUT1 L1:2.2 PH COUT1 10 PF SGND LM3370 VDD VIN1 4.7 PF EN1 PGND2 EN2 SW2 FB2 VIN2 L2:2.2 PH * VOUT2 COUT2 2.7V to 5.5V CIN2 10 PF 4.7 PF * Optional Capacitor Figure 1. Typical Application Circuit 5 Operating Information The LM3370SD evaluation board is pre-programmed to 1.2V at VOUT1 and 3.3V at VOUT2 for evaluation purpose (no additional interface hardware is needed). If different default output option is desired, the same evaluation board can be used to demount the existing device and replace with a new voltage option (voltage option can be ordered from TI's website at www.ti.com). The device comes with the following default setting: Auto PFM and PWM transition mode when the I2C compatible interface is not enabled. For other settings, I2C compatible interface must be used to enable all other functions. Registers information are listed on page 4 for I2C compatible interface. 6 Powering Up the Evaluation Board • • • • 7 Apply a voltage at the "Vin_EXT" pin only (not Vin_IO). All logic pins are tied to "Vin” on the evaluation board Do not power the “Vin_IO” pin unless powering the logic pins via an external source. (Jumper at Vin_IO must be removed.) VDD pin is tied to VIN1 & VIN2 on the evaluation board, no additional connection required. (For any reason if VDD is not directly tied to VIN, VDD needs to be equal or greater than the two inputs (VIN1 or VIN2) for proper operation.) I2C Interface Ready If interface capability is available via I2C compatible, the SDA & SCL test pins of the evaluation board are brought out for such function. The SDA & SCL pins of the evaluation board are connected to 2 kΩ resistors and pulled up to VIN pin. 2 AN-1428 LM3370 Evaluation Board SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Package Marking Information www.ti.com 8 Package Marking Information VIN2 1 16 FB2 SW2 2 15 EN2 PGND2 3 14 EN1 VDD 4 13 nPOR2 SGND 5 12 nPOR1 PGND1 6 11 SCL SW1 7 10 SDA VIN1 8 9 FB1 Figure 2. Top View 9 Pin Descriptions (WSON) Table 1. Pin Descriptions (WSON) 1 VIN2 Power supply voltage input to PFET and NFET switches for Buck2 2 SW2 Buck 2 Switch pin 3 PGND2 4 VDD Buck 2 Power Ground Signal supply voltage input, VDD must be equal or greater of the two inputs (VIN1 or VIN2) 5 SGND Signal GND 6 PGND1 Buck 1 Power Ground 7 SW1 Buck 1 Switch pin 8 VIN1 Power supply voltage input to PFET and NFET switches for Buck1 9 FB1 Analog feedback input for Buck 1 10 SDA I2C Compatible Data, a 2 kΩ pull up resistor is required 11 SCL I2C Compatible Data, a 2 kΩ pull up resistor is required 12 nPOR1 Power ON Reset for Buck 1, Open drain output low when Buck 2 output is 92% of target output. A 100 kΩ pull up resistor is required 13 nPOR2 Power ON Reset for Buck 2, Open drain output low when Buck 2 output is 92% of target output. A 100 kΩ pull up resistor is required 14 EN1 Buck 1 Enable 15 EN2 Buck 2 Enable 16 FB2 Analog feedback input for Buck 2 SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback AN-1428 LM3370 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 3 Package Marking Information (DSBGA) 10 www.ti.com Package Marking Information (DSBGA) Figure 3. Top View 11 Figure 4. Bottom View Pin Descriptions (DSBGA) Table 2. Pin Descriptions (DSBGA) 4 Pin No Name Description A1 SW1 Buck 1 Switch Pin A2 VIN1 Power supply voltage input to PFET and NFET switches for Buck 1 A3 SGND Signal GND A4 FB1 B1 PGND1 Analog Feedback Input for Buck 1 B2 PGND1_S B3 SDA I2C Compatible Data, a 2 kΩ pull up resistor is required B4 SCL I2C Compatible Clock, a 2 kΩ pull up resistor is required C1 VDD Signal supply voltage input, VDD must be equal or greater of the two inputs (VIN1 & VIN2) C2 SGND Signal GND C3 nPOR1 Power ON Reset for Buck 1, Open drain output Low when Buck 1 output is 92% of target output. A 100 kΩ pull up resistor is required C4 nPOR2 Power ON Reset for Buck 2, Open drain output Low when Buck 2 output is 92% of target output. A 100 kΩ pull up resistor is required D1 PGND2 Buck 2 Power Ground D2 PGND2_S D3 EN2 Buck 2 Enable D4 EN1 Buck 1 Enable E1 SW2 Buck 2 Switch Pin E2 VIN2 Power supply voltage input to PFET and NFET switches for Buck 2 E3 SGND E4 FB2 Buck 1 Power Ground Buck 1 Power Ground Sense Buck 2 Power Ground Sense Signal GND Analog feedback for Buck 2 AN-1428 LM3370 Evaluation Board SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Pin Descriptions (DSBGA) www.ti.com 2 Table 3. Output Selection Table via I C Programing Buck Output Voltage Selection Codes (1) Data Code Buck_1 (V) Buck_2 (V) 00000 NA NA 00001 NA 1.8 00010 NA 1.85 or 1.9 (1) 00011 NA 2.0 00100 NA 2.1 00101 1.00 2.2 00110 1.05 2.3 00111 1.10 2.4 01000 1.15 2.5 01001 1.20 2.6 01010 1.25 2.7 01011 1.30 2.8 01100 1.35 2.9 01101 1.40 3.0 01110 1.45 3.1 01111 1.50 3.2 10000 1.55 3.3 10001 1.60 NA 10010 1.65 NA 10011 1.70 NA 10100 1.75 NA 10101 1.80 NA 10110 1.85 NA 10111 1.90 NA 11000 1.95 NA 11001 2.00 NA Can be trimmed at the factory at 1.85V or 1.9V using the same trim code. SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback AN-1428 LM3370 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 5 Registers Information 12 www.ti.com Registers Information MSB LSB ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 1 0 0 0 0 1 2 I C SLAVE address (chip address) Figure 5. Device Address MSB LSB 7 6 5 4 3 2 1 0 EN1 for Buck 1 (default = 1) Bit0 = 1 to enable EN2 for Buck 2 (default = 1) Bit1 = 1 to enable Spread Spectrum (SS) Enable Bit2 = 1 to enable SS_fmod (SS Frequency Modulator) ss_fmod = 1 1 kHz (default) ss_fmod = 0 2 kHz Pstep Enable for Buck1 Pstep = 0 (default) not enable Pstep = 1 50 mV/step at 32 Ps/step Pstep Enable for Buck2 Pstep = 0 (default) not enable Pstep = 1 100 mV/step at 32 Ps/step Bit 6 & 7 are not used Figure 6. Register 00 MSB 7 LSB 6 5 4 3 2 1 0 Vout for Buck 1 00101 = 1V (Min.) 11111 = 2V (Max.) Forced PWM Mode (FPWM1) Auto = 0 (default) FPWM1 = 1 (PWM mode only) Bit 6 and 7 are not used Figure 7. Register 01 6 AN-1428 LM3370 Evaluation Board SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Evaluation Board Layout (WSON) www.ti.com MSB 7 LSB 6 5 4 3 2 1 0 Vout for Buck 2 00001= 1.8V (Min.) 11111 = 3.3V (Max.) Forced PWM Mode (FPWM2) Auto = 0 (default) FPWM2 = 1 (PWM mode only) Disable Por function (DISPOR) DISPOR = 0 enable Por (default) DISPOR = 1 disable Por Bit 7 is not used Figure 8. Register 02 13 Evaluation Board Layout (WSON) LM3370SD is a 4-layer board designed to maximize the performance fo the device. Figure 9. Silk Screen SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback AN-1428 LM3370 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 7 Evaluation Board Layout (WSON) www.ti.com Figure 10. Top Layer Figure 11. Mid Layer 1 8 AN-1428 LM3370 Evaluation Board SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Evaluation Board Layout (WSON) www.ti.com Figure 12. Mid Layer 2 Figure 13. Bottom Layer SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback AN-1428 LM3370 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 9 Evaluation Board Layout (DSBGA) 14 www.ti.com Evaluation Board Layout (DSBGA) The LM3370TL applications is of similar layout to the LLP board with the exception of the SCL, SDA pins. When using the USB interface cable the order of these pins is reversed. Figure 14. Silk Screen Figure 15. Top Layer 10 AN-1428 LM3370 Evaluation Board SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Evaluation Board Layout (DSBGA) www.ti.com Figure 16. Mid Layer 1 Figure 17. Bottom Layer SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback AN-1428 LM3370 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 11 Bill of Materials (BOM) 15 www.ti.com Bill of Materials (BOM) Component Name Manufacture Manufacture No Specification TDK C2012X5R0J475K 4.7µF/6.3V/0805/X5R muRata GRM219R60J475KE19D TDK C2012X5R0J106K LM3370 CIN1 and CIN2 COUT1 and COUT2 10µF/6.3V/0805/X5R muRata GRM219R60J106KE19D L1 & L2 Taiyo-Yuden NR3015T-2R2M R1-2(SDA+SCL) Vishay 2k Ωs R3-4 (nPOR1-2) Vishay 100k Ωs 2.2µH TEST Pins and Connectors VOUT1,VOUT2, GND, *Vin_EXT, Vin_IO Turret 0.09 in nPOR1. nPOR2, SDA, SCL, PGND1, PGND2, VIN1, VIN2, Turret 0.072 in Jumper SDA/SCL/nPOR1 Jumpers Female(Handle centerline) A26242-ND nPOR2/EN1/EN2 *VIN & *VIN_IO *VIN_IO 2 in series (2x1) *VIN_EXT 2 in series (2x1) Int Berk stick Header 4 in series (4x1) JP2:SDA & SCL 6 in series(6x2) nPOR1/ nPOR2/EN1& EN2 2 in series 2(2x1) 12 AN-1428 LM3370 Evaluation Board SNVA140D – April 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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