LM3370
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SNVS406N – NOVEMBER 2005 – REVISED MAY 2013
LM3370 Dual Synchronous Step-Down DC-DC Converter
with Dynamic Voltage Scaling Function
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FEATURES
APPLICATIONS
1
•
2
•
•
•
•
•
•
•
•
•
•
•
2
I C-compatible interface
– VOUT1 = 1V to 2V in 50 mV Steps
– VOUT2 = 1.8V to 3.3V in 100 mV Steps
– Automatic PFM/PWM Mode Switching and
Forced PWM Mode for Low Noise Operation
– Spread Spectrum Capability Using I2C
600mA Load Per Channel
2MHz PWM Fixed Switching Frequency (Typ.)
The Bucks Operate 180° Out-of-Phase Timing
Offset for Noise and Input Surge Current
Abatement
Internal Synchronous Rectification for High
Efficiency
Internal Soft Start
Power-on-Reset Function for Both Outputs
2.7V ≤ VIN ≤ 5.5V
Operates from a Single Li-Ion Cell or 3 Cell
NiMH/NiCd Batteries and 3.3V/5.5V Fixed Rails
2.2µH Inductor, 4.7µF Input and 10µF Output
Capacitor Per Channel
16-lead WSON Package (4 mm x 5 mm x 0.8
mm)
20-Bump DSBGA Package (3.0 mm x 2.0 mm x
0.6 mm)
•
•
•
•
Baseband Processors
Application Processors (Video, Audio)
I/O Power
FPGA Power and CPLD
DESCRIPTION
The LM3370 is a dual step-down DC-DC converter
optimized for powering ultra-low voltage circuits from
a single Li-Ion battery and input rail ranging from 2.7V
to 5.5V. It provides two outputs with 600mA load per
channel. The output voltage range varies from 1V to
3.3V and can be dynamically controlled using the I2Ccompatible interface. This dynamic voltage scaling
function allows processors to achieve maximum
performance at the lowest power level. The I2Ccompatible interface can also be used to control auto
PFM-PWM/PWM mode selection and other
performance enhancing features.
The LM3370 offers superior features and
performance for portable systems with complex
power
management
requirements.
Automatic
intelligent switching between PWM low-noise and
PFM low-current mode offers improved system
efficiency.
Internal
synchronous
rectification
enhances the converter efficiency without the use of
further external devices.
Typical Application Circuit
CIN1
4.7 PF
FB1
VIN1
SDA
SW1
SCL
PGND1
VIN1
nPOR1
VIN2
nPOR2
2.7V to 5.5V
VOUT1
L1:2.2 PH
10 PF
SGND
LM3370
COUT1
VDD
* 4.7 PF
EN1
PGND2
EN2
SW2
FB2
VIN2 L2:2.2 PH
VIN1
VOUT2
2.7V to 5.5V
CIN2
COUT2
10 PF
4.7 PF
* Optional Capacitor
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM3370
SNVS406N – NOVEMBER 2005 – REVISED MAY 2013
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DESCRIPTION (CONTINUED)
There is a power-on-reset function that monitors the level of the output voltage to avoid unexpected power
losses. The independent enable pin for each output allows for simple and effective power sequencing.
LM3370 is available in a 4mm by 5mm 16-lead non-pullback WSON and a 20-bump DSBGA, 3.0mm x 2.0mm x
0.6mm, package. A high switching frequency—2 MHz (typ)—allows use of tiny surface-mount components
including a 2.2µH inductor.
Default fixed voltages for the 2 output voltages combination can be customized to fit system requirements by
contacting Texas Instruments.
Functional Block Diagram
FB1
FB1
SDA
buck1 control
2
I C
Registers
EPROM
SCL
OR2
EN_I2C
VIN1
SW
SW1
EN1
SDA
SCL
VIN1
Buck1
buck2 control
POR1
PGND
PGND1
EN_bk1
EN_bk2
SGND
nPOR1
U1
VDD
1
nPOR2
2
U2
AND
EN1
EN2
POR2
PGND
Buck2
AND
PGND2
SW2
SW2
VIN2
VIN2
EN2
FB2
FB2
Typical Performance Curve
2
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VIN2
1
16
FB2
SW2
2
15
EN2
PGND2
3
14
EN1
VDD
4
13
nPOR2
SGND
5
12
nPOR1
PGND1
6
11
SCL
SW1
7
10
SDA
VIN1
8
9
FB1
Figure 1. WSON Connection Diagram
(See Package Number NHR0016B)
PIN DESCRIPTIONS (WSON)
Pin #
Name
1
VIN2
Power supply voltage input to PFET and NFET switches for Buck 2
Description
2
SW2
Buck 2 Switch Pin
3
PGND2
4
VDD
5
SGND
Signal GND
6
PGND1
Buck 1 Power Ground
7
SW1
Buck 1 Switch Pin
8
VIN1
Power supply voltage input to PFET and NFET switches for Buck 1
9
FB1
Analog Feedback Input for Buck 1
10
SDA
I2C-Compatible Data, a 2 kΩ pull up resistor is required
11
SCL
I2C-Compatible Clock, a 2 kΩ pull up resistor is required
12
nPOR1
Power ON Reset for Buck 1, Open drain output Low when Buck 1 output is 92% of target
output. A 100 kΩ pull up resistor is required
13
nPOR2
Power ON Reset for Buck 2, Open drain output Low when Buck 2 output is 92% of target
output. A 100 kΩ pull up resistor is required
14
EN1
Buck 1 Enable
15
EN2
Buck 2 Enable
16
FB2
Analog feedback for Buck 2
Buck 2 Power Ground
Signal supply voltage input, VDD must be equal or greater of the two inputs (VIN1 and VIN2)
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LM3370
SNVS406N – NOVEMBER 2005 – REVISED MAY 2013
A
B
C
1
2
3
4
4
3
2
1
SW1
VIN1
SGND
FB1
FB1
SGND
VIN1
SW1
A1
A2
A3
A4
A4
A3
A2
A1
PGND1
PGND1_S
SDA
SCL
SCL
SDA
PGND1_S
PGND1
B2
B3
B4
B4
B3
B2
VDD
SGND
NPOR1
NPOR2
NPOR2
NPOR1
SGND
VDD
C1
C2
C3
C4
C4
C3
C2
C1
EN2
EN1
EN1
EN2
B1
PGND2 PGND2_S
D
E
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B1
A
B
C
PGND2_S PGND2
D1
D2
D3
D4
D4
D3
D2
D1
SW2
VIN2
SGND
FB2
FB2
SGND
VIN2
SW2
E1
E2
E3
E4
E4
E3
E2
E1
D
E
Bottom View
Top View
Figure 2. DSBGA Connection Diagram
(See Package Number YZR0020DWA)
PIN DESCRIPTIONS (DSBGA)
4
Pin #
Name
Description
A1
SW1
Buck 1 Switch Pin
A2
VIN1
Power supply voltage input to PFET and NFET switches for Buck 1
A3
SGND
A4
FB1
Signal GND
Analog Feedback Input for Buck 1
B1
PGND1
B2
PGND1_S
Buck 1 Power Ground
B3
SDA
I2C-Compatible Data, a 2 kΩ pullup resistor is required
B4
SCL
I2C-Compatible Clock, a 2 kΩ pullup resistor is required
C1
VDD
Signal supply voltage input, VDD must be equal or greater of the two inputs ( VIN1 and VIN2)
C2
SGND
Signal GND
C3
nPOR1
Power ON Reset for Buck 1, Open drain output Low when Buck 1 output is 92% of target output.
A 100 kΩ pullup resistor is required
C4
nPOR2
Power ON Reset for Buck 2, Open drain output Low when Buck 2 output is 92% of target output.
A 100 kΩ pullup resistor is required
D1
PGND2
Buck 2 Power Ground
D2
PGND2_S
D3
EN2
Buck 2 Enable
D4
EN1
Buck 1 Enable
E1
SW2
Buck 2 Switch Pin
E2
VIN2
Power supply voltage input to PFET and NFET switches for Buck 2
E3
SGND
E4
FB2
Buck 1 Power Ground Sense
Buck 2 Power Ground Sense
Signal GND
Analog feedback for Buck 2
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I2C Controlled Features
Features
Parameter
Comments
Output Voltage
VOUT1 and VOUT2
Output voltage is controlled via I2Ccompatible
Modes
Buck 1 and Buck 2
Mode can be controlled via I2C
compatible by either forcing device
in Auto mode or forced PWM mode
Spread Spectrum
Buck 1 and Buck 2
Spread Spectrum capability via I2Ccompatible for noise reduction
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1) (2)
Ordering Information
Voltage Option (V)
LM3370 (WSON)
LM3370SD-3013
1.2 and 2.5
LM3370SDX-3013
LM3370SD-3021
1.2 and 3.3
LM3370SDX-3021
LM3370SD-3416
1.4 and 2.8
LM3370SDX-3416
LM3370SD-3621
1.5 and 3.3
LM3370SDX-3621
LM3370SD-3806
1.6 and 1.8
LM3370SDX-3806
LM3370SD-4221
1.8 and 3.3
LM3370SDX-4221
LM3370 (DSBGA)
LM3370TL-2613/NOPB
LM3370TLX-2613/NOPB
LM3370TL-3607/NOPB
LM3370TLX-3607/NOPB
LM3370TL-3008/NOPB
LM3370TLX-3008/NOPB
LM3370TL-3006/NOPB
LM3370TLX-3006/NOPB
LM3370TL-3806/NOPB
LM3370TLX-3806/NOPB
LM3370TL-3206/NOPB
LM3370TLX-3206/NOPB
LM3370TL-3022/NOPB
LM3370TLX-3022/NOPB
(1)
(2)
1.0 and 2.5
1.5 and 1.9
1.2 and 2.0
1.2 and 1.8
1.6 and 1.8
1.3 and 1.8
1.2 and 1.85
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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Absolute Maximum Ratings (1) (2) (3)
−0.2V to 6V
VIN1 , VIN2 VDD to PGND and SGND
−0.2V to +0.2V
PGND to SGND
SDA, SCL, EN, EN2, nPOR1, nPOR2, SW1, SW2, FB1 and FB2
Maximum Continuous Power
Dissipation (PD_MAX) (4)
(GND - 0.2) to (VIN + 0.2V)
Internally Limited
Junction Temperature (TJ-MAX)
125°C
Storage Temperature Range
−65°C to +150°C
Maximum Lead Temperature
(Soldering)
(5)
ESD Ratings
(1)
(2)
(3)
(4)
(5)
(6)
(6)
All Pins
2 kV HBM
200V MM
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and
associated test conditions, see Electrical Characteristics.
All voltages are with respect to the potential at the GND pin.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. The thermal shutdown engages at TJ = 150°C (typ.)
and disengages at TJ = 140°C(typ.).
For detailed soldering specifications and information, please refer to Texas Instruments Application Note 1187: Leadless Leadframe
Package (LLP) (SNOA401).
The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine
model is a 200 pF capacitor discharged directly into each pin. (EAIJ)
Operating Ratings (1) (2)
Input Voltage Range ( (3))
2.7V to 5.5V
Recommended Load Current Per Channel
0 mA to 600 mA
−30°C to +125°C
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
(1)
(2)
(3)
(4)
6
(4)
−30°C to +85°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and
associated test conditions, see Electrical Characteristics.
All voltages are with respect to the potential at the GND pin.
Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages: VIN = 2.7V
to 5.5V for 1V ≤ VOUT ≤ 1.7V and for VOUT = 1.8V or greater, VIN = VOUT + 1VorVIN,MIN = ILOAD * (RDSON_PFET + RDCR_INDUCTOR) + VOUT
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125ºC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
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Thermal Properties (1)
Junction-to-Ambient Thermal Resistance
θJA (WSON-16)
26°C/W
θJA (20-Bump DSBGA)
(1)
50°C/W
Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2 x 1 array
of thermal vias. Thickness of copper layers are 2/1/1/2oz. Junction-to-ambient thermal resistance is highly application and board-layout
dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in
board design.The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In
applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues.
For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) (SNOA401).
Electrical Characteristics (1) (2) (3)
Typical limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range (TA = TJ = −30°C to +85°C). Unless otherwise noted, VIN1 = VIN2 = 3.6V.
Symbol
Parameter
Conditions
Min
(4)
Typ
−3.5
Max
Units
VFB
Feedback Voltage
VOUT
Line Regulation
2.7V ≤ VIN ≤ 5.5V
IO = 10 mA, VOUT = 1.8V
0.031
%/V
Load Regulation
100 mA ≤ IO ≤ 600 mA
VIN = 3.6V, VOUT = 1.8V
0.0013
%/mA
IQ PFM
Quiescent Current “On”
PFM Mode, Both Bucks ON
34
IQ SD
Quiescent Current “Off”
EN1 = EN2 = 0V
0.2
3
µA
ILIM
Peak Switching Current Limit
VIN = 3.6V
1200
1400
mA
RDS_ON
(WSON)
PFET
VIN = 3.6V, ISW = 200 mA
390
500
NFET
VIN = 3.6V, ISW = 200 mA
240
350
RDS_ON
(DSBGA)
PFET
VIN = 3.6V, ISW = 200 mA
350
400
NFET
VIN = 3.6V, ISW = 200 mA
170
210
FOSC
Internal Oscillator Frequency
2.0
2.4
MHz
IEN
Enable (EN) Input Current
0.01
1
µA
VIL
Enable Logic Low
0.4
V
VIH
Enable Logic High
850
1.5
+3.5
%
µA
mΩ
mΩ
1.0
V
POWER ON RESET THRESHOLD/FUNCTION (POR)
nPOR1 and
nPOR2
Delay Time
nPOR1 = Power ON Reset
for Buck 1
50 mS (default)
nPOR2 = Power ON Reset
for Buck 2
Can be pre-trimmd to 50 uS, 100
mS and 200 mS
POR
Threshold
Percentage of Target VOUT
VOUT Rising
94
VOUT Falling, 85% (default), Can be
pre-trimmed to 70% or 94%
85
(1)
(2)
(3)
(4)
50
mS
%
All voltages are with respect to the potential at the GND pin.
Min. and Max are specified by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are
tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages: VIN = 2.7V
to 5.5V for 1V ≤ VOUT ≤ 1.7V and for VOUT = 1.8V or greater, VIN = VOUT + 1VorVIN,MIN = ILOAD * (RDSON_PFET + RDCR_INDUCTOR) + VOUT
Test condition: for VOUT less than 2.5V, VIN = 3.6V; for VOUT greater than or equal to 2.5V, VIN = VOUT + 1V.
Dissipation Rating Table
θJA
TA = 60°C
Power Rating
26°C/W (4-Layer Board) WSON-16
50°C/W (4-Layer Board) 20-bump DSBGA
TA = 85°C
Power Rating
1538 mW
1300 mW
800 mW
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Typical Performance Characteristics
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN =
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
IQ_PFM (Non Switching)
Both Channels
IQ_PWM (Non Switching)
Both Channels
1
0.06
0.05
85oC
0.8
IQ_PWM (mA)
IQ_PFM (mA)
85oC
0.04
25oC
-30oC
0.03
0.02
25oC
-30oC
0.4
0.2
0.01
0
2.7
0.6
3.4
4.1
4.8
0
2.7
5.5
3.4
4.1
4.8
5.5
VIN (V)
VIN (V)
Figure 3.
Figure 4.
IQ_PWM (Switching)
Both Channels
IQ_SD (EN1 = EN2 = 0V)
0.5
14
0.45
-30oC
12
0.4
25oC
0.35
85oC
8
IQ_SD (PA)
IQ_PWM (mA)
10
6
0.3
0.25
0.2
0.15
4
0.1
2
0.05
0
2.7
3.4
4.1
4.8
0
2.7
5.5
3.4
4.1
VIN (V)
500
Figure 5.
Figure 6.
RDS_ON (PFET)
vs.
Temperature
VIN = 3.6V
RDS_ON (NFET)
vs.
Temperature
VIN = 3.6V
350
450
5.5
300
RDS_ON (m:)
RDS_ON (m:)
4.8
VIN (V)
400
LLP
350
micro SMD
250
LLP
200
300
micro SMD
150
250
200
-40
-20_
0
20
40
60
80
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7.
8
100
-40
Figure 8.
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN =
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
RDS_ON (WSON)
vs.
VIN
Current Limit
vs.
VIN
1200
500
450
1150
400
1100
PFET
ILIMIT (mA)
300
250
NFET
200
1050
85°C
1000
25°C
950
-40°C
900
150
850
100
800
750
50
0
2.7
3.4
4.1
4.8
700
2.7
5.5
3.2
3.7
4.2
Figure 9.
VIN
1.4
2.25
Buck1 = Buck2
5.5
Output Voltage
vs.
Output Current
= 3.6V (Forced PWM)
1.9
1.35
2.16
1.8V
1.8
1.3
VOUT (V)
SWITCH FREQUENCY (MHz)
5.2
Figure 10.
Switching Frequency
vs.
VIN
2.07
1.98
1.25
1.2V
1.7
1.2
1.15
1.6
1.1
1.89
1.05
1.8
2.7
1
3.4
4.1
4.8
5.5
0
100
200
VIN (V)
100
300
400
500
1.5
600
LOAD (mA)
Figure 11.
Figure 12.
Efficiency
vs.
Output Current
Forced PWM Mode, VOUT1 = 1.2V
Efficiency
vs.
Output Current
Forced PWM Mode, VOUT1 = 1.8V
100
90
90
80
70
60
4.5V
3.6V
50
5.5V
40
30
70
30
10
100.00
1000.00
5.5V
40
20
10.00
4.5V
50
10
1.00
3.6V
60
20
0
0.10
2.7V
80
2.7V
EFFICIENCY (%)
EFFICIENCY (%)
4.7
VIN (V)
VIN (V)
VOUT (V)
RDS_ON (m:)
350
0
0.10
1.00
10.00
LOAD (mA)
LOAD (mA)
Figure 13.
Figure 14.
100.00
1000.00
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN =
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
100
Efficiency
vs.
Output Current
Auto Mode, VOUT1 = 1.5V
Efficiency
vs.
Output Current
Auto Mode, VOUT2 = 1.9V
Figure 15.
Figure 16.
Efficiency
vs.
Output Current
Auto Mode, VOUT2 = 3.3V
Efficiency
vs.
Output Current
Forced PWM Mode, VOUT2 = 3.3V
100
90
90
60
5.5V
50
40
30
70
4.5V
60
40
30
20
10
10
1.00
10.00
100.00
1000.00
5.5V
50
20
0
0.10
10
80
4.5V
70
EFFICIENCY (%)
EFFICIENCY (%)
80
0
0.10
1.00
10.00
100.00
1000.00
LOAD (mA)
LOAD (mA)
Figure 17.
Figure 18.
Typical Operation Waveform
VIN = 3.6V, VOUT1 = 1.8V and VOUT2 = 1.8V
Load = 400 mA
Typical Operation Waveform
VIN = 4.8V, VOUT1 = 1V and VOUT2 = 3.3V
Load = 400 mA
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN =
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
Typical Operation Waveform
VIN = 3.6V, VOUT1 = 1.5V, VOUT2 = 2.5V,
Load = 600 mA Each
Startup at PWM for BUCK1
(VIN = 3.6V, VOUT = 1.5V, Load = 200 mA)
Figure 21.
Figure 22.
Startup at PWM for BUCK2
(VIN = 3.6V, VOUT = 2.5V, Load = 200 mA)
Line Transient
(VOUT1 = 1.2V)
Figure 23.
Figure 24.
Line Transient
(VOUT2 = 1.8V)
Load Transient in PFM MODE
(VOUT1 = 1.5V)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN =
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
12
Load Transient in PFM MODE
(VOUT1 = 1.5V)
Load Transient in PFM MODE
(VOUT1 = 1.8V)
Figure 27.
Figure 28.
Load Transient in PFM MODE (VOUT1 = 1.8V)
Load Transient in PWM MODE
(VIN = 3.6V, VOUT1 = 1.2V)
Figure 29.
Figure 30.
Load Transient in PWM MODE
(VIN = 3.6V, VOUT1 = 1.5V)
Load Transient in PWM MODE
(VIN = 3.6V, VOUT2 = 2.5V)
Figure 31.
Figure 32.
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Typical Performance Characteristics (continued)
LM3370, Circuit of Typical Application Circuit, VIN = 3.6V, VOUT1 = 1.5V and VOUT2 = 2.5V, L = 2.2 µH (NR3015T2R2M), CIN =
4.7 µF (0805) and COUT = 10 µF (0805) and TA = 25°C, unless otherwise noted.
Spread Spectrum Enabling
(VOUT Signal at 2 MHz)
VOUT Stepping
(From 1.8V to 3.3V)
BUCK2 at 100 mV/STEP
No Spread Spectrum
3.3V
11 dB
With Spread
Spectrum
5 dB/DIV
1.8V
RBW = 1 kHz
1.92 1.94 1.96 1.98 2.0 2.02 2.04 2.06 2.08 2.1 2.12
100 Ps/DIV
20 kHz/DIV
Figure 33.
Figure 34.
VOUT Stepping
(From 3.3V to 1.8V)
BUCK2 at 100 mV/STEP
3.3V
1.8V
100 Ps/DIV
Figure 35.
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OPERATION DESCRIPTION
Device Information
The LM3370, a dual high efficiency step-down DC-DC converter, delivers regulated voltages from input rails
between 2.7V to 5.5V. Using voltage mode architecture with synchronous rectification, the LM3370 has the ability
to deliver up to 600 mA per channel. The performance is optimized for systems where efficiency and space are
critical.
There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode
handles loads of approximately 70 mA or higher with 90% efficiency or better. Lighter loads cause the device to
automatically switch into PFM mode to maintain high efficiency with low supply current (IQ = 20µA typ.) per
channel.
The LM3370 can operate up to a 100% duty cycle (PFET switch always on) for low drop out control of the output
voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.
Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload
protection.
Circuit Operation
During the first portion of each switching cycle, the control block in the LM3370 turns on the internal PFET
switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The
inductor limits the current to a ramp with a slope of
VIN -VOUT
L
(1)
by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the PFET
switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor
draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor
current down with a slope of
-VOUT
L
(2)
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage
across the load.
PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is
introduced.
Internal Synchronous Rectification
While in PWM mode, the LM3370 uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
Current Limiting
A current limit feature allows the LM3370 to protect itself and external components during overload conditions.
PWM mode implements cycle-by-cycle current limiting using an internal comparator that trips at 1200 mA (typ.).
If the outputs are shorted to ground the device enters a timed current limit mode where the NFET is turned on for
a longer duration until the inductor current falls below a low threshold, ensuring inductor has more time to decay,
thereby preventing runaway.
14
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PFM Operation
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The part will automatically transition into PFM mode when either of two conditions are true, for a duration of 32 or
more clock cycles:
1. The NFET current reaches zero.
2. The peak PFET switch current drops below the IMODE level .
(Typically IMODE < 66 mA +
VIN
160:
)
(3)
Supply current during this PFM mode is less than 20 µA per channel, which allows the part to achieve high
efficiency under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle
repeats to restore the output voltage to ∼1.2% above the nominal PWM output voltage.
If the load current should increase during PFM mode (see Figure 36) causing the output voltage to fall below the
‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output
voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PFET power switch is turned on.
It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level
set for PFM mode. The typical peak current in PFM mode is:
IPFM = 115 mA + VIN/57Ω
(4)
Once the PFET power switch is turned off, the NFET power switch is turned on until the inductor current ramps
to zero. When the NFET zero-current condition is detected, the NFET power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold (see Figure 36), the PFET switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NFET switch is turned on briefly to ramp the inductor current to zero and then both output switches
are turned off and the part enters an extremely low power mode.
Forced PWM Mode
The LM3370 auto mode can be bypassed by forcing the device to operate in PWM mode, this can be
implemented through the I2C-compatible interface, see Table 3.
Soft-Start
The LM3370 has a soft start circuit that limits in-rush current during start up. Soft start is activated only if EN
goes from logic low to logic high after VIN reaches 2.7V.
LDO - Low Drop Out Operation
The LM3370 can operate at 100% duty cycle (no switching, PFET switch completely on) for low drop out support
of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.
The minimum input voltage needed to support the output voltage is
VIN,MIN = ILOAD*(RDSON,PFET + RINDUCTOR) + VOUT
where
•
•
•
ILOAD load current
• RDSON/PFET drain to source resistance of PFET switch in the triode region
• RINDUCTOR inductor resistance
(5)
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High PFM Threshold
~1.016*Vout
PFM Mode at Light Load
Load current
increases
ZAx
is
High PFM
Voltage
Threshold
reached,
go into
sleep mode
Nfet on
drains
conductor
current
until
I inductor=0
Current load
increases,
draws Vout
towards
Low2 PFM
Threshold
Low PFM
Threshold,
turn on
PFET
Low2 PFM Threshold
Vout
Low2 PFM Threshold,
switch back to PWM mode
xis
Z-A
Pfet on
until
Ipfm limit
reached
Low1 PFM Threshold
~1.008*Vout
PWM Mode at
Moderate to Heavy
Loads
Figure 36. Operation in PFM Mode and Transfer to PWM Mode
Table 1. I2C-Compatible Interface Electrical Specifications (1)
Symbol
FCLK
Parameter
Conditions
Min
Typ
Clock Frequency
Max
Units
400
kHz
tBF
Bus-Free Time between Start and Stop
(2)
1.3
µS
tHOLD
Hold Time Repeated Start Condition
(2)
0.6
µS
tCLKLP
CLK Low Period
(2)
1.3
µS
tCLKHP
CLK High Period
(2)
0.6
µS
tSU
Set Up Time Repeated Start Condition
(2)
0.6
µS
tDATAHLD
Data Hold Time
(2)
200
nS
tCLKSU
Data Set Up Time
(2)
200
nS
TSU
Set Up Time for Start Condition
(2)
0.6
TTRANS
Maximum Pulse Width of Spikes that Must be Suppressed
by the Input Filter of Both DATA and CLK signals.
(2)
VDD_I2C
I2C Logic High Level
(1)
(2)
µS
50
1
nS
VIN
V
Unless otherwise noted, VBATT = 2.7V to 5.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −30°C to +125°C.
Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages: VIN = 2.7V
to 5.5V for 1V ≤ VOUT ≤ 1.7V and for VOUT = 1.8V or greater, VIN = VOUT + 1VorVIN,MIN = ILOAD * (RDSON_PFET + RDCR_INDUCTOR) + VOUT
I2C-Compatible Interface
In I2C-compatible mode, the SCL pin is used for the I2C clock and the SDA pin is used for the I2C data. Both
these signals need a pull-up resistor according to I2C specification. The values of the pull-up resistor are
determined by the capacitance of the bus (typ. ∼1.8k). Signal timing specifications are according to the I2C bus
specification. Maximum frequency is 400 kHz.
I2C-Compatible Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
16
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SCL
SDA
data
change
allowed
data valid
data
change
allowed
data valid
data
change
allowed
Figure 37.
I2C-Compatible START and STOP Conditions
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
START condition
STOP condition
Figure 38.
Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by
an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the
9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an
acknowledge after each byte has been received.
After the START condition, I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the data will be written. The third byte contains data to write
to the selected register.
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I2C-Compatible Write Cycle
ack from slave
start
msb Chip Address lsb w ack
ack from slave
msb Register Add lsb
ack
ack from slave
msb
DATA
lsb
ack
stop
ack
stop
SCL
SDA
id = K¶xx
start
addr = K¶02
w ack
ack
DGGUHVV K¶02 data
W = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated startxx=36h
Figure 39.
However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as
shown in I2C-Compatible Read Cycle
I2C-Compatible Read Cycle
ack from slave
start
msb Chip Address lsb w ack
ack from slave repeated start
msb Register Add lsb
ack from slave
ack
rs
msb Chip Address lsb
r ack
ack
rs
id = K¶xx
r ack
data from slave
msb
DATA
ack from master
lsb
ack stop
SCL
SDA
start
id = K¶xx
w ack
addr = K¶00
DGGUHVV K¶00 data
ack stop
Figure 40.
Device Register Information
Table 2. Register Information
Register Name
Location
Type
Function
Control
00
R/W
Control signal for Buck 1 and Buck 2
Buck 1
01
R/W
Output setting and Mode selection for Buck 1
Buck 2
02
R/W
Output setting and Mode selection for Buck 2 and POR disable
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I2C Chip Address Information
MSB
LSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
0
1
0
0
0
0
1
R/W
bit0
2
I C SLAVE address (chip address)
Figure 41.
Register 00
MSB
LSB
7
6
5
4
3
2
1
0
EN1 for Buck 1 (default = 1)
Bit0 = 1 to enable
EN2 for Buck 2 (default = 1)
Bit1 = 1 to enable
Spread Spectrum (SS) Enable
Bit2 = 1 to enable
SS_fmod (SS Frequency Modulator)
ss_fmod = 1 1 kHz (default)
ss_fmod = 0 2 kHz
Pstep Enable for Buck1
Pstep = 0 (default) not enable
Pstep = 1
50 mV/step at 32 Ps/step
Pstep Enable for Buck2
Pstep = 0 (default) not enable
Pstep = 1
100 mV/step at 32 Ps/step
Bit 6 & 7 are not used
Register 01
MSB
7
LSB
6
5
4
3
2
1
0
Vout for Buck 1
00101 = 1V (Min.)
11111 = 2V (Max.)
Forced PWM Mode (FPWM1)
Auto = 0 (default)
FPWM1 = 1 (PWM mode only)
Bit 6 and 7 are not used
Figure 42.
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Register 02
MSB
7
LSB
6
5
4
3
2
1
0
Vout for Buck 2
00001 = 1.8V (Min.)
11111 = 3.3V (Max.)
Forced PWM Mode (FPWM2)
Auto = 0 (default)
FPWM2 = 1 (PWM mode only)
Disable Por function (DISPOR)
DISPOR = 0
enable Por (default)
DISPOR = 1
disable Por
Bit 7 is not used
Figure 43.
Table 3. Output Selection Table via I2C Programing
Buck Output Voltage Selection Codes
(1)
20
Data Code
Buck_1 (V)
Buck_2 (V)
00000
NA
NA
00001
NA
1.8
00010
NA
1.85 or 1.9 (1)
00011
NA
2.0
00100
NA
2.1
00101
1.00
2.2
00110
1.05
2.3
00111
1.10
2.4
01000
1.15
2.5
01001
1.20
2.6
01010
1.25
2.7
01011
1.30
2.8
01100
1.35
2.9
01101
1.40
3.0
01110
1.45
3.1
01111
1.50
3.2
10000
1.55
3.3
10001
1.60
NA
10010
1.65
NA
10011
1.70
NA
10100
1.75
NA
10101
1.80
NA
10110
1.85
NA
10111
1.90
NA
11000
1.95
NA
11001
2.00
NA
Can be trimmed at the factory at 1.85V or 1.9V using the same trim code.
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Application Information
Setting Output Voltage via I2C-Compatible
The outputs of the LM3370 can be programmed through Buck 1 and Buck 2 registers via I2C. Buck 1 output
voltage can be dynamically adjusted between 1V to 2V in 50 mV steps and Buck 2 output voltage can be
adjusted between 1.8V to 3.3V in 100 mV steps. Finer adjustments to the output of Buck 2 can be achieved with
the placement of a resistor between VOUT2 and the FB2 pin. Typically by placing a 20 KΩ resistor, R, between
these nodes will result in the programmed Output Voltage increasing by approximately 45 mV,ΔVTYP.
ΔVTYP= R × 500mV / 234KΩ
(6)
Please refer to for programming the desire output voltage. If the I2C-compatible feature is not used, the default
output voltage will be the pre-trimmed voltage. For example, LM3370SD-3021 refers to 1.2V for Buck 1 and 3.3V
for Buck 2.
VDD Pin
VDD is the power supply to the internal control circuit, if VDD pin is not tied to VIN during normal operating
condition, VDD must be set equal or greater of the two inputs ( VIN1 or VIN2 ). An optional capacitor can be used
for better noise immunity at VDD pin or when VDD is not tied to either VIN pins. Additionally, for reasons of noise
suppression, it is advisable to tie the EN1/EN2 pins to VDD rather than VIN .
SDA, SCL Pins
When not using I2C the SDA and SCL pins should be tied directly to the VDD pin.
Micro-Stepping:
The Micro-Stepping feature minimizes output voltage overshoot/undershoot during large output transients. If
Micro-stepping is enabled through I2C, the output voltage automatically ramps at 50 mV per step for Buck 1 and
100 mV per step for Buck 2. The steps are summarized as follow:
• Buck 1: 50 mV/step and 32 µs/step
• Buck 2: 100 mV/step and 32 µs/step
For example if changing Buck 1 voltage from 1V to 1.8V yields 20 steps [(1.8 - 1)/ 0.05 = 20]. This translates to
640 μs [(20 x 32 µs) = 640 µs] needed to reach the final target voltage.
Inductor Selection
There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor
current ripple is small enough to achieve the desired output voltage ripple.
There are two methods to choose the inductor current rating.
method 1:
The total current is the sum of the load and the inductor ripple current. This can be written as
IMAX = ILOAD + (
= ILOAD + (
IRIPPLE
)
2
VIN - VOUT
2*L
)*(
VOUT
VIN
)*(
1
)
f
where
•
•
•
•
ILOAD load current
VIN input voltage
L inductor
f switching frequency
(7)
method 2:
A more conservative approach is to choose an inductor that can handle the maximum current limit of 1400 mA.
Given a peak-to-peak current ripple (IPP) the inductor needs to be at least
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L >= (
VIN - VOUT
IPP
)*(
VOUT
VIN
)*(
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1
)
f
(8)
A 2.2 µH inductor with a saturation current rating of at least 1400 mA is recommended for most applications. The
inductor’s resistance should be less than around 0.2Ω for good efficiency. Table 4 lists suggested inductors and
suppliers.
For low-cost applications, an unshielded bobbin inductor is suggested. For noise critical applications, a toroidal or
shielded-bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of
both types for design flexibility. This allows substitution of a low-noise toroidal inductor, in the event that noise
from low-cost bobbin models is unacceptable.
Below are some suggested inductor manufacturers that include but are not limited to:
Table 4. Suggested Inductors and Suppliers
Model
Vendor
Dimensions (mm)
ISAT
DO3314-222
Coilcraft
3.3 x 3.3 x 1.4
1.6A
LPO3310-222
3.3 x 3.3 x 1.0
1.1A
SD3114-2R2
Cooper
3.1 x 3.1 x 1.4
1.48A
NR3010T2R2M
Taiyo Yuden
3.0 x 3.0 x 1.0
1.1A
3.0 x 3.0 x 1.5
1.48A
2.6 x 2.8 x 1.0
1.0A
NR3015T2R2M
VLF3010AT- 2R2M1R0
TDK
Input Capacitor Selection
A ceramic input capacitor of 4.7 μF, 6.3V is sufficient for most applications. A larger value may be used for
improved input voltage filtering. The input filter capacitor supplies current to the PFET switch of the LM3370 in
the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor's
low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select
an input filter capacitor with a surge current rating sufficient for the power-up surge from the input power source.
The power-up surge current is approximately the capacitor’s value (µF) times the voltage rise rate (V/µs).
The input current ripple can be calculated as:
VOUT
IRMS = IOUTMAX *
VIN
§
*¨1©
VOUT ·
VIN
¸
¹
The worst case IRMS is:
IOUTMAX
(duty cycle = 50%)
IRMS =
2
(9)
Output Capacitor Selection
DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603.
DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested from
them as part of the capacitor selection process.
The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output
voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with
sufficient capacitance and sufficiently low ESR to perform these functions. The output ripple voltage can be
calculated as:
Voltage peak-to-peak ripple due to capacitance =
VPP-C =
22
IPP
f*8*C
(10)
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Voltage peak-to-peak ripple due to ESR = VPP-ESR = IPP*RESR
Voltage peak-to-peak ripple, root mean squared =
VPP-RMS =
VPP-C2 + VPP-ESR2
(11)
Note that the output ripple is dependent on the current ripple and the equivalent series resistance of the output
capacitor (RESR). The RESR is frequency dependent (as well as temperature dependent); make sure that the
frequency of the RESR given is the same order of magnitude as the switching frequency.
Table 5. Suggested Capacitors and Their Suppliers
Model
Description
Case Size
Vendor
TDK
4.7 µF for CIN
C1608X5R0J475
Ceramic, X5R, 6.3V Rating
0603
C2012X5R0J475
Ceramic, X5R, 6.3V Rating
0805
JMK212BJ475
Ceramic, X5R, 6.3V Rating
0805
GRM21BR60J475
Ceramic, X5R, 6.3V Rating
0805
GRM219R60J475KE19D
Ceramic, X5R, 6.3V Rating
0805(Thin)