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LM3421, LM3423
SNVS574G – JULY 2008 – REVISED JULY 2019
LM342x N -Channel Controllers for Constant-Current LED Drivers
1 Features
3 Description
•
•
•
•
The LM3421 and LM3423 family of devices are
versatile high voltage N-channel MOSFET controllers
for LED drivers. They can be easily configured in
buck, boost, buck-boost and SEPIC topologies. This
flexibility, along with an input voltage rating of 75 V,
makes the these controllers ideal for illuminating
LEDs in a large family of applications.
1
•
•
•
•
•
•
VIN Range From 4.5 V to 75 V
High-Side Adjustable Current Sense
2-Ω, 1-A Peak MOSFET Gate Driver
Input Undervoltage and Output Overvoltage
Protection
PWM and Analog Dimming
Cycle-by-Cycle Current Limit
Programmable Switching Frequency
Zero Current Shutdown and Thermal Shutdown
LED Output Status Flag (LM3423 and LM3423-Q0
Only)
Fault Status Flag and Timer(LM3423 and
LM3423-Q0 Only)
The LM3421 and LM3423 devices include a highvoltage start-up regulator that operates over a wide
input range of 4.5 V to 75 V. The internal PWM
controller is designed for adjustable switching
frequencies of up to 2 MHz, thus enabling compact
solutions.
2 Applications
•
•
•
•
•
Adjustable high-side current sense voltage allows for
tight regulation of the LED current with the highest
efficiency possible. The LM3421 and LM3423 devices
use predictive off-time (PRO) control, which is a
combination of peak current-mode control and a
predictive off-timer. This method of control eases the
design of loop compensation while providing inherent
input voltage feed-forward compensation.
LED Drivers: Buck, Boost, Buck-Boost, and
SEPIC
Indoor and Outdoor Area SSL
Automotive
General Illumination
Constant-Current Regulators
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM3421
HTSSOP (16)
5.00 mm × 4.40 mm
LM3423
HTSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Boost Application
VIN
PWM
1
VIN
HSN
16
2
EN
HSP
15
3
COMP
RPD
14
4
CSH
IS
13
5
RCT
VCC
12
6
AGND
GATE
11
7
OVP
PGND
10
8
nDIM
DDRV
9
ILED
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3421, LM3423
SNVS574G – JULY 2008 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics .......................................... 7
Typical Characteristics ........................................... 11
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
9
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Applications ................................................ 32
10 Power Supply Recommendations ..................... 65
10.1 General Recommendations .................................. 65
10.2 Input Supply Current Limit .................................... 65
11 Layout................................................................... 65
11.1 Layout Guidelines ................................................. 65
11.2 Layout Example .................................................... 66
12 Device and Documentation Support ................. 67
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
67
67
67
67
67
67
13 Mechanical, Packaging, and Orderable
Information ........................................................... 67
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (July 2015) to Revision G
Page
•
Deleted references to automotive grade (LM342x-Q1 and LM342x-Q0) devices, now available in data sheet SNVSB95... 1
•
Corrected typographic error in Table 1................................................................................................................................... 3
•
Changed EN pulldown resistance specification minimum value from: 0.45 MΩ to: 0.245 MΩ Electrical
Characteristics table. ............................................................................................................................................................. 7
•
Changed EN pulldown resistance specification maximum value from: 1.3 MΩ to: 2.85 MΩ in Electrical
Characteristics table. ............................................................................................................................................................. 7
Changes from Revision E (April 2013) to Revision F
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision D (May 2013) to Revision E
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 64
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SNVS574G – JULY 2008 – REVISED JULY 2019
5 Device Comparison
Table 1. Device Comparison
FLAG FEATURES
LED OUTPUT
FAULT
STATUS
QUALIFACTION
TEMPERATURE
RANGE, TA
LM3421-Q0
No
No
AEC-Q100 Grade 0
–40°C to +150°C
LM3421-Q1
No
No
AEC-Q100 Grade 1
–40°C to +125°C
LM3423-Q0
Yes
Yes
AEC-Q100 Grade 0
–40°C to +150°C
LM3423-Q1
Yes
Yes
AEC-Q100 Grade 1
–40°C to +125°C
DEVICE
LM3421
No
No
Commercial Grade
–40°C to +125°C
LM3423
Yes
Yes
Commercial Grade
–40°C to +125°C
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SNVS574G – JULY 2008 – REVISED JULY 2019
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6 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
PWP Package
20-Pin HTSSOP
Top View
VIN
1
16
HSN
VIN
1
20
HSN
EN
2
15
HSP
EN
2
19
HSP
COMP
3
14
RPD
COMP
3
18
RPD
CSH
4
13
IS
CSH
4
17
IS
RCT
5
12
VCC
RCT
5
16
VCC
AGND
6
OVP
7
nDIM
8
17 Thermal
Pad
11
GATE
AGND
6
15
GATE
10
PGND
OVP
7
10
14
PGND
9
DDRV
nDIM
8
9
13
DDRV
FLT
9
12
IADJ
11
VREF
TIMR
21 Thermal
Pad
10
Pin Functions
PIN
I/O (1)
FUNCTION
6
G
Analog ground. Connect to PGND through the DAP copper pad to provide ground return
for CSH, COMP, RCT, and TIMR.
3
3
I
Compensation. Connect a capacitor to AGND to set the compensation.
CSH
4
4
I
Current sense high. Connect a resistor to AGND to set the signal current. For analog
dimming, connect a controlled current source or a potentiometer to AGND as detailed in
the Analog Dimming section.
DDRV
13
9
O
Dim gate drive output. Connect to the gate of the dimming MOSFET.
DPOL
12
—
I
Dim polarity. Connect to AGND if dimming with a series P-channel MOSFET or leave
open when dimming with series N-channel MOSFET.
EN
2
2
I
Enable. Connect to AGND for zero current shutdown or apply more than 2.4 V to enable
device.
FLT
9
—
I
Fault flag. Connect to pullup resistor from VIN and N-channel MOSFET open-drain
output is high when a fault condition is latched by the timer.
GATE
15
11
O
Main gate drive output. Connect to the gate of the main switching MOSFET.
HSN
20
16
I
LED current sense negative. Connect through a series resistor to the negative side of
the LED current sense resistor.
HSP
19
15
I
LED current sense positive. Connect through a series resistor to the positive side of the
LED current sense resistor.
IS
17
13
I
Main switch current sense. Connect to the drain of the main N-channel MOSFET switch
for RDS-ON sensing or to a sense resistor installed in the source of the same device.
LRDY
11
—
O
LED ready flag. Connect to pullup resistor from VIN and N-channel MOSFET open-drain
output pulls down when the LED current is not in regulation.
nDIM
8
8
I
Dimming input and undervoltage protection. Connect a PWM signal for dimming as
detailed in the PWM Dimming section and/or a resistor divider from VIN to program input
undervoltage lockout (UVLO). Turnon threshold is 1.24 V and hysteresis for turnoff is
provided by a 23-µA current source.
OVP
7
7
I
Overvoltage protection. Connect to a resistor divider from VO to program output
overvoltage lockout (OVLO). Turnoff threshold is 1.24 V and hysteresis for turnon is
provided by 23-µA current source.
PGND
14
10
G
Power ground. Connect to AGND through the DAP copper pad to provide ground return
for GATE and DDRV.
RCT
5
5
I
Resistor capacitor timing. External RC network sets the predictive off-time and thus the
switching frequency.
NAME
LM3423
LM3421
AGND
6
COMP
(1)
4
G = Ground, I = Input, O = Output
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SNVS574G – JULY 2008 – REVISED JULY 2019
Pin Functions (continued)
PIN
NAME
I/O (1)
FUNCTION
LM3423
LM3421
RPD
18
14
I
Resistor pulldown. Connect the low side of all external resistor dividers (VIN UVLO,
OVP) to implement zero-current shutdown.
TIMR
10
—
I
Fault timer. Connect a capacitor to AGND to set the time delay before a sensed fault
condition is latched.
VIN
1
1
I
Input voltage. Bypass with 100-nF capacitor to AGND as close to the device as possible
in the printed-circuit-board layout.
VCC
16
12
I
Internal regulator output. Bypass with 2.2-µF to 3.3-µF ceramic capacitor to PGND.
G
Thermal PAD on bottom of IC. Star ground, connecting AGND and PGND.
DAP (21)
DAP (17)
G
Star ground, connecting AGND and PGND.
Thermal PAD
DAP
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
VIN, EN, RPD, nDIM
MIN
MAX
–0.3
76
UNIT
–1 continuous
–0.3
OVP, HSP, HSN, LRDY, FLT, DPOL
76
–100 continuous
RCT
IS
µA
76
V
–1 continuous
5 continuous
mA
–0.3
76
–1 continuous
TIMR
COMP, CSH
GATE, DDRV
PGND
8
7
(3)
V
V
–100 continuous
100 continuous
µA
–0.3
6
V
–200 continuous
200 continuous
µA
–0.3
VCC
–2.5 for 100 ns
VCC+ 2.5 for 100 ns
–1 continuous
1 continuous
–0.3
0.3
–2.5 for 100 ns
2.5 for 100 ns
V
mA
V
Internally Limited
Internally Limited
(3)
Storage temperature
(2)
mA
–0.3
Maximum junction temperature
(1)
V
–0.3
Continuous power dissipation
Maximum lead temperature (solder and reflow)
V
–0.3
–2 for 100 ns
VCC
V
mA
–65
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Refer to http://www.ti.com/packaging for more detailed information and mounting techniques.
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7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±2000
Charged-device model (CDM), per JEDEC specification
JESD22-C101
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Operating junction temperature, TJ
LM3421 , LM3423
Input voltage, VIN
MIN
MAX
UNIT
−40
125
°C
4.5
75
V
7.4 Thermal Information
THERMAL METRIC
(1)
LM3421
LM3423
PWP (HTSSOP)
PWP (HTSSOP)
16 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
38.9
36.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.1
21.5
°C/W
RθJB
Junction-to-board thermal resistance
16.8
18
°C/W
ψJT
Junction-to-top characterization parameter
0.6
0.5
°C/W
ψJB
Junction-to-board characterization parameter
16.6
17.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.7
1.9
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
VIN = 14, −40°C ≤ TJ ≤ 125°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
START-UP REGULATOR
VCCREG
VCC regulation
ICCLIM
VCC current limit
IQ
Quiescent Current
ISD
Shutdown current
ICC = 0 mA
6.3
ICC = 0 mA, TA = 25°C
7.35
6.9
VCC = 0 V
20
VCC = 0 V, TA = 25°C
mA
25
VEN = 3 V, Static
3
VEN = 3 V, Static, TA = 25°C
2
VEN = 0 V
1
VEN = 0 V, TA = 25°C
V
0.1
mA
µA
VCC SUPPLY
VCC Increasing
VCCUV
VCC UVLO Threshold
VCCHYS
VCC UVLO Hysteresis
4.5
VCC Increasing, TA = 25°C
4.17
VCC Decreasing
V
3.7
VCC Decreasing, TA = 25°C
4.08
TA = 25°C
0.1
V
ENABLE THRESHOLDS
ENST
EN start-up threshold
ENST
EN start-up threshold
ENSTHYS
EN start-up hysteresis
REN
EN pulldown resistance
VEN Increasing
2.4
VEN Increasing, TA = 25°C
1.75
VEN Decreasing
0.8
VEN Decreasing, TA = 25°C
V
1.63
TA = 25°C
0.1
VEN = 1 V
0.245
VEN = 1 V, TA = 25°C
V
V
2.85
0.82
MΩ
CSH THRESHOLDS
CSH high fault
CSH Increasing, TA = 25°C
CSH low condition on LRDY
Pin
CSH increasing, TA = 25°C
LM3423
1.6
V
1
V
OV THRESHOLDS
OVPCB
OVP OVLO threshold
OVPHYS
OVP hysteresis source current
OVP Increasing
1.185
OVP Increasing, TA = 25°C
OVP Active (high)
OVP Active (high), TA = 25°C
1.285
1.24
20
25
23
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Electrical Characteristics (continued)
VIN = 14, −40°C ≤ TJ ≤ 125°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DPOL THRESHOLDS
DPOLTHRSH
DPOL logic threshold
RDPOL
DPOL pullup resistance
DPOL Increasing
2
2.6
DPOL Increasing, TA = 25°C
2.3
TA = 25°C
500
1200
V
kΩ
FAULT TIMER
VFLTTH
Fault threshold
IFLT
FAULT pin source current
1.185
TA = 25°C
1.29
1.24
10
TA = 25°C
13
11.5
V
µA
ERROR AMPLIFIER
VREF
CSH reference voltage
Error amplifier input bias
current
COMP sink or source current
Transconductance
Linear input range
Transconductance bandwidth
w/r/t to AGND
1.21
w/r/t to AGND, TJ = 25°C
1.26
1.235
TJ = 25°C
–0.6
0
22
35
TJ = 25°C
30
TJ = 25°C
(1)
, TJ = 25°C
–6dB Unloaded Response
MIN = TJ = 25°C
0.6
V
µA
µA
100
µA/V
±125
mV
1
MHz
(1)
,
0.5
OFF TIMER
tOFF(min)
Minimum OFF-time
RRCT
RCT reset pulldown resistance
VRCT
VIN/25 reference voltage
f
Continuous conduction
switching frequency
RCT = 1 V through 1 kΩ
75
RCT = 1 V through 1 kΩ, TJ = 25°C
35
120
TJ = 25°C
VIN = 14 V
36
540
VIN = 14 V, TJ = 25°C
585
565
2.2 nF > CT > 470 pF, TJ = 25°C
(See
(2)
)
ns
Ω
mV
Hz
PWM COMPARATOR
COMP-to-PWM offset voltage
700
TJ = 25°C
900
800
mV
CURRENT LIMIT (IS)
ILIM
Current limit threshold
Current limit delay-to-output
tLEB
Leading edge blanking (LEB)
time
215
275
TJ = 25°C
245
TJ = 25°C
35
75
115
TJ = 25°C
325
210
mV
ns
ns
HIGH SIDE TRANSCONDUCTANCE AMPLIFIER
Input bias current
gM
(1)
(2)
8
Transconductance
TJ = 25°C
11.5
20
TJ = 25°C
119
µA
mA/V
Specified by design. Not production tested.
f = 25/(CT × RT
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Electrical Characteristics (continued)
VIN = 14, −40°C ≤ TJ ≤ 125°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
Input offset current
Input offset voltage
gM(BW)
Transconductance bandwidth
TEST CONDITIONS
MIN
TYP
–1.5
TJ = 25°C
1.5
0
–7
TJ = 25°C
ICSH = 100 µA (1), TJ = 25°C
MAX
7
0
250
500
UNIT
µA
mV
kHz
GATE DRIVER (GATE)
RSRC(GATE)
GATE sourcing resistance
RSNK(GATE)
GATE sinking resistance
GATE = High
6
GATE = High, TJ = 25°C
2
GATE = Low
4.5
GATE = Low, TJ = 25°C
1.3
Ω
Ω
DIM DRIVER (DIM, DDRV)
nDIMVTH
nDIM / UVLO threshold
nDIMHYS
nDIM hysteresis current
RSRC(DDRV)
DDRV sourcing resistance
RSNK(DDRV)
DDRV sinking resistance
1.185
TJ = 25°C
1.285
1.24
20
TJ = 25°C
25
23
DDRV = High
DDRV = High, TJ = 25°C
30
13.5
DDRV = Low
DDRV = Low, TJ = 25°C
10
3.5
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µA
Ω
Ω
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Electrical Characteristics (continued)
VIN = 14, −40°C ≤ TJ ≤ 125°C unless otherwise specified. Minimum and maximum limits are specified through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PULLDOWN N-CHANNEL MOSFETS
RRPD
RPD pulldown resistance
RFLT
FLT pulldown resistance
RLRDY
LRDY pulldown resistance
300
TJ = 25°C
145
TJ = 25°C
145
TJ = 25°C
135
300
300
Ω
Ω
Ω
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold (1)
TJ = 25°C
165
°C
THYS
Thermal shutdown
hysteresis (1)
TJ = 25°C
25
°C
10
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7.6 Typical Characteristics
TA= 25°C, VIN = 14 V unless otherwise specified
VO = 32 V (9 LEDs)
Figure 1. Boost Efficiency vs. Input Voltage
VO = 21 V (6 LEDs)
Figure 2. Buck-Boost Efficiency vs. Input Voltage
VO = 32V (9 LEDs)
Figure 3. Boost LED Current vs. Input Voltage
VO = 21 V (6 LEDs)
Figure 4. Buck-Boost LED Current vs. Input Voltage
VO = 21 V (6 LEDs), VIN = 24 V
Figure 5. Analog Dimming
VO = 32 V (9 LEDs), VIN = 24 V
Figure 6. PWM Dimming
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Typical Characteristics (continued)
TA= 25°C, VIN = 14 V unless otherwise specified
Figure 8. VCC vs Junction Temperature
Figure 7. VCSH vs Junction Temperature
567
VRCT (mV)
566
565
564
563
562
-50
-14
22
58
94
130
TEMPERATURE (°C)
Figure 9. VRCT vs Junction Temperature
Figure 10. VLIM vs Junction Temperature
225
tON-MIN (ns)
220
215
210
205
200
195
-50
-14
22
58
94
130
TEMPERATURE (°C)
Figure 11. tON(min) vs Junction Temperature
12
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8 Detailed Description
8.1 Overview
The LM3421 and LM3423 are N-channel MOSFET ( N-channel FET ) controllers for buck, boost and buck-boost
current regulators which are ideal for driving LED loads. The controller has wide input voltage range allowing for
regulation of a variety of LED loads. The high-side differential current sense, with low adjustable threshold
voltage, provides an excellent method for regulating output current while maintaining high system efficiency.
The devices use a Predictive Off-time (PRO) control architecture that allows the regulator to be operated using
minimal external control loop compensation, while providing an inherent cycle-by-cycle current limit. The
adjustable current sense threshold provides the capability to amplitude (analog) dim the LED current and the
output enable and disable function with external dimming FET driver allows for fast PWM dimming of the LED
load. The maximum attainable LED current is not internally limited because the device is a controller. Instead,
current is a function of the system operating point, component choices, and switching frequency that allows the
device to easily provide constant currents up to 5 A. This controller contains all the features necessary to
implement a high-efficiency versatile LED driver.
8.2 Functional Block Diagram
VIN
6.9V LDO
Regulator
EN
VCC
820k
UVLO
(4.1V)
VCC UVLO
REFERENCE
500k
VIN UVLO
Standby
HYSTERESIS
23 PA
nDIM
1.235V
VCC
TLIM Thermal
DPOL
Limit
Dimming
1.24V
DDRV
OVLO
LatchOff
RCT
PGND
Reset
Dominant
Start new on time
VIN/25
LEB
VCC
Q
S
GATE
R
W = 150 ns
PGND
COMP
RPD
23 PA
PWM
1.235V
OVP
HYSTERESIS
EN
CSH
OVP
OVLO
800 mV
LOGIC
HSN
1.24V
STOP
HSP
LRDY
CURRENT
LIMIT
IS
0.245V
11.5 PA
LED CURRENT LOW
LEB
1.0V
LatchOff
LED CURRENT HIGH
FLT
TIMR
1.24V
1.6V
AGND
Grey pins are available in the LM3423 only.
In the LM3421, TIMR is internally shorted to AGND.
TLIM
VCC UVLO
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8.3 Feature Description
8.3.1 Current Regulators
iL (t)
IL-MAX
ÂiL-PP
IL
IL-MIN
tON = DTS
tOFF = (1-D)TS
t
0
TS
Figure 12. Ideal CCM Regulator Inductor Current iL(t)
Current regulators can create three basic topologies: buck, boost, or buck-boost. All three topologies in their
most basic form contain a main switching MOSFET, a recirculating diode, an inductor and capacitors. The
controller is designed to drive a ground referenced N-channel FET which is perfect for a standard boost
regulator. However, buck and buck-boost regulators usually have a high-side switch. When driving an LED load,
a ground referenced load is often not necessary, therefore a ground referenced switch drives a floating load
instead. The controller can then be used to drive all three basic topologies as shown in the Basic Topology
Schematics section. Other topologies such as the SEPIC and flyback converter (both derivatives of the buckboost) can be implemented as well.
Looking at the buck-boost design, the basic operation of a current regulator can be analyzed. During the time
that the N-channel FET (Q1) is turned on (tON), the input voltage source stores energy in the inductor (L1) while
the output capacitor (CO) provides energy to the LED load. When Q1 is turned off (tOFF), the re-circulating diode
(D1) becomes forward biased and L1 provides energy to both CO and the LED load. Figure 12 shows the
inductor current (iL(t)) waveform for a regulator operating in CCM.
The average output LED current (ILED) is proportional to the average inductor current (IL) , therefore if IL is tightly
controlled, ILED is well regulated. As the system changes input voltage or output voltage, the ideal duty cycle (D)
is varied to regulate IL and ultimately ILED. For any current regulator, D is a function of the conversion ratio:
Buck
D=
VO
VIN
(1)
VO - VIN
VO
(2)
Boost
D=
Buck-boost
D=
VO
VO + VIN
(3)
8.3.2 Predictive Off-Time (PRO) Control
PRO control is used by the device to control ILED. It is a combination of average peak current control and a oneshot off-timer that varies with input voltage. The LM3421 and LM3423 use peak current control to regulate the
average LED current through an array of HBLEDs. This method of control uses a series resistor in the LED path
to sense LED current and can use either a series resistor in the MOSFET path or the MOSFET RDS-ON for both
cycle-by-cycle current limit and input voltage feed forward. D is indirectly controlled by changes in both tOFF and
tON, which vary depending on the operating point.
14
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Feature Description (continued)
Even though the off-time control is quasi-hysteretic, the input voltage proportionality in the off-timer creates an
essentially constant switching frequency over the entire operating range for boost and buck-boost topologies.
The buck topology can be designed to give constant ripple over either input voltage or output voltage, however
switching frequency is only constant at a specific operating point .
This type of control minimizes the control loop compensation necessary in many switching regulators, simplifying
the design process. The averaging mechanism in the peak detection control loop provides extremely accurate
LED current regulation over the entire operating range.
PRO control was designed to mitigate current mode instability (also called sub-harmonic oscillation) found in
standard peak current mode control when operating near or above 50% duty cycles. When using standard peak
current mode control with a fixed switching frequency, this condition is present, regardless of the topology.
However, using a constant off-time approach, current mode instability cannot occur, enabling easier design and
control.
Predictive off-time advantages:
• There is no current mode instability at any duty cycle.
• Higher duty cycles or voltage transformation ratios are possible, especially in the boost regulator.
The only disadvantage is that synchronization to an external reference frequency is generally not available.
8.3.3 Average LED Current
LM3421/23
ILED
VSNS
RSNS
RHSP
RHSN
RCSH
HSP
High-Side
Sense Amplifier
HSN
CSH
ICSH
Error Amplifier
1.24V
CCMP
To PWM
Comparator
COMP
Figure 13. LED Current Sense Circuitry
The LM3421 and LM3423 use an external current sense resistor (RSNS) placed in series with the LED load to
convert the LED current (ILED) into a voltage (VSNS) as shown in Figure 13. The HSP and HSN pins are the inputs
to the high-side sense amplifier which are forced to be equal potential (VHSP=VHSN) through negative feedback.
Because of this, the VSNS voltage is forced across RHSP to generate the signal current (ICSH) which flows out of
the CSH pin and through the RCSH resistor. The error amplifier regulates the CSH pin to 1.24 V, therefore ICSH
can be calculated using Equation 4.
ICSH =
VSNS
RHSP
(4)
This application regulates VSNS as described in Equation 5.
RHSP
VSNS = 1.24V x
RCSH
(5)
Calculate ILED using Equation 6.
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Feature Description (continued)
ILED =
VSNS
1.24V RHSP
x
=
RSNS
RSNS
RCSH
(6)
The selection of the three resistors (RSNS, RCSH, and RHSP) is not arbitrary. For matching and noise performance,
the suggested signal current ICSH is approximately 100 µA. This current does not flow in the LEDs and does not
affect either the off-state LED current or the regulated LED current. ICSH can be above or below this value, but
the high-side amplifier offset characteristics may be affected slightly. In addition, to minimize the effect of the
high-side amplifier voltage offset on LED current accuracy, the minimum VSNS is suggested to be 50 mV. Place a
resistor (RHSN = RHSP) in series with the HSN pin to cancel out the effects of the input bias current (approximately
10 µA) of both inputs of the high-side sense amplifier.
The sense resistor (RSNS) can be placed anywhere in the series string of LEDs as long as the voltage at the HSN
and HSP pins (VHSP and VHSN) satisfies the following conditions.
VHSP < 76V
VHSN > 3.5V
(7)
Typically, for a buck-boost configuration, RSNS is placed at the bottom of the string (LED-) which allows for
greater flexibility of input and output voltage. However, if there is substantial input voltage ripple allowed, it can
help to place RSNS at the top of the string (LED+) which limits the output voltage of the string to:
VO = 76V - VIN
(8)
The CSH pin can also be used as a low-side current sense input regulated to 1.24 V. The high-side sense
amplifier is disabled if HSP and HSN are tied to AGND (or VHSN > VHSP) .
8.3.4 Analog Dimming
The CSH pin can be used to analog dim the LED current by adjusting the current sense voltage (VSNS). There
are several different methods to adjust VSNS using the CSH pin:
1. External variable resistance: Adjust a potentiometer placed in series with RCSH to vary VSNS.
2. External variable current source: Source current (0 µA to ICSH) into the CSH pin to adjust VSNS.
Variable Current Source
VCC
LM3421/23
VREF
Q8
Q7
RMAX
Q6
RADJ
RBIAS
CSH
RCSH
RADJ
Variable
Resistance
Figure 14. Analog Dimming Circuitry
In general, analog dimming applications require a lower switching frequency to minimize the effect of the leading
edge blanking circuit. As the LED current is reduced, the output voltage and the duty cycle decreases.
Eventually, the minimum on-time is reached. The lower the switching frequency, the wider the linear dimming
range. Figure 14 shows how both CSH methods are physically implemented.
Method 1 uses an external potentiometer in the CSH path which is a simple addition to the existing circuitry.
However, the LEDs cannot dim completely because there is always some resistance causing signal current to
flow. This method is also susceptible to noise coupling at the CSH pin because the potentiometer increases the
size of the signal current loop.
16
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Feature Description (continued)
Method 2 provides a complete dimming range and better noise performance, though it is more complex. It
consists of a PNP current mirror and a bias network consisting of an NPN, 2 resistors and a potentiometer
(RADJ), where RADJ controls the amount of current sourced into the CSH pin. A higher resistance value sources
more current into the CSH pin, causing less regulated signal current through RHSP, effectively dimming the LEDs.
VREF should be a precise external voltage reference, while Q7 and Q8 should be a dual pair PNP for best
matching and performance. The additional current (IADD) sourced into the CSH pin can be calculated using
Equation 9.
IADD =
§ RADJ x VREF ·
¨R + R ¸ - VBE-Q6
© ADJ MAX ¹
RBIAS
(9)
The corresponding LED current ( ILED) for a specific IADD is:
§ RHSP·
¸
© RSNS¹
ILED = (ICSH - IADD) x ¨
(10)
8.3.5 Current Sense and Current Limit
The LM3421 and LM3423 achieve peak current mode control using a comparator that monitors the main
MOSFET (Q1) transistor current, comparing it with the COMP pin voltage as shown in Figure 15. The controller
incorporates a cycle-by-cycle overcurrent protection function. Aredundant internal current sense comparator
provides the current limit functionality . If the voltage at the current sense comparator input (IS pin) exceeds 245
mV (typical), the on cycle is immediately terminated. The IS input pin has an internal N-channel MOSFET which
pulls it down at the conclusion of every cycle. The discharge device remains on for an additional 210 ns (typical)
after the beginning of a new cycle to blank the leading edge spike on the current sense signal. The leading edge
blanking (LEB) determines the minimum achievable on-time (tON-MIN).
RDS-ON
Sensing
Q1
LM3421/23
COMP
GATE
0.8V
RLIM
Sensing
PWM
IS
0.245V
IT
RLIM
LEB
PGND
Figure 15. Current Sense / Current Limit Circuitry
There are two possible methods to sense the transistor current. The RDS-ON of the main power MOSFET can be
used as the current sense resistance because the IS pin was designed to withstand the high voltages present on
the drain when the MOSFET is in the off state. Alternatively, a sense resistor located in the source of the
MOSFET may be used for current sensing; however, TI suggests a low inductance (ESL) type. The cycle-bycycle current limit (ILIM) can be calculated using either method as the limiting resistance (RLIM):
245 mV
ILIM =
RLIM
(11)
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Feature Description (continued)
8.3.6 Overcurrent Protection
The LM3421 and LM3423 controllers have a secondary method of overcurrent protection. Switching action is
disabled whenever the current in the LEDs is more than 30% above the regulation set point. The dimming
MOSFET switch driver (DDRV) is not disabled however as this would immediately remove the fault condition and
cause oscillatory behavior.
8.3.7 Zero Current Shutdown
The LM3421 and LM3423 controllers implement zero current shutdown through the EN and RPD pins. When
pulled low, the EN pin places the devices into near-zero current state, where only the leakage currents occurs at
the pins (typical 0.1 µA). The applications circuits frequently have resistor dividers to set UVLO, OVLO, or other
similar functions. The RPD pin is an open-drain N-channel MOSFET that is enabled only when the device is
enabled. Tying the bottom of all resistor dividers to the RPD pin as shown in Figure 16 allows them to float
during shutdown, thus removing their current paths and providing true application-wide zero current shutdown.
L1
D1
VIN
VO
Enable
LM3421/23
EN
ROV2
VIN
OVP
ROV1
RUV2
nDIM
RPD
RUV1
Figure 16. Zero Current Shutdown Circuit
8.3.8 Control Loop Compensation
The control loop is modeled as most typical current mode controllers. Using a first order approximation, the
uncompensated loop can be modeled as a single pole created by the output capacitor and, in the boost and
buck-boost topologies, a right half plane zero created by the inductor, where both have a dependence on the
LED string dynamic resistance. There is also a high-frequency pole in the model; however, it is near the
switching frequency and plays no part in the compensation design process. Therefore, it is neglected. Because
ceramic capacitance is recommended for use with LED drivers, due to long lifetimes and high ripple current
rating, the ESR of the output capacitor can also be neglected in the loop analysis. The DC gain of the
uncompensated loop depends on internal controller gains and the external sensing network.
This section describes a buck-boost regulator as an example case.
Use Equation 12 to calculate the uncompensated loop gain for a buck-boost regulator.
§
s ·
¸
¨1 ¨ ZZ1 ¸
¹
©
TU = TU0 x
§
s ·
¨1+
¸
¨ ZP1 ¸
©
¹
(12)
Where the uncompensated DC loop gain of the system is calculated using Equation 13.
Dc x 500V x RCSH x RSNS
Dc x 620V
TU0 =
=
(1+ D) x RHSP x R LIM (1+ D) x ILED x R LIM
(13)
And the output
3 pole (ωP1) is approximated using Equation 14.
1+ D
ZP1 =
rD x CO
(14)
18
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Feature Description (continued)
And the right half plane zero (ωZ1) is:
rD x Dc2
ZZ1 =
D x L1
(15)
100
öZ1
80
135
öP1
90
GAIN
GAIN (dB)
0
40
PHASE
-45
20
0° Phase Margin
-90
0
-20
-135
-40
-180
-60
1e-1
PHASE (°)
45
60
1e1
1e3
1e5
-225
1e7
FREQUENCY (Hz)
Figure 17. Uncompensated Loop Gain Frequency Response
Figure 17 shows the uncompensated loop gain in a worst-case scenario when the RHP zero is below the output
pole. This occurs at high duty cycles when the regulator is trying to boost the output voltage significantly. The
RHP zero adds 20dB/decade of gain while losing 45°/decade of phase, which places the crossover frequency
(when the gain is zero dB) extremely high because the gain only starts falling again due to the high-frequency
pole (not shown in Figure 17). The phase is below –180° at the crossover frequency, which means there is no
phase margin (180° + phase at crossover frequency) causing system instability. Even if the output pole is below
the RHP zero, the phase reaches –180° before the crossover frequency in most cases yielding instability.
LM3421/23
ILED
RHSP
HSP
High-Side
Sense Amplifier
CFS
VSNS
RSNS
RHSN
HSN
RFS
sets öP3
RCSH
Error Amplifier
CSH
1.24V
sets öP2
CCMP
RO
To PWM
Comparator
COMP
Figure 18. Compensation Circuitry
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Feature Description (continued)
To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the
crossover frequency. A simple compensator using a single capacitor at the COMP pin (CCMP) adds a dominant
pole to the system, which ensures adequate phase margin if placed low enough. At high duty cycles (as shown
in Figure 17), the RHP zero places extreme limits on the achievable bandwidth with this type of compensation.
However, because an LED driver is essentially free of output transients (except catastrophic failures open or
short), the dominant pole approach, even with reduced bandwidth, is usually the best approach. The dominant
compensation pole (ωP2) is determined by CCMP and the output resistance (RO) of the error amplifier (typically 5
MΩ) as demonstrated in Equation 16.
1
ZP2
6
5 u 10 u CCMP
(16)
It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate
switching noise and, in some cases, provide better gain margin. This pole can be placed across RSNS to filter the
ESL of the sense resistor at the same time. Figure 18 shows how the compensation is physically implemented in
the system.
The high-frequency pole (ωP3) can be calculated using Equation 17.
1
ZP3 =
RFS x CFS
(17)
The total system transfer function becomes:
§ s ·
¨1 ¸
¨ ZZ1¸
©
¹
T = TU0 x
§
s · §
s · §
s ·
¸ ¨
¸ ¨
¨1+
¸
¨ ZP1¸ x ¨1+ ZP2¸ x ¨1+ ZP3¸
¹ ©
¹ ©
©
¹
(18)
The resulting compensated loop gain frequency response shown in Figure 19 indicates that the system has
adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability.
90
80
öP2
45
60
20
0
0
GAIN
öZ1
-90
PHASE
öP3
-20
-40
-45
öP1
-135
60° Phase Margin
-180
-225
-60
-80
1e-1
PHASE (°)
GAIN (dB)
40
1e1
1e3
1e5
-270
1e7
FREQUENCY (Hz)
Figure 19. Compensated Loop Gain Frequency Response
8.3.9 Start-Up Regulator
The controller includes a high voltage, low dropout bias regulator. When power is applied, the regulator is
enabled and sources current into an external capacitor (CBYP) connected to the VCC pin. The recommended
bypass capacitance for the VCC regulator is 2.2 µF to 3.3 µF. The output of the VCC regulator is monitored by an
internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage and the
supply is also internally current limited. Figure 20 shows the typical start-up waveforms.
20
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Feature Description (continued)
VCMP
0.9V
0
tVCC
tCMP
tCO
t
Figure 20. Start-Up Waveforms
First, CBYP is charged to be above VCC UVLO threshold (approximately 4.2 V). The CVCC charging time (tVCC) can
be estimated using Equation 19.
t VCC =
4.2V
x CBYP = 168: x CBYP
25 mA
(19)
CCMP is then charged to 0.9 V over the charging time (tCMP), which can be estimated using Equation 20.
t CMP =
0.9V
x CCMP = 36 k: x CCMP
25 PA
(20)
Once CCMP = 0.9 V, the part starts switching to charge CO until the LED current is in regulation. The CO charging
time (tCO) can be roughly estimated using Equation 21.
t CO = CO x
VO
ILED
(21)
The system start-up time (tSU) is defined using Equation 22.
t SU = t VCC + t CMP + t CO
(22)
In some configurations, the start-up waveform overshoots the steady state COMP pin voltage. In this case, the
LED current and output voltage overshoots also, which can trip the overvoltage or protection, causing a race
condition. The easiest way to prevent this is to use a larger compensation capacitor (CCMP), thereby slowing
down the control loop.
8.3.10 Overvoltage Lockout (OVLO)
The LM3421 and LM3423 can be configured to detect an output (or input) overvoltage condition through the OVP
pin. The pin features a precision 1.24-V threshold with 23 µA (typical) of hysteresis current as shown in
Figure 21. When the OVLO threshold is exceeded, the GATE pin is immediately pulled low and a 23-µA current
source provides hysteresis to the lower threshold of the OVLO hysteretic band.
If the LEDs are referenced to a potential other than ground (floating), as in the buck-boost and buck
configuration, the output voltage (VO) should be sensed and translated to ground by using a single PNP as
shown in Figure 22.
The overvoltage turnoff threshold (VTURN-OFF) is defined:
Ground Referenced
§R + ROV 2·
¸
VTURN - OFF = 1.24V x ¨¨ OV1
¸
© R OV1 ¹
(23)
Floating
§0.5 x R OV1+ R OV2·
¸
VTURN - OFF = 1.24V x ¨¨
¸
R OV1
¹
©
(24)
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Feature Description (continued)
In the ground referenced configuration, the voltage across ROV2 is VO – 1.24 V whereas in the floating
configuration it is VO – 620 mV where 620 mV approximates VBE of the PNP.
The overvoltage hysteresis (VHYSO) is defined using Equation 25.
VHYSO = 23 PA x ROV2
(25)
LM3421/23
VO
23 PA
ROV2
OVP
OVLO
1.24V
ROV1
Figure 21. Overvoltage Protection Circuitry
LED+
ROV2
LM3421/23
LEDOVP
ROV1
Figure 22. Floating Output OVP Circuitry
The OVLO feature can cause some interesting results if the OVLO trip-point is set too close to VO. At turnon, the
converter has a modest amount of voltage overshoot before the control loop gains control of ILED. If the overshoot
exceeds the OVLO threshold, the controller shuts down, opening the dimming MOSFET. This isolates the LED
load from the converter and the output capacitance. The voltage then discharges very slowly through the HSP
and HSN pins until VO drops below the lower threshold, where the process repeats. This looks like the LEDs are
blinking at around 2 Hz. This mode can be escaped if the input voltage is reduced.
8.3.11 Input Undervoltage Lockout (UVLO)
The nDIM pin is a dual-function input that features an accurate 1.24-V threshold with programmable hysteresis
as shown in Figure 23. This pin functions as both the PWM dimming input for the LEDs and as a VIN UVLO.
When the pin voltage rises and exceeds the 1.24-V threshold, 23 µA (typical) of current is driven out of the nDIM
pin into the resistor divider providing programmable hysteresis.
22
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Feature Description (continued)
LM3421/23
VIN
23 PA
RUV2
RUV1
nDIM
RUVH
1.24V
UVLO
(optional)
Figure 23. UVLO Circuit
When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra series
resistor to set the hysteresis. This allows the standard resistor divider to have smaller resistor values minimizing
PWM delays due to a pulldown MOSFET at the nDIM pin (see PWM Dimming section). In general, at least 3 V of
hysteresis is preferable when PWM dimming, if operating near the UVLO threshold.
The turnon threshold (VTURN-ON) is defined using Equation 26.
§R UV1 + RUV2·
¸
¨
VTURN ON
- = 1. 24V x ¨
¸
© RUV1 ¹
(26)
The hysteresis (VHYS) is defined as follows:
8.3.11.1 UVLO Only
VHYS = 23 PA x RUV2
(27)
8.3.11.2 PWM Dimming and UVLO
§
R x (RUV1 + RUV2)·
¸
VHYS = 23 PA x ¨¨RUV2 + UVH
¸
RUV1
¹
©
(28)
When zero current shutdown and UVLO are implemented together, the EN pin can be used to escape UVLO.
The nDIM pin pulls up to VIN when EN is pulled low. Therefore, if VIN is within the UVLO hysteretic window when
EN is pulled high again, the controller starts-up even though VTURN-ON is not exceeded.
8.3.12 PWM Dimming
The active low nDIM pin can be driven with a PWM signal which controls the main N-channel FET and the
dimming FET (dimFET). The brightness of the LEDs can be varied by modulating the duty cycle of this signal.
LED brightness is approximately proportional to the PWM signal duty cycle, (that is, 30% duty cycle equals
approximately 30% LED brightness). This function can be ignored if PWM dimming is not required by using nDIM
solely as a VIN UVLO input as described in Input Undervoltage Lockout (UVLO) or by tying it directly to VCC or
VIN.
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Feature Description (continued)
Inverted
PWM
VIN
LM3421/23
DDIM
RUV2
RUVH
RUV1
nDIM
QDIM
Standard
PWM
Figure 24. PWM Dimming Circuit
STOPPED DD EDITING HERELM3421 and LM3423
Figure 24 shows how the PWM signal is applied to nDIM:
1. Connect the dimming MOSFET (QDIM) with the drain to the nDIM pin and the source to AGND. Apply an
external logic-level PWM signal to the gate of QDIM.
2. Connect the anode of a Schottky diode (DDIM) to the nDIM pin. Apply an inverted external logic-level PWM
signal to the cathode of the same diode.
The DDRV pin is a PWM output that follows the nDIM PWM input signal. When the nDIM pin rises, the DDRV pin
rises and the PWM latch reset signal is removed allowing the main MOSFET Q1 to turn on at the beginning of
the next clock set pulse. In boost and buck-boost topologies, the DDRV pin is used to control a N-channel
MOSFET placed in series with the LED load, while it would control a P-channel MOSFET in parallel with the load
for a buck topology.
The series dimFET opens the LED load, when nDIM is low, effectively speeding up the rise and fall times of the
LED current. Without any dimFET, the rise and fall times are limited by the inductor slew rate and dimming
frequencies above 1 kHz are impractical. Using the series dimFET, dimming frequencies up to 30 kHz are
achievable. With a parallel dimFET (buck topology), even higher dimming frequencies are achievable.
When using the PWM functionality in a boost regulator, the PWM signal can drive a ground referenced FET.
However, with buck-boost and buck topologies, level shifting circuitry is necessary to translate the PWM dim
signal to the floating dimFET as shown in Figure 25 and Figure 26. If high side dimming is necessary in a boost
regulator using the LM3423, level shifting can be added providing the polarity inverting DPOL pin is pulled low
(see LM3423 Only: DPOL, FLT, TIMR, and LRDY section) as shown in Figure 27.
When using a series dimFET to PWM dim the LED current, more output capacitance is always better. Typical
applications use a minimum of 40 µF for PWM dimming. For most applications, a capacitance of 40 µF provides
adequate energy storage at the output when the dimFET turns off and opens the LED load. Then when the
dimFET is turned back on, the capacitance helps source current into the load, improving the LED current rise
time.
A minimum on-time must be maintained in order for PWM dimming to operate in the linear region of its transfer
function. Because the controller is disabled during dimming, the PWM pulse must be long enough such that the
energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and
buck-boost regulators, the minimum dimming pulse length in seconds (tPULSE) is:
2 x ILED x VO X L1
tPULSE =
VIN2
(29)
Even maintaining a dimming pulse greater than tPULSE, preserving linearity at low dimming duty cycles is difficult.
24
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Feature Description (continued)
The second helpful modification is to remove the CFS capacitor and RFS resistor, eliminating the high-frequency
compensation pole. Typically, this does not affect stability, but it speeds up the response of the CSH pin,
specifically at the rising edge of the LED current when PWM dimming, thus improving the achievable linearity at
low dimming duty cycles.
LED+
LM3421/23
10:
5 k:
Q7
100 nF
Q2
VCC
Q6
Q4
RSNS
100 pF
10V
VIN
500:
DDRV
Figure 25. Buck-boost Level-Shifted PWM Circuit
LM3421/23
RSNS
100
k:
10V
Q2
100 nF
DDRV
Figure 26. Buck Level-Shifted PWM Circuit
VO
LM3421/23
RSNS
DPOL
100
k:
10V
Q2
VCC
Q6
100 pF
10 k:
DDRV
Figure 27. Boost Level-Shifted PWM Circuit
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Feature Description (continued)
8.3.13 LM3423 Only: DPOL, FLT, TIMR, and LRDY
The LM3423 has four additional pins: DPOL, FLT, TIMR, and LRDY. The DPOL pin is simply used to invert the
DDRV polarity . If DPOL is left open, then it is internally pulled high and the polarity is correct for driving a series
N-channel dimFET. If DPOL is pulled low then the polarity is correct for using a series P-channel dimFET in highside dimming applications. For a parallel P-channel dimFET, as used in the buck topology, leave DPOL open for
proper polarity.
The additional TIMR and FLT pins can be used in conjunction with an input disconnect MOSFET switch as
shown in Figure 28 to protect the module from various fault conditions.
A fault is detected and an 11.5 µA (typical) current is sourced from the TIMR pin whenever any one of the
following conditions exists.
• LED current is above regulation by more than 30%.
• OVLO has engaged.
• Thermal shutdown has engaged.
An external capacitor (CTMR) from TIMR to AGND programs the fault filter time as follows:
t FLT x 11.5 PA
CTMR =
1.24V
(30)
When the voltage on the TIMR pin reaches 1.24 V, the device is latched off and the N-channel MOSFET opendrain FLT pin transitions to a high impedance state. The controller immediatly pulls the TIMR pin to ground
(resets) if the fault condition is removed at any point during the filter period. Otherwise, if the timer expires, the
fault remains latched until one of these situations occurs:
• The EN pin is pulled low long enough for the VCC pin to drop below 4.1 V (approximately 200 ms) or
• the TIMR pin is pulled to ground or
• a complete power cycle occurs
When using the EN and OVP pins in conjunction with the RPD pulldown pin, a race condition exists when exiting
the disabled (EN low) state. When disabled, controller pulls up the OVP pin to the output voltage because the
RPD pulldown is disabled, and this appears as if it is a real OVLO condition. The timer pin immediately rises and
latches the controller to the fault state. To protect against this behavior, a minimum timer capacitor (CTMR = 220
pF) should be used. If fault latching is not required, short the TMR pin to AGND, which disables the FLT flag
function.
The LM3423 also includes an LED Ready (LRDY) flag to notify the system that the LEDs are in proper
regulation. The N-channel MOSFET open-drain LRDY pin is pulled low whenever any of the following conditions
are met:
1. VCC UVLO has engaged.
2. LED current is below regulation by more than 20%.
3. LED current is above regulation by more than 30%.
4. Overvoltage protection has engaged
5. Thermal shutdown has engaged.
6. A fault has latched the device off.
The LRDY pin is pulled low during start-up of the device and remains low until the LED current is in regulation.
26
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Feature Description (continued)
VIN
VSW
LM3421/23
FLT
VIN
High = LED in regulation
LRDY
TIMR
Figure 28. Fault Detection and LED Status Circuit
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Inductor
The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy
is stored in the inductor and transfered to the load in different ways (as an example, buck-boost operation is
detailed in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the
switching subinterval (tON or tOFF) determines the inductor current ripple (ΔiL-PP). In the design process, L1 is
chosen to provide a desired ΔiL-PP. For a buck regulator the inductor has a direct connection to the load, which is
good for a current regulator. This requires little to no output capacitance therefore ΔiL-PP is basically equal to the
LED ripple current ΔiLED-PP. However, for boost and buck-boost regulators, there is always an output capacitor
which reduces ΔiLED-PP; therefore, the inductor ripple can be larger than in the buck regulator case where output
capacitance is minimal or completely absent.
In general, ΔiLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED).
Therefore, for the buck regulator with no output capacitance, ΔiL-PP should also be less than 40% of ILED. For the
boost and buck-boost topologies, ΔiL-PP can be much higher depending on the output capacitance value.
However, ΔiL-PP is suggested to be less than 100% of the average inductor current (IL) to limit the RMS inductor
current.
L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable
RMS inductor current (IL-RMS).
9.1.2 LED Dynamic Resistance
When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus RSNS.
LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the
forward voltage of a single LED (VLED) by the forward current (ILED) leads to an incorrect calculation of the
dynamic resistance of a single LED (rLED). The result can be 5 to 10 times higher than the true rLED value.
Figure 29. Dynamic Resistance
Obtaining rLED is accomplished by referring to the manufacturer's LED I-V characteristic. It can be calculated as
the slope at the nominal operating point as shown in Figure 29. For any application with more than 2 series
LEDs, RSNS can be neglected allowing rD to be approximated as the number of LEDs multiplied by rLED.
28
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Application Information (continued)
9.1.3 Output Capacitor
For boost and buck-boost regulators, the output capacitor (CO) provides energy to the load when the recirculating
diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a buck topology simplys
reduce the LED current ripple (ΔiLED-PP) below the inductor current ripple (ΔiL-PP). In all cases, CO is sized to
provide a desired ΔiLED-PP. As mentioned in the Inductor section, ΔiLED-PP is recommended by manufacturers to be
less than 40% of the average LED current (ILED).
CO should be carefully chosen to account for derating due to temperature and operating voltage. It must also
have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current
rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested.
9.1.4 Input Capacitors
The input capacitance (CIN) provides energy during the discontinuous portions of the switching period. For buck
and buck-boost regulators, CIN provides energy during tON and during tOFF, the input voltage source charges up
CIN with the average input current (IIN). For boost regulators, CIN only needs to provide the ripple current due to
the direct connection to the inductor. CIN is selected given the maximum input voltage ripple (ΔvIN-PP) which can
be tolerated. ΔvIN-PP is suggested to be less than 10% of the input voltage (VIN).
An input capacitance at least 100% greater than the calculated CIN value is recommended to account for derating
due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to
minimize the large current draw from the input voltage source during the rising transition of the LED current
waveform.
The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the
best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R
dielectric rating is suggested.
For most applications, TI recommends bypassing the VIN pin with an 0.1 µF ceramic capacitor placed as close as
possible to the pin. In situations where the bulk input capacitance may be far from the controller, a 10-Ω series
resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150-kHz filter to
eliminate undesired high-frequency noise.
9.1.5 Main MOSFET / Dimming MOSFET
The controller requires an external N-channel FET (Q1) as the main power MOSFET for the switching regulator.
TI recommends Q1 have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe
operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the
switch node due to the diode parasitic capacitance and the lead inductance. TI recommends the current rating be
at least 10% higher than the average transistor current. The power rating is then verified by calculating the power
loss given the RMS transistor current and the N-channel FET on-resistance (RDS-ON).
When PWM dimming, the controller requires another MOSFET (Q2) placed in series (or parallel for a buck
regulator) with the LED load. This MOSFET should have a voltage rating greater than the output voltage (VO)
and a current rating at least 10% higher than the nominal LED current (ILED) . The power rating is simply RDS-ON
multiplied by ILED, assuming 100% dimming duty cycle (continuous operation) occurs.
For most applications, choose an N-channel FET that minimizes total gate charge (Qg) when fSW is high. It that is
not possible. minimize the on-resistance RDS(on) to minimize the dominant power losses in the system.
Frequently, higher current N-channel FETs in larger packages yield better thermal performance.
9.1.6 Re-Circulating Diode
The controller requires a recirculating diode (D1) to carry the inductor current during the off time (tOFF). The most
efficient choice for D1 is a Schottky diode due to low forward voltage drop and near-zero reverse recovery time.
Similar to Q1, TI recommends D1 have a voltage rating at least 15% higher than the maximum transistor voltage
to ensure safe operation during the ringing of the switch node and a current rating at least 10% higher than the
average diode current. The power rating is verified by calculating the power loss through the diode. This is
accomplished by checking the typical diode forward voltage from the I-V curve on the product data sheet and
multiplying by the average diode current. In general, higher current diodes have a lower forward voltage and
come in better performing packages minimizing both power losses and temperature rise.
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Application Information (continued)
9.1.7 Boost Inrush Current
When configured as a boost converter, there is a phantom power path comprised of the inductor, the output
diode, and the output capacitor. This path causes two things to happen when power is applied:
1. a very large inrush of current to charge the output capacitor
2. the energy stored in the inductor during this inrush collects in the output capacitor, charging it to a higher
potential than the input voltage
Depending on the state of the EN pin, the output capacitor discharges by:
1. EN < 1.3 V: no discharge path (leakage only).
2. EN > 1.3 V, the OVP divider resistor path, if present, and 10 µA into each of the HSP & HSN pins.
In applications using the OVP divider and with EN > 1.3 V, the output capacitor voltage can charge higher than
VTURN-OFF. In this situation, the FLT pin (LM3423 only) is open and the PWM dimming MOSFET is turned off.
This condition (the system appearing disabled) can persist for an undesirably long time. Possible solutions to this
condition include:
• Add an inrush diode from VIN to the output as shown in Figure 30.
• Add an NTC thermistor in series with the input to prevent the inrush from overcharging the output capacitor
too high.
• Use a current limited source supply.
• Raise the OVP threshold.
Boost Inrush Diode
L1
D1
VIN
VO
Q1
Figure 30. Boost Topology with Inrush Diode
9.1.8 Switching Frequency
An external resistor (RT) connected between the RCT pin and the switch node (where D1, Q1, and L1 connect),
in combination with a capacitor (CT) between the RCT and AGND pins, sets the off-time (tOFF) as shown in
Figure 31. For boost and buck-boost topologies, the VIN proportionality ensures a virtually constant switching
frequency (fSW).
For a buck topology, RT and CT are also used to set tOFF, however the iinput voltage (VIN) proportionality does
not ensure a constant switching frequency. Instead, constant ripple operation can be achieved. Changing the
connection of RT in Figure 31 from VSW to VIN provides a constant ripple over varying VIN. Adding a PNP
transistor as shown in Figure 32 provides constant ripple over varying VO.
The switching frequency is defined:
Buck (Constant Ripple vs. VIN)
fSW =
25 x ( VIN - VO )
RT x CT X VIN
(31)
Buck (Constant Ripple vs. VO)
25 x (VIN x VO - VO )
2
fSW =
2
RT x C T x VIN
(32)
Boost and Buck-boost
30
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Application Information (continued)
fSW =
25
R T x CT
(33)
For all topologies, the CT capacitor is recommended to be 1 nF and should be located very close to the LM34xxQ1.
VIN
VSW
LM3421/23
RT
VIN/25
RSNS
Start tON
RCT
RT
LM3421/23
CT
VIN/25
Reset timer
LED-
Start tON
RCT
CT
Reset timer
Figure 31. Off-timer Circuitry for Boost and Buckboost Regulators
Figure 32. Off-timer Circuitry for Buck Regulators
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9.2 Typical Applications
9.2.1 Basic Topology Schematics
L1
D1
VIN
1
CIN
2
LM3421
VIN
HSN
HSP
EN
16
RHSN
15
RHSP
CFS
RSNS
RFS
RT
CCMP
RCSH
3
4
5
COMP
RPD
CSH
IS
RCT
VCC
14
13
CO
ROV2
COV
ROV1
ILED
12
CBYP
CT
6
AGND
GATE
OVP
PGND
11
Q1
RUV2
7
10
RLIM
DAP
RUVH
RUV1
Q3
8
nDIM
DDRV
9
Q2
PWM
Figure 33. Boost Regulator (VIN < VO)
32
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Typical Applications (continued)
VIN
1
CIN
2
VIN
LM3421
HSN
HSP
EN
16
RHSN
15
RHSP
CFS
RSNS
RFS
RT
CCMP
3
COMP
RPD
CO
14
RPU
RCSH
4
CSH
IS
D2
13
Q2
DIM
5
RCT
VCC
ROV2
ILED
D1
12
L1
CBYP
CT
6
AGND
GATE
OVP
PGND
Q5
11
Q1
RUV2
7
10
RLIM
DAP
RUVH
8
nDIM
DDRV
9
DIM
CDIM
RUV1
Q3
PWM
COV
ROV1
Figure 34. Buck Regulator (VIN > VO)
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Typical Applications (continued)
L1
D1
VIN
ILED
1
CIN
2
VIN
LM3421
HSN
HSP
EN
16
RHSN
15
RHSP
DIM
CO
Q2
CFS
RSNS
VIN
RFS
RT
CCMP
RCSH
3
4
COMP
RPD
CSH
IS
14
RPU
13
Q7
DIM
5
RCT
VCC
12
Q6
Q4
CBYP
CT
6
GATE
AGND
D2
11
ROV2
CG
Q5
Q1
VIN
RUV2
7
PGND
OVP
10
RSER
RLIM
DAP
RUVH
RUV1
Q3
8
nDIM
DDRV
9
PWM
COV
ROV1
Figure 35. Buck-Boost Regulator
34
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Typical Applications (continued)
9.2.1.1 Design Requirements
Number of series LEDs: N
Single LED forward voltage: VLED
Single LED dynamic resistance: rLED
Nominal input voltage: VIN
Input voltage range: VIN-MAX, VIN-MIN
Switching frequency: fSW
Current sense voltage: VSNS
Average LED current: ILED
Inductor current ripple: ΔiL-PP
LED current ripple: ΔiLED-PP
Peak current limit: ILIM
Input voltage ripple: ΔvIN-PP
Output OVLO characteristics: VTURN-OFF, VHYSO
Input UVLO characteristics: VTURN-ON, VHYS
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Operating Point
Given the number of series LEDs (N), the forward voltage (VLED) and dynamic resistance (rLED) for a single LED,
solve for the nominal output voltage (VO) and the nominal LED string dynamic resistance (rD):
VO = N x VLED
(34)
rD = N x rLED
(35)
Solve for the ideal nominal duty cycle (D):
Buck:
D=
VO
VIN
(36)
VO - VIN
VO
(37)
Boost:
D=
Buck-Boost:
D=
VO
VO + VIN
(38)
Using the same equations, find the minimum duty cycle (DMIN) using maximum input voltage (VIN-MAX) and the
maximum duty cycle (DMAX) using the minimum input voltage (VIN-MIN). Also, remember that D' = 1 - D.
9.2.1.2.2 Switching Frequency
Set the switching frequency (fSW) by assuming a CT value of 1 nF and solving for RT:
Buck (Constant Ripple vs. VIN)
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Typical Applications (continued)
RT =
25 x ( VIN - VO )
fSW x CT X VIN
(39)
Buck (Constant Ripple vs. VO)
2
RT =
25 x (VIN x VO - VO
fSW x C T x
)
2
VIN
(40)
Boost and Buck-Boost
25
RT =
fSW x C T
(41)
9.2.1.2.3 Average LED Current
For all topologies, set the average LED current (ILED) knowing the desired current sense voltage (VSNS) and
solving for RSNS:
VSNS
RSNS =
ILED
(42)
If the calculated RSNS is too far from a desired standard value, then VSNS requires adjustment to obtain a
standard value.
Setup the suggested signal current of 100 µA by assuming RCSH = 12.4 kΩ and solving for RHSP:
ILED x RCSH x RSNS
RHSP =
1.24V
(43)
If the calculated RHSP is too far from a desired standard value, then RCSH can be adjusted to obtain a standard
value.
9.2.1.2.4 Inductor Ripple Current
Set the nominal inductor ripple current (ΔiL-PP) by solving for the appropriate inductor (L1):
Buck
L1
(VIN VO ) u D
'iL PP u fSW
(44)
Boost and Buck-Boost
VIN u D
L1
'iL PP u fSW
(45)
To set the worst case inductor ripple current, use VIN-MAX and DMIN when solving for L1.
The minimum allowable inductor RMS current rating (IL-RMS) can be calculated as:
Buck
IL-RMS = ILED x
1 § 'IL-PP·
x
1+
¸
12 ¨ ILED
©
2
¹
(46)
Boost and Buck-Boost
1 §'IL-PP x D' ·
x
x 1+
IL-RMS =
¸
12 ¨ ILED
D'
ILED
©
36
2
¹
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Typical Applications (continued)
9.2.1.2.5 LED Ripple Current
Set the nominal LED ripple current (ΔiLED-PP), by solving for the output capacitance (CO):
Buck
CO =
'iL - PP
8 x fSW x rD x 'iLED - PP
(48)
Boost and Buck-boost
ILED u D
CO
rD u 'iLED PP u fSW
(49)
To set the worst case LED ripple current, use DMAX when solving for CO. Remember, when PWM dimming, TI
recommends using a minimum of 40 µF of output capacitance to improve performance.
The minimum allowable RMS output capacitor current rating (ICO-RMS) can be approximated:
Buck
ICO - RMS =
üiLED - PP
12
(50)
Boost and Buck-boost
ICO-RMS = ILED x
DMAX
1-DMAX
(51)
9.2.1.2.6 Peak Current Limit
Set the peak current limit (ILIM) by solving for the transistor path sense resistor (RLIM):
R LIM =
245 mV
ILIM
(52)
9.2.1.2.7 Loop Compensation
Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the
necessary loop compensation can be determined.
First, the uncompensated loop gain (TU) of the regulator can be approximated:
Buck
TU = TU0 x
1
§
s ·
¨1+
¸
¨ ZP1 ¸
©
¹
(53)
Boost and Buck-Boost
§
s ·
¸
¨1 ¨ ZZ1 ¸
¹
©
TU = TU0 x
§
s ·
¨1+
¸
¨ ZP1 ¸
©
¹
(54)
Where the pole (ωP1) is approximated:
3
Buck
ZP1 =
1
rD x CO
(55)
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Typical Applications (continued)
3
Boost
2
rD x CO
ZP1 =
(56)
3
Buck-Boost
1+ D
rD x CO
ZP1 =
(57)
And the RHP zero (ωZ1) is approximated:
Boost
rD x Dc2
ZZ1 =
L1
(58)
Buck-Boost
ZZ1 =
rD x Dc2
D x L1
(59)
And the uncompensated DC loop gain (TU0) is approximated:
Buck
TU0 =
500V x RCSH x RSNS
620V
=
RHSP x R LIM
ILED x RLIM
(60)
Dc x 500V x RCSH x RSNS
Dc x 310V
=
2 x RHSP x R LIM
ILED x R LIM
(61)
Boost
TU0 =
Buck-Boost
Dc x 500V x RCSH x RSNS
Dc x 620V
TU0 =
=
(1+ D) x RHSP x R LIM (1+ D) x ILED x R LIM
(62)
For all topologies, the primary method of compensation is to place a low frequency dominant pole (ωP2), which
ensures that there is ample phase margin at the crossover frequency. This is accomplished by placing a
capacitor (CCMP) from the COMP pin to AGND, which is calculated according to the lower value of the pole and
the RHP zero of the system (shown as a minimizing function):
min(Z P1, ZZ1)
ZP2 =
5 x TU0
(63)
CCMP
1
ZP2 u 5 u 106
(64)
If analog dimming is used, CCMP should be approximately 4× larger to maintain stability as the LEDs are dimmed
to zero.
A high-frequency compensation pole (ωP3) can be used to attenuate switching noise and provide better gain
margin. Assuming RFS = 10 Ω, CFS is calculated according to the higher value of the pole and the RHP zero of
the system (shown as a maximizing function):
ZP3 = max (ZP1, ZZ1) x 10
CFS
(65)
1
10 u ZP3
(66)
The total system loop gain (T) can then be written as:
38
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Typical Applications (continued)
Buck
T = TU0 x
1
§
s ·
¨1+
¸
¨ ZP1¸ x
©
¹
§
s · §
s ·
¨1+
¸ ¨
¸
¨ ZP2¸ x ¨1+ ZP3¸
©
¹ ©
¹
(67)
§ s ·
¨1 ¸
¨ ZZ1¸
©
¹
T = TU0 x
·
§
§
s
s · §
s ·
¸ ¨
¸ ¨
¨1+
¸
¨ ZP1¸ x ¨1+ ZP2¸ x ¨1+ ZP3¸
¹ ©
¹ ©
©
¹
(68)
Boost and Buck-Boost
9.2.1.2.8 Input Capacitance
Set the nominal input voltage ripple (ΔvIN-PP) by solving for the required capacitance (CIN):
Buck
ILED x (1 - D) x D
CIN =
'VIN-PP x fSW
(69)
Boost
CIN =
'iL-PP
8 x 'VIN-PP x fSW
(70)
Buck-Boost
CIN =
ILED x D
'VIN-PP x fSW
(71)
Use DMAX to set the worst case input voltage ripple, when solving for CIN in a buck-boost regulator and DMID = 0.5
when solving for CIN in a buck regulator.
The minimum allowable RMS input current rating (ICIN-RMS) can be approximated:
Buck
ICIN - RMS = ILED x DMID x (1-DMID)
(72)
Boost
ICIN-RMS =
'iL-PP
12
(73)
Buck-Boost
ICIN-RMS = ILED x
9.2.1.2.9
DMAX
1-DMAX
(74)
N-channel FET
The N-channel FET voltage rating should be at least 15% higher than the maximum N-channel FET drain-tosource voltage (VT-MAX):
Buck
VT - MAX = VIN - MAX
(75)
Boost
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Typical Applications (continued)
VT - MAX = VO
(76)
Buck-Boost
VT - MAX = VIN - MAX + VO
(77)
The current rating should be at least 10% higher than the maximum average N-channel FET current (IT-MAX):
Buck
IT-MAX = DMAX x ILED
(78)
Boost and Buck-Boost
DMAX
IT-MAX =
xI
1 - DMAX LED
(79)
Approximate the nominal RMS transistor current (IT-RMS) :
Buck
IT- RMS = ILED x D
(80)
9.2.1.2.9.1 Boost and Buck-Boost
IT - RMS =
ILED
x D
Dc
(81)
Given an N-channel FET with on-resistance (RDS-ON), solve for the nominal power dissipation (PT):
2
PT = IT - RMS x R DSON
(82)
9.2.1.2.10 Diode
The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (VRD-MAX):
Buck
VRD-MAX = VIN-MAX
(83)
Boost
VRD-MAX = VO
(84)
Buck-Boost
VRD-MAX = VIN-MAX + VO
(85)
The current rating should be at least 10% higher than the maximum average diode current (ID-MAX):
Buck
ID-MAX = (1 - DMIN) x ILED
(86)
Boost and Buck-Boost
ID-MAX = ILED
(87)
Replace DMAX with D in the ID-MAX equation to solve for the average diode current (ID). Given a diode with forward
voltage (VFD), solve for the nominal power dissipation (PD):
PD = ID x VFD
40
(88)
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Typical Applications (continued)
9.2.1.2.11 Output OVLO
For boost and buck-boost regulators, output OVLO is programmed with the turn-off threshold voltage (VTURN-OFF)
and the desired hysteresis (VHYSO). To set VHYSO, solve for ROV2:
VHYSO
ROV2 =
23 PA
(89)
To set VTURN-OFF, solve for ROV1:
Boost
ROV1 =
1.24V x ROV2
VTURN - OFF - 1.24V
(90)
Buck-Boost
R OV1 =
1.24V x R OV2
VTURN - OFF - 620 mV
(91)
A small filter capacitor (COVP = 47 pF) should be added from the OVP pin to ground to reduce coupled switching
noise.
9.2.1.2.12 Input UVLO
For all topologies, input UVLO is programmed with the turnon threshold voltage (VTURN-ON) and the desired
hysteresis (VHYS).
Method 1: If no PWM dimming is required, a two resistor network can be used. To set VHYS, solve for RUV2:
VHYS
RUV2 =
23 PA
(92)
To set VTURN-ON, solve for RUV1:
RUV1 =
1.24V x RUV2
VTURN - ON - 1.24V
(93)
Method 2: If PWM dimming is required, a three resistor network is suggested. To set VTURN-ON, assume RUV2 =
10 kΩ and solve for RUV1 as in Method 1. To set VHYS, solve for RUVH:
RUVH =
R UV1 x (VHYS - 23 PA x RUV2)
23 PA x (RUV1 + R UV2)
(94)
9.2.1.2.13 PWM Dimming Method
PWM dimming can be performed several ways:
Method 1: Connect the dimming MOSFET (Q3) with the drain to the nDIM pin and the source to AGND. Apply an
external PWM signal to the gate of QDIM. A pulldown resistor may be necessary to properly turn off Q3.
Method 2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to the
cathode of the same diode.
The DDRV pin should be connected to the gate of the dimFET with or without level-shifting circuitry as described
in the PWM Dimming section. The dimFET should be rated to handle the average LED current and the nominal
output voltage.
9.2.1.2.14 Analog Dimming Method
Analog dimming can be performed several ways:
Method 1: Place a potentiometer in series with the RCSH resistor to dim the LED current from the nominal ILED to
near zero.
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Typical Applications (continued)
Method 2: Connect a controlled current source as detailed in the Analog Dimming section to the CSH pin.
Increasing the current sourced into the CSH node decreases the LEDs from the nominal ILED to zero current in
the same manner as the thermal foldback circuit.
42
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Typical Applications (continued)
9.2.2 LM3421 Buck-Boost Application
10V ± 70V
VIN
L1
D1
1
CIN
RT
CCMP
RCSH
2
3
4
5
VIN
LM3421
HSN
EN
HSP
COMP
RPD
CSH
IS
RCT
VCC
16
RHSN
15
RHSP
1A
ILED
CO
14
13
CFS
RSNS
VIN
12
RFS
CBYP
CT
6
AGND
GATE
OVP
PGND
11
Q1
RUV2
7
10
ROV2
RLIM
DAP
8
nDIM
DDRV
9
RUV1
VIN
COV
Q2
ROV1
Figure 36. LM3421 Buck-Boost Application
9.2.2.1 Design Requirements
N=6
VLED = 3.5 V
rLED = 325 mΩ
VIN = 24 V
VIN-MIN = 10 V
VIN-MAX = 70 V
fSW = 500 kHz
VSNS = 100 mV
ILED = 1 A
ΔiL-PP = 700 mA
ΔiLED-PP = 12 mA
ΔvIN-PP = 100 mV
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Typical Applications (continued)
ILIM = 6 A
VTURN-ON = 10 V
VHYS = 3 V
VTURN-OFF = 40 V
VHYSO = 10 V
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Operating Point
Solve for VO and rD:
VO = N x VLED = 6 x 3.5V = 21V
(95)
rD = N x rLED = 6 x 325 m: = 1. 95:
(96)
Solve for D, D', DMAX, and DMIN:
D=
VO
21V
=
= 0.467
VO + VIN 21V + 24V
(97)
D' = 1 - D = 1 - 0. 467 = 0. 533
DMIN =
DMAX =
(98)
VO
21V
=
= 0.231
VO + VIN-MAX 21V + 70V
VO
21V
=
= 0.677
VO + VIN-MIN 21V + 10V
(99)
(100)
9.2.2.2.2 Switching Frequency
Assume CT = 1 nF and solve for RT:
RT =
25
25
=
= 50 k:
fSW x CT 500 kHz x 1 nF
(101)
The closest standard resistor is 49.9 kΩ; therefore, fSW is:
fSW =
25
25
=
= 501 kHz
RT x CT 49.9 k: x 1 nF
The chosen component from step 2 is:
CT = 1 nF
RT = 49.9 k:
(102)
(103)
9.2.2.2.3 Average LED Current
Solve for RSNS:
V
100 mV
RSNS = SNS =
= 0.1:
ILED
1A
(104)
Assume RCSH = 12.4 kΩ and solve for RHSP:
ILED x RCSH x RSNS 1A x 12.4 k : x 0.1:
RHSP =
=
= 1.0 k:
1.24V
1.24V
(105)
44
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Typical Applications (continued)
The closest standard resistor for RSNS is actually 0.1 Ω and for RHSP is actually 1 kΩ; therefore, ILED is:
1.24V x RHSP 1.24V x 1.0 k:
ILED =
=
= 1.0A
R SNS x R CSH 0.1: x 12.4 k:
(106)
The chosen components from step 3 are:
RS NS = 0.1:
R CSH = 12.4 k :
RHSP = RHSN = 1 k:
(107)
9.2.2.2.4 Inductor Ripple Current
Solve for L1:
L1 =
VIN x D
24V x 0. 467
=
= 32 PH
'iL- PP x fSW 700 mA x 501 kHz
(108)
The closest standard inductor is 33 µH; therefore, ΔiL-PP is:
'iL- PP =
VIN x D
24V x 0. 467
= 678 mA
=
L1 x fSW 33 PH x 501 kHz
(109)
Determine minimum allowable RMS current rating:
2
I
1 §¨ 'iL - PP x Dc·¸
x
IL - RMS = LED x 1+
12 ¨© ILED ¸¹
Dc
2
IL - RMS =
1 §678 mA x 0.533· 1.89A
1A
x¨
¸¸ =
x 1+
12 ¨©
1A
0. 533
¹
(110)
The chosen component from step 4 is:
L1 = 33 PH
(111)
9.2.2.2.5 Output Capacitance
Solve for CO:
CO =
CO =
ILED x D
rD x 'iLED- PP x fSW
1A x 0. 467
= 39.8 PF
1.95: x 12 mA x 5 01 kHz
(112)
The closest capacitance totals 40 µF; therefore, ΔiLED-PP is:
'iLED- PP =
ILED x D
rD x CO x fSW
'iLED- PP =
1A x 0. 467
= 12 mA
1.95 : x 40 PF x 5 01 kHz
(113)
Determine minimum allowable RMS current rating:
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Typical Applications (continued)
DMAX
0.677
= 1.45A
= 1A x
1- DMAX
1- 0.677
ICO- RMS = ILED x
(114)
The chosen components from step 5 are:
CO = 4 x 10 PF
(115)
9.2.2.2.6 Peak Current Limit
Solve for RLIM:
RLIM =
245 mV 245 mV
=
= 0.041:
ILIM
6A
(116)
The closest standard resistor is 0.04 Ω; therefore, ILIM is:
ILIM =
245 mV 245 mV
=
= 6.13A
RLIM
0.04 :
(117)
The chosen component from step 6 is:
RLIM = 0.04:
(118)
9.2.2.2.7 Loop Compensation
ωP1 is approximated:
rad
1.467
1+ D
ZP1 =
=
= 19 k
sec
rD x CO 1.95: x 40 PF
(119)
ωZ1 is approximated:
rD x Dc2 1.95: x 0.5332
rad
=
= 36k
D x L1 0.467 x 33 PH
sec
(120)
TU0 is approximated:
0.533 x 620V
Dc x 620V
TU0 =
=
= 5630
1
.
467
x 1A x 0.04:
(1+ D) x ILED x R LIM
(121)
ZZ1 =
To ensure stability, calculate ωP2:
ZP2 =
min(ZP1, ZZ1)
5 x TU0
rad
sec
rad
=
=
= 0. 675
sec
5 x 5630 5 x 5630
ZP1
19k
(122)
Solve for CCMP:
CCMP
1
6
ZP2 u 5 u 10 :
1
rad
0.675
u 5 u 106 :
sec
0.3 PF
(123)
To attenuate switching noise, calculate ωP3:
ZP3 = (max ZP1, ZZ1) x 10 = ZZ1 x 10
rad
rad
ZP3 = 36k sec x 10 = 360k sec
(124)
Assume RFS = 10 Ω and solve for CFS:
46
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Typical Applications (continued)
CFS =
1
=
10: x ZP3
1
10: x 360k
rad
sec
= 0.28 PF
(125)
The chosen components from step 7 are:
CCMP = 0.33 PF
RFS = 10:
CFS = 0.27PF
(126)
9.2.2.2.8 Input Capacitance
Solve for the minimum CIN:
CIN =
ILED x D
1A x 0. 467
=
= 9.27 PF
'vIN- PP x fSW 100 mV x 504 kHz
(127)
To minimize power supply interaction a 200% larger capacitance of approximately 20 µF is used, therefore the
actual ΔvIN-PP is much lower. Because high voltage ceramic capacitor selection is limited, four 4.7-µF X7R
capacitors are chosen.
Determine minimum allowable RMS current rating:
IIN- RMS = ILED x
DMAX
0.677
= 1.45A
= 1A x
1- DMAX
1- 0.677
(128)
The chosen components from step 8 are:
CIN = 4 x 4.7 PF
9.2.2.2.9
(129)
N-channel FET
Determine minimum Q1 voltage rating and current rating:
VT - MAX = VIN - MAX + VO = 70V + 21V = 91V
IT- MAX =
(130)
0. 677
x 1A = 2.1A
1- 0.677
(131)
A 100-V N-channel FET is chosen with a current rating of 32 A due to the low RDS-ON = 50 mΩ. Determine IT-RMS
and PT:
IT - RMS =
ILED
1A
x D=
x 0.467 = 1. 28A
c
0. 533
D
(132)
2
PT = IT- RMS x RDSON = 1. 28A2 x 50 m: = 82 mW
(133)
The chosen component from step 9 is:
Q1 o 32A, 100V, DPAK
(134)
9.2.2.2.10 Diode
Determine minimum D1 voltage rating and current rating:
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Typical Applications (continued)
VRD - MAX = VIN - MAX + VO = 70V + 21V = 91V
(135)
ID - MAX = ILED = 1A
(136)
A 100-V diode is chosen with a current rating of 12 A and VDF = 600 mV. Determine PD:
PD = ID x VFD = 1A x 600 mV = 600 mW
(137)
The chosen component from step 10 is:
D1 o 12A, 100V, DPAK
(138)
9.2.2.2.11 Input UVLO
Solve for RUV2:
R UV2 =
VHYS
3V
=
= 130 k:
23 P A 23 PA
(139)
The closest standard resistor is 130 kΩ; therefore, VHYS is:
VHYS = RUV2 x 23 P A = 130 k: x 23 P A = 2.99V
(140)
Solve for RUV1:
R UV1 =
1.24V x R UV2
1.24V x 130 k:
=
= 18.4 k:
10V -1.24V
VTURN - ON - 1.24V
(141)
The closest standard resistor is 18.2 kΩ, making VTURN-ON:
VTURN - ON =
1.24V x (R UV1 + R UV2)
R UV1
VTURN- ON =
1.24V x (18.2 k: + 130 k:)
= 10.1V
18.2 k:
(142)
The chosen components from step 11 are:
RUV1 = 18.2 k:
RUV2 = 130 k:
(143)
9.2.2.2.12 Output OVLO
Solve for ROV2:
ROV2 =
VHYSO
10V
=
= 435 k:
23 P A 23 P A
(144)
The closest standard resistor is 432 kΩ; therefore, VHYSO is:
VHYSO = ROV2 x 23 PA = 432 k: x 23 PA = 9.94V
(145)
Solve for ROV1:
R OV1 =
1.24V x ROV2
1.24V x 432 k:
=
= 13.6 k:
VTURN - OFF - 0.62V
40V - 0.62V
(146)
The closest standard resistor is 13.7 kΩ, making VTURN-OFF:
48
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Typical Applications (continued)
VTURN - OFF =
1.24V x (0.5 x R OV1 + R OV2)
R OV1
VTURN- OFF =
1.24V x ( 0.5 x 13.7 k: + 432 k:)
= 39.7V
13.7 k:
(147)
The chosen components from step 12 are:
ROV1 = 13.7 k:
ROV2 = 432 k:
(148)
Table 2. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3421
Buck-boost controller
TI
LM3421MH
1
CBYP
2.2-µF X7R 10% 16V
MURATA
GRM21BR71C225KA12L
1
CCMP
0.33-µF X7R 10% 25V
MURATA
GRM21BR71E334KA01L
1
CFS
0.27-µF X7R 10% 25V
MURATA
GRM21BR71E274KA01L
4
CIN
4.7-µF X7R 10% 100V
TDK
C5750X7R2A475K
4
CO
10-µF X7R 10% 50V
TDK
C4532X7R1H106K
1
COV
47-pF COG/NPO 5% 50V
AVX
08055A470JAT2A
1
CT
1000-pF COG/NPO 5% 50V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 100 V 12 A
VISHAY
12CWQ10FNPBF
1
L1
33 µH 20% 6.3 A
COILCRAFT
MSS1278-333MLB
1
Q1
NMOS 100 V 32 A
FAIRCHILD
FDD3682
1
Q2
PNP 150 V 600 mA
FAIRCHILD
MMBT5401
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.04 Ω 1% 1 W
VISHAY
WSL2512R0400FEA
1
ROV1
13.7 kΩ 1%
VISHAY
CRCW080513K7FKEA
1
ROV2
432 kΩ 1%
VISHAY
CRCW0805432KFKEA
1
RSNS
0.1 Ω 1% 1 W
VISHAY
WSL2512R1000FEA
1
RT
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RUV1
18.2 kΩ 1%
VISHAY
CRCW080518K2FKEA
1
RUV2
130 kΩ 1%
VISHAY
CRCW0805130KFKEA
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9.2.2.3 Application Curve
VOUT = 21 V
Figure 37. Sample Buck-Boost Efficiency vs Input Voltage.
50
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9.2.3 LM3421 BOOST Application
D2
8V ± 28V
VIN
L1
D1
1
CIN
2
VIN
LM3421
HSN
HSP
EN
16
RHSN
15
RHSP
CFS
RSNS
RFS
RT
CCMP
RCSH
3
4
5
COMP
RPD
CSH
IS
RCT
VCC
14
13
1A
ILED
12
CO
CBYP
CT
6
AGND
GATE
OVP
PGND
11
Q1
RUV2
7
10
RLIM
DAP
RUVH
RUV1
Q3
8
nDIM
DDRV
9
PWM
Q2
COV
ROV2
ROV1
Figure 38. LM3421 BOOST Application
9.2.3.1 Design Requirements
• Input: 8 V to 28 V
• Output: 9 LEDs at 1 A
• PWM Dimming up to 30kHz
• Switching Frequency: 700-kHz
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9.2.3.2 Detailed Design Procedure
Table 3. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3421
Boost controller
TI
LM3421MH
1
CBYP
2.2-µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CCMP
0.1-µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
0
CFS
DNP
4
CIN
4.7-µF X7R 10% 100 V
TDK
C5750X7R2A475K
4
CO
10-µF X7R 10% 50 V
TDK
C4532X7R1H106K
1
COV
47-pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
2
D1, D2
Schottky 60 V 5 A
COMCHIP
CDBC560-G
1
L1
33-µH 20% 6.3 A
COILCRAFT
MSS1278-333MLB
2
Q1, Q2
NMOS 60 V 8 A
VISHAY
SI4436DY
1
Q3
NMOS 60 V 115 mA
ON-SEMI
2N7002ET1G
2
RCSH, ROV1
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
0 Ω 1%
VISHAY
CRCW08050000Z0EA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.06 Ω 1% 1 W
VISHAY
WSL2512R0600FEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RSNS
0.1 Ω 1% 1 W
VISHAY
WSL2512R1000FEA
1
RUV2
10 kΩ 1%
VISHAY
CRCW080510K0FKEA
1
RT
35.7 kΩ 1%
VISHAY
CRCW080535K7FKEA
1
RUV1
1.82 kΩ 1%
VISHAY
CRCW08051K82FKEA
1
RUVH
17.8 kΩ 1%
VISHAY
CRCW080517K8FKEA
52
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9.2.4 LM3421 Buck-Boost Application
10V ± 30V
VIN
L1
D1
1
LM3421
VIN
HSN
16
RHSN
15
RHSP
2A
ILED
CO
CIN
RT
2
CCMP
3
EN
HSP
COMP
RPD
Q2
DIM
14
CFS
RSNS
VIN
RPOT
RCSH
4
5
CSH
IS
RCT
VCC
RFS
13
RPU
12
Q7
6
GATE
AGND
11
Q1
Q6
RUV2
PGND
OVP
10
RLIM
RUV1
Q3
8
nDIM
D2
Q5
RSER
VIN
DAP
RUVH
ROV2
Q4
CB
7
CF
DIM
CBYP
CT
RF
DDRV
9
PWM
COV
ROV1
Figure 39. LM3421 Buck-Boost Application
9.2.4.1 Design Requirements
• Input: 10 V to 30 V
• Output: 4 LEDs at 2 A
• PWM Dimming: up to 10 kHz
• Analog Dimming
• Switching Frequency: 600-kHz
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9.2.4.2 Detailed Design Procedure
Table 4. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3421
Buck-boost controller
TI
LM3421MH
1
CB
100-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H101JA01D
1
CBYP
2.2-µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
3
CCMP, CREF, CSS
1-µF X7R 10% 25 V
MURATA
GRM21BR71E105KA01L
1
CF
0.1-µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
0
CFS
DNP
4
CIN
6.8-µF X7R 10% 50 V
TDK
C5750X7R1H685K
4
CO
10-µF X7R 10% 50 V
TDK
C4532X7R1H106K
1
COV
47-pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 100 V 12 A
VISHAY
12CWQ10FNPBF
1
D2
Zener 10 V 500 mA
ON-SEMI
BZX84C10LT1G
1
L1
22 µH 20% 7.2 A
COILCRAFT
MSS1278-223MLB
2
Q1, Q2
NMOS 60 V 8 A
VISHAY
SI4436DY
1
Q3
NMOS 60 V 260 mA
ON-SEMI
2N7002ET1G
1
Q4
PNP 40 V 200 mA
FAIRCHILD
MMBT5087
1
Q5
PNP 150 V 600 mA
FAIRCHILD
MMBT5401
1
Q6
NPN 300 V 600 mA
FAIRCHILD
MMBTA42
1
Q7
NPN 40 V 200 mA
FAIRCHILD
MMBT6428
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RF
10 Ω 1%
VISHAY
CRCW080510R0FKEA
1
RFS
0 Ω 1%
VISHAY
CRCW08050000Z0EA
1
RUV2
10 kΩ 1%
VISHAY
CRCW080510K0FKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.04 Ω 1% 1 W
VISHAY
WSL2512R0400FEA
1
ROV1
18.2 kΩ 1%
VISHAY
CRCW080518K2FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RPOT
1-MΩ potentiometer
BOURNS
3352P-1-105
1
RPU
4.99 kΩ 1%
VISHAY
CRCW08054K99FKEA
1
RSER
499 Ω 1%
VISHAY
CRCW0805499RFKEA
1
RSNS
0.05 Ω 1% 1 W
VISHAY
WSL2512R0500FEA
1
RT
41.2 kΩ 1%
VISHAY
CRCW080541K2FKEA
1
RUV1
1.43 kΩ 1%
VISHAY
CRCW08051K43FKEA
1
RUVH
17.4 kΩ 1%
VISHAY
CRCW080517K4FKEA
54
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9.2.5 LM3423 Boost Application
18V ± 38V
VIN
D2
L1
D1
1
VCC
External
Enable
CIN
VREF
CCMP
3
RMAX
HSN
HSP
EN
20
RHSN
19
RHSP
CFS
RSNS
COMP
RPD
18
RPD
D3
RPU
Q2
4
Q7
RADJ
LM3423
RFS
RT
Q4
Q5
2
VIN
CSH
IS
17
VCC
RBIAS2
RCSH
5
RCT
VCC
16
Q6
CDIM
CBYP
CT
6
GATE
AGND
15
Q1
RSER
CO
RUV2
7
8
OVP
PGND
nDIM
DDRV
FLT
DPOL
14
RLIM
13
RUVH
9
12
DAP
RUV1
10
TIMR
LRDY
700 mA
ILED
11
ROV2
Q3
PWM
COV
ROV1
RPD
Figure 40. LM3423 Boost Application
9.2.5.1 Design Requirements
• Input: 18 V to 38 V
• Output: 12 LEDs at 700 mA
• High-Side PWM Dimming: up to 30 kHz
• Dimming: Analog
• Zero Current Shutdown
• Switching Frequency: 700-kHz
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9.2.5.2 Detailed Design Procedure
Table 5. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3423
Boost controller
TI
LM3423MH
1
CBYP
2.2-µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CCMP
1-µF X7R 10% 25 V
MURATA
GRM21BR71E105KA01L
1
CFS
0.1-µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
4
CIN
4.7-µF X7R 10% 100 V
TDK
C5750X7R2A475K
4
CO
10-µF X7R 10% 50 V
TDK
C4532X7R1H106K
1
COV
47-pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
2
D1, D2
Schottky 60 V 5 A
COMCHIP
CDBC560-G
1
D3
Zener 10 V 500 mA
ON-SEMI
BZX84C10LT1G
1
L1
47 µH 20% 5.3 A
COILCRAFT
MSS1278-473MLB
1
Q1
NMOS 60 V 8 A
VISHAY
SI4436DY
1
Q2
PMOS 70 V 5.7 A
ZETEX
ZXMP7A17K
1
Q3
NMOS 60 V 260 mA
ON-SEMI
2N7002ET1G
1
Q4, Q5 (dual pack)
Dual PNP 40 V 200 mA
FAIRCHILD
FFB3906
1
Q6
NPN 300 V 600 mA
FAIRCHILD
MMBTA42
1
Q7
NPN 40 V 200 mA
FAIRCHILD
MMBT3904
1
RADJ
100-kΩ potentiometer
BOURNS
3352P-1-104
1
RBIAS2
17.4 kΩ 1%
VISHAY
CRCW080517K4FKEA
2
RCSH, ROV1
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
3
RHSP, RHSN, RMAX
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.06 Ω 1% 1W
VISHAY
WSL2512R0600FEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RSNS
0.15 Ω 1% 1W
VISHAY
WSL2512R1500FEA
1
RT
35.7 kΩ 1%
VISHAY
CRCW080535K7FKEA
1
RUV1
1.43 kΩ 1%
VISHAY
CRCW08051K43FKEA
1
RUV2
10 kΩ 1%
VISHAY
CRCW080510K0FKEA
1
RUVH
16.9 kΩ 1%
VISHAY
CRCW080516K9FKEA
56
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9.2.6 LM3421 Buck-Boost Application
10V ± 70V
VIN
L1
D1
RT
CIN
RCT
External
Enable
1
VIN
LM3421
HSN
16
RHSN
15
RHSP
Q9
2
EN
HSP
COMP
RPD
500 mA
ILED
CO
CEN
3
14
DIM
Q2
CCMP
RCSH
Q8
4
CSH
IS
13
CFS
RSNS
VIN
CCSH
5
RCT
RCT
VCC
RFS
12
RF
CBYP
CT
6
GATE
AGND
11
Q7
RPU
CF
Q1
DIM
RUV2
7
PGND
OVP
DAP
RUVH
RUV1
Q3
8
nDIM
Q6
10
RSER
DDRV
ROV2
Q4
CB
D2
Q5
9
VIN
PWM
COV
ROV1
Figure 41. LM3421 Buck-Boost Application
9.2.6.1 Design Requirements
• Input: 10 V to 70 V
• Output: 6 LEDs at 500 mA
• PWM Dimming up to 10 kHz
• Slow Fade Out
• MOSFET RDS-ON Sensing
• 700-kHz Switching Frequency
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9.2.6.2 Detailed Design Procedure
Table 6. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3421
Buck-boost controller
TI
LM3421MH
1
CB
100-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H101JA01D
1
CBYP
2.2-µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CCMP
1-µF X7R 10% 25 V
MURATA
GRM21BR71E105KA01L
1
CF
0.1-µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
0
CFS
DNP
4
CIN
4.7-µF X7R 10% 100 V
TDK
C5750X7R2A475K
4
CO
10-µF X7R 10% 50 V
TDK
C4532X7R1H106K
1
COV
47-pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 100 V 12 A
VISHAY
12CWQ10FNPBF
1
D2
Zener 10 V 500 mA
ON-SEMI
BZX84C10LT1G
1
L1
68 µH 20% 4.3 A
COILCRAFT
MSS1278-683MLB
2
Q1, Q2
NMOS 100 V 32 A
FAIRCHILD
FDD3682
1
Q3
NMOS 60 V 260 mA
ON-SEMI
2N7002ET1G
2
Q4, Q8
PNP 40 V 200 mA
FAIRCHILD
MMBT5087
1
Q5
PNP 150 V 600 mA
FAIRCHILD
MMBT5401
1
Q6
NPN 300 V 600 mA
FAIRCHILD
MMBTA42
2
Q7, Q9
NPN 40 V 200 mA
FAIRCHILD
MMBT6428
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
0 Ω 1%
VISHAY
CRCW08050000Z0EA
1
RUV2
10 kΩ 1%
VISHAY
CRCW080510K0FKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
ROV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RPU
4.99 kΩ 1%
VISHAY
CRCW08054K99FKEA
1
RSER
499 Ω 1%
VISHAY
CRCW0805499RFKEA
1
RSNS
0.2 Ω 1% 1 W
VISHAY
WSL2512R2000FEA
1
RT
35.7 kΩ 1%
VISHAY
CRCW080535K7FKEA
1
RUV1
1.43 kΩ 1%
VISHAY
CRCW08051K43FKEA
1
RUVH
17.4 kΩ 1%
VISHAY
CRCW080517K4FKEA
58
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9.2.7 LM3423 Buck Application
15V ± 50V
VIN
1
External
Enable
CIN
2
LM3423
VIN
HSN
HSP
EN
20
RHSN
19
RHSP
CFS
RSNS
RFS
RT
CCMP
3
COMP
RPD
18
CO
RPD
RPU
RCSH
4
5
CSH
IS
RCT
VCC
D2
17
ROV2
Q2
1.25A
ILED
D1
16
L1
CBYP
CT
6
7
AGND
GATE
OVP
PGND
nDIM
DDRV
FLT
DPOL
Q4
15
14
Q1
CDIM
RLIM
RUV2
RUVH
RUV1
Q3
8
13
PWM
9
12
VIN
DAP
RPU2
10
TIMR
LRDY
11
LED
STATUS
LIGHT
COV
ROV1
RPD
Figure 42. LM3423 Buck Application
9.2.7.1 Design Requirements
• Input: 15 V to 50 V
• Output: 3 LEDs at 1.25 A
• PWM Dimming up to 50 kHz
• LED Status Indicator
• Zero Current Shutdown
• 700-kHz Switching Frequency
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9.2.7.2 Detailed Design Procedure
Table 7. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3423
Buck controller
TI
LM3423MH
1
CBYP
2.2-µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
2
CCMP, CDIM
0.1 µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
0
CFS
DNP
4
CIN
4.7-µF X7R 10% 100 V
TDK
C5750X7R2A475K
0
CO
DNP
1
COV
47-pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 100 V 12 A
VISHAY
12CWQ10FNPBF
1
D2
Zener 10 V 500 mA
ON-SEMI
BZX84C10LT1G
1
L1
22 µH 20% 7.3 A
COILCRAFT
MSS1278-223MLB
1
Q1
NMOS 60 V 8 A
VISHAY
SI4436DY
1
Q2
PMOS 30 V 6.2 A
VISHAY
SI3483DV
1
Q3
NMOS 60 V 115 mA
ON-SEMI
2N7002ET1G
1
Q4
PNP 150 V 600 mA
FAIRCHILD
MMBT5401
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
0 Ω 1%
VISHAY
CRCW08050000OZEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.04 Ω 1% 1 W
VISHAY
WSL2512R0400FEA
1
ROV1
21.5 kΩ 1%
VISHAY
CRCW080521K5FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
3
RPU, RPU2, RUV2
100 kΩ 1%
VISHAY
CRCW0805100KFKEA
1
RT
35.7 kΩ 1%
VISHAY
CRCW080535K7FKEA
1
RSNS
0.08 Ω 1% 1 W
VISHAY
WSL2512R0800FEA
1
RUV1
11.5 kΩ 1%
VISHAY
CRCW080511K5FKEA
60
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SNVS574G – JULY 2008 – REVISED JULY 2019
9.2.8 LM3423 Buck-Boost Application
L1
15V ± 60V
VIN
D1
Q2
RPU
D2
1
CIN
External
Enable
RT
CCMP
RCSH
2
3
4
VIN
LM3423
HSN
EN
HSP
COMP
RPD
IS
CSH
20
RHSN
19
RHSP
18
2.5A
ILED
CO
RPD
17
CFS
RSNS
VIN
5
RFLT
RCT
VCC
RFS
16
CBYP
CT
6
7
AGND
GATE
OVP
PGND
nDIM
DDRV
15
Q1
ROV2
14
RUV2
8
VIN
13
Q5
RUV1
9
FLT
DPOL
12
DAP
10
TIMR
LRDY
11
CTMR
COV
ROV1
RPD
Figure 43. LM3423 Buck-Boost Application
9.2.8.1 Design Requirements
• Input: 15 V to 60 V
• Output: 8 LEDs at 2.5 A
• Fault Input Disconnect
• Zero Current Shutdown
• 500-kHz Switching Frequency
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9.2.8.2 Detailed Design Procedure
Table 8. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3423
Buck-boost controller
TI
LM3423MH
1
CBYP
2.2-µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CCMP
0.33-µF X7R 10% 25 V
MURATA
GRM21BR71E334KA01L
1
CFS
0.1-µF X7R 10% 25 V
MURATA
GRM21BR71E104KA01L
4
CIN
4.7-µF X7R 10% 100 V
TDK
C5750X7R2A475K
4
CO
10-µF X7R 10% 50 V
TDK
C4532X7R1H106K
1
COV
47-pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
CTMR
220-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H221JA01D
1
D1
Schottky 100 V 12 A
VISHAY
12CWQ10FNPBF
1
D2
Zener 10 V 500 mA
ON-SEMI
BZX84C10LT1G
1
L1
22 µH 20% 7.2 A
COILCRAFT
MSS1278-223MLB
1
Q1
NMOS 100 V 32 A
FAIRCHILD
FDD3682
1
Q2
PMOS 70 V 5.7 A
ZETEX
ZXMP7A17K
1
Q5
PNP 150 V 600 mA
FAIRCHILD
MMBT5401
2
RCSH, ROV1
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10 Ω 1%
VISHAY
CRCW080510R0FKEA
2
RFLT, RPU2
100 kΩ 1%
VISHAY
CRCW0805100KFKEA
2
RHSP, RHSN
1 kΩ 1%
VISHAY
CRCW08051K00FKEA
2
RLIM, RSNS
0.04 Ω 1% 1 W
VISHAY
WSL2512R0400FEA
1
ROV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RT
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RUV1
13.7 kΩ 1%
VISHAY
CRCW080513K7FKEA
1
RUV2
150 kΩ 1%
VISHAY
CRCW0805150KFKEA
62
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SNVS574G – JULY 2008 – REVISED JULY 2019
9.2.9 LM3421 SEPIC Application
9V ± 36V
VIN
L1
D1
CSEP
L2
1
CIN
2
VIN
LM3421
HSN
HSP
EN
16
RHSN
15
RHSP
CFS
RSNS
RFS
RT
CCMP
RCSH
3
4
5
COMP
RPD
CSH
IS
RCT
VCC
14
13
750 mA
ILED
12
CO
CBYP
CT
6
AGND
GATE
OVP
PGND
11
Q1
RUV2
7
10
RLIM
DAP
RUVH
RUV1
Q3
8
nDIM
DDRV
9
PWM
Q2
COV
ROV2
ROV1
Figure 44. LM3421 SEPIC Application
9.2.9.1 Design Procedure
• Input: 9 V to 36 V
• Output: 5 LEDs at 750 mA
• PWM Dimming up to 30 kHz
• 500-kHz Switching Frequency
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9.2.9.2 Detailed Design Procedure
Table 9. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3421
SEPIC controller
TI
LM3421MH
1
CBYP
2.2-µF X7R 10% 16 V
MURATA
GRM21BR71C225KA12L
1
CCMP
0.47-µF X7R 10% 25 V
MURATA
GRM21BR71E474KA01L
0
CFS
DNP
4
CIN
4.7-µF X7R 10% 100 V
TDK
C5750X7R2A475K
4
CO
10-µF X7R 10% 50 V
TDK
C4532X7R1H106K
1
CSEP
1-µF X7R 10% 100 V
TDK
C4532X7R2A105K
1
COV
47-pF COG/NPO 5% 50 V
AVX
08055A470JAT2A
1
CT
1000-pF COG/NPO 5% 50 V
MURATA
GRM2165C1H102JA01D
1
D1
Schottky 60 V 5 A
COMCHIP
CDBC560-G
2
L1, L2
68 µH 20% 4.3 A
COILCRAFT
DO3340P-683
2
Q1, Q2
NMOS 60 V 8 A
VISHAY
SI4436DY
1
Q3
NMOS 60 V 115 mA
ON-SEMI
2N7002ET1G
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
0 Ω 1%
VISHAY
CRCW08050000OZEA
2
RHSP, RHSN
750 Ω 1%
VISHAY
CRCW0805750RFKEA
1
RLIM
0.04 Ω 1% 1 W
VISHAY
WSL2512R0400FEA
1
ROV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
2
RREF1, RREF2
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RSNS
0.1 Ω 1% 1 W
VISHAY
WSL2512R1000FEA
1
RT
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RUV1
1.62 kΩ 1%
VISHAY
CRCW08051K62FKEA
1
RUV2
10 kΩ 1%
VISHAY
CRCW080510K0FKEA
1
RUVH
16.9 kΩ 1%
VISHAY
CRCW080516K9FKEA
64
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LM3421, LM3423
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SNVS574G – JULY 2008 – REVISED JULY 2019
10 Power Supply Recommendations
10.1 General Recommendations
The device is designed to operate from an input voltage supply range from 4.5 V to 75 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the EVM or PCB, additional
bulk capacitance may be required in addition to the ceramic bypass capacitors.
10.2 Input Supply Current Limit
It is important to set the output current limit of your input supply to an appropriate value to avoid delays in your
converter analysis and optimization. If not set high enough, current limit can be tripped during start-up or when
your converter output power is increased, causing a foldback or shutdown condition. It is a common oversight
when powering up a converter for the first time.
11 Layout
11.1 Layout Guidelines
•
•
•
•
The performance of any switching regulator depends as much upon the layout of the PCB as the component
selection. Following a few simple guidelines allows maximum noise rejection and minimal generation of EMI
within the circuit.
Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing
these paths. The main path for discontinuous current in the LM34xx-Q1 buck regulator contains the input
capacitor (CIN), the recirculating diode (D1), the N-channel MOSFET (Q1), and the sense resistor (RLIM). In
the LM34xx-Q1 boost regulator, the discontinuous current flows through the output capacitor (CO), D1, Q1,
and RLIM. In the buck-boost regulator, both loops are discontinuous and should be carefully layed out. These
loops should be kept as small as possible and the connections between all the components should be short
and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and Q1 connect)
should be just large enough to connect the components. To minimize excessive heating, large copper pours
can be placed adjacent to the short current path of the switch node.
The RT, COMP, CSH, IS, HSP and HSN pins are all high-impedance inputs which couple external noise
easily; therefore, the loops containing these nodes should be minimized whenever possible.
In some applications the LED or LED array can be far away (several inches or more) from the controller or on
a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large
or separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce
the effects of parasitic inductance on the AC impedance of the capacitor.
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LM3421, LM3423
SNVS574G – JULY 2008 – REVISED JULY 2019
www.ti.com
11.2 Layout Example
Note critical paths and component placement:
Minimize power loop containing discontinuous currents
Minimize signal current loops (components close to IC)
x
Ground plane under IC for signal routing helps minimize noise coupling
discontinuous switching
frequency currents
VIN
Input
Power
1
GND
VIN
2
3
4
5
6
7
LM3421
HSN
EN
HSP
COMP
RPD
CSH
IS
RCT
VCC
GATE
AGND
PGND
OVP
16
15
14
13
ILED
12
11
10
DAP
PWM
8
nDIM
DDRV
9
STAR GROUND
Power Ground
Figure 45. LM3421 Boost Layout Guideline
66
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LM3421, LM3423
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SNVS574G – JULY 2008 – REVISED JULY 2019
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 10. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM3421
Click here
Click here
Click here
Click here
Click here
LM3421-Q1
Click here
Click here
Click here
Click here
Click here
LM3423
Click here
Click here
Click here
Click here
Click here
LM3423-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LM3421 LM3423
67
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM3421MH/NOPB
ACTIVE
HTSSOP
PWP
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3421
MH
LM3421MHX/NOPB
ACTIVE
HTSSOP
PWP
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3421
MH
LM3423MH/NOPB
ACTIVE
HTSSOP
PWP
20
73
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3423
MH
LM3423MHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3423
MH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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