LM3450EV120V15W/NOPB

User's Guide SNVA463A – November 2010 – Revised May 2013 AN-2098 LM3450 Evaluation Board 1 Introduction The LM3450 evaluation board is designed to provide an AC to LED solution for a 15W LED load. Specifically, it takes an AC mains input and converts it to a constant current output of 350mA for a series string of 1 to 14 LEDs (maximum LED stack voltage of 45V). There are two assembly versions designed to operate from two different nominal AC input voltages, 120VAC or 230VAC. The board employs a two stage design with an LM3450 flyback primary stage and an LM3409 secondary stage. The LM3450 provides an isolated 50V regulated output voltage and a power factor corrected input current. The LM3409 uses the 50V flyback output as its input and provides a constant current of 350mA to the LED load. This two-stage design provides excellent line and load regulation as well as isolation. The board is comprised of two copper layers with components on both sides and an FR4 dielelctric. The two stage design has several key advantages over a single stage design including: • No 120Hz LED current ripple. • Better dimming performance at low dimming levels. • Better line disturbance rejection. • Better efficiency using small LED stack voltages. 2 Specifications • • • • • • • • 120VAC 15W Version Input Voltage Range: VIN = 90VAC – 135VAC Regulated Flyback Output Voltage: VOUT = 50V Maximum LED Stack Voltage: VLED < 45V Regulated LED Current: ILED = 350mA 230VAC 15W Version Input Voltage Range: VIN = 180VAC – 265VAC Regulated Flyback Output Voltage: VOUT = 50V Maximum LED Stack Voltage: VLED < 45V Regulated LED Current: ILED = 350mA PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. SNVA463A – November 2010 – Revised May 2013 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated AN-2098 LM3450 Evaluation Board 1 Specifications www.ti.com VREF BIAS VADJ HOLD RETURN EMI FILTER FLT2 ZCD FLT1 VCC LM3409 LED Driver LM3450 PWM AC INPUT DIM VAC COMP FB GATE LED LOAD CS OPTICAL ISOLATION GND ISEN PWM HOLD RETURN Figure 1. Board Design 2 AN-2098 LM3450 Evaluation Board SNVA463A – November 2010 – Revised May 2013 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Typical Performance www.ti.com Typical Performance 83 83 81 81 EFFICIENCY (%) EFFICIENCY (%) 3 120VAC 79 100VAC 200VAC 230VAC 79 77 77 75 8 10 12 14 75 8 16 10 POUT (W) 12 14 16 POUT (W) Figure 2. 120V 15W Version Efficiency vs. Output Power Figure 3. 230V 15W Version Efficiency vs. Output Power 1.00 1.00 100VAC 0.98 0.98 200VAC PF PF 120VAC 0.96 0.96 230VAC 0.94 0.94 0.92 8 10 12 14 0.92 8 16 10 POUT (W) 12 14 16 POUT (W) Figure 4. 120V 15W Version Power Factor vs. Output Power Figure 5. 230V 15W Version Power Factor vs. Output Power 100 70 mA Dynamic Hold + 4 mA Fixed Hold EFFICIENCY (%) 80 60 40 20 0 0 20 mA Fixed Hold Only 4 8 12 16 POUT (W) Figure 6. Dimming Efficiency Comparison SNVA463A – November 2010 – Revised May 2013 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated AN-2098 LM3450 Evaluation Board 3 EMI Performance 4 www.ti.com EMI Performance 110.0 Amplitude in dBuV 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 100.0k 1.0M 10.0M 100.0M Frequency Figure 7. 120V 15W Conducted EMI Peak Scan Line and Neutral - CISPR/FCC Class B Quasi Peak and Average Limits 110.0 Amplitude in dBuV 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 100.0k 1.0M 10.0M 100.0M Frequency Figure 8. 230V 15W Conducted EMI Peak Scan Line and Neutral - CISPR/FCC Class B Quasi Peak and Average Limits 30 30 25 Limits 20 AMPLITUDE (mA) AMPLITUDE (mA) 25 Measured 15 10 5 Limits 20 Measured 15 10 5 0 0 3 5 7 9 11 13 3 HARMONIC NUMBER Figure 9. 120V 15W THD Measurements EN 61000-3 Class C Limits 4 AN-2098 LM3450 Evaluation Board 5 7 9 11 13 HARMONIC NUMBER Figure 10. 230V 15W THD Measurements EN 61000-3 Class C Limits SNVA463A – November 2010 – Revised May 2013 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated LM3450 Pin Descriptions www.ti.com 5 LM3450 Pin Descriptions 1 2 3 4 5 6 7 8 VREF BIAS VADJ HOLD FLT2 ZCD FLT1 VCC DIM GATE VAC CS COMP FB GND ISEN 16 15 14 13 12 11 10 9 Pin Name Description Application Information 1 VREF 3V Reference Reference Output: Connect directly to VADJ or to resistor divider feeding VADJ and to necessary external circuits. 2 VADJ Analog Adjust Analog Dim and Phase Dimming Range Input: Connect directly to VREF to force standard 70% phase dimming range. Connect to resistor divider from VREF to extend usable range of some phase dimmers or for analog dimming. Connect to GND for low power mode. 3 FLT2 Filter 2 Ramp Comparator Input: Connect a series resistor from FLT1 capacitor and a capacitor to GND to establish second filter pole. 4 FLT1 Filter 1 Angle Decoder Output: Connect a series resistor to a capacitor to ground to establish first filter pole. 5 DIM 500 HzPWM Output 6 VAC SampledRectified Line 7 COMP Compensation Error Amplifier Output and PWM Comparator Input: Connect a capacitor to GND to set the compensation. Feedback Error Amplifier Inverting Input: Connect to output voltage via resistor divider to control PFC voltage loop for non-isolated designs. Connect to a 5.11kΩ resistor to GND for isolated designs (bypasses error amplifier). Also includes over-voltage protection and shutdown modes. Input Current Sense Non-Inverting Input: Connect to diode bridge return and resistor to GND to sense input current for dynamic hold. Connect a 0.1µF capacitor and Schottky diode to GND, and a 0.22µF capacitor to HOLD. 8 FB Open Drain PWM Dim Output: Connect to dimming input of output stage LED driver (directly or with isolation) to provide decoded dimming command. Multiplier and Angle Decoder Input: Connect to resistor divider from rectified AC line. 9 ISEN Input Current Sense 10 GND Power Ground System Ground 11 CS Current Sense MosFET Current Sense Input: Connect to positive terminal of sense resistor in PFC MosFET source. 12 GATE Gate Drive Gate Drive Output: Connect to gate of main power MosFET for PFC.Gate Drive Output: Connect to gate of main power MosFET for PFC. 13 VCC Input Supply 14 ZCD Zero Crossing Detector 15 HOLD Dynamic Hold Open Drain Dynamic Hold Input: Connect to holding resistor which is connected to source of passFET. 16 BIAS Pre-regulator Gate Bias Pre-regulator Gate Bias Output: Connect to gate of passFET and to resistor to rectified AC (drain of passFET) to aid with startup. Power Supply Input: Connect to primary bias supply. Connect a 0.1µF bypass capacitor to ground. Demagnetization Sense Input: Connect a resistor to transformer/inductor winding to detect when all energy has been transferred. SNVA463A – November 2010 – Revised May 2013 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated AN-2098 LM3450 Evaluation Board 5 LM3409HV Pin Descriptions 6 www.ti.com LM3409HV Pin Descriptions 1 2 3 4 5 6 UVLO VIN IADJ VCC EN COFF GND DAP CSP CSN PGATE 10 9 8 7 6 Pin Name Description 1 UVLO Input Under Voltage Lock-out 2 IADJ Analog LED Current Adjust 3 EN Logic Level Enable 4 COFF Off-time programming 5 GND Power Ground 6 PGATE Gate Drive 7 CSN Negative Current Sense Connect to the negative side of the sense resistor. 8 CSP Positive Current Sense Connect to the positive side of the sense resistor (also connected to VIN). 9 VCC VIN-referenced Linear Regulator Output Connect at least a 1 µF ceramic capacitor from this pin to CSN. The regulator provides power for P-FET drive. 10 VIN Input Voltage DAP DAP Thermal PAD on bottom of IC AN-2098 LM3450 Evaluation Board Application Information Connect to a resistor divider from VIN. UVLO threshold is 1.24V and hysteresis is provided by a 22µA current source. Apply a voltage between 0 - 1.24V, or connect a resistor from this pin to GND, to set the current sense threshold voltage. Apply a voltage >1.6V to enable device, a PWM signal to dim, or a voltage