LM34902ITMX/NOPB

LM34902 www.ti.com SNVS804B – MAY 2012 – REVISED APRIL 2013 300mA Current Limited Power Switch Check for Samples: LM34902 FEATURES DESCRIPTION • • • • • • • • • The LM34902 is a 0.3A PFET switch used to control the input voltage of electronic devices. It is easily integrated into system designs that have a 2.8V to 5.3V voltage rail. Besides the 0.45Ω PFET switch, the LM34902 can be enabled or disabled by a logic signal. The IC monitors the presence of a downstream electronic device via a dedicated pin to decide whether to turn on the PFET switch. A power good signal generated by the IC can be used by system control to determine the status of the switch. The LM34902 also provides over-current and overtemperature protection. The IC comes in a tiny 6bump Thin DSBGA package. 1 2 Input Voltage of 2.8V to 5.3V 0.3A Maximum Switch Current 0.64Ω Typical Total On-Resistance Load Detection Enable/Disable Switch On Indicator Peak Current Limit Thermal Shutdown 6-Bump Thin DSBGA Package APPLICATIONS • • Handsets, Tablets, Notebooks Portable devices Typical Application Circuit VCC Main: 2.8V to 5.3V 1.8V 220k 220k VCC GND POK B1 C1 A2 LM34902 PC A1 B2 C2 ACC_PWR VIN Accessory Device ENABLE ACC_DET 1M Accessory Detection 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated LM34902 SNVS804B – MAY 2012 – REVISED APRIL 2013 www.ti.com Connection Diagram Figure 1. Top View 6-Bump Thin DSBGA Package See Package Number YFQ PIN DESCRIPTION Name Pin Number VCC A1 Power input of the PFET switch. It also provides power to the entire IC. Connect to the voltage rail that the accessory device is expected to work off. GND B1 Common Ground (device substrate). POK C1 Open-drain PFET status indicator. When the PFET is off, this pin floats. When PFET is on, it is grounded. ACC_DET C2 Pull this pin low to tell the IC that the downstream accessory device is plugged in. ENABLE B2 When this pin is low, the PFET will be turned off and POK will be open-drained. Current limit circuitry will also be disabled. The IC will be in a low-power state. This pin should be held low until VCC is established to ensure proper initial state of internal logic. When ENABLE is high, the PFET switch will be allowed to turn on. ACC_PWR A2 Power output terminal of the PFET switch. Connect to input rail of accessory device. Function Truth Table Input Output ENABLE ACC_DET Current Limit Detected TJ Limit Exceeded 2.8V < VCC < 5.3V PFET Switch Status POK 0 x No No Yes Open Open Drain x 1 No No Yes Open Open Drain 0 to 1 0 No No Yes On Grounded 0 to 1 0 Yes No Yes Current Limited Grounded x x x Yes 2.2V < VCC < 5.3V Open Open Drain 0 x x No 2.2V < VCC < 2.8V Open Open Drain Note: "x" stands for "don't care". These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) VCC -0.3V to 6V ENABLE, POK, ACC_DET, ACC_PWR (2) -0.3V to 6V Junction Temperature (TJ) +150°C −65°C to +150°C Storage Temperature Range ESD Susceptibility, Human Body Model (3) (1) (2) (3) 2 2kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics table. The voltages on these pins should never exceed VCC+0.3V. The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-A114. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM34902 LM34902 www.ti.com SNVS804B – MAY 2012 – REVISED APRIL 2013 Operating Ratings (1) VCC Voltage (2) 2.8V to 5.3V Junction Temperature (TJ), LM34902 (1) -40°C to +85°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics table. For VCC between 2.2V and 2.8V, if ENABLE is a logic low, the LM34902 will not turn on the PFET switch. (2) Electrical Characteristics Unless otherwise stated, the following conditions apply: VCC = 3V. Limits in standard type are for TJ = 25°C only; limits in boldfacetype apply over the operating junction temperature (TJ) range. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. Symbol Parameter Conditions VIL Input Low Voltage, ACC_DET, ENABLE VIH Input High Voltage, ACC_DET, ENABLE VIHS Input Hysteresis, ACC_DET, ENABLE ILK Input Current, ACC_DET, ENABLE ACC_DET, ENABLE between 0V and VCC Min Typ Max Units 0.45 V 1.35 V 55 mV 1 µA 10 µA 47 100 µA 0.64 1 Ω 1 µA 0.65 A 0.4 V 1 µA ISD VCC Current in Shutdown Mode VENABLE = 0V VVCC = 5.3V IQ VCC Quiescent Current VENABLE = 1.8V VVCC = 5.3V, IACC_PWR = 0A RON Total On Resistance Between VCC and ACC_PWR Pins VVCC = 3V IACC_PWR = 0.3A ILK_ACC ACC_PWR Leakage Current When PFET is Off VACC_PWR = 0V to VCC VVCC = 5.3V VENABLE = 0V ILIMIT PFET Switch Current Limit VVCC = 2.8V to 5.3V VACC_PWR = 0V VPOK POK Current Sink Capability POK asserted. 1mA sink current. IPOK POK Leakage Current POK de-asserted. VPOK = 3.3V T1 ACC_DET Response Time ACC_DET rising to either PFET or POK FET turn-off 40 ns T2 ENABLE Response Time ENABLE rising to either PFET or POK FET turnon 10 µs T3 Minimum ENABLE Cycle Time (1) ACC_DET tied to ground. ENABLE logic high = 1.8V. VCC = 2.8V to 5.3V. 300 ns (1) 0.3 0.45 If ENABLE toggles low from a high state, it needs to stay low for at least T3 long before toggling back to high. Otherwise the internal flipflop may not be set and the PFET switch may not turn on. Thermal Characteristics Symbol Description Conditions Typical Value Unit θJA1 Junction-to-Ambient Thermal Resistance Mount device on a standard 4-layer 4" x 3" JEDEC board. Apply known amount of power to the package. Measure junction temperature and surrounding air temperature. No air flow. Refer to JESD51-7 for more information. 104 °C/W θJA2 Junction-to-Ambient Thermal Resistance Mount device on a 2-layer 2.19" x 2.9" board. Copper thickness is 1 oz per layer. No airflow. Power dissipation is 0.5W. 136 °C/W TSD Thermal Shutdown Threshold Raise TJ from below 150°C until POK is de-asserted. No load is connected at ACC_PWR. 170 °C Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM34902 3 LM34902 SNVS804B – MAY 2012 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Unless indicated otherwise, VCC = 3V and TJ = 25°C. 4 Total ON Resistance vs Temperature Total ON Resistance vs Switch Current Figure 2. Figure 3. Total ON Resistance vs VCC Current Limit vs Temperature Figure 4. Figure 5. Input Logic High Threshold vs Temperature Input Logic Low Threshold vs Temperature Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM34902 LM34902 www.ti.com SNVS804B – MAY 2012 – REVISED APRIL 2013 BLOCK DIAGRAM APPLICATION HINTS To turn on the PFET switch, both the ENABLE and the ACC_DET pins need to be asserted. In addition, ACC_DET needs to be asserted no later than the rising edge of the ENABLE signal. De-assertion of either the ENABLE or the ACC_DET will result in turned-off PFET switch and de-asserted POK signal. To prevent a glitch in the otherwise asserted ACC_DET from keeping the FETs turned off, it is a good practice to cycle the ENABLE following every falling edge in the ACC_DET signal. When cycling the ENABLE, make sure it stays low for at least T3 long before toggling back high. If ENABLE logic high level is not 1.8V, make sure ENABLE stays low for at least 1µs. When laying out the PCB, try to keep the ENABLE and ACC_DET traces as short as possible and away from noisy traces. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM34902 5 LM34902 SNVS804B – MAY 2012 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B • 6 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 5 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM34902 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM34902ITM/NOPB ACTIVE DSBGA YFQ 6 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 K LM34902ITMX/NOPB ACTIVE DSBGA YFQ 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 K (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of