LM34919EVAL

User's Guide SNVA250A – June 2007 – Revised April 2013 AN-1650 LM34919 Evaluation Board 1 Introduction The LM34919EVAL evaluation board provides the design engineer with a fully functional buck regulator, employing the constant on-time (COT) operating principle. This evaluation board provides a 5V output over an input range of 8V to 40V. The circuit delivers load currents to 600 mA, with current limit set at a nominal 700 mA. The board is populated with all components except R5, C9 and C10. These components provide options for managing the output ripple as described later in this document. The board’s specification are: • Input Voltage: 8V to 40V • Output Voltage: 5V • Maximum load current: 600 mA • Minimum load current: 0A • Current Limit: 640 mA to 730 mA • Measured Efficiency: 92.7% (VIN = 8V, IOUT = 300 mA) • Nominal Switching Frequency: 800 kHz • Size: 2.6 in. x 1.6 in. x 0.5 in Figure 1. Evaluation Board - Top Side All trademarks are the property of their respective owners. SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback AN-1650 LM34919 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 1 Theory of Operation 2 www.ti.com Theory of Operation Refer to the evaluation board schematic in Figure 5, which contains a simplified block diagram of the LM34919. When the circuit is in regulation, the buck switch is on each cycle for a time determined by R1 and VIN according to the equation: tON = 1.13 x 10 -10 x (R1 + 1.4 k:) + 100 ns VIN - 1.5V (1) The on-time of this evaluation board ranges from ≊875 ns at VIN = 8V, to ≊231 ns at VIN = 40V. The ontime varies inversely with VIN to maintain a nearly constant switching frequency. At the end of each ontime the Minimum Off-Timer ensures the buck switch is off for at least 155 ns. In normal operation, the offtime is much longer. During the off-time, the load current is supplied by the output capacitor (C7, C8). When the output voltage falls sufficiently that the voltage at FB is below 2.5V, the regulation comparator initiates a new on-time period. For stable, fixed frequency operation, a minimum of 25 mV of ripple is required at FB to switch the regulation comparator. The current limit threshold, is ≊640 mA at Vin = 8V, and ≊730 mA at Vin = 40V. The variation is due to the change in ripple current amplitude as Vin varies. Refer to the LM34919 data sheet for a more detailed block diagram, and a complete description of the various functional blocks. 3 Board Layout and Probing The pictorial in Figure 1 shows the placement of the circuit components. The following should be kept in mind when the board is powered: 1) When operating at high input voltage and high load current, forced air flow may be necessary. 2) The LM34919, and diode D1 may be hot to the touch when operating at high input voltage and high load current. 3) Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible damage to the circuit. 4) At maximum load current (0.6A), the wire size and length used to connect the load becomes important. Ensure there is not a significant drop in the wires between this evaluation board and the load. 4 Board Connection/Start-up The input connections are made to the J1 connector. The load is connected to the J2 (OUT) and J3 (GND) terminals. Ensure the wires are adequately sized for the intended load current. Before start-up a voltmeter should be connected to the input terminals, and to the output terminals. The load current should be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased gradually to 8V, at which time the output voltage should be 5V. If the output voltage is correct with 8V at VIN, then increase the input voltage as desired and proceed with evaluating the circuit. DO NOT EXCEED 40V AT VIN. 5 Output Ripple Control The LM34919 requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform at the SW pin, for proper operation. The required ripple can be supplied from ripple at VOUT, through the feedback resistors as described in Options A and B below, or the ripple can be generated separately (using R5, C9, and C10) in order to keep the ripple at VOUT at a minimum (Option C). Option A) Lowest Cost Configuration: This evaluation board is supplied with R4 installed in series with the output capacitance (C7, C8). Since ≥25 mVp-p are required at the FB pin, R4 is chosen to generate ≥50 mVp-p at VOUT, knowing that the minimum ripple current in this circuit is ≊155 mAp-p at minimum VIN. Using 0.39Ω for R4, the ripple at VOUT ranges from ≊60 mVp-p to ≊140 mVp-p over the input voltage range. If the application can accept this ripple level, this is the most economical solution. The circuit is shown in Figure 2 and Figure 8. 2 AN-1650 LM34919 Evaluation Board SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Output Ripple Control www.ti.com 8V to 40V VIN D1 IN C1 1 PF C2 1 PF LM34919 C3 R1 43.2k Minimum Off Timer On Timer 0.1PF VCC C3 VIN BST D3 Gnd RON/SD A1 SS B3 C6 0.022 PF C4 0.1 PF C5 SW D2 Logic 2.5V 0.022 PF L1 15 PH 5V VOUT D1 ISEN FB A3 R6 0: Regulation Comparator A2 R2 2.49k C1 Current Limit Detect C7 SGND R3 2.49k B1 RTN R4 0.39: C8 10 PF 10 PF Gnd Figure 2. Lowest Cost Configuration Option B) Intermediate Ripple Configuration: This configuration generates less ripple at VOUT than option A above by the addition of one capacitor (Cff) across R2, as shown in Figure 3. 8V to 40V VIN D1 IN C1 1 PF C2 1 PF LM34919 C3 R1 43.2k Minimum Off Timer On Timer 0.1PF Gnd RON/SD A1 C6 0.022 PF SS B3 FB A3 VCC C3 VIN BST D3 C5 SW D2 Logic C4 0.1 PF 2.5V 0.022 PF L1 15 PH R6 0: 5V VOUT D1 ISEN Regulation Comparator A2 Current Limit Detect RTN C1 R2 2.49k Cff 1000 pF R4 0.18: C7 SGND R3 2.49k B1 C8 10 PF 10 PF Gnd Figure 3. Intermediate Ripple Configuration Since the output ripple is passed by Cff to the FB pin with little or no attenuation, R4 can be reduced so the minimum ripple at VOUT is ≊25 mVp-p. The minimum value for Cff is calculated from: Cff t tON (max) (R2//R3) (2) where tON(max) is the maximum on-time (at minimum VIN), and R2//R3 is the parallel equivalent of the feedback resistors. See Figure 8. Option C) Minimum Ripple Configuration: To obtain minimum ripple at VOUT, R4 is set to 0Ω, and R5, C9, and C10 are added to generate the required ripple for the FB pin. In this configuration, the output ripple is determined primarily by the ESR of the output capacitance and the inductor’s ripple current. The ripple voltage required by the FB pin is generated by R5, C10, and C9 since the SW pin switches from -1V to VIN, and the right end of C10 is a virtual ground. The values for R5 and C10 are chosen to generate a 50-100 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through C9. The following procedure is used to calculate values for R5, C10 and C9: SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback AN-1650 LM34919 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 3 Monitor The Inductor Current www.ti.com 1) Calculate the voltage VA: VA = VOUT – (VSW x (1 – (VOUT/VIN))) (3) where VSW is the absolute value of the voltage at the SW pin during the off-time (typically 1V), and VIN is the minimum input voltage. For this circuit, VA calculates to 4.63V. This is the approximate DC voltage at the R5/C10 junction, and is used in the next equation. 2) Calculate the R5 x C10 product: R5 x C10 = (VIN ± VA) x tON 'V (4) where tON is the maximum on-time (≊875 ns), VIN is the minimum input voltage, and ΔV is the desired ripple amplitude at the R5/C10 junction, 100 mVp-p for this example. R5 x C10 = (8V - 4.63V) x 875 ns 0.1V = 29.5 x 10-6 (5) R5 and C10 are then chosen from standard value components to satisfy the above product. Typically C10 is 3000 to 5000 pF, and R5 is 10kΩ to 300 kΩ. C9 is chosen large compared to C10, typically 0.1 µF. See Figure 4 and Figure 8. 8V to 40V VIN D1 IN C1 1 PF C2 1 PF LM34919 C3 R1 43.2k Minimum Off Timer On Timer 0.1PF Gnd RON/SD A1 C6 0.022 PF SS B3 FB A3 Logic VCC C3 C4 0.1 PF VIN BST D3 C5 SW D2 0.022 PF L1 15 PH R5 R6 0: 5V C10 VOUT 2.5V ISEN Regulation Comparator A2 Current Limit Detect RTN C1 D1 8.87 k: 3300 pF C9 0.1 PF R2 2.49k R4 0: C7 SGND R3 2.49k B1 C8 10 PF 10 PF Gnd Figure 4. Minimum Output Ripple Configuration 6 Monitor The Inductor Current The inductor’s current can be monitored or viewed on a scope with a current probe. Remove R6, and install an appropriate current loop across the two large pads where R6 was located. In this way the inductor’s ripple current and peak current can be accurately determined. 7 Scope Probe Adapters Scope probe adapters are provided on this evaluation board for monitoring the waveform at the SW pin, and at the circuit’s output (VOUT), without using the probe’s ground lead which can pick up noise from the switching waveforms. The probe adapters are suitable for Tektronix P6137 or similar probes, with a 0.135” diameter. 8 Minimum Load Current The LM34919 requires a minimum load current of ≊1 mA to ensure the boost capacitor (C5) is recharged sufficiently during each off-time. In this evaluation board, the minimum load current is provided by the feedback resistors allowing the board’s minimum load current at VOUT to be specified at zero. 4 AN-1650 LM34919 Evaluation Board SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Minimum Load Current www.ti.com VIN D1 IN C2 1 PF C1 1 PF LM34919 C3 R1 43.2k Minimum Off Timer On Timer 0.1PF VCC C3 VIN Gnd RON/SD A1 C6 0.022 PF SS B3 C4 0.1 PF Logic BST D3 0.022 C5 PF SW D2 SW L1 15 PH R5 R6 0: 5V C10 VOUT 2.5V ISEN FB A3 Regulation Comparator A2 Current Limit Detect RTN D1 R2 2.49k C9 C1 SGND R3 2.49k B1 C7 R4 0.39: OUTPUT 8V to 40V C8 10 PF 10 PF Gnd Figure 5. Complete Evaluation Board Schematic Table 1. Bill of Materials Item Description Mfg., Part Number Package Value C1, C2 Ceramic Capacitor TDK C3216X7R1H105M 1210 1.0 µF, 50V C3 Ceramic Capacitor TDK C1608X7R1H104K 0603 0.1 µF, 50V C4 Ceramic Capacitor TDK C1608X7R1H104K 0603 0.1 µF, 50V C5, C6 Ceramic Capacitor TDK C1608X7R1H223K 0603 0.022 µF, 50V C7, C8 Ceramic Capacitor TDK C3216X7R1C106K 1206 10 µF, 16V C9 Ceramic Capacitor Unpopulated 0603 C10 Ceramic Capacitor Unpopulated 0603 D1 Schottky Diode Zetex ZLLS2000 SOT23-6 40V, 2.2A L1 Power Inductor Bussman DR73-150 7.6 mm x 7.6 mm 15 µH, 1.8A R1 Resistor Vishay CRCW06034322F 0603 43.2 kΩ R2, R3 Resistor Vishay CRCW06032491F 0603 2.49 kΩ R4 Resistor Panasonic ERJ3RQFR39 0603 0.39Ω R5 Resistor Unpopulated 0603 R6 Resistor Vishay CRCW08050000Z 0805 U1 Switching Regulator LM34919 10 Bump DSBGA SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback 0Ω Jumper AN-1650 LM34919 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 5 Circuit Performance 9 www.ti.com Circuit Performance Figure 6. Efficiency vs Load Current Figure 7. Efficiency vs Input Voltage Figure 8. Output Voltage Ripple 6 AN-1650 LM34919 Evaluation Board SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Circuit Performance www.ti.com Figure 9. Switching Frequency vs. Input Voltage Figure 10. Load Current Limit vs Input Voltage SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback AN-1650 LM34919 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 7 Typical Waveforms 10 www.ti.com Typical Waveforms Trace 4 = VOUT Trace 3 = inductor Current Trace 2 = SW Pin Vin = 24V, Iout = 400 mA Figure 11. Continuous Conduction Mode Trace 4 = VOUT Trace 3 = inductor Current Trace 2 = SW Pin Vin = 24V, Iout = 20 mA Figure 12. Discontinuous Conduction Mode 8 AN-1650 LM34919 Evaluation Board SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated PC Board Layout www.ti.com 11 PC Board Layout Figure 13. Board Silkscreen Figure 14. Board Top Layer SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback AN-1650 LM34919 Evaluation Board Copyright © 2007–2013, Texas Instruments Incorporated 9 PC Board Layout www.ti.com Figure 15. Board Second Layer (Viewed from Top) 10 AN-1650 LM34919 Evaluation Board SNVA250A – June 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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