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LM34927
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
适用于隔离式直流/直
直流转换器的 LM34927 集成式二次侧偏置稳压器
1 特性
•
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1
3 说明
7.5V 至 100V 宽输入电压范围
集成 600mA 高侧和低侧开关
无需肖特基二极管
恒定导通时间控制
无需环路补偿
超快瞬态响应
接近恒定的运行频率
智能峰值电流限制
可调节输出电压（以 1.225V 为基准电压）
2% 的反馈基准电压精度
频率可调至 1MHz
可调低压闭锁 (UVLO)
远程关断
热关断
封装：
– 8 引脚 WSON
– 8 引脚 SO PowerPAD™
LM34927 稳压器 具有 实现低成本高效率的隔离式偏
置稳压器所需的全部功能。此高压稳压器包含两个
100V N 沟道 MOSFET 开关 – 一个高侧降压开关和一
个低侧同步开关。LM34927 器件所采用的恒定导通时
间 (COT) 控制方案无需环路补偿，且可提供出色的瞬
态响应。此稳压器的运行接通时间与输入电压成反比。
此特性使得工作频率能够保持相对恒定。使用集成感测
电路来执行智能峰值电流限制。其他 特性 包括一个用
于抑制低压条件下运行的可编程输入欠压比较器。保护
特性 包括热关断和 VCC 欠压锁定 (UVLO)。LM34927
器件采用 WSON-8 和 SO PowerPAD-8 塑料封装。
器件信息(1)
器件型号
LM34927
封装尺寸（标称值）
4.89mm × 3.90mm
WSON (8)
4.00mm x 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
空白
2 应用
•
•
封装
SO PowerPAD (8)
空白
隔离式电信偏压电源
隔离式汽车和工业用电子元件
典型应用
D1
VOUT2
+
LM34927
VIN
9V-100V
CIN
2
+
4
RUV2
BST
VIN
RON
VCC
UVLO
FB
RUV1
RTN
1
COUT2
7
+
SW 8
RON
3
NS
X1
CBST
VOUT1
NP
6
D2
5
+
CVCC
Rr
RFB2
+
RFB1
COUT1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVS799
LM34927
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
10.3 Thermal Curves..................................................... 21
11 器件和文档支持 ..................................................... 22
11.1
11.2
11.3
11.4
11.5
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
22
22
22
22
22
12 机械、封装和可订购信息 ....................................... 22
4 修订历史记录
Changes from Revision G (December 2014) to Revision H
Page
•
Deleted lead temperature from Abs Max table ...................................................................................................................... 5
•
Changed 14 V to 13 V in VCC Regulator section ................................................................................................................. 12
Changes from Revision F (December 2013) to Revision G
Page
•
已添加 引脚配置和功能 部分、ESD 额定值 表、特性 说明、器件功能模式、应用和实施、电源相关建议、布局、器件
和文档支持以及机械、封装和可订购信息部分 ........................................................................................................................ 1
•
Changed Thermal Information table ....................................................................................................................................... 5
•
Changed TON vs VIN and RON in Typical Characteristics ....................................................................................................... 7
•
Deleted 3-W Isolated Bias Application Schematic, Lowest Part Count Isolated Application Schematic, and Typical
Buck Configuration graphics................................................................................................................................................... 9
•
Changed Control Overview section ...................................................................................................................................... 11
•
Changed Soft-Start Circuit, Isolated Fly-Buck Converter graphics. ..................................................................................... 15
Changes from Revision E (December 2013) to Revision F
Page
•
Added Thermal Parameters. .................................................................................................................................................. 5
•
Added Thermal Derating Curve............................................................................................................................................ 21
2
版权 © 2012–2017, Texas Instruments Incorporated
LM34927
www.ti.com.cn
Changes from Revision D (September 2013) to Revision E
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
Page
•
已更改 将特性和典型应用 中的最小工作输入电压由 9V 更改成了 7.5V；将格式更改为 TI 标准 ........................................... 1
•
Added abs max junction temp; changed min op. input V from 9 to 7.5 V in ROC table ........................................................ 5
Changes from Revision C (July 2013) to Revision D
•
Page
Added SW to RTN (100-ns transient) to Absolute Maximum Ratings .................................................................................. 5
Copyright © 2012–2017, Texas Instruments Incorporated
3
LM34927
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
www.ti.com.cn
5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
RTN
1
VIN
2
UVLO
3
RON
4
SO
PowePAD-8
Exp Pad
8
SW
7
BST
6
VCC
5
FB
Connect Exposed Pad to RTN
8-Pin WSON With Exposed Thermal Pad
NGU Package
Top View
RTN
1
VIN
2
UVLO
3
RON
4
8 SW
WSON-8
Exp Pad
7 BST
6 VCC
5 FB
Pin Functions
PIN
NO.
NAME
I/O
1
RTN
—
2
VIN
DESCRIPTION
APPLICATION INFORMATION
Ground
Ground connection of the integrated circuit.
I
Input voltage
Operating input range is 7.5 V to 100 V.
Resistor divider from VIN to UVLO to GND programs the
undervoltage detection threshold. An internal current source is
enabled when UVLO is above 1.225 V to provide hysteresis.
When UVLO pin is pulled below 0.66 V externally, the parts goes
in shutdown mode.
3
UVLO
I
Input pin of undervoltage
comparator
4
RON
I
On-time control
A resistor between this pin and VIN sets the switch on-time as a
function of VIN. Minimum recommended on-time is 100 ns at max
input voltage.
5
FB
I
Feedback
This pin is connected to the inverting input of the internal
regulation comparator. The regulation level is 1.225 V.
6
VCC
O
Output from the internal high
voltage series pass regulator;
regulated at
7.6 V.
7
BST
I
Bootstrap capacitor
An external capacitor is required between the BST and SW pins
(0.01-μF ceramic). The BST pin capacitor is charged by the VCC
regulator through an internal diode when the SW pin is low.
8
SW
O
Switching node
Power switching node. Connect to the output inductor and
bootstrap capacitor.
—
EP
—
Exposed pad
Exposed pad must be connected to RTN pin. Connect to system
ground plane on application board for reduced thermal resistance.
4
The internal VCC regulator provides bias supply for the gate
drivers and other internal circuitry. A 1.0-μF decoupling capacitor
is recommended.
Copyright © 2012–2017, Texas Instruments Incorporated
LM34927
www.ti.com.cn
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
MIN
MAX
UNIT
VIN, UVLO to RTN
–0.3
100
V
SW to RTN
–1.5
VIN + 0.3
V
–5
VIN + 0.3
V
100
V
SW to RTN (100-ns transient)
BST to VCC
BST to SW
13
V
RON to RTN
–0.3
100
V
VCC to RTN
–0.3
13
V
FB to RTN
–0.3
Maximum junction temperature (2)
Storage temperature range
(1)
(2)
–55
5
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN voltage
7.5
100
V
Operating junction temperature (1)
–40
125
°C
(1)
UNIT
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM34927
THERMAL METRICS
(1)
NGU (WSON)
DDA (SO
PowerPAD)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
41.3
41.1
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
3.2
2.4
°C/W
ΨJB
Junction-to-board thermal characteristic parameter
19.2
24.4
°C/W
RθJB
Junction-to-board thermal resistance
19.1
30.6
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
34.7
37.3
°C/W
ΨJT
Junction-to-top thermal characteristic parameter
0.3
6.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2012–2017, Texas Instruments Incorporated
5
LM34927
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
www.ti.com.cn
6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range, unless otherwise stated. VIN = 48 V unless otherwise stated. See (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.25
7.6
8.55
UNIT
VCC SUPPLY
VCC Reg
VCC Regulator Output
VIN = 48 V, ICC = 20 mA
VCC Current Limit
VIN = 48 V (2)
26
VCC UVLO Threshold (VCC increasing)
4.15
VCC UVLO Hysteresis
4.5
4.9
300
VCC Dropout Voltage
VIN = 8 V, ICC = 20 mA
IIN Operating Current
Non-switching, FB = 3 V
IIN Shutdown Current
UVLO = 0 V
V
mA
V
mV
2.3
V
1.75
mA
50
225
µA
UNDERVOLTAGE SENSING FUNCTION
UV Threshold
UV Rising
1.19
1.225
1.26
V
UV Hysteresis Input Current
UV = 2.5 V
–10
–20
–29
µA
Remote Shutdown Threshold
Voltage at UVLO Falling
0.32
0.66
V
110
mV
Remote Shutdown Hysteresis
REGULATION AND OVERVOLTAGE COMPARATORS
FB Regulation Level
Internal Reference Trip Point for Switch ON
FB Overvoltage Threshold
Trip Point for Switch OFF
1.2
FB Bias Current
1.225
1.25
V
1.62
V
60
nA
SWITCH CHARACTERISTICS
Buck Switch RDS(ON)
ITEST = 200 mA, BST-SW = 7 V
Synchronous RDS(ON)
ITEST = 200 mA
Gate Drive UVLO
VBST − VSW Rising
2.4
Gate Drive UVLO Hysteresis
0.8
1.8
Ω
0.45
1
Ω
3
3.6
V
260
mV
CURRENT LIMIT
Current Limit Threshold
0.7
Current Limit Response Time
Time to switch off
OFF-Time Generator (Test 1)
OFF-Time Generator (Test 2)
1.02
1.3
A
150
ns
FB = 0.1 V, VIN = 48 V
12
µs
FB = 1.0 V, VIN = 48 V
2.5
µs
165
°C
20
°C
THERMAL SHUTDOWN
Tsd
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
(1)
(2)
6
All limits are specified by design. All electrical characteristics having room temperature limits are tested during production at TA = 25°C.
All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
Copyright © 2012–2017, Texas Instruments Incorporated
LM34927
www.ti.com.cn
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
6.6 Switching Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. VIN = 48 V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ON-TIME GENERATOR
TON Test 1
VIN = 32 V, RON = 100 kΩ
270
350
460
ns
TON Test 2
VIN = 48 V, RON = 100 kΩ
188
250
336
ns
TON Test 3
VIN = 75 V, RON = 250 kΩ
250
370
500
ns
TON Test 4
VIN = 10 V, RON = 250 kΩ
1880
3200
4425
ns
MINIMUM OFF-TIME
Minimum Off-Timer
FB = 0 V
144
ns
6.7 Typical Characteristics
Figure 1. Efficiency at 750 kHz, VOUT1 = 10 V
Figure 2. VCC vs VIN
Figure 3. VCC vs ICC
Figure 4. ICC vs External VCC
Copyright © 2012–2017, Texas Instruments Incorporated
7
LM34927
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
8
Figure 5. TON vs VIN and RON
Figure 6. TOFF (ILIM) vs VFB and VIN
Figure 7. IIN vs VIN (Operating, Non-switching)
Figure 8. IIN vs VIN (Shutdown)
Figure 9. Efficiency
Figure 10. Buck Transient Response 36 VIN
Copyright © 2012–2017, Texas Instruments Incorporated
LM34927
www.ti.com.cn
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
Typical Characteristics (continued)
Figure 11. Buck Transient Response 36 VIN
Figure 12. Buck Transient Response 48 VIN
Figure 13. Buck Transient Response 48 VIN
Figure 14. Buck Transient Response 72 VIN
Figure 15. Buck Transient Response 72 VIN
Copyright © 2012–2017, Texas Instruments Incorporated
9
LM34927
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The LM34927 step-down switching regulator features all the functions needed to implement a low-cost, efficient,
isolated-bias supply. This high-voltage regulator contains 100 V, N-channel buck and synchronous switches, is
easy to implement, and is provided in thermally enhanced SO PowerPAD-8 and WSON-8 packages. The
regulator operation is based on a constant on-time control scheme using an on-time inversely proportional to VIN.
This control scheme does not require loop compensation. Current limit is implemented with forced off-time
inversely proportional to VOUT. This scheme ensures short-circuit protection while providing minimum foldback.
The simplified block diagram of the LM34927 device is shown in Functional Block Diagram.
The LM34927 device can be applied in numerous applications to efficiently regulate down higher voltages. This
regulator is well suited for 48-V telecom and automotive power bus ranges. Protection features include: thermal
shutdown, UVLO, minimum forced off-time, and an intelligent current limit.
7.2 Functional Block Diagram
LM34927
START-UP
REGULATOR
VIN
VCC
V UVLO
20 µA
4.5V
UVLO
THERMAL
SHUTDOWN
UVLO
1.225V
SD
VDD REG
BST
0.66V
SHUTDOWN
BG REF
VIN
DISABLE
ON/OFF
TIMERS
RON
1.225V
SW
COT CONTROL
LOGIC
FEEDBACK
FB
OVER-VOLTAGE
1.62V
RTN
10
CURRENT
LIMIT
ONE-SHOT
ILIM
COMPARATOR
+
VILIM
Copyright © 2012–2017, Texas Instruments Incorporated
LM34927
www.ti.com.cn
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
7.3 Feature Description
7.3.1 Control Overview
The LM34927 regulator employs a control principle based on a comparator and a one-shot on-timer, with the
output voltage feedback (FB) compared to an internal reference (1.225 V). If the FB voltage is below the
reference the internal buck switch is switched on for the one-shot timer period, which is a function of the input
voltage and the programming resistor (RT). Following the on-time the switch remains off until the FB voltage falls
below the reference, and the forced minimum off-time has expired. When the FB pin voltage falls below the
reference and the off-time one-shot period expires, the buck switch is then turned on for another on-time oneshot period. This continues until regulation is achieved and the FB voltage is approximately equal to 1.225 V
(typ).
In a synchronous buck converter, the low-side (sync) FET is on when the high side (buck) FET is off. The
inductor current ramps up when the high-side switch is on and ramps down when the high side switch is off.
There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative
direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of
the output loading. The operating frequency remains relatively constant with load and line variations. The
operating frequency can be calculated as shown in Equation 1.
VOUT1
f SW =
. x RON
(1)
Where K = 9 × 10–11
The output voltage (VOUT) is set by two external resistors ®FB1, RFB2). The regulated output voltage is calculated
as shown in Equation 2.
VOUT = 1.225V x
RFB2 + RFB1
RFB1
(2)
This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor ©OUT). A minimum of 25 mV of ripple voltage at the feedback pin (FB) is
required for the LM34927 device. In cases where the capacitor ESR is too small, additional series resistance
may be required ®C in Figure 16).
For applications where lower output voltage ripple is required, the output can be taken directly from a low ESR
output capacitor, as shown in Figure 16. However, RC slightly degrades the load regulation.
L1
VOUT
SW
LM34927
RFB2
FB
RC
+
RFB1
COUT
VOUT
(low ripple)
Figure 16. Low Ripple Output Configuration
7.3.2 VCC Regulator
The LM34927 device contains an internal high voltage linear regulator with a nominal output of 7.6 V. The input
pin (VIN) can be connected directly to the line voltages up to 100 V. The VCC regulator is internally current limited
to 30 mA. The regulator sources current into the external capacitor at VCC. This regulator supplies current to
internal circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the
VCC pin reaches the UVLO threshold of 4.5 V, the IC is enabled.
The VCC regulator contains an internal diode connection to the BST pin to replenish the charge in the gate drive
boot capacitor when SW pin is low.
Copyright © 2012–2017, Texas Instruments Incorporated
11
LM34927
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
www.ti.com.cn
Feature Description (continued)
At high input voltages, the power dissipated in the high-voltage regulator is significant and can limit the overall
achievable output power. As an example, with the input at 48 V and switching at high frequency, the VCC
regulator may supply up to 7 mA of current resulting in 48 V × 7 mA = 336 mW of power dissipation. If the VCC
voltage is driven externally by an alternate voltage source, from 8.55 V to 13 V, the internal regulator is disabled.
This reduces the power dissipation in the IC.
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 1.225 V reference. In normal operation, when the output
voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225 V. The high-side
switch will stay on for the on-time, causing the FB voltage to rise above 1.225 V. After the on-time period, the
high-side switch will stay off until the FB voltage again falls below 1.225 V. During start-up, the FB voltage will be
below 1.225 V at the end of each on-time causing the high-side switch to turn on immediately after the minimum
forced off-time of 144 ns. The high-side switch can be turned off before the on-time is over if peak current in the
inductor reaches the current limit threshold.
7.3.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 1.62-V reference. If the voltage at FB rises above 1.62 V
the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load
changes suddenly. The high-side switch will not turn on again until the voltage at FB falls below 1.225 V.
7.3.5 On-Time Generator
The on-time for the LM34927 device is determined by the RON resistor, and is inversely proportional to the input
voltage (VIN), resulting in a nearly constant frequency as VIN is varied over its range. The on-time equation for the
LM34927 device is shown in Equation 3.
TON =
10-10 x RON
VIN
(3)
See Figure 5. RON should be selected for a minimum on-time (at maximum VIN) greater than 100 ns for proper
operation. This requirement limits the maximum frequency for each application.
7.3.6 Current Limit
The LM34927 device contains an intelligent current limit off-timer. If the current in the buck switch exceeds
1.02 A, the present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of offtime is controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0 V and VIN = 48 V, a
maximum off-time is set to 16 μs. This condition occurs when the output is shorted, and during the initial part of
start up. This amount of time ensures safe short circuit operation up to the maximum input voltage of
100 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is
reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and
start-up time. The off-time is calculated from Equation 4.
TOFF(ILIM)
0.07 u VIN
Ps
VFB 0.2 V
(4)
The current limit protection feature is peak limited, the maximum average output will be less than the peak.
7.3.7 N-Channel Buck Switch and Driver
The LM34927 device integrates an N-Channel Buck switch and associated floating high-voltage gate driver. The
gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage diode. A
0.01-µF ceramic capacitor connected between the BST pin and SW pin provides the voltage to the driver during
the on-time. During each off-time, the SW pin is at approximately 0 V and the bootstrap capacitor charges from
VCC through the internal diode. The minimum off-timer, set to 144 ns, ensures a minimum time each cycle to
recharge the bootstrap capacitor.
12
Copyright © 2012–2017, Texas Instruments Incorporated
LM34927
www.ti.com.cn
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
Feature Description (continued)
7.3.8 Synchronous Rectifier
The LM34927 device provides an internal synchronous N-channel MOSFET rectifier. This MOSFET provides a
path for the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous
conduction mode even during light loads which would otherwise result in discontinuous operation. This feature
specifically lets the user design a secondary regulator using a transformer winding off the main inductor to
generate the alternate regulated output voltage.
7.3.9 Undervoltage Detector
The LM34927 device contains a dual-level UVLO circuit. When the UVLO pin voltage is below 0.66 V, the
controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66 V but less than
1.225 V, the controller is in standby mode. In standby mode the VCC bias regulator is active while the regulator
output is disabled. When the VCC pin exceeds the VCC undervoltage thresholds and the UVLO pin voltage is
greater than 1.225 V, normal operation begins. An external set-point voltage divider from VIN to GND can be
used to set the minimum operating voltage of the regulator.
UVLO hysteresis is accomplished with an internal 20-μA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance
RUV2.
If the UVLO pin is wired directly to the VIN pin, the regulator will begin operation once the VCC undervoltage is
satisfied.
VIN
CIN
2
VIN
+
RUV2
LM34927
3
UVLO
RUV1
Figure 17. UVLO Resistor Setting
7.3.10 Thermal Protection
The LM34927 device should be operated so the junction temperature does not exceed 150°C during normal
operation. An internal Thermal Shutdown circuit is provided to protect the LM34927 in the event of a higher than
normal junction temperature. When activated, typically at 165°C, the controller is forced into a low-power reset
state, disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental
device overheating. When the junction temperature reduces below 145°C (typical hysteresis = 20°C), the VCC
regulator is enabled, and normal operation is resumed.
7.3.11 Ripple Configuration
LM34927 uses COT control scheme, in which the on-time is terminated by an on-timer, and the off-time is
terminated by the feedback voltage (VFB) falling below the reference voltage (VREF). Therefore, for stable
operation, the feedback voltage must decrease monotonically, in phase with the inductor current during the offtime. Furthermore this change in feedback voltage (ΔVFB) during off-time must be large enough to suppress any
noise component present at the feedback node.
Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1
and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output
voltage ripple has two components:
• Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
• Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.
Copyright © 2012–2017, Texas Instruments Incorporated
13
LM34927
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
www.ti.com.cn
Feature Description (continued)
The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
decreases monotonically during off-time. The resistive ripple must exceed the capacitive ripple at the output node
(VOUT) for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This
triangular ramp is ac coupled using Cac to the feedback node (FB). Because this circuit does not use the output
voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See AN-1481
Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs
(SNVA166) for more details for each ripple generation method.
Table 1. Ripple Configuration
TYPE 1
LOWEST COST CONFIGURATION
TYPE 2
REDUCED RIPPLE CONFIGURATION
TYPE 3
MINIMUM RIPPLE CONFIGURATION
VOUT
VOUT
L1
VOUT
L1
L1
Cac
R FB2
R FB2
RC
To FB
R FB1
R FB1
GND
25 mV VOUT
x
ûIL(MIN) VREF
Cr
R FB2
C OUT
Cac
To FB
C OUT
RC >
Rr
RC
GND
C OUT
To FB
R FB1
GND
C>
(5)
Cr = 3300 pF
Cac = 100 nF
(VIN(MIN) - VOUT) x TON
R rC r <
25 mV
5
gsw (RFB2||RFB1)
25 mV
RC >
ûIL(MIN)
(6)
(7)
7.3.12 Soft Start
A soft-start feature can be implemented with the LM34927 device using an external circuit. As shown in
Figure 18, the soft-start circuit consists of one capacitor C1, two resistors R1 and R2, and a diode D. During the
initial start-up, the VCC voltage is established prior to the VOUT voltage. Capacitor C1 is discharged and D is
thereby forward biased to pull up the FB voltage. The FB voltage exceeds the reference voltage (1.225 V) and
switching is therefore disabled. As capacitor C1 charges, the voltage at node B gradually decreases and
switching commences. VOUT will gradually rise to maintain the FB voltage at the reference voltage. Once the
voltage at node B is less than a diode drop above the FB voltage, the soft-start sequence is finished and D is
reverse biased.
During the initial part of the start up, the FB voltage can be approximated as shown in Equation 8. The effect of
R1 has been ignored to simplify the calculation.
VFB = (VCC - VD) x
RFB1 x RFB2
R2 x (RFB1 + RFB2) + RFB1 x RFB2
(8)
C1 is charged after the first start up. Diode D1 is optional and can be added to discharge C1 and initialize the
soft-start sequence when the input voltage experiences a momentary drop.
14
Copyright © 2012–2017, Texas Instruments Incorporated
LM34927
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ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
To achieve the desired soft start, the following design guidance is recommended:
• R2 is selected so that VFB is higher than 1.225 V for a VCC of 4.5 V, but is lower than 5 V when VCC is 8.55 V.
If an external VCC is used, VFB should not exceed 5 V at maximum VCC.
• C1 is selected to achieve the desired start-up time which can be determined from Equation 9.
RFB1 x RFB2
)
tS = C1 x (R2 +
RFB1 + RFB2
(9)
• R1 is used to maintain the node B voltage at zero after the soft start is finished. A value larger than the
feedback resistor divider is preferred. The effect of resistor R1 is ignored.
Using component values shown in Figure 19, selecting C1 = 1 µF, R2 = 1 kΩ, R1 = 30 kΩ results in a soft-start
time of about 2 ms.
VOUT
VCC
C1
RFB2
R2
To FB
D
D1
B
RFB1
R1
Figure 18. Soft-Start Circuit
7.4 Device Functional Modes
Table 2. Undervoltage Detector
UVLO
VCC
MODE
DESCRIPTION
< 0.66 V
Disabled
Shutdown
VCC regulator disabled.
Switching disabled.
0.66 V to 1.225 V
Enabled
Standby
VCC regulator enabled.
Switching disabled.
VCC < 4.5 V
Standby
VCC regulator enabled.
Switching disabled.
VCC > 4.5 V
Operating
> 1.225 V
Copyright © 2012–2017, Texas Instruments Incorporated
VCC enabled.
Switching enabled.
15
LM34927
ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM34927 device is step-down DC-DC converter. The device is typically used to convert a higher DC voltage
to a lower DC voltage with a maximum available output current of 600 mA. Use the following design procedure to
select component values for the LM34927 device. Alternately, use the WEBENCH® software to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Applications
8.2.1 Application Circuit: 20-V to 95-V Input and 10-V, 300-mA Output Isolated Fly-Buck™ Converter
VOUT2
D1
+
N2
X1
1:1
LM34927
BST
VIN
20V-95V
0.01 µF
+
CBST
+
N1
33 µH
VOUT1
SW
46.4 NŸ 1 nF
Rr
Cr
VIN
CIN
2.2 µF
COUT2
1 µF
CBYP
0.47 µF
+
RON
RUV2
127 NŸ
RON
130 NŸ
RUV1
8.25 NŸ
0.1 µF
RTN
COUT1
1 µF
RFB2
VCC
UVLO
+
Cac
FB
+
D2
7.32 NŸ
CVCC
1 µF
RFB1
1 NŸ
Figure 19. Isolated Fly-Buck Converter Using LM34927
8.2.1.1 Design Requirements
Selection of external components is illustrated through a design example. The design example specifications are
shown in Table 3.
Table 3. Buck Converter Design Specifications
DESIGN PARAMETERS
Input voltage range
VALUE
20 V to 95 V
Primary output voltage
10 V
Secondary (isolated) output voltage
9.5 V
Maximum output current (primary + secondary)
Maximum power output
Nominal switching frequency
16
300 mA
3W
750 kHz
Copyright © 2012–2017, Texas Instruments Incorporated
LM34927
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ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Transformer Turns Ratio
The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary
(isolated) output voltage. In this design example, the two outputs are nearly equal and a 1:1 turns ratio
transformer is selected. Therefore, N2 / N1 = 1.
If the secondary (isolated) output voltage is significantly higher or lower than the primary output voltage, a turns
ratio less than or greater than 1 is recommended. The primary output voltage is normally selected based on the
input voltage range such that the duty cycle of the converter does not exceed 50% at the minimum input voltage.
This condition is satisfied if VOUT1 < VIN_MIN / 2.
8.2.1.2.2 Total IOUT
The total primary referred load current is calculated by multiplying the isolated output loads by the turns ratio of
the transformer as shown in Equation 10.
IOUT(MAX)
IOUT1 IOUT2 u
N2
N1
0.3 A
(10)
8.2.1.2.3 RFB1, RFB2
The feedback resistors are selected to set the primary output voltage. The selected value for RFB1 is 1 kΩ. RFB2
can be calculated using the following equations to set VOUT1 to the specified value of 10 V. A standard resistor
value of 7.32 kΩ is selected for RFB2.
VOUT1 = 1.225V x (1 +
RFB2
)
RFB1
(11)
VOUT1
- 1) x RFB1 = 7.16 k:
: RFB2 = (
1.225
(12)
8.2.1.2.4 Frequency Selection
Equation 13 is used to calculate the value of RON required to achieve the desired switching frequency.
VOUT1
f SW =
. x RON
where
K = 9 × 10–11
(13)
VOUT1 of 10 V and fSW of 750 kHz, the calculated value of RON is 148 kΩ. A lower value of 130 kΩ is selected for
this design to allow for second-order effects at high switching frequency that are not included in Equation 13.
8.2.1.2.5 Transformer Selection
A coupled inductor or a flyback-type transformer is required for this topology. Energy is transferred from primary
to secondary when the low-side synchronous switch of the buck converter is conducting.
The maximum inductor primary ripple current that can be tolerated without exceeding the buck switch peak
current limit threshold (0.7 A minimum) is given by Equation 14.
'IL1
N2 ·
§
¨ 0.7 IOUT1 IOUT2 u N1 ¸ u 2
©
¹
0.8 A
(14)
Using the maximum peak-to-peak inductor ripple current ΔIL1 from Equation 14, the minimum inductor value is
given by Equation 15.
L1
VIN(MAX)
VOUT
'IL1 u fSW
u
VOUT
VIN(MAX)
14.9 PH
(15)
A higher value of 33 µH is selected to insure the high-side switch current does not exceed the minimum peak
current limit threshold. With this inductance, the inductor current ripple is ΔIL1= 0.36 A at the maximum VIN.
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8.2.1.2.6 Primary Output Capacitor
In a conventional buck converter the output ripple voltage is calculated as shown in Equation 16.
f
'VOUT =
'IL1
x f x COUT1
(16)
To limit the primary output ripple voltage ΔVOUT1 to approximately 50 mV, an output capacitor COUT1 of 1.2 µF
would be required for a conventional buck.
Figure 20 shows the primary winding current waveform (IL1) of a Fly-Buck converter. The reflected secondary
winding current adds to the primary winding current during the buck switch off-time. Because of this increased
current, the output voltage ripple is not the same as in conventional buck converter. The output capacitor value
calculated in Equation 16 should be used as the starting point. Optimization of output capacitance over the entire
line and load range must be done experimentally. If the majority of the load current is drawn from the secondary
isolated output, a better approximation of the primary output voltage ripple is given by Equation 17.
'VOUT1
N2 ·
§
¨ IOUT2 u N1 ¸ u TON(MAX)
©
¹
| 67 mV
COUT1
(17)
TON(MAX) x IOUT2 x N2/N1
IL1
IOUT2
IL2
TON(MAX) x IOUT2
Figure 20. Current Waveforms for COUT1 Ripple Calculation
A standard 1-µF, 25-V capacitor is selected for this design. If lower output voltage ripple is required, a higher
value should be selected for COUT1 and/or COUT2.
8.2.1.2.7 Secondary Output Capacitor
A simplified waveform for secondary output current (IOUT2) is shown in Figure 21.
IOUT2
IL2
TON(MAX) x IOUT2
Figure 21. Secondary Current Waveforms for COUT2 Ripple Calculation
The secondary output current (IOUT2) is sourced by COUT2 during on-time of the buck switch, TON. Ignoring the
current transition times in the secondary winding, the secondary output capacitor ripple voltage can be calculated
using Equation 18.
IOUT2 x TON (MAX)
'VOUT2 =
COUT2
(18)
For a 1:1 transformer turns ratio, the primary and secondary voltage ripple equations are identical. Therefore,
COUT2 is chosen to be equal to COUT1 (1 µF) to achieve comparable ripple voltages on primary and secondary
outputs.
If lower output voltage ripple is required, a higher value should be selected for COUT1 and/or COUT2.
18
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LM34927
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ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
8.2.1.2.8 Type III Feedback Ripple Circuit
Type III ripple circuit as described in Ripple Configuration is required for the Fly-Buck topology. Type I and Type
II ripple circuits use series resistance and the triangular inductor ripple current to generate ripple at VOUT and the
FB pin. The primary ripple current of a Fly-Buck is the combination or primary and reflected secondary currents
as illustrated in Figure 20. In the Fly-Buck topology, Type I and Type II ripple circuits suffer from large jitter as the
reflected load current affects the feedback ripple.
VOUT
L1
Rr
Cac
C OUT
Cr
R FB2
GND
To FB
R FB1
Figure 22. Type III Ripple Circuit
Selecting the Type III ripple components using the equations from Ripple Configuration will ensure that the FB
pin ripple is be greater than the capacitive ripple from the primary output capacitor COUT1. The feedback ripple
component values are chosen as shown in Equation 19.
Cr = 1000 pF
Cac = 0.1 PF
RrCr d
(VIN (MIN) - VOUT) x TON
50 mV
(19)
The calculated value for Rr is 66 kΩ. This value provides the minimum ripple for stable operation. A smaller
resistance should be selected to allow for variations in TON, COUT1 and other components. For this design, Rr
value of 46.4 kΩ is selected.
8.2.1.2.9 Secondary Diode
The reverse voltage across secondary-rectifier diode D1 when the high-side buck switch is off can be calculated
using Equation 20.
VD1 =
N2
VIN
N1
(20)
For a VIN_MAX of 95 V and the 1:1 turns ratio of this design, a 100-V Schottky is selected.
8.2.1.2.10 VCC and Bootstrap Capacitor
A 1-µF capacitor of 16 V or higher rating is recommended for the VCC regulator bypass capacitor.
A good value for the BST pin bootstrap capacitor is 0.01-µF with a voltage rating of 16 or higher.
8.2.1.2.11 Input Capacitor
The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a
larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a
desired amplitude. For input ripple voltage ΔVIN, CIN can be calculated using Equation 21.
CIN t
IOUT(MAX)
4 u ¦ u '9IN
(21)
Choosing a ΔVIN of 0.5 V gives a minimum CIN of 0.2 μF. A standard value of 0.47 μF is selected for CBYP in this
design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the power
source to the converter. A standard value of 2.2 μF is selected for CIN in this design. The voltage ratings of the
two input capacitors should be greater than the maximum input voltage under all conditions.
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8.2.1.2.12 UVLO Resistors
UVLO resistors RUV1 and RUV2 set the undervoltage lockout threshold and hysteresis according to Equation 22
and Equation 23.
VIN (HYS) = IHYS x RUV2
(22)
VIN (UVLO, rising) = 1.225V x
R
( RUV2
+ 1)
(23)
UV1
Where IHYS = 20 μA, typical.
For a UVLO hysteresis of 2.5 V and UVLO rising threshold of 20 V, Equation 22 and Equation 23 require RUV1 of
8.25 kΩ and RUV2 of 127 kΩ and these values are selected for this design example.
8.2.1.2.13 VCC Diode
Diode D2 is an optional diode connected between VOUT1 and the VCC regulator output pin. When VOUT1 is more
than one diode drop greater than the VCC voltage, the VCC bias current is supplied from VOUT1. This results in
reduced power losses in the internal VCC regulator which improves converter efficiency. VOUT1 must be set to a
voltage at least one diode drop higher than 8.55 V (the maximum VCC voltage) if D2 is used to supply bias
current.
8.2.1.3 Application Curves
Figure 23. Efficiency at 750 kHz, VOUT1 = 10 V
Figure 24. Steady State Waveform (VIN = 48 V, IOUT1 = 100
mA, IOUT2 = 200 mA)
Figure 25. Step Load Response (VIN = 48 V, IOUT1 = 0, Step Load on IOUT2 = 100 mA to 200 mA)
20
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LM34927
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ZHCSBB6H – APRIL 2012 – REVISED NOVEMBER 2017
9 Power Supply Recommendations
LM34927 is a power-management device. The power supply for the device is any dc voltage source within the
specified input range.
10 Layout
10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should
be observed:
1. CIN: The loop consisting of input capacitor ©IN), VIN pin, and RTN pin carries switching currents. Therefore,
place the input capacitor close to the IC, directly across VIN and RTN pins and the connections to these two
pins should be direct to minimize the loop area. In general it is not possible to accommodate all of input
capacitance near the IC. A good practice is to use a 0.1-µF or 0.47-μF capacitor directly across the VIN and
RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Placement of Bypass
Capacitors ).
2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high- and
low-side gate drivers. These two capacitors must also be placed as close to the IC as possible, and the
connecting trace lengths and loop area should be minimized (See Figure 26).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for
proper operation of LM34927 device. Therefore take care while routing the feedback trace so avoid coupling
any noise to this pin. In particular, feedback trace should not run close to magnetic components, or parallel to
any other switching trace.
4. SW trace: SW node switches rapidly between VIN and GND every cycle and is therefore a possible source of
noise. SW node area should be minimized. In particular SW node should not be inadvertently connected to a
copper plane or pour.
10.2 Layout Example
RTN
1
VIN
2
8
SW
7
BST
CIN
SO
PowerPAD-8
UVLO
3
6
VCC
RON
4
5
FB
CVCC
Figure 26. Placement of Bypass Capacitors
10.3 Thermal Curves
0.7
Output Current (A)
0.6
0.5
VIN=54V
fsw=125kHz
VOUT=3.3V
L=220uH
0.4
0.3
0.2
500LFM
200LFM
100LFM
No Flow
0.1
0.0
0
20
40
60
80
100
120
Ambient Temperature (ƒC)
140
C003
Figure 27. Thermal Derating Curve
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LM34927
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www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
PowerPAD, Fly-Buck, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
22
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PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2025
PACKAGING INFORMATION
Orderable part number
(1)
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
LM34927MR/NOPB
Active
Production
SO PowerPAD
(DDA) | 8
95 | TUBE
Yes
NIPDAU | SN
Level-3-260C-168 HR
-40 to 125
L34927
LM34927MR/NOPB.A
Active
Production
SO PowerPAD
(DDA) | 8
95 | TUBE
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 125
L34927
LM34927MR/NOPB.B
Active
Production
SO PowerPAD
(DDA) | 8
95 | TUBE
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 125
L34927
LM34927MRX/NOPB
Active
Production
SO PowerPAD
(DDA) | 8
2500 | LARGE T&R
Yes
NIPDAU | SN
Level-3-260C-168 HR
-40 to 125
L34927
LM34927MRX/NOPB.A
Active
Production
SO PowerPAD
(DDA) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 125
L34927
LM34927MRX/NOPB.B
Active
Production
SO PowerPAD
(DDA) | 8
2500 | LARGE T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 125
L34927
LM34927SD/NOPB
Active
Production
WSON (NGU) | 8
1000 | SMALL T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
L34927
LM34927SD/NOPB.A
Active
Production
WSON (NGU) | 8
1000 | SMALL T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
L34927
LM34927SD/NOPB.B
Active
Production
WSON (NGU) | 8
1000 | SMALL T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
L34927
LM34927SDX/NOPB
Active
Production
WSON (NGU) | 8
4500 | LARGE T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
L34927
LM34927SDX/NOPB.A
Active
Production
WSON (NGU) | 8
4500 | LARGE T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
L34927
LM34927SDX/NOPB.B
Active
Production
WSON (NGU) | 8
4500 | LARGE T&R
Yes
SN
Level-1-260C-UNLIM
-40 to 125
L34927
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(6)
23-May-2025
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM34927MRX/NOPB
SO
PowerPAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM34927MRX/NOPB
SO
PowerPAD
DDA
8
2500
330.0
12.5
6.4
5.2
2.1
8.0
12.0
Q1
LM34927SD/NOPB
WSON
NGU
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM34927SDX/NOPB
WSON
NGU
8
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM34927MRX/NOPB
SO PowerPAD
DDA
8
2500
356.0
356.0
36.0
LM34927MRX/NOPB
SO PowerPAD
DDA
8
2500
353.0
353.0
32.0
LM34927SD/NOPB
WSON
NGU
8
1000
208.0
191.0
35.0
LM34927SDX/NOPB
WSON
NGU
8
4500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2025
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM34927MR/NOPB
DDA
HSOIC
8
95
507.79
LM34927MR/NOPB
DDA
HSOIC
8
95
495
8
630
4.32
8
4064
LM34927MR/NOPB.A
DDA
HSOIC
8
95
3.05
507.79
8
630
4.32
LM34927MR/NOPB.A
DDA
HSOIC
8
LM34927MR/NOPB.B
DDA
HSOIC
8
95
495
8
4064
3.05
95
495
8
4064
3.05
LM34927MR/NOPB.B
DDA
HSOIC
8
95
507.79
8
630
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
DDA0008B
PowerPAD TM SOIC - 1.7 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.2
TYP
5.8
A
SEATING PLANE
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.0
4.8
NOTE 3
4
5
8X
B
4.0
3.8
NOTE 4
0.51
0.31
0.25
1.7 MAX
C A B
0.25
TYP
0.10
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
3.4
2.8
0.25
GAGE PLANE
9
8
1
0 -8
0.15
0.00
1.27
0.40
DETAIL A
2.71
2.11
TYPICAL
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008B
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
9
SYMM
(1.3)
TYP
(3.4)
SOLDER MASK
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
( 0.2) TYP
VIA
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008B
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
1
8
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
9
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.150
0.175
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
NGU0008B
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
(0.1) TYP
1.98 0.05
4
2X
2.4
5
SYMM
9
3 0.05
8
1
6X 0.8
PIN 1 ID
8X
SYMM
0.35
0.25
0.1
0.05
0.5
8X
0.3
C A B
C
4214936/A 12/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NGU0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.98)
8X (0.6)
SYMM
1
8
8X (0.3)
SYMM
9
(3)
(1.25)
6X (0.8)
4
(R0.05) TYP
5
( 0.2) VIA
TYP
(0.74)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214936/A 12/2023
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
NGU0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
8X (0.6)
METAL
TYP
1
8
8X (0.3)
(0.755)
9
SYMM
(1.31)
6X (0.8)
5
4
(R0.05) TYP
(1.75)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4214936/A 12/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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