User's Guide
SLOA172B – June 2012 – Revised April 2013
AN-2250 LM3533 Evaluation Kit
1
Introduction
The LM3533 Evaluation Module (LM3533EVM) is designed to fully evaluate the LM3533 Dual String
backlight driver + 5 indicator LED driver. The LM3533EVM consists of the USB Interface Board and the
LM3533 Evaluation Board. The USB Interface Board Rev 1.1 provides the hardware link between a PC
and LM3533 Evaluation Board. On the PC side, the LM3533.exe software communicates to the
LM3533EVM to provide an easy control over all the features of the LM3533. Both the USB Interface Board
and the LM3533 Evaluation Board plug together at the USBL and USBR connectors and are keyed so the
boards can only fit together one way.
2
LM3533 Evaluation Board Schematics
IH2
1.8V/VI/O/VIN
IH1
VUSB/VL
VIN
RSH1
(10:)
1.8V
RSCL
(4.7 k:)
RSDA
(4.7 k:)
RHWEN
(4.7 k:)
SCL
OVP
C4
CPOUT
C3 B3
IN
GND
SW
D4 D3
PWM
16
C+
HWEN
15
LVLED4
H2I
H1I
H2H
H1H
H2G
H1G
H2F
H1F
H2E
H1E
H2D
H1D
H2C
H1C
H2B
H1B
1
2
C-
LM3533
LVLED5
E4
H1J
USBR
A1
LVLED2
LVLED3
H2J
B1
SCL
E3
B2
SDA
E2
C1
HVLED1
SDA
USBL
LVLED1
D1 C2
INT
E1
ALS
2
D2
HVLED2
1
VL
RSH2
(10:)
B4
A2
A3
A4
CIN
(2.2 uF)
15
16
VIN/VL
H1A
H2A
VOUT
L1 (10 uH)
D1 (40V Schottky)
7
7
8
8
GND
6
6
CL
COUT (1 uF, 50V)
9
5
4
HL2
GND
9
5
4
HL1
VL
Figure 1. Boost Circuit with Dual 10 Series White LED Strings
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LM3533 Evaluation Board Schematics
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IL5
1.8V/VI/O/VIN
IL4
IL3
IL2
IL1
VIN
VUSB/VL
VL
RSL2 (10:)
RSL5 (10:)
RSL4 (10:) RSL3 (10:)
RSL1 (10:)
1.8V
RHWEN
(4.7 k:)
RSCL
(4.7 k:)
3
2
1
6
5
4
RGB
DL4
DL5
RSDA
(4.7 k:)
CP (1 PF)
D2
C1
B2
B1
SCL
SDA
HVLED1
C-
LM3533
C3
GND
C4
OVP
D3
SW
D4
PWM
HWEN
LVLED4
CPOUT
LVLED5
E4
16
CPOUT
A1
ANODES
1
C+
E3 LVLED3
15
C2
E2 LVLED2
SDA
USBL
HVLED2
E1 LVLED1
D1
INT
SCL
2
ALS
1
B3
B4
IN
2
A2
CPOUT
(1 PF)
A3
USBR
A4
CIN
(2.2 PF)
VIN/VL
15
16
L1 (10 PH)
GND
CL
GND
VL
Figure 2. Charge Pump and Low Voltage Indicator LEDs
2
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LM3533 Evaluation Board Schematics
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VUSB/VL
1.8V/VI/O/VIN
VL
RSASL
(10:)
RHWEN
(4.7 k:)
RSOL
(4.7 k:)
INT
PWM
SCL
CALS
SCL
D4
D3
C4
C3
CPOUT
OVP
LVLED4
B3
2
1
C-
GND
C1
(1 PF)
SCL
1.8V
SDA
VCC
LVLED3
SW
C3
(1 PF)
B1
A1
C+ A2
PWM
C2
(1 PF)
HVLED1
16
B2
LM3533
HWEN
E4
15
C1
LVLED2
LVLED5
LED
N/C
VSS
2.8V
E3
C2
INT
E2
LVLED1
HVLED2
E1
SDA
USBL
D1
D2
ALS1
(APDS9005)
IR
ALS2
(Not
Populated)
ALS
2
SDA
1
RINT2
RSCL
(4.7 k:)
RSDA
(4.7 k:)
VIN
B4
IN
USBR
A3
A4
15
16
CIN
(2.2 PF)
VIN/VL
2.8V EN1
GND
LDO
EN2
GND
GND
C4
(0.1 PF)
BYP
CL
VDD
INT2
PWM
SOL
HWEN
VALS
IALS-
IALS+
VL
GND
Figure 3. Ambient Light Sensor and Logic Pull-ups
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3
Bill of Materials
3
4
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Bill of Materials
Component
Symbol
Value
Manufacturer
Part #
Size/Package
(L x W x H)
LM3533
LED Driver
Texas
Instruments
LM3533
(2.015mm × 1.755mm x
0.6mm)
LDO
1.8V/2.8V dual linear
regulator
Texas
Instruments
LP3986
(1.55mm x 1.55mm x 0.6mm)
RGB
RGB Indicator LEDs
Kingbright
APF3236SURKZGQBDC
(3.6mm x 3.2mm x 1.1mm)
DL4, DL5
Red Indicator LED
Rohm
SML-310VTT86
0603
L1
10µH, ISAT = 1A, RL =
0.22Ω
TDK
VLF4014ST-100M1R0
(3.8mm x 3.6mmx 1.4mm)
CIN
2.2µF, 10V, X5R
TDK
C1005X5R1A225M
0402
COUT
1µF, 50V, X7R
TDK
C3216X7R1H105M
0805
CPOUT
1µF, 10V, X5R
TDK
C1005X5R1A105K
0402
CP
1µF, 10V, X5R
TDK
C1005X5R1A105K
0402
CL
10µF, 10V
TDK
C1608X5R1A106K
0603
C1 - C4
1µF, 10V, X5R
TDK
C1005X5R1A105K
0402
D1
Schottky, 40V, 250mA
On-Semi
NSR0240V2T1GOSCT-ND
SOD-523
H1A - H1J
White LED
Rohm
SML312WBCW1
0603
H2A - H2J
White LED
Rohm
SML312WBCW1
0603
ALS1
Ambient Light Sensor
Avago
APDS-9005-020
(1.6mm x 1.5mm x 0.55mm)
ALS2
Ambient Light Sensor
N/A
N/A
N/A
RHWEN
4.7kΩ
Vishay
CRCW06034K70JNEA
0603
RSDA
4.7kΩ
Vishay
CRCW06034K70JNEA
0603
RSCL
44.7kΩ
Vishay
CRCW06034K70JNEA
0603
RSOL
4.7kΩ
Vishay
CRCW06034K70JNEA
0603
RSASL
10Ω, 1%
Panasonic
ERJ-3EKF10R0V
0603
RSH1, RSH2
10Ω, 0.01%
Bourns
CRT0805-BY-10R0ELF
0805
RSL1 - RSL5
10Ω, 0.01%
Bourns
CRT0805-BY-10R0ELF
0805
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Board Layout
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4
Board Layout
Figure 4. Top Layer
Figure 5. Mid Layer 1
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Board Layout
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Figure 6. Mid Layer 2
Figure 7. Bottom Layer
6
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Board Set-Up
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5
Board Set-Up
The LM3533EVM requires jumpers installed at the following headers for proper operation:
1. 1.8V/VIO/VIN: The center pin (VIO) of this three position header connects to the top side of the pull-up
resistors (RSCL, RSDA, RSOL, and RHWEN). Jumper this pin to either the 1.8V output from the on
board LDO or to VIN.
2. VOUT: The VOUT header connects the LM3533's boost output to the top side of the high voltage LED
strings (HL1 and HL2)
3. VIN/VL: This header jumpers the voltage at VL to the LM3533's IN bump (VIN)
4. ANODES: This header jumpers the LM3533's charge pump output to the top side of the low voltage
indicator LEDs (RGB, DL4, and DL5)
Once the jumpers are installed, connect a 2.5V to 5.5V power supply to the banana plug inputs (VL) and
(GND).
6
USB Interface Board
The LM3533 Evaluation Board can be controlled via an I2C master by connecting directly to the I2C header
(SCL SDA) or it can be controlled with the USB Interface Board. The USB Interface Board requires the
use of the LM3533.exe software that operates from a PC.
To operate the LM3533 Evaluation Board with the USB Interface Board, ensure the LM3533 Evaluation
Board is connected to the USB Interface Board. The boards are keyed so they will only fit together one
way. Next, follow the jumper settings in Section 5. After this, apply power to the board and open the
LM3533.exe program. The LM3533.exe software is grouped into tabs, see the following sections for each
tab description.
7
LM3533 Graphical User Interface
Figure 8. Main Control Tab
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LM3533 Graphical User Interface
7.1
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Main Control Tab
The Main Control tab (Figure 8) contains the pulldown menu's and buttons for configuring the LM3533's
global registers. The main tab is separated into different sections, where each section represents a
specific register within the LM3533. When any of the pulldown menus or buttons are selected the specific
data will get written to the LM3533. The exception is for the Control Bank Enable Buttons. These must first
be selected and then the Enable Selected Control Banks button must be pressed to write the data. A
button that is pushed indicates a 1 is written to the register. A button un-pushed indicates a 0. Table 1
through Table 10 show the break down of each register in the Main Control Tab.
Table 1. Output Configuration 1 (0x10)
Bit [7:6]
LVLED3
Bits [5:4]
LVLED2
Bits [3:2]
LVLED1
Bit [1]
HVLED2
Bit 0
HVLED1
00 = LVLED3 is
controlled by Control
Bank C
00 = LVLED2 is
controlled by Control
Bank C
00 = LVLED1 is controlled
by Control Bank C
(Default)
0 = HVLED2 is
controlled by Control
Bank A
0 = HVLED1 is
controlled by Control
Bank A (Default)
01 = LVLED3 is
controlled by Control
Bank D
01 = LVLED2 is
controlled by Control
Bank D (Default)
01 = LVLED1 is controlled
by Control Bank D
1 = HVLED2 is
controlled by Control
Bank B (Default)
1 = HVLED1 is
controlled by Control
Bank B
10 = LVLED3 is
controlled by Control
Bank E (Default)
10 = LVLED2 is
controlled by Control
Bank E
10 = LVLED1 is controlled
by Control Bank E
11 = LVLED3 is
controlled by Control
Bank F
11 = LVLED2 is
controlled by Control
Bank F
11 = LVLED1 is controlled
by Control Bank F
Table 2. Output Configuration 2 (0x11)
Bits [3:2]
LVLED5
Bits [1:0]
LVLED4
00 = LVLED5 is controlled by Control Bank C
00 = LVLED4 is controlled by Control Bank C
01 = LVLED5 is controlled by Control Bank D
01 = LVLED4 is controlled by Control Bank D
10 = LVLED5 is controlled by Control Bank E
10 = LVLED4 is controlled by Control Bank E
11 = LVLED5 is controlled by Control Bank F (Default)
11 = LVLED4 is controlled by Control Bank F (Default)
Table 3. Charge Pump Control (0x26)
Bits [2:1]
Gain Select
Bit 0
Charge Pump Disable
0X = Automatic gain select (Default)
10 = Gain set at 1x
11 = Gain set at 2x
0 = Charge pump enabled (Default)
1 = Charge pump disabled (high impedance from IN to CPOUT)
Table 4. Start-Up/Shutdown (0x12)
Bits [5:3]
Start-up Transition Time
000 = 2.048ms (Default)
001 = 262ms
010 = 524ms
011 = 1.049s
100 = 2.097s
101 = 4.194s
110 = 8.389s
111 = 16.78s
Startup time is from when the device is enabled via I2C to when
the initial target current is reached.
8
Bits [2:0]
Shutdown Transition Time
000 = 2.048ms (Default)
001 = 262ms
010 = 524ms
011 = 1.049s
100 = 2.097s
101 = 4.194s
110 = 8.389s
111 = 16.78s
Shutdown ramp time is from when the device is shutdown via
I2C until the current sink ramps to 0.
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Table 5. Run Time Ramp (0x13)
Bits [5:3]
Transition Time Ramp Up
Bits [2:0]
Transition Time Ramp Down
000 = 2048µs (Default)
001 = 262ms
010 = 524ms
011 = 1.049s
100 =2.097s
101 = 4.194s
110 = 8.389s
111 = 16.78s
000 = 2048µs (Default)
001 = 262ms
010 = 524ms
011 = 1.049s
100 =2.097s
101 = 4.194s
110 = 8.389s
111 = 16.78s
Table 6. Control Bank Enable (0x27)
Bit 5
Control F Select
Bit 4
Control E Select
Bit 3
Control D Select
Bit 2
Control C Select
Bit 1
Control B Select
Bit 0
Control A Select
0 = Control Bank F 0 = Control Bank E 0 = Control Bank D 0 = Control Bank C 0 = Control Bank B 0 = Control Bank A is
is disabled
is disabled
is disabled
is disabled
is disabled (Default) disabled (Default)
(Default)
(Default)
(Default)
(Default)
1 = Control Bank F 1 = Control Bank E 1 = Control Bank D 1 = Control Bank C 1 = Control Bank B
is enabled
is enabled
is enabled
is enabled
is enabled
1 = Control Bank A is
enabled
Table 7. Anode Connect (0x25)
Bit 6
LVLED5 Anode
Connect
Bit 5
LVLED4 Anode
Connect
Bit 4
LVLED3 Anode
Connect
Bit 3
LVLED2 Anode
Connect
Bit 2
LVLED1 Anode
Connect
Bit 1
HVLED2
Anode
Connect
Bit 0
HVLED1
Anode
Connect
0 = LVLED5 LED
anode is not
connected to
CPOUT
0 = LVLED4 LED
anode is not
connected to
CPOUT
0 = LVLED3 LED
anode is not
connected to
CPOUT
0 = LVLED2
LED anode is
not connected to
CPOUT
0 = LVLED1 LED
anode is not
connected to
CPOUT
0 = HVLED2
LED string
anode is not
connected to
COUT
0 = HVLED1
LED string
anode is not
connected to
COUT
1 = LVLED5 LED
anode is
connected to
CPOUT (Default)
1 = LVLED4 LED
anode is
connected to
CPOUT (Default)
1 = LVLED3 LED
anode is
connected to
CPOUT (Default)
1 = LVLED2
LED anode is
connected to
CPOUT
(Default)
1 = LVLED1 LED
anode is
connected to
CPOUT (Default)
1 = HVLED2
LED string
anode is
connected to
COUT
(Default)
1 = HVLED1
LED string
anode is
connected to
COUT
(Default)
Table 8. OVP/Boost Frequency/PWM Polarity (0x2C)
Bit 3
PWM Polarity
0 = Active Low Polarity
1 = Active High Polarity (Default)
Bit [2:1]
Boost OVP Select
00
01
10
11
= 16V (Default)
= 24V
= 32V
= 40V
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Bit 1
Boost Frequency Select
0 = 500 kHz (Default)
1 = 1MHz
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Table 9. LED Open Fault (0xB0)
Bit 6
(LVLED5 )
0 = Normal
Operation
1 = Open
Bit 5
(LVLED4 )
0 = Normal
Operation
1 = Open
Bit 4
(LVLED3 )
0 = Normal
Operation
1 = Open
Bit 3
(LVLED2 )
0 = Normal
Operation
1 = Open
Bit 2
(LVLED1 )
Bit 1
(HVLED2 )
0 = Normal
Operation
1 = Open
0 = Normal
Operation
1 = Open
Bit 0
(HVLED1 )
0 = Normal
Operation
1 = Open
Table 10. LED Short Fault (0xB1)
Bit 6
(LVLED5 )
0 = Normal
Operation
1 = Short
10
Bit 5
(LVLED4 )
0 = Normal
Operation
1 = Short
Bit 4
(LVLED3 )
0 = Normal
Operation
1 = Short
Bit 3
(LVLED2 )
0 = Normal
Operation
1 = Short
Bit 2
(LVLED1 )
0 = Normal
Operation
1 = Short
AN-2250 LM3533 Evaluation Kit
Bit 1
(HVLED2 )
0 = Normal
Operation
1 = Short
Bit 0
(HVLED1 )
0 = Normal
Operation
1 = Short
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7.2
Bank A/B Control Tab
The Bank A/B Control Tab (Figure 9) contains all the register options that are unique to the High Voltage
Control Banks (A and B). Table 11 through Table 15 describe these registers.
Figure 9. Bank A/B Control Tab
Table 11. Bank A or Bank B PWM Configuration (0x14, 0x15)
Bit 5
Zone 4 PWM
Enabled
Bit 4
Zone 3 PWM
Enabled
Bit 3
Zone 2 PWM
Enabled
Bit 2
Zone 1 PWM
Enabled
Bit 1
Zone 0 PWM Enabled
Bit 0
PWM Enabled
0 = PWM input is
disabled in Zone 4
0 = PWM input is
disabled in Zone 3
0 = PWM input is
disabled in Zone 2
0 = PWM input is
disabled in Zone 1
(Default)
0 = PWM input is
disabled in Zone 0
(Default)
0 = PWM Input is
disabled (Default)
1 = PWM input is
enabled in Zone 4
(Default)
1 = PWM input is
enabled in Zone 3
(Default)
1 = PWM input is
enabled in Zone 2
(Default)
1 = PWM input is
enabled in Zone 1
1 = PWM input is
enabled in Zone 0
1 = PWM Input is
enabled
Table 12. Bank A Configuration (0x1A, Bits[1:0])
Bit 1
Control Bank A Mapping Mode
Bit 0
BREGA/ALSM1 Control
0 = Exponential Mapping (Default)
0 = Control Bank A is configured for Brightness Register Current
Control (Default)
1 = Linear Mapping
1 = Control Bank A is configured for ALS current control via the
ALSM1 Zone Target Registers
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Table 13. Bank A or Bank B Full Scale Current (0x1F,
0x20)
Bits [4:0]
Full-Scale Current (800µA per setting)
00000 = 5mA
:
:
10011 = 20.2mA (Default)
:
:
11111 = 29.8mA
Table 14. Bank B Configuration (0x1A, Bits[3:2])
Bit 3
Control Bank B Mapping Mode
Bit 2
BREGB/ALSM2 Control
0 = Exponential Mapping (Default)
0 = Control Bank B is configured for Brightness Register Current
Control (Default)
1 = Linear Mapping
1 = Control Bank B is configured for ALS current control via the
ALSM2 Zone Target Registers
Table 15. Bank A and Bank B Brightness (0x40, 0x41)
Brightness Code
Bits[7:0}
When the Mapping Mode is set for exponential mapping (Control Bank X Brightness Configuration Register, Bit [2] = 0), the current
approximates the equation:
(1)
When the Mapping Mode is set for linear mapping (Control Bank X Brightness Configuration Register, Bit [2] = 1), the current
approximates the equation:
(2)
12
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7.3
Bank C, D, E, and F Tab
Each low voltage Control Bank (C, D, E, and F) has its own tab. Each tab has all the register options that
are unique to each of the low voltage control banks and the pattern generators. Table 16 through Table 24
describe these registers.
Figure 10. Low Voltage Control Bank Tab
Table 16. Bank (C/D/E/F) Configuration (0x1B, 0x1C, 0x1D, 0x1E), Bits[2:0]
Bit 2
Mapping Mode
Bits [1:0]
Current Control
0 = Exponential Mapping (Default)
0X = Control Bank_ is configured for Brightness Register Current Control
via the respective Brightness Register (Default)
1 = Linear Mapping
10 = Control Bank_ is configured for ALS current control via the ALSM2
Zone Target Registers
11 = Control Bank_ is configured for ALS current control via the ALSM3
Zone Target Registers
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Table 17. Bank C/D/E/F High Brightness (0x42, 0x43, 0x44, 0x45)
Brightness Code
Bits[7:0}
When the Mapping Mode is set for exponential mapping (Control Bank_Brightness Configuration Register Bit [2] = 0), the current
approximates the equation:
(3)
When the Mapping Mode is set for linear mapping (Control Bank_Brightness Configuration Register Bit [2] = 1), the current
approximates the equation:
(4)
Table 18. Bank (C/D/E/F) Full Scale Current (0x21,
0x22, 0x23, 0x24)
Bits [4:0]
Full-Scale Current (800µA per setting)
00000 = 5mA
:
:
10011 = 20.2mA (Default)
:
:
11111 = 29.8mA
Table 19. Bank (C/D/E/F) PWM Configuration (0x16, 0x17, 0x18, 0x19)
Bit 5
Zone 4
Bit 4
Zone 3
Bit 3
Zone 2
Bit 2
Zone 1
0 = PWM input is
disabled in Zone
1 (Default)
Bit 1
Zone 0
0 = PWM input is
disabled in Zone 4
0 = PWM input is
disabled in Zone 3
0 = PWM input is
disabled in Zone
2
0 = PWM input is
disabled in Zone 0
(Default)
1 = PWM input is
enabled in Zone 4
(Default)
1 = PWM input is
enabled in Zone 3
(Default)
1 = PWM input is 1 = PWM input is 1 = PWM input is
enabled in Zone 2 enabled in Zone 1 enabled in Zone 0
(Default)
Bit 0
PWM Enabled
0 = PWM Input is
disabled (Default)
1 = PWM Input is
enabled
The PGEN Enable field in the low voltage control bank tabs is mirrored for each tab. Once a check box is
selected, the Enable Selected Patterns button must be pushed to write the specific bit to register 0x28. A
checked box means a 1 is being written and an empty box means a 0 is bing written.
Table 20. PGEN Enable (0X28, Bits[0, 2, 4, 6])
Bit 6
Pattern 4
Enable
14
Bit 4
Pattern 3
Enable
Bit 2
Pattern 2
Enable
Bit 0
Pattern 1
Enable
0 = Pattern 4 Disabled (Default)
0 = Pattern 3 Disabled
(Default)
0 = Pattern 2 Disabled
(Default)
0 = Pattern 1 Disabled (Default)
1 = Pattern 4 Enabled
1 = Pattern 3 Enabled
1 = Pattern 2 Enabled
1 = Pattern 1 Enabled
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Each low voltage control bank has its own pattern generator control. Bank C has Pattern Generator 1,
Bank D has Pattern Generator 2, Bank E has Pattern Generator 3, and Bank F has Pattern Generator 4.
Each pattern generator has registers that control the pulse high time, pulse low time, pulse rise time, pulse
fall time, pulse delay from when the pattern is enabled, and the pulse low brightness. The pulse high
brightness is the same as the high brightness register for the particular Control Bank.
tHIGH
IHIGH
tFALL
tRISE
tDELAY
ILOW
tLOW
Figure 11. Pattern Generator Timing
Table 21. Low Time(s) (0x71, 0x81, 0x91, 0xA1)
Bit [7:0]
tLOW times
0x00 = 16.384ms (16.384ms/step) (Default)
0x01 = 32.768ms
:
0x3B = 983.05ms
0x3C = 999.424ms
0x3D = 1130.496ms (131.072ms/step)
0x3E = 1261.568ms
:
0x7F = 9781.248ms
0x80 = 10.305536s (524.288ms/step)
:
0xFF = 76.890112s
Table 22. High Time(s) (0x72, 0x82, 0x92, 0xA2)
Bit [6:0]
tHIGH times
0x00 = 16.384ms (16.384ms/step) (Default)
0x01 = 32.768ms
:
0x3B = 983.05ms
0x3C = 999.424ms
0x3D = 1130.496ms (131.072ms/step)
0x3E = 1261.568ms
:
0x7F = 9781.248ms
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For Exponential Mapping Mode the low-level current becomes:
(5)
For Linear Mapping Mode the low-level current becomes:
(6)
7.4
LOW BRIGHTNESS (0x73, 0x83, 0x93, 0xA3)
Table 23. Rise Time (0x74, 0x84, 0x94, 0xA4)
Bits [2:0]
tRISE (from ILOW to IHIGH)
000 = 2048µs (Default)
001 = 262ms
010 = 524ms
011 = 1.049s
100 = 2.097s
101 = 4.194s
110 = 8.389s
111 = 16.78s
Table 24. Fall Time (0x75, 0x85, 0x95, 0xA5)
Bits [2:0]
tFALL (from IHIGH to ILOW )
000 = 2048µs (Default)
001 = 262ms
010 = 524ms
011 = 1.049s
100 = 2.097s
101 = 4.194s
110 = 8.389s
111 = 16.78s
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7.5
ALS TAB
The Ambient Light Sensor (ALS) tab (Figure 12) contains all the registers that are applicable to the
LM3533's ALS interface. Table 25 through Table 34 describe these registers.
Figure 12. ALS Tab
Table 25. ALS Configuration (0x31)
Bits [5:3]
ALS Average Times
Bit 2
Fast startup Enable/Disable
000 = 17.92 ms
001 = 35.84ms
010 = 71.68ms
011 = 143.36ms
100 = 286.72ms (Default)
101 = 573.44ms
110 = 1146.88ms
111 = 2293.76ms
Bit 1
ALS Input Mode
Bit 0
ALS Enable/Disable
0 = ALS fast startup is enabled 0 = ALS is set for Analog
0 = ALS is disabled
(Default)
Sensor Input Mode (Default)
(Default)
1 = ALS fast startup is disabled 1 = ALS is set for PWM Sensor 1 = ALS is enabled
Input Mode
Table 26. Algorithm Select (0X32)
Bits [7:6]
PGEN
Bits [5:4]
ALSM3
Bits [3:2]
ALSM2
Bits [1:0]
ALSM1
00 = Direct Control (Default) 00 = Direct Control (Default)
00 = Direct Control (Default)
00 = Direct Control (default)
01 = Up Only Control
01 = Up Only Control
01 = Up Only
01 = Up Only
1X = Down Delay Control
1X = Down Delay Control
1X = Down Delay
1X = Down Delay
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Table 27. Down Delay (0x33)
Bits [4:0]
Down Delay Settings
(# Indicates total average periods required to force a change in the down direction)
00000 = 6 (Default)
:
:
:
11111 = 37
Table 28. Zone Information (0x34)
Bits [4:2]
Average Zone Information Bits
Bit 1
Zone Change Bit
000 = Zone 0 (Default)
001 = Zone 1
010 = Zone 2
011 = Zone 3
1XX = Zone 4
Bit 0
Interrupt Enable Bit
0 = no change in the ALS zone since the last
read back of this register (Default)
1 = the ALS zone has changed. A read back
of this
0 = INT Mode Disabled (Default)
1 = INT Mode Enabled
Table 29. ADC Readback (0x37)
Bit 7
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSB
Data
Data
Data
Data
Data
Data
Data
Data
Table 30. Read-Average ADC Register (ADDRESS 0x38)
Bit 7
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSB
Data
Data
Data
Data
Data
Data
Data
Data
Table 31. Zone Boundaries
Name
Address
Function
Zone 0H
0x50
ALS Zone Boundary 0 High
Zone 0L
0x51
ALS Zone Boundary 0 Low
Zone 1H
0x52
ALS Zone Boundary 1 High
Zone 1L
0x53
ALS Zone Boundary 1 Low
Zone 2H
0x54
ALS Zone Boundary 2 High
Zone 2L
0x55
ALS Zone Boundary 2 Low
Zone 3H
0x56
ALS Zone Boundary 3 High
Zone 3L
0x57
ALS Zone Boundary 3 Low
Note: Each Zone Boundary register is 8 bits with a maximum voltage of 2V. This gives a step size for
each Zone Boundary Register bit of:
(7)
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Table 32. ALSM1 Zone Target Registers (ADDRESS 0x60 - 0x64)
Address
Function
0x60
ALSM1 Zone Target 0
0x61
ALSM1 Zone Target 1
0x62
ALSM1 Zone Target 2
0x63
ALSM1 Zone Target 3
0x64
ALSM1 Zone Target 4
Table 33. ALSM2 Zone Target Registers (ADDRESS 0x65 - 0x69)
Address
Function
0x65
ALSM2 Zone Target 0
0x66
ALSM2 Zone Target 1
0x67
ALSM2 Zone Target 2
0x68
ALSM2 Zone Target 3
0x69
ALSM2 Zone Target 4
Table 34. ALSM3 Zone Target Registers (ADDRESS 0x6A - 0x6E)
Address
Function
0x6A
ALSM3 Zone Target 0
0x6B
ALSM3 Zone Target 1
0x6C
ALSM3 Zone Target 2
0x6D
ALSM3 Zone Target 3
0x6E
ALSM3 Zone Target 4
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