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LM321LV, LM324LV, LM358LV
SBOS944D – SEPTEMBER 2018 – REVISED SEPTEMBER 2019
LM321LV, LM358LV, LM324LV Industry Standard, Low Voltage Operational Amplifiers
1 Features
3 Description
•
The LM3xxLV family includes the single LM321LV,
dual LM358LV, and quad LM324LV operational
amplifiers, or op amps. The devices operate from a
low voltage of 2.7 V to 5.5 V.
1
•
•
•
•
•
•
•
•
•
•
Industry standard amplifier for cost-sensitive
systems
Low input offset voltage: ±1 mV
Common-mode voltage range includes ground
Unity-gain bandwidth: 1 MHz
Low broadband noise: 40 nV/√Hz
Low quiescent current: 90 µA/Ch
Unity-gain stable
Operational at supply voltages from 2.7 V to 5.5 V
Offered in single, dual, and quad channel variants
Robust ESD specification: 2-kV HBM
Extended temperature range: –40°C to 125°C
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Cordless appliances
Uninterruptible power supply
Battery pack, charger, and test equipment
Power supply modules
Environmental sensors signal conditioning
Field transmitter: temperature sensors
Oscilloscopes, digital multimeters, test equipment
Rack mount server
HVAC: heating, ventilating, and air conditioning
DC motor control
Low-side current sensing
These op amps supply an alternative to the LM321,
LM358, and LM324 in low-voltage applications that
are sensitive to cost. Some applications are large
appliances,
smoke
detectors,
and
personal
electronics. The LM3xxLV devices supply better
performance than the LM3xx devices at low voltage,
and have lower power consumption. The op amps
are stable at unity gain, and do not have reverse
phase in overdrive conditions. The design for ESD
gives the LM3xxLV family an HBM specification for a
minimum of 2 kV.
The LM3xxLV family is available in packages that
have industry standards. The packages include SOT23, SOIC, VSSOP, and TSSOP packages.
Device Information(1)
PART NUMBER
PACKAGE
LM321LV
LM358LV
LM324LV
BODY SIZE (NOM)
SOT-23 (5)
1.60 mm × 2.90 mm
SC70 (5)
1.25 mm × 2.00 mm
SOIC (8)
3.91 mm × 4.90 mm
SOT-23 (8)
1.60 mm × 2.90 mm
TSSOP (8)
3.00 mm × 4.40 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Single-Pole, Low-Pass Filter
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM321LV, LM324LV, LM358LV
SBOS944D – SEPTEMBER 2018 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6
6
6
7
7
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: LM321LV ................................
Thermal Information: LM358LV ................................
Thermal Information: LM324LV ................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 16
9
Power Supply Recommendations...................... 18
9.1 Input and ESD Protection ....................................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision C (May 2019) to Revision D
•
Page
Deleted all preview notations in datasheet for SOT-23 (DDF) package ................................................................................ 1
Changes from Revision B (February 2019) to Revision C
Page
•
Added SOT-23 (DDF) package to Device Information table .................................................................................................. 1
•
Added DDF (SOT-23) information to Pin Configuration and Functions section ..................................................................... 4
•
Added DDF (SOT-23) to Thermal Information: LM358LV table ............................................................................................. 7
Changes from Revision A (January 2019) to Revision B
•
Page
Changed LM321LVIDBV (SOT-23) pinout diagram to match the LM321LVIDCK (SC70) pinout ......................................... 3
Changes from Original (September 2018) to Revision A
•
2
Page
Changed data sheet title from LM3xxLV... to LM321LV, LM358LV, LM324LV... .................................................................. 1
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: LM321LV LM324LV LM358LV
LM321LV, LM324LV, LM358LV
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SBOS944D – SEPTEMBER 2018 – REVISED SEPTEMBER 2019
5 Pin Configuration and Functions
LM321LV DBV, DCK Package
5-Pin SOT-23, SC70
Top View
IN+
1
V±
2
IN±
3
5
V+
4
OUT
Not to scale
Pin Functions: LM321LV
PIN
NAME
NO.
I/O
DESCRIPTION
IN–
3
I
Inverting input
IN+
1
I
Noninverting input
OUT
4
O
Output
V–
2
I or —
V+
5
I
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
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LM321LV, LM324LV, LM358LV
SBOS944D – SEPTEMBER 2018 – REVISED SEPTEMBER 2019
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LM358LV D, DGK, PW, DDF Packages
8-Pin SOIC, VSSOP, TSSOP, SOT-23
Top View
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
Not to scale
Pin Functions: LM358LV
PIN
NAME
NO.
I/O
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V–
4
I or —
V+
8
I
4
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Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
Copyright © 2018–2019, Texas Instruments Incorporated
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SBOS944D – SEPTEMBER 2018 – REVISED SEPTEMBER 2019
LM324LV D, PW Packages
14-Pin SOIC, TSSOP
Top View
OUT1
1
14
OUT4
IN1±
2
13
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
Not to scale
Pin Functions: LM324LV
PIN
NAME
NO.
I/O
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
IN3–
9
I
Inverting input, channel 3
IN3+
10
I
Noninverting input, channel 3
IN4–
13
I
Inverting input, channel 4
IN4+
12
I
Noninverting input, channel 4
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
V–
11
I or —
V+
4
I
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
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SBOS944D – SEPTEMBER 2018 – REVISED SEPTEMBER 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
Supply voltage, ([V+] – [V–])
Common-mode
Voltage (2)
Signal input pins
MIN
MAX
0
6
V
(V+) + 0.5
V
(V–) – 0.5
Differential
(V+) – (V–) + 0.2
Current (2)
–10
Output short-circuit (3)
–55
Operating junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
10
mA
150
°C
150
°C
150
°C
Continuous
Operating, TA
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
VS
Supply voltage [(V+) – (V–)]
VIN
Input pin voltage range
TA
Specified temperature
6
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MIN
MAX
2.7
5.5
UNIT
V
(V–) – 0.1
(V+) – 1
V
–40
125
°C
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SBOS944D – SEPTEMBER 2018 – REVISED SEPTEMBER 2019
6.4 Thermal Information: LM321LV
LM321LV
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
232.9
239.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
153.8
148.5
°C/W
RθJB
Junction-to-board thermal resistance
100.9
82.3
°C/W
ψJT
Junction-to-top characterization parameter
77.2
54.5
°C/W
ψJB
Junction-to-board characterization parameter
100.4
81.8
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Thermal Information: LM358LV
LM358LV
THERMAL METRIC (1)
RθJA
DGK (VSSOP)
PW (TSSOP)
DDF (SOT-23)
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
207.9
201.2
200.7
183.7
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
92.8
85.7
95.4
112.5
°C/W
RθJB
Junction-to-board thermal resistance
129.7
122.9
128.6
98.2
°C/W
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
(1)
Junction-to-ambient thermal resistance
D (SOIC)
26
21.2
27.2
18.8
°C/W
127.9
121.4
127.2
97.6
°C/W
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.6 Thermal Information: LM324LV
LM324LV
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
UNIT
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
102.1
148.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.8
68.1
°C/W
RθJB
Junction-to-board thermal resistance
58.5
92.7
°C/W
ψJT
Junction-to-top characterization parameter
20.5
16.9
°C/W
ψJB
Junction-to-board characterization parameter
58.1
91.8
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: LM321LV LM324LV LM358LV
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 5.5 V (±1.35 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT =
VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±1
±3
UNIT
OFFSET VOLTAGE
VS = 5 V
VOS
Input offset voltage
dVOS/dT
VOS vs temperature
TA = –40°C to 125°C
PSRR
Power-supply rejection ratio
VS = 2.7 V to 5.5 V, VCM = (V–)
mV
VS = 5 V, TA = –40°C to 125°C
±5
80
±4
µV/°C
100
dB
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode voltage range
Common-mode rejection ratio
No phase reversal
(V–) – 0.1
VS = 2.7 V, (V–) – 0.1 V < VCM < (V+) – 1 V,
TA = –40°C to 125°C
(V+) – 1
V
84
dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1 V,
TA = –40°C to 125°C
63
92
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
VS = 5 V
±15
pA
±5
pA
NOISE
En
Input voltage noise (peak-to-peak)
ƒ = 0.1 Hz to 10 Hz, VS = 5 V
5.1
µVPP
en
Input voltage noise density
ƒ = 1 kHz, VS = 5 V
40
nV/√Hz
2
pF
5.5
pF
INPUT CAPACITANCE
CID
Differential
CIC
Common-mode
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = 2.7 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ
110
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ
125
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
VS = 5 V
φm
Phase margin
VS = 5.5 V, G = 1
75
1
°
SR
Slew rate
VS = 5 V
1.5
V/µs
tS
Settling time
tOR
To 0.1%, VS = 5 V, 2-V step, G = 1, CL = 100 pF
4
To 0.01%, VS = 5 V, 2-V step, G = 1, CL = 100 pF
5
Overload recovery time
VS = 5 V, VIN × gain > VS
1
Total harmonic distortion + noise
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = 1, f = 1 kHz,
80-kHz measurement BW
VOH
Voltage output swing from positive supply
RL ≥ 2 kΩ, TA = –40°C to 125°C
VOL
Voltage output swing from negative supply
RL ≤ 10 kΩ, TA = –40°C to 125°C
ISC
Short-circuit current
VS = 5.5 V
ZO
Open-loop output impedance
VS = 5 V, f = 1 MHz
THD+N
MHz
µs
µs
0.005%
OUTPUT
1
V
40
75
mV
±40
mA
1200
Ω
POWER SUPPLY
VS
IQ
8
Specified voltage range
Quiescent current per amplifier
2.7 (±1.35)
IO = 0 mA, VS = 5.5 V
V
150
µA
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
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5.5 (±2.75)
90
160
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6.8 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
10
160
8
140
6
120
IB and IOS (pA)
4
Gain (dB)
2
0
IBIB+
IOS
-2
-4
100
80
60
40
-6
20
-8
-10
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5
Common-Mode Voltage (V)
2
2.5
0
-40
3
20
100
60
80
60
20
40
0
20
Gain
Phase
Open-Loop Voltage Gain (dB)
80
40
40
60
80
Temperature (qC)
100
120
140
D008
160
Phase (q)
Gain (dB)
120
140
120
100
80
60
40
20
0
-3
0
100k
Frequency (Hz)
0
Figure 2. Open-Loop Gain vs Temperature
Figure 1. IB and IOS vs Common-Mode Voltage
10k
-20
D007
100
-20
1k
VS = 5.5 V
VS = 2.5 V
1M
-2
D009
-1
0
1
Output Voltage (V)
2
3
D010
CL = 10 pF
Figure 4. Open-Loop Voltage Gain vs Output Voltage
Figure 3. Open-Loop Gain and Phase vs Frequency
80
Gain = 1
Gain = 1
Gain = 10
Gain = 100
Gain = 1000
70
60
Gain (dB)
50
40
30
20
10
0
-10
-20
100
1k
10k
100k
Frequency (Hz)
1M
D011
CL = 10 pF
Figure 5. Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
120
2
Power Supply Rejection Ratio (dB)
1.5
Output Voltage (V)
1
0.5
-40 qC
25 qC
85 qC
125 qC
0
-0.5
-1
-1.5
-2
-2.5
80
60
40
20
0
100
-3
0
5
10
15
20
25
30
35
Output Current (mA)
40
45
PSRR+
PSRR
100
50
120
100k
1M
D013
120
Common-Mode Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
10k
Frequency (Hz)
Figure 7. PSRR vs Frequency
Figure 6. Output Voltage vs Output Current (Claw)
100
80
60
40
20
0
-40
1k
D012
-20
0
20
40
60
80
Temperature (qC)
100
120
100
80
60
40
20
0
100
140
1k
D014
10k
Frequency (Hz)
100k
1M
D015
VS = 2.7 V to 5.5 V
Figure 8. DC PSRR vs Temperature
Figure 9. CMRR vs Frequency
100
Amplitude (1 PV/div)
Common-Mode Rejection Ratio (dB)
120
80
60
40
20
0
-40
VS = 2.7 V
VS = 5.5 V
-20
0
20
40
60
80
Temperature (qC)
100
120
Time (1 s/div)
140
D017
D016
VCM = (V–) – 0.1 V to (V+) – 1.5 V
Figure 10. DC CMRR vs Temperature
10
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Figure 11. 0.1-Hz to 10-Hz Integrated Voltage Noise
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Typical Characteristics (continued)
-50
140
120
-60
100
THD + N (dB)
Input Voltage Noise Spectral Density (nV/—Hz)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
80
60
-70
-80
40
-90
20
RL = 2K
RL = 10K
0
10
100
1k
Frequency (Hz)
10k
-100
100
100k
1k
Frequency (Hz)
D018
VS = 5.5 V
BW = 80 kHz
10k
D019
VCM = 2.5 V
VOUT = 0.5 VRMS
G=1
Figure 13. THD + N vs Frequency
Figure 12. Input Voltage Noise Spectral Density
0
100
G = +1, RL = 2 k:
G = +1, RL = 10 k:
G = 1, RL = 2 k:
G = 1, RL = 10 k:
Quiescent Current (PA)
THD + N (dB)
-20
-40
-60
-80
-100
0.001
0.01
VS = 5.5 V
BW = 80 kHz
0.1
Amplitude (V RMS)
1
90
80
70
60
2.5
2
VCM = 2.5 V
f = 1 kHz
5
5.5
D021
Figure 15. Quiescent Current vs Supply Voltage
100
2000
Open-Loop Output Impedance (:)
Quiescent Current (PA)
3.5
4
4.5
Voltage Supply (V)
G=1
Figure 14. THD + N vs Amplitude
90
80
70
60
-40
3
D020
-20
0
20
40
60
80
Temperature (qC)
100
120
Figure 16. Quiescent Current vs Temperature
140
1800
1600
1400
1200
1000
800
600
400
200
0
1k
10k
D022
100k
Frequency (Hz)
1M
10M
D023
Figure 17. Open-Loop Output Impedance vs Frequency
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Typical Characteristics (continued)
50
50
45
45
40
40
35
35
Overshoot (%)
Overshoot (%)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
30
25
20
30
25
20
15
15
10
10
Overshoot (+)
Overshoot (–)
5
Overshoot (+)
Overshoot (–)
5
0
0
0
200
G=1
400
600
Capacitance Load (pF)
800
1000
0
200
D024
VIN = 100 mVpp
G = –1
Figure 18. Small Signal Overshoot vs Capacitive Load
400
600
Capacitance Load (pF)
800
1000
D025
VIN = 100 mVpp
Figure 19. Small Signal Overshoot vs Capacitive Load
90
VOUT
VIN
80
Amplitude (1 V/div)
Phase Margin (q)
70
60
50
40
30
20
10
0
0
200
400
600
Capacitance Load (pF)
800
Time (100 Ps/div)
1000
D027
D026
G=1
VIN = 6.5 VPP
Figure 21. No Phase Reversal
Figure 20. Phase Margin vs Capacitive Load
VOUT
VIN
Amplitude (1 V/div)
Voltage (20 mV/div)
VOUT
VIN
Time (20 Ps/div)
Time (10 Ps/div)
D028
G = –10
VIN = 600 mVPP
Figure 22. Overload Recovery
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D029
G=1
VIN = 100 mVPP
CL = 10 pF
Figure 23. Small-Signal Step Response
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Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Voltage (1 V/div)
Output Voltage (1 mV/div)
VOUT
VIN
Time (1 μs/div)
Time (10 Ps/div)
D031
D030
G=1
VIN = 4 VPP
G=1
CL = 10 pF
CL = 100 pF
2-V step
Figure 25. Large-Signal Settling Time (Negative)
Figure 24. Large-Signal Step Response
80
Short Circuit Current (mA)
Output Voltage (1 mV/div)
60
40
20
0
-20
-40
-60
Sinking
Sourcing
-80
-40
Time (1 Ps/div)
-20
0
D032
G=1
CL = 100 pF
100
120
D033
Figure 27. Short-Circuit Current vs Temperature
0
120
-20
Channel Separation (dB)
140
100
EMIRR (dB)
80
2-V step
Figure 26. Large-Signal Settling Time (Positive)
80
60
40
-40
-60
-80
-100
-120
20
0
10M
20
40
60
Temperature (qC)
100M
1G
Frequency (Hz)
10G
-140
1k
10k
D035
Figure 28. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
100k
Frequency (Hz)
1M
10M
D036
Figure 29. Channel Separation
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7 Detailed Description
7.1 Overview
The LM3xxLV family of low-power op amps is intended for cost-optimized systems. These devices operate from
2.7 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The
input common-mode voltage range includes the negative rail and allows the LM3xxLV family to be used in many
single-supply applications.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
7.3 Feature Description
7.3.1 Operating Voltage
The LM3xxLV family of op amps is specified for operation from 2.7 V to 5.5 V. In addition, many specifications
apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are shown
in the Electrical Characteristics section.
7.3.2 Common-Mode Input Range Includes Ground
The input common-mode voltage range of the LM3xxLV family extends to the negative supply rail and within 1 V
below the positive rail for the full supply voltage range of 2.7 V to 5.5 V. This performance is achieved with a
P‑channel differential pair, as shown in the Functional Block Diagram. Additionally, a complementary N‑channel
differential pair has been included in parallel to eliminate issues with phase reversal that are common with
previous generations of op amps. However, the N-channel pair is not optimized for operation, and significant
performance degradation occurs while this pair is operational. TI recommends limiting any voltage applied at the
inputs to at least 1 V below the positive supply rail (V+) to ensure that the op amp conforms to the specifications
detailed in the Electrical Characteristics section.
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Feature Description (continued)
7.3.3 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the specified output voltage swing, because of the high input voltage or the high gain. After the
device enters the saturation region, the charge carriers in the output devices require time to return to the linear
state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate.
Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and
the slew time. The overload recovery time for the LM3xxLV family is typically 1 µs.
7.3.4 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can also involve the supply voltage pins. Each of these
different pin functions has electrical stress limits determined by the voltage breakdown characteristics of the
particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal
electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events
both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 30 shows the ESD circuits contained in the LM3xxLV. The ESD protection circuitry involves
several current-steering diodes connected from the input and output pins and routed back to the internal power
supply lines, where they meet at an absorption device internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
V+
Power Supply
ESD Cell
+IN
+
±
± IN
OUT
V±
Figure 30. Equivalent Internal ESD Circuitry
7.3.5 EMI Susceptibility and Input Filtering
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The Figure 28 plot illustrates the
performance of the LM3xxLV family's EMI filters across a wide range of frequencies. For more detailed
information, see EMI Rejection Ratio of Operational Amplifiers available for download from www.ti.com.
7.4 Device Functional Modes
The LM3xxLV family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 2.7 V (±1.35 V) and 5.5 V (±2.75 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM3xxLV devices are a family of low-power, cost-optimized operational amplifiers. The devices operate from
2.7 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications. The input
common-mode voltage range includes the negative rail, and allows the LM3xxLV to be used in any single-supply
applications.
8.2 Typical Application
Figure 31 shows the LM3xxLV device configured in a low-side current sensing application.
VBUS
ILOAD
Z LOAD
5V
+
VOUT
í
+
RSHUNT
0.1 Ÿ
VSHUNT
í
RF
255 NŸ
RG
7.5 NŸ
Figure 31. LM3xxLV Device in a Low-Side, Current-Sensing Application
8.2.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 3.5 V
• Maximum shunt voltage: 100 mV
8.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 31 is given in Equation 1:
VOUT ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest allowable shunt
resistor is shown using Equation 2:
VSHUNT _ MAX 100mV
RSHUNT
100m:
ILOAD _ MAX
1A
(2)
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Typical Application (continued)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the LM3xxLV device to produce an output voltage of approximately 0 V to 3.5 V. The gain needed
by the LM3xxLV to produce the necessary output voltage is calculated using Equation 3:
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 35 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the LM3xxLV device to 35 V/V.
RF
Gain 1
RG
(4)
8.2.3 Application Curve
Selecting RF as 255 kΩ and RG as 7.5 kΩ provides a combination that equals 35 V/V. Figure 32 shows the
measured transfer function of the circuit shown in Figure 31. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, you must choose an impedance that is ideal for your
system parameters.
3.5
3
Output (V)
2.5
2
1.5
1
0.5
0
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Outp
Figure 32. Low-Side, Current-Sense Transfer Function
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9 Power Supply Recommendations
The LM3xxLV family is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.75 V); many specifications apply
from –40°C to 125°C. The Electrical Characteristics section presents parameters that may exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
9.1 Input and ESD Protection
The LM3xxLV family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA, as stated in the Absolute Maximum Ratings table. Figure 33 shows how a series input resistor can be
added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier
input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
Figure 33. Input Current Protection
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op
amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Take care to physically separate digital and analog grounds. Use thermal signatures or EMI
measurement techniques to determine where the majority of the ground current is flowing and be sure to
route this path away from sensitive analog circuitry. For more detailed information, see Circuit Board
Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is
much better as opposed to running the traces in parallel with the noisy trace.
• Place the external components as close to the device as possible, as shown in Figure 35. Keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
+
VIN 1
+
VIN 2
VOUT 1
RG
RF
VOUT 2
RG
RF
Figure 34. Schematic Representation for Figure 35
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Layout Example (continued)
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
V+
RF
OUT 2
GND
IN1 ±
OUT2
IN1 +
IN2 ±
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
VS±
IN2 +
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Ground (GND) plane on another layer
Figure 35. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM321LV
Click here
Click here
Click here
Click here
Click here
LM324LV
Click here
Click here
Click here
Click here
Click here
LM358LV
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM321LVIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1SPF
LM321LVIDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1DH
LM324LVIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LM324LV
LM324LVIPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
LM324LV
LM358LVIDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
L58L
LM358LVIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1PKX
LM358LVIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
L358LV
LM358LVIPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
358LV
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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