LM3674MF-1.2

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 LM3674 2-MHz, 600-mA Step-Down DC-DC Converter in SOT-23 1 Features 3 Description • • • The LM3674 step-down DC-DC converter is optimized for powering low-voltage circuits from a single Li-Ion cell battery and input voltage rails from 2.7 V to 5.5 V. It provides up to 600-mA load current over the entire input voltage range. There are several fixed output voltages and adjustable output voltage versions. 1 • • • • • • Input Voltage Range From 2.7 V to 5.5 V 600-mA Maximum Load Current Available in Fixed and Adjustable Output Voltages Ranging From 1 V to 3.3 V Operates From a Single Li-Ion Cell Battery Internal Synchronous Rectification for High Efficiency Internal Soft-Start 0.01-µA Typical Shutdown Current 2-MHz PWM Fixed Switching Frequency (typical) Current Overload Protection and Thermal Shutdown Protection 2 Applications • • • • • • • The LM3674 is available in a 5-pin SOT-23 package. A high switching frequency of 2 MHz (typical) allows use of only three tiny external surface-mount components, an inductor and two ceramic capacitors. Mobile Phones PDAs MP3 Players Portable Instruments W-LAN Digital Still Cameras Portable Hard Disk Drives Device Information(1) PART NUMBER SW 1 CIN 4.7 PF SOT-23 (5) Typical Application Circuit for Adjustable Voltage Option VOUT 5 VIN 2.7V to 5.5V L1: 2.2 PH VIN 1 COUT 10 PF LM3674 GND CIN: 4.7 PF GND FB 3 5 VOUT SW LM3674ADJ 2 2 EN BODY SIZE (NOM) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. L1:2.2 PH VIN PACKAGE LM3674 Typical Application Circuit VIN 2.7V to 5.5V The device offers superior features and performance for mobile phones and similar portable systems. During the Pulse Width Modulation (PWM) mode, the device operates at a fixed-frequency of 2 MHz (typical). Internal synchronous rectification provides high efficiency during the PWM mode operation. In shutdown mode, the device turns off and reduces battery consumption to 0.01 µA (typical). 4 C1 R1 C2 R2 COUT: 10 PF FB EN 3 4 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Dissipation Ratings ................................................... Electrical Characteristics .......................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Applications ................................................ 12 9 Power Supply Recommendations...................... 17 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 18 11 Device and Documentation Support ................. 19 11.1 11.2 11.3 11.4 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History Changes from Revision F (May 2013) to Revision G Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Deleted "in leaded (Pb) and lead-free (no Pb) versions" ....................................................................................................... 1 Changes from Revision E (April 2013) to Revision F • 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 18 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 LM3674 www.ti.com SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View SW 5 VIN 1 FB 4 GND 2 EN 3 Note: The actual physical placement of the package marking will vary from part to part. Pin Functions PIN NAME NUMBER TYPE DESCRIPTION EN 3 Digital Enable input. The device is in shutdown mode when voltage to this pin is < 0.4 V and enable when > 1 V. Do not leave this pin floating. FB 4 Analog Feedback analog input. Connect to the output filter capacitor, COUT, for fixed voltage versions. For adjustable version, external resistor dividers are required (R1 and R2). The internal resistor dividers are disabled for the adjustable version. GND 2 Ground Ground pin SW 5 Analog Switching node connection to the internal PFET switch and NFET synchronous rectifier. VIN 1 Power Power supply input. Connect to the input filter capacitor, CIN. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 3 LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) VIN pin: voltage to GND EN, FB, and SW pins Continuous power dissipation (3) MIN MAX UNIT −0.2 6 V GND − 0.2 VIN + 0.2 V Internally Limited Junction temperature (TJ-MAX) Maximum lead temperature (soldering, 10 seconds) Storage temperature, Tstg (1) (2) (3) 125 °C 260 °C –65 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military- or Aerospace-specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. In applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), the maximum power dissipation of the device in the application (PD-MAX) and the junction-to-ambient thermal resistance of the package (RθJA) in the application, as given by the following equation: TA-MAX = TJ-MAX – (RθJA × PD-MAX). See Dissipation Ratings for PD-MAX values at different ambient temperatures. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge VALUE UNIT ±2000 V ±200 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX 2.7 5.5 V 0 600 mA Junction temperature, TJ –30 125 °C Ambient temperature,TA –30 85 °C Input voltage (2) Recommended load current (1) (2) UNIT All voltages are with respect to the potential at the GND pin. Input voltage range recommended for ideal applications performance for the specified output voltages are given below: VIN = 2.7 V to 5.5 V for 1 V ≤ VOUT < 1.8 V VIN = (VOUT + VDROP OUT) to 5.5 V for 1.8 ≤ VOUT ≤ 3.3 V, where VDROP OUT = ILOAD × (RDSON (P) + RINDUCTOR) 6.4 Thermal Information LM3674 THERMAL METRIC (1) DBV (SOT-23) UNIT 5 PINS RθJA (1) Junction-to-ambient thermal resistance 4-layer board 130 2-layer board 250 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Dissipation Ratings over operating free-air temperature range (unless otherwise noted) TA ≤ 25°C (POWER RATING) TA = 60°C (POWER RATING) TA = 85°C (POWER RATING) 250°C/W (2-layer board) 400 mW 260 mW 160 mW 130°C/W (4-layer board) 770 mW 500 mW 310 mW RθJA 4 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 LM3674 www.ti.com SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 6.6 Electrical Characteristics Typical limits are TA = 25°C; unless otherwise noted, specifications apply to the LM3674 with VIN = EN = 3.6 V (1) (2) (3) PARAMETER Feedback voltage (4) (5) TEST CONDITIONS MIN IO = 10 mA, −30°C ≤ TJ ≤ 125°C –4% TYP MAX UNIT 4% Line regulation 2.7 V ≤ VIN ≤ 5.5 V, IO = 100 mA Load regulation 100 mA ≤ IO ≤ 600 mA, VIN = 3.6 V VREF Internal reference voltage See (6) ISHDN Shutdown supply current IQ DC bias current into VIN No load, device is not switching (FB = 0 V) –30°C ≤ TJ ≤ 125°C RDSON (P) Pin-to-pin resistance for PFET ISW = 200 mA 380 500 mΩ RDSON (N) Pin-to-pin resistance for NFET ISW = 200 mA 250 400 mΩ VFB EN = 0 V Open loop Logic high input –30°C ≤ TJ ≤ 125°C VIL Logic low input –30°C ≤ TJ ≤ 125°C (1) (2) (3) (4) (5) (6) (7) Open loop (7), –30°C ≤ TJ ≤ 125°C µA 1 300 µA 600 (7) VIH Internal oscillator frequency V 0.01 Switch peak current limit FOSC %/mA EN = 0 V, –30°C ≤ TJ ≤ 125°C ILIM Enable (EN) input current %/V 0.0010 0.5 No load, device is not switching (FB = 0 V) IEN 0.083 1020 830 mA 1200 1 V 0.4 V 0.01 –30°C ≤ TJ ≤ 125°C PWM mode PWM mode, −30°C ≤ TJ ≤ 125°C µA 1 2 1.6 2.6 MHz All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely values. The parameters in the Electrical Characteristics are tested at VIN = 3.6 V unless otherwise specified. For performance curves over the input voltage range, see Typical Characteristics. ADJ configured to 1.5-V output. For VOUT < 2.5 V, VIN = 3.6 V; for VOUT ≥ 2.5 V, VIN = VOUT + 1. For the ADJ version the resistor dividers should be selected such that at the desired output voltage, the voltage at the FB pin is 0.5 V. See Typical Characteristics for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristics reflect open loop data (FB = 0 V and current drawn from the SW pin ramped up until cycle-by-cycle current limit is activated). Closed-loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 5 LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com 6.7 Typical Characteristics (unless otherwise stated: VIN = 3.6 V, VOUT = 1.5 V, TA = 25°C) 0.40 EN = GND SHUTDOWN CURRENT (PA) 0.35 0.30 0.25 0.20 VIN = 5.5V 0.15 VIN = 3.6V 0.10 VIN = 2.7V 0.05 0.00 -30 FB = 0 V, No Switching 6 -10 10 30 50 70 90 Figure 1. Quiescent Current vs Supply Voltage TEMPERATURE (°C) Figure 2. IQ Shutdown vs Temperature Figure 3. Feedback Bias Current vs Temperature Figure 4. Output Voltage vs Supply Voltage Figure 5. Output Voltage vs Temperature Figure 6. Output Voltage vs Output Current Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 LM3674 www.ti.com SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 Typical Characteristics (continued) (unless otherwise stated: VIN = 3.6 V, VOUT = 1.5 V, TA = 25°C) 2.00 600 VIN = 3.6V FREQUENCY (MHz) RDS(ON) (m:) 450 PFET 400 VIN = 2.7V 350 300 VIN = 4.5V 250 VIN = 4.5V VIN = 3.6V 1.96 _ VIN = 2.7V 1.94 _ 1.92 _ NFET 200 100 -30 1.98 _ VIN = 4.5V 500 150 IOUT = 300 mA VIN = 2.7V 550 1.90 _ VIN = 3.6V -10 10 30 50 70 90 110 1.88 _ -30 TEMPERATURE (°C) Figure 7. RDSON vs Temperature 10 _ 10 50 30 _ _ TEMPERATURE (°C) 70 _ 90 _ Figure 8. Switching Frequency vs Temperature VOUT = 1.2 V, L = 2.2 µH, DCR = 200 mΩ VOUT = 1.5 V, L = 2.2 µH, DCR = 200 mΩ Figure 9. Efficiency vs Output Current VOUT = 1.8 V, L = 2.2 µH, DCR = 200 mΩ Figure 10. Efficiency vs Output Current VOUT = 3.3 V, L = 2.2 µH, DCR = 200 mΩ Figure 11. Efficiency vs Output Current Figure 12. Efficiency vs Output Current Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 7 LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com Typical Characteristics (continued) (unless otherwise stated: VIN = 3.6 V, VOUT = 1.5 V, TA = 25°C) Figure 13. Open or Closed Loop Current Limit vs Temperature Figure 14. Line Transient Response Output Current = 300 mA Figure 16. Start-Up Figure 15. Load Transient Output Current = 10 mA Figure 17. Start-Up 8 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 LM3674 www.ti.com SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 7 Detailed Description 7.1 Overview The LM3674, a high-efficiency, step-down, DC-DC switching buck converter, delivers a constant voltage from a single Li-Ion battery and input voltage rails from 2.7 V to 5.5 V to portable devices such as cell phones and PDAs. Using a voltage mode architecture with synchronous rectification, the LM3674 has the ability to deliver up to 600 mA depending on the input voltage, output voltage, ambient temperature, and the inductor chosen. Additional features include soft-start, undervoltage protection, current overload protection, and thermal overload protection. As shown in Typical Application Circuit, only three external power components, CIN, COUT, and L1, are required for implementation. The part uses an internal reference voltage of 0.5 V. It is recommended to keep the part in shutdown mode until the input voltage is 2.7 V or higher. 7.2 Functional Block Diagram VIN EN SW Current Limit Comparator Thermal Shutdown Ramp Generator Soft Start + Undervoltage Lockout Ref1 2 MHz Oscillator Bandgap PWM Comparator Error Amp VREF 0.5V + - + - + - Control Logic Driver Vcomp 1.0V Frequency Compensation Adjustable Version Fixed Version GND FB Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 9 LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com 7.3 Feature Description 7.3.1 Circuit Operation During the first portion of each switching cycle, the control block in the LM3674 turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of: VIN-VOUT (1) L by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of: -VOUT (2) L The output filter stores charge when the inductor current is high, and releases it when the inductor current is low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch-on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. 7.3.2 PWM Operation During PWM operation, the converter operates as a voltage-mode controller with input voltage feed-forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed-forward inversely proportional to the input voltage is introduced. While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle, the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET. VSW 2V/DIV IL 200 mA/DIV VIN = 3.6V VOUT = 1.5V IOUT = 400 mA VOUT 10 mV/DIV AC Coupled TIME (200 ns/DIV) Figure 18. PWM Operation 10 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 LM3674 www.ti.com SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 Feature Description (continued) 7.3.2.1 Internal Synchronous Rectification While in PWM mode, the LM3674 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. 7.3.2.2 Current Limiting A current limit feature allows the LM3674 to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 1020 mA (typical). If the output is shorted to ground, then the device enters a timed current-limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, and thereby preventing runaway. 7.4 Device Functional Modes There are two modes of operation depending on the current required: Pulse Width Modulation (PWM) and shutdown. The device operates in PWM mode throughout the IOUT range. Shutdown mode turns off the device, offering the lowest current consumption (ISHUTDOWN = 0.01 µA, typical). Additional features include soft-start, undervoltage protection, and current overload protection. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 11 LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Soft-Start The LM3674 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft-start is activated only if EN goes from logic low to logic high after VIN reaches 2.7 V. Soft-start is implemented by increasing switch current limit in steps of 70 mA, 140 mA, 280 mA, and 1020 mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. Typical start-up times with 10-µF output capacitor and a 300-mA load current is 350 µs and with a 10-mA load current is 240 µs. 8.1.2 Low-Dropout (LDO) Operation The LM3674-ADJ can operate at 100% duty-cycle (no switching, PMOS switch completely on) for low-dropout support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty-cycle, the output voltage supply ripple is slightly higher, approximately 25 mV. The minimum input voltage needed to support the output voltage is: VIN,MIN = ILOAD × (RDSON (P) + RINDUCTOR) + VOUT where: • • • ILOAD is load current RDSON (P) is drain-to-source resistance of PFET switch in the triode region RINDUCTOR is inductor resistance (3) 8.2 Typical Applications 8.2.1 Typical Application for Fixed Voltage Configuration VIN 2.7V to 5.5V L1:2.2 PH VIN SW 1 CIN 4.7 PF VOUT 5 COUT 10 PF LM3674 GND 2 FB EN 3 4 Figure 19. Fixed-Voltage Typical Application Circuit 8.2.1.1 Design Requirements 12 DESIGN PARAMETER EXAMPLE VALUE Input voltage 3.6 V Output voltage 1.5 V Output current 300 mA Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 LM3674 www.ti.com SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Inductor Selection There are two main considerations when choosing an inductor: • The inductor should not saturate. • The inductor current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of the application should be requested from the manufacturer. The minimum value of inductance to ensure good performance is 1.76 µH at ILIM (typical) DC current over the ambient temperature range. Shielded inductors radiate less noise and should be preferred. There are two methods to choose the inductor saturation current rating: Method 1: The saturation current is greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as: ISAT > IOUTMAX + IRIPPLE (4) VIN - VOUT· § VOUT· § 1 where IRIPPLE = § © 2 x L ¹ © VIN ¹ © f · ¹ and • • • • • • IRIPPLE is average-to-peak inductor current IOUTMAX is maximum load current (600 mA) VIN is maximum input voltage in application L is minimum inductor value including worst case tolerances (30% drop can be considered for method 1 f is minimum switching frequency (1.6 MHz) VOUT is output voltage (5) Method 2: A more conservative and recommended approach is to choose an inductor that has saturation current rating greater than the maximum current limit of 1200 mA. A 2.2-µH inductor with a saturation current rating of at least 1200 mA is recommended for most applications. The resistance of the inductor should be less than 0.3 Ω for good efficiency. Table 1 lists suggested inductors and suppliers. For low-cost applications, an unshielded bobbin inductor is suggested. For noise critical applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of both types for design flexibility. This allows substitution of a low-noise toroidal inductor in the event that noise from low-cost bobbin models is unacceptable. Table 1. Suggested Inductors and Their Suppliers MODEL VENDOR DIMENSIONS L×W×H (mm) D.C.R (maximum) (mΩ) DO3314-222MX Coilcraft 3.3 x 3.3 x 1.4 200 LPO3310-222MX Coilcraft 3.3 x 3.3 x 1.0 150 ELL5GM2R2N Panasonic 5.2 x 5.2 x 1.5 53 CDRH2D14NP-2R2NC Sumida 3.2 x 3.2 x 1.55 94 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 13 LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com 8.2.1.2.2 Input Capacitor Selection A ceramic input capacitor of 4.7 µF, 6.3 V is sufficient for most applications. Place the input capacitor as close as possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The minimum input capacitance to ensure good performance is 2.2 µF at 3-V DC bias; 1.5 µF at 5-V DC bias including tolerances and over ambient temperature range. The input filter capacitor supplies current to the PFET switch of the LM3674 in the first half of each cycle and reduces voltage ripple imposed on the input power source. The low equivalent series resistance (ESR) of a ceramic capacitor provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating. The input current ripple can be calculated as: I RMS = I OUTMAX x VOUT VIN ( VIN - V ) x V OUT OUT r= Lxf xI OUTMAX x VIN x (1 - VOUT VIN 2 + r 12 ) The worst case is when VIN = 2 x VOUT (6) 8.2.1.2.3 Output Capacitor Selection A ceramic output capacitor of 10 µF, 6.3 V is sufficient for most applications. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC-bias characteristics vary from manufacturer to manufacturer and DC-bias curves should be requested from them as part of the capacitor selection process. The minimum output capacitance to ensure good performance is 5.75 µF at 1.8 V DC bias including tolerances and over ambient temperature range. The output filter capacitor smoothes out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes, and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. The output voltage ripple is caused by the charging and discharging of the output capacitor and by the RESR and can be calculated as: Voltage peak-to-peak ripple due to capacitance can be expressed as: VPP-C = I ripple fx4xC (7) Voltage peak-to-peak ripple due to ESR: VOUT = VPP-ESR = IPP * RESR (8) Because these two components are out of phase, the root mean squared (rms) value can be used to get an approximate value of peak-to-peak ripple. Voltage peak-to-peak ripple, rms: VPP-RMS = VPP-C2 + VPP-ESR2 (9) Note that the output ripple is dependent on the current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency-dependent (as well as temperature-dependent); make sure the value used for calculations is at the switching frequency of the part. 14 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 LM3674 www.ti.com SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 Table 2. Suggested Capacitors and Their Suppliers MODEL TYPE VENDOR VOLTAGE RATING (V) CASE SIZE [Inch (mm)] GRM21BR60J106K Ceramic, X5R Murata 6.3 0805 (2012) C2012X5R0J106K Ceramic, X5R TDK 6.3 0805 (2012) JMK212BJ106K Ceramic, X5R Taiyo-Yuden 6.3 0805 (2012) 10 µF for COUT 4.7 µF for CIN GRM21BR60J475K Ceramic, X5R Murata 6.3 0805 (2012) JMK212BJ475K Ceramic, X5R Taiyo-Yuden 6.3 0805 (2012) C2012X5R0J475K Ceramic, X5R TDK 6.3 0805 (2012) 8.2.1.3 Application Curves Table 3. Related Plots PLOT TITLE FIGURE Output Voltage vs Supply Voltage Figure 4 Output Voltage vs Temperature Figure 5 Output Voltage vs Output Current Figure 6 Efficiency vs Output Current Figure 9 Efficiency vs Output Current Figure 10 Efficiency vs Output Current Figure 11 Efficiency vs Output Current Figure 12 Line Transient Response Figure 14 Load Transient Figure 15 Start-Up Figure 16 Start-Up Figure 17 8.2.2 Typical Application Circuit for Adjustable Voltage Option VIN 2.7V to 5.5V L1: 2.2 PH VIN 1 CIN: 4.7 PF GND 5 VOUT SW LM3674ADJ 2 C1 R1 C2 R2 COUT: 10 PF FB EN 3 4 Figure 20. Typical Application Circuit for Adjustable Voltage Option Schematic 8.2.2.1 Design Requirements DESIGN PARAMETER EXAMPLE VALUE Output voltage 1.5 V Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 15 LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com 8.2.2.2 Detailed Design Procedure 8.2.2.2.1 Output Voltage Selection for Adjustable (LM3674-ADJ) The output voltage of the adjustable parts can be programmed through the resistor network connected from VOUT to FB then to GND. VOUT will be adjusted to make FB equal to 0.5 V. The resistor from FB to GND (R2) should be 200 kΩ to keep the current drawn through this network small but large enough that it is not susceptible to noise. If R2 is 200 kΩ, and given the VFB is 0.5 V, then the current through the resistor feedback network will be 2.5 µA. The output voltage formula is: VOUT = VFB * ( R1 R2 + 1) where: • • • • VOUT = Output voltage (V) VFB = Feedback voltage (0.5 V typical) R1 = Resistor from VOUT to FB (Ω) R2 = Resistor from FB to GND (Ω) (10) For any output voltage greater than or equal to 1.0 V, a frequency zero must be added at 45 kHz for stability. The formula is: C1 = 1 2 x S x R1 x 45 kHz (11) For output voltages greater than or equal to 2.5 V, a pole must also be placed at 45 kHz as well. If the pole and zero are at the same frequency the formula for calculation of C2 is: C2 = 1 2 x S x R2 x 45 kHz (12) The formula for location of zero and pole frequency created by adding C1,C2 are given below. It can be seen that by adding C1, a zero as well as a higher frequency pole is introduced. Fz = 1 1 Fp = (2 * S * R1 * C1) 2 * S * (R1 R2) * (C1+C2) (13) See Table 4. Table 4. Adjustable LM3674 Configurations for Various VOUT 16 VOUT (V) R1 (kΩ) R2 (kΩ) C1 (pF) C2 (pF) L (µH) CIN (µF) COUT (µF) 1.0 200 200 18 None 2.2 4.7 10 1.1 191 158 18 None 2.2 4.7 10 1.2 280 200 12 None 2.2 4.7 10 1.5 357 178 10 None 2.2 4.7 10 1.6 442 200 8.2 None 2.2 4.7 10 1.7 432 178 8.2 None 2.2 4.7 10 1.8 464 178 8.2 None 2.2 4.7 10 1.875 523 191 6.8 None 2.2 4.7 10 2.5 402 100 8.2 None 2.2 4.7 10 2.8 464 100 8.2 33 2.2 4.7 10 3.3 562 100 6.8 33 2.2 4.7 10 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 LM3674 www.ti.com SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 8.2.2.3 Application Curves Table 5. Related Plots PLOT TITLE FIGURE Output Voltage vs Supply Voltage Figure 4 Output Voltage vs Temperature Figure 5 Output Voltage vs Output Current Figure 6 Efficiency vs Output Current Figure 9 Efficiency vs Output Current Figure 10 Efficiency vs Output Current Figure 11 Efficiency vs Output Current Figure 12 Line Transient Response Figure 14 Load Transient Figure 15 Start-Up Figure 16 Start-Up Figure 17 9 Power Supply Recommendations The LM3674 requires a single supply input voltage. This voltage can range between 2.7 V to 5.5 V and be able to supply enough current for a given application. 10 Layout 10.1 Layout Guidelines PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter device, resulting in poor regulation or instability. Good layout for the LM3674 can be implemented by following a few simple design rules, as illustrated in Figure 21. 1. Place the LM3674, inductor and filter capacitors close together and make the traces short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Special care must by given to place the input filter capacitor very close to the VIN and GND pin. 2. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor, through the LM3674 and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the LM3674 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 3. Connect the ground pins of the LM3674, and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the LM3674 by giving it a low-impedance ground connection. 4. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces. 5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power components. The voltage feedback trace must remain close to the LM3674 circuit and should be direct but should be routed opposite to noisy components. This reduces the EMI radiated onto the voltage feedback trace of the DC-DC converter. A good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and layer on which the feedback trace is routed. In the same manner for the adjustable part it is desired to have the feedback dividers on the bottom layer. 6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 17 LM3674 SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com Layout Guidelines (continued) and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through distance. In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board, arrange the CMOS digital circuitry around it (because this also generates noise), and then place sensitive preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal pan and power to it is post-regulated to reduce conducted noise by using low-dropout linear regulators. 10.2 Layout Example Figure 21. Board Layout Design Rules for the LM3674 18 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 LM3674 www.ti.com SNVS405G – DECEMBER 2005 – REVISED APRIL 2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Trademarks All trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM3674 19 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM3674MF-1.2/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SLRB LM3674MF-1.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SLSB LM3674MF-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SLHB LM3674MF-1.875/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SNNB LM3674MF-2.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SLZB LM3674MF-ADJ NRND SOT-23 DBV 5 1000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -30 to 85 SLTB LM3674MF-ADJ/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SLTB LM3674MFX-1.2/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SLRB LM3674MFX-1.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SLSB LM3674MFX-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SLHB LM3674MFX-1.875/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SNNB LM3674MFX-ADJ/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -30 to 85 SLTB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of