LM3687TL-1815EV

User's Guide SNVA249A – July 2008 – Revised April 2013 AN-1647 LM3687 Evaluation Board 1 Introduction This evaluation board is designed to enable independent evaluation of the LM3687 electrical performance. Each board is pre-assembled and tested in the factory. The evaluation kit is available in two options: LM3687TL-1812EV and LM3687TL-1815EV. For other voltage options, the device can be ordered from LM3687 product folder on the TI website. The board contains the LM3687, an inductor, and input and output capacitors connected to GND. This user's guide contains information about the evaluation board. For further information on device electrical characteristics and component selection, please refer to LM3687 Step-Down DC-DC Converter with Integrated Low Dropout Regulator and Startup Mode (SNVS473). 2 General Description The LM3687 is a high efficiency synchronous switching step-down DC-DC converter with an integrated low dropout Linear Regulator optimized for powering ultra-low voltage circuits from a single Li-Ion cell or 3 cell NiMH/NiCd batteries. It provides a dual output with fixed output voltages and combined load current up to 750mA in post regulation mode or 1100mA in independent mode of operation. The LM3687 is capable of operating with input voltage ranges from 2.7V ≤ VBATT ≤ 5.5V and 0.7V ≤ VIN_LIN ≤ 4.5V. It also features internal protection against short-circuit and over-temperature conditions. For the Evaluation Board the typical post regulation application is realized: the output voltage of the DCDC converter is used as supply for the linear regulator (VOUT_DCDC = VIN_LIN). Thereby a higher efficiency and lower power dissipation of the system can be achieved compared to using the battery voltage VBATT as supply for the linear regulator (VIN_LIN). For both available evaluation kit options the output voltage of the DC-DC converter is 1.8V and therefore sufficiently high as supply for both linear regulator output voltage options (the power input voltage applied at VIN_LIN should be at least 0.25V above the nominal output voltage of the linear regulator). VBATT should be at least 1.5V above the output voltage of the linear regulator (VOUT_LIN) and 1.0V above the output voltage of the DC-DC converter (VOUT_DCDC) (with a minimum of 2.7V) to operate the device within operating conditions. That means for the 1.8V-1.2V combination, the minimum VBATT = 2.8V and for the 1.8V-1.5V combination it is 3.0V. Input connections should be kept reasonably short ( 1.0V. Do not leave this pin floating. See Table 2. B3 VIN_LIN Power Supply Input for the linear regulator C1 VBATT Power Supply for the DC-DC output stage and internal circuitry. Connected to the input filter capacitor. C2 FB_DCDC Feedback Analog Input for the DC-DC converter. Directly connected to the output filter capacitor. C3 EN_LIN Enable Input for the linear regulator. The linear regulator is in shutdown mode if voltage at this pin is < 0.4V and enabled if > 1.0V. Do not leave this pin floating. See Table 2. Table 2. Enable Combinations EN_DCDC EN_LIN Comments 0 0 No Outputs 0 1 Linear Regulator enabled only (1) 1 0 DC-DC converter enabled only 1 1 DC-DC converter and linear regulator active (1) (1) 7 Startup Mode: • VIN_LIN must be higher than VOUT_LIN(NOM) + 200mV in order to enable the main regulator (IMAX = 350mA). • If VIN_LIN < VOUT_LIN(NOM) + 100mV (100mV hysteresis), the startup LDO (IMAX = 50mA) is active, supplied from VBATT. For example in the typical post regulation application, the LDO will remain in startup mode until the DC-DC converter has ramped up its output voltage. Bill of Materials Table 3. Bill of Materials Item Description C1 CIN_LIN, ceramic capacitor, 1µF, X5R at VIN_LIN, optional, not needed in post regulation application due to C4 Qty 0 Footprint 0603 / 0402 Mfg., Part Number C2 CBATT, ceramic capacitor, 4.7µF, X5R at VBATT 1 0805 / 0603 TDK, C1608X5R1A475K C3 COUT_LIN, ceramic capacitor, 2.2µF, X5R at VOUT_LIN 1 0603 / 0402 TDK, C1608X5R1A225K C4 COUT_DCDC, ceramic capacitor, 10µF, X5R at VOUT_DCDC 1 0805 / 0603 TDK, C1608X5R0J106K L1 Inductor, 2.2µH, 1.6A ISAT 1 U1 LM3687 1 VBATT, VOUT_DCDC, VOUT_LIN, 2x GND Terminal 5 J5, J6 3 pin jumper for enable function 2 Coilcraft, DO3314-222MLB 9-bump DSBGA YZR0009BBA SNVA249A – July 2008 – Revised April 2013 Submit Documentation Feedback Texas Instruments, LM3687 Cambion, 160-1026-02-05 AN-1647 LM3687 Evaluation Board Copyright © 2008–2013, Texas Instruments Incorporated 5 Application Hints www.ti.com 8 Application Hints 8.1 Power Dissipation and Device Operation The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. The allowable power dissipation for the device in a given package can be calculated using the following equation: PD_SYS = (TJ(MAX) - TA) / θJA (1) For the LM3687 there are two different main sources contributing to the systems power dissipation (PD_SYS): • the DC-DCconverter (PD_DCDC) • the linear regulator (PD_LIN) Neglecting switching losses and quiescent currents these two main contributors can be estimated by the following equations: PD_LIN = (VIN_LIN - VOUT_LIN) × IOUT_LIN PD_DCDC = IOUT_DCDC2× [(RDSON(P) × D) + (RDSON(N) × (1 - D))] (2) (3) with duty cycle D = VOUT_DCDC / VBATT. As an example, assuming the typical post regulation application, the conversion from VBATT = 3.6V to VOUT_DCDC = 1.8Vand further to VOUT_LIN = 1.5V, at maximum load currents, results in following power dissipations: PD_DCDC = (0.75A)2 × (0.38Ω × 1.8V / 3.6V + 0.25Ω × (1 - 1.8V /3.6V)) = 177mW and PD_LIN = (1.8V - 1.5V) × 0.35A = 105mW PD_SYS = 282mW With a θJA = 70°C/W for the DSBGA 9 package, this PD_SYS will cause a rise of the junction temperature TJ of: ΔTJ = PD_SYS × θJA = 20K For the same conditions but the linear regulator biased from VBATT, this results in a PD_LIN of 735mW, PD_DCDC = 50mW (because IOUT_DCDC = 400mA) and therefore an increase of TJ = 55K. As lower total power dissipation translates to higher efficiency this example highlights the advantage of the post regulation setup. 6 AN-1647 LM3687 Evaluation Board SNVA249A – July 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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