LM3743
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SNVS427E – SEPTEMBER 2006 – REVISED APRIL 2013
LM3743 High-Performance Synchronous Buck Controller with Comprehensive Fault
Protection Features
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FEATURES
DESCRIPTION
•
•
•
The LM3743 is a DC-DC voltage mode PWM buck
controller featuring synchronous rectification at 300
kHz or 1 MHz. It can deliver current as high as 20A
and step down from an input voltage between 3V and
5.5V down to a minimum output voltage of 0.8V, with
a ±1.75% internal reference accuracy. The LM3743
provides a set of comprehensive fault protection
features such as high-side current limit, output undervoltage protection, and low-side current limit. When
any of these fault protection features are engaged, it
enters a hiccup protection mode which is suitable for
high reliability systems such as rack mounted servers
and telecom base station subsystems. The LM3743
also employs a proprietary monolithic glitch free prebias start-up method suited for FPGA and ASIC logic
devices. An external programmable soft-start allows
for tracking and timing flexibility. The driver features
1.6Ω of pull-up resistance and 1Ω of pull-down drive
resistance for high power density and very efficient
power processing.
1
2
•
•
•
•
•
•
•
Input Voltage From 3.0V to 5.5V
Output Voltage Adjustable Down to 0.8V
Reference Accuracy: ±1.75%, over Full
Temperature and Input Voltage Range
High-Side and Low-Side N-Channel MOSFETs
Switching Frequency Options of 1 MHz or 300
kHz
Comprehensive Fault Protection Features:
– High-Side Current Limit
– Low-Side Current Limit
– Output Under-Voltage Protection
Hiccup Mode Protection Eliminates Thermal
Runaway During Fault Conditions
Externally Programmable Soft-Start with
Tracking Capability
Pre-Bias Start-Up Capability
VSSOP-10 Package
APPLICATIONS
•
•
•
•
•
•
Rack-Mount Servers
Telecom Base Stations
Routers
Printers/Scanners
Multi-Media Set-Top Boxes
FPGAs, ASICs, and DSPs
Typical Application
VIN
D1
R6
BOOT
C10
VCC
HGATE
C3
C1
Q1
+
+
C2
SW
LM3743
SS/TRACK
LGATE
C4
VOUT
L1
R1
ILIM
Q2
+
C5
GND
COMP/EN
FB
R2
R5
C8
C7
C9
R4
R3
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM3743
SNVS427E – SEPTEMBER 2006 – REVISED APRIL 2013
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Connection Diagram
1
2
3
4
5
VCC
BOOT
HGATE
LGATE
GND
ILIM
FB
LM3743
SW
SS/TRACK
COMP/EN
10
9
8
7
6
Figure 1. 10-Lead Plastic VSSOP (Top View)
See Package Number DGS
PIN DESCRIPTIONS
VCC (Pin 1)
Supply rail for the controller section of the IC. A minimum capacitance of 1 µF, preferably a multi-layer
ceramic capacitor type (MLCC), must be connected as close as possible to the VCC and GND pin and a
1 to 4.99Ω resistance must be connected in series from the supply rail to the Vcc pin. See VCC Filtering
in the Design Consideration section for further details.
LGATE (Pin 2)
Gate drive for the low-side N-channel MOSFET. This signal is interlocked with HGATE to avoid a shootthrough problem.
GND (Pin 3)
Power ground (PGND) and signal ground (SGND). Connect the bottom feedback resistor between this
pin and the feedback pin.
ILIM (Pin 4)
Low side current limit threshold setting pin. This pin sources a fixed 50 µA current. A resistor of
appropriate value should be connected between this pin and the drain of the low-side N-FET.
FB (Pin 5)
Feedback pin. This is the inverting input of the error amplifier used for sensing the output voltage and
compensating the control loop.
COMP/EN (Pin 6)
Output of the error amplifier and enable pin. The voltage level on this pin is compared with an internally
generated ramp signal to determine the duty cycle. This pin is necessary for compensating the control
loop. Forcing this pin to ground will shut down the IC.
SS/TRACK (Pin 7)
Soft-start and tracking pin. This pin is connected to the non-inverting input of the error amplifier during
initial soft-start, or any time the voltage is below the reference. To track the rising ramp of another power
supply's output, connect a resistor divider from the output of that supply to this pin as described in
Application Information.
SW (Pin 8)
Switch pin. The lower rail of the high-side N-FET driver. Also used for the high side current limit sensing.
HGATE (Pin 9)
Gate drive for the high-side N-channel MOSFET. This signal is interlocked with LGATE to avoid a shootthrough problem.
BOOT (Pin 10)
Supply rail for the N-channel MOSFET high gate drive. The voltage should be at least one gate
threshold above the regulator input voltage to properly turn on the high-side N-FET. See MOSFET
GATE DRIVE in the Application Information section for more details on how to select MOSFETs.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2)
VCC
-0.3V to 6V
SW to GND
-0.3V to 6V
Boot to GND
-0.3V to 12V
Boot to SW
-0.3V to 6V
SS/TRACK, ILIM, COMP/EN,FB to GND
-0.3V to VCC
Junction Temperature
150°C
Storage Temperature
−65°C to 150°C
Lead Temperature (soldering, 10sec)
Soldering Information
260°C
Infrared or Convention (20sec)
235°C
ESD Rating (3)
(1)
(2)
(3)
+ / – 2 kV
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device operates correctly. Operating Ratings do not imply specified performance limits.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
ESD using the human body model which is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per
JESD22–A114.
Operating Ratings
Supply Voltage Range, VCC (1)
3.0V to 5.5V
−40°C to +125°C
Junction Temperature Range (TJ)
(1)
Practical lower limit of VCC depends on selection of the external MOSFET. See the MOSFET GATE DRIVE section under Application
Information for further details.
Electrical Characteristics
VCC = 3.3V, COMP/EN floating unless otherwise indicated in the conditions column. Limits in standard type are for TJ = 25°C
only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits
are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ =
25°C, and are provided for reference purposes only.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
0.814
V
2.84
3.0
SYSTEM PARAMETERS
VFB
VUVLO
FB pin voltage in regulation
3.0V ≤ VCC ≤ 5.5V
UVLO thresholds
Input voltage rising
0.786
Input voltage falling
IVCC
ISS/TRACK
2.45
2.66
V
Operating VCC current
fSW = 300 kHz, LM3743-300
1.5
2.5
mA
Operating VCC current
fSW = 1 MHz, LM3743-1000
1.8
3.0
mA
Shutdown VCC current
COMP/EN = 0V
6
50
µA
µA
SS/TRACK pin source current
VSS/TRACK = 0V
IILIM
ILIM pin source current
VILIM = 0V
VILIM
Current Limit Trip Level
ICOMP/EN
COMP/EN pin pull-up current
VCOMP/EN = 0V
VHS-CLIM
High-side current limit threshold
Measured at VCC pin with respect to SW
8
10.2
12.5
42.5
50
57.5
µA
–25
0
25
mV
4
µA
500
mV
Error Amplifier Unity Gain Bandwidth
30
MHz
Error Amplifier DC Gain
90
dB
0.5
V/µs
ERROR AMPLIFER
GBW
G
SR
Error Amplifier Slew Rate
IFB
FB pin Bias Current
IEAO
CCOMPENSATION = 2.2 nF, IEAO = 1 mA
10
EAO pin sourcing/sinking current capability
VCOMP/EN = 1.5, VFB = 0.75V
1.7
VCOMP/EN = 1.5, VFB = 0.85V
-1
VBOOT-VSW = 3.3V, VCOMP/EN = 0V
25
200
nA
mA
GATE DRIVE
ISHDN-BOOT
BOOT Pin Shutdown Current
50
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µA
3
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Electrical Characteristics (continued)
VCC = 3.3V, COMP/EN floating unless otherwise indicated in the conditions column. Limits in standard type are for TJ = 25°C
only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits
are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ =
25°C, and are provided for reference purposes only.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RHG-UP
High Side MOSFET Driver Pull-up ON
resistance
VBOOT-VSW = 3.3V, IHGATE = 350mA
(sourcing)
1.6
Ω
RHG-DN
High Side MOSFET Driver Pull-down ON
resistance
VBOOT-VSW = 3.3V, IHGATE = 350mA
(sinking)
1
Ω
RLG-UP
Low Side MOSFET Driver Pull-up ON
resistance
VCC = 3.3V, ILGATE = 350mA (sourcing)
1.6
Ω
RLG-DN
Low Side MOSFET Driver Pull-down ON
resistance
VCC = 3.3V, ILGATE = 350mA (sinking)
1
Ω
OSCILLATOR
fSW
DMAX
VRAMP
Oscillator Frequency
Max Duty Cycle
3.0V ≤ VCC ≤ 5.5V, LM3743-300
255
300
345
3.0V ≤ VCC ≤ 5.5V, LM3743-1000
850
1000
1150
fSW = 300 kHz, LM3743-300
85
91
fSW = 1 MHz, LM3743-1000
69
76
PWM Ramp Amplitude
kHz
%
1.0
V
LOGIC INPUTS AND OUTPUTS
VCOMP/EN-HI COMP/EN pin logic high trip-point
0.65
VCOMP/EN-LO COMP/EN pin logic low trip-point
0.1
0.9
V
0.45
V
HICCUP MODE
NLSCYCLES
Low-side sensing cycles before hiccup mode
15
Cycles
NLSRESET
Low-side sensing cycles reset without
activating current limit
32
Cycles
VUVP
Under Voltage Protection comparator
threshold
400
mV
7
µs
Hiccup timeout
5.5
ms
Soft-start time coming out of hiccup mode
3.6
ms
235
°C/W
tGLICH-UVP
tHICCUP
tSS
Under Voltage Protection fault time before
hiccup mode
THERMAL RESISTANCE
θJA
4
Junction to Ambient Thermal Resistance
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Block Diagram
VCC
SS/TRACK
10 PA
ILIMHS
VREF
SS Comp/
Hiccup
Logic
ILIMLS
UVLO
OSC
300 kHz/1 MHz
15%
2.84V
2.66V
BOOT
0.8V ±1.75%
UVP
HGATE
UVP
50%
Error Amp
2.2V
1.2V
+
FB
SYNC Drive
Logic
+
-
-
SW
PWM
Comp
4 PA
LGATE
COMP/EN
LS Ilim
Comparator
ILIMLS
SD COMP
+
50 PA
GND
HS Ilim
Comparator
SD
ILIMHS
-
-
SW
+
VCC - 0.5V
ILIM
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Typical Performance Characteristics
VIN = 3.3, TJ = 25°C, ILOAD = 1A unless otherwise specified.
DMax vs Temperature fSW = 1 MHZ
DMax vs Temperature fSW = 300 kHz
Figure 2.
Figure 3.
FB vs Temperature fSW = 1 MHZ
FB vs Temperature fSW = 300 kHz
Figure 4.
Figure 5.
Frequency vs Temperature fSW = 1 MHz
Frequency vs Temperature
fSW = 300 kHz
1.5
fSW NORMALIZED (%)
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-50
-25
0
25
50
75
100
125
TEMPERATURE (oC)
Figure 6.
6
Figure 7.
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Typical Performance Characteristics (continued)
VIN = 3.3, TJ = 25°C, ILOAD = 1A unless otherwise specified.
Frequency vs VCC fSW = 1 MHz
Frequency vs VCC fSW = 300 kHz
Figure 8.
Figure 9.
ISHDN_BOOT vs Temperature fSW = 1 MHz
ISHDN_BOOT vs Temperature fSW = 300 kHz
Figure 10.
Figure 11.
ILIM vs Temperature fSW = 1 MHz
ILIM vs Temperature fSW = 300 kHz
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VIN = 3.3, TJ = 25°C, ILOAD = 1A unless otherwise specified.
8
IVCC vs Temperature fSW = 1 MHz
IVCC vs Temperature fSW = 300 kHz
Figure 14.
Figure 15.
Line Regulation VOUT = 1.2V, IOUT = 1A, fSW = 300 kHz
Line Regulation VOUT = 1.5V, IOUT = 1A, fSW = 1 MHz
Figure 16.
Figure 17.
Load Regulation VIN = 3.3V, fSW = 1 MHz
Load Regulation VIN = 3.3V, fSW = 300 kHz
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
VIN = 3.3, TJ = 25°C, ILOAD = 1A unless otherwise specified.
Efficiency vs Load fSW = 300 kHz, VIN = 5.0V
(Refer to Figure 56)
Efficiency vs Load fSW = 300 kHz, VOUT = 2.5V
(Refer to Figure 56)
Figure 20.
Figure 21.
Efficiency vs Load fSW = 300 kHz, VIN = 5.0V
(Refer to Figure 56)
Efficiency vs Load fSW = 300 kHz, VOUT = 1.8V
(Refer to Figure 56)
Figure 22.
Figure 23.
Efficiency vs Load fSW = 300 kHz, VOUT = 3.3V
(Refer to Figure 56)
Efficiency vs Load fSW = 300 kHz, VOUT = 1.5V
(Refer to Figure 56)
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
VIN = 3.3, TJ = 25°C, ILOAD = 1A unless otherwise specified.
10
Efficiency vs Load fSW = 300 kHz, VOUT = 1.2V
(Refer to Figure 56)
Efficiency vs Load fSW = 300 kHz, VOUT = 1.0V
(Refer to Figure 56)
Figure 26.
Figure 27.
Efficiency vs Load fSW = 300 kHz, VOUT = 0.8V
(Refer to Figure 56)
Efficiency vs Load fSW = 1 MHz, VOUT = 2.5V
(Refer to AN-1450 (SNVA151) for BOM)
Figure 28.
Figure 29.
Efficiency vs Load fSW = 1 MHz, VOUT = 1.8V
(Refer to AN-1450 (SNVA151) for BOM)
Efficiency vs Load fSW = 1 MHz, VOUT = 1.5V
(Refer to AN-1450 (SNVA151) for BOM)
Figure 30.
Figure 31.
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Typical Performance Characteristics (continued)
VIN = 3.3, TJ = 25°C, ILOAD = 1A unless otherwise specified.
Efficiency vs Load fSW = 1 MHz, VOUT = 1.2V
(Refer to AN-1450 (SNVA151) for BOM)
Efficiency vs Load fSW = 1 MHz, VOUT = 1.0V
(Refer to AN-1450 (SNVA151) for BOM)
Figure 32.
Figure 33.
Efficiency vs Load fSW = 1 MHz, VOUT = 0.8V
(Refer to AN-1450 (SNVA151) for BOM)
Efficiency vs Load fSW = 300 kHz, VOUT = 2.5V
(Refer to AN-1450 (SNVA151) for BOM)
Figure 34.
Figure 35.
Efficiency vs Load fSW = 300 kHz, VOUT = 1.8V
(Refer to AN-1450 (SNVA151) for BOM)
Efficiency vs Load fSW = 300 kHz, VOUT = 1.5V
(Refer to AN-1450 (SNVA151) for BOM)
Figure 36.
Figure 37.
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Typical Performance Characteristics (continued)
VIN = 3.3, TJ = 25°C, ILOAD = 1A unless otherwise specified.
Efficiency vs Load fSW = 300 kHz, VOUT = 1.2V
(Refer to AN-1450 (SNVA151) for BOM)
Efficiency vs Load fSW = 300 kHz, VOUT = 1.0V
(Refer to AN-1450 (SNVA151) for BOM)
Figure 38.
Figure 39.
Efficiency vs Load fSW = 300 kHz, VOUT = 0.8V
(Refer to AN-1450 (SNVA151) for BOM)
Load Transient Response fSW = 1 MHz, VIN = 3.3V, ILOAD =
100 mA to 3.5A
(Refer to AN-1450 (SNVA151) for BOM)
2A/DIV
IOUT
20 mV/DIV
VOUT
100 µs/DIV
Figure 40.
Figure 41.
Load Transient Response
fSW = 300 kHz, VIN = 3.3V, ILOAD = 100 mA to 3.5A
(Refer to AN-1450 (SNVA151) for BOM)
2A/DIV
IOUT
VOUT
20 mV/DIV
100 µs/DIV
Figure 42.
12
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Typical Performance Characteristics (continued)
VIN = 3.3, TJ = 25°C, ILOAD = 1A unless otherwise specified.
Shutdown RLOAD = 1Ω, VIN = 5V
Pre Bias Startup
2V/DIV
VOUT3
SW
VOUT2
500 mV/DIV
VOUT1
COMP/
EN
VOUT
1V/DIV
1V/DIV
400 µs/DIV
2 ms/DIV
Figure 43.
Figure 44.
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APPLICATION INFORMATION
THEORY OF OPERATION
The LM3743 is a voltage mode PWM buck controller featuring synchronous rectification at 300 kHz or 1 MHz. In
steady state operation the LM3743 is always synchronous even at no load, thus simplifying the compensation
design. The LM3743 ensures a smooth and controlled start-up to support pre-biased outputs. Two levels of
current limit protection enhance the robustness of the power supply and requires no current sense resistor in the
power path. The primary level of protection is the low side current limit and is achieved by sensing the voltage
VDS across the low side MOSFET. The second level of protection is the high side current limit, which protects
power components from extremely high currents, caused by switch node short to ground.
NORMAL OPERATION
While in normal operation, the LM3743 IC controls the output voltage by controlling the duty cycle of the power
FETs. The DC level of the output voltage is determined by a pair of feedback resistors using the following
equation:
VOUT = 0.8 x
R3 + R2
R3
(1)
(Designators refer to the Typical Application in the front page)
For synchronous buck regulators, the duty ratio D is approximately equal to:
VOUT
D=
VIN
(2)
START UP
The LM3743 IC begins to operate when the COMP/EN pin is released from a clamped condition and the voltage
at the VCC pin has exceeded 2.84V. Once these two conditions have been met the internal 10µA current source
begins to charge the soft-start capacitor connected at the SS/TRACK pin. During soft-start the voltage on the
soft-start capacitor is connected internally to the non-inverting input of the error amplifier. The soft-start period
lasts until the voltage on the soft-start capacitor exceeds the LM3743 reference voltage of 0.8V. At this point the
reference voltage takes over at the non-inverting error amplifier input. The capacitance determines the length of
the soft-start period, and can be approximated by:
C4 = (tSS x 10 µA) / 0.8V
where
•
tSS is the desired soft-start time
(3)
In the event of either VCC falling below UVLO or COMP/EN pin being pulled below 0.45V, the soft-start pin will
discharge C4 to allow the output voltage to recover smoothly.
START UP WITH PRE-BIAS
A pre-bias output is a condition in which current from another source has charged up the output capacitor of the
switching regulator before it has been turned on. The LM3743 features a proprietary glitch free monotonic prebias start-up method designed to ramp the output voltage from a pre-biased rail to the target nominal output
voltage. The IC limits the on time of the low-side FET to 150 ns (typ) during soft-start, while allowing the highside FET to adjust it's time according to soft-start voltage, VOUT, and the internal voltage ramp. Any further
commutation of the load current is carried by the body diode of the low-side FET or an external Schottky diode, if
used. The low side current limit is active during soft-start while allowing the asynchronous switching. When softstart is completed, the on-time of the low-side FET is allowed to increase in a controlled fashion up to the steady
state duty cycle determined by the control loop. A plot of the LM3743 starting up into a pre-biased condition is
shown in the Typical Performance Characteristics section.
Note that the pre-bias voltage must not be greater than the target output voltage of the LM3743, otherwise the
LM3743 will pull the pre-bias supply down during steady state operation.
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TRACKING WITH EQUAL SOFT-START TIME
The LM3743 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS/TRACK pin. In this way, the output voltage slew rate of the LM3743 will be controlled by the master
supply for loads that require precise sequencing. When the tracking function is used, no soft-start capacitor
should be connected to the SS/TRACK pin. However in all other cases, a capacitor value (C4) of at least 560 pF
should be connected between the soft-start pin and ground.
Master Power
Supply
VOUT1 = 5V
RT2
1 k:
VOUT2 = 1.8V
SS/TRACK
VSS = 0.85V
RT1
205:
LM3743
FB
R2
10 k:
VFB
R3
7.87 k:
Figure 45. Tracking Circuit
One way to use the tracking feature is to design the tracking resistor divider so that the master supply’s output
voltage (VOUT1) and the LM3743’s output voltage (represented symbolically in Figure 45 as VOUT2, therefore
without explicitly showing the power components) both rise together and reach their target values at the same
time. For this case, the equation governing the values of the tracking divider resistors RT1 and RT2 is:
0.85
x RT2
RT1 = V
OUT1 - 0.85
(4)
The top resistance RT2 must be set to 1 kΩ in order to limit current into the LM3743 during UVLO or shutdown.
The final voltage of the SS/TRACK pin should be slightly higher than the feedback voltage of 0.8V, say about
0.85V as in the above equation. The 50 mV difference will ensure the LM3743 to reach regulation slightly before
the master supply. If the master supply voltage was 5V and the LM3743 output voltage was 1.8V, for example,
then the value of RT1 needed to give the two supplies identical soft-start times would be 205Ω. A timing diagram
for the equal soft-start time case is shown in Figure 46.
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5V
VOUT1
1.8V
VOUT2
Figure 46. Tracking with Equal Soft-Start Time
TRACKING WITH EQUAL SLEW RATES
The tracking feature can alternatively be used not to make both rails reach regulation at the same time but rather
to have similar rise rates (in terms of output dV/dt). In this case, the tracking resistors can be determined based
on the following equation:
RT1 =
0.80
x RT2
VOUT2 - 0.80
(5)
For the example case of VOUT1 = 5V and VOUT2 = 1.8V, with RT2 set to 1 kΩ as before, RT1 is calculated from the
above equation to be 887Ω. A timing diagram for the case of equal slew rates is shown in Figure 47.
5V
1.8V
VOUT1
1.8V
VOUT2
Figure 47. Tracking with Equal Slew Rate
TRACKING AND SHUTDOWN SEQUENCING
LM3743 is designed to track the output of a master power supply during start-up, but when the master supply
powers down the output capacitor of the LM3743 will discharge cycle by cycle through the low-side FET. The offtime will reach 100% when the voltage at the track pin reaches zero volts. This condition will persist as long as
the master output voltage is zero volts and the drivers of the LM3743 are still on. For example if the load is
required to not be discharged, the drivers must be shut-off before the master powers down. This is achieved by
shutting down the LM3743 or bring VCC below UVLO falling threshold. In this case the load will not be
discharged.
16
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SHUTDOWN
The LM3743 IC can be put into shutdown mode by bringing the voltage at the COMP/EN pin below 0.45V (typ).
The quiescent current during shutdown is approximately 6 µA (typ). During shutdown both the high-side and lowside FETs are disabled. The soft-start capacitor is discharged through an internal FET so that the output voltage
rises in a controlled fashion when the part is enabled again. When enabled a 4 µA pull-up current increases the
charge of the compensation capacitors.
UNDER VOLTAGE LOCK-OUT (UVLO)
If VCC drops below 2.66V (typ), the chip enters UVLO mode. UVLO consists of turning off the top and bottom
FETs and remaining in that condition until VCC rises above 2.84V (typ). As with shutdown, the soft-start capacitor
is discharged through an internal FET, ensuring that the next start-up will be controlled by the soft-start circuitry.
MOSFET GATE DRIVE
The LM3743 has two gate drivers designed for driving N-channel MOSFETs in synchronous mode. Power for the
high gate driver is supplied through the BOOT pin, while driving power for the low gate is provided through the
VCC pin. The BOOT voltage is supplied from a local charge pump structure which consists of a Schottky diode
and 0.1 µF capacitor, shown in Figure 48. Since the bootstrap capacitor (C10) is connected to the SW node, the
peak voltage impressed on the BOOT pin is the sum of the input voltage (VIN) plus the voltage across the
bootstrap capacitor (ignoring any forward drop across the bootstrap diode). The bootstrap capacitor is charged
up by VIN (called VBOOT_DC here) whenever the upper MOSFET turns off.
VCC
LM3743
BOOT
D1
C10
VIN
HG
+
VO
+
LG
GND
Figure 48. Charge Pump Circuit and Driver Circuitry
The output of the low-side driver swings between VCC and ground, whereas the output of the high-side driver
swings between VIN + VBOOT_DC and VIN. To keep the high-side MOSFET fully on, the Gate pin voltage of the
MOSFET must be higher than its instantaneous Source pin voltage by an amount equal to the 'Miller plateau'. It
can be shown that this plateau is equal to the threshold voltage of the chosen MOSFET plus a small amount
equal to IOUT/g. Here IOUT is the maximum load current of the application, and g is the transconductance of this
MOSFET (typically about 100 for logic-level devices). That means we must choose VBOOT_DC to at least exceed
the Miller plateau level. This may therefore affect the choice of the threshold voltage of the external MOSFETs,
and that in turn may depend on the chosen VIN rail.
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So far in the discussion above, the forward drop across the bootstrap diode has been ignored. But since that
does affect the output of the driver, it is a good idea to include this drop in the following examples. Looking at the
Typical Application schematic, this means that the difference voltage VIN - VD1, which is the voltage the bootstrap
capacitor charges up to, must always be greater than the maximum tolerance limit of the threshold voltage of the
upper MOSFET. Here VD1 is the forward voltage drop across the bootstrap diode D1. This voltage drop may
place restrictions on the type of MOSFET selected.
The capacitor C10 serves to maintain enough voltage between the top MOSFET gate and source to control the
device even when the top MOSFET is on and its source has risen up to the input voltage level. The charge pump
circuitry is fed from VIN, which can operate over a range from 3.0V to 5.5V. Using this basic method the voltage
applied to the high side gate VIN - VD1. This method works well when VIN is 5V±10%, because the gate drives will
get at least 4.0V of drive voltage during the worst case of VIN-MIN = 4.5V and VD1-MAX = 0.5V. Logic level
MOSFETs generally specify their on-resistance at VGS = 4.5V. When VCC = 3.3V±10%, the gate drive at worst
case could go as low as 2.5V. Logic level MOSFETs are not ensured to turn on, or may have much higher onresistance at 2.5V. Sub-logic level MOSFETs, usually specified at VGS = 2.5V, will work, but are more expensive
and tend to have higher on-resistance.
LOW-SIDE CURRENT LIMIT
The main current limit of the LM3743 is realized by sensing the voltage drop across the low-side FET as the load
current passes through it. The RDSON of the MOSFET is a known value; hence the voltage across the MOSFET
can be determined as:
VDS = IOUT x RDSON
(6)
The current flowing through the low-side MOSFET while it is on is the falling portion of the inductor current. The
current limit threshold is determined by an external resistor, R1, connected between the switching node and the
ILIM pin. A constant current (IILIM) of 50 µA typical is forced through R1, causing a fixed voltage drop. This fixed
voltage is compared against VDS and if the latter is higher, the current limit of the chip has been reached. To
obtain a more accurate value for R1 you must consider the operating values of RDSON and IILIM at their operating
temperatures in your application and the effect of slight parameter variations from part to part. R1 can be found
by using the following equation using the RDSON value of the low side MOSFET at it's expected hot temperature
and the absolute minimum value expected over the full temperature range for the IILIM which is 42.5 µA:
R1 = RDSON-HOT x ICLIM / IILIM
(7)
For example, a conservative 15A current limit (ICLIM) in a 10A design with a RDSON-HOT of 10 mΩ would require a
3.83 kΩ resistor. The LM3743 enters current limit mode if the inductor current exceeds the set current limit
threshold. The inductor current is first sampled 50 ns after the low-side MOSFET turns on. Note that in normal
operation mode the high-side MOSFET always turns on at the beginning of a clock cycle. In current limit mode,
by contrast, the high-side MOSFET on-pulse is skipped. This causes inductor current to fall. Unlike a normal
operation switching cycle, however, in a current limit mode switching cycle the high-side MOSFET will turn on as
soon as inductor current has fallen to the current limit threshold.
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Normal Operation
Current Limit
ILIM
IL
D
Figure 49. Current Limit Threshold
The low-side current sensing scheme can only limit the current during the converter off-time, when inductor
current is falling. Therefore in a typical current limit plot the valleys are normally well defined, but the peaks are
variable, according to the duty cycle, see Figure 49. The PWM error amplifier and comparator control the pulse
of the high-side MOSFET, even during current limit mode, meaning that peak inductor current can exceed the
current limit threshold. For example, during an output short-circuit to ground, and assuming that the output
inductor does not saturate, the maximum peak inductor current during current limit mode can be calculated with
the following equation:
IPK-CL = ICLIM + (TSW - 200 ns)
VIN - VO
L
where
•
TSW is the inverse of switching frequency fSW
(8)
The 200 ns term represents the minimum off-time of the duty cycle, which ensures enough time for correct
operation of the current sensing circuitry.
In order to minimize the temperature effects of the peak inductor currents, the IC enters hiccup mode after 15
over current events, or a long current limit event that lasts 15 switching cycles (the counter is reset when 32 noncurrent limit cycles occur in between two current limit events). Hiccup mode will be discussed in further detail in
the “Hiccup Mode and Internal Soft-Start” section.
HIGH-SIDE COARSE CURRENT LIMIT
The LM3743 employs a comparator to monitor the voltage across the high-side MOSFET when it is on. This
provides protection for short circuits from switch node to ground or the case when the inductor is shorted, which
the low side current limit cannot detect. A 200 ns blanking time period after the high-side FET turns on is used to
prevent switching transient voltages from tripping the high-side current limit without cause. If the difference
between VCC pin and SW pin voltage exceeds 500 mV, the LM3743 will immediately enter hiccup mode (see
HICCUP MODE AND INTERNAL SOFT-START section).
OUTPUT UNDER-VOLTAGE PROTECTION (UVP)
After the end of soft-start the output UVP comparator is activated. The threshold is 50% of the feedback voltage.
Once the comparator indicates UVP for more than 7 µs typ. (glitch filter time), the IC goes into hiccup mode.
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HICCUP MODE AND INTERNAL SOFT-START
Hiccup protection mode is designed to protect the external components of the circuit (output inductor, FETs, and
input voltage source) from thermal stress. During hiccup mode, the LM3743 disables both the high-side and lowside FETs and begins a cool down period of 5.5 ms. At the conclusion of this cool down period, the regulator
performs an internal 3.6 ms soft-start. There are three distinct conditions under which the IC will enter the hiccup
protection mode:
1. The low-side current sensing threshold has exceeded the current limit threshold for fifteen sampled cycles,
see Figure 50. Each cycle is sampled at the start of each off time (tOFF). The low-side current limit counter is
reset when 32 consecutive non-current limit cycles occur in between two current limit events.
2. The high-side current limit comparator has sensed a differential voltage larger than 500 mV.
3. The voltage at the FB pin has fallen below 0.4V, and the UVP comparator has sensed this condition for 7 μs
(during steady state operation).
The band gap reference, the external soft-start, and internal hiccup soft-start of 3.6 ms (typ) connect to the noninverting input of the error amplifier through a multiplexer. The lowest voltage of the three connects directly to the
non-inverting input. Hiccup mode will not discharge the external soft-start, only UVLO or shut-down will. When in
hiccup mode the internal 5.5 ms timer is set, and the internal soft-start capacitor is discharged. After the 5.5 ms
timeout, the internal 3.6 ms soft-start begins, see Figure 51. During soft-start, only low-side current limit and high
side current limit can put the LM3743 into hiccup mode.
Current Limit
2 A/DIV
200 mV/DIV
IL1
5 V/DIV
LG
VOUT
10 Ps/DIV
2 ms/DIV
Figure 50. Entering Hiccup Mode
Figure 51. Hiccup Time-Out and Internal Soft-Start
For example, if the low-side current limit is 10A, then once in overload the low-side current limit controls the
valley current and only allows an average amount of 10A plus the ripple current to pass through the inductor and
FETs for 15 switching cycles. In such an amount of time, the temperature rise is very small. Once in hiccup
mode, the average current through the high-side FET is:
IHSF-AVE = (ICLIM + ΔI) x [ D(15 cycles x TSW) ] / 5.5 ms = 71mA
(9)
With an arbitrary D = 60%, ripple current of 3A, and a 300 kHz switching frequency.
The average current through the low-side FET is:
ILSF-AVE = (ICLIM + ΔI) x [ (1–D) x (15 cycles x TSW) ] / 5.5 ms = 47mA
(10)
And the average current through the inductor is:
IL-AVE = (ICLIM + ΔI) x [ (15 cycles x TSW) ] / 5.5 ms = 118mA
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DESIGN CONSIDERATIONS
The following is a design procedure for selecting all the components in the Typical Application circuit on the front
page. This design converts 5V (VIN) to 1.8V (VOUT) at a maximum load of 10A with an efficiency of 90% and a
switching frequency of 300 kHz. The same procedures can be followed to create many other designs with
varying input voltages, output voltages, load currents, and switching frequency.
Switching Frequency
Selection of the operating switching frequency is based on trade-offs between size, cost, efficiency, and
response time. For example, a lower frequency will require larger more expensive inductors and capacitors.
While a higher switching frequency will generally reduce the size of these components, but will have a reduction
in efficiency. Fast switching converters allow for higher loop gain bandwidths, which in turn have the ability to
respond quickly to load and line transients. For the example application we have chosen a 300 kHz switching
frequency because it will reduce the switching power losses and in turn allow for higher conduction losses
considering the same power loss criteria, thus it is possible to sustain a higher load current.
Output Inductor
The output inductor is responsible for smoothing the square wave created by the switching action and for
controlling the output current ripple (ΔIOUT) also called the AC component of the inductor current. The DC current
into the load is equal to the average current flowing in the inductor. The inductance is chosen by selecting
between trade-offs in efficiency, size, and response time. The recommended percentage of AC component to DC
current is 30% to 40%, this will provide the best trade-off between energy requirements and size, (read AN-1197
(SNVA038) for theoretical analysis). Another criteria is the ability to respond to large load transient responses;
the smaller the output inductor, the more quickly the converter can respond. The equation for output inductor
selection is:
L=
L=
VIN-MAX - VOUT
'IOUT x fSW
x DMIN
(12)
5.5V - 1.8V
1.8V
x
0.3 x 10A x 300 kHz 5.5V
(13)
L = 1.34 µH
(14)
Here we have plugged in the values for input voltage, output voltage, switching frequency, and 30% of the
maximum load current. This yields an inductance of 1.34 µH. The output inductor must be rated to handle the
peak current (also equal to the peak switch current), which is (IOUT + (0.5 x ΔIOUT)) = 11.5A, for a 10A design and
a AC current of 3A.
The Coiltronics DR125–1R5 is 1.5 µH, is rated to 13.8A RMS current, and has a direct current resistance (DCR)
of 3 mΩ. After selecting the Coiltronics DR125–1R5 for the output inductor, actual inductor current ripple must be
re-calculated with the selected inductance value. This information is needed to determine the RMS current
through the input and output capacitors. Re-arranging the equation used to select inductance yields the following:
VIN(MAX) - VOUT
'IOUT =
fSW x LACTUAL
x DMIN
(15)
VIN(MAX) is assumed to be 10% above the steady state input voltage, or 5.5V at VIN = 5.0V. The re-calculated
current ripple will then be 2.69A. This gives a peak inductor/switch current will be 11.35A.
Output Capacitor
The output capacitor in a switching regulator is selected on the basis of capacitance, equivalent series resistance
(ESR), size, and cost. In this example the output current is 10A and the expected type of capacitor is an
aluminum electrolytic, as with the input capacitors. An important specification in switching converters is the
output voltage ripple ΔVOUT. At 300 kHz the impedance of most capacitors is very small compared to ESR, hence
ESR becomes the main selection criteria. In this design the load requires a 2% ripple , which results in a ΔVOUT
of 36 mVP-P. Thus the maximum ESR is then:
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ESRMAX =
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'VOUT
'IOUT
(16)
ESRMAX is 13 mΩ. Aluminum electrolytic (Al-E), tantalum (Ta), solid aluminum, organic, and niobium (Nb)
capacitors are all popular in switching converters. In general, by the time enough capacitors have been paralleled
to obtain the desired ESR, the bulk capacitance is more than enough to supply the load current during a transient
from no-load to full load. The number and type of capacitors used depends mainly on their size and cost. One
exception to this is multi-layer ceramic capacitors. MLCCs have very low ESR, but also low capacitance in
comparison with other types. This makes them attractive for lower power designs. For higher power or for fast
load transients the number of MLCCs needed often increases the size and cost to unacceptable levels. Because
the load could transition quickly from 0 to 10A, more bulk capacitance is needed than the MLCCs can provide.
One compromise is a solid electrolytic POSCAP from Sanyo or SP-caps from Panasonic. POSCAP and SPcaps
often have large capacitances needed to supply currents for load transients, and low ESRs. The 6TPD470M by
Sanyo has 470 µF, and a maximum ESR of 10 mΩ. Solid electrolytics have stable ESR relative to temperature,
and capacitance change is relatively immune to bias voltage. Tantalums (Ta), niobium (Nb), and Al-E are good
solutions for ambient operating temperatures above 0°C, however their ESR tends to increase quickly below 0°C
ambient operating temperature, so these capacitor types are not recommended for this area of operation.
Input Capacitor
The input capacitors in a buck converter are subjected to high RMS current stress. Input capacitors are selected
for their ability to withstand the heat generated by the RMS current and the ESR as specified by the
manufacturer. Input RMS ripple current is approximately:
IRMS_RIP = IOUT x
D(1 - D)
where
•
duty cycle D = VOUT/VIN
(17)
The worst-case ripple for a buck converter occurs during full load and when the duty cycle (D) is 0.5.
When multiple capacitors of the same type and value are paralleled, the power dissipated by each input
capacitor is:
(IRMS_RIP)2 x ESR
PCAP =
n
where
•
•
n is the number of paralleled capacitors
ESR is the equivalent series resistance of each capacitor
(18)
The equation above indicates that power loss in each capacitor decreases rapidly as the number of input
capacitors increases. For this 5V to 1.8V design the duty cycle is 0.36. For a 10A maximum load the RMS
current is 4.8A.
Connect one or two 22 µF MLCC as close as possible across the drain of the high-side MOSFET and the source
of the low-side MOSFET, this will provide high frequency decoupling and satisfy the RMS stress. A bulk capacitor
is recommended in parallel with the MLCC in order to prevent switching frequency noise from reflecting back into
the input line, this capacitor should be no more than 1inch away from the MLCC capacitors.
MOSFETs
Selection of the power MOSFETs is governed by a trade-off between cost, size, and efficiency. One method is to
determine the maximum cost that can be endured, and then select the most efficient device that fits that price.
Using a spreadsheet to estimate the losses in the high-side and low-side MOSFETs is one way to determine
relative efficiencies between different MOSFETs. Good correlation between the prediction and the bench result is
not ensured.
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Losses in the high-side MOSFET can be broken down into conduction loss, gate charging loss, and switching
loss. Conduction, or I2R loss, is approximately:
For the high side FET:
PC = D (IOUT2 x RDSON-HI x 1.3)
(19)
For the low side FET:
PC = (1 - D) x (IOUT2 x RDSON-LO x 1.3)
(20)
In the above equations the factor 1.3 accounts for the increase in MOSFET RDSON due to heating. Alternatively,
the 1.3 can be ignored and the RDSON of the MOSFET estimated using the RDSON vs. Temperature curves in the
MOSFET manufacturer datasheet.
Gate charging loss results from the current driving the gate capacitance of the power MOSFETs, and is
approximated as:
PGC = (VCC) x QG x fSW
(21)
VCC is the driving voltage (see MOSFET GATE DRIVE section) and QG is the gate charge of the MOSFET. If
multiple devices will be placed in parallel, their gate charges can simply be summed to form a cumulative QG.
Switching loss occurs during the brief transition period as the high-side MOSFET turns on and off, during which
both current and voltage are present in the channel of the MOSFET. It can be approximated as:
PSW = 0.5 x VIN x IOUT x (tr + tf) x fSW
where
•
tr and tf are the rise and fall times of the MOSFET
(22)
Switching loss occurs in the high-side MOSFET only.
For this example, the maximum drain-to-source voltage applied to either MOSFET is 5.5V. The maximum drive
voltage at the gate of the high-side MOSFET is 5.0V, and the maximum drive voltage for the low-side MOSFET
is 5.5V. For designs between 5A and 10A, single MOSFETs in SO-8 provide a good trade-off between size, cost,
and efficiency.
VCC Filtering
To ensure smooth DC voltage for the chip supply a 1 µF (C3), X5R MLCC type or better must be placed as close
as possible to the VCC and GND pin. Together with a small 1 to 4.99Ω resistor placed between the input rail and
the VCC pin, a low pass filter is formed to filter out high frequency noise from injecting into the VCC rail. Since VCC
is also the sense pin for the high-side current limit, the resistor should connect close to the drain of the high-side
MOSFET to prevent IR drops due to trace resistance. A second design consideration is the low pass filter formed
by C3 and R6 on the VCC pin, a fast slew rate, large amplitude load transient may cause a larger voltage droop
on CIN than on VCC pin. This may lead to a lower current at which high-side protection may occur. Thus increase
the bulk input capacitor if the high-side current limit is engaging due to a dynamic load transient behavior as
explained above.
Bootstrap Diode (D1)
The MBR0520 and BAT54 work well as a bootstrap diode in most designs. Schottky diodes are the preferred
choice for the bootstrap circuit because of their low forward voltage drop. For circuits that will operate at high
ambient temperature the Schottky diode datasheet must be read carefully to ensure that the reverse current
leakage at high temperature does not increase enough to deplete the charge on the bootstrap capacitor while the
high side FET is on. Some Schottky diodes increase their reverse leakage by as much as 1000 times at high
temperatures. Fast rectifier and PN junction diodes maintain low reverse leakage even at high ambient
temperature. These diode types have higher forward voltage drop but can still be used for high ambient
temperature operation.
Control Loop Compensation
The LM3743 uses voltage-mode (‘VM’) PWM control to correct changes in output voltage due to line and load
transients. VM requires careful small signal compensation of the control loop for achieving high bandwidth and
good phase margin.
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The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle
modulator, output inductor, output capacitor, and load. The second part is the error amplifier, which for the
LM3743 is a 30 MHz op-amp used in the classic inverting configuration. Figure 52 shows the regulator and
control loop components.
L
RL
+ C
O
VIN
RO
+
RC
+
VRAMP
R5
C9
R2
R4
C8
C7
+
R3
+
-
VREF
Figure 52. Power Stage and Error Amp
One popular method for selecting the compensation components is to create Bode plots of gain and phase for
the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the
regulator easy to see. Software tools such as Excel, MathCAD, and Matlab are useful for showing how changes
in compensation or the power stage affect system gain and phase.
The power stage modulator provides a DC gain ADC that is equal to the input voltage divided by the peak-to-peak
value of the PWM ramp. This ramp is 1.0Vpk-pk for the LM3743. The inductor and output capacitor create a
double pole at frequency fDP, and the capacitor ESR and capacitance create a single zero at frequency fESR. For
this example, with VIN = 5.0V, these quantities are:
VIN
5.0
= 5V/V
=
ADC =
VRAMP 1.0
(23)
fDP =
fESR =
1
2S
RO + RL
LCO(RO + ESR)
1
2SCOESR
= 6 kHz
(24)
= 33.9 kHz
(25)
In the equation for fDP, the variable RL is the power stage resistance, and represents the inductor DCR plus the
on resistance of the top power MOSFET. RO is the output voltage divided by output current. The power stage
transfer function GPS is given by the following equation, and Figure 53 shows Bode plots of the phase and gain in
this example.
GPS =
AVIN x RO
VRAMP
x
sCORC + 1
2
as + bs + c
(26)
(27)
(28)
(29)
a = LCO(RO + RC)
b = L + CO(RORL + RORC + RCRL)
c = RO + RL
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20
0
10
-30
0
-60
PHASE (o)
GAIN (dB)
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-10
-90
-20
-120
-30
-150
-40
100
1k
10k
100k
1M
-180
100
FREQUENCY (Hz)
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 53. Power Stage Gain and Phase
The double pole at 6 kHz causes the phase to drop to approximately -140° at around 15 kHz. The ESR zero, at
33.9 kHz, provides a +90° boost that prevents the phase from dropping to -180º. If this loop were left
uncompensated, the bandwidth would be approximately 15 kHz and the phase margin 40°. In theory, the loop
would be stable, but would suffer from poor DC regulation (due to the low DC gain) and would be slow to
respond to load transients (due to the low bandwidth.) In practice, the loop could easily become unstable due to
tolerances in the output inductor, capacitor, or changes in output current, or input voltage. Therefore, the loop is
compensated using the error amplifier and a few passive components.
For this example, a Type III, or three-pole-two-zero approach gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including Type III, a single pole is placed at the origin to boost DC
gain as high as possible. Two zeroes fZ1 and fZ2 are placed at the double pole frequency to cancel the double
pole phase lag. Then, a pole, fP1 is placed at the frequency of the ESR zero. A final pole fP2 is placed at one-half
of the switching frequency. The gain of the error amplifier transfer function is selected to give the best bandwidth
possible without violating the Nyquist stability criteria. In practice, a good crossover point is one-fifth of the
switching frequency, or 60 kHz for this example. The generic equation for the error amplifier transfer function is:
s
+1
2SfZ1
GEA = AEA x
s
s
+1
2SfP1
s
+1
2SfZ2
s
+1
2SfP2
(30)
In this equation the variable AEA is a ratio of the values of the capacitance and resistance of the compensation
components, arranged as shown in Figure 52. AEA is selected to provide the desired bandwidth. A starting value
of 80,000 for AEA should give a conservative bandwidth. Increasing the value will increase the bandwidth, but will
also decrease phase margin. Designs with 45-60° are usually best because they represent a good trade-off
between bandwidth and phase margin. In general, phase margin is lowest and gain highest (worst-case) for
maximum input voltage and minimum output current. One method to select AEA is to use an iterative process
beginning with these worst-case conditions.
1. Increase AEA
2. Check overall bandwidth and phase margin
3. Change VIN to minimum and recheck overall bandwidth and phase margin
4. Change IO to maximum and recheck overall bandwidth and phase margin
The process ends when both bandwidth and phase margin are sufficiently high. For this example input voltage
can vary from 4.5V to 5.5V and output current can vary from 0 to 10A, and after a few iterations a moderate gain
factor of 90 dB is used.
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The error amplifier of the LM3743 has a unity-gain bandwidth of 30 MHz. In order to model the effect of this
limitation, the open-loop gain can be calculated as:
OPG =
2S x 30 MHz
s
(31)
The new error amplifier transfer function that takes into account unity-gain bandwidth is:
GEA x OPG
HEA =
1 + GEA + OPG
(32)
48
60
40
30
32
0
PHASE (o)
GAIN (dB)
The gain and phase of the error amplifier are shown in Figure 54.
24
-30
16
-60
8
-90
0
100
1k
10k
100k
1M
-120
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 54. Error Amp. Gain and Phase
In VM regulators, the top feedback resistor R2 forms a part of the compensation. Setting R2 to 10 kΩ±1%,
usually gives values for the other compensation resistors and capacitors that fall within a reasonable range.
(Capacitances > 1 pF, resistances
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