LM3880MF-1AA/NOPB

LM3880 LM3880 SNVS451M – AUGUST 2006 – REVISED MARCH 2021 SNVS451M – AUGUST 2006 – REVISED MARCH 2021 www.ti.com LM3880 Three-Rail Simple Power Supply Sequencer 1 Features 3 Description • The LM3880 simple power supply sequencer offers the easiest method to control powerup sequencing and powerdown sequencing of multiple Independent voltage rails. By staggering the startup sequence, it is possible to avoid latch conditions or large in-rush currents that can affect the reliability of the system. • • • • • • Simple solution for sequencing three voltage rails from a single input signal Easily cascade up to three devices to sequence as many as nine voltage rails Powerup and powerdown control Tiny 2.9-mm x 1.6-mm footprint Low quiescent current: 25 µA Input voltage range: 2.7 V to 5.5 V Standard timing options available 2 Applications • • • • • • • • Advanced driver assistance systems (ADAS) Automotive camera modules Security cameras Servers Networking elements FPGA power supply sequencing Microprocessor and microcontroller sequencing Multiple supply sequencing Available in a 6-pin SOT-23 package, the simple sequencer contains a precision enable pin and three open-drain output flags. The open-drain output flags permit that they can be pulled up to distinct voltage supplies separate from the sequencer VDD (only if they do not exceed the recommended maximum voltage of 0.3 V greater than VDD), so as to interface with ICs requiring a range of different enable signals. When the LM3880 is enabled, the three output flags sequentially release, after individual time delays, thus permitting the connected power supplies to start up. The output flags follow a reverse sequence during power down to avoid latch conditions. EPROM capability allows every delay and sequence to be fully adjustable. Contact Texas Instruments to request a non-standard configuration. Device Information (1) PART NUMBER LM3880 (1) PACKAGE DBV SOT (6) BODY SIZE (NOM) 2.90 mm × 1.60 mm For all available packages, see the orderable addendum at the end of the datasheet. Input Supply 1 VCC Enable 3 EN FLAG1 6 FLAG2 5 FLAG3 4 GND Enable Power Supply 1 Enable Power Supply 2 Enable Power Supply 3 2 Simple Power Supply Sequencing An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. 1 LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 6.6 Typical Characteristics................................................ 7 7 Detailed Description........................................................9 7.1 Overview..................................................................... 9 7.2 Functional Block Diagram........................................... 9 7.3 Feature Description.....................................................9 7.4 Device Functional Modes..........................................12 8 Application and Implementation.................................. 13 8.1 Application Information............................................. 13 8.2 Typical Application.................................................... 13 8.3 Dos and Don'ts..........................................................15 9 Layout.............................................................................18 9.1 Layout Guidelines..................................................... 18 9.2 Layout Example........................................................ 18 10 Device and Documentation Support..........................19 10.1 Device Support....................................................... 19 10.2 Community Resources............................................19 10.3 Trademarks............................................................. 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision L (November 2018) to Revision M (March 2021) Page • Specified device dimensions in Features section............................................................................................... 1 • Updated application curve titles........................................................................................................................14 Changes from Revision K (February 2016) to Revision L (November 2018) Page • Updated Features section to specify how many rails can be sequenced by a single device ............................ 1 • Added feature that devices can be cascaded ....................................................................................................1 • Specified device dimensions in Features section............................................................................................... 1 • Specified FPGA Power Supply Sequencing in Applications...............................................................................1 • Added note in description about open drain FLAG pins..................................................................................... 1 • Added I/O column to Pin Functions table........................................................................................................... 3 • Changed Part Nomenclature section to Device Nomenclature section............................................................ 19 Changes from Revision J (December 2014) to Revision K (February 2016) Page • Changed Handling Ratings to ESD Ratings and moved storage temperature to Absolute Maximum Ratings ... 4 • Removed “Customized Timing and Sequence” section ...................................................................................12 • Added cross references to timing diagrams..................................................................................................... 19 Changes from Revision I (March 2013) to Revision J (August 2014) Page • Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 4 Changes from Revision H (March 2013) to Revision I (March 2013) Page • Changed layout of National Data Sheet to TI format........................................................................................ 19 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 5 Pin Configuration and Functions VCC 1 6 FLAG1 GND 2 5 FLAG2 EN 3 4 FLAG3 Figure 5-1. DBV Package 6-Pin SOT-23 Top View Pin Functions PIN NAME NO. I/O(1) DESCRIPTION EN 3 I Precision enable pin FLAG1 6 O Open-drain output 1 FLAG2 5 O Open-drain output 2 FLAG3 4 O Open-drain output 3 GND 2 G Ground VCC 1 I Input supply (1) I = input, O = output, G = ground Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) (1) (2) MIN MAX UNIT VCC –0.3 6 V EN, FLAG1, FLAG2, FLAG3 –0.3 6 V Maximum Flag ON current 50 mA Maximum Junction temperature 150 °C Lead temperature (Soldering, 5 s) 260 °C 150 °C Storage temperature Tstg (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins VALUE UNIT ±2 kV (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC to GND 2.7 5.5 V EN, FLAG1, FLAG2, FLAG3 –0.3 VCC + 0.3 V Junction temperature –40 125 °C 6.4 Thermal Information LM3880 THERMAL METRIC(1) DBV (SOT-23) UNIT 6 PINS RθJA Junction-to-ambient thermal resistance 187.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 127.4 °C/W RθJB Junction-to-board thermal resistance 31.5 °C/W ψJT Junction-to-top characterization parameter 23.3 °C/W ψJB Junction-to-board characterization parameter 31.0 °C/W (1) 4 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 6.5 Electrical Characteristics Limits apply to all timing options and VCC = 3.3 V, unless otherwise specified. Minimum and Maximum limits apply over the full Operating Temperature Range (TJ = -40°C to +125°C) and are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. PARAMETER IQ MIN(1) TEST CONDITIONS Operating Quiescent current TYP(2) MAX(1) 25 80 µA 20 nA 0.4 V UNIT OPEN-DRAIN FLAGS IFLAG FLAGx Leakage Current VFLAGx = 3.3 V VOL FLAGx Output Voltage Low IFLAGx = 1.2 mA 1 POWER-UP SEQUENCE td1 Timer delay 1 accuracy td2 Timer delay 2 accuracy td3 Timer delay 3 accuracy All Other Timing Options –15% 15% 2 ms Timing Option –20% 20% All Other Timing Options –15% 15% 2 ms Timing Option –20% 20% All Other Timing Options –15% 15% 2 ms Timing Option –20% 20% POWER-DOWN SEQUENCE td4 Timer delay 4 accuracy td5 Timer delay 5 accuracy td6 Timer delay 6 accuracy All Other Timing Options –15% 15% 2 ms Timing Option –20% 20% All Other Timing Options –15% 15% 2 ms Timing Option –20% 20% All Other Timing Options –15% 15% 2 ms Timing Option –20% 20% 95% 105% TIMING DELAY ERROR (td(x) – 400 µs) / td(x+1) Ratio of timing delays td(x) / td(x+1) Ratio of timing delays For x = 1 or 4 For x = 1 or 4, 2 ms option 90% 110% For x = 2 or 5 95% 105% For x = 2 or 5, 2 ms option 90% 110% ENABLE PIN VEN EN pin threshold IEN EN pin pullup current (1) (2) 1.0 VEN = 0 V 1.25 1.4 7 V µA Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate the TI average outgoing quality level (AOQL). Typical numbers are at 25°C and represent the most likely parametric norm. EN FLAG1 FLAG2 FLAG3 td1 td2 td3 All standard options use Sequence 1 for output flags rise and fall order. Refer to section 11.1.2 for details of other possible sequences. Figure 6-1. Timing Requirements Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 EN FLAG1 FLAG2 FLAG3 td4 td5 td6 All standard options use Sequence 1 for output flags rise and fall order. Refer to section 11.1.2 for details of other possible sequences. Figure 6-2. Power-Down Sequence 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 6.6 Typical Characteristics 26 30 29 25 28 24 26 IQ (PA) IQ (PA) 27 25 23 24 22 23 22 21 21 20 2.5 3 3.5 4 4.5 5 20 -40 -25 -10 5 20 35 50 65 80 95 110 125 5.5 TEMPERATURE (oC) VCC (V) Figure 6-3. Quiescent Current vs Supply Voltage VCC = 3.3 V Figure 6-4. Quiescent Current vs Temperature 1.232 1.230 1.228 VEN (V) 1.226 1.224 RISING FALLING 1.222 1.220 1.218 1.216 1.214 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 6-5. Enable Threshold vs Temperature tDELAY = 30 ms Figure 6-6. Time Delay vs Supply Voltage Figure 6-7. Time Delay Ratio vs Temperature tDELAY = 30 ms Figure 6-8. Time Delay vs Temperature Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 LM3880 SNVS451M – AUGUST 2006 – REVISED MARCH 2021 RFLAG = 100 kΩ www.ti.com Figure 6-10. Flag Voltage vs Input Current Figure 6-9. Flag Voltage vs Supply Voltage 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 7 Detailed Description 7.1 Overview The LM3880 simple power supply sequencer provides a simple solution for sequencing multiple rails in a controlled manner. Six independent timers are integrated to control the timing sequence (power up and power down) of three open-drain output flags. These flags permit connection to either a shutdown or enable pin of linear regulators and switchers to control the operation of the power supplies. This allows design of a complete power system without concern for large inrush currents or latch-up conditions that can occur. The timing sequence of the device is controlled entirely by the enable (EN) pin. Upon power up, all the flags are held low until this precision enable is pulled high. When the EN pin is asserted, the power-up sequence starts. An internal counter delays the first flag (FLAG1) from rising until a fixed time period has expired. When the first flag is released, another timer will begin to delay the release of the second flag (FLAG2). This process repeats until all three flags have sequentially been released. The power-down sequence is the same as power-up sequence, but in reverse. When the EN pin is deasserted a timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a sequential manner after their appropriate delays. The three timers that are used to control the power-down scheme can also be individually programmed and are completely independent of the power-up timers. 7.2 Functional Block Diagram VCC 7 µA EN FLAG1 tD1 tD2 + 1.25 V FLAG2 tD3 Timing Delay Generation tD4 tD5 Master Clock Sequence Control FLAG3 tD6 EEPROM (Factory Set) GND 7.3 Feature Description 7.3.1 Enable Pin Operation The timing sequence of the LM3880 is controlled by the assertion of the enable signal. The enable pin is designed with an internal comparator, referenced to a bandgap voltage (1.25 V), to provide a precision threshold. This allows a delayed timing to be externally set using a capacitor or to start the sequencing based on a certain event, such as a line voltage reaching 90% of nominal. For an additional delayed sequence from the rail powering VCC, simply attach a capacitor to the EN pin as shown in Figure 7-1. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 7 µA EN + CEN Enable 1.25 V Figure 7-1. Capacitor Timing Using the internal pullup current source to charge the external capacitor (CEN) the enable pin delay can be calculated by Equation 1: tenable_delay = 1.25V x CEN 7 PA (1) A resistor divider can also be used to enable the device based on a certain voltage threshold. Take care when sizing the resistor divider to include the effects of the internal current source. One of the features of the EN pin is that it provides glitch free operation. The first timer will start counting at a rising threshold, but will always reset if the EN pin is deasserted before the first output flag is released. This can be shown in Figure 7-2: EN FLAG1 td1 Figure 7-2. EN Glitch 7.3.2 Incomplete Sequence Operation If the enable signal remains high for the entire power-up sequence, then the part will operate as shown in the standard timing diagrams. However, if the enable signal is de-asserted before the power-up sequence is completed the part will enter a controlled shutdown. This allows the system to walk through a controlled power cycling, preventing any latch conditions from occurring. This state only occurs if the enable pin is deasserted after the completion of timer 1, but before the entire power-up sequence is completed. When this event occurs, the falling edge of EN pin resets the current timer and will allow the remaining power-up cycle to complete before beginning the power-down sequence. The power down sequence starts approximately 120 ms after the final power-up flag. This allows output voltages in the system to stabilize before everything is shut down. Figure 7-3 shows this operation. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 EN FLAG1 FLAG2 FLAG3 td1 td2 td3 120 ms td4 td5 td6 Figure 7-3. Incomplete Power-Up Sequence When the enable signal is deasserted, the part will commence its power-down sequence. If the enable signal is pulled high before the power-down sequence is completed, the part will ensure completion of the power-down sequence before starting power-up. This ensures that the system does not partially power down and power up and helps prevent latch-up events, such as in FPGAs and microprocessors. This state only occurs if the enable pin is pulled high after the completion of timer 1, but before the entire power-down sequence is completed. When this event occurs, the rising edge of enable pin resets the current timer and will allow the remaining power-down cycle to complete before beginning the power-up sequence. The power-up sequence starts approximately 120 ms after the final power-down flag. This allows the system to fully shut down before it is powered up. Figure 7-4 shows this operation. EN FLAG1 FLAG2 FLAG3 td1t t td2t t td3t t t120 mst td4t t td5t t td6t t Figure 7-4. Incomplete Power-Down Sequence All the internal timers are generated by a master clock that has an extremely low tempco. This allows for tight accuracy across temperature and a consistent ratio between the individual timers. There is a slight additional delay of approximately 400 µs to timers 1 and 4, which is a result of the EPROM refresh. This refresh time is in addition to the programmed delay time and will be almost insignificant to all but the shortest of timer delays. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 LM3880 SNVS451M – AUGUST 2006 – REVISED MARCH 2021 www.ti.com 7.4 Device Functional Modes 7.4.1 Power Up With EN Pin The timing sequence of the Simple Power Supply Sequencer is controlled entirely by the enable (EN) pin. Upon power up, all the flags are held low until this precision enable is pulled high. After the EN pin is asserted, the power-up sequence will commence. 7.4.2 Power Down With EN Pin When EN pin is deasserted, the power down sequence will commence. A timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a sequential manner after their appropriate delays. 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Open Drain Flags Pullup The Simple Power Supply Sequencer contains three open-drain output flags which need to be pulled up for proper operation. 100-kΩ resistors can be used as pullup resistors. 8.1.2 Enable the Device See Section 7.3.1. 8.2 Typical Application 8.2.1 Simple Sequencing of Three Power Supplies The Simple Power Supply Sequencer is used to implement a power-up and power-down sequence of three power supplies. Sequence 1 for the LM3880, e.g. orderable part number LM3880MF-1AA has a power-up sequence (1 – 2 – 3) and power-down sequence (3 – 2 –1). See Table 10-1 and Table 10-2 for other sequence options or contact TI if other sequence options are desired. Figure 8-1. Typical Application Circuit Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 8.2.1.1 Design Requirements For this design example, use the parameters listed in Table 8-1 as the input parameters. The circuit shown in Figure 8-1 can have various power-down sequences depending on the sequence the part is programmed for. See Table 10-1 for power-down sequence options. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input Supply voltage range 2.7 V to 5.5 V Flag Output voltage, EN high Input Supply Flag Output voltage, EN low 0V Flag Timing Delay 30 ms Power-Up Sequence 1-2-3 Power-Down Sequence 3-2-1 8.2.1.2 Detailed Design Procedure Table 8-2. List of Materials DESIGNATOR DESCRIPTION DEVICE QUANTITY MANUFACTURER U1 LM3880, Sequence 1, 30 ms timing LM3880 1 Texas Instruments R1 100-kΩ Resistor, 0603 CRCW0603100KFKEA 1 Vishay R2 100-kΩ Resistor, 0603 CRCW0603100KFKEA 1 Vishay R3 100-kΩ Resistor, 0603 CRCW0603100KFKEA 1 Vishay This application uses the Sequence 1 and 30-ms timing options of the simple power supply sequencer. See Section 8.2.1.3 for details on the sequence and timing option. 8.2.1.3 Application Curves Figure 8-2. Powerup Sequence for LM3880MF-1AB 14 Submit Document Feedback Figure 8-3. Powerdown Sequence for LM3880MF-1AB Copyright © 2021 Texas Instruments Incorporated LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 8.2.2 Sequencing Using Independent Flag Supply For applications requiring a flag output voltage that is different from the VCC, a separate Flag Supply may be used to pullup the open-drain outputs of the simple power supply sequencer. This is useful when interfacing the flag outputs with inputs that require a different voltage than VCC. The designer must ensure the flag supply voltage is not taken above VCC + 0.3 V as specified in the Section 6.3. Figure 8-4. Sequencing Using Independent Flag Supply 8.3 Dos and Don'ts Connecting the EN pin to VCC is not recommended. During powerup sequencing, maintain the EN voltage to a level below the EN voltage threshold until VCC rises above the minimum operating voltage. If EN is connected to VCC, undefined operation at the flag outputs can occur, especially during slow VCC rising slew rates. For systems requiring only powerup sequencing, a capacitor at the EN pin can be used to create a delay or a resistor divider can be used to enable the device based on a certain voltage threshold. While these solutions work for powerup sequencing, it does not powerdown the flag outputs in sequential fashion because the flag outputs simply follow the input supply. For systems requiring both powerup and powerdown sequencing, use an external enable signal, such as a GPIO signal from a microcontroller, to properly control powerup and powerdown of the flag outputs. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 LM3880 SNVS451M – AUGUST 2006 – REVISED MARCH 2021 www.ti.com Figure 8-5. Recommended EN Connection 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com LM3880 SNVS451M – AUGUST 2006 – REVISED MARCH 2021 Power Supply Recommendations The VCC pin should be located as close as possible to the input supply (2.7–5.5 V). An input capacitor is not required but is recommended when noise might be present on the VCC pin. A 0.1-μF ceramic capacitor may be used to bypass this noise. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 9 Layout 9.1 Layout Guidelines • • Pullup resistors should be connected between the flag output pins and a positive input supply, usually VCC. An independent flag supply may also be used. These resistors should be placed as close as possible to the Simple Power Supply Sequencer and the flag supply. Minimal trace length is recommended to make the connections. A typical value for the pullup resistors is 100 kΩ. For very tight sequencing requirements, minimal and equal trace lengths should be used to connect the flag outputs to the desired inputs. This will reduce any propagation delay and timing errors between the flag outputs along the line. 9.2 Layout Example Figure 9-1 and Figure 9-2 are layout examples for the LM3880. These examples are taken from the LM3880EVAL. Figure 9-1. LM3880 Top Figure 9-2. LM3880 Bottom 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated LM3880 www.ti.com SNVS451M – AUGUST 2006 – REVISED MARCH 2021 10 Device and Documentation Support 10.1 Device Support 10.1.1 Device Nomenclature The list of parts available to order appear in the Package Option Addendum. Figure 10-1. Device Nomenclature Table 10-1. Sequence Designator Table (1) FLAG ORDER SEQUENCE NUMBER 1 (1) POWER UP POWER DOWN 1-2-3 3-2-1 2 1-2-3 3-1-2 3 1-2-3 2-3-1 4 1-2-3 2-1-3 5 1-2-3 1-3-2 6 1-2-3 1-2-3 See and Figure 6-2. Table 10-2. Timing Designator Table (1) TIMING DESIGNATOR (1) DELAYS (ms) td1 td2 td3 td4 td5 td6 AA 10 10 10 10 10 10 AB 30 30 30 30 30 30 AC 60 60 60 60 60 60 AD 120 120 120 120 120 120 AE 2 2 2 2 2 2 AF 16 16 16 16 16 16 See and Figure 6-2. 10.2 Community Resources 10.3 Trademarks All trademarks are the property of their respective owners. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 LM3880 SNVS451M – AUGUST 2006 – REVISED MARCH 2021 www.ti.com Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) (1) LM3880MF-1AA NRND SOT-23 DBV 6 1000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 125 F20A LM3880MF-1AA/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F20A LM3880MF-1AB/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F21A LM3880MF-1AC/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F22A LM3880MF-1AD/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F23A LM3880MF-1AE/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F25A LM3880MF-1AF/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F31A LM3880MFE-1AA/NOPB ACTIVE SOT-23 DBV 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F20A LM3880MFE-1AB/NOPB ACTIVE SOT-23 DBV 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F21A LM3880MFE-1AC/NOPB ACTIVE SOT-23 DBV 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F22A LM3880MFE-1AD/NOPB ACTIVE SOT-23 DBV 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F23A LM3880MFE-1AE/NOPB ACTIVE SOT-23 DBV 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F25A LM3880MFE-1AF/NOPB ACTIVE SOT-23 DBV 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F31A LM3880MFX-1AA/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F20A LM3880MFX-1AB/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F21A LM3880MFX-1AC/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F22A LM3880MFX-1AD/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F23A LM3880MFX-1AE/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F25A LM3880MFX-1AF/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 F31A The marketing status values are defined as follows: Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of