LM393LV, LM339LV
LM393LV,
LM339LV
SNOSDA4B – JUNE 2020 – REVISED
DECEMBER
2020
SNOSDA4B – JUNE 2020 – REVISED DECEMBER 2020
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LM393LV Dual and LM339LV Quad Low Voltage, Rail-to-Rail Comparators
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The LV device family consists of two (LM393LV), or
four (LM339LV), independent voltage comparators
that are designed to operate from a wide range of
supply voltages. The LV devices can drop-in replace
the standard LM2xx, LM3xx and LM290x comparator
family in low voltage (≤ 5 V) applications for improved
performance and added features.
1.65 V to 5.5 V Supply range
Rail-to-Rail input with Failsafe
Low input offset voltage 400 μV Typ
600ns Typ propagation delay
Low quiescent current 25 µA/Ch Typ
Low input bias current 5 pA Typ
Open-drain output
Full -40°C to +125°C temperature range
Power-On Reset (POR) for known start-up
2 kV ESD protection
Improved replacement for LM393 & LM339 family
for VCC ≤ 5 V.
The LV devices include a Power On Reset (POR)
feature that ensures the output is in a High-Z state
until the minimum supply voltage has been reached.
This prevents output transients during system powerup and power-down.
These comparators also feature Rail to Rail inputs
and no output phase inversion with inputs that can go
up to 6V without damage. This makes this family of
comparators well suited for precision voltage
monitoring in harsh, noisy environments.
2 Applications
•
•
•
•
•
•
•
•
•
•
Vacuum robot
Single phase UPS
Server PSU
Cordless power tool
Wireless Infrastructure
Applicances
Building Automation
Factory automation & control
Motor drives
Infotainment & cluster
The LV devices are specified for the temperature
range of -40°C to +125°C, which covers the
temperature ranges of all the LM2xx, LM3xx and
LM290x comparator families.
Device Information
PACKAGE (1)
PART NUMBER
LM393LV
(Dual)
LM339LV
(Quad)
(1)
BODY SIZE (NOM)
SOIC (8)
3.91 mm × 4.90 mm
TSSOP (8)
3.00 mm × 4.40 mm
VSSOP (8)
3.00 mm × 3.00 mm
WSON (8)
2.00 mm × 2.00 mm
SOT-23 (8)
1.60 mm × 2.90 mm
SOIC (14)
3.91 mm × 8.65 mm
TSSOP (14)
4.40 mm × 5.00 mm
SOT-23-THIN (14)
4.20 mm x 2.00 mm
WQFN (16)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
V+
IN+
+
IN-
SNAPBACK
ESD
CLAMPS
GND
V+
OUT
Output
Control
SUPPLY
CLAMP
GND
GND
GND
Bias
Power-On-Reset
GND
Block Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
5.1 Pin Functions: LM393LV............................................. 3
5.2 Pin Functions: LM339LV............................................. 4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information, LM393LV ..................................6
6.5 Thermal Information, LM339LV ..................................6
6.6 Electrical Characteristics, LM393LV .......................... 7
6.7 Switching Characteristics, LM393LV ..........................8
6.8 Electrical Characteristics, LM339LV .......................... 9
6.9 Switching Characteristics, LM339LV ........................10
6.10 Typical Characteristics............................................ 11
7 Detailed Description......................................................16
7.1 Overview................................................................... 16
7.2 Functional Block Diagram......................................... 16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................16
8 Application and Implementation.................................. 19
8.1 Application Information............................................. 19
8.2 Typical Applications.................................................. 22
9 Power Supply Recommendations................................30
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Example...................................................... 30
11 Device and Documentation Support..........................31
11.1 Related Documentation...........................................31
11.2 Receiving Notification of Documentation Updates.. 31
11.3 Support Resources................................................. 31
11.4 Trademarks............................................................. 31
11.5 Electrostatic Discharge Caution.............................. 31
11.6 Glossary.................................................................. 31
12 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2020) to Revision B (December 2020)
Page
• Updated LM339LV quad tables...........................................................................................................................5
Changes from Revision * (June 2020) to Revision A (September 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added LM339LV quad tables..............................................................................................................................5
• Added Typical Graphs.......................................................................................................................................11
2
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5 Pin Configuration and Functions
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
GND
4
5
IN2+
Figure 5-1. D, DGK, PW, DDF Packages
8-Pin SOIC, VSSOP, TSSOP, SOT-23-8
Top View
OUT1
1
IN1±
2
IN1+
3
GND
4
Exposed
Thermal
Die Pad
on
Underside
8
V+
7
OUT2
6
IN2±
5
IN2+
NOTE: Connect exposed thermal pad directly to GND pin.
Figure 5-2. DSG Package
8-Pad WSON With Exposed Thermal Pad
Top View
5.1 Pin Functions: LM393LV
PIN
NAME
NO.
I/O
DESCRIPTION
OUT1
1
O
Output pin of the comparator 1
IN1–
2
I
Inverting input pin of comparator 1
IN1+
3
I
Noninverting input pin of comparator 1
GND
4
—
IN2+
5
I
Negative supply
Noninverting input pin of comparator 2
IN2–
6
I
Inverting input pin of comparator 2
OUT2
7
O
Output pin of the comparator 2
V+
8
—
Positive supply
Thermal Pad
—
—
Connect directly to GND pin
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OUT2
1
14 OUT3
OUT1
2
13 OUT4
V+
3
12 GND
IN1±
4
11 IN4+
IN1+
5
10 IN4±
IN2±
6
9
IN3+
IN2+
7
8
IN3±
V+
1
IN1±
2
NC
3
IN1+
4
OUT1
OUT2
OUT3
OUT4
16
15
14
13
Figure 5-3. D, PW, DYY Package
14-Pin SOIC, TSSOP, SOT-23
Top View
12
GND
11
IN4+
Thermal
Pad
10
5
6
7
8
IN2±
IN2+
IN3±
IN3+
9
NC
IN4±
Not to scale
NOTE: Connect exposed thermal pad directly to GND pin.
Figure 5-4. RTE Package
16-Pad WQFN With Exposed Thermal Pad
Top View
5.2 Pin Functions: LM339LV
PIN
NAME(1)
DESCRIPTION
WQFN
OUT1
1
15
Output
Output pin of the comparator 1
OUT2
2
16
Output
Output pin of the comparator 2
V+
3
1
—
IN2–
4
2
Input
Negative input pin of the comparator 2
Positive supply
IN2+
5
4
Input
Positive input pin of the comparator 2
IN1–
6
5
Input
Negative input pin of the comparator 1
IN1+
7
6
Input
Positive input pin of the comparator 1
IN3–
8
7
Input
Negative input pin of the comparator 3
IN3+
9
8
Input
Positive input pin of the comparator 3
IN4–
10
9
Input
Negative input pin of the comparator 4
IN4+
11
11
Input
Positive input pin of the comparator 4
GND
12
12
—
OUT3
13
13
Output
Output pin of the comparator 4
OUT4
14
14
Output
Output pin of the comparator 3
NC
—
3
—
No Internal Connection - Leave floating or GND
NC
—
10
—
No Internal Connection - Leave floating or GND
Thermal Pad
—
PAD
—
Connect directly to GND pin
(1)
4
I/O
SOIC
Negative supply
Some manufacturers transpose the names of channels 1 & 2. Electrically the pinouts are identical, just a difference in channel naming
convention.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage: VS = (V+) – (GND)
–0.3
6
V
Input pins (IN+, IN–) from GND(2)
–0.3
6
V
Current into Input pins (IN+, IN–)
–10
10
mA
Output (OUT) from GND(3)
–0.3
6
V
Output short circuit
duration(4)
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
(4)
–65
10
s
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Input terminals are diode-clamped to GND pin. Input signals that can swing more than 0.3 V beyond the supply rails must be currentlimited to 10 mA or less. Additionally, Inputs (IN+, IN–) can be greater than V+ and OUT as long as it is within the –0.3 V to 6 V range
Output (OUT) can be greater than V+ and inputs (IN+, IN–) as long as it is within the –0.3 V to 6 V range
Short circuits from outputs to V+ can cause excessive heating and eventual destruction.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Supply voltage: VS = (V+) – (GND)
1.65
5.5
UNIT
Input voltage range (IN+, IN–) from (GND)
–0.1
5.6
V
Ambient temperature, TA
–40
125
°C
V
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6.4 Thermal Information, LM393LV
LM393LV
THERMAL METRIC (1)
D (SOIC)
8 PINS
PW
DGK
(TSSOP) (VSSOP)
8 PINS
8 PINS
DSG
(WSON)
DDF
(SOT-23)
8 PINS
8 PINS
UNIT
RqJA
Junction-to-ambient thermal resistance
167.7
221.7
–
175.2
–
°C/W
RqJC(top)
Junction-to-case (top) thermal resistance
107.0
109.1
–
178.1
–
°C/W
RqJB
Junction-to-board thermal resistance
111.2
152.5
–
139.5
–
°C/W
yJT
Junction-to-top characterization parameter
53.1
36.4
–
47.2
–
°C/W
yJB
Junction-to-board characterization parameter
110.4
150.7
–
138.9
–
°C/W
RqJC(bot)
Junction-to-case (bottom) thermal resistance
–
–
–
127.3
–
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information, LM339LV
LM339LV
THERMAL METRIC(1)
RTE
(WQFN)
DYY
(SOT-23)
UNIT
14 PINS
14 PINS
16 PINS
14 PINS
RqJA
Junction-to-ambient thermal resistance
136.0
155.0
134.1
–
°C/W
RqJC(top)
Junction-to-case (top) thermal resistance
91.2
82.0
122.6
–
°C/W
RqJB
Junction-to-board thermal resistance
92.0
98.5
109.3
–
°C/W
yJT
Junction-to-top characterization parameter
46.9
25.7
30.9
–
°C/W
yJB
Junction-to-board characterization parameter
91.6
97.6
108.3
–
°C/W
RqJC(bot)
Junction-to-case (bottom) thermal resistance
–
–
98.7
–
°C/W
(1)
6
PW
D (SOIC)
(TSSOP)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics, LM393LV
For VS (Total Supply Voltage) = (V+) – ( GND) = 5 V, VCM = ( GND) at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.4
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 1.8 V and 5 V
–2
VOS
Input offset voltage
VS = 1.8 V and 5 V, TA = –40°C to +125°C
–3
dVIO/dT
Input offset voltage drift
VS = 1.8 V and 5 V, TA = –40°C to +125°C
2
mV
3
mV
±1.5
µV/°C
POWER SUPPLY
IQ
Quiescent current per
comparator
VS = 1.8 V and 5 V, No Load, Output Low
IQ
Quiescent current per
comparator
VS = 1.8 V and 5 V, No Load, Output Low, TA =
–40°C to +125°C
PSRR
Power-supply rejection
ratio
VS = 1.8 V to 5 V, TA = –40°C to +125°C
25
35
µA
50
70
80
dB
INPUT BIAS CURRENT
IB
Input bias current
VCM = VS/2
5
pA
IOS
Input offset current
VCM = VS/2
1
pA
INPUT CAPACITANCE
CID
Input Capacitance,
Differential
VCM = VS/2
2
pF
CIC
Input Capacitance,
Common Mode
VCM = VS/2
3
pF
INPUT VOLTAGE RANGE
VCM-Range
Common-mode voltage
range
VS = 1.8 V and 5 V, TA = –40°C to +125°C
CMRR
Common-mode
rejection ratio
VS = 5 V, (GND) < VCM < (V+), TA = –40°C to
+125°C
60
65
dB
CMRR
Common-mode
rejection ratio
VS = 1.8 V, (GND) < VCM < (V+), TA = –40°C to
+125°C
50
60
dB
50
200
V/mV
(GND)
(V+)
V
OPEN-LOOP GAIN
AVD
Large signal differential
voltage amplification
OUTPUT
VOL
Voltage swing from
GND
ISINK = 4 mA, TA = 25°C
VOL
Voltage swing from
GND
ISINK = 4 mA, TA = –40°C to +125°C
ILKG
Open-drain output
leakage current
VPULLUP = (V+), TA = 25°C
ISC
Short-circuit current
VS = 5 V, Sinking
150
60
200
mV
300
mV
100
pA
100
mA
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6.7 Switching Characteristics, LM393LV
For VS (Total Supply Voltage) = (V+) – ( GND) = 5 V, VCM = VS / 2, CL = 15 pF at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
TPD-HL
Propagation delay time, highto-low
VID = –10 mV; Delay from mid-point of
input to mid-point of output (RP = 2.5 KΩ)
TPD-LH
Propagation delay time, low-to- VID = 10 mV; Delay from mid-point of input
high
to mid-point of output (RP = 2.5 KΩ)
TFALL
5V Output Fall Time, 80% to
20%
FTOGGLE
5V, Toggle Frequency
VID = –100 mV
VID = 100 mV (RP = 2.5 KΩ)
600
ns
600
ns
20
ns
1
MHz
50
µs
POWER ON TIME
PON
8
Power on-time
VS = 1.8 V and 5 V, VCM = (GND), VID = –
0.1 V, VPULL-UP = VS / 2, Delay from VS /
2 to VOUT = 0.1 x VS / 2 (RP = 2.5 KΩ)
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6.8 Electrical Characteristics, LM339LV
For VS (Total Supply Voltage) = (V+) – ( GND) = 5 V, VCM = ( GND) at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.4
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 1.8 V and 5 V
–2
VOS
Input offset voltage
VS = 1.8 V and 5 V, TA = –40°C to +125°C
–3
dVIO/dT
Input offset voltage drift
VS = 1.8 V and 5 V, TA = –40°C to +125°C
2
mV
3
mV
±1.5
µV/°C
POWER SUPPLY
IQ
Quiescent current per
comparator
VS = 1.8 V and 5 V, No Load, Output Low
IQ
Quiescent current per
comparator
VS = 1.8 V and 5 V, No Load, Output Low, TA =
–40°C to +125°C
PSRR
Power-supply rejection
ratio
VS = 1.8 V to 5 V, TA = –40°C to +125°C
25
35
µA
50
70
80
dB
INPUT BIAS CURRENT
IB
Input bias current
VCM = VS/2
5
pA
IOS
Input offset current
VCM = VS/2
1
pA
INPUT CAPACITANCE
CID
Input Capacitance,
Differential
VCM = VS/2
2
pF
CIC
Input Capacitance,
Common Mode
VCM = VS/2
3
pF
INPUT VOLTAGE RANGE
VCM-Range
Common-mode voltage
range
VS = 1.8 V and 5 V, TA = –40°C to +125°C
CMRR
Common-mode
rejection ratio
VS = 5 V, (GND) < VCM < (V+), TA = –40°C to
+125°C
60
65
dB
CMRR
Common-mode
rejection ratio
VS = 1.8 V, (GND) < VCM < (V+), TA = –40°C to
+125°C
50
60
dB
50
200
V/mV
(GND)
(V+)
V
OPEN-LOOP GAIN
AVD
Large signal differential
voltage amplification
OUTPUT
VOL
Voltage swing from
GND
ISINK = 4 mA, TA = 25°C
VOL
Voltage swing from
GND
ISINK = 4 mA, TA = –40°C to +125°C
ILKG
Open-drain output
leakage current
VPULLUP = (V+), TA = 25°C
ISC
Short-circuit current
VS = 5 V, Sinking
150
60
200
mV
300
mV
100
pA
100
mA
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6.9 Switching Characteristics, LM339LV
For VS (Total Supply Voltage) = (V+) – ( GND) = 5 V, VCM = VS / 2, CL = 15 pF at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
TPD-HL
Propagation delay time, highto-low
VID = –10 mV; Delay from mid-point of
input to mid-point of output (RP = 2.5 KΩ)
TPD-LH
Propagation delay time, low-to- VID = 10 mV; Delay from mid-point of input
high
to mid-point of output (RP = 2.5 KΩ)
TFALL
5V Output Fall Time, 80% to
20%
FTOGGLE
5V, Toggle Frequency
VID = –100 mV
VID = 100 mV (RP = 2.5 KΩ)
600
ns
600
ns
20
ns
1
MHz
50
µs
POWER ON TIME
PON
10
Power on-time
VS = 1.8 V and 5 V, VCM = (GND), VID = –
0.1 V, VPULL-UP = VS / 2, Delay from VS /
2 to VOUT = 0.1 x VS / 2 (RP = 2.5 KΩ)
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6.10 Typical Characteristics
40
38 No Load, Output High
36
34
32
30
28
26
24
22
20
18
16
14
12
10
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
36
125°C
85°C
25°C
-40°C
4.5
5
34
Supply Current Per Channel (PA)
Supply Current Per Channel (PA)
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
32
30
28
26
24
5V
3.3V
1.8V
22
20
-40
5.5
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
-0.2
125°C
85°C
25°C
-40°C
VS=1.8V
0
0.2
0.4
0.6 0.8 1 1.2
Input Voltage (V)
1.4
1.6
1.8
2
5
20 35 50 65
Temperature (°C)
80
95
110 125
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
-0.2
125°C
85°C
25°C
-40°C
VS=3.3V
0.2
0.6
1
1.4 1.8 2.2
Input Voltage (V)
2.6
3
3.4
Figure 6-4. Supply Current vs. Input Voltage, 3.3V
1000
125°C
85°C
25°C
-40°C
VS=5V
0
0.5
1
1.5
2 2.5 3 3.5
Input Voltage (V)
4
4.5
5
Figure 6-5. Supply Current vs. Input Voltage, 5V
5.5
Input Bias Current (pA)
Supply Current Per Channel (PA)
Figure 6-3. Supply Current vs. Input Voltage, 1.8V
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
-0.5
-10
Figure 6-2. Supply Current vs. Temperature
Supply Current Per Channel (PA)
Supply Current Per Channel (PA)
Figure 6-1. Supply Current vs. Supply Voltage
-25
100
10
1
0.1
VS = 5V
VIN = VS/2
0.01
0.002
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 6-6. Input Bias Current vs. Temperature
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6.10 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
10
1
100m
125°C
85°C
25°C
-40°C
10m
1m
100P
1m
10m
Output Sinking Current (A)
Output Voltage to GND (V)
Output Voltage to GND (V)
10
125°C
85°C
25°C
-40°C
10m
1m
100P
1m
10m
Output Sinking Current (A)
Sinking Short Circuit Current (mA)
Output Voltage to GND (V)
100m
100m
Figure 6-9. Output Sinking Current vs. Output Voltage, 5V
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-40
100m
5V
3.3V
1.8
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
1k
VS = 5V
VS = 5V
100
Falltime (ns)
Risetime (ns)
1m
10m
Output Sinking Current (A)
Figure 6-10. Sinking Short Circuit Current vs. Temperature
1k
10
125°C
85°C
25°C
-40°C
1
10p
100p
1n
Output Capacittive Load (F)
10n
Figure 6-11. Risetime vs. Capacitive Load
12
125°C
85°C
25°C
-40°C
10m
Figure 6-8. Output Sinking Current vs. Output Voltage, 3.3V
10
1
100m
1m
100P
100m
Figure 6-7. Output Sinking Current vs. Output Voltage, 1.8V
1
100
10
125°C
85°C
25°C
-40°C
1
10p
100p
1n
Output Capacittive Load (F)
10n
Figure 6-12. Falltime vs. Capacitive Load
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6.10 Typical Characteristics (continued)
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
VS = 1.8V
5 6 7 8 10
-40°C
25°C
85°C
125°C
20 30 4050 70 100
200 300 500
Input Overdrive (mV)
Propagation Delay, Low to High (ns)
Propagation Delay, High to Low (ns)
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
1000
5 6 7 8 10
125°C
85°C
25°C
-40°C
20 30 4050 70 100
200 300 500
Input Overdrive (mV)
5 6 7 8 10
Figure 6-17. Propagation Delay, High to Low, 5V
1000
-40°C
25°C
85°C
125°C
20 30 4050 70 100
200 300 500
Input Overdrive (mV)
1000
Figure 6-16. Propagation Delay, Low to High, 3.3V
-40°C
25°C
85°C
125°C
20 30 4050 70 100
200 300 500
Input Overdrive (mV)
20 30 4050 70 100
200 300 500
Input Overdrive (mV)
VS = 3.3V
5 6 7 8 10
1000
Propagation Delay, Low to High (ns)
Propagation Delay, High to Low (ns)
VS = 5V
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
1000
Figure 6-15. Propagation Delay, High to Low, 3.3V
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-40°C
25°C
85°C
125°C
Figure 6-14. Propagation Delay, Low to High, 1.8V
Propagation Delay, Low to High (ns)
Propagation Delay, High to Low (ns)
VS = 3.3V
VS = 1.8V
5 6 7 8 10
Figure 6-13. Propagation Delay, High to Low, 1.8V
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
VS = 5V
5 6 7 8 10
-40°C
25°C
85°C
125°C
20 30 4050 70 100
200 300 500
Input Overdrive (mV)
1000
Figure 6-18. Propagation Delay, Low to High, 5V
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6.10 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
2
2
TA = 125°C
1.6
1.2
Input Offset Voltage (mV)
Input Offset Voltage (mV)
1.6
0.8
0.4
0
-0.4
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
-1.6
-2
-0.2
0
0.2
0.4
0.6 0.8 1
1.2
Input Voltage (V)
1.4
1.6
1.8
0
-0.4
Unit 1
Unit 2
Unit 3
Unit 4
-0.8
-1.2
0
0.5
1
1.5
2 2.5 3 3.5
Input Voltage (V)
4
4.5
5
5.5
2
1.6
1.2
Input Offset Voltage (mV)
Input Offset Voltage (mV)
0.4
Figure 6-20. Offset Voltage vs. Input Votlage at 125°C, 5V
TA = 25°C
0.8
0.4
0
-0.4
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
-1.6
-2
-0.2
0
0.2
0.4
0.6 0.8 1
1.2
Input Voltage (V)
1.4
1.6
1.8
0.8
0.4
0
-0.4
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
0
0.5
1
1.5
2 2.5 3 3.5
Input Voltage (V)
4
4.5
5
5.5
Figure 6-22. Offset Voltage vs. Input Votlage at 25°C, 5V
2
TA = -40°C
1.6
Input Offset Voltage (mV)
1.2
0.8
0.4
0
-0.4
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
-1.6
-2
-0.2
1.2
-2
-0.5
2
2
1.6
TA = 25°C
-1.6
Figure 6-21. Offset Voltage vs. Input Votlage at 25°C, 1.8V
Input Offset Voltage (mV)
0.8
-2
-0.5
2
2
0
0.2
TA = -40°C
1.2
0.8
0.4
0
-0.4
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
-1.6
0.4
0.6 0.8 1
1.2
Input Voltage (V)
1.4
1.6
1.8
2
Figure 6-23. Offset Voltage vs. Input Votlage at -40°C, 1.8V
14
1.2
-1.6
Figure 6-19. Offset Voltage vs. Input Votlage at 125°C, 1.8V
1.6
TA = 125°C
-2
-0.5
0
0.5
1
1.5
2 2.5 3 3.5
Input Voltage (V)
4
4.5
5
5.5
Figure 6-24. Offset Voltage vs. Input Votlage at -40°C, 5V
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6.10 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RPULLUP = 2.5k, CL = 15 pF, VCM = GND, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless
otherwise noted.
2
2
TA = 125°C
Vin = V+
1.6
1.2
0.8
0.4
0
-0.4
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
-1.6
-2
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
Input Offset Voltage (mV)
Input Offset Voltage (mV)
1.6
0.4
0
-0.4
-0.8
-1.2
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
Unit 1
Unit 2
Unit 3
Unit 4
TA = -40°C
Vin = GND
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
-2
1.5
5.5
Figure 6-27. Offset Voltage vs. Supply Voltage at 25°C, VIN=V+
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
Figure 6-28. Offset Voltage vs. Supply Voltage at 25°C, VIN=0V
2
2
TA = -40°C
Vin = V+
1.6
1.2
0.8
0.4
0
-0.4
-0.8
Unit 1
Unit 2
Unit 3
Unit 4
-1.2
-1.6
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
Figure 6-29. Offset Voltage vs. Supply Voltage at -40°C, VIN=V+
Input Offset Voltage (mV)
Input Offset Voltage (mV)
-0.8
1.6
-1.6
-2
1.5
0
-0.4
Figure 6-26. Offset Voltage vs. Supply Voltage at 125°C, VIN=0V
Input Offset Voltage (mV)
Input Offset Voltage (mV)
0.8
1.6
0.4
2
Unit 1
Unit 2
Unit 3
Unit 4
TA = 25°C
Vin = V+
1.2
-2
1.5
0.8
-2
1.5
2
1.6
1.2
-1.6
5.5
Figure 6-25. Offset Voltage vs. Supply Voltage at 125°C, VIN=V+
TA = 125°C
Vin = GND
Unit 1
Unit 2
Unit 3
Unit 4
TA = -40°C
Vin = GND
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
-1.6
-2
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
Figure 6-30. Offset Voltage vs. Supply Voltage at -40°C, VIN=0V
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7 Detailed Description
7.1 Overview
The LV Family devices are micro-power comparators with open-drain outputs and improved input offset voltage
that operate down to 1.65 V while only consuming only 25 µA per channel. The LV family are ideally suited for
portable, automotive and industrial applications. An internal power-on reset circuit ensures that the output
remains in a known state during power-up and power-down while fail-safe inputs can tolerate input transients
without damage or false outputs.
7.2 Functional Block Diagram
V+
IN+
+
IN-
-
V+
Output
Control
SNAPBACK
ESD
CLAMPS
GND
OUT
GND
GND
GND
Power-On-Reset
(POR)
Bias
GND
7.3 Feature Description
The LV family devices are micro-power comparators that have low input offset voltages and are capable of
operating at low voltages. The LV family feature a rail-to-rail input stage capable of operating up to 100 mV
beyond the power supply rails. The comparators also feature an open-drain output stage options with Power On
Reset for known start-up conditions.
7.4 Device Functional Modes
7.4.1 Open Drain Output
The LV family features an open-drain (also commonly called open collector) sinking-only output stage enabling
the output logic levels to be pulled up to an external voltage from 0 V up to 5.5 V, independent of the comparator
supply voltage (V+). The open-drain output also allows logical OR'ing of multiple open drain outputs and logic
level translation. TI recommends setting the pull-up resistor current to between 100uA and 1mA. Lower pull-up
resistor values will help increase the rising edge risetime, but at the expense of increasing VOL and higher power
dissipation. The risetime will be dependant on the time constant of the total pull-up resistance and total load
capacitance. Large value pull-up resistors (>1 MΩ) will create an exponential rising edge due to the RC time
constant and increase the risetime.
Unused open drain outputs should be left floating, or can be tied to the GND pin if floating pins are not allowed.
While an individual output can typically sink up to 100 mA, the total combined current for all channels must be
less than 200 mA.
7.4.2 Power-On Reset (POR)
The LV family has an internal Power-on-Reset (POR) circuit for known start-up or power-down conditions. While
the power supply (V+) is ramping up or ramping down, the POR circuitry will be activated for up to 30µs after the
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minimum supply voltage threshold of 1.5V is crossed, or immediately when the supply voltage drops below 1.5V.
When the supply voltage is equal to or greater than the minimum supply voltage, and after the delay period, the
comparator output reflects the state of the differential input (VID).
The POR circuit will keep the output high impedance (HI-Z) during the POR period (ton).
tON
GND
VCC
GND + 1.5V
VOH/2
GND
OUT
Figure 7-1. Power-On Reset Timing Diagram
Note that it is the nature of an open collector output that the output will rise with the pull-up voltage during the
POR period.
A light pull-up (to V+) or pull-down (to GND) resistor can be used to pre-bias the output condition to prevent the
output from floating.
7.4.3 Inputs
7.4.3.1 Rail to Rail Input
The LV family input voltage range extends from 100mV below GND to 100 mV above V+. The differential input
voltage (VID) can be any voltage within these limits. No phase-inversion of the comparator output will occur when
the input pins exceed V+ or GND.
7.4.3.2 Fault Tolerant Inputs
The LV family inputs are fault tolerant up to 5.5V independent of V+. Fault tolerant is defined as maintaining the
same high input impedance when V+ is unpowered or within the recommended operating ranges.
The fault tolerant inputs can be any value between 0 V and 5.5 V, even while V+ is zero or ramping up or down.
This feature avoids power sequencing issues as long as the input voltage range and supply voltage are within
the specified ranges. This is possible since the inputs are not clamped to V+ and the input current maintains its
value even when a higher voltage is applied to the inputs.
As long as one of the input pins remains within the valid input range, and the supply voltage is valid and not in
POR, the output state will be correct.
The following is a summary of input voltage excursions and their outcomes:
1. When both IN- and IN+ are within the specified input voltage range:
a. If IN- is higher than IN+ and the offset voltage, the output is low.
b. If IN- is lower than IN+ and the offset voltage, the output is high.
2. When IN- is outside the specified input voltage range and IN+ is within the specified voltage range, the output
is low.
3. When IN+ is higher than the specified input voltage range and IN- is within the specified input voltage range,
the output is high
4. When IN- and IN+ are both outside the specified input voltage range, the output is indeterminate (random).
Do not operate in this region.
Even with the fault tolerant feature, TI strongly recommends keeping the inputs within the specified input voltage
range during normal system operation to maintain datasheet specifications. Operating outside the specified input
range can cause changes in specifications such as propagation delay, which can lead to unpredictable behavior.
7.4.3.3 Input Protection
The input bias current is typically 5 pA for input voltages between V+ and GND. The comparator inputs are
protected from reverse voltage by the internal ESD diodes connected to GND. As the input voltage goes under
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GND, or above the input Absolute Maximum ratings the protection diodes become forward biased and begin to
conduct causing the input bias current to increase exponentially. Input bias current typically doubles for each
10°C temperature increase.
If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line,
TI recommends adding a current-limiting resistor in series with the input to limit any transient currents should the
clamps conduct. The current should be limited 10 mA or less. This series resistance can be part of any resistive
input dividers or networks.
7.4.4 ESD Protection
The LV family incorporates internal ESD protection circuits on all pins. The inputs, and the open-drain output,
use a proprietary "snapback" type ESD clamp from each pin to GND, which allows the pins to exceed the supply
voltage (V+). While shown as Zener diodes, snapbacks momentarily "short" and go low impedance (like an
SCR) when the threshold is exceeded, as opposed to clamping to a defined voltage like a Zener. There is no
ESD clamp from the inputs to V+.
The open-drain output protection also consists of a ESD clamp between the output and GND to allow the output
to be pulled above V+ to a maximum of 5.5V. There is no ESD clamp from the output to V+.
If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line,
TI recommends adding a current-limiting resistor in series with the input to limit any transient currents should the
clamps conduct. The current should be limited 10 mA or less. This series resistance can be part of any resistive
input dividers or networks.
TI does not specify the performance of the ESD clamps and external clamping diodes should be added if the
inputs or output could exceed the maximum ratings as part of normal operation.
7.4.5 Unused Inputs
If a channel is not to be used, DO NOT tie the inputs together. Due to the high equivalent bandwidth and low
offset voltage, tying the inputs directly together can cause high frequency oscillations as the device triggers on
it's own internal wideband noise. Instead, the inputs should be tied to any available voltage that resides within
the specified input voltage range and provides a minimum of 50mV differential voltage. For example, one input
can be grounded and the other input connected to a reference voltage, or even V+ (as long as the input is
directly connected to the V+ pin to avoid transients).
7.4.6 Hysteresis
The LV family does not have internal hysteresis. Due to the wide effective bandwidth and low input offset
voltage, it is possible for the output to "chatter" (oscillate) when the absolute differential voltage near zero, as the
comparator triggers on it's own internal wideband noise. TI recommends that the user add external hysteresis if
slow moving signals are expected. See Section 8.1.2 in the following section.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Basic Comparator Definitions
8.1.1.1 Operation
The basic comparator compares the input voltage (V IN) on one input to a reference voltage (V REF) on the other
input. In the Figure 8-1 example below, if VIN is less than VREF, the output voltage (V O) is logic low (V OL). If VIN is
greater than V REF, the output voltage (V O) is at logic high (V OH). Table 8-1 summarizes the output conditions.
The output logic can be inverted by simply swapping the input pins.
Table 8-1. Output Conditions
Inputs Condition
Output
IN+ > IN-
HIGH (VOH)
IN+ = IN-
Indeterminate (chatters - see Hysteresis)
IN+ < IN-
LOW (VOL)
8.1.1.2 Propagation Delay
There is a delay between from when the input crosses the reference voltage and the output responds. This is
called the Propagation Delay. Propagation delay can be different between high-to low and low-to-high input
transitions. This is shown as t pLH and t pHL in Figure 8-1 and is measured from the mid-point of the input to the
midpoint of the output.
VREF + 200mV
V+
Input
VIN
VOD (+200mV)
VREF + 100mV
+
Output
±
VIN
VREF
VREF
+
GND
±
VREF 5 100mV
VOD (-200mV)
VREF - 200mV
tpLH
tpHL
VOH
80%
Output
80%
50%
50%
20%
VOL
20%
tR
tF
Figure 8-1. Comparator Timing Diagram
8.1.1.3 Overdrive Voltage
The overdrive voltage, V OD, is the amount of input voltage beyond the reference voltage (and not the total input
peak-to-peak voltage). The overdrive voltage is 100mV as shown in the Figure 8-1 example. The overdrive
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voltage can influence the propagation delay (t p). The smaller the overdrive voltage, the longer the propagation
delay, particularly when
