LM3S1F11-IBZ80-A2

厂商：
BURR-BROWN(德州仪器)
封装：
LFBGA108
描述：
IC MCU 32BIT 384KB FLASH 108BGA

数据手册：

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LM3S1F11-IBZ80-A2 数据手册

TE X AS I NS TRUM E NTS - P RO DUCTION D ATA ® Stellaris LM3S1F11 Microcontroller D ATA SHE E T D S -LM 3S 1F 11 - 9 9 7 0 C opyri ght © 200 7-2011 Texas Instruments Incorporated Copyright Copyright © 2007-2011 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare® are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm 2 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table of Contents Revision History ............................................................................................................................. 28 About This Document .................................................................................................................... 29 Audience .............................................................................................................................................. About This Manual ................................................................................................................................ Related Documents ............................................................................................................................... Documentation Conventions .................................................................................................................. 29 29 29 30 1 Architectural Overview .......................................................................................... 32 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 1.2 1.3 1.4 Functional Overview ...................................................................................................... ARM Cortex-M3 ............................................................................................................ On-Chip Memory ........................................................................................................... External Peripheral Interface ......................................................................................... Serial Communications Peripherals ................................................................................ System Integration ........................................................................................................ Analog .......................................................................................................................... JTAG and ARM Serial Wire Debug ................................................................................ Packaging and Temperature .......................................................................................... Target Applications ........................................................................................................ High-Level Block Diagram ............................................................................................. Hardware Details .......................................................................................................... 34 34 36 37 38 41 47 48 49 49 50 52 2 The Cortex-M3 Processor ...................................................................................... 53 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.5 2.5.1 2.5.2 2.5.3 Block Diagram .............................................................................................................. 54 Overview ...................................................................................................................... 55 System-Level Interface .................................................................................................. 55 Integrated Configurable Debug ...................................................................................... 55 Trace Port Interface Unit (TPIU) ..................................................................................... 56 Cortex-M3 System Component Details ........................................................................... 56 Programming Model ...................................................................................................... 57 Processor Mode and Privilege Levels for Software Execution ........................................... 57 Stacks .......................................................................................................................... 57 Register Map ................................................................................................................ 58 Register Descriptions .................................................................................................... 59 Exceptions and Interrupts .............................................................................................. 72 Data Types ................................................................................................................... 72 Memory Model .............................................................................................................. 72 Memory Regions, Types and Attributes ........................................................................... 74 Memory System Ordering of Memory Accesses .............................................................. 74 Behavior of Memory Accesses ....................................................................................... 75 Software Ordering of Memory Accesses ......................................................................... 75 Bit-Banding ................................................................................................................... 77 Data Storage ................................................................................................................ 79 Synchronization Primitives ............................................................................................. 79 Exception Model ........................................................................................................... 80 Exception States ........................................................................................................... 81 Exception Types ............................................................................................................ 81 Exception Handlers ....................................................................................................... 84 July 24, 2011 3 Texas Instruments-Production Data Table of Contents 2.5.4 2.5.5 2.5.6 2.5.7 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.7.1 2.7.2 2.8 Vector Table .................................................................................................................. 84 Exception Priorities ....................................................................................................... 85 Interrupt Priority Grouping .............................................................................................. 86 Exception Entry and Return ........................................................................................... 86 Fault Handling .............................................................................................................. 88 Fault Types ................................................................................................................... 89 Fault Escalation and Hard Faults .................................................................................... 89 Fault Status Registers and Fault Address Registers ........................................................ 90 Lockup ......................................................................................................................... 90 Power Management ...................................................................................................... 90 Entering Sleep Modes ................................................................................................... 91 Wake Up from Sleep Mode ............................................................................................ 91 Instruction Set Summary ............................................................................................... 92 3 Cortex-M3 Peripherals ........................................................................................... 96 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.3 3.4 3.5 3.6 Functional Description ................................................................................................... 96 System Timer (SysTick) ................................................................................................. 96 Nested Vectored Interrupt Controller (NVIC) .................................................................... 97 System Control Block (SCB) .......................................................................................... 99 Memory Protection Unit (MPU) ....................................................................................... 99 Register Map .............................................................................................................. 104 System Timer (SysTick) Register Descriptions .............................................................. 106 NVIC Register Descriptions .......................................................................................... 110 System Control Block (SCB) Register Descriptions ........................................................ 123 Memory Protection Unit (MPU) Register Descriptions .................................................... 152 4 JTAG Interface ...................................................................................................... 162 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.5 4.5.1 4.5.2 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. JTAG Interface Pins ..................................................................................................... JTAG TAP Controller ................................................................................................... Shift Registers ............................................................................................................ Operational Considerations .......................................................................................... Initialization and Configuration ..................................................................................... Register Descriptions .................................................................................................. Instruction Register (IR) ............................................................................................... Data Registers ............................................................................................................ 163 163 164 164 166 166 167 169 170 170 172 5 System Control ..................................................................................................... 174 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 5.4 5.5 Signal Description ....................................................................................................... Functional Description ................................................................................................. Device Identification .................................................................................................... Reset Control .............................................................................................................. Non-Maskable Interrupt ............................................................................................... Power Control ............................................................................................................. Clock Control .............................................................................................................. System Control ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 4 174 174 175 175 180 180 181 188 190 190 192 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 6 Hibernation Module .............................................................................................. 268 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.5 6.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Register Access Timing ............................................................................................... Hibernation Clock Source ............................................................................................ Battery Management ................................................................................................... Real-Time Clock .......................................................................................................... Non-Volatile Memory ................................................................................................... Power Control Using HIB ............................................................................................. Power Control Using VDD3ON Mode ........................................................................... Initiating Hibernate ...................................................................................................... Interrupts and Status ................................................................................................... Initialization and Configuration ..................................................................................... Initialization ................................................................................................................. RTC Match Functionality (No Hibernation) .................................................................... RTC Match/Wake-Up from Hibernation ......................................................................... External Wake-Up from Hibernation .............................................................................. RTC or External Wake-Up from Hibernation .................................................................. Register Reset ............................................................................................................ Register Map .............................................................................................................. Register Descriptions .................................................................................................. 269 269 270 270 271 273 273 273 274 274 274 274 275 275 276 276 276 277 277 277 278 7 Internal Memory ................................................................................................... 295 7.1 7.2 7.2.1 7.2.2 7.2.3 7.3 7.4 7.5 Block Diagram ............................................................................................................ 295 Functional Description ................................................................................................. 295 SRAM ........................................................................................................................ 296 ROM .......................................................................................................................... 296 Flash Memory ............................................................................................................. 298 Register Map .............................................................................................................. 303 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 304 Memory Register Descriptions (System Control Offset) .................................................. 316 8 Micro Direct Memory Access (μDMA) ................................................................ 340 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.3 8.3.1 8.3.2 8.3.3 Block Diagram ............................................................................................................ 341 Functional Description ................................................................................................. 341 Channel Assignments .................................................................................................. 342 Priority ........................................................................................................................ 343 Arbitration Size ............................................................................................................ 343 Request Types ............................................................................................................ 343 Channel Configuration ................................................................................................. 344 Transfer Modes ........................................................................................................... 346 Transfer Size and Increment ........................................................................................ 354 Peripheral Interface ..................................................................................................... 354 Software Request ........................................................................................................ 354 Interrupts and Errors .................................................................................................... 355 Initialization and Configuration ..................................................................................... 355 Module Initialization ..................................................................................................... 355 Configuring a Memory-to-Memory Transfer ................................................................... 356 Configuring a Peripheral for Simple Transmit ................................................................ 357 July 24, 2011 5 Texas Instruments-Production Data Table of Contents 8.3.4 8.3.5 8.4 8.5 8.6 Configuring a Peripheral for Ping-Pong Receive ............................................................ Configuring Channel Assignments ................................................................................ Register Map .............................................................................................................. μDMA Channel Control Structure ................................................................................. μDMA Register Descriptions ........................................................................................ 359 361 361 363 370 9 General-Purpose Input/Outputs (GPIOs) ........................................................... 400 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.3 9.4 9.5 Signal Description ....................................................................................................... 400 Functional Description ................................................................................................. 405 Data Control ............................................................................................................... 406 Interrupt Control .......................................................................................................... 407 Mode Control .............................................................................................................. 408 Commit Control ........................................................................................................... 408 Pad Control ................................................................................................................. 409 Identification ............................................................................................................... 409 Initialization and Configuration ..................................................................................... 409 Register Map .............................................................................................................. 410 Register Descriptions .................................................................................................. 413 10 External Peripheral Interface (EPI) ..................................................................... 456 10.1 10.2 10.3 10.3.1 10.3.2 10.4 10.4.1 10.4.2 10.4.3 10.5 10.6 EPI Block Diagram ...................................................................................................... Signal Description ....................................................................................................... Functional Description ................................................................................................. Non-Blocking Reads .................................................................................................... DMA Operation ........................................................................................................... Initialization and Configuration ..................................................................................... SDRAM Mode ............................................................................................................. Host Bus Mode ........................................................................................................... General-Purpose Mode ............................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 457 458 460 461 462 462 463 467 478 486 487 11 General-Purpose Timers ...................................................................................... 531 11.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. GPTM Reset Conditions .............................................................................................. Timer Modes ............................................................................................................... DMA Operation ........................................................................................................... Accessing Concatenated Register Values ..................................................................... Initialization and Configuration ..................................................................................... One-Shot/Periodic Timer Mode .................................................................................... Real-Time Clock (RTC) Mode ...................................................................................... Input Edge-Count Mode ............................................................................................... Input Edge Timing Mode .............................................................................................. PWM Mode ................................................................................................................. Register Map .............................................................................................................. Register Descriptions .................................................................................................. 531 532 535 536 536 541 542 542 542 543 543 544 544 545 546 12 Watchdog Timers ................................................................................................. 577 12.1 Block Diagram ............................................................................................................ 578 6 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 12.2 12.2.1 12.3 12.4 12.5 Functional Description ................................................................................................. Register Access Timing ............................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 578 579 579 579 580 13 Analog-to-Digital Converter (ADC) ..................................................................... 602 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.4 13.4.1 13.4.2 13.5 13.6 Block Diagram ............................................................................................................ 603 Signal Description ....................................................................................................... 603 Functional Description ................................................................................................. 604 Sample Sequencers .................................................................................................... 604 Module Control ............................................................................................................ 605 Hardware Sample Averaging Circuit ............................................................................. 607 Analog-to-Digital Converter .......................................................................................... 608 Differential Sampling ................................................................................................... 611 Internal Temperature Sensor ........................................................................................ 613 Digital Comparator Unit ............................................................................................... 614 Initialization and Configuration ..................................................................................... 618 Module Initialization ..................................................................................................... 618 Sample Sequencer Configuration ................................................................................. 619 Register Map .............................................................................................................. 619 Register Descriptions .................................................................................................. 621 14 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 677 14.1 Block Diagram ............................................................................................................ 14.2 Signal Description ....................................................................................................... 14.3 Functional Description ................................................................................................. 14.3.1 Transmit/Receive Logic ............................................................................................... 14.3.2 Baud-Rate Generation ................................................................................................. 14.3.3 Data Transmission ...................................................................................................... 14.3.4 Serial IR (SIR) ............................................................................................................. 14.3.5 ISO 7816 Support ....................................................................................................... 14.3.6 Modem Handshake Support ......................................................................................... 14.3.7 LIN Support ................................................................................................................ 14.3.8 FIFO Operation ........................................................................................................... 14.3.9 Interrupts .................................................................................................................... 14.3.10 Loopback Operation .................................................................................................... 14.3.11 DMA Operation ........................................................................................................... 14.4 Initialization and Configuration ..................................................................................... 14.5 Register Map .............................................................................................................. 14.6 Register Descriptions .................................................................................................. 678 678 680 680 681 682 682 683 683 685 686 686 687 687 688 689 690 15 Synchronous Serial Interface (SSI) .................................................................... 738 15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Bit Rate Generation ..................................................................................................... FIFO Operation ........................................................................................................... Interrupts .................................................................................................................... Frame Formats ........................................................................................................... DMA Operation ........................................................................................................... July 24, 2011 739 739 740 741 741 741 742 749 7 Texas Instruments-Production Data Table of Contents 15.4 15.5 15.6 Initialization and Configuration ..................................................................................... 750 Register Map .............................................................................................................. 751 Register Descriptions .................................................................................................. 752 16 Inter-Integrated Circuit (I2C) Interface ................................................................ 780 16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.4 16.5 16.6 16.7 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. I2C Bus Functional Overview ........................................................................................ Available Speed Modes ............................................................................................... Interrupts .................................................................................................................... Loopback Operation .................................................................................................... Command Sequence Flow Charts ................................................................................ Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions (I2C Master) ............................................................................... Register Descriptions (I2C Slave) ................................................................................. 781 781 782 782 784 785 786 787 794 795 796 808 17 Analog Comparators ............................................................................................ 817 17.1 17.2 17.3 17.3.1 17.4 17.5 17.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Internal Reference Programming .................................................................................. Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 18 Pin Diagram .......................................................................................................... 830 817 818 819 819 821 821 822 19 Signal Tables ........................................................................................................ 832 19.1 19.2 19.3 100-Pin LQFP Package Pin Tables ............................................................................... 833 108-Ball BGA Package Pin Tables ................................................................................ 858 Connections for Unused Signals ................................................................................... 884 20 Operating Characteristics ................................................................................... 886 21 Electrical Characteristics .................................................................................... 887 21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.8.1 21.8.2 21.8.3 21.8.4 21.8.5 21.8.6 21.9 21.10 Maximum Ratings ....................................................................................................... 887 Recommended Operating Conditions ........................................................................... 887 Load Conditions .......................................................................................................... 888 JTAG and Boundary Scan ............................................................................................ 888 Power and Brown-out .................................................................................................. 890 Reset ......................................................................................................................... 891 On-Chip Low Drop-Out (LDO) Regulator ....................................................................... 892 Clocks ........................................................................................................................ 892 PLL Specifications ....................................................................................................... 892 PIOSC Specifications .................................................................................................. 893 Internal 30-kHz Oscillator Specifications ....................................................................... 893 Hibernation Clock Source Specifications ....................................................................... 893 Main Oscillator Specifications ....................................................................................... 894 System Clock Specification with ADC Operation ............................................................ 895 Sleep Modes ............................................................................................................... 895 Hibernation Module ..................................................................................................... 895 8 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 21.11 Flash Memory ............................................................................................................ 21.12 GPIO Module .............................................................................................................. 21.13 External Peripheral Interface (EPI) ............................................................................... 21.14 Analog-to-Digital Converter (ADC) ................................................................................ 21.15 Synchronous Serial Interface (SSI) ............................................................................... 21.16 Inter-Integrated Circuit (I2C) Interface ........................................................................... 21.17 Ethernet Controller ...................................................................................................... 21.18 Analog Comparator ..................................................................................................... 21.19 Current Consumption .................................................................................................. 21.19.1 Nominal Power Consumption ....................................................................................... 21.19.2 Maximum Current Consumption ................................................................................... A 897 897 897 903 904 906 907 908 909 909 910 Register Quick Reference ................................................................................... 912 B Ordering and Contact Information ..................................................................... 939 B.1 B.2 B.3 B.4 Ordering Information .................................................................................................... 939 Part Markings .............................................................................................................. 939 Kits ............................................................................................................................. 940 Support Information ..................................................................................................... 940 C Package Information ............................................................................................ 941 C.1 C.1.1 C.1.2 C.1.3 C.2 C.2.1 C.2.2 C.2.3 100-Pin LQFP Package ............................................................................................... Package Dimensions ................................................................................................... Tray Dimensions ......................................................................................................... Tape and Reel Dimensions .......................................................................................... 108-Ball BGA Package ................................................................................................ Package Dimensions ................................................................................................... Tray Dimensions ......................................................................................................... Tape and Reel Dimensions .......................................................................................... July 24, 2011 941 941 943 943 945 945 947 948 9 Texas Instruments-Production Data Table of Contents List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 6-2. Figure 6-3. Stellaris LM3S1F11 Microcontroller High-Level Block Diagram .............................. 51 CPU Block Diagram ............................................................................................. 55 TPIU Block Diagram ............................................................................................ 56 Cortex-M3 Register Set ........................................................................................ 58 Bit-Band Mapping ................................................................................................ 78 Data Storage ....................................................................................................... 79 Vector Table ........................................................................................................ 85 Exception Stack Frame ........................................................................................ 87 SRD Use Example ............................................................................................. 102 JTAG Module Block Diagram .............................................................................. 163 Test Access Port State Machine ......................................................................... 166 IDCODE Register Format ................................................................................... 172 BYPASS Register Format ................................................................................... 172 Boundary Scan Register Format ......................................................................... 173 Basic RST Configuration .................................................................................... 177 External Circuitry to Extend Power-On Reset ....................................................... 177 Reset Circuit Controlled by Switch ...................................................................... 178 Power Architecture ............................................................................................ 181 Main Clock Tree ................................................................................................ 184 Hibernation Module Block Diagram ..................................................................... 269 Using a Crystal as the Hibernation Clock Source ................................................. 272 Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode ................................................................................................................ 272 Figure 7-1. Internal Memory Block Diagram .......................................................................... 295 Figure 8-1. μDMA Block Diagram ......................................................................................... 341 Figure 8-2. Example of Ping-Pong μDMA Transaction ........................................................... 347 Figure 8-3. Memory Scatter-Gather, Setup and Configuration ................................................ 349 Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 350 Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 352 Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 353 Figure 9-1. Digital I/O Pads ................................................................................................. 405 Figure 9-2. Analog/Digital I/O Pads ...................................................................................... 406 Figure 9-3. GPIODATA Write Example ................................................................................. 407 Figure 9-4. GPIODATA Read Example ................................................................................. 407 Figure 10-1. EPI Block Diagram ............................................................................................. 458 Figure 10-2. SDRAM Non-Blocking Read Cycle ...................................................................... 465 Figure 10-3. SDRAM Normal Read Cycle ............................................................................... 466 Figure 10-4. SDRAM Write Cycle ........................................................................................... 467 Figure 10-5. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 473 Figure 10-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 475 Figure 10-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 476 Figure 10-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH = 0, RDHIGH = 0 ............................................................................................... 476 Figure 10-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual CSn .................................................................................................................. 477 Figure 10-10. Continuous Read Mode Accesses ...................................................................... 477 10 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 10-11. Figure 10-12. Figure 10-13. Figure 10-14. Figure 10-15. Figure 10-16. Figure 10-17. Figure 10-18. Figure 10-19. Figure 10-20. Figure 10-21. Figure 10-22. Figure 10-23. Figure 10-24. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure 11-5. Figure 12-1. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Figure 13-12. Figure 13-13. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 15-5. Figure 15-6. Figure 15-7. Figure 15-8. Figure 15-9. Write Followed by Read to External FIFO ............................................................ 478 Two-Entry FIFO ................................................................................................. 478 Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 482 Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1, WRCYC=1 ........................................................................................................ 482 Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 483 FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 483 FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 483 FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 484 FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 484 FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 484 FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 484 iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 485 EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 485 EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 486 GPTM Module Block Diagram ............................................................................ 532 Timer Daisy Chain ............................................................................................. 538 Input Edge-Count Mode Example ....................................................................... 539 16-Bit Input Edge-Time Mode Example ............................................................... 540 16-Bit PWM Mode Example ................................................................................ 541 WDT Module Block Diagram .............................................................................. 578 ADC Module Block Diagram ............................................................................... 603 ADC Sample Phases ......................................................................................... 607 Sample Averaging Example ............................................................................... 607 Internal Voltage Conversion Result ..................................................................... 609 External Voltage Conversion Result with 3.0-V Setting ......................................... 610 External Voltage Conversion Result with 1.0-V Setting ......................................... 610 Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 612 Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 612 Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 613 Internal Temperature Sensor Characteristic ......................................................... 614 Low-Band Operation (CIC=0x0) .......................................................................... 616 Mid-Band Operation (CIC=0x1) .......................................................................... 617 High-Band Operation (CIC=0x3) ......................................................................... 618 UART Module Block Diagram ............................................................................. 678 UART Character Frame ..................................................................................... 681 IrDA Data Modulation ......................................................................................... 683 LIN Message ..................................................................................................... 685 LIN Synchronization Field ................................................................................... 686 SSI Module Block Diagram ................................................................................. 739 TI Synchronous Serial Frame Format (Single Transfer) ........................................ 743 TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 743 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 744 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 744 Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 745 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 746 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 746 Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 747 July 24, 2011 11 Texas Instruments-Production Data Table of Contents Figure 15-10. Figure 15-11. Figure 15-12. Figure 16-1. Figure 16-2. Figure 16-3. Figure 16-4. Figure 16-5. Figure 16-6. Figure 16-7. Figure 16-8. Figure 16-9. Figure 16-10. Figure 16-11. Figure 16-12. Figure 16-13. Figure 17-1. Figure 17-2. Figure 17-3. Figure 18-1. Figure 18-2. Figure 21-1. Figure 21-2. Figure 21-3. Figure 21-4. Figure 21-5. Figure 21-6. Figure 21-7. Figure 21-8. Figure 21-9. Figure 21-10. Figure 21-11. Figure 21-12. Figure 21-13. Figure 21-14. Figure 21-15. Figure 21-16. Figure 21-17. Figure 21-18. Figure 21-19. Figure 21-20. Figure 21-21. Figure 21-22. Figure 21-23. Figure 21-24. MICROWIRE Frame Format (Single Frame) ........................................................ 748 MICROWIRE Frame Format (Continuous Transfer) ............................................. 749 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 749 I2C Block Diagram ............................................................................................. 781 I2C Bus Configuration ........................................................................................ 782 START and STOP Conditions ............................................................................. 783 Complete Data Transfer with a 7-Bit Address ....................................................... 783 R/S Bit in First Byte ............................................................................................ 784 Data Validity During Bit Transfer on the I2C Bus ................................................... 784 Master Single TRANSMIT .................................................................................. 788 Master Single RECEIVE ..................................................................................... 789 Master TRANSMIT with Repeated START ........................................................... 790 Master RECEIVE with Repeated START ............................................................. 791 Master RECEIVE with Repeated START after TRANSMIT with Repeated START .............................................................................................................. 792 Master TRANSMIT with Repeated START after RECEIVE with Repeated START .............................................................................................................. 793 Slave Command Sequence ................................................................................ 794 Analog Comparator Module Block Diagram ......................................................... 817 Structure of Comparator Unit .............................................................................. 819 Comparator Internal Reference Structure ............................................................ 820 100-Pin LQFP Package Pin Diagram .................................................................. 830 108-Ball BGA Package Pin Diagram (Top View) ................................................... 831 Load Conditions ................................................................................................ 888 JTAG Test Clock Input Timing ............................................................................. 889 JTAG Test Access Port (TAP) Timing .................................................................. 889 Power-On Reset Timing ..................................................................................... 890 Brown-Out Reset Timing .................................................................................... 890 Power-On Reset and Voltage Parameters ........................................................... 891 External Reset Timing (RST) .............................................................................. 891 Software Reset Timing ....................................................................................... 891 Watchdog Reset Timing ..................................................................................... 892 MOSC Failure Reset Timing ............................................................................... 892 Hibernation Module Timing with Internal Oscillator Running in Hibernation ............ 896 Hibernation Module Timing with Internal Oscillator Stopped in Hibernation ............ 896 SDRAM Initialization and Load Mode Register Timing .......................................... 898 SDRAM Read Timing ......................................................................................... 899 SDRAM Write Timing ......................................................................................... 899 Host-Bus 8/16 Mode Read Timing ...................................................................... 900 Host-Bus 8/16 Mode Write Timing ....................................................................... 900 Host-Bus 8/16 Mode Muxed Read Timing ............................................................ 901 Host-Bus 8/16 Mode Muxed Write Timing ............................................................ 901 General-Purpose Mode Read and Write Timing ................................................... 902 General-Purpose Mode iRDY Timing .................................................................. 902 ADC Input Equivalency Diagram ......................................................................... 904 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................... 905 SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 905 12 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 21-25. Figure 21-26. Figure C-1. Figure C-2. Figure C-3. Figure C-4. Figure C-5. Figure C-6. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 906 I2C Timing ......................................................................................................... 907 100-Pin LQFP Package Dimensions ................................................................... 941 100-Pin LQFP Tray Dimensions .......................................................................... 943 100-Pin LQFP Tape and Reel Dimensions ........................................................... 944 108-Ball BGA Package Dimensions .................................................................... 945 108-Ball BGA Tray Dimensions ........................................................................... 947 108-Ball BGA Tape and Reel Dimensions ............................................................ 948 July 24, 2011 13 Texas Instruments-Production Data Table of Contents List of Tables Table 1. Table 2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 7-1. Table 7-2. Table 7-3. Table 8-1. Table 8-2. Revision History .................................................................................................. 28 Documentation Conventions ................................................................................ 30 Summary of Processor Mode, Privilege Level, and Stack Use ................................ 58 Processor Register Map ....................................................................................... 59 PSR Register Combinations ................................................................................. 64 Memory Map ....................................................................................................... 72 Memory Access Behavior ..................................................................................... 75 SRAM Memory Bit-Banding Regions .................................................................... 77 Peripheral Memory Bit-Banding Regions ............................................................... 77 Exception Types .................................................................................................. 83 Interrupts ............................................................................................................ 83 Exception Return Behavior ................................................................................... 88 Faults ................................................................................................................. 89 Fault Status and Fault Address Registers .............................................................. 90 Cortex-M3 Instruction Summary ........................................................................... 92 Core Peripheral Register Regions ......................................................................... 96 Memory Attributes Summary ................................................................................ 99 TEX, S, C, and B Bit Field Encoding ................................................................... 102 Cache Policy for Memory Attribute Encoding ....................................................... 103 AP Bit Field Encoding ........................................................................................ 103 Memory Region Attributes for Stellaris Microcontrollers ........................................ 103 Peripherals Register Map ................................................................................... 104 Interrupt Priority Levels ...................................................................................... 131 Example SIZE Field Values ................................................................................ 159 Signals for JTAG_SWD_SWO (100LQFP) ........................................................... 163 Signals for JTAG_SWD_SWO (108BGA) ............................................................ 164 JTAG Port Pins State after Power-On Reset or RST assertion .............................. 165 JTAG Instruction Register Commands ................................................................. 170 Signals for System Control & Clocks (100LQFP) .................................................. 174 Signals for System Control & Clocks (108BGA) ................................................... 174 Reset Sources ................................................................................................... 175 Clock Source Options ........................................................................................ 182 Possible System Clock Frequencies Using the SYSDIV Field ............................... 185 Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 185 Examples of Possible System Clock Frequencies with DIV400=1 ......................... 186 System Control Register Map ............................................................................. 191 RCC2 Fields that Override RCC Fields ............................................................... 211 Signals for Hibernate (100LQFP) ........................................................................ 269 Signals for Hibernate (108BGA) .......................................................................... 270 Hibernation Module Clock Operation ................................................................... 275 Hibernation Module Register Map ....................................................................... 278 Flash Memory Protection Policy Combinations .................................................... 299 User-Programmable Flash Memory Resident Registers ....................................... 302 Flash Register Map ............................................................................................ 303 μDMA Channel Assignments .............................................................................. 342 Request Type Support ....................................................................................... 344 14 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table 8-7. Table 8-8. Table 8-9. Table 8-10. Table 8-11. Table 8-12. Table 8-13. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 9-7. Table 9-8. Table 9-9. Table 9-10. Table 9-11. Table 9-12. Table 10-1. Table 10-2. Table 10-3. Table 10-4. Table 10-5. Table 10-6. Table 10-7. Table 10-8. Table 11-1. Table 11-2. Table 11-3. Table 11-4. Table 11-5. Table 11-6. Table 12-1. Table 13-1. Table 13-2. Table 13-3. Table 13-4. Table 13-5. Table 14-1. Table 14-2. Table 14-3. Table 14-4. Control Structure Memory Map ........................................................................... 345 Channel Control Structure .................................................................................. 345 μDMA Read Example: 8-Bit Peripheral ................................................................ 354 μDMA Interrupt Assignments .............................................................................. 355 Channel Control Structure Offsets for Channel 30 ................................................ 356 Channel Control Word Configuration for Memory Transfer Example ...................... 356 Channel Control Structure Offsets for Channel 7 .................................................. 357 Channel Control Word Configuration for Peripheral Transmit Example .................. 358 Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 359 Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............................................................................................................ 360 μDMA Register Map .......................................................................................... 362 GPIO Pins With Non-Zero Reset Values .............................................................. 401 GPIO Pins and Alternate Functions (100LQFP) ................................................... 401 GPIO Pins and Alternate Functions (108BGA) ..................................................... 403 GPIO Pad Configuration Examples ..................................................................... 409 GPIO Interrupt Configuration Example ................................................................ 410 GPIO Pins With Non-Zero Reset Values .............................................................. 411 GPIO Register Map ........................................................................................... 411 GPIO Pins With Non-Zero Reset Values .............................................................. 424 GPIO Pins With Non-Zero Reset Values .............................................................. 430 GPIO Pins With Non-Zero Reset Values .............................................................. 432 GPIO Pins With Non-Zero Reset Values .............................................................. 435 GPIO Pins With Non-Zero Reset Values .............................................................. 442 Signals for External Peripheral Interface (100LQFP) ............................................ 458 Signals for External Peripheral Interface (108BGA) .............................................. 459 EPI SDRAM Signal Connections ......................................................................... 464 Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 468 EPI Host-Bus 8 Signal Connections .................................................................... 469 EPI Host-Bus 16 Signal Connections .................................................................. 470 EPI General Purpose Signal Connections ........................................................... 480 External Peripheral Interface (EPI) Register Map ................................................. 486 Available CCP Pins ............................................................................................ 532 Signals for General-Purpose Timers (100LQFP) .................................................. 533 Signals for General-Purpose Timers (108BGA) .................................................... 534 General-Purpose Timer Capabilities .................................................................... 535 16-Bit Timer With Prescaler Configurations ......................................................... 537 Timers Register Map .......................................................................................... 545 Watchdog Timers Register Map .......................................................................... 580 Signals for ADC (100LQFP) ............................................................................... 603 Signals for ADC (108BGA) ................................................................................. 604 Samples and FIFO Depth of Sequencers ............................................................ 605 Differential Sampling Pairs ................................................................................. 611 ADC Register Map ............................................................................................. 619 Signals for UART (100LQFP) ............................................................................. 679 Signals for UART (108BGA) ............................................................................... 679 Flow Control Mode ............................................................................................. 684 UART Register Map ........................................................................................... 689 July 24, 2011 15 Texas Instruments-Production Data Table of Contents Table 15-1. Table 15-2. Table 15-3. Table 16-1. Table 16-2. Table 16-3. Table 16-4. Table 16-5. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 19-1. Table 19-2. Table 19-3. Table 19-4. Table 19-5. Table 19-6. Table 19-7. Table 19-8. Table 19-9. Table 19-10. Table 19-11. Table 19-12. Table 19-13. Table 20-1. Table 20-2. Table 20-3. Table 21-1. Table 21-2. Table 21-3. Table 21-4. Table 21-5. Table 21-6. Table 21-7. Table 21-8. Table 21-9. Table 21-10. Table 21-11. Table 21-12. Table 21-13. Table 21-14. Table 21-15. Table 21-16. Table 21-17. Table 21-18. Table 21-19. Table 21-20. Signals for SSI (100LQFP) ................................................................................. 740 Signals for SSI (108BGA) ................................................................................... 740 SSI Register Map .............................................................................................. 751 Signals for I2C (100LQFP) ................................................................................. 781 Signals for I2C (108BGA) ................................................................................... 781 Examples of I2C Master Timer Period versus Speed Mode ................................... 785 Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 795 Write Field Decoding for I2CMCS[3:0] Field ......................................................... 800 Signals for Analog Comparators (100LQFP) ........................................................ 818 Signals for Analog Comparators (108BGA) .......................................................... 818 Internal Reference Voltage and ACREFCTL Field Values ..................................... 820 Analog Comparators Register Map ..................................................................... 821 GPIO Pins With Default Alternate Functions ........................................................ 832 Signals by Pin Number ....................................................................................... 833 Signals by Signal Name ..................................................................................... 841 Signals by Function, Except for GPIO ................................................................. 848 GPIO Pins and Alternate Functions ..................................................................... 854 Possible Pin Assignments for Alternate Functions ................................................ 856 Signals by Pin Number ....................................................................................... 858 Signals by Signal Name ..................................................................................... 866 Signals by Function, Except for GPIO ................................................................. 874 GPIO Pins and Alternate Functions ..................................................................... 880 Possible Pin Assignments for Alternate Functions ................................................ 882 Connections for Unused Signals (100-Pin LQFP) ................................................. 884 Connections for Unused Signals (108-Ball BGA) .................................................. 884 Temperature Characteristics ............................................................................... 886 Thermal Characteristics ..................................................................................... 886 ESD Absolute Maximum Ratings ........................................................................ 886 Maximum Ratings .............................................................................................. 887 Recommended DC Operating Conditions ............................................................ 887 JTAG Characteristics ......................................................................................... 888 Power Characteristics ........................................................................................ 890 Reset Characteristics ......................................................................................... 891 LDO Regulator Characteristics ........................................................................... 892 Phase Locked Loop (PLL) Characteristics ........................................................... 892 Actual PLL Frequency ........................................................................................ 893 PIOSC Clock Characteristics .............................................................................. 893 30-kHz Clock Characteristics .............................................................................. 893 Hibernation Clock Characteristics ....................................................................... 893 HIB Oscillator Input Characteristics ..................................................................... 894 Main Oscillator Clock Characteristics .................................................................. 894 Supported MOSC Crystal Frequencies ................................................................ 894 System Clock Characteristics with ADC Operation ............................................... 895 Sleep Modes AC Characteristics ......................................................................... 895 Hibernation Module Battery Characteristics ......................................................... 895 Hibernation Module AC Characteristics ............................................................... 896 Flash Memory Characteristics ............................................................................ 897 GPIO Module Characteristics ............................................................................. 897 16 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 21-21. Table 21-22. Table 21-23. Table 21-24. Table 21-25. Table 21-26. Table 21-27. Table 21-28. Table 21-29. Table 21-30. Table 21-31. Table 21-32. Table 21-33. Table 21-34. Table 21-35. Table 21-36. Table 21-37. Table 21-38. Table 21-39. Table 21-40. Table 21-41. Table 21-42. Table B-1. EPI SDRAM Characteristics ............................................................................... 897 EPI SDRAM Interface Characteristics ................................................................. 898 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics ................................... 899 EPI General-Purpose Interface Characteristics .................................................... 901 ADC Characteristics ........................................................................................... 903 ADC Module External Reference Characteristics ................................................. 904 ADC Module Internal Reference Characteristics .................................................. 904 SSI Characteristics ............................................................................................ 904 I2C Characteristics ............................................................................................. 906 100BASE-TX Transmitter Characteristics ............................................................ 907 100BASE-TX Transmitter Characteristics (informative) ......................................... 907 100BASE-TX Receiver Characteristics ................................................................ 907 10BASE-T Transmitter Characteristics ................................................................ 907 10BASE-T Transmitter Characteristics (informative) ............................................. 908 10BASE-T Receiver Characteristics .................................................................... 908 Isolation Transformers ....................................................................................... 908 Analog Comparator Characteristics ..................................................................... 908 Analog Comparator Voltage Reference Characteristics ........................................ 909 Nominal Power Consumption ............................................................................. 909 Detailed Current Specifications ........................................................................... 910 Hibernation Detailed Current Specifications ......................................................... 910 External VDDC Source Current Specifications ....................................................... 911 Part Ordering Information ................................................................................... 939 July 24, 2011 17 Texas Instruments-Production Data Table of Contents List of Registers The Cortex-M3 Processor ............................................................................................................. 53 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Cortex General-Purpose Register 0 (R0) ........................................................................... 60 Cortex General-Purpose Register 1 (R1) ........................................................................... 60 Cortex General-Purpose Register 2 (R2) ........................................................................... 60 Cortex General-Purpose Register 3 (R3) ........................................................................... 60 Cortex General-Purpose Register 4 (R4) ........................................................................... 60 Cortex General-Purpose Register 5 (R5) ........................................................................... 60 Cortex General-Purpose Register 6 (R6) ........................................................................... 60 Cortex General-Purpose Register 7 (R7) ........................................................................... 60 Cortex General-Purpose Register 8 (R8) ........................................................................... 60 Cortex General-Purpose Register 9 (R9) ........................................................................... 60 Cortex General-Purpose Register 10 (R10) ....................................................................... 60 Cortex General-Purpose Register 11 (R11) ........................................................................ 60 Cortex General-Purpose Register 12 (R12) ....................................................................... 60 Stack Pointer (SP) ........................................................................................................... 61 Link Register (LR) ............................................................................................................ 62 Program Counter (PC) ..................................................................................................... 63 Program Status Register (PSR) ........................................................................................ 64 Priority Mask Register (PRIMASK) .................................................................................... 68 Fault Mask Register (FAULTMASK) .................................................................................. 69 Base Priority Mask Register (BASEPRI) ............................................................................ 70 Control Register (CONTROL) ........................................................................................... 71 Cortex-M3 Peripherals ................................................................................................................... 96 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 107 SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 109 SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 110 Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 111 Interrupt 32-54 Set Enable (EN1), offset 0x104 ................................................................ 112 Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 113 Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ............................................................ 114 Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 115 Interrupt 32-54 Set Pending (PEND1), offset 0x204 ......................................................... 116 Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 117 Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 .................................................. 118 Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 119 Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ........................................................... 120 Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 121 Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 121 Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 121 Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 121 Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 121 Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 121 Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 121 Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 121 Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 121 18 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 121 Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 121 Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 121 Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 121 Interrupt 52-54 Priority (PRI13), offset 0x434 ................................................................... 121 Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 123 Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 124 CPU ID Base (CPUID), offset 0xD00 ............................................................................... 126 Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 127 Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 130 Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 131 System Control (SYSCTRL), offset 0xD10 ....................................................................... 133 Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 135 System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 137 System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 138 System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 139 System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 140 Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 144 Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 150 Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 151 Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 152 MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 153 MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 154 MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 156 MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 157 MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 157 MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 157 MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 157 MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 159 MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 159 MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 159 MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 159 System Control ............................................................................................................................ 174 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Device Identification 0 (DID0), offset 0x000 ..................................................................... 193 Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 195 Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 196 Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 198 Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 200 Reset Cause (RESC), offset 0x05C ................................................................................ 202 Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 204 XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 208 GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 209 Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 211 Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 214 Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 215 Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 217 Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 219 Device Identification 1 (DID1), offset 0x004 ..................................................................... 220 July 24, 2011 19 Texas Instruments-Production Data Table of Contents Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 222 Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 223 Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 225 Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 227 Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 229 Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 231 Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 232 Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 233 Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 237 Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 238 Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 239 Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 240 Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 242 Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 244 Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 246 Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 249 Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 252 Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 255 Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 257 Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 259 Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 261 Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 263 Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 266 Hibernation Module ..................................................................................................................... 268 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... Hibernation Control (HIBCTL), offset 0x010 ..................................................................... Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 279 280 281 282 283 286 288 290 292 293 294 Internal Memory ........................................................................................................................... 295 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Flash Memory Address (FMA), offset 0x000 .................................................................... 305 Flash Memory Data (FMD), offset 0x004 ......................................................................... 306 Flash Memory Control (FMC), offset 0x008 ..................................................................... 307 Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 310 Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 311 Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 312 Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 313 Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 314 Flash Control (FCTL), offset 0x0F8 ................................................................................. 315 Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 316 ROM Control (RMCTL), offset 0x0F0 .............................................................................. 317 Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 318 20 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 319 Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 320 User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 322 User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 323 User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 324 User Register 3 (USER_REG3), offset 0x1EC ................................................................. 325 Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 326 Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 327 Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 328 Flash Memory Protection Read Enable 4 (FMPRE4), offset 0x210 .................................... 329 Flash Memory Protection Read Enable 5 (FMPRE5), offset 0x214 .................................... 330 Flash Memory Protection Read Enable 6 (FMPRE6), offset 0x218 .................................... 331 Flash Memory Protection Read Enable 7 (FMPRE7), offset 0x21C ................................... 332 Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 333 Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 334 Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 335 Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 ............................... 336 Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 ............................... 337 Flash Memory Protection Program Enable 6 (FMPPE6), offset 0x418 ............................... 338 Flash Memory Protection Program Enable 7 (FMPPE7), offset 0x41C ............................... 339 Micro Direct Memory Access (μDMA) ........................................................................................ 340 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 364 DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 365 DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 366 DMA Status (DMASTAT), offset 0x000 ............................................................................ 371 DMA Configuration (DMACFG), offset 0x004 ................................................................... 373 DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 374 DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 375 DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 376 DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 377 DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 378 DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 379 DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 380 DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 381 DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 382 DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 383 DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 384 DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 385 DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 386 DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 387 DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 388 DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 389 DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 390 DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 391 DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 392 DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 393 DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 394 DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 395 July 24, 2011 21 Texas Instruments-Production Data Table of Contents Register 28: Register 29: Register 30: Register 31: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 396 397 398 399 General-Purpose Input/Outputs (GPIOs) ................................................................................... 400 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 414 GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 415 GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 416 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 417 GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 418 GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 419 GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 420 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 421 GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 423 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 424 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 426 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 427 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 428 GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 429 GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 430 GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 432 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 434 GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 435 GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 437 GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 438 GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 440 GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 442 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 444 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 445 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 446 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 447 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 448 GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 449 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 450 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 451 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 452 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 453 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 454 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 455 External Peripheral Interface (EPI) ............................................................................................. 456 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: EPI Configuration (EPICFG), offset 0x000 ....................................................................... 488 EPI Main Baud Rate (EPIBAUD), offset 0x004 ................................................................. 489 EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 .............................................. 491 EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ............................................... 493 EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ........................................... 496 EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ........................................ 500 EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 .......................................... 505 EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 ....................................... 508 22 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 ................................... EPI Address Map (EPIADDRMAP), offset 0x01C ............................................................. EPI Read Size 0 (EPIRSIZE0), offset 0x020 .................................................................... EPI Read Size 1 (EPIRSIZE1), offset 0x030 .................................................................... EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................ EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................ EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 ............................................. EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 ............................................. EPI Status (EPISTAT), offset 0x060 ................................................................................ EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ...................................................... EPI Read FIFO (EPIREADFIFO), offset 0x070 ................................................................ EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 .................................................... EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 .................................................... EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ................................................... EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 .................................................... EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 .................................................... EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 .................................................... EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ................................................... EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................ EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ...................................................... EPI Interrupt Mask (EPIIM), offset 0x210 ......................................................................... EPI Raw Interrupt Status (EPIRIS), offset 0x214 .............................................................. EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................ EPI Error Interrupt Status and Clear (EPIEISC), offset 0x21C ........................................... 511 512 514 514 515 515 516 516 518 520 521 521 521 521 521 521 521 521 522 524 525 526 528 529 General-Purpose Timers ............................................................................................................. 531 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 547 GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 548 GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 550 GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 552 GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 555 GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 557 GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 560 GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 563 GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 565 GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 566 GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 567 GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 568 GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 569 GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 570 GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 571 GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 572 GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 573 GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 574 GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 575 GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 576 Watchdog Timers ......................................................................................................................... 577 Register 1: Register 2: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 581 Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 582 July 24, 2011 23 Texas Instruments-Production Data Table of Contents Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 583 Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 585 Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 586 Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 587 Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 588 Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 589 Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 590 Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 591 Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 592 Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 593 Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 594 Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 595 Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 596 Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 597 Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 598 Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 599 Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 600 Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 601 Analog-to-Digital Converter (ADC) ............................................................................................. 602 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 622 ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 623 ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 625 ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 627 ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 630 ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 632 ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 636 ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 637 ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 639 ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 640 ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 642 ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 643 ADC Control (ADCCTL), offset 0x038 ............................................................................. 645 ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 646 ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 648 ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 651 ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 651 ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 651 ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 651 ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 652 ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 652 ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 652 ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 652 ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 654 ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 656 ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 658 ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 658 ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 659 ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 659 24 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 661 ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 661 ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 662 ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 662 ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 664 ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 665 ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 666 ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 667 ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 668 ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 673 ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 673 ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 673 ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 673 ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 673 ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 673 ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 673 ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 673 ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 675 ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 675 ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 675 ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 675 ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 675 ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 675 ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 675 ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 675 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 677 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: UART Data (UARTDR), offset 0x000 ............................................................................... 691 UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 693 UART Flag (UARTFR), offset 0x018 ................................................................................ 696 UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 699 UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 700 UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 701 UART Line Control (UARTLCRH), offset 0x02C ............................................................... 702 UART Control (UARTCTL), offset 0x030 ......................................................................... 704 UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 708 UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 710 UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 714 UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 717 UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 720 UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 722 UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 723 UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 724 UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 725 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 726 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 727 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 728 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 729 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 730 July 24, 2011 25 Texas Instruments-Production Data Table of Contents Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 731 732 733 734 735 736 737 Synchronous Serial Interface (SSI) ............................................................................................ 738 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 753 SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 755 SSI Data (SSIDR), offset 0x008 ...................................................................................... 757 SSI Status (SSISR), offset 0x00C ................................................................................... 758 SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 760 SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 761 SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 762 SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 764 SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 766 SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 767 SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 768 SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 769 SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 770 SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 771 SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 772 SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 773 SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 774 SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 775 SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 776 SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 777 SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 778 SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 779 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 780 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 797 I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 798 I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 802 I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 803 I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 804 I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 805 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 806 I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 807 I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 808 I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 809 I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 810 I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 812 I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 813 I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 814 I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 815 I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 816 26 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Analog Comparators ................................................................................................................... 817 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... July 24, 2011 823 824 825 826 827 827 828 828 27 Texas Instruments-Production Data Revision History Revision History The revision history table notes changes made between the indicated revisions of the LM3S1F11 data sheet. Table 1. Revision History Date Revision July 2011 9970 March 2011 9538 Description ■ Corrected "Reset Sources" table. ■ Added Important Note that RCC register must be written before RCC2 register. ■ Added missing Start Calibration (CAL) bit to the Precision Internal Oscillator Calibration (PIOSCCAL) register. ■ Added missing Precision Internal Oscillator Statistics (PIOSCSTAT) register. ■ In Hibernation Module chapter, deleted section "Special Considerations When Using a 4.194304-MHz Crystal" as this content was added to the errata document. ■ Added a note that all GPIO signals are 5-V tolerant when configured as inputs except for PB0 and PB1, which are limited to 3.6 V. ■ Corrected LIN Mode bit names in UART Interrupt Clear (UARTICR) register. ■ Corrected pin number for RST in table "Connections for Unused Signals" (other pin tables were correct). ■ In the "Operating Characteristics" chapter: – In the "Thermal Characteristics" table, the Thermal resistance value was changed. – In the "ESD Absolute Maximum Ratings" table, the VESDCDM parameter was changed and the VESDMM parameter was deleted. ■ The "Electrical Characteristics" chapter was reorganized by module. In addition, some of the Recommended DC Operating Conditions, LDO Regulator, Clock, GPIO, EPI, Hibernation Module, ADC, and SSI characteristics were finalized. ■ Additional minor data sheet clarifications and corrections. Started tracking revision history. 28 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller About This Document This data sheet provides reference information for the LM3S1F11 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents ® The following related documents are available on the Stellaris web site at www.ti.com/stellaris: ■ Stellaris® Errata ■ ARM® Cortex™-M3 Errata ■ Cortex™-M3 Instruction Set Technical User's Manual ■ Stellaris® Boot Loader User's Guide ■ Stellaris® Graphics Library User's Guide ■ Stellaris® Peripheral Driver Library User's Guide ■ Stellaris® ROM User’s Guide The following related documents are also referenced: ■ ARM® Debug Interface V5 Architecture Specification ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers. July 24, 2011 29 Texas Instruments-Production Data About This Document Documentation Conventions This document uses the conventions shown in Table 2 on page 30. Table 2. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. bit A single bit in a register. bit field Two or more consecutive and related bits. offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 2-4 on page 72. Register N Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. reserved Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. Register Bit/Field Types This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. R/WC Software can read or write this field. Writing to it with any value clears the register. R/W1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1S Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit value in the register. W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field Reset Value This value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. 30 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 2. Documentation Conventions (continued) Notation Meaning assert a signal Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). deassert a signal Change the value of the signal from the logically True state to the logically False state. SIGNAL Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. 0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. July 24, 2011 31 Texas Instruments-Production Data Architectural Overview 1 Architectural Overview ® Texas Instruments is the industry leader in bringing 32-bit capabilities and the full benefits of ARM Cortex™-M3-based microcontrollers to the broadest reach of the microcontroller market. For current ® users of 8- and 16-bit MCUs, Stellaris with Cortex-M3 offers a direct path to the strongest ecosystem of development tools, software and knowledge in the industry. Designers who migrate to Stellaris benefit from great tools, small code footprint and outstanding performance. Even more important, designers can enter the ARM ecosystem with full confidence in a compatible roadmap from $1 to 1 GHz. For users of current 32-bit MCUs, the Stellaris family offers the industry’s first implementation of Cortex-M3 and the Thumb-2 instruction set. With blazingly-fast responsiveness, Thumb-2 technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density and performance. Thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system cost while delivering 25 percent better performance. The Texas Instruments Stellaris family of microcontrollers—the first ARM Cortex-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S1F11 microcontroller has the following features: ■ ARM Cortex-M3 Processor Core – 80-MHz operation; 100 DMIPS performance – ARM Cortex SysTick Timer – Nested Vectored Interrupt Controller (NVIC) ■ On-Chip Memory – 384 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance above 50 MHz – 48 KB single-cycle SRAM ® – Internal ROM loaded with StellarisWare software: • Stellaris Peripheral Driver Library • Stellaris Boot Loader • Advanced Encryption Standard (AES) cryptography tables • Cyclic Redundancy Check (CRC) error detection functionality ■ External Peripheral Interface (EPI) – 8/16/32-bit dedicated parallel bus for external peripherals – Supports SDRAM, SRAM/Flash memory, FPGAs, CPLDs ■ Advanced Serial Integration – Three UARTs with IrDA and ISO 7816 support (one UART with modem flow control and status) – Two I2C modules 32 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller – Two Synchronous Serial Interface modules (SSI) ■ System Integration – Direct Memory Access Controller (DMA) – System control and clocks including on-chip precision 16-MHz oscillator – Four 32-bit timers (up to eight 16-bit) – Eight Capture Compare PWM pins (CCP) – Lower-power battery-backed hibernation module – Real-Time Clock in Hibernation module – Two Watchdog Timers • One timer runs off the main oscillator • One timer runs off the precision internal oscillator – Up to 67 GPIOs, depending on configuration • Highly flexible pin muxing allows use as GPIO or one of several peripheral functions • Independently configurable to 2, 4 or 8 mA drive capability • Up to 4 GPIOs can have 18 mA drive capability ■ Analog – 12-bit Analog-to-Digital Converter (ADC) with eight analog input channels and a sample rate of one million samples/second – Two analog comparators – Eight digital comparators – On-chip voltage regulator ■ JTAG and ARM Serial Wire Debug (SWD) ■ 100-pin LQFP package ■ 108-ball BGA package ■ Industrial (-40°C to 85°C) Temperature Range The LM3S1F11 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, and fire and security. For applications requiring extreme conservation of power, the LM3S1F11 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S1F11 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S1F11 microcontroller perfectly for battery applications. July 24, 2011 33 Texas Instruments-Production Data Architectural Overview In addition, the LM3S1F11 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S1F11 microcontroller is code-compatible to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise needs. Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact Information” on page 939 for ordering information for Stellaris family devices. 1.1 Functional Overview The following sections provide an overview of the features of the LM3S1F11 microcontroller. The page number in parentheses indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 939. 1.1.1 ARM Cortex-M3 The following sections provide an overview of the ARM Cortex-M3 processor core and instruction set, the integrated System Timer (SysTick) and the Nested Vectored Interrupt Controller. 1.1.1.1 Processor Core (see page 53) All members of the Stellaris product family, including the LM3S1F11 microcontroller, are designed around an ARM Cortex-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. ■ 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast multiplier ■ Deterministic, high-performance interrupt handling for time-critical applications 34 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing ■ Migration from the ARM7 processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage ■ Ultra-low power consumption with integrated sleep modes ■ 80-MHz operation ■ 1.25 DMIPS/MHz 1.1.1.2 Memory Map (see page 72) A memory map lists the location of instructions and data in memory. The memory map for the LM3S1F11 controller can be found in “Memory Model” on page 72. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. 1.1.1.3 System Timer (SysTick) (see page 96) ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine ■ A high-speed alarm timer using the system clock ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter ■ A simple counter used to measure time to completion and time used ■ An internal clock-source control based on missing/meeting durations. 1.1.1.4 Nested Vectored Interrupt Controller (NVIC) (see page 97) The LM3S1F11 controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC and Cortex-M3 prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 37 interrupts. ■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining ■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler for safety critical applications July 24, 2011 35 Texas Instruments-Production Data Architectural Overview ■ Dynamically reprioritizable interrupts ■ Exceptional interrupt handling via hardware implementation of required register manipulations 1.1.1.5 System Control Block (SCB) (see page 99) The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 1.1.1.6 Memory Protection Unit (MPU) (see page 99) The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 1.1.2 On-Chip Memory The following sections describe the on-chip memory modules. 1.1.2.1 SRAM (see page 296) The LM3S1F11 microcontroller provides 48 KB of single-cycle on-chip SRAM. The internal SRAM of the Stellaris devices is located at offset 0x2000.0000 of the device memory map. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller (µDMA). 1.1.2.2 Flash Memory (see page 298) The LM3S1F11 microcontroller provides 384 KB of single-cycle on-chip Flash memory (above 50 MHz, the Flash memory can be accessed in a single cycle as long as the code is linear; branches incur a one-cycle stall). The Flash memory is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.1.2.3 ROM (see page 296) The LM3S1F11 ROM is preprogrammed with the following software and programs: ■ Stellaris Peripheral Driver Library ■ Stellaris Boot Loader ■ Advanced Encryption Standard (AES) cryptography tables ■ Cyclic Redundancy Check (CRC) error-detection functionality 36 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller The Stellaris Peripheral Driver Library is a royalty-free software library for controlling on-chip peripherals with a boot-loader capability. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M3 core. No special pragmas or custom assembly code prologue/epilogue functions are required. For applications that require in-field programmability, the royalty-free Stellaris Boot Loader can act as an application loader and support in-field firmware updates. The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government. AES is a strong encryption method with reasonable performance and size. In addition, it is fast in both hardware and software, is fairly easy to implement, and requires little memory. The Texas Instruments encryption package is available with full source code, and is based on lesser general public license (LGPL) source. An LGPL means that the code can be used within an application without any copyleft implications for the application (the code does not automatically become open source). Modifications to the package source, however, must be open source. CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents as when previously checked. This technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that Flash memory contents have not been changed, and for other cases where the data needs to be validated. A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more readily. 1.1.3 External Peripheral Interface (see page 456) The External Peripheral Interface (EPI) provides access to external devices using a parallel path. Unlike communications peripherals such as SSI, UART, and I2C, the EPI is designed to act like a bus to external peripherals and memory. The EPI has the following features: ■ 8/16/32-bit dedicated parallel bus for external peripherals and memory ■ Memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from SDRAM, SRAM and Flash memory ■ Blocking and non-blocking reads ■ Separates processor from timing details through use of an internal write FIFO ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for read and write – Read channel request asserted by programmable levels on the internal non-blocking read FIFO (NBRFIFO) – Write channel request asserted by empty on the internal write FIFO (WFIFO) The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory (SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same way as a communication mechanism and is speed-controlled using clocking. ■ Synchronous Dynamic Random Access Memory (SDRAM) mode July 24, 2011 37 Texas Instruments-Production Data Architectural Overview – Supports x16 (single data rate) SDRAM at up to 50 MHz – Supports low-cost SDRAMs up to 64 MB (512 megabits) – Includes automatic refresh and access to all banks/rows – Includes a Sleep/Standby mode to keep contents active with minimal power draw – Multiplexed address/data interface for reduced pin count ■ Host-Bus mode – Traditional x8 and x16 MCU bus interface capabilities – Similar device compatibility options as PIC, ATmega, 8051, and others – Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with no byte selects) – Support of both muxed and de-muxed address and data – Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant, with support for external FIFO (XFIFO) EMPTY and FULL signals – Speed controlled, with read and write data wait-state counters – Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn – Manual chip-enable (or use extra address pins) ■ General-Purpose mode – Wide parallel interfaces for fast communications with CPLDs and FPGAs – Data widths up to 32 bits – Data rates up to 150 MB/second – Optional "address" sizes from 4 bits to 20 bits – Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input ■ General parallel GPIO – 1 to 32 bits, FIFOed with speed control – Useful for custom peripherals or for digital data acquisition and actuator controls 1.1.4 Serial Communications Peripherals The LM3S1F11 controller supports both asynchronous and synchronous serial communications with: ■ Three UARTs with IrDA and ISO 7816 support (one UART with modem flow control and status) 38 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ Two I2C modules ■ Two Synchronous Serial Interface modules (SSI) The following sections provide more detail on each of these communications functions. 1.1.4.1 UART (see page 677) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S1F11 microcontroller includes three fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, modem status, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and are unmasked. The three UARTs have the following features: ■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by 16) and 10 Mbps for high speed (divide by 8) ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Standard asynchronous communication bits for start, stop, and parity ■ Line-break generation and detection ■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Support for communication with ISO 7816 smart cards ■ Full modem handshake support (on UART1) July 24, 2011 39 Texas Instruments-Production Data Architectural Overview ■ LIN protocol support ■ Standard FIFO-level and End-of-Transmission interrupts ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level 1.1.4.2 I2C (see page 780) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. Each device on the I2C bus can be designated as either a master or a slave. Each I2C module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts. The LM3S1F11 microcontroller includes two I2C modules with the following features: ■ Devices on the I2C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation ■ Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive ■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) ■ Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected ■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 40 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 1.1.4.3 SSI (see page 738) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts data between parallel and serial. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The LM3S1F11 microcontroller includes two SSI modules with the following features: ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Master or slave operation ■ Programmable clock bit rate and prescaler ■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing ■ Standard FIFO-based interrupts and End-of-Transmission interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries – Transmit single request asserted when there is space in the FIFO; burst request asserted when FIFO contains 4 entries 1.1.5 System Integration The LM3S1F11 microcontroller provides a variety of standard system functions integrated into the device, including: ■ Direct Memory Access Controller (DMA) ■ System control and clocks including on-chip precision 16-MHz oscillator ■ Four 32-bit timers (up to eight 16-bit) ■ Eight Capture Compare PWM pins (CCP) ■ Lower-power battery-backed hibernation module ■ Real-Time Clock in Hibernation module July 24, 2011 41 Texas Instruments-Production Data Architectural Overview ■ Two Watchdog Timers – One timer runs off the main oscillator – One timer runs off the precision internal oscillator ■ Up to 67 GPIOs, depending on configuration – Highly flexible pin muxing allows use as GPIO or one of several peripheral functions – Independently configurable to 2, 4 or 8 mA drive capability – Up to 4 GPIOs can have 18 mA drive capability The following sections provide more detail on each of these functions. 1.1.5.1 Direct Memory Access (see page 340) The LM3S1F11 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: ® ■ ARM PrimeCell 32-channel configurable µDMA controller ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Primary and secondary channel assignments – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable priority scheme – Optional software-initiated requests for any channel ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping 42 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller – Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Transfer size is programmable in binary steps from 1 to 1024 ■ Source and destination address increment size of byte, half-word, word, or no increment ■ Maskable peripheral requests ■ Interrupt on transfer completion, with a separate interrupt per channel 1.1.5.2 System Control and Clocks (see page 174) System control determines the overall operation of the device. It provides information about the device, controls power-saving features, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. ■ Device identification information: version, part number, SRAM size, Flash memory size, and so on ■ Power control – On-chip fixed Low Drop-Out (LDO) voltage regulator – Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits – Low-power options for microcontroller: Sleep and Deep-sleep modes with clock gating – Low-power options for on-chip modules: software controls shutdown of individual peripherals and memory – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Multiple clock sources for microcontroller system clock – Precision Oscillator (PIOSC): On-chip resource providing a 16 MHz ±1% frequency at room temperature • 16 MHz ±3% across temperature • Can be recalibrated with 7-bit trim resolution • Software power down control for low power modes – Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. • External crystal used with or without on-chip PLL: select supported frequencies from 1 MHz to 16.384 MHz. • External oscillator: from DC to maximum device speed – Internal 30-kHz Oscillator: on chip resource providing a 30 kHz ± 50% frequency, used during power-saving modes – 32.768-kHz external oscillator for the Hibernation Module: eliminates need for additional crystal for main clock source July 24, 2011 43 Texas Instruments-Production Data Architectural Overview ■ Flexible reset sources – Power-on reset (POR) – Reset pin assertion – Brown-out reset (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – MOSC failure 1.1.5.3 Programmable Timers (see page 531) Programmable timers can be used to count or time external events that drive the Timer input pins. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional options: ■ Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 16-bit input-edge count- or time-capture modes – 16-bit PWM mode with software-programmable output inversion of the PWM signal ■ Count up or down ■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events ■ ADC event trigger ■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding RTC mode) ■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each timer – Burst request generated on timer interrupt 44 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 1.1.5.4 CCP Pins (see page 538) Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin. The LM3S1F11 microcontroller includes eight Capture Compare PWM pins (CCP) that can be programmed to operate in the following modes: ■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer captures and stores the current timer value when a programmed event occurs. ■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer compares the current value with a stored value and generates an interrupt when a match occurs. ■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated based on a match between the counter value and a value stored in a match register and is output on the CCP pin. 1.1.5.5 Hibernation Module (see page 268) The Hibernation module provides logic to switch power off to the main processor and peripherals and to wake on external or time-based events. The Hibernation module includes power-sequencing logic and has the following features: ■ 32-bit real-time counter (RTC) – Two 32-bit RTC match registers for timed wake-up and interrupt generation – RTC predivider trim for making fine adjustments to the clock rate ■ Two mechanisms for power control – System power control using discrete external regulator – On-chip power control using internal switches under register control ■ Dedicated pin for waking using an external signal ■ RTC operational and hibernation memory valid as long as VBAT is valid ■ Low-battery detection, signaling, and interrupt generation ■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal; 32.768-kHz external oscillator can be used for main controller clock ■ 64 32-bit words of non-volatile memory to save state during hibernation ■ Programmable interrupts for RTC match, external wake, and low battery events 1.1.5.6 Watchdog Timers (see page 577) A watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer can generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate an interrupt to the microcontroller on its July 24, 2011 45 Texas Instruments-Production Data Architectural Overview first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. The LM3S1F11 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris Watchdog Timer module has the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug 1.1.5.7 Programmable GPIOs (see page 400) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris GPIO module is comprised of nine physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 0-67 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 832 for the signals available to each GPIO pin). ■ Up to 67 GPIOs, depending on configuration ■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions ■ 5-V-tolerant in input configuration ■ Fast toggle capable of a change every two clock cycles ■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with existing code ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can be used to initiate an ADC sample sequence ■ Pins configured as digital inputs are Schmitt-triggered ■ Programmable control for GPIO pad configuration 46 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 1.1.6 Analog The LM3S1F11 microcontroller provides analog functions integrated into the device, including: ■ 12-bit Analog-to-Digital Converter (ADC) with eight analog input channels and a sample rate of one million samples/second ■ Two analog comparators ■ Eight digital comparators ■ On-chip voltage regulator The following provides more detail on these analog functions. 1.1.6.1 ADC (see page 602) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris ADC module features 12-bit conversion resolution and supports eight input channels plus an internal temperature sensor. Four buffered sample sequencers allow rapid sampling of up to eight analog input sources without controller intervention. Each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. The ADC module has a digital comparator function that allows the conversion value to be diverted to a comparison unit that provides eight digital comparators. The LM3S1F11 microcontroller provides one ADC module with the following features: ■ Eight analog input channels ■ 12-bit precision ADC with an accurate 10-bit data compatibility mode ■ Single-ended and differential-input configurations ■ On-chip internal temperature sensor ■ Maximum sample rate of one million samples/second ■ Optional phase shift in sample time programmable from 22.5º to 337.5º ■ Four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) July 24, 2011 47 Texas Instruments-Production Data Architectural Overview – Timers – Analog Comparators – GPIO ■ Hardware averaging of up to 64 samples ■ Digital comparison unit providing eight digital comparators ■ Converter uses an internal 3-V reference or an external reference ■ Power and ground for the analog circuitry is separate from the digital power and ground ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each sample sequencer – ADC module uses burst requests for DMA 1.1.6.2 Analog Comparators (see page 817) An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The LM3S1F11 microcontroller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. The LM3S1F11 microcontroller provides two independent integrated analog comparators with the following functions: ■ Compare external pin input to external pin input or to internal programmable voltage reference ■ Compare a test voltage against any one of the following voltages: – An individual external reference voltage – A shared single external reference voltage – A shared internal reference voltage 1.1.7 JTAG and ARM Serial Wire Debug (see page 162) The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module providing all the normal JTAG debug and test functionality plus real-time access to system 48 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller memory without halting the core or requiring any target resident code. The SWJ-DP interface has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer 1.1.8 Packaging and Temperature ■ Industrial-range 100-pin RoHS-compliant LQFP package ■ Industrial-range 108-ball RoHS-compliant BGA package 1.2 Target Applications The Stellaris family is positioned for cost-conscious applications requiring significant control processing and connectivity capabilities such as: ■ Test and measurement equipment ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation July 24, 2011 49 Texas Instruments-Production Data Architectural Overview 1.3 High-Level Block Diagram Figure 1-1 on page 51 depicts the features on the Stellaris LM3S1F11 microcontroller. Note that there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back access performance than the APB bus. 50 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 1-1. Stellaris LM3S1F11 Microcontroller High-Level Block Diagram JTAG/SWD ARM® Cortex™-M3 ROM (80 MHz) System Control and Clocks (w/ Precis. Osc.) Flash (384 KB) DCode bus NVIC Boot Loader DriverLib AES & CRC MPU ICode bus System Bus LM3S1F11 Bus Matrix SRAM (48 KB) SYSTEM PERIPHERALS GeneralPurpose Timers (4) Hibernation Module External Peripheral Interface I2C (2) Advanced Peripheral Bus (APB) Watchdog Timers (2) Advanced High-Performance Bus (AHB) DMA GPIOs (67) SERIAL PERIPHERALS UARTs (3) SSI (2) ANALOG PERIPHERALS Analog Comparators (2) 12-Bit ADC Channels (8) July 24, 2011 51 Texas Instruments-Production Data Architectural Overview 1.4 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 830 ■ “Signal Tables” on page 832 ■ “Operating Characteristics” on page 886 ■ “Electrical Characteristics” on page 887 ■ “Package Information” on page 941 52 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 2 The Cortex-M3 Processor The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ® ■ 32-bit ARM Cortex™-M3 architecture optimized for small-footprint embedded applications ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast multiplier ■ Deterministic, high-performance interrupt handling for time-critical applications ■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing ■ Migration from the ARM7 processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage ■ Ultra-low power consumption with integrated sleep modes ■ 80-MHz operation ■ 1.25 DMIPS/MHz ® The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. July 24, 2011 53 Texas Instruments-Production Data The Cortex-M3 Processor This chapter provides information on the Stellaris implementation of the Cortex-M3 processor, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the instruction set, see the Cortex™-M3 Instruction Set Technical User's Manual. 2.1 Block Diagram The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. 54 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep ARM Cortex-M3 CM3 Core Debug Instructions Data Trace Port Interface Unit Memory Protection Unit Flash Patch and Breakpoint Instrumentation Data Watchpoint Trace Macrocell and Trace ROM Table Private Peripheral Bus (internal) Adv. Peripheral Bus Bus Matrix Serial Wire JTAG Debug Port Debug Access Port 2.2 Overview 2.2.1 System-Level Interface Serial Wire Output Trace Port (SWO) I-code bus D-code bus System bus The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis. 2.2.2 Integrated Configurable Debug The Cortex-M3 processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification for details on SWJ-DP. For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. July 24, 2011 55 Texas Instruments-Production Data The Cortex-M3 Processor The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored in a read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration. For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5 Architecture Specification. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer, as shown in Figure 2-2 on page 56. Figure 2-2. TPIU Block Diagram 2.2.4 Debug ATB Slave Port ATB Interface APB Slave Port APB Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) Cortex-M3 System Component Details The Cortex-M3 includes the following system components: ■ SysTick A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as a simple counter (see “System Timer (SysTick)” on page 96). ■ Nested Vectored Interrupt Controller (NVIC) An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 97). ■ System Control Block (SCB) 56 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions( see “System Control Block (SCB)” on page 99). ■ Memory Protection Unit (MPU) Improves system reliability by defining the memory attributes for different memory regions. The MPU provides up to eight different regions and an optional predefined background region (see “Memory Protection Unit (MPU)” on page 99). 2.3 Programming Model This section describes the Cortex-M3 programming model. In addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included. 2.3.1 Processor Mode and Privilege Levels for Software Execution The Cortex-M3 has two modes of operation: ■ Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. ■ Handler mode Used to handle exceptions. When the processor has finished exception processing, it returns to Thread mode. In addition, the Cortex-M3 has two privilege levels: ■ Unprivileged In this mode, software has the following restrictions: – Limited access to the MSR and MRS instructions and no use of the CPS instruction – No access to the system timer, NVIC, or system control block – Possibly restricted access to memory or peripherals ■ Privileged In this mode, software can use all the instructions and has access to all resources. In Thread mode, the CONTROL register (see page 71) controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 2.3.2 Stacks The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements July 24, 2011 57 Texas Instruments-Production Data The Cortex-M3 Processor two stacks: the main stack and the process stack, with independent copies of the stack pointer (see the SP register on page 61). In Thread mode, the CONTROL register (see page 71) controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1 on page 58. Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use Processor Mode Use Privilege Level Thread Applications Privileged or unprivileged Stack Used Handler Exception handlers Always privileged a Main stack or process stack a Main stack a. See CONTROL (page 71). 2.3.3 Register Map Figure 2-3 on page 58 shows the Cortex-M3 register set. Table 2-2 on page 59 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. Figure 2-3. Cortex-M3 Register Set R0 R1 R2 Low registers R3 R4 R5 R6 General-purpose registers R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSR PSP‡ MSP‡ ‡ Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL CONTROL register 58 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 2-2. Processor Register Map Offset Type Reset - R0 R/W - Cortex General-Purpose Register 0 60 - R1 R/W - Cortex General-Purpose Register 1 60 - R2 R/W - Cortex General-Purpose Register 2 60 - R3 R/W - Cortex General-Purpose Register 3 60 - R4 R/W - Cortex General-Purpose Register 4 60 - R5 R/W - Cortex General-Purpose Register 5 60 - R6 R/W - Cortex General-Purpose Register 6 60 - R7 R/W - Cortex General-Purpose Register 7 60 - R8 R/W - Cortex General-Purpose Register 8 60 - R9 R/W - Cortex General-Purpose Register 9 60 - R10 R/W - Cortex General-Purpose Register 10 60 - R11 R/W - Cortex General-Purpose Register 11 60 - R12 R/W - Cortex General-Purpose Register 12 60 - SP R/W - Stack Pointer 61 - LR R/W 0xFFFF.FFFF Link Register 62 - PC R/W - Program Counter 63 - PSR R/W 0x0100.0000 Program Status Register 64 - PRIMASK R/W 0x0000.0000 Priority Mask Register 68 - FAULTMASK R/W 0x0000.0000 Fault Mask Register 69 - BASEPRI R/W 0x0000.0000 Base Priority Mask Register 70 - CONTROL R/W 0x0000.0000 Control Register 71 2.3.4 Description See page Name Register Descriptions This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 58. The core registers are not memory mapped and are accessed by register name rather than offset. Note: The register type shown in the register descriptions refers to type during program execution in Thread mode and Handler mode. Debug access can differ. July 24, 2011 59 Texas Instruments-Production Data The Cortex-M3 Processor Register 1: Cortex General-Purpose Register 0 (R0) Register 2: Cortex General-Purpose Register 1 (R1) Register 3: Cortex General-Purpose Register 2 (R2) Register 4: Cortex General-Purpose Register 3 (R3) Register 5: Cortex General-Purpose Register 4 (R4) Register 6: Cortex General-Purpose Register 5 (R5) Register 7: Cortex General-Purpose Register 6 (R6) Register 8: Cortex General-Purpose Register 7 (R7) Register 9: Cortex General-Purpose Register 8 (R8) Register 10: Cortex General-Purpose Register 9 (R9) Register 11: Cortex General-Purpose Register 10 (R10) Register 12: Cortex General-Purpose Register 11 (R11) Register 13: Cortex General-Purpose Register 12 (R12) The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Cortex General-Purpose Register 0 (R0) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - DATA Type Reset DATA Type Reset Bit/Field Name Type Reset 31:0 DATA R/W - Description Register data. 60 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 14: Stack Pointer (SP) The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode. Stack Pointer (SP) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - SP Type Reset SP Type Reset Bit/Field Name Type Reset 31:0 SP R/W - Description This field is the address of the stack pointer. July 24, 2011 61 Texas Instruments-Production Data The Cortex-M3 Processor Register 15: Link Register (LR) The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. LR can be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 88 for the values and description. Link Register (LR) Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 LINK Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 LINK Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 LINK R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF This field is the return address. 62 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 16: Program Counter (PC) The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode. Program Counter (PC) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - PC Type Reset PC Type Reset Bit/Field Name Type Reset 31:0 PC R/W - Description This field is the current program address. July 24, 2011 63 Texas Instruments-Production Data The Cortex-M3 Processor Register 17: Program Status Register (PSR) Note: This register is also referred to as xPSR. The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions: ■ Application Program Status Register (APSR), bits 31:27, ■ Execution Program Status Register (EPSR), bits 26:24, 15:10 ■ Interrupt Program Status Register (IPSR), bits 6:0 The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be accessed in either privileged or unprivileged mode. APSR contains the current state of the condition flags from previous instruction executions. EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see “Exception Entry and Return” on page 86). IPSR contains the exception type number of the current Interrupt Service Routine (ISR). These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. page 64 shows the possible register combinations for the PSR. See the MRS and MSR instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual for more information about how to access the program status registers. Table 2-3. PSR Register Combinations Register Type PSR R/W Combination APSR, EPSR, and IPSR IEPSR RO EPSR and IPSR a, b a APSR and IPSR b APSR and EPSR IAPSR R/W EAPSR R/W a. The processor ignores writes to the IPSR bits. b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. Program Status Register (PSR) Type R/W, reset 0x0100.0000 Type Reset 31 30 29 28 27 N Z C V Q 26 25 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 15 14 13 12 11 10 9 ICI / IT ICI / IT Type Reset RO 0 RO 0 RO 0 24 23 22 21 20 THUMB RO 1 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 reserved RO 0 RO 0 RO 0 RO 0 RO 0 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 reserved ISRNUM RO 0 RO 0 64 RO 0 RO 0 RO 0 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 31 N R/W 0 Description APSR Negative or Less Flag Value Description 1 The previous operation result was negative or less than. 0 The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessing PSR or APSR. 30 Z R/W 0 APSR Zero Flag Value Description 1 The previous operation result was zero. 0 The previous operation result was non-zero. The value of this bit is only meaningful when accessing PSR or APSR. 29 C R/W 0 APSR Carry or Borrow Flag Value Description 1 The previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. 0 The previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. The value of this bit is only meaningful when accessing PSR or APSR. 28 V R/W 0 APSR Overflow Flag Value Description 1 The previous operation resulted in an overflow. 0 The previous operation did not result in an overflow. The value of this bit is only meaningful when accessing PSR or APSR. 27 Q R/W 0 APSR DSP Overflow and Saturation Flag Value Description 1 DSP Overflow or saturation has occurred. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. July 24, 2011 65 Texas Instruments-Production Data The Cortex-M3 Processor Bit/Field Name Type Reset 26:25 ICI / IT RO 0x0 Description EPSR ICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 24 THUMB RO 1 EPSR Thumb State This bit indicates the Thumb state and should always be set. The following can clear the THUMB bit: ■ The BLX, BX and POP{PC} instructions ■ Restoration from the stacked xPSR value on an exception return ■ Bit 0 of the vector value on an exception entry Attempting to execute instructions when this bit is clear results in a fault or lockup. See “Lockup” on page 90 for more information. The value of this bit is only meaningful when accessing PSR or EPSR. 23:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:10 ICI / IT RO 0x0 EPSR ICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When an interrupt occurs during the execution of an LDM, STM, PUSH or POP instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. When EPSR holds the ICI execution state, bits 11:10 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 9:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 66 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 6:0 ISRNUM RO 0x00 IPSR ISR Number This field contains the exception type number of the current Interrupt Service Routine (ISR). Value Description 0x00 Thread mode 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x46 Interrupt Vector 54 0x47-0x7F Reserved See “Exception Types” on page 81 for more information. The value of this field is only meaningful when accessing PSR or IPSR. July 24, 2011 67 Texas Instruments-Production Data The Cortex-M3 Processor Register 18: Priority Mask Register (PRIMASK) The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M3 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 81. Priority Mask Register (PRIMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PRIMASK R/W 0 RO 0 PRIMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority. 0 No effect. 68 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 19: Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the Cortex™-M3 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 81. Fault Mask Register (FAULTMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 FAULTMASK R/W 0 RO 0 FAULTMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI. 0 No effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. July 24, 2011 69 Texas Instruments-Production Data The Cortex-M3 Processor Register 20: Base Priority Mask Register (BASEPRI) The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. For more information on exception priority levels, see “Exception Types” on page 81. Base Priority Mask Register (BASEPRI) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset BASEPRI RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:5 BASEPRI R/W 0x0 R/W 0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Base Priority Any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. The PRIMASK register can be used to mask all exceptions with programmable priority levels. Higher priority exceptions have lower priority levels. Value Description 4:0 reserved RO 0x0 0x0 All exceptions are unmasked. 0x1 All exceptions with priority level 1-7 are masked. 0x2 All exceptions with priority level 2-7 are masked. 0x3 All exceptions with priority level 3-7 are masked. 0x4 All exceptions with priority level 4-7 are masked. 0x5 All exceptions with priority level 5-7 are masked. 0x6 All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 70 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 21: Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. This register is only accessible in privileged mode. Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 88). In an OS environment, threads running in Thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex™-M3 Instruction Set Technical User's Manual, or perform an exception return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 88. Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the Cortex™-M3 Instruction Set Technical User's Manual. Control Register (CONTROL) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 ASP TMPL RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 ASP R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Active Stack Pointer Value Description 1 PSP is the current stack pointer. 0 MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. 0 TMPL R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. July 24, 2011 71 Texas Instruments-Production Data The Cortex-M3 Processor 2.3.5 Exceptions and Interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See “Exception Entry and Return” on page 86 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” on page 97 for more information. 2.3.6 Data Types The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. See “Memory Regions, Types and Attributes” on page 74 for more information. 2.4 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map for the LM3S1F11 controller is provided in Table 2-4 on page 72. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see “Bit-Banding” on page 77). The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers (see “Cortex-M3 Peripherals” on page 96). Note: Within the memory map, all reserved space returns a bus fault when read or written. Table 2-4. Memory Map Start End Description For details, see page ... 0x0000.0000 0x0005.FFFF On-chip Flash 298 0x0006.0000 0x00FF.FFFF Reserved - 0x0100.0000 0x1FFF.FFFF Reserved for ROM 296 0x2000.0000 0x2000.BFFF Bit-banded on-chip SRAM 296 0x2000.C000 0x21FF.FFFF Reserved - 0x2200.0000 0x2217.FFFF Bit-band alias of bit-banded on-chip SRAM starting at 0x2000.0000 296 0x2218.0000 0x3FFF.FFFF Reserved - 0x4000.0000 0x4000.0FFF Watchdog timer 0 580 0x4000.1000 0x4000.1FFF Watchdog timer 1 580 0x4000.2000 0x4000.3FFF Reserved - 0x4000.4000 0x4000.4FFF GPIO Port A 413 0x4000.5000 0x4000.5FFF GPIO Port B 413 0x4000.6000 0x4000.6FFF GPIO Port C 413 Memory FiRM Peripherals 72 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x4000.7000 0x4000.7FFF GPIO Port D 413 0x4000.8000 0x4000.8FFF SSI0 752 0x4000.9000 0x4000.9FFF SSI1 752 0x4000.A000 0x4000.BFFF Reserved - 0x4000.C000 0x4000.CFFF UART0 690 0x4000.D000 0x4000.DFFF UART1 690 0x4000.E000 0x4000.EFFF UART2 690 0x4000.F000 0x4001.FFFF Reserved - 0x4002.0FFF I2C 0 796 0x4002.1000 0x4002.1FFF I2C 796 0x4002.2000 0x4002.3FFF Reserved - 0x4002.4000 0x4002.4FFF GPIO Port E 413 0x4002.5000 0x4002.5FFF GPIO Port F 413 0x4002.6000 0x4002.6FFF GPIO Port G 413 0x4002.7000 0x4002.7FFF GPIO Port H 413 0x4002.8000 0x4002.FFFF Reserved - 0x4003.0000 0x4003.0FFF Timer 0 546 0x4003.1000 0x4003.1FFF Timer 1 546 0x4003.2000 0x4003.2FFF Timer 2 546 0x4003.3000 0x4003.3FFF Timer 3 546 0x4003.4000 0x4003.7FFF Reserved - 0x4003.8000 0x4003.8FFF ADC0 621 0x4003.9000 0x4003.BFFF Reserved - 0x4003.C000 0x4003.CFFF Analog Comparators 817 0x4003.D000 0x4003.DFFF GPIO Port J 413 0x4003.E000 0x4005.7FFF Reserved - 0x4005.8000 0x4005.8FFF GPIO Port A (AHB aperture) 413 0x4005.9000 0x4005.9FFF GPIO Port B (AHB aperture) 413 0x4005.A000 0x4005.AFFF GPIO Port C (AHB aperture) 413 0x4005.B000 0x4005.BFFF GPIO Port D (AHB aperture) 413 0x4005.C000 0x4005.CFFF GPIO Port E (AHB aperture) 413 0x4005.D000 0x4005.DFFF GPIO Port F (AHB aperture) 413 0x4005.E000 0x4005.EFFF GPIO Port G (AHB aperture) 413 0x4005.F000 0x4005.FFFF GPIO Port H (AHB aperture) 413 0x4006.0000 0x4006.0FFF GPIO Port J (AHB aperture) 413 0x4006.1000 0x400C.FFFF Reserved - 0x400D.0000 0x400D.0FFF EPI 0 487 0x400D.1000 0x400F.BFFF Reserved - 0x400F.C000 0x400F.CFFF Hibernation Module 278 0x400F.D000 0x400F.DFFF Flash memory control 304 Peripherals 0x4002.0000 1 July 24, 2011 73 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x400F.E000 0x400F.EFFF System control 192 0x400F.F000 0x400F.FFFF µDMA 361 0x4010.0000 0x41FF.FFFF Reserved - 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - 0x4400.0000 0x5FFF.FFFF Reserved - 0x6000.0000 0xDFFF.FFFF EPI0 mapped peripheral and RAM - 0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 55 0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 55 0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 55 0xE000.3000 0xE000.DFFF Reserved - 0xE000.E000 0xE000.EFFF Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU) 80 0xE000.F000 0xE003.FFFF Reserved - 0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 56 0xE004.1000 0xFFFF.FFFF Reserved - Private Peripheral Bus 2.4.1 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: ■ Normal: The processor can re-order transactions for efficiency and perform speculative reads. ■ Device: The processor preserves transaction order relative to other transactions to Device or Strongly Ordered memory. ■ Strongly Ordered: The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region. 2.4.2 Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions (see “Software Ordering of Memory Accesses” on page 75). However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either 74 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always observed before A2. 2.4.3 Behavior of Memory Accesses Table 2-5 on page 75 shows the behavior of accesses to each region in the memory map. See “Memory Regions, Types and Attributes” on page 74 for more information on memory types and the XN attribute. Stellaris devices may have reserved memory areas within the address ranges shown below (refer to Table 2-4 on page 72 for more information). Table 2-5. Memory Access Behavior Address Range Memory Region Memory Type Execute Never (XN) Description 0x0000.0000 - 0x1FFF.FFFF Code Normal - This executable region is for program code. Data can also be stored here. 0x2000.0000 - 0x3FFF.FFFF SRAM Normal - This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 77). 0x4000.0000 - 0x5FFF.FFFF Peripheral Device XN This region includes bit band and bit band alias areas (see Table 2-7 on page 77). 0x6000.0000 - 0x9FFF.FFFF External RAM Normal - This executable region is for data. 0xA000.0000 - 0xDFFF.FFFF External device Device XN This region is for external device memory. 0xE000.0000- 0xE00F.FFFF Private peripheral bus Strongly Ordered XN This region includes the NVIC, system timer, and system control block. 0xE010.0000- 0xFFFF.FFFF Reserved - - - The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region because the Cortex-M3 has separate buses that can perform instruction fetches and data accesses simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit (MPU)” on page 99. The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. 2.4.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: ■ The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. ■ The processor has multiple bus interfaces. ■ Memory or devices in the memory map have different wait states. ■ Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” on page 74 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is July 24, 2011 75 Texas Instruments-Production Data The Cortex-M3 Processor critical, software must include memory barrier instructions to force that ordering. The Cortex-M3 has the following memory barrier instructions: ■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. ■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. ■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. Memory barrier instructions can be used in the following situations: ■ MPU programming – If the MPU settings are changed and the change must be effective on the very next instruction, use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. – Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not required. ■ Vector table If the program changes an entry in the vector table and then enables the corresponding exception, use a DMB instruction between the operations. The DMB instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. ■ Self-modifying code If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. The change then takes effect on completion of the DSB instruction. Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use of DMB instructions. For more information on the memory barrier instructions, see the Cortex™-M3 Instruction Set Technical User's Manual. 76 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 2.4.5 Bit-Banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-6 on page 77. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region, as shown in Table 2-7 on page 77. For the specific address range of the bit-band regions, see Table 2-4 on page 72. Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region. A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. Table 2-6. SRAM Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses 0x2000.0000 - 0x200F.FFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. 0x2200.0000 - 0x23FF.FFFF SRAM bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. Table 2-7. Peripheral Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses 0x4000.0000 - 0x400F.FFFF Peripheral bit-band region Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. 0x4200.0000 - 0x43FF.FFFF Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where: bit_word_offset The position of the target bit in the bit-band memory region. bit_word_addr The address of the word in the alias memory region that maps to the targeted bit. bit_band_base The starting address of the alias region. byte_offset The number of the byte in the bit-band region that contains the targeted bit. July 24, 2011 77 Texas Instruments-Production Data The Cortex-M3 Processor bit_number The bit position, 0-7, of the targeted bit. Figure 2-4 on page 78 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: ■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4) ■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4) ■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) Figure 2-4. Bit-Band Mapping 32-MB Alias Region 0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0 0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0004 0x2200.0000 7 3 1-MB SRAM Bit-Band Region 7 6 5 4 3 2 1 0 7 6 0x200F.FFFF 7 6 5 4 3 2 0x2000.0003 2.4.5.1 5 4 3 2 1 0 7 6 0x200F.FFFE 1 0 7 6 5 4 3 2 5 4 3 2 1 0 6 0x200F.FFFD 1 0x2000.0002 0 7 6 5 4 3 2 0x2000.0001 5 4 2 1 0 1 0 0x200F.FFFC 1 0 7 6 5 4 3 2 0x2000.0000 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. 78 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set. 2.4.5.2 Directly Accessing a Bit-Band Region “Behavior of Memory Accesses” on page 75 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 2.4.6 Data Storage The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-5 on page 79 illustrates how data is stored. Figure 2-5. Data Storage Memory 7 Register 0 31 2.4.7 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte Synchronization Primitives The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. A pair of synchronization primitives consists of: ■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. ■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write is performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: ■ The word instructions LDREX and STREX ■ The halfword instructions LDREXH and STREXH July 24, 2011 79 Texas Instruments-Production Data The Cortex-M3 Processor ■ The byte instructions LDREXB and STREXB Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and test the returned status bit. If the status bit is clear, the read-modify-write completed successfully; if the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1. The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has executed a Load-Exclusive instruction. The processor removes its exclusive access tag if: ■ It executes a CLREX instruction. ■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds. ■ An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see the Cortex™-M3 Instruction Set Technical User's Manual. 2.5 Exception Model The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 2-8 on page 83 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 37 interrupts (listed in Table 2-9 on page 83). Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting 80 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller priority levels into preemption priorities and subpriorities. All the interrupt registers are described in “Nested Vectored Interrupt Controller (NVIC)” on page 97. Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the programmable priorities. Important: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC)” on page 97 for more information on exceptions and interrupts. 2.5.1 Exception States Each exception is in one of the following states: ■ Inactive. The exception is not active and not pending. ■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. ■ Active. An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. ■ Active and Pending. The exception is being serviced by the processor, and there is a pending exception from the same source. 2.5.2 Exception Types The exception types are: ■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. ■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. ■ Hard Fault. A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. July 24, 2011 81 Texas Instruments-Production Data The Cortex-M3 Processor ■ Memory Management Fault. A memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. The MPU or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. ■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. ■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. ■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. ■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception is only active when enabled. This exception does not activate if it is a lower priority than the current activation. ■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using the Interrupt Control and State (INTCTRL) register. ■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor can use this exception as system tick. ■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 83 lists the interrupts on the LM3S1F11 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 2-8 on page 83 shows as having configurable priority (see the SYSHNDCTRL register on page 140 and the DIS0 register on page 113). For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” on page 88. 82 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 2-8. Exception Types Exception Type a Vector Number Priority Vector Address or b Offset - 0 - 0x0000.0000 Stack top is loaded from the first entry of the vector table on reset. Reset 1 -3 (highest) 0x0000.0004 Asynchronous Non-Maskable Interrupt (NMI) 2 -2 0x0000.0008 Asynchronous Hard Fault 3 -1 0x0000.000C - c 0x0000.0010 Synchronous c 0x0000.0014 Synchronous when precise and asynchronous when imprecise c Synchronous Memory Management 4 programmable Bus Fault 5 programmable Usage Fault 6 programmable 0x0000.0018 7-10 - - - 0x0000.002C Synchronous c 0x0000.0030 Synchronous c 0x0000.0038 Asynchronous c 0x0000.003C Asynchronous SVCall 11 programmable 12 programmable - 13 - PendSV 14 programmable 15 Interrupts - programmable 16 and above Reserved c Debug Monitor SysTick Activation d programmable Reserved 0x0000.0040 and above Asynchronous a. 0 is the default priority for all the programmable priorities. b. See “Vector Table” on page 84. c. See SYSPRI1 on page 137. d. See PRIn registers on page 121. Table 2-9. Interrupts Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 0-15 - 0x0000.0000 0x0000.003C 16 0 0x0000.0040 GPIO Port A 17 1 0x0000.0044 GPIO Port B 18 2 0x0000.0048 GPIO Port C 19 3 0x0000.004C GPIO Port D 20 4 0x0000.0050 GPIO Port E 21 5 0x0000.0054 UART0 22 6 0x0000.0058 UART1 23 7 0x0000.005C SSI0 24 8 0x0000.0060 I2C0 25-29 9-13 - 30 14 0x0000.0078 ADC0 Sequence 0 31 15 0x0000.007C ADC0 Sequence 1 32 16 0x0000.0080 ADC0 Sequence 2 33 17 0x0000.0084 ADC0 Sequence 3 34 18 0x0000.0088 Watchdog Timers 0 and 1 35 19 0x0000.008C Timer 0A Processor exceptions Reserved July 24, 2011 83 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-9. Interrupts (continued) 2.5.3 Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 36 20 0x0000.0090 Timer 0B 37 21 0x0000.0094 Timer 1A 38 22 0x0000.0098 Timer 1B 39 23 0x0000.009C Timer 2A 40 24 0x0000.00A0 Timer 2B 41 25 0x0000.00A4 Analog Comparator 0 42 26 0x0000.00A8 Analog Comparator 1 43 27 - 44 28 0x0000.00B0 System Control 45 29 0x0000.00B4 Flash Memory Control 46 30 0x0000.00B8 GPIO Port F 47 31 0x0000.00BC GPIO Port G 48 32 0x0000.00C0 GPIO Port H 49 33 0x0000.00C4 UART2 50 34 0x0000.00C8 SSI1 51 35 0x0000.00CC Timer 3A 52 36 0x0000.00D0 Timer 3B 53 37 0x0000.00D4 I2C1 54-58 38-42 - 59 43 0x0000.00EC 60-61 44-45 - 62 46 0x0000.00F8 µDMA Software µDMA Error Reserved Reserved Hibernation Module Reserved 63 47 0x0000.00FC 64-68 48-52 - 69 53 0x0000.0114 EPI 70 54 0x0000.0118 GPIO Port J Reserved Exception Handlers The processor handles exceptions using: ■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. ■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. ■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. 2.5.4 Vector Table The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in Table 2-8 on page 83. Figure 2-6 on page 85 shows the order of the exception 84 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code Figure 2-6. Vector Table Exception number IRQ number 70 54 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Offset 0x0118 . . . 0x004C 0x0048 0x0044 0x0040 0x003C 0x0038 12 11 Vector IRQ54 . . . IRQ2 IRQ1 IRQ0 Systick PendSV Reserved Reserved for Debug -5 10 0x002C 9 SVCall Reserved 8 7 6 -10 5 -11 4 -12 3 -13 2 -14 1 0x0018 0x0014 0x0010 0x000C 0x0008 0x0004 0x0000 Usage fault Bus fault Memory management fault Hard fault NMI Reset Initial SP value On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000.0200 to 0x3FFF.FE00 (see “Vector Table” on page 84). Note that when configuring the VTABLE register, the offset must be aligned on a 512-byte boundary. 2.5.5 Exception Priorities As Table 2-8 on page 83 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see page 137 and page 121. Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. July 24, 2011 85 Texas Instruments-Production Data The Cortex-M3 Processor For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 2.5.6 Interrupt Priority Grouping To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields: ■ An upper field that defines the group priority ■ A lower field that defines a subpriority within the group Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see page 131. 2.5.7 Exception Entry and Return Descriptions of exception handling use the following terms: ■ Preemption. When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” on page 86 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” on page 87 more information. ■ Return. Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” on page 88 for more information. ■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. ■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late 86 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller arrival because the state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.5.7.1 Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers (see PRIMASK on page 68, FAULTMASK on page 69, and BASEPRI on page 70). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to as stack frame. Figure 2-7. Exception Stack Frame ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack IRQ top of stack Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The stack frame includes the return address, which is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. July 24, 2011 87 Texas Instruments-Production Data The Cortex-M3 Processor 2.5.7.2 Exception Return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: ■ An LDM or POP instruction that loads the PC ■ A BX instruction using any register ■ An LDR instruction with the PC as the destination EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest four bits of this value provide information on the return stack and processor mode. Table 2-10 on page 88 shows the EXC_RETURN values with a description of the exception return behavior. EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table 2-10. Exception Return Behavior EXC_RETURN[31:0] Description 0xFFFF.FFF0 Reserved 0xFFFF.FFF1 Return to Handler mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFF2 - 0xFFFF.FFF8 Reserved 0xFFFF.FFF9 Return to Thread mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFFA - 0xFFFF.FFFC Reserved 0xFFFF.FFFD Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. 0xFFFF.FFFE - 0xFFFF.FFFF 2.6 Reserved Fault Handling Faults are a subset of the exceptions (see “Exception Model” on page 80). The following conditions generate a fault: ■ A bus error on an instruction fetch or vector table load or a data access. ■ An internally detected error such as an undefined instruction or an attempt to change state with a BX instruction. ■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN). ■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region. 88 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 2.6.1 Fault Types Table 2-11 on page 89 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. See page 144 for more information about the fault status registers. Table 2-11. Faults Fault Handler Fault Status Register Bit Name Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) FORCED MPU or default memory mismatch on Memory management instruction access fault Memory Management Fault Status (MFAULTSTAT) IERR MPU or default memory mismatch on Memory management data access fault Memory Management Fault Status (MFAULTSTAT) DERR MPU or default memory mismatch on Memory management exception stacking fault Memory Management Fault Status (MFAULTSTAT) MSTKE MPU or default memory mismatch on Memory management exception unstacking fault Memory Management Fault Status (MFAULTSTAT) MUSTKE Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF Attempt to enter an invalid instruction Usage fault b set state Usage Fault Status (UFAULTSTAT) INVSTAT a Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0 a. Occurs on an access to an XN region even if the MPU is disabled. b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation. 2.6.2 Fault Escalation and Hard Faults All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on page 137). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on page 140). Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in “Exception Model” on page 80. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when: ■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. July 24, 2011 89 Texas Instruments-Production Data The Cortex-M3 Processor ■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. ■ An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. ■ A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: 2.6.3 Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-12 on page 90. Table 2-12. Fault Status and Fault Address Registers 2.6.4 Handler Status Register Name Address Register Name Register Description Hard fault Hard Fault Status (HFAULTSTAT) - page 150 Memory management Memory Management Fault Status fault (MFAULTSTAT) Memory Management Fault Address (MMADDR) page 144 Bus fault Bus Fault Status (BFAULTSTAT) Bus Fault Address (FAULTADDR) page 144 Usage fault Usage Fault Status (UFAULTSTAT) - page 144 page 151 page 152 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset or an NMI occurs. Note: 2.7 If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state. Power Management The Cortex-M3 processor sleep modes reduce power consumption: ■ Sleep mode stops the processor clock. ■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory. The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used (see page 133). For more information about the behavior of the sleep modes, see “System Control” on page 188. 90 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to Sleep mode and Deep-sleep mode. 2.7.1 Entering Sleep Modes This section describes the mechanisms software can use to put the processor into one of the sleep modes. The system can generate spurious wake-up events, for example a debug operation wakes up the processor. Therefore, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. 2.7.1.1 Wait for Interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 91). When the processor executes a WFI instruction, it stops executing instructions and enters sleep mode. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. 2.7.1.2 Wait for Event The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes a WFE instruction, it checks the event register. If the register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction. Typically, this situation occurs if an SEV instruction has been executed. Software cannot access this register directly. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. 2.7.1.3 Sleep-on-Exit If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution of an exception handler, it returns to Thread mode and immediately enters sleep mode. This mechanism can be used in applications that only require the processor to run when an exception occurs. 2.7.2 Wake Up from Sleep Mode The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode. 2.7.2.1 Wake Up from WFI or Sleep-on-Exit Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor clears PRIMASK. For more information about PRIMASK and FAULTMASK, see page 68 and page 69. 2.7.2.2 Wake Up from WFE The processor wakes up if it detects an exception with sufficient priority to cause exception entry. July 24, 2011 91 Texas Instruments-Production Data The Cortex-M3 Processor In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about SYSCTRL, see page 133. 2.8 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 92 lists the supported instructions. Note: In Table 2-13 on page 92: ■ ■ ■ ■ ■ Angle brackets, , enclose alternative forms of the operand Braces, {}, enclose optional operands The Operands column is not exhaustive Op2 is a flexible second operand that can be either a register or a constant Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual. Table 2-13. Cortex-M3 Instruction Summary Mnemonic Operands Brief Description Flags ADC, ADCS {Rd,} Rn, Op2 Add with carry N,Z,C,V ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V ADD, ADDW {Rd,} Rn , #imm12 Add N,Z,C,V ADR Rd, label Load PC-relative address - AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C ASR, ASRS Rd, Rm, Arithmetic shift right N,Z,C B label Branch - BFC Rd, #lsb, #width Bit field clear - BFI Rd, Rn, #lsb, #width Bit field insert - BIC, BICS {Rd,} Rn, Op2 Bit clear N,Z,C BKPT #imm Breakpoint - BL label Branch with link - BLX Rm Branch indirect with link - BX Rm Branch indirect - CBNZ Rn, label Compare and branch if non-zero - CBZ Rn, label Compare and branch if zero - CLREX - Clear exclusive - CLZ Rd, Rm Count leading zeros - CMN Rn, Op2 Compare negative N,Z,C,V CMP Rn, Op2 Compare N,Z,C,V CPSID i Change processor state, disable interrupts - CPSIE i Change processor state, enable interrupts - DMB - Data memory barrier - DSB - Data synchronization barrier - 92 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C ISB - Instruction synchronization barrier - IT - If-Then condition block - LDM Rn{!}, reglist Load multiple registers, increment after - LDMDB, LDMEA Rn{!}, reglist Load multiple registers, decrement before LDMFD, LDMIA Rn{!}, reglist Load multiple registers, increment after - LDR Rt, [Rn, #offset] Load register with word - LDRB, LDRBT Rt, [Rn, #offset] Load register with byte - LDRD Rt, Rt2, [Rn, #offset] Load register with two bytes - LDREX Rt, [Rn, #offset] Load register exclusive - LDREXB Rt, [Rn] Load register exclusive with byte - LDREXH Rt, [Rn] Load register exclusive with halfword - LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword - LDRSB, LDRSBT Rt, [Rn, #offset] Load register with signed byte - LDRSH, LDRSHT Rt, [Rn, #offset] Load register with signed halfword - LDRT Rt, [Rn, #offset] Load register with word - LSL, LSLS Rd, Rm, Logical shift left N,Z,C LSR, LSRS Rd, Rm, Logical shift right N,Z,C MLA Rd, Rn, Rm, Ra Multiply with accumulate, 32-bit result - MLS Rd, Rn, Rm, Ra Multiply and subtract, 32-bit result - MOV, MOVS Rd, Op2 Move N,Z,C MOV, MOVW Rd, #imm16 Move 16-bit constant N,Z,C MOVT Rd, #imm16 Move top - MRS Rd, spec_reg Move from special register to general register - MSR spec_reg, Rm Move from general register to special register N,Z,C,V MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z MVN, MVNS Rd, Op2 Move NOT N,Z,C NOP - No operation - ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C POP reglist Pop registers from stack - PUSH reglist Push registers onto stack - RBIT Rd, Rn Reverse bits - REV Rd, Rn Reverse byte order in a word - REV16 Rd, Rn Reverse byte order in each halfword - REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend - ROR, RORS Rd, Rm, Rotate right N,Z,C RRX, RRXS Rd, Rm Rotate right with extend N,Z,C July 24, 2011 - 93 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags RSB, RSBS {Rd,} Rn, Op2 Reverse subtract N,Z,C,V SBC, SBCS {Rd,} Rn, Op2 Subtract with carry N,Z,C,V SBFX Rd, Rn, #lsb, #width Signed bit field extract - SDIV {Rd,} Rn, Rm Signed divide - SEV - Send event - SMLAL RdLo, RdHi, Rn, Rm Signed multiply with accumulate (32x32+64), 64-bit result - SMULL RdLo, RdHi, Rn, Rm Signed multiply (32x32), 64-bit result - SSAT Rd, #n, Rm {,shift #s} Signed saturate Q STM Rn{!}, reglist Store multiple registers, increment after - STMDB, STMEA Rn{!}, reglist Store multiple registers, decrement before STMFD, STMIA Rn{!}, reglist Store multiple registers, increment after - STR Rt, [Rn {, #offset}] Store register word - STRB, STRBT Rt, [Rn {, #offset}] Store register byte - STRD Rt, Rt2, [Rn {, #offset}] Store register two words - STREX Rt, Rt, [Rn {, #offset}] Store register exclusive - STREXB Rd, Rt, [Rn] Store register exclusive byte - STREXH Rd, Rt, [Rn] Store register exclusive halfword - STRH, STRHT Rt, [Rn {, #offset}] Store register halfword - STRSB, STRSBT Rt, [Rn {, #offset}] Store register signed byte - STRSH, STRSHT Rt, [Rn {, #offset}] Store register signed halfword - STRT Rt, [Rn {, #offset}] Store register word - SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V SUB, SUBW {Rd,} Rn, #imm12 Subtract 12-bit constant N,Z,C,V SVC #imm Supervisor call - SXTB {Rd,} Rm {,ROR #n} Sign extend a byte - SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword - TBB [Rn, Rm] Table branch byte - TBH [Rn, Rm, LSL #1] Table branch halfword - TEQ Rn, Op2 Test equivalence N,Z,C TST Rn, Op2 Test N,Z,C UBFX Rd, Rn, #lsb, #width Unsigned bit field extract - UDIV {Rd,} Rn, Rm Unsigned divide - UMLAL RdLo, RdHi, Rn, Rm Unsigned multiply with accumulate (32x32+32+32), 64-bit result - UMULL RdLo, RdHi, Rn, Rm Unsigned multiply (32x 2), 64-bit result - USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q UXTB {Rd,} Rm, {,ROR #n} Zero extend a Byte - UXTH {Rd,} Rm, {,ROR #n} Zero extend a Halfword - USAT Rd, #n, Rm {,shift #s} Unsigned saturate Q UXTB {Rd,} Rm {,ROR #n} Zero extend a byte - 94 - July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword - WFE - Wait for event - WFI - Wait for interrupt - July 24, 2011 95 Texas Instruments-Production Data Cortex-M3 Peripherals 3 Cortex-M3 Peripherals ® This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals, including: ■ SysTick (see page 96) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. ■ Nested Vectored Interrupt Controller (NVIC) (see page 97) – Facilitates low-latency exception and interrupt handling – Controls power management – Implements system control registers ■ System Control Block (SCB) (see page 99) Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. ■ Memory Protection Unit (MPU) (see page 99) Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. Table 3-1 on page 96 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed. Table 3-1. Core Peripheral Register Regions Address Core Peripheral Description (see page ...) 0xE000.E010-0xE000.E01F System Timer 96 0xE000.E100-0xE000.E4EF Nested Vectored Interrupt Controller 97 System Control Block 99 Memory Protection Unit 99 0xE000.EF00-0xE000.EF03 0xE000.E008-0xE000.E00F 0xE000.ED00-0xE000.ED3F 0xE000.ED90-0xE000.EDB8 3.1 Functional Description This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals: SysTick, NVIC, SCB and MPU. 3.1.1 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. 96 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter used to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNT bit in the STCTRL control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. The timer consists of three registers: ■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the counter's wrap value. ■ SysTick Current Value (STCURRENT): The current value of the counter. When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter reaches zero, the COUNT status bit is set. The COUNT bit clears on reads. Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers. Note: 3.1.2 When the processor is halted for debugging, the counter does not decrement. Nested Vectored Interrupt Controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ■ 37 interrupts. ■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ■ Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). July 24, 2011 97 Texas Instruments-Production Data Cortex-M3 Peripherals The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. 3.1.2.1 Level-Sensitive and Pulse Interrupts The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts” on page 98 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 3.1.2.2 Hardware and Software Control of Interrupts The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: ■ The NVIC detects that the interrupt signal is High and the interrupt is not active. ■ The NVIC detects a rising edge on the interrupt signal. ■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit in the PEND0 register on page 115 or SWTRIG on page 123. A pending interrupt remains pending until one of the following: ■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. ■ Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. 98 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller – For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. 3.1.3 System Control Block (SCB) The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. 3.1.4 Memory Protection Unit (MPU) This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines eight separate memory regions, 0-7, and a background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” on page 74 for more information). Table 3-2 on page 99 shows the possible MPU region attributes. See the section called “MPU Configuration for a Stellaris Microcontroller” on page 103 for guidelines for programming a microcontroller implementation. Table 3-2. Memory Attributes Summary Memory Type Description Strongly Ordered All accesses to Strongly Ordered memory occur in program order. Device Memory-mapped peripherals Normal Normal memory To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: ■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. July 24, 2011 99 Texas Instruments-Production Data Cortex-M3 Peripherals The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. 3.1.4.1 Updating an MPU Region To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can be programmed separately or with a multiple-word write to program all of these registers. You can use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using an STM instruction. Updating an MPU Region Using Separate Words This example simple code configures one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER STR R1, [R0, #0x0] STR R4, [R0, #0x4] STRH R2, [R0, #0x8] STRH R3, [R0, #0xA] ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Region Base Address Region Size and Enable Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER STR R1, [R0, #0x0] BIC R2, R2, #1 STRH R2, [R0, #0x8] STR R4, [R0, #0x4] STRH R3, [R0, #0xA] ORR R2, #1 STRH R2, [R0, #0x8] ; ; ; ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Disable Region Size and Enable Region Base Address Region Attribute Enable Region Size and Enable Software must use memory barrier instructions: ■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings. ■ After MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region. 100 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is required after changing MPU settings, such as at the end of context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISB is not required. Updating an MPU Region Using Multi-Word Writes The MPU can be programmed directly using multi-word writes, depending how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region number, address, attribute, size and enable This operation can be done in two words for pre-packed information, meaning that the MPU Region Base Address (MPUBASE) register (see page 157) contains the required region number and has the VALID bit set. This method can be used when the data is statically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and region number combined ; with VALID (bit 4) set STR R2, [R0, #0x4] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0,=MPUBASE ; 0xE000ED9C, MPU Region Base register STM R0, {R1-R2} ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 159) to disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the most-significant bit controls the last subregion. Disabling a subregion means another region July 24, 2011 101 Texas Instruments-Production Data Cortex-M3 Peripherals overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be configured to 0x00, otherwise the MPU behavior is unpredictable. Example of SRD Use Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 102 shows. Figure 3-1. SRD Use Example Region 2, with subregions Region 1 Base address of both regions 3.1.4.2 Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB Disabled subregion 64KB Disabled subregion 0 MPU Access Permission Attributes The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 3-3 on page 102 shows the encodings for the TEX, C, B, and S access permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M3 does not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration for a Stellaris Microcontroller” on page 103 for information on programming the MPU for Stellaris implementations. Table 3-3. TEX, S, C, and B Bit Field Encoding TEX S 000b x C B Memory Type Shareability Other Attributes a 0 0 Strongly Ordered Shareable - a - 000 x 0 1 Device Shareable 000 0 1 0 Normal Not shareable 000 1 1 0 Normal Shareable 000 0 1 1 Normal Not shareable 000 1 1 1 Normal Shareable 001 0 0 0 Normal Not shareable 001 1 001 x Outer and inner write-through. No write allocate. 0 0 Normal Shareable Outer and inner noncacheable. a 0 1 Reserved encoding - - a 001 x 1 0 Reserved encoding - - 001 0 1 1 Normal Not shareable 001 1 1 1 Normal Shareable Outer and inner write-back. Write and read allocate. 102 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 3-3. TEX, S, C, and B Bit Field Encoding (continued) TEX S Other Attributes 0 0 Device Not shareable Nonshared Device. a 0 1 Reserved encoding - - x Shareability x Memory Type 010 B 010 C a a a 010 x 1 x Reserved encoding - - 1BB 0 A A Normal Not shareable 1BB 1 A A Normal Shareable Cached memory (BB = outer policy, AA = inner policy). See Table 3-4 for the encoding of the AA and BB bits. a. The MPU ignores the value of this bit. Table 3-4 on page 103 shows the cache policy for memory attribute encodings with a TEX value in the range of 0x4-0x7. Table 3-4. Cache Policy for Memory Attribute Encoding Encoding, AA or BB Corresponding Cache Policy 00 Non-cacheable 01 Write back, write and read allocate 10 Write through, no write allocate 11 Write back, no write allocate Table 3-5 on page 103 shows the AP encodings in the MPUATTR register that define the access permissions for privileged and unprivileged software. Table 3-5. AP Bit Field Encoding AP Bit Field Privileged Permissions Unprivileged Permissions Description 000 No access No access All accesses generate a permission fault. 001 R/W No access Access from privileged software only. 010 R/W RO Writes by unprivileged software generate a permission fault. 011 R/W R/W Full access. 100 Unpredictable Unpredictable Reserved. 101 RO No access Reads by privileged software only. 110 RO RO Read-only, by privileged or unprivileged software. 111 RO RO Read-only, by privileged or unprivileged software. MPU Configuration for a Stellaris Microcontroller Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 103. Table 3-6. Memory Region Attributes for Stellaris Microcontrollers Memory Region TEX S C B Memory Type and Attributes Flash memory 000b 0 1 0 Normal memory, non-shareable, write-through Internal SRAM 000b 1 1 0 Normal memory, shareable, write-through July 24, 2011 103 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-6. Memory Region Attributes for Stellaris Microcontrollers (continued) Memory Region TEX S C B Memory Type and Attributes External SRAM 000b 1 1 1 Normal memory, shareable, write-back, write-allocate Peripherals 000b 1 0 1 Device memory, shareable In current Stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. 3.1.4.3 MPU Mismatch When an access violates the MPU permissions, the processor generates a memory management fault (see “Exceptions and Interrupts” on page 72 for more information). The MFAULTSTAT register indicates the cause of the fault. See page 144 for more information. 3.2 Register Map Table 3-7 on page 104 lists the Cortex-M3 Peripheral SysTick, NVIC, SCB, and MPU registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note: Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table 3-7. Peripherals Register Map Offset Name Type Reset Description See page System Timer (SysTick) Registers 0x010 STCTRL R/W 0x0000.0004 SysTick Control and Status Register 107 0x014 STRELOAD R/W 0x0000.0000 SysTick Reload Value Register 109 0x018 STCURRENT R/WC 0x0000.0000 SysTick Current Value Register 110 Nested Vectored Interrupt Controller (NVIC) Registers 0x100 EN0 R/W 0x0000.0000 Interrupt 0-31 Set Enable 111 0x104 EN1 R/W 0x0000.0000 Interrupt 32-54 Set Enable 112 0x180 DIS0 R/W 0x0000.0000 Interrupt 0-31 Clear Enable 113 0x184 DIS1 R/W 0x0000.0000 Interrupt 32-54 Clear Enable 114 0x200 PEND0 R/W 0x0000.0000 Interrupt 0-31 Set Pending 115 0x204 PEND1 R/W 0x0000.0000 Interrupt 32-54 Set Pending 116 0x280 UNPEND0 R/W 0x0000.0000 Interrupt 0-31 Clear Pending 117 0x284 UNPEND1 R/W 0x0000.0000 Interrupt 32-54 Clear Pending 118 0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0-31 Active Bit 119 0x304 ACTIVE1 RO 0x0000.0000 Interrupt 32-54 Active Bit 120 0x400 PRI0 R/W 0x0000.0000 Interrupt 0-3 Priority 121 104 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 3-7. Peripherals Register Map (continued) Description See page Offset Name Type Reset 0x404 PRI1 R/W 0x0000.0000 Interrupt 4-7 Priority 121 0x408 PRI2 R/W 0x0000.0000 Interrupt 8-11 Priority 121 0x40C PRI3 R/W 0x0000.0000 Interrupt 12-15 Priority 121 0x410 PRI4 R/W 0x0000.0000 Interrupt 16-19 Priority 121 0x414 PRI5 R/W 0x0000.0000 Interrupt 20-23 Priority 121 0x418 PRI6 R/W 0x0000.0000 Interrupt 24-27 Priority 121 0x41C PRI7 R/W 0x0000.0000 Interrupt 28-31 Priority 121 0x420 PRI8 R/W 0x0000.0000 Interrupt 32-35 Priority 121 0x424 PRI9 R/W 0x0000.0000 Interrupt 36-39 Priority 121 0x428 PRI10 R/W 0x0000.0000 Interrupt 40-43 Priority 121 0x42C PRI11 R/W 0x0000.0000 Interrupt 44-47 Priority 121 0x430 PRI12 R/W 0x0000.0000 Interrupt 48-51 Priority 121 0x434 PRI13 R/W 0x0000.0000 Interrupt 52-54 Priority 121 0xF00 SWTRIG WO 0x0000.0000 Software Trigger Interrupt 123 System Control Block (SCB) Registers 0x008 ACTLR R/W 0x0000.0000 Auxiliary Control 124 0xD00 CPUID RO 0x412F.C230 CPU ID Base 126 0xD04 INTCTRL R/W 0x0000.0000 Interrupt Control and State 127 0xD08 VTABLE R/W 0x0000.0000 Vector Table Offset 130 0xD0C APINT R/W 0xFA05.0000 Application Interrupt and Reset Control 131 0xD10 SYSCTRL R/W 0x0000.0000 System Control 133 0xD14 CFGCTRL R/W 0x0000.0200 Configuration and Control 135 0xD18 SYSPRI1 R/W 0x0000.0000 System Handler Priority 1 137 0xD1C SYSPRI2 R/W 0x0000.0000 System Handler Priority 2 138 0xD20 SYSPRI3 R/W 0x0000.0000 System Handler Priority 3 139 0xD24 SYSHNDCTRL R/W 0x0000.0000 System Handler Control and State 140 0xD28 FAULTSTAT R/W1C 0x0000.0000 Configurable Fault Status 144 0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 150 0xD34 MMADDR R/W - Memory Management Fault Address 151 0xD38 FAULTADDR R/W - Bus Fault Address 152 MPU Type 153 Memory Protection Unit (MPU) Registers 0xD90 MPUTYPE RO 0x0000.0800 July 24, 2011 105 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-7. Peripherals Register Map (continued) Offset Name Type Reset Description See page 0xD94 MPUCTRL R/W 0x0000.0000 MPU Control 154 0xD98 MPUNUMBER R/W 0x0000.0000 MPU Region Number 156 0xD9C MPUBASE R/W 0x0000.0000 MPU Region Base Address 157 0xDA0 MPUATTR R/W 0x0000.0000 MPU Region Attribute and Size 159 0xDA4 MPUBASE1 R/W 0x0000.0000 MPU Region Base Address Alias 1 157 0xDA8 MPUATTR1 R/W 0x0000.0000 MPU Region Attribute and Size Alias 1 159 0xDAC MPUBASE2 R/W 0x0000.0000 MPU Region Base Address Alias 2 157 0xDB0 MPUATTR2 R/W 0x0000.0000 MPU Region Attribute and Size Alias 2 159 0xDB4 MPUBASE3 R/W 0x0000.0000 MPU Region Base Address Alias 3 157 0xDB8 MPUATTR3 R/W 0x0000.0000 MPU Region Attribute and Size Alias 3 159 3.3 System Timer (SysTick) Register Descriptions This section lists and describes the System Timer registers, in numerical order by address offset. 106 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 Note: This register can only be accessed from privileged mode. The SysTick STCTRL register enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type R/W, reset 0x0000.0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 16 COUNT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 CLK_SRC INTEN ENABLE R/W 1 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 COUNT RO 0 Count Flag Value Description 0 The SysTick timer has not counted to 0 since the last time this bit was read. 1 The SysTick timer has counted to 0 since the last time this bit was read. This bit is cleared by a read of the register or if the STCURRENT register is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in the AHB-AP Control Register is clear. Otherwise, the COUNT bit is not changed by the debugger read. See the ARM® Debug Interface V5 Architecture Specification for more information on MasterType. 15:3 reserved RO 0x000 2 CLK_SRC R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Source Value Description 0 External reference clock. (Not implemented for Stellaris microcontrollers.) 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. July 24, 2011 107 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 1 INTEN R/W 0 0 ENABLE R/W 0 Description Interrupt Enable Value Description 0 Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. 1 An interrupt is generated to the NVIC when SysTick counts to 0. Enable Value Description 0 The counter is disabled. 1 Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. 108 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 Note: This register can only be accessed from privileged mode. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD field. SysTick Reload Value Register (STRELOAD) Base 0xE000.E000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 RO 0 RO 0 RO 0 RO 0 15 14 13 R/W 0 R/W 0 R/W 0 27 26 25 24 23 22 21 20 18 17 16 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 19 RELOAD RELOAD Type Reset Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 RELOAD R/W 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. July 24, 2011 109 Texas Instruments-Production Data Cortex-M3 Peripherals Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 Note: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000 Offset 0x018 Type R/WC, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 reserved Type Reset 20 19 18 17 16 CURRENT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 CURRENT Type Reset R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 CURRENT R/WC 0x00.0000 Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. 3.4 NVIC Register Descriptions This section lists and describes the NVIC registers, in numerical order by address offset. The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any other unprivileged mode access causes a bus fault. Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An interrupt can enter the pending state even if it is disabled. Before programming the VTABLE register to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For more information, see page 130. 110 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 Note: This register can only be accessed from privileged mode. See Table 2-9 on page 83 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 0-31 Set Enable (EN0) Base 0xE000.E000 Offset 0x100 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Enable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. July 24, 2011 111 Texas Instruments-Production Data Cortex-M3 Peripherals Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104 Note: This register can only be accessed from privileged mode. The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 83 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 32-54 Set Enable (EN1) Base 0xE000.E000 Offset 0x104 Type R/W, reset 0x0000.0000 31 30 29 28 RO 0 RO 0 RO 0 RO 0 15 14 13 R/W 0 R/W 0 R/W 0 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset INT INT Type Reset Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT R/W 0x00.0000 Interrupt Enable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. 112 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 Note: This register can only be accessed from privileged mode. See Table 2-9 on page 83 for interrupt assignments. Interrupt 0-31 Clear Enable (DIS0) Base 0xE000.E000 Offset 0x180 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 INT R/W R/W 0 Reset R/W 0 Description 0x0000.0000 Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. July 24, 2011 113 Texas Instruments-Production Data Cortex-M3 Peripherals Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184 Note: This register can only be accessed from privileged mode. The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 83 for interrupt assignments. Interrupt 32-54 Clear Enable (DIS1) Base 0xE000.E000 Offset 0x184 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset 19 18 17 16 INT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT R/W 0x00.0000 Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. 114 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 Note: This register can only be accessed from privileged mode. See Table 2-9 on page 83 for interrupt assignments. Interrupt 0-31 Set Pending (PEND0) Base 0xE000.E000 Offset 0x200 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 INT R/W R/W 0 Reset R/W 0 Description 0x0000.0000 Interrupt Set Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. July 24, 2011 115 Texas Instruments-Production Data Cortex-M3 Peripherals Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204 Note: This register can only be accessed from privileged mode. The PEND1 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 83 for interrupt assignments. Interrupt 32-54 Set Pending (PEND1) Base 0xE000.E000 Offset 0x204 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset 19 18 17 16 INT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT R/W 0x00.0000 Interrupt Set Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. 116 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 Note: This register can only be accessed from privileged mode. See Table 2-9 on page 83 for interrupt assignments. Interrupt 0-31 Clear Pending (UNPEND0) Base 0xE000.E000 Offset 0x280 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 INT R/W R/W 0 Reset R/W 0 Description 0x0000.0000 Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. July 24, 2011 117 Texas Instruments-Production Data Cortex-M3 Peripherals Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 Note: This register can only be accessed from privileged mode. The UNPEND1 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 83 for interrupt assignments. Interrupt 32-54 Clear Pending (UNPEND1) Base 0xE000.E000 Offset 0x284 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset 19 18 17 16 INT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT R/W 0x00.0000 Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 118 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 Note: This register can only be accessed from privileged mode. See Table 2-9 on page 83 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 0-31 Active Bit (ACTIVE0) Base 0xE000.E000 Offset 0x300 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 INT Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 INT Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type 31:0 INT RO RO 0 Reset RO 0 Description 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. July 24, 2011 119 Texas Instruments-Production Data Cortex-M3 Peripherals Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 Note: This register can only be accessed from privileged mode. The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 83 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 32-54 Active Bit (ACTIVE1) Base 0xE000.E000 Offset 0x304 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset 19 18 17 16 INT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 INT Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT RO 0x00.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. 120 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 Register 25: Interrupt 44-47 Priority (PRI11), offset 0x42C Register 26: Interrupt 48-51 Priority (PRI12), offset 0x430 Register 27: Interrupt 52-54 Priority (PRI13), offset 0x434 Note: This register can only be accessed from privileged mode. The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: PRIn Register Bit Field Interrupt Bits 31:29 Interrupt [4n+3] Bits 23:21 Interrupt [4n+2] Bits 15:13 Interrupt [4n+1] Bits 7:5 Interrupt [4n] See Table 2-9 on page 83 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register (see page 131) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. July 24, 2011 121 Texas Instruments-Production Data Cortex-M3 Peripherals Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 INTD Type Reset 25 24 23 reserved 22 21 20 19 INTC 18 17 16 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 INTB Type Reset 26 R/W 0 R/W 0 reserved RO 0 INTA Bit/Field Name Type Reset 31:29 INTD R/W 0x0 R/W 0 reserved RO 0 Description Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 INTC R/W 0x0 Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 INTB R/W 0x0 Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 INTA R/W 0x0 Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 122 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 28: Software Trigger Interrupt (SWTRIG), offset 0xF00 Note: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). See Table 2-9 on page 83 for interrupt assignments. When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 135) is set, unprivileged software can access the SWTRIG register. Software Trigger Interrupt (SWTRIG) Base 0xE000.E000 Offset 0xF00 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 INTID Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:0 INTID WO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. 3.5 System Control Block (SCB) Register Descriptions This section lists and describes the System Control Block (SCB) registers, in numerical order by address offset. The SCB registers can only be accessed from privileged mode. All registers must be accessed with aligned word accesses except for the FAULTSTAT and SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. July 24, 2011 123 Texas Instruments-Production Data Cortex-M3 Peripherals Register 29: Auxiliary Control (ACTLR), offset 0x008 Note: This register can only be accessed from privileged mode. The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M3 processor and does not normally require modification. Auxiliary Control (ACTLR) Base 0xE000.E000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2 DISFOLD R/W 0 DISFOLD DISWBUF DISMCYC RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Disable IT Folding Value Description 0 No effect. 1 Disables IT folding. In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding. 1 DISWBUF R/W 0 Disable Write Buffer Value Description 0 No effect. 1 Disables write buffer use during default memory map accesses. In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. Note: This bit only affects write buffers implemented in the Cortex-M3 processor. 124 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 DISMCYC R/W 0 Description Disable Interrupts of Multiple Cycle Instructions Value Description 0 No effect. 1 Disables interruption of load multiple and store multiple instructions. In this situation, the interrupt latency of the processor is increased because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. July 24, 2011 125 Texas Instruments-Production Data Cortex-M3 Peripherals Register 30: CPU ID Base (CPUID), offset 0xD00 Note: This register can only be accessed from privileged mode. The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x412F.C230 31 30 29 28 27 26 25 24 23 22 IMP Type Reset 21 20 19 18 VAR R0 0 R0 1 R0 0 R0 0 R0 0 R0 0 R0 0 R0 1 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PARTNO Type Reset RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 17 16 RO 1 RO 1 1 0 RO 0 RO 0 CON REV RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 IMP R0 0x41 Implementer Code RO 1 RO 1 RO 0 RO 0 Value Description 0x41 ARM 23:20 VAR RO 0x2 Variant Number Value Description 0x2 19:16 CON RO 0xF The rn value in the rnpn product revision identifier, for example, the 2 in r2p0. Constant Value Description 0xF 15:4 PARTNO RO 0xC23 Always reads as 0xF. Part Number Value Description 0xC23 Cortex-M3 processor. 3:0 REV RO 0x0 Revision Number Value Description 0x0 The pn value in the rnpn product revision identifier, for example, the 0 in r2p0. 126 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 31: Interrupt Control and State (INTCTRL), offset 0xD04 Note: This register can only be accessed from privileged mode. The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits. Interrupt Control and State (INTCTRL) Base 0xE000.E000 Offset 0xD04 Type R/W, reset 0x0000.0000 31 NMISET Type Reset 30 29 reserved 28 26 25 24 PENDSV UNPENDSV PENDSTSET PENDSTCLR reserved 23 22 21 ISRPRE ISRPEND 20 19 18 reserved 17 16 VECPEND R/W 0 RO 0 RO 0 R/W 0 WO 0 R/W 0 WO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 VECPEND Type Reset 27 RO 0 RETBASE RO 0 reserved RO 0 Bit/Field Name Type Reset 31 NMISET R/W 0 VECACT RO 0 Description NMI Set Pending Value Description 0 On a read, indicates an NMI exception is not pending. On a write, no effect. 1 On a read, indicates an NMI exception is pending. On a write, changes the NMI exception state to pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 30:29 reserved RO 0x0 28 PENDSV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PendSV Set Pending Value Description 0 On a read, indicates a PendSV exception is not pending. On a write, no effect. 1 On a read, indicates a PendSV exception is pending. On a write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to the UNPENDSV bit. July 24, 2011 127 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 27 UNPENDSV WO 0 Description PendSV Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the PendSV exception. This bit is write only; on a register read, its value is unknown. 26 PENDSTSET R/W 0 SysTick Set Pending Value Description 0 On a read, indicates a SysTick exception is not pending. On a write, no effect. 1 On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception state to pending. This bit is cleared by writing a 1 to the PENDSTCLR bit. 25 PENDSTCLR WO 0 SysTick Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the SysTick exception. This bit is write only; on a register read, its value is unknown. 24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23 ISRPRE RO 0 Debug Interrupt Handling Value Description 0 The release from halt does not take an interrupt. 1 The release from halt takes an interrupt. This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. 22 ISRPEND RO 0 Interrupt Pending Value Description 0 No interrupt is pending. 1 An interrupt is pending. This bit provides status for all interrupts excluding NMI and Faults. 21:19 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 128 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 18:12 VECPEND RO 0x00 Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. Value Description 0x00 No exceptions are pending 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x46 Interrupt Vector 54 0x47-0x7F Reserved 11 RETBASE RO 0 Return to Base Value Description 0 There are preempted active exceptions to execute. 1 There are no active exceptions, or the currently executing exception is the only active exception. This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero). 10:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:0 VECACT RO 0x00 Interrupt Pending Vector Number This field contains the active exception number. The exception numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 64). July 24, 2011 129 Texas Instruments-Production Data Cortex-M3 Peripherals Register 32: Vector Table Offset (VTABLE), offset 0xD08 Note: This register can only be accessed from privileged mode. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type R/W, reset 0x0000.0000 31 30 reserved Type Reset 29 28 27 26 25 24 23 BASE RO 0 RO 0 R/W 0 15 14 13 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 OFFSET R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 OFFSET Type Reset R/W 0 R/W 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:30 reserved RO 0x0 29 BASE R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Vector Table Base Value Description 28:9 OFFSET R/W 0x000.00 0 The vector table is in the code memory region. 1 The vector table is in the SRAM memory region. Vector Table Offset When configuring the OFFSET field, the offset must be aligned to the number of exception entries in the vector table. Because there are 54 interrupts, the minimum alignment is 128 words. 8:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 130 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 33: Application Interrupt and Reset Control (APINT), offset 0xD0C Note: This register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored. The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table 3-8 on page 131 shows how the PRIGROUP value controls this split. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29. Note: Determining preemption of an exception uses only the group priority field. Table 3-8. Interrupt Priority Levels a PRIGROUP Bit Field Binary Point Group Priority Field Subpriority Field Group Priorities Subpriorities 0x0 - 0x4 bxxx. [7:5] None 8 1 0x5 bxx.y [7:6] [5] 4 2 0x6 bx.yy [7] [6:5] 2 4 0x7 b.yyy None [7:5] 1 8 a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. Application Interrupt and Reset Control (APINT) Base 0xE000.E000 Offset 0xD0C Type R/W, reset 0xFA05.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 5 4 3 2 1 0 VECTKEY Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 15 14 13 12 11 10 reserved ENDIANESS Type Reset RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 0 R/W 0 R/W 0 9 8 7 6 PRIGROUP RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 VECTKEY R/W 0xFA05 reserved R/W 0 RO 0 RO 0 RO 0 SYSRESREQ VECTCLRACT VECTRESET RO 0 RO 0 WO 0 WO 0 WO 0 Description Register Key This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. 15 ENDIANESS RO 0 Data Endianess The Stellaris implementation uses only little-endian mode so this is cleared to 0. 14:11 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 131 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 10:8 PRIGROUP R/W 0x0 Description Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-8 on page 131 for more information). 7:3 reserved RO 0x0 2 SYSRESREQ WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Reset Request Value Description 0 No effect. 1 Resets the core and all on-chip peripherals except the Debug interface. This bit is automatically cleared during the reset of the core and reads as 0. 1 VECTCLRACT WO 0 Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 0 VECTRESET WO 0 System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 132 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 34: System Control (SYSCTRL), offset 0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.00 4 SEVONPEND R/W 0 RO 0 RO 0 RO 0 RO 0 4 3 SEVONPEND reserved R/W 0 RO 0 SLEEPDEEP SLEEPEXIT R/W 0 R/W 0 0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Wake Up on Pending Value Description 0 Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor. When an event or interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of a SEV instruction or an external event. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 SLEEPDEEP R/W 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. July 24, 2011 133 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 1 SLEEPEXIT R/W 0 Description Sleep on ISR Exit Value Description 0 When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. 1 When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 134 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 35: Configuration and Control (CFGCTRL), offset 0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 123). Configuration and Control (CFGCTRL) Base 0xE000.E000 Offset 0xD14 Type R/W, reset 0x0000.0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 reserved STKALIGN BFHFNMIGN RO 0 RO 0 R/W 1 Bit/Field Name Type Reset 31:10 reserved RO 0x0000.00 9 STKALIGN R/W 1 R/W 0 RO 0 RO 0 RO 0 4 3 2 1 0 DIV0 UNALIGNED reserved MAINPEND BASETHR R/W 0 R/W 0 RO 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Stack Alignment on Exception Entry Value Description 0 The stack is 4-byte aligned. 1 The stack is 8-byte aligned. On exception entry, the processor uses bit 9 of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 8 BFHFNMIGN R/W 0 Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK escalated handlers. Value Description 0 Data bus faults caused by load and store instructions cause a lock-up. 1 Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 135 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 4 DIV0 R/W 0 Description Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. Value Description 3 UNALIGNED R/W 0 0 Do not trap on divide by 0. A divide by zero returns a quotient of 0. 1 Trap on divide by 0. Trap on Unaligned Access Value Description 0 Do not trap on unaligned halfword and word accesses. 1 Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 MAINPEND R/W 0 Allow Main Interrupt Trigger Value Description 0 BASETHR R/W 0 0 Disables unprivileged software access to the SWTRIG register. 1 Enables unprivileged software access to the SWTRIG register (see page 123). Thread State Control Value Description 0 The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 88 for more information). 136 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 36: System Handler Priority 1 (SYSPRI1), offset 0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 reserved Type Reset RO 0 15 RO 0 RO 0 RO 0 RO 0 14 13 12 11 BUS Type Reset R/W 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 10 9 8 7 reserved R/W 0 RO 0 22 21 20 19 USAGE RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 MEM RO 0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 USAGE R/W 0x0 Usage Fault Priority This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 BUS R/W 0x0 Bus Fault Priority This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 MEM R/W 0x0 Memory Management Fault Priority This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 137 Texas Instruments-Production Data Cortex-M3 Peripherals Register 37: System Handler Priority 2 (SYSPRI2), offset 0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 SVC Type Reset 22 21 20 19 18 17 16 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:29 SVC R/W 0x0 RO 0 Description SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 28:0 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 138 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 38: System Handler Priority 3 (SYSPRI3), offset 0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type R/W, reset 0x0000.0000 31 30 29 28 27 TICK Type Reset 26 25 24 23 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 22 21 20 19 PENDSV R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 DEBUG RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:29 TICK R/W 0x0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 RO 0 RO 0 RO 0 Description SysTick Exception Priority This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority. 28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 PENDSV R/W 0x0 PendSV Priority This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority. 20:8 reserved RO 0x000 7:5 DEBUG R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. 4:0 reserved RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 139 Texas Instruments-Production Data Cortex-M3 Peripherals Register 39: System Handler Control and State (SYSHNDCTRL), offset 0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. Caution – Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified. System Handler Control and State (SYSHNDCTRL) Base 0xE000.E000 Offset 0xD24 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 SVC BUSP MEMP USAGEP R/W 0 R/W 0 R/W 0 R/W 0 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 USAGE BUS MEM R/W 0 R/W 0 R/W 0 10 9 8 7 6 5 4 3 2 1 0 TICK PNDSV reserved MON SVCA R/W 0 R/W 0 RO 0 R/W 0 R/W 0 USGA reserved BUSA MEMA R/W 0 RO 0 R/W 0 R/W 0 reserved Type Reset Type Reset reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 USAGE R/W 0 Usage Fault Enable Value Description 17 BUS R/W 0 0 Disables the usage fault exception. 1 Enables the usage fault exception. Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. 140 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 16 MEM R/W 0 Description Memory Management Fault Enable Value Description 15 SVC R/W 0 0 Disables the memory management fault exception. 1 Enables the memory management fault exception. SVC Call Pending Value Description 0 An SVC call exception is not pending. 1 An SVC call exception is pending. This bit can be modified to change the pending status of the SVC call exception. 14 BUSP R/W 0 Bus Fault Pending Value Description 0 A bus fault exception is not pending. 1 A bus fault exception is pending. This bit can be modified to change the pending status of the bus fault exception. 13 MEMP R/W 0 Memory Management Fault Pending Value Description 0 A memory management fault exception is not pending. 1 A memory management fault exception is pending. This bit can be modified to change the pending status of the memory management fault exception. 12 USAGEP R/W 0 Usage Fault Pending Value Description 0 A usage fault exception is not pending. 1 A usage fault exception is pending. This bit can be modified to change the pending status of the usage fault exception. 11 TICK R/W 0 SysTick Exception Active Value Description 0 A SysTick exception is not active. 1 A SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. July 24, 2011 141 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 10 PNDSV R/W 0 Description PendSV Exception Active Value Description 0 A PendSV exception is not active. 1 A PendSV exception is active. This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 MON R/W 0 Debug Monitor Active Value Description 7 SVCA R/W 0 0 The Debug monitor is not active. 1 The Debug monitor is active. SVC Call Active Value Description 0 SVC call is not active. 1 SVC call is active. This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit. 6:4 reserved RO 0x0 3 USGA R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Usage Fault Active Value Description 0 Usage fault is not active. 1 Usage fault is active. This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BUSA R/W 0 Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. 142 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 MEMA R/W 0 Description Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. July 24, 2011 143 Texas Instruments-Production Data Cortex-M3 Peripherals Register 40: Configurable Fault Status (FAULTSTAT), offset 0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: ■ Usage Fault Status (UFAULTSTAT), bits 31:16 ■ Bus Fault Status (BFAULTSTAT), bits 15:8 ■ Memory Management Fault Status (MFAULTSTAT), bits 7:0 FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows: ■ ■ ■ ■ ■ The complete FAULTSTAT register, with a word access to offset 0xD28 The MFAULTSTAT, with a byte access to offset 0xD28 The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28 The BFAULTSTAT, with a byte access to offset 0xD29 The UFAULTSTAT, with a halfword access to offset 0xD2A Bits are cleared by writing a 1 to them. In a fault handler, the true faulting address can be determined by: 1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address (FAULTADDR) value. 2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the MMADDR or FAULTADDR contents are valid. Software must follow this sequence because another higher priority exception might change the MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the MMADDR or FAULTADDR value. Configurable Fault Status (FAULTSTAT) Base 0xE000.E000 Offset 0xD28 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 reserved Type Reset RO 0 RO 0 RO 0 15 14 13 BFARV Type Reset R/W1C 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 25 24 DIV0 UNALIGN R/W1C 0 R/W1C 0 23 22 21 20 reserved RO 0 RO 0 RO 0 6 5 12 11 10 9 8 7 BSTKE BUSTKE IMPRE PRECISE IBUS MMARV R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved RO 0 RO 0 RO 0 19 18 17 16 NOCP INVPC INVSTAT UNDEF R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 4 3 2 1 0 MSTKE MUSTKE reserved DERR IERR R/W1C 0 R/W1C 0 RO 0 R/W1C 0 R/W1C 0 Bit/Field Name Type Reset Description 31:26 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 144 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 25 DIV0 R/W1C 0 Description Divide-by-Zero Usage Fault Value Description 0 No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 1 The processor has executed an SDIV or UDIV instruction with a divisor of 0. When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the Configuration and Control (CFGCTRL) register (see page 135). This bit is cleared by writing a 1 to it. 24 UNALIGN R/W1C 0 Unaligned Access Usage Fault Value Description 0 No unaligned access fault has occurred, or unaligned access trapping is not enabled. 1 The processor has made an unaligned memory access. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting the UNALIGNED bit in the CFGCTRL register (see page 135). This bit is cleared by writing a 1 to it. 23:20 reserved RO 0x00 19 NOCP R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. No Coprocessor Usage Fault Value Description 0 A usage fault has not been caused by attempting to access a coprocessor. 1 The processor has attempted to access a coprocessor. This bit is cleared by writing a 1 to it. 18 INVPC R/W1C 0 Invalid PC Load Usage Fault Value Description 0 A usage fault has not been caused by attempting to load an invalid PC value. 1 The processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing a 1 to it. July 24, 2011 145 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 17 INVSTAT R/W1C 0 Description Invalid State Usage Fault Value Description 0 A usage fault has not been caused by an invalid state. 1 The processor has attempted to execute an instruction that makes illegal use of the EPSR register. When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register. This bit is not set if an undefined instruction uses the EPSR register. This bit is cleared by writing a 1 to it. 16 UNDEF R/W1C 0 Undefined Instruction Usage Fault Value Description 0 A usage fault has not been caused by an undefined instruction. 1 The processor has attempted to execute an undefined instruction. When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it. 15 BFARV R/W1C 0 Bus Fault Address Register Valid Value Description 0 The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address. 1 The FAULTADDR register is holding a valid fault address. This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 14:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 146 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 12 BSTKE R/W1C 0 Description Stack Bus Fault Value Description 0 No bus fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 11 BUSTKE R/W1C 0 Unstack Bus Fault Value Description 0 No bus fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more bus faults. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 10 IMPRE R/W1C 0 Imprecise Data Bus Error Value Description 0 An imprecise data bus error has not occurred. 1 A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When this bit is set, a fault address is not written to the FAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the IMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it. 9 PRECISE R/W1C 0 Precise Data Bus Error Value Description 0 A precise data bus error has not occurred. 1 A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When this bit is set, the fault address is written to the FAULTADDR register. This bit is cleared by writing a 1 to it. July 24, 2011 147 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 8 IBUS R/W1C 0 Description Instruction Bus Error Value Description 0 An instruction bus error has not occurred. 1 An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 7 MMARV R/W1C 0 Memory Management Fault Address Register Valid Value Description 0 The value in the Memory Management Fault Address (MMADDR) register is not a valid fault address. 1 The MMADDR register is holding a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 6:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 MSTKE R/W1C 0 Stack Access Violation Value Description 0 No memory management fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more access violations. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 148 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 3 MUSTKE R/W1C 0 Description Unstack Access Violation Value Description 0 No memory management fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more access violations. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 DERR R/W1C 0 Data Access Violation Value Description 0 A data access violation has not occurred. 1 The processor attempted a load or store at a location that does not permit the operation. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register. This bit is cleared by writing a 1 to it. 0 IERR R/W1C 0 Instruction Access Violation Value Description 0 An instruction access violation has not occurred. 1 The processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing a 1 to it. July 24, 2011 149 Texas Instruments-Production Data Cortex-M3 Peripherals Register 41: Hard Fault Status (HFAULTSTAT), offset 0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type R/W1C, reset 0x0000.0000 Type Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBG FORCED R/W1C 0 R/W1C 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VECT reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 RO 0 reserved Type Reset Bit/Field Name Type Reset 31 DBG R/W1C 0 Description Debug Event This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable. 30 FORCED R/W1C 0 Forced Hard Fault Value Description 0 No forced hard fault has occurred. 1 A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it. 29:2 reserved RO 0x00 1 VECT R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Vector Table Read Fault Value Description 0 No bus fault has occurred on a vector table read. 1 A bus fault occurred on a vector table read. This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 150 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 42: Memory Management Fault Address (MMADDR), offset 0xD34 Note: This register can only be accessed from privileged mode. The MMADDR register contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in the MMADDR register is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Bits in the Memory Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether the value in the MMADDR register is valid (see page 144). Memory Management Fault Address (MMADDR) Base 0xE000.E000 Offset 0xD34 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. July 24, 2011 151 Texas Instruments-Production Data Cortex-M3 Peripherals Register 43: Bus Fault Address (FAULTADDR), offset 0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDR register contains the address of the location that generated a bus fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT) register indicate the cause of the fault and whether the value in the FAULTADDR register is valid (see page 144). Bus Fault Address (FAULTADDR) Base 0xE000.E000 Offset 0xD38 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. 3.6 Memory Protection Unit (MPU) Register Descriptions This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset. The MPU registers can only be accessed from privileged mode. 152 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 44: MPU Type (MPUTYPE), offset 0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.0800 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 DREGION Type Reset RO 0 RO 0 RO 0 RO 0 19 18 17 16 RO 0 IREGION RO 0 RO 0 RO 0 RO 0 4 3 2 1 reserved RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 0 SEPARATE RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 IREGION RO 0x00 Number of I Regions This field indicates the number of supported MPU instruction regions. This field always contains 0x00. The MPU memory map is unified and is described by the DREGION field. 15:8 DREGION RO 0x08 Number of D Regions Value Description 0x08 Indicates there are eight supported MPU data regions. 7:1 reserved RO 0x00 0 SEPARATE RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Separate or Unified MPU Value Description 0 Indicates the MPU is unified. July 24, 2011 153 Texas Instruments-Production Data Cortex-M3 Peripherals Register 45: MPU Control (MPUCTRL), offset 0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRL register enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask Register (FAULTMASK) escalated handlers. When the ENABLE and PRIVDEFEN bits are both set: ■ For privileged accesses, the default memory map is as described in “Memory Model” on page 72. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. ■ Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled, then only privileged software can operate. When the ENABLE bit is clear, the system uses the default memory map, which has the same memory attributes as if the MPU is not implemented (see Table 2-5 on page 75 for more information). The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set. Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when operating with these two priorities. MPU Control (MPUCTRL) Base 0xE000.E000 Offset 0xD94 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 PRIVDEFEN HFNMIENA R/W 0 R/W 0 ENABLE R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 154 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 2 PRIVDEFEN R/W 0 Description MPU Default Region This bit enables privileged software access to the default memory map. Value Description 0 If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 If the MPU is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. When this bit is set, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. 1 HFNMIENA R/W 0 MPU Enabled During Faults This bit controls the operation of the MPU during hard fault, NMI, and FAULTMASK handlers. Value Description 0 The MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit. 1 The MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. 0 ENABLE R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. July 24, 2011 155 Texas Instruments-Production Data Cortex-M3 Peripherals Register 46: MPU Region Number (MPUNUMBER), offset 0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBER register selects which memory region is referenced by the MPU Region Base Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the required region number should be written to this register before accessing the MPUBASE or the MPUATTR register. However, the region number can be changed by writing to the MPUBASE register with the VALID bit set (see page 157). This write updates the value of the REGION field. MPU Region Number (MPUNUMBER) Base 0xE000.E000 Offset 0xD98 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 NUMBER R/W 0x0 NUMBER RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. 156 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 47: MPU Region Base Address (MPUBASE), offset 0xD9C Register 48: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 Register 49: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC Register 50: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 Note: This register can only be accessed from privileged mode. The MPUBASE register defines the base address of the MPU region selected by the MPU Region Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To change the current region number and update the MPUNUMBER register, write the MPUBASE register with the VALID bit set. The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size, as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines the value of N where: N = Log2(Region size in bytes) If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x0000.0000. The base address is aligned to the size of the region. For example, a 64-KB region must be aligned on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000. MPU Region Base Address (MPUBASE) Base 0xE000.E000 Offset 0xD9C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALID reserved WO 0 RO 0 ADDR Type Reset ADDR Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:5 ADDR R/W 0x0000.000 R/W 0 R/W 0 R/W 0 R/W 0 REGION R/W 0 R/W 0 R/W 0 Description Base Address Mask Bits 31:N in this field contain the region base address. The value of N depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 157 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 4 VALID WO 0 Description Region Number Valid Value Description 0 The MPUNUMBER register is not changed and the processor updates the base address for the region specified in the MPUNUMBER register and ignores the value of the REGION field. 1 The MPUNUMBER register is updated with the value of the REGION field and the base address is updated for the region specified in the REGION field. This bit is always read as 0. 3 reserved RO 0 2:0 REGION R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Region Number On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the current region number in the MPUNUMBER register. 158 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 51: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 Register 52: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 Register 53: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 Register 54: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 Note: This register can only be accessed from privileged mode. The MPUATTR register defines the region size and memory attributes of the MPU region specified by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions. The MPUATTR register is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table 3-9 on page 159 gives example SIZE values with the corresponding region size and value of N in the MPU Region Base Address (MPUBASE) register. Table 3-9. Example SIZE Field Values a SIZE Encoding Region Size Value of N Note 00100b (0x4) 32 B 5 Minimum permitted size 01001b (0x9) 1 KB 10 - 10011b (0x13) 1 MB 20 - 11101b (0x1D) 1 GB 30 - 11111b (0x1F) 4 GB No valid ADDR field in MPUBASE; the Maximum possible size region occupies the complete memory map. a. Refers to the N parameter in the MPUBASE register (see page 157). MPU Region Attribute and Size (MPUATTR) Base 0xE000.E000 Offset 0xDA0 Type R/W, reset 0x0000.0000 31 30 29 28 27 reserved Type Reset 26 25 24 23 AP 21 reserved 20 19 18 TEX 17 16 XN reserved S C B RO 0 RO 0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 SRD Type Reset 22 reserved SIZE July 24, 2011 R/W 0 ENABLE R/W 0 159 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description 31:29 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 XN R/W 0 Instruction Access Disable Value Description 0 Instruction fetches are enabled. 1 Instruction fetches are disabled. 27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 26:24 AP R/W 0 Access Privilege For information on using this bit field, see Table 3-5 on page 103. 23:22 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21:19 TEX R/W 0x0 Type Extension Mask For information on using this bit field, see Table 3-3 on page 102. 18 S R/W 0 Shareable For information on using this bit, see Table 3-3 on page 102. 17 C R/W 0 Cacheable For information on using this bit, see Table 3-3 on page 102. 16 B R/W 0 Bufferable For information on using this bit, see Table 3-3 on page 102. 15:8 SRD R/W 0x00 Subregion Disable Bits Value Description 0 The corresponding subregion is enabled. 1 The corresponding subregion is disabled. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, configure the SRD field as 0x00. See the section called “Subregions” on page 101 for more information. 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:1 SIZE R/W 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 159 for more information. 160 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 ENABLE R/W 0 Description Region Enable Value Description 0 The region is disabled. 1 The region is enabled. July 24, 2011 161 Texas Instruments-Production Data JTAG Interface 4 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. ® The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO output. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM, Stellaris, and unimplemented JTAG instructions. The Stellaris JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. 162 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 4.1 Block Diagram Figure 4-1. JTAG Module Block Diagram TCK TMS TAP Controller TDI Instruction Register (IR) BYPASS Data Register TDO Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register Cortex-M3 Debug Port 4.2 Signal Description The following table lists the external signals of the JTAG/SWD controller and describes the function of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals are under commit protection and require a special process to be configured as GPIOs, see “Commit Control” on page 408. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 424) is set to choose the JTAG/SWD function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 442) to assign the JTAG/SWD controller signals to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 400. Table 4-1. Signals for JTAG_SWD_SWO (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description SWCLK 80 PC0 (3) I TTL JTAG/SWD CLK. SWDIO 79 PC1 (3) I/O TTL JTAG TMS and SWDIO. SWO 77 PC3 (3) O TTL JTAG TDO and SWO. TCK 80 PC0 (3) I TTL JTAG/SWD CLK. TDI 78 PC2 (3) I TTL JTAG TDI. TDO 77 PC3 (3) O TTL JTAG TDO and SWO. July 24, 2011 163 Texas Instruments-Production Data JTAG Interface Table 4-1. Signals for JTAG_SWD_SWO (100LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment 79 TMS PC1 (3) a Pin Type Buffer Type I TTL Description JTAG TMS and SWDIO. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 4-2. Signals for JTAG_SWD_SWO (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description A9 PC0 (3) I TTL JTAG/SWD CLK. SWDIO B9 PC1 (3) I/O TTL JTAG TMS and SWDIO. SWO A10 PC3 (3) O TTL JTAG TDO and SWO. TCK A9 PC0 (3) I TTL JTAG/SWD CLK. SWCLK TDI B8 PC2 (3) I TTL JTAG TDI. TDO A10 PC3 (3) O TTL JTAG TDO and SWO. TMS B9 PC1 (3) I TTL JTAG TMS and SWDIO. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 4.3 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 163. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 4-4 on page 170 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 888 for JTAG timing diagrams. Note: 4.3.1 Of all the possible reset sources, only Power-On reset (POR) and the assertion of the RST input have any effect on the JTAG module. The pin configurations are reset by both the RST input and POR, whereas the internal JTAG logic is only reset with POR. See “Reset Sources” on page 175 for more information on reset. JTAG Interface Pins The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their associated state after a power-on reset or reset caused by the RST input are given in Table 4-3. Detailed information on each pin follows. Refer to “General-Purpose Input/Outputs (GPIOs)” on page 400 for information on how to reprogram the configuration of these pins. 164 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 4-3. JTAG Port Pins State after Power-On Reset or RST assertion 4.3.1.1 Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value TCK Input Enabled Disabled N/A N/A TMS Input Enabled Disabled N/A N/A TDI Input Enabled Disabled N/A N/A TDO Output Enabled Disabled 2-mA driver High-Z Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks and to ensure that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset, assuring that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source (see page 430 and page 432). 4.3.1.2 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG module and associated registers are reset to their default values. This procedure should be performed to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety in Figure 4-2 on page 166. By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost (see page 430). 4.3.1.3 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, may present this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost (see page 430). 4.3.1.4 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the July 24, 2011 165 Texas Instruments-Production Data JTAG Interface chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset, assuring that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states (see page 430 and page 432). 4.3.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 4-2. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset the JTAG module after the microcontroller has been powered on, the TMS input must be held HIGH for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. Figure 4-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 0 Select DR Scan 1 Select IR Scan 1 0 1 Capture DR 1 Capture IR 0 0 Shift DR Shift IR 0 1 Exit 1 DR Exit 1 IR 1 Pause IR 0 1 Exit 2 DR 0 1 0 Exit 2 IR 1 1 Update DR 4.3.3 1 0 Pause DR 1 0 1 0 0 1 0 0 Update IR 1 0 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows 166 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller this information to be shifted out on TDO during the TAP controller’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 170. 4.3.4 Operational Considerations Certain operational parameters must be considered when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. 4.3.4.1 GPIO Functionality When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0] set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0] set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors (PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select (GPIOAFSEL) register) on the JTAG/SWD pins. See page 424, page 430, page 432, and page 435. It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides four more GPIOs for use in the design. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 424), GPIO Pull Up Select (GPIOPUR) register (see page 430), GPIO Pull-Down Select (GPIOPDR) register (see page 432), and GPIO Digital Enable (GPIODEN) register (see page 435) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 437) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 438) have been set. 4.3.4.2 Communication with JTAG/SWD Because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software should check the ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. July 24, 2011 167 Texas Instruments-Production Data JTAG Interface 4.3.4.3 Recovering a "Locked" Microcontroller Note: Performing the sequence below restores the nonvolatile registers discussed in “Nonvolatile Register Programming” on page 302 to their factory default values. The mass erase of the Flash memory caused by the sequence below occurs prior to the nonvolatile registers being restored. If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug port unlock sequence that can be used to recover the microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence is: 1. Assert and hold the RST signal. 2. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD Switching” on page 169. 3. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG Switching” on page 169. 4. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 5. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 6. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 7. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 8. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 9. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 10. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 11. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 12. Release the RST signal. 13. Wait 400 ms. 14. Power-cycle the microcontroller. 4.3.4.4 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued before the SWD session begins. The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. 168 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Stepping through this sequence of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Debug Interface V5 Architecture Specification. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This instance is the only one where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send the switching preamble to the microcontroller. The 16-bit TMS command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already in SWD mode, the SWD goes into the line reset state before sending the switch sequence. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch command to the microcontroller. The 16-bit TMS command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first. This command can also be represented as 0xE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already in JTAG mode, the JTAG goes into the Test Logic Reset state before sending the switch sequence. 4.4 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. To return the pins to their JTAG functions, enable the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the four JTAG pins (PC[3:0]) should be returned to their default settings. July 24, 2011 169 Texas Instruments-Production Data JTAG Interface 4.5 Register Descriptions The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within the JTAG controller are all accessed serially through the TAP Controller. These registers include the Instruction Register and the six Data Registers. 4.5.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-4. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 4-4. JTAG Instruction Register Commands 4.5.1.1 IR[3:0] Instruction Description 0x0 EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0x1 INTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. 0x2 SAMPLE / PRELOAD 0x8 ABORT Shifts data into the ARM Debug Port Abort Register. 0xA DPACC Shifts data into and out of the ARM DP Access Register. 0xB APACC Shifts data into and out of the ARM AC Access Register. 0xE IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. 0xF BYPASS Connects TDI to TDO through a single Shift Register chain. All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. EXTEST Instruction The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. With tests that drive known values out of the controller, this instruction can be used to verify connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 4.5.1.2 INTEST Instruction The INTEST instruction is not associated with its own Data Register chain. Instead, the INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. With tests that drive known values into the controller, this instruction can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. 170 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller While the INTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 4.5.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. See “Boundary Scan Data Register” on page 172 for more information. 4.5.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. See the “ABORT Data Register” on page 173 for more information. 4.5.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. See “DPACC Data Register” on page 173 for more information. 4.5.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. See “APACC Data Register” on page 173 for more information. 4.5.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure input and output data streams. IDCODE is the default instruction loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. See “IDCODE Data Register” on page 172 for more information. July 24, 2011 171 Texas Instruments-Production Data JTAG Interface 4.5.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 172 for more information. 4.5.2 Data Registers The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections. 4.5.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-3. The standard requires that every JTAG-compliant microcontroller implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This definition allows auto-configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 4-3. IDCODE Register Format 31 TDI 4.5.2.2 28 27 12 11 Version Part Number 1 0 Manufacturer ID 1 TDO BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-4. The standard requires that every JTAG-compliant microcontroller implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This definition allows auto-configuration test tools to determine which instruction is the default instruction. Figure 4-4. BYPASS Register Format 0 TDI 4.5.2.3 0 TDO Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each 172 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as shown in the figure. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. The EXTEST instruction forces data out of the controller, and the INTEST instruction forces data into the controller. Figure 4-5. Boundary Scan Register Format TDI I N O U T O E ... 1st GPIO 4.5.2.4 I N O U T mth GPIO O E I N O U T (m+1)th GPIO O E ... I N O U T O E TDO GPIO nth APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. July 24, 2011 173 Texas Instruments-Production Data System Control 5 System Control System control configures the overall operation of the device and provides information about the device. Configurable features include reset control, NMI operation, power control, clock control, and low-power modes. 5.1 Signal Description The following table lists the external signals of the System Control module and describes the function of each. The NMI signal is the alternate function for the GPIO PB7 signal and functions as a GPIO after reset. PB7 is under commit protection and requires a special process to be configured as any alternate function or to subsequently return to the GPIO function, see “Commit Control” on page 408. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 424) should be set to choose the NMI function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 442) to assign the NMI signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 400. The remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment and function. Table 5-1. Signals for System Control & Clocks (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description NMI 89 PB7 (4) I TTL Non-maskable interrupt. OSC0 48 fixed I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 64 fixed I TTL System reset input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 5-2. Signals for System Control & Clocks (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description NMI A8 PB7 (4) I TTL Non-maskable interrupt. OSC0 L11 fixed I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST H11 fixed I TTL System reset input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 5.2 Functional Description The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 175 ■ Local control, such as reset (see “Reset Control” on page 175), power (see “Power Control” on page 180) and clock control (see “Clock Control” on page 181) 174 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 188 5.2.1 Device Identification Several read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, Flash memory size, and other features. See the DID0 (page 193), DID1 (page 220), DC0-DC9 (page 222) and NVMSTAT (page 239) registers. 5.2.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 Reset Sources The LM3S1F11 microcontroller has six sources of reset: 1. Power-on reset (POR) (see page 176). 2. External reset input pin (RST) assertion (see page 176). 3. Internal brown-out (BOR) detector (see page 178). 4. Software-initiated reset (with the software reset registers) (see page 178). 5. A watchdog timer reset condition violation (see page 179). 6. MOSC failure (see page 180). Table 5-3 provides a summary of results of the various reset operations. Table 5-3. Reset Sources Reset Source Core Reset? JTAG Reset? On-Chip Peripherals a Reset? Power-On Reset Yes Yes Yes RST Yes Yes Yes Brown-Out Reset Yes Yes Yes Software System Request Reset using the SYSRESREQ bit in the APINT register. Yes Yes Yes Software System Request Reset using the VECTRESET bit in the APINT register. Yes No No Software Peripheral Reset No Yes Yes b Watchdog Reset Yes Yes Yes MOSC Failure Reset Yes Yes Yes a. Refer to “Register Reset” on page 277 for information on how reset affects the Hibernation module. b. Programmable on a module-by-module basis using the Software Reset Control Registers. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, in which case, all the bits in the RESC register are cleared except for the POR indicator. A bit in the RESC register can be cleared by writing a 0. July 24, 2011 175 Texas Instruments-Production Data System Control At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal as configured in the Boot Configuration (BOOTCFG) register. At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always executed. The boot sequence executed from ROM is as follows: 1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is mapped to address 0x0. 2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is valid data at address 0x0000.0004, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. For example, if the BOOTCFG register is written and committed with the value of 0x0000.3C01, then PB7 is examined at reset to determine if the ROM Boot Loader should be executed. If PB7 is Low, the core unconditionally begins executing the ROM boot loader. If PB7 is High, then the application in Flash memory is executed if the reset vector at location 0x0000.0004 is not 0xFFFF.FFFF. Otherwise, the ROM boot loader is executed. 5.2.2.2 Power-On Reset (POR) The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VTH). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete (see “Power and Brown-out” on page 890). For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input may be used as discussed in “External RST Pin” on page 176. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller and when the microcontroller wakes from hibernation. The Power-On Reset timing is shown in Figure 21-4 on page 890. 5.2.2.3 External RST Pin Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be sure to place any components connected to the RST signal as close to the microcontroller as possible. 176 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller If the application only uses the internal POR circuit, the RST input must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 177. Figure 5-1. Basic RST Configuration VDD Stellaris® RPU RST RPU = 0 to 100 kΩ The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals except the JTAG TAP controller (see “JTAG Interface” on page 162). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted (see “Reset” on page 891). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. To improve noise immunity and/or to delay reset at power up, the RST input may be connected to an RC network as shown in Figure 5-2 on page 177. Figure 5-2. External Circuitry to Extend Power-On Reset VDD Stellaris® RPU RST C1 RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 µF If the application requires the use of an external reset switch, Figure 5-3 on page 178 shows the proper circuitry to use. July 24, 2011 177 Texas Instruments-Production Data System Control Figure 5-3. Reset Circuit Controlled by Switch VDD Stellaris® RPU RST C1 RS Typical RPU = 10 kΩ Typical RS = 470 Ω C1 = 10 nF The RPU and C1 components define the power-on delay. The external reset timing is shown in Figure 21-7 on page 891. 5.2.2.4 Brown-Out Reset (BOR) The microcontroller provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate an interrupt or a system reset. The default condition is to reset the microcontroller. Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset; if BORIOR is clear, an interrupt is generated. When a Brown-out condition occurs during a Flash PROGRAM or ERASE operation, a full system reset is always triggered without regard to the setting in the PBORCTL register. The brown-out reset sequence is as follows: 1. When VDD drops below VBTH, an internal BOR condition is set. 2. If the BOR condition exists, an internal reset is asserted. 3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. 4. The internal BOR condition is reset after 500 µs to prevent another BOR condition from being set before software has a chance to investigate the original cause. The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 21-5 on page 890. 5.2.2.5 Software Reset Software can reset a specific peripheral or generate a reset to the entire microcontroller. 178 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Peripherals can be individually reset by software via three registers that control reset signals to each on-chip peripheral (see the SRCRn registers, page 261). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 188). The entire microcontroller, including the core, can be reset by software by setting the SYSRESREQ bit in the Application Interrupt and Reset Control (APINT) register. The software-initiated system reset sequence is as follows: 1. A software microcontroller reset is initiated by setting the SYSRESREQ bit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The core only can be reset by software by setting the VECTRESET bit in the APINT register. The software-initiated core reset sequence is as follows: 1. A core reset is initiated by setting the VECTRESET bit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 21-8 on page 891. 5.2.2.6 Watchdog Timer Reset The Watchdog Timer module's function is to prevent system hangs. The LM3S1F11 microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module operates in the same manner except that because the PIOSC watchdog timer module is in a different clock domain, register accesses must have a time delay between them. The watchdog timer can be configured to generate an interrupt to the microcontroller on its first time-out and to generate a reset on its second time-out. After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. For more information on the Watchdog Timer module, see “Watchdog Timers” on page 577. July 24, 2011 179 Texas Instruments-Production Data System Control The watchdog reset timing is shown in Figure 21-9 on page 892. 5.2.3 Non-Maskable Interrupt The microcontroller has three sources of non-maskable interrupt (NMI): ■ The assertion of the NMI signal ■ A main oscillator verification error ■ The NMISET bit in the Interrupt Control and State (INTCTRL) register in the Cortex™-M3 (see page 127). Software must check the cause of the interrupt in order to distinguish among the sources. 5.2.3.1 NMI Pin The NMI signal is the alternate function for GPIO port pin PB7. The alternate function must be enabled in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs (GPIOs)” on page 400. Note that enabling the NMI alternate function requires the use of the GPIO lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality, see page 438. The active sense of the NMI signal is High; asserting the enabled NMI signal above VIH initiates the NMI interrupt sequence. 5.2.3.2 Main Oscillator Verification Failure The LM3S1F11 microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is enabled and a failure occurs, a power-on reset is generated and control is transferred to the NMI handler. The NMI handler is used to address the main oscillator verification failure because the necessary code can be removed from the general reset handler, speeding up reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator fail status (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit action is described in more detail in “Main Oscillator Verification Circuit” on page 188. 5.2.4 Power Control ® The Stellaris microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture. An external regulator may be used instead of the on-chip LDO, but must meet the requirements in Table 21-4 on page 890. Regardless of the LDO implementation, the internal LDO requires decoupling capacitors as specified in “On-Chip Low Drop-Out (LDO) Regulator” on page 892. Note: VDDA must be supplied with 3.3 V, or the microcontroller does not function properly. VDDA is the supply for all of the analog circuitry on the device, including the clock circuitry. 180 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 5-4. Power Architecture VDDC Internal Logic and PLL VDDC GND GND LDO Low-Noise LDO +3.3V VDD GND I/O Buffers VDD GND VDDA GNDA Analog Circuits VDDA 5.2.5 GNDA Clock Control System control determines the control of clocks in this part. 5.2.5.1 Fundamental Clock Sources There are multiple clock sources for use in the microcontroller: ■ Precision Internal Oscillator (PIOSC). The precision internal oscillator is an on-chip clock source that is the clock source the microcontroller uses during and following POR. It does not require the use of any external components and provides a clock that is 16 MHz ±1% at room temperature and ±3% across temperature. The PIOSC allows for a reduced system cost in applications that require an accurate clock source. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. If the Hibernation Module clock source is a 32.768-kHz oscillator, the precision internal oscillator can be trimmed by software based on a reference clock for increased accuracy. ■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being used, the crystal value must be one of the supported frequencies between 3.579545 MHz to July 24, 2011 181 Texas Instruments-Production Data System Control 16.384 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz to 16.384 MHz. The single-ended clock source range is from DC through the specified speed of the microcontroller. The supported crystals are listed in the XTAL bit field in the RCC register (see page 204). ■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator provides an operational frequency of 30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the MOSC to be powered down. ■ Hibernation Module Clock Source. The Hibernation module can be clocked in one of two ways. The first way is a 4.194304-MHz crystal connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to produce the 32.768-kHz clock reference. The second way is a 32.768-kHz oscillator connected to the XOSC0 pin. The 32.768-kHz oscillator can be used for the system clock, thus eliminating the need for an additional crystal or oscillator. The Hibernation module clock source is intended to provide the system with a real-time clock source and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings. The internal system clock (SysClk), is derived from any of the above sources plus two others: the output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz (inclusive). Table 5-4 on page 182 shows how the various clock sources can be used in a system. Table 5-4. Clock Source Options 5.2.5.2 Clock Source Drive PLL? Precision Internal Oscillator Yes Used as SysClk? BYPASS = 0, OSCSRC = 0x1 Yes BYPASS = 1, OSCSRC = 0x1 Precision Internal Oscillator divide by 4 No (4 MHz ± 1%) - Yes BYPASS = 1, OSCSRC = 0x2 Main Oscillator BYPASS = 0, OSCSRC = 0x0 Yes BYPASS = 1, OSCSRC = 0x0 Yes Internal 30-kHz Oscillator No - Yes BYPASS = 1, OSCSRC = 0x3 Hibernation Module 32.768-kHz Oscillator No - Yes BYPASS = 1, OSCSRC2 = 0x7 Hibernation Module 4.194304-MHz Crystal No - No - Clock Configuration The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. These registers control the following clock functionality: ■ Source of clocks in sleep and deep-sleep modes ■ System clock derived from PLL or other clock source ■ Enabling/disabling of oscillators and PLL ■ Clock divisors 182 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ Crystal input selection Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the RCC register is required, include another register access after writing the RCC register and before writing the RCC2 register. Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. When the PLL is enabled, the ADC clock signal is automatically divided down to 16 MHz from the PLL output for proper ADC operation. Note: When the ADC module is in operation, the system clock must be at least 16 MHz. July 24, 2011 183 Texas Instruments-Production Data System Control Figure 5-5. Main Clock Tree XTALa USBPWRDN c USB PLL (480 MHz) ÷4 USB Clock RXINT RXFRAC I2S Receive MCLK TXINT TXFRAC I2S Transmit MCLK USEPWMDIV a PWMDW a PWM Clock XTALa PWRDN b MOSCDIS a PLL (400 MHz) Main OSC USESYSDIV a,d DIV400 c ÷2 IOSCDIS a System Clock Precision Internal OSC (16 MHz) SYSDIV e ÷4 BYPASS b,d Internal OSC (30 kHz) Hibernation OSC (32.768 kHz) PWRDN ADC Clock OSCSRC b,d ÷ 25 a. Control provided by RCC register bit/field. b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2. c. Control provided by RCC2 register bit/field. d. Also may be controlled by DSLPCLKCFG when in deep sleep mode. e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2 bit, or [SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set. Note: The figure above shows all features available on all Stellaris® Firestorm-class microcontrollers. Not all peripherals may be available on this device. Using the SYSDIV and SYSDIV2 Fields In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register 184 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1). The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see Table 5-4 on page 182. Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field SYSDIV 0x0 Divisor /1 a ® Frequency (BYPASS=0) Frequency (BYPASS=1) StellarisWare Parameter reserved SYSCTL_SYSDIV_1 Clock source frequency/2 b 0x1 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x2 /3 66.67 MHz Clock source frequency/3 SYSCTL_SYSDIV_3 0x3 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x4 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 0x5 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x6 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 0x7 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x8 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9 0x9 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 0xA /11 18.18 MHz Clock source frequency/11 SYSCTL_SYSDIV_11 0xB /12 16.67 MHz Clock source frequency/12 SYSCTL_SYSDIV_12 0xC /13 15.38 MHz Clock source frequency/13 SYSCTL_SYSDIV_13 0xD /14 14.29 MHz Clock source frequency/14 SYSCTL_SYSDIV_14 0xE /15 13.33 MHz Clock source frequency/15 SYSCTL_SYSDIV_15 0xF /16 12.5 MHz (default) Clock source frequency/16 SYSCTL_SYSDIV_16 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding plus 1. Table 5-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list of possible clock sources, see Table 5-4 on page 182. Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field SYSDIV2 Divisor a Frequency (BYPASS2=0) Frequency (BYPASS2=1) StellarisWare Parameter b 0x00 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1 0x01 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x02 /3 66.67 MHz Clock source frequency/3 SYSCTL_SYSDIV_3 0x03 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x04 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 ... ... ... ... ... 0x09 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 ... ... ... ... ... July 24, 2011 185 Texas Instruments-Production Data System Control Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field (continued) Divisor SYSDIV2 0x3F /64 a Frequency (BYPASS2=0) Frequency (BYPASS2=1) StellarisWare Parameter 3.125 MHz Clock source frequency/64 SYSCTL_SYSDIV_64 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In this situation, the divisor is equivalent to the (SYSDIV2 encoding with SYSDIV2LSB appended) plus one. Table 5-7 shows the frequency choices when DIV400 is set. When the DIV400 bit is clear, SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table 5-6 on page 185. Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1 /2 reserved - 0 /3 reserved - 1 /4 reserved - 0 /5 80 MHz SYSCTL_SYSDIV_2_5 1 /6 66.67 MHz SYSCTL_SYSDIV_3 0 /7 reserved - 1 /8 50 MHz SYSCTL_SYSDIV_4 0 /9 44.44 MHz SYSCTL_SYSDIV_4_5 1 /10 40 MHz SYSCTL_SYSDIV_5 ... ... ... ... 0 /127 3.15 MHz SYSCTL_SYSDIV_63_5 1 /128 3.125 MHz SYSCTL_SYSDIV_64 0x00 reserved 0x01 0x02 0x03 0x04 ... 0x3F b StellarisWare Parameter SYSDIV2LSB Divisor a Frequency (BYPASS2=0) SYSDIV2 a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0. b. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. 5.2.5.3 Precision Internal Oscillator Operation (PIOSC) The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC must remain enabled as it is used for internal functions. The PIOSC can only be disabled during Deep-Sleep mode. It can be powered down by setting the IOSCDIS bit in the RCC register. The PIOSC generates a 16-MHz clock with a ±1% accuracy at room temperatures. Across the extended temperature range, the accuracy is ±3%. At the factory, the PIOSC is set to 16 MHz at room temperature, however, the frequency can be trimmed for other voltage or temperature conditions using software in one of three ways: ■ Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator Calibration (PIOSCCAL) register. ■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As the UT value increases, the generated period increases. To commit a new UT value, first set the 186 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within a few clock periods and is glitch free. ■ Automatic calibration using the enable 32.768-kHz oscillator from the Hibernation module: Set the CAL bit in the PIOSCCAL register; the results of the calibration are shown in the RESULT field in the Precision Internal Oscillator Statistic (PIOSCSTAT) register. After calibration is complete, the PIOSC is trimmed using the trimmed value returned in the CT field. 5.2.5.4 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 16.384 MHz, otherwise, the range of supported crystals is 1 to 16.384 MHz. The XTAL bit in the RCC register (see page 204) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 5.2.5.5 Main PLL Frequency Configuration The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor, unless the DIV400 bit in the RCC2 register is set. To configure the PIOSC to be the clock source for the main PLL, program the OSCRC2 field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x1. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 208). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 21-8 on page 893 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 204) describes the available crystal choices and default programming of the PLLCFG register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. 5.2.5.6 PLL Modes ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 204 and page 211). 5.2.5.7 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 21-7 on page 892). During the relock time, the affected PLL is not usable as a clock reference. The PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. July 24, 2011 187 Texas Instruments-Production Data System Control ■ Change in the PLL from Power-Down to Normal mode. A counter clocked by the system clock is used to measure the TREADY requirement. If the system clock is the main oscillator and it is running off an 8.192 MHz or slower external oscillator clock, the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz). If the system clock is running off the PIOSC or an external oscillator clock that is faster than 8.192 MHz, the down counter is set to 0x2400. Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the microcontroller from the oscillator selected by the RCC/RCC2 register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt. 5.2.5.8 Main Oscillator Verification Circuit The clock control includes circuitry to ensure that the main oscillator is running at the appropriate frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable band of attached crystals. The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL) register. If this circuit is enabled and detects an error, the following sequence is performed by the hardware: 1. The MOSCFAIL bit in the Reset Cause (RESC) register is set. 2. If the internal oscillator (PIOSC) is disabled, it is enabled. 3. The system clock is switched from the main oscillator to the PIOSC. 4. An internal power-on reset is initiated that lasts for 32 PIOSC periods. 5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence. if the MOSCIM bit in the MOSCCTL register is set, then the following sequence is performed by the hardware: 1. The system clock is switched from the main oscillator to the PIOSC. 2. The MOFRIS bit in the RIS register is set to indicate a MOSC failure. 5.2.6 System Control For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating logic for each peripheral or block in the system while the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. These registers are located in the System Control register map starting at offsets 0x600, 0x700, and 0x800, respectively. There must be a delay of 3 system clocks after a peripheral module clock is enabled in the RCGC register before any module registers are accessed. There are four levels of operation for the microcontroller defined as: ■ Run mode 188 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ Sleep mode ■ Deep-Sleep mode ■ Hibernation mode The following sections describe the different modes in detail. Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their Run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock. A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface. 5.2.6.1 Run Mode In Run mode, the microcontroller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. 5.2.6.2 Sleep Mode In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 90 for more details. Peripherals are clocked that are enabled in the SCGCn registers when auto-clock gating is enabled (see the RCC register) or the RCGCn registers when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. 5.2.6.3 Deep-Sleep Mode In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-Sleep mode is entered by first setting the SLEEPDEEP bit in the System Control (SYSCTRL) register (see page 133) and then executing a WFI instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 90 for more details. The Cortex-M3 processor core and the memory subsystem are not clocked in Deep-Sleep mode. Peripherals are clocked that are enabled in the DCGCn registers when auto-clock gating is enabled (see the RCC register) or the RCGCn registers when auto-clock gating is disabled. The system clock source is specified in the DSLPCLKCFG register. When the DSLPCLKCFG register is used, the internal oscillator source is powered up, if necessary, and other clocks are powered down. If the PLL is running at the time of the WFI instruction, hardware powers the PLL down and overrides July 24, 2011 189 Texas Instruments-Production Data System Control the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the PIOSC is used as the PLL reference clock source, it may continue to provide the clock during Deep-Sleep. See page 215. 5.2.6.4 Hibernation Mode In this mode, the power supplies are turned off to the main part of the microcontroller and only the Hibernation module's circuitry is active. An external wake event or RTC event is required to bring the microcontroller back to Run mode. The Cortex-M3 processor and peripherals outside of the Hibernation module see a normal "power on" sequence and the processor starts running code. Software can determine if the microcontroller has been restarted from Hibernate mode by inspecting the Hibernation module registers. For more information on the operation of Hibernation mode, see “Hibernation Module” on page 268. 5.3 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register, thereby configuring the microcontroller to run off a “raw” clock source and allowing for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 5.4 Register Map Table 5-8 on page 191 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Additional Flash and ROM registers defined in the System Control register space are described in the “Internal Memory” on page 295. 190 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 5-8. System Control Register Map Description See page Offset Name Type Reset 0x000 DID0 RO - Device Identification 0 193 0x004 DID1 RO - Device Identification 1 220 0x008 DC0 RO 0x00BF.00BF Device Capabilities 0 222 0x010 DC1 RO - Device Capabilities 1 223 0x014 DC2 RO 0x430F.5037 Device Capabilities 2 225 0x018 DC3 RO 0xBFFF.0FC0 Device Capabilities 3 227 0x01C DC4 RO 0x0004.F1FF Device Capabilities 4 229 0x020 DC5 RO 0x0000.0000 Device Capabilities 5 231 0x024 DC6 RO 0x0000.0000 Device Capabilities 6 232 0x028 DC7 RO 0xFFFF.FFFF Device Capabilities 7 233 0x02C DC8 RO 0x0000.00FF Device Capabilities 8 ADC Channels 237 0x030 PBORCTL R/W 0x0000.0002 Brown-Out Reset Control 195 0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 261 0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 263 0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 266 0x050 RIS RO 0x0000.0000 Raw Interrupt Status 196 0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 198 0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 200 0x05C RESC R/W - Reset Cause 202 0x060 RCC R/W 0x0780.3AD1 Run-Mode Clock Configuration 204 0x064 PLLCFG RO - XTAL to PLL Translation 208 0x06C GPIOHBCTL R/W 0x0000.0000 GPIO High-Performance Bus Control 209 0x070 RCC2 R/W 0x07C0.6810 Run-Mode Clock Configuration 2 211 0x07C MOSCCTL R/W 0x0000.0000 Main Oscillator Control 214 0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 240 0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 246 0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 255 0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 242 0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 249 0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 257 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 244 0x124 DCGC1 R/W 0x00000000 Deep-Sleep Mode Clock Gating Control Register 1 252 July 24, 2011 191 Texas Instruments-Production Data System Control Table 5-8. System Control Register Map (continued) Name Type Reset 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 259 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 215 0x150 PIOSCCAL R/W 0x0000.0000 Precision Internal Oscillator Calibration 217 0x154 PIOSCSTAT RO 0x0000.0040 Precision Internal Oscillator Statistics 219 0x190 DC9 RO 0x0000.00FF Device Capabilities 9 ADC Digital Comparators 238 0x1A0 NVMSTAT RO 0x0000.0001 Non-Volatile Memory Information 239 5.5 Description See page Offset Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. 192 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset 31 30 28 27 26 VER reserved Type Reset 29 25 24 23 22 21 20 reserved 18 17 16 CLASS RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - MAJOR Type Reset 19 MINOR Bit/Field Name Type Reset 31 reserved RO 0 30:28 VER RO 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 Second version of the DID0 register format. 27:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 CLASS RO 0x06 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all microcontrollers in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior microcontrollers. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x06 Stellaris® Firestorm-class microcontrollers July 24, 2011 193 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 15:8 MAJOR RO - Description Major Revision This field specifies the major revision number of the microcontroller. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. 7:0 MINOR RO - Minor Revision This field specifies the minor revision number of the microcontroller. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. 194 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.0002 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORIOR reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORIOR R/W 1 BOR Interrupt or Reset Value Description 0 reserved RO 0 0 A Brown Out Event causes an interrupt to be generated to the interrupt controller. 1 A Brown Out Event causes a reset of the microcontroller. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 195 Texas Instruments-Production Data System Control Register 3: Raw Interrupt Status (RIS), offset 0x050 This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1 to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt status bit. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 MOSCPUPRIS reserved PLLLRIS BORRIS reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 MOSCPUPRIS RO 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MOSC Power Up Raw Interrupt Status Value Description 1 Sufficient time has passed for the MOSC to reach the expected frequency. The value for this power-up time is indicated by TMOSC_START. 0 Sufficient time has not passed for the MOSC to reach the expected frequency. This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC register. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PLLLRIS RO 0 PLL Lock Raw Interrupt Status Value Description 1 The PLL timer has reached TREADY indicating that sufficient time has passed for the PLL to lock. 0 The PLL timer has not reached TREADY. This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register. 5:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 196 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 1 BORRIS RO 0 Description Brown-Out Reset Raw Interrupt Status Value Description 1 A brown-out condition is currently active. 0 A brown-out condition is not currently active. Note the BORIOR bit in the PBORCTL register must be cleared to cause an interrupt due to a Brown Out Event. This bit is cleared by writing a 1 to the BORMIS bit in the MISC register. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 197 Texas Instruments-Production Data System Control Register 4: Interrupt Mask Control (IMC), offset 0x054 This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the corresponding bit in this register is set. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 MOSCPUPIM reserved PLLLIM BORIM reserved R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 MOSCPUPIM R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MOSC Power Up Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the MOSCPUPRIS bit in the RIS register is set. 0 The MOSCPUPRIS interrupt is suppressed and not sent to the interrupt controller. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PLLLIM R/W 0 PLL Lock Interrupt Mask Value Description 5:2 reserved RO 0x0 1 An interrupt is sent to the interrupt controller when the PLLLRIS bit in the RIS register is set. 0 The PLLLRIS interrupt is suppressed and not sent to the interrupt controller. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 198 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 1 BORIM R/W 0 Description Brown-Out Reset Interrupt Mask Value Description 0 reserved RO 0 1 An interrupt is sent to the interrupt controller when the BORRIS bit in the RIS register is set. 0 The BORRIS interrupt is suppressed and not sent to the interrupt controller. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 199 Texas Instruments-Production Data System Control Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt in the Raw Interrupt Status (RIS) register. All of the bits are R/W1C, thus writing a 1 to a bit clears the corresponding raw interrupt bit in the RIS register (see page 196). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 MOSCPUPMIS reserved PLLLMIS BORMIS reserved R/W1C 0 RO 0 R/W1C 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 MOSCPUPMIS R/W1C 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MOSC Power Up Masked Interrupt Status Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the MOSC PLL to lock. Writing a 1 to this bit clears it and also the MOSCPUPRIS bit in the RIS register. 0 When read, a 0 indicates that sufficient time has not passed for the MOSC PLL to lock. A write of 0 has no effect on the state of this bit. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PLLLMIS R/W1C 0 PLL Lock Masked Interrupt Status Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the PLL to lock. Writing a 1 to this bit clears it and also the PLLLRIS bit in the RIS register. 0 When read, a 0 indicates that sufficient time has not passed for the PLL to lock. A write of 0 has no effect on the state of this bit. 200 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 5:2 reserved RO 0x0 1 BORMIS R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. BOR Masked Interrupt Status Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because of a brown-out condition. Writing a 1 to this bit clears it and also the BORRIS bit in the RIS register. 0 When read, a 0 indicates that a brown-out condition has not occurred. A write of 0 has no effect on the state of this bit. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 201 Texas Instruments-Production Data System Control Register 6: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other than POR in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W - 9 8 7 6 5 4 3 2 1 0 WDT1 SW WDT0 BOR POR EXT RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - R/W - R/W - reserved Type Reset MOSCFAIL reserved Type Reset RO 0 16 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 MOSCFAIL R/W - MOSC Failure Reset Value Description 1 When read, this bit indicates that the MOSC circuit was enabled for clock validation and failed, generating a reset event. 0 When read, this bit indicates that a MOSC failure has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 15:6 reserved RO 0x00 5 WDT1 R/W - Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Timer 1 Reset Value Description 1 When read, this bit indicates that Watchdog Timer 1 timed out and generated a reset. 0 When read, this bit indicates that Watchdog Timer 1 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 202 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 4 SW R/W - Description Software Reset Value Description 1 When read, this bit indicates that a software reset has caused a reset event. 0 When read, this bit indicates that a software reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 3 WDT0 R/W - Watchdog Timer 0 Reset Value Description 1 When read, this bit indicates that Watchdog Timer 0 timed out and generated a reset. 0 When read, this bit indicates that Watchdog Timer 0 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 2 BOR R/W - Brown-Out Reset Value Description 1 When read, this bit indicates that a brown-out reset has caused a reset event. 0 When read, this bit indicates that a brown-out reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 1 POR R/W - Power-On Reset Value Description 1 When read, this bit indicates that a power-on reset has caused a reset event. 0 When read, this bit indicates that a power-on reset has not generated a reset. Writing a 0 to this bit clears it. 0 EXT R/W - External Reset Value Description 1 When read, this bit indicates that an external reset (RST assertion) has caused a reset event. 0 When read, this bit indicates that an external reset (RST assertion) has not caused a reset event since the previous power-on reset. Writing a 0 to this bit clears it. July 24, 2011 203 Texas Instruments-Production Data System Control Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 The bits in this register configure the system clock and oscillators. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x0780.3AD1 31 30 29 28 26 25 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 15 14 13 12 11 PWRDN reserved BYPASS R/W 1 RO 1 R/W 1 reserved Type Reset reserved Type Reset RO 0 RO 0 27 24 23 R/W 1 R/W 1 R/W 1 10 9 8 R/W 0 R/W 1 ACG 21 20 19 R/W 0 RO 0 RO 0 RO 0 7 6 5 4 3 R/W 1 R/W 1 R/W 0 R/W 1 RO 0 SYSDIV 22 XTAL Bit/Field Name Type Reset 31:28 reserved RO 0x0 27 ACG R/W 0 17 16 RO 0 RO 0 RO 0 2 1 0 reserved USESYSDIV R/W 0 18 OSCSRC reserved RO 0 IOSCDIS MOSCDIS R/W 0 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the microcontroller enters a Sleep or Deep-Sleep mode (respectively). Value Description 1 The SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the microcontroller is in a sleep mode. The SCGCn and DCGCn registers allow unused peripherals to consume less power when the microcontroller is in a sleep mode. 0 The Run-Mode Clock Gating Control (RCGCn) registers are used when the microcontroller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. 26:23 SYSDIV R/W 0xF System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). See Table 5-5 on page 185 for bit encodings. If the SYSDIV value is less than MINSYSDIV (see page 223), and the PLL is being used, then the MINSYSDIV value is used as the divisor. If the PLL is not being used, the SYSDIV value can be less than MINSYSDIV. 204 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 22 USESYSDIV R/W 0 Description Enable System Clock Divider Value Description 1 The system clock divider is the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field in the RCC2 register is used as the system clock divider rather than the SYSDIV field in this register. 0 The system clock is used undivided. 21:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 PWRDN R/W 1 PLL Power Down Value Description 1 The PLL is powered down. Care must be taken to ensure that another clock source is functioning and that the BYPASS bit is set before setting this bit. 0 The PLL is operating normally. 12 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 BYPASS R/W 1 PLL Bypass Value Description 1 The system clock is derived from the OSC source and divided by the divisor specified by SYSDIV. 0 The system clock is the PLL output clock divided by the divisor specified by SYSDIV. See Table 5-5 on page 185 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. July 24, 2011 205 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 10:6 XTAL R/W 0x0B Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Depending on the crystal used, the PLL frequency may not be exactly 400 MHz, see Table 21-8 on page 893 for more information. Value Crystal Frequency (MHz) Not Crystal Frequency (MHz) Using Using the PLL the PLL 0x00 1.000 MHz reserved 0x01 1.8432 MHz reserved 0x02 2.000 MHz reserved 0x03 2.4576 MHz reserved 0x04 3.579545 MHz 0x05 3.6864 MHz 0x06 4 MHz 0x07 4.096 MHz 0x08 4.9152 MHz 0x09 5 MHz 0x0A 5.12 MHz 0x0B 6 MHz (reset value) 0x0C 6.144 MHz 0x0D 7.3728 MHz 0x0E 8 MHz 0x0F 8.192 MHz 0x10 10.0 MHz 0x11 12.0 MHz 0x12 12.288 MHz 0x13 13.56 MHz 0x14 14.31818 MHz 0x15 16.0 MHz 0x16 16.384 MHz 206 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 5:4 OSCSRC R/W 0x1 Description Oscillator Source Selects the input source for the OSC. The values are: Value Input Source 0x0 MOSC Main oscillator 0x1 PIOSC Precision internal oscillator (default) 0x2 PIOSC/4 Precision internal oscillator / 4 0x3 30 kHz 30-kHz internal oscillator For additional oscillator sources, see the RCC2 register. 3:2 reserved RO 0x0 1 IOSCDIS R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Precision Internal Oscillator Disable Value Description 0 MOSCDIS R/W 1 1 The precision internal oscillator (PIOSC) is disabled. 0 The precision internal oscillator is enabled. Main Oscillator Disable Value Description 1 The main oscillator is disabled (default). 0 The main oscillator is enabled. July 24, 2011 207 Texas Instruments-Production Data System Control Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 204). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO - RO - RO - RO - RO - 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - reserved Type Reset reserved Type Reset RO 0 RO 0 F Bit/Field Name Type Reset 31:14 reserved RO 0x0000.0 13:5 F RO - R Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL F Value This field specifies the value supplied to the PLL’s F input. 4:0 R RO - PLL R Value This field specifies the value supplied to the PLL’s R input. 208 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C This register controls which internal bus is used to access each GPIO port. When a bit is clear, the corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and through the APB memory aperture. When a bit is set, the corresponding port is accessed across the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each GPIO port can be individually configured to use AHB or APB, but may be accessed only through one aperture. The AHB bus provides better back-to-back access performance than the APB bus. The address aperture in the memory map changes for the ports that are enabled for AHB access (see Table 9-7 on page 411). GPIO High-Performance Bus Control (GPIOHBCTL) Base 0x400F.E000 Offset 0x06C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PORTJ PORTH PORTG PORTF PORTE PORTD PORTC PORTB PORTA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:9 reserved RO 0x0000.0 8 PORTJ R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Port J Advanced High-Performance Bus This bit defines the memory aperture for Port J. Value Description 7 PORTH R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port H Advanced High-Performance Bus This bit defines the memory aperture for Port H. Value Description 6 PORTG R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port G Advanced High-Performance Bus This bit defines the memory aperture for Port G. Value Description 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. July 24, 2011 209 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 5 PORTF R/W 0 Description Port F Advanced High-Performance Bus This bit defines the memory aperture for Port F. Value Description 4 PORTE R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port E Advanced High-Performance Bus This bit defines the memory aperture for Port E. Value Description 3 PORTD R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port D Advanced High-Performance Bus This bit defines the memory aperture for Port D. Value Description 2 PORTC R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port C Advanced High-Performance Bus This bit defines the memory aperture for Port C. Value Description 1 PORTB R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port B Advanced High-Performance Bus This bit defines the memory aperture for Port B. Value Description 0 PORTA R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port A Advanced High-Performance Bus This bit defines the memory aperture for Port A. Value Description 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. 210 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields, as shown in Table 5-9, when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC field is located at the same LSB bit position; however, some RCC2 fields are larger than the corresponding RCC field. Table 5-9. RCC2 Fields that Override RCC Fields RCC2 Field... Overrides RCC Field SYSDIV2, bits[28:23] SYSDIV, bits[26:23] PWRDN2, bit[13] PWRDN, bit[13] BYPASS2, bit[11] BYPASS, bit[11] OSCSRC2, bits[6:4] OSCSRC, bits[5:4] Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x07C0.6810 31 30 USERCC2 DIV400 Type Reset R/W 0 R/W 0 15 14 reserved Type Reset RO 0 RO 0 29 28 27 26 25 24 23 SYSDIV2 reserved RO 0 R/W 0 22 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 10 9 8 7 6 13 12 11 PWRDN2 reserved BYPASS2 R/W 1 RO 0 R/W 1 reserved RO 0 21 20 19 RO 0 RO 0 Bit/Field Name Type Reset Description 31 USERCC2 R/W 0 Use RCC2 R/W 0 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 RO 0 RO 0 OSCSRC2 RO 0 18 reserved SYSDIV2LSB R/W 0 reserved R/W 1 RO 0 RO 0 Value Description 30 DIV400 R/W 0 1 The RCC2 register fields override the RCC register fields. 0 The RCC register fields are used, and the fields in RCC2 are ignored. Divide PLL as 400 MHz vs. 200 MHz This bit, along with the SYSDIV2LSB bit, allows additional frequency choices. Value Description 29 reserved RO 0x0 1 Append the SYSDIV2LSB bit to the SYSDIV2 field to create a 7 bit divisor using the 400 MHz PLL output, see Table 5-7 on page 186. 0 Use SYSDIV2 as is and apply to 200 MHz predivided PLL output. See Table 5-6 on page 185 for programming guidelines. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 211 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 28:23 SYSDIV2 R/W 0x0F System Clock Divisor 2 Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS2 bit is configured). SYSDIV2 is used for the divisor when both the USESYSDIV bit in the RCC register and the USERCC2 bit in this register are set. See Table 5-6 on page 185 for programming guidelines. 22 SYSDIV2LSB R/W 1 Additional LSB for SYSDIV2 When DIV400 is set, this bit becomes the LSB of SYSDIV2. If DIV400 is clear, this bit is not used. See Table 5-6 on page 185 for programming guidelines. This bit can only be set or cleared when DIV400 is set. 21:14 reserved RO 0x0 13 PWRDN2 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power-Down PLL 2 Value Description 1 The PLL is powered down. 0 The PLL operates normally. 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 BYPASS2 R/W 1 PLL Bypass 2 Value Description 1 The system clock is derived from the OSC source and divided by the divisor specified by SYSDIV2. 0 The system clock is the PLL output clock divided by the divisor specified by SYSDIV2. See Table 5-6 on page 185 for programming guidelines. Note: 10:7 reserved RO 0x0 The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 212 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 6:4 OSCSRC2 R/W 0x1 Description Oscillator Source 2 Selects the input source for the OSC. The values are: Value Description 0x0 MOSC Main oscillator 0x1 PIOSC Precision internal oscillator 0x2 PIOSC/4 Precision internal oscillator / 4 0x3 30 kHz 30-kHz internal oscillator 0x4-0x6 Reserved 0x7 32.768 kHz 32.768-kHz external oscillator 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 213 Texas Instruments-Production Data System Control Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C This register provides the ability to enable the MOSC clock verification circuit. When enabled, this circuit monitors the frequency of the MOSC to verify that the oscillator is operating within specified limits. If the clock goes invalid after being enabled, the microcontroller issues a power-on reset and reboots to the NMI handler. Main Oscillator Control (MOSCCTL) Base 0x400F.E000 Offset 0x07C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 CVAL R/W 0 RO 0 CVAL R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Validation for MOSC Value Description 1 The MOSC monitor circuit is enabled. 0 The MOSC monitor circuit is disabled. 214 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 29 28 27 26 reserved Type Reset 25 24 23 22 21 20 DSDIVORIDE 18 17 16 reserved RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 19 DSOSCSRC RO 0 Bit/Field Name Type Reset 31:29 reserved RO 0x0 28:23 DSDIVORIDE R/W 0x0F R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Divider Field Override If Deep-Sleep mode is enabled when the PLL is running, the PLL is disabled. This 6-bit field contains a system divider field that overrides the SYSDIV field in the RCC register or the SYSDIV2 field in the RCC2 register during Deep Sleep. This divider is applied to the source selected by the DSOSCSRC field. Value Description 0x0 /1 0x1 /2 0x2 /3 0x3 /4 ... ... 0x3F /64 22:7 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 215 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 6:4 DSOSCSRC R/W 0x0 Description Clock Source Specifies the clock source during Deep-Sleep mode. Value Description 0x0 MOSC Use the main oscillator as the source. Note: 0x1 If the PIOSC is being used as the clock reference for the PLL, the PIOSC is the clock source instead of MOSC in Deep-Sleep mode. PIOSC Use the precision internal 16-MHz oscillator as the source. 0x2 Reserved 0x3 30 kHz Use the 30-kHz internal oscillator as the source. 0x4-0x6 Reserved 0x7 32.768 kHz Use the Hibernation module 32.768-kHz external oscillator as the source. 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 216 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 This register provides the ability to update or recalibrate the precision internal oscillator. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC. Precision Internal Oscillator Calibration (PIOSCCAL) Base 0x400F.E000 Offset 0x150 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 22 21 20 19 18 17 16 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 CAL UPDATE reserved R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 UTEN Type Reset reserved reserved Type Reset 23 RO 0 Bit/Field Name Type Reset 31 UTEN R/W 0 UT Description Use User Trim Value Value Description 30:10 reserved RO 0x0000 9 CAL R/W 0 1 The trim value in bits[6:0] of this register are used for any update trim operation. 0 The factory calibration value is used for an update trim operation. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Start Calibration Value Description 1 Starts a new calibration of the PIOSC. Results are in the PIOSCSTAT register. The resulting trim value from the operation is active in the PIOSC after the calibration completes. The result overrides any previous update trim operation whether the calibration passes or fails. 0 No action. This bit is auto-cleared after it is set. 8 UPDATE R/W 0 Update Trim Value Description 1 Updates the PIOSC trim value with the UT bit or the DT bit in the PIOSCSTAT register. Used with UTEN. 0 No action. This bit is auto-cleared after the update. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 217 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 6:0 UT R/W 0x0 Description User Trim Value User trim value that can be loaded into the PIOSC. Refer to “Main PLL Frequency Configuration” on page 187 for more information on calibrating the PIOSC. 218 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 14: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 This register provides the user information on the PIOSC calibration. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC. Precision Internal Oscillator Statistics (PIOSCSTAT) Base 0x400F.E000 Offset 0x154 Type RO, reset 0x0000.0040 31 30 29 28 RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO - RO - RO - RO - RO - RO - RO - 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset DT reserved Type Reset RO 0 RESULT CT reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:16 DT RO - Default Trim Value This field contains the default trim value. This value is loaded into the PIOSC after every full power-up. 15:10 reserved RO 0x0 9:8 RESULT RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Calibration Result Value Description 7 reserved RO 0 6:0 CT RO 0x40 0x0 Calibration has not been attempted. 0x1 The last calibration operation completed to meet 1% accuracy. 0x2 The last calibration operation failed to meet 1% accuracy. 0x3 Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Calibration Trim Value This field contains the trim value from the last calibration operation. After factory calibration CT and DT are the same. July 24, 2011 219 Texas Instruments-Production Data System Control Register 15: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 31 30 29 28 27 26 RO 0 15 25 24 23 22 21 20 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 14 13 12 11 10 9 8 7 6 5 4 RO 0 RO 0 RO 0 RO 0 RO 0 RO - RO - RO - VER Type Reset FAM PINCOUNT Type Reset RO 0 RO 1 18 17 16 RO 1 RO 1 RO 0 RO 1 3 2 1 0 PARTNO reserved RO 0 19 TEMP Bit/Field Name Type Reset 31:28 VER RO 0x1 RO - PKG ROHS RO - RO 1 QUAL RO - RO - Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 27:24 FAM RO 0x0 Second version of the DID1 register format. Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 23:16 PARTNO RO 0x1D Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0x1D LM3S1F11 15:13 PINCOUNT RO 0x2 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin package 220 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 12:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 TEMP RO - Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 4:3 PKG RO - 0x0 Commercial temperature range (0°C to 70°C) 0x1 Industrial temperature range (-40°C to 85°C) 0x2 Extended temperature range (-40°C to 105°C) Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 2 ROHS RO 1 0x0 SOIC package 0x1 LQFP package 0x2 BGA package RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 1:0 QUAL RO - Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified July 24, 2011 221 Texas Instruments-Production Data System Control Register 16: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00BF.00BF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 1 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 SRAMSZ Type Reset FLASHSZ Type Reset RO 1 Bit/Field Name Type Reset Description 31:16 SRAMSZ RO 0x00BF SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x00BF 48 KB of SRAM 15:0 FLASHSZ RO 0x00BF Flash Size Indicates the size of the on-chip flash memory. Value Description 0x00BF 384 KB of Flash 222 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 17: Device Capabilities 1 (DC1), offset 0x010 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 31 30 29 reserved Type Reset 28 26 25 24 23 WDT1 22 21 20 19 18 17 reserved 16 ADC0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MPU HIB TEMPSNS PLL WDT0 SWO SWD JTAG RO - RO - RO - RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 MINSYSDIV Type Reset 27 RO - reserved RO 0 MAXADC0SPD RO 1 RO 1 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 RO 1 Watchdog Timer 1 Present When set, indicates that watchdog timer 1 is present. 27:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC0 RO 1 ADC Module 0 Present When set, indicates that ADC module 0 is present 15:12 MINSYSDIV RO - System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 11:10 reserved RO 0 0x1 Specifies an 80-MHz CPU clock with a PLL divider of 2.5. 0x2 Specifies a 66.67-MHz CPU clock with a PLL divider of 3. 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 0x7 Specifies a 25-MHz clock with a PLL divider of 8. 0x9 Specifies a 20-MHz clock with a PLL divider of 10. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 223 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 9:8 MAXADC0SPD RO 0x3 Description Max ADC0 Speed This field indicates the maximum rate at which the ADC samples data. Value Description 0x3 7 MPU RO 1 1M samples/second MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the "Cortex-M3 Peripherals" chapter for details on the MPU. 6 HIB RO 1 Hibernation Module Present When set, indicates that the Hibernation module is present. 5 TEMPSNS RO 1 Temp Sensor Present When set, indicates that the on-chip temperature sensor is present. 4 PLL RO 1 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 3 WDT0 RO 1 Watchdog Timer 0 Present When set, indicates that watchdog timer 0 is present. 2 SWO RO 1 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 1 SWD RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 0 JTAG RO 1 JTAG Present When set, indicates that the JTAG debugger interface is present. 224 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 18: Device Capabilities 2 (DC2), offset 0x014 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x430F.5037 Type Reset Type Reset 31 30 29 28 reserved EPI0 RO 0 27 26 25 24 RO 1 RO 0 RO 0 RO 0 RO 0 COMP1 COMP0 RO 1 15 14 13 12 11 10 9 reserved I2C1 reserved I2C0 RO 0 RO 1 RO 0 RO 1 RO 0 RO 0 RO 0 reserved 23 22 21 20 19 18 17 16 RO 1 RO 0 RO 0 RO 0 RO 0 TIMER3 TIMER2 TIMER1 TIMER0 RO 1 RO 1 RO 1 RO 1 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 SSI1 SSI0 reserved UART2 UART1 UART0 RO 1 RO 1 RO 0 RO 1 RO 1 RO 1 reserved reserved Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPI0 RO 1 EPI Module 0 Present When set, indicates that EPI module 0 is present. 29:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 RO 1 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 24 COMP0 RO 1 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 RO 1 Timer Module 3 Present When set, indicates that General-Purpose Timer module 3 is present. 18 TIMER2 RO 1 Timer Module 2 Present When set, indicates that General-Purpose Timer module 2 is present. 17 TIMER1 RO 1 Timer Module 1 Present When set, indicates that General-Purpose Timer module 1 is present. 16 TIMER0 RO 1 Timer Module 0 Present When set, indicates that General-Purpose Timer module 0 is present. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 225 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 14 I2C1 RO 1 Description I2C Module 1 Present When set, indicates that I2C module 1 is present. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 RO 1 I2C Module 0 Present When set, indicates that I2C module 0 is present. 11:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 RO 1 SSI Module 1 Present When set, indicates that SSI module 1 is present. 4 SSI0 RO 1 SSI Module 0 Present When set, indicates that SSI module 0 is present. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 RO 1 UART Module 2 Present When set, indicates that UART module 2 is present. 1 UART1 RO 1 UART Module 1 Present When set, indicates that UART module 1 is present. 0 UART0 RO 1 UART Module 0 Present When set, indicates that UART module 0 is present. 226 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 19: Device Capabilities 3 (DC3), offset 0x018 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0xBFFF.0FC0 Type Reset 31 30 29 28 27 26 25 24 32KHZ reserved CCP5 CCP4 CCP3 CCP2 CCP1 CCP0 RO 1 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset C1O RO 0 RO 0 C1PLUS C1MINUS RO 1 RO 1 RO 1 Bit/Field Name Type Reset 31 32KHZ RO 1 C0O RO 1 23 22 21 20 19 18 17 16 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 C0PLUS C0MINUS RO 1 RO 1 reserved Description 32KHz Input Clock Available When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock. 30 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 CCP5 RO 1 CCP5 Pin Present When set, indicates that Capture/Compare/PWM pin 5 is present. 28 CCP4 RO 1 CCP4 Pin Present When set, indicates that Capture/Compare/PWM pin 4 is present. 27 CCP3 RO 1 CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 26 CCP2 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 25 CCP1 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 24 CCP0 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 23 ADC0AIN7 RO 1 ADC Module 0 AIN7 Pin Present When set, indicates that ADC module 0 input pin 7 is present. 22 ADC0AIN6 RO 1 ADC Module 0 AIN6 Pin Present When set, indicates that ADC module 0 input pin 6 is present. 21 ADC0AIN5 RO 1 ADC Module 0 AIN5 Pin Present When set, indicates that ADC module 0 input pin 5 is present. July 24, 2011 227 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 20 ADC0AIN4 RO 1 Description ADC Module 0 AIN4 Pin Present When set, indicates that ADC module 0 input pin 4 is present. 19 ADC0AIN3 RO 1 ADC Module 0 AIN3 Pin Present When set, indicates that ADC module 0 input pin 3 is present. 18 ADC0AIN2 RO 1 ADC Module 0 AIN2 Pin Present When set, indicates that ADC module 0 input pin 2 is present. 17 ADC0AIN1 RO 1 ADC Module 0 AIN1 Pin Present When set, indicates that ADC module 0 input pin 1 is present. 16 ADC0AIN0 RO 1 ADC Module 0 AIN0 Pin Present When set, indicates that ADC module 0 input pin 0 is present. 15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 C1O RO 1 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present. 10 C1PLUS RO 1 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 9 C1MINUS RO 1 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. 8 C0O RO 1 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 7 C0PLUS RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 6 C0MINUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 5:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 228 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 20: Device Capabilities 4 (DC4), offset 0x01C This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x0004.F1FF 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 CCP7 CCP6 UDMA ROM RO 1 RO 1 RO 1 RO 1 25 24 23 22 21 20 19 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 9 8 7 6 5 4 3 2 1 0 GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 reserved Type Reset Type Reset reserved RO 0 RO 0 RO 0 18 17 PICAL 16 reserved Bit/Field Name Type Reset Description 31:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 PICAL RO 1 PIOSC Calibrate When set, indicates that the PIOSC can be calibrated. 17:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 CCP7 RO 1 CCP7 Pin Present When set, indicates that Capture/Compare/PWM pin 7 is present. 14 CCP6 RO 1 CCP6 Pin Present When set, indicates that Capture/Compare/PWM pin 6 is present. 13 UDMA RO 1 Micro-DMA Module Present When set, indicates that the micro-DMA module present. 12 ROM RO 1 Internal Code ROM Present When set, indicates that internal code ROM is present. 11:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ RO 1 GPIO Port J Present When set, indicates that GPIO Port J is present. 7 GPIOH RO 1 GPIO Port H Present When set, indicates that GPIO Port H is present. 6 GPIOG RO 1 GPIO Port G Present When set, indicates that GPIO Port G is present. July 24, 2011 229 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 5 GPIOF RO 1 Description GPIO Port F Present When set, indicates that GPIO Port F is present. 4 GPIOE RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 3 GPIOD RO 1 GPIO Port D Present When set, indicates that GPIO Port D is present. 2 GPIOC RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 1 GPIOB RO 1 GPIO Port B Present When set, indicates that GPIO Port B is present. 0 GPIOA RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. 230 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 21: Device Capabilities 5 (DC5), offset 0x020 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 5 (DC5) Base 0x400F.E000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 231 Texas Instruments-Production Data System Control Register 22: Device Capabilities 6 (DC6), offset 0x024 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 6 (DC6) Base 0x400F.E000 Offset 0x024 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 232 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 23: Device Capabilities 7 (DC7), offset 0x028 This register is predefined by the part and can be used to verify uDMA channel features. A 1 indicates the channel is available on this device; a 0 that the channel is only available on other devices in the family. Most channels have primary and secondary assignments. If the primary function is not available on this microcontroller, the secondary function becomes the primary function. If the secondary function is not available, the primary function is the only option. Device Capabilities 7 (DC7) Base 0x400F.E000 Offset 0x028 Type RO, reset 0xFFFF.FFFF 31 reserved Type Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 DMACH3 DMACH2 DMACH1 DMACH0 Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset 31 reserved RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Description Reserved Reserved for uDMA channel 31. 30 DMACH30 RO 1 SW When set, indicates uDMA channel 30 is available for software transfers. 29 DMACH29 RO 1 I2S0_TX / CAN1_TX When set, indicates uDMA channel 29 is available and connected to the transmit path of I2S module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of CAN module 1 transmit. 28 DMACH28 RO 1 I2S0_RX / CAN1_RX When set, indicates uDMA channel 28 is available and connected to the receive path of I2S module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of CAN module 1 receive. 27 DMACH27 RO 1 CAN1_TX / ADC1_SS3 When set, indicates uDMA channel 27 is available and connected to the transmit path of CAN module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 3. 26 DMACH26 RO 1 CAN1_RX / ADC1_SS2 When set, indicates uDMA channel 26 is available and connected to the receive path of CAN module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 2. July 24, 2011 233 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 25 DMACH25 RO 1 Description SSI1_TX / ADC1_SS1 When set, indicates uDMA channel 25 is available and connected to the transmit path of SSI module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 1. 24 DMACH24 RO 1 SSI1_RX / ADC1_SS0 When set, indicates uDMA channel 24 is available and connected to the receive path of SSI module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 0. 23 DMACH23 RO 1 UART1_TX / CAN2_TX When set, indicates uDMA channel 23 is available and connected to the transmit path of UART module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of CAN module 2 transmit. 22 DMACH22 RO 1 UART1_RX / CAN2_RX When set, indicates uDMA channel 22 is available and connected to the receive path of UART module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of CAN module 2 receive. 21 DMACH21 RO 1 Timer1B / EPI0_WFIFO When set, indicates uDMA channel 21 is available and connected to Timer 1B. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of EPI module 0 write FIFO (WRIFO). 20 DMACH20 RO 1 Timer1A / EPI0_NBRFIFO When set, indicates uDMA channel 20 is available and connected to Timer 1A. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of EPI module 0 non-blocking read FIFO (NBRFIFO). 19 DMACH19 RO 1 Timer0B / Timer1B When set, indicates uDMA channel 19 is available and connected to Timer 0B. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 1B. 18 DMACH18 RO 1 Timer0A / Timer1A When set, indicates uDMA channel 18 is available and connected to Timer 0A. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 1A. 17 DMACH17 RO 1 ADC0_SS3 When set, indicates uDMA channel 17 is available and connected to ADC module 0 Sample Sequencer 3. 16 DMACH16 RO 1 ADC0_SS2 When set, indicates uDMA channel 16 is available and connected to ADC module 0 Sample Sequencer 2. 234 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 15 DMACH15 RO 1 Description ADC0_SS1 / Timer2B When set, indicates uDMA channel 15 is available and connected to ADC module 0 Sample Sequencer 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2B. 14 DMACH14 RO 1 ADC0_SS0 / Timer2A When set, indicates uDMA channel 14 is available and connected to ADC module 0 Sample Sequencer 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2A. 13 DMACH13 RO 1 CAN0_TX / UART2_TX When set, indicates uDMA channel 13 is available and connected to the transmit path of CAN module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 2 transmit. 12 DMACH12 RO 1 CAN0_RX / UART2_RX When set, indicates uDMA channel 12 is available and connected to the receive path of CAN module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 2 receive. 11 DMACH11 RO 1 SSI0_TX / SSI1_TX When set, indicates uDMA channel 11 is available and connected to the transmit path of SSI module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of SSI module 1 transmit. 10 DMACH10 RO 1 SSI0_RX / SSI1_RX When set, indicates uDMA channel 10 is available and connected to the receive path of SSI module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of SSI module 1 receive. 9 DMACH9 RO 1 UART0_TX / UART1_TX When set, indicates uDMA channel 9 is available and connected to the transmit path of UART module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 1 transmit. 8 DMACH8 RO 1 UART0_RX / UART1_RX When set, indicates uDMA channel 8 is available and connected to the receive path of UART module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 1 receive. 7 DMACH7 RO 1 ETH_TX / Timer2B When set, indicates uDMA channel 7 is available and connected to the transmit path of the Ethernet module. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2B. July 24, 2011 235 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 6 DMACH6 RO 1 Description ETH_RX / Timer2A When set, indicates uDMA channel 6 is available and connected to the receive path of the Ethernet module. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2A. 5 DMACH5 RO 1 USB_EP3_TX / Timer2B When set, indicates uDMA channel 5 is available and connected to the transmit path of USB endpoint 3. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2B. 4 DMACH4 RO 1 USB_EP3_RX / Timer2A When set, indicates uDMA channel 4 is available and connected to the receive path of USB endpoint 3. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2A. 3 DMACH3 RO 1 USB_EP2_TX / Timer3B When set, indicates uDMA channel 3 is available and connected to the transmit path of USB endpoint 2. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 3B. 2 DMACH2 RO 1 USB_EP2_RX / Timer3A When set, indicates uDMA channel 2 is available and connected to the receive path of USB endpoint 2. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 3A. 1 DMACH1 RO 1 USB_EP1_TX / UART2_TX When set, indicates uDMA channel 1 is available and connected to the transmit path of USB endpoint 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 2 transmit. 0 DMACH0 RO 1 USB_EP1_RX / UART2_RX When set, indicates uDMA channel 0 is available and connected to the receive path of USB endpoint 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 2 receive. 236 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 24: Device Capabilities 8 ADC Channels (DC8), offset 0x02C This register is predefined by the part and can be used to verify features. Device Capabilities 8 ADC Channels (DC8) Base 0x400F.E000 Offset 0x02C Type RO, reset 0x0000.00FF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset reserved Type Reset ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 ADC0AIN7 RO 1 ADC Module 0 AIN7 Pin Present When set, indicates that ADC module 0 input pin 7 is present. 6 ADC0AIN6 RO 1 ADC Module 0 AIN6 Pin Present When set, indicates that ADC module 0 input pin 6 is present. 5 ADC0AIN5 RO 1 ADC Module 0 AIN5 Pin Present When set, indicates that ADC module 0 input pin 5 is present. 4 ADC0AIN4 RO 1 ADC Module 0 AIN4 Pin Present When set, indicates that ADC module 0 input pin 4 is present. 3 ADC0AIN3 RO 1 ADC Module 0 AIN3 Pin Present When set, indicates that ADC module 0 input pin 3 is present. 2 ADC0AIN2 RO 1 ADC Module 0 AIN2 Pin Present When set, indicates that ADC module 0 input pin 2 is present. 1 ADC0AIN1 RO 1 ADC Module 0 AIN1 Pin Present When set, indicates that ADC module 0 input pin 1 is present. 0 ADC0AIN0 RO 1 ADC Module 0 AIN0 Pin Present When set, indicates that ADC module 0 input pin 0 is present. July 24, 2011 237 Texas Instruments-Production Data System Control Register 25: Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 This register is predefined by the part and can be used to verify features. Device Capabilities 9 ADC Digital Comparators (DC9) Base 0x400F.E000 Offset 0x190 Type RO, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 ADC0DC7 ADC0DC6 ADC0DC5 ADC0DC4 ADC0DC3 ADC0DC2 ADC0DC1 ADC0DC0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 ADC0DC7 RO 1 ADC0 DC7 Present When set, indicates that ADC module 0 Digital Comparator 7 is present. 6 ADC0DC6 RO 1 ADC0 DC6 Present When set, indicates that ADC module 0 Digital Comparator 6 is present. 5 ADC0DC5 RO 1 ADC0 DC5 Present When set, indicates that ADC module 0 Digital Comparator 5 is present. 4 ADC0DC4 RO 1 ADC0 DC4 Present When set, indicates that ADC module 0 Digital Comparator 4 is present. 3 ADC0DC3 RO 1 ADC0 DC3 Present When set, indicates that ADC module 0 Digital Comparator 3 is present. 2 ADC0DC2 RO 1 ADC0 DC2 Present When set, indicates that ADC module 0 Digital Comparator 2 is present. 1 ADC0DC1 RO 1 ADC0 DC1 Present When set, indicates that ADC module 0 Digital Comparator 1 is present. 0 ADC0DC0 RO 1 ADC0 DC0 Present When set, indicates that ADC module 0 Digital Comparator 0 is present. 238 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 26: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 This register is predefined by the part and can be used to verify features. Non-Volatile Memory Information (NVMSTAT) Base 0x400F.E000 Offset 0x1A0 Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 FWB RO 1 Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 FWB RO 1 32 Word Flash Write Buffer Active When set, indicates that the 32 word Flash memory write buffer feature is active. July 24, 2011 239 Texas Instruments-Production Data System Control Register 27: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 reserved Type Reset 28 27 26 25 24 23 WDT1 21 20 19 18 17 reserved 16 ADC0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 22 RO 0 MAXADC0SPD R/W 0 R/W 0 reserved HIB RO 0 R/W 1 reserved RO 0 RO 0 WDT0 R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 R/W 0 WDT1 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC0 R/W 0 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 240 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 9:8 MAXADC0SPD R/W 0 Description ADC0 Sample Speed This field sets the rate at which ADC0 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADC0SPD bit as follows (all other encodings are reserved): Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 1 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT0 R/W 0 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 241 Texas Instruments-Production Data System Control Register 28: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 reserved Type Reset 28 27 26 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 24 23 RO 0 RO 0 22 21 20 19 18 17 reserved reserved Type Reset 25 WDT1 RO 0 RO 0 9 8 MAXADC0SPD RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 5 4 7 6 reserved HIB RO 0 R/W 1 16 ADC0 reserved RO 0 RO 0 RO 0 RO 0 3 2 WDT0 R/W 0 RO 0 R/W 0 1 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 R/W 0 WDT1 Clock Gating Control This bit controls the clock gating for Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC0 R/W 0 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 242 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 9:8 MAXADC0SPD R/W 0 Description ADC0 Sample Speed This field sets the rate at which ADC module 0 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADC0SPD bit as follows (all other encodings are reserved): Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 1 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT0 R/W 0 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 243 Texas Instruments-Production Data System Control Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 reserved Type Reset 28 27 26 25 24 23 WDT1 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 22 21 20 19 18 17 reserved RO 0 RO 0 RO 0 6 5 4 HIB RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 16 ADC0 reserved RO 0 RO 0 RO 0 RO 0 3 2 WDT0 R/W 0 RO 0 R/W 0 1 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 R/W 0 WDT1 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC0 R/W 0 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 244 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 6 HIB R/W 1 Description HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT0 R/W 0 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 245 Texas Instruments-Production Data System Control Register 30: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 Type Reset Type Reset 31 30 29 28 reserved EPI0 RO 0 27 26 25 24 R/W 0 RO 0 RO 0 RO 0 RO 0 COMP1 COMP0 R/W 0 15 14 13 12 11 10 9 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 reserved 23 22 21 20 19 18 17 16 R/W 0 RO 0 RO 0 RO 0 RO 0 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved reserved Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPI0 R/W 0 EPI0 Clock Gating This bit controls the clock gating for EPI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 29:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 246 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 R/W 0 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 11:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 24, 2011 247 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 4 SSI0 R/W 0 Description SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 248 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 31: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 Type Reset Type Reset 31 30 reserved EPI0 RO 0 R/W 0 29 28 27 26 reserved RO 0 25 24 COMP1 COMP0 23 22 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 11 10 9 8 7 6 15 14 13 12 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 reserved RO 0 RO 0 RO 0 RO 0 21 20 reserved RO 0 RO 0 RO 0 RO 0 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 5 4 3 2 1 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPI0 R/W 0 EPI0 Clock Gating This bit controls the clock gating for EPI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 29:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 24, 2011 249 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 R/W 0 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 11:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 250 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 4 SSI0 R/W 0 Description SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 24, 2011 251 Texas Instruments-Production Data System Control Register 32: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 Type Reset Type Reset 31 30 reserved EPI0 RO 0 R/W 0 29 28 27 26 reserved RO 0 25 24 COMP1 COMP0 23 22 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 11 10 9 8 7 6 15 14 13 12 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 reserved RO 0 RO 0 RO 0 RO 0 21 20 reserved RO 0 RO 0 RO 0 RO 0 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 5 4 3 2 1 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPI0 R/W 0 EPI0 Clock Gating This bit controls the clock gating for EPI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 29:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 252 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 R/W 0 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 11:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 24, 2011 253 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 4 SSI0 R/W 0 Description SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 254 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 33: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 UDMA R/W 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA R/W 0 Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 12:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ R/W 0 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 7 GPIOH R/W 0 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 24, 2011 255 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 6 GPIOG R/W 0 Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 256 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 34: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 15 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 13 12 11 10 9 UDMA R/W 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA R/W 0 Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 12:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ R/W 0 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 7 GPIOH R/W 0 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 24, 2011 257 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 6 GPIOG R/W 0 Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 258 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 35: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 15 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 13 12 11 10 9 UDMA R/W 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA R/W 0 Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 12:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ R/W 0 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 7 GPIOH R/W 0 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 24, 2011 259 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 6 GPIOG R/W 0 Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 260 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 36: Software Reset Control 0 (SRCR0), offset 0x040 This register allows individual modules to be reset. Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 reserved Type Reset 27 26 25 24 23 WDT1 21 20 19 18 17 reserved 16 ADC0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset 22 HIB RO 0 reserved RO 0 RO 0 WDT0 R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 R/W 0 WDT1 Reset Control When this bit is set, Watchdog Timer module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 27:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC0 R/W 0 ADC0 Reset Control When this bit is set, ADC module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 15:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 0 HIB Reset Control When this bit is set, the Hibernation module is reset. All internal data is lost and the registers are returned to their reset states.This bit must be manually cleared after being set. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT0 R/W 0 WDT0 Reset Control When this bit is set, Watchdog Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. July 24, 2011 261 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 2:0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 262 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 37: Software Reset Control 1 (SRCR1), offset 0x044 This register allows individual modules to be reset. Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 Type Reset Type Reset 31 30 29 28 reserved EPI0 RO 0 27 26 25 24 R/W 0 RO 0 RO 0 RO 0 RO 0 COMP1 COMP0 R/W 0 15 14 13 12 11 10 9 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 reserved 23 22 21 20 19 18 17 16 R/W 0 RO 0 RO 0 RO 0 RO 0 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved reserved Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 EPI0 R/W 0 EPI0 Reset Control When this bit is set, EPI module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 29:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comp 1 Reset Control When this bit is set, Analog Comparator module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 24 COMP0 R/W 0 Analog Comp 0 Reset Control When this bit is set, Analog Comparator module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 R/W 0 Timer 3 Reset Control Timer 3 Reset Control. When this bit is set, General-Purpose Timer module 3 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 18 TIMER2 R/W 0 Timer 2 Reset Control When this bit is set, General-Purpose Timer module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. July 24, 2011 263 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 17 TIMER1 R/W 0 Description Timer 1 Reset Control When this bit is set, General-Purpose Timer module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 16 TIMER0 R/W 0 Timer 0 Reset Control When this bit is set, General-Purpose Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Reset Control When this bit is set, I2C module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Reset Control When this bit is set, I2C module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 11:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Reset Control When this bit is set, SSI module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 4 SSI0 R/W 0 SSI0 Reset Control When this bit is set, SSI module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Reset Control When this bit is set, UART module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 1 UART1 R/W 0 UART1 Reset Control When this bit is set, UART module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 264 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 UART0 R/W 0 Description UART0 Reset Control When this bit is set, UART module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. July 24, 2011 265 Texas Instruments-Production Data System Control Register 38: Software Reset Control 2 (SRCR2), offset 0x048 This register allows individual modules to be reset. Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 UDMA R/W 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA R/W 0 Micro-DMA Reset Control When this bit is set, uDMA module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 12:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ R/W 0 Port J Reset Control When this bit is set, Port J module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 7 GPIOH R/W 0 Port H Reset Control When this bit is set, Port H module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 6 GPIOG R/W 0 Port G Reset Control When this bit is set, Port G module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 5 GPIOF R/W 0 Port F Reset Control When this bit is set, Port F module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 4 GPIOE R/W 0 Port E Reset Control When this bit is set, Port E module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 266 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 3 GPIOD R/W 0 Description Port D Reset Control When this bit is set, Port D module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 2 GPIOC R/W 0 Port C Reset Control When this bit is set, Port C module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 1 GPIOB R/W 0 Port B Reset Control When this bit is set, Port B module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0 GPIOA R/W 0 Port A Reset Control When this bit is set, Port A module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. July 24, 2011 267 Texas Instruments-Production Data Hibernation Module 6 Hibernation Module The Hibernation Module manages removal and restoration of power to provide a means for reducing power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation module remaining powered. Power can be restored based on an external signal or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power supply. The Hibernation module has the following features: ■ 32-bit real-time counter (RTC) – Two 32-bit RTC match registers for timed wake-up and interrupt generation – RTC predivider trim for making fine adjustments to the clock rate ■ Two mechanisms for power control – System power control using discrete external regulator – On-chip power control using internal switches under register control ■ Dedicated pin for waking using an external signal ■ RTC operational and hibernation memory valid as long as VBAT is valid ■ Low-battery detection, signaling, and interrupt generation ■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal; 32.768-kHz external oscillator can be used for main controller clock ■ 64 32-bit words of non-volatile memory to save state during hibernation ■ Programmable interrupts for RTC match, external wake, and low battery events 268 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 6.1 Block Diagram Figure 6-1. Hibernation Module Block Diagram HIBCTL.CLK32EN XOSC0 Interrupts HIBIM HIBRIS HIBMIS HIBIC Pre-Divider XOSC1 HIBRTCT /128 HIBCTL.CLKSEL RTC HIBRTCC HIBRTCLD HIBRTCM0 HIBRTCM1 Non-Volatile Memory 64 words HIBDATA Clock Source for System Clock Interrupts to CPU MATCH0/1 HIBCTL.RTCEN WAKE LOWBAT Power Sequence Logic Low Battery Detect VBAT HIBCTL.LOWBATEN HIB HIBCTL.PWRCUT HIBCTL.RTCWEN HIBCTL.EXTWEN HIBCTL.VABORT HIBCTL.HIBREQ 6.2 Signal Description The following table lists the external signals of the Hibernation module and describes the function of each. These signals have dedicated functions and are not alternate functions for any GPIO signals. Table 6-1. Signals for Hibernate (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description HIB 51 fixed O OD An output that indicates the processor is in Hibernate mode. VBAT 55 fixed - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE 50 fixed I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 52 fixed I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a 4.194304-MHz crystal or a 32.768-kHz oscillator for the Hibernation module RTC. See the CLKSEL bit in the HIBCTL register. XOSC1 53 fixed O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 24, 2011 269 Texas Instruments-Production Data Hibernation Module Table 6-2. Signals for Hibernate (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description HIB M12 fixed O OD An output that indicates the processor is in Hibernate mode. VBAT L12 fixed - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE M10 fixed I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 K11 fixed I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a 4.194304-MHz crystal or a 32.768-kHz oscillator for the Hibernation module RTC. See the CLKSEL bit in the HIBCTL register. XOSC1 K12 fixed O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 6.3 Functional Description Important: The Hibernate module must have either the RTC function or the External Wake function enabled to ensure proper operation of the microcontroller. See “Initialization” on page 275. The Hibernation module provides two mechanisms for power control: ■ The first mechanism controls the power to the microcontroller with a control signal (HIB) that signals an external voltage regulator to turn on or off. ■ The second mechanism uses internal switches to control power to the Cortex-M3 as well as to most analog and digital functions while retaining I/O pin power (VDD3ON mode). The Hibernation module power source is determined dynamically. The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage source (VBAT). The Hibernation module also has an independent clock source to maintain a real-time clock (RTC) when the system clock is powered down. Once in hibernation, the module signals an external voltage regulator to turn the power back on when an external pin (WAKE) is asserted or when the internal RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is low and optionally prevent hibernation when this occurs. When waking from hibernation, the HIB signal is deasserted. The return of VDD causes a POR to be executed. The time from when the WAKE signal is asserted to when code begins execution is equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TIRPOR). 6.3.1 Register Access Timing Because the Hibernation module has an independent clocking domain, certain registers must be written only with a timing gap between accesses. The delay time is tHIB_REG_ACCESS, therefore software must guarantee that this delay is inserted between back-to-back writes to certain Hibernation registers or between a write followed by a read to those same registers. Software may make use of the WRC bit in the Hibernation Control (HIBCTL) register to ensure that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to 270 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller software that another write or read may be started safely. Software should poll HIBCTL for WRC=1 prior to accessing any affected register. The following registers are subject to this timing restriction: ■ Hibernation RTC Counter (HIBRTCC) ■ Hibernation RTC Match 0 (HIBRTCM0) ■ Hibernation RTC Match 1 (HIBRTCM1) ■ Hibernation RTC Load (HIBRTCLD) ■ Hibernation RTC Trim (HIBRTCT) ■ Hibernation Data (HIBDATA) Back-to-back reads from Hibernation module registers have no timing restrictions. Reads are performed at the full peripheral clock rate. 6.3.2 Hibernation Clock Source In systems where the Hibernation module is used to put the microcontroller into hibernation, the module must be clocked by an external source that is independent from the main system clock, even if the RTC feature is not used. An external oscillator or crystal is used for this purpose. To use a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to produce a 32.768-kHz Hibernation clock reference. Alternatively, a 32.768-kHz oscillator can be connected to the XOSC0 pin, leaving XOSC1 unconnected. Care must be taken that the voltage amplitude of the 32.768-kHz oscillator is less than VBAT, otherwise, the Hibernation module may draw power from the oscillator and not VBAT during hibernation. See Figure 6-2 on page 272 and Figure 6-3 on page 272. Note that these diagrams only show the connection to the Hibernation pins and not to the full system. See “Hibernation Module” on page 895 for specific values. The Hibernation clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock source is selected by clearing the CLKSEL bit for a 4.194304-MHz crystal and setting the CLKSEL bit for a 32.768-kHz oscillator. If a crystal is used for the clock source, the software must leave a delay of tHIBOSC_START after writing to the CLK32EN bit and before any other accesses to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for the clock source, no delay is needed. July 24, 2011 271 Texas Instruments-Production Data Hibernation Module Figure 6-2. Using a Crystal as the Hibernation Clock Source Stellaris® Microcontroller Regulator or Switch Input Voltage IN OUT VDD EN XOSC0 X1 RL XOSC1 C1 C2 HIB WAKE RPU1 Open drain external wake up circuit Note: VBAT GND 3V Battery RPU2 X1 = Crystal frequency is fXOSC_XTAL. C1,2 = Capacitor value derived from crystal vendor load capacitance specifications. RL = Load resistor is RXOSC_LOAD. RPU1 = Pull-up resistor 1 (value and voltage source (VBAT or Input Voltage) determined by regulator or switch enable input characteristics). RPU2 = Pull-up resistor 2 is 200 kΩ See “Hibernation Module” on page 895 for specific parameter values. Figure 6-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode Stellaris® Microcontroller Regulator Input Voltage IN OUT VDD Clock Source XOSC0 (fEXT_OSC) N.C. XOSC1 HIB WAKE Open drain external wake up circuit Note: VBAT GND RPU 3V Battery RPU = Pull-up resistor is 1 MΩ If the application does not require the use of the Hibernation module, refer to “Connections for Unused Signals” on page 884 for more information on how to connect the unused signals. In this situation, the HIB bit in the Run Mode Clock Gating Control Register 0 (RCGC0) register must be cleared, disabling the system clock to the Hibernation module and Hibernation module registers are not accessible. 272 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 6.3.3 Battery Management Important: System-level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. The Hibernation module can be independently powered by a battery or an auxiliary power source. The module can monitor the voltage level of the battery and detect when the voltage drops below VLOWBAT. The module can also be configured so that it does not go into Hibernate mode if the battery voltage drops below this threshold. Battery voltage is not measured while in Hibernate mode. The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN bit of the HIBCTL register. In this configuration, the LOWBAT bit of the Hibernation Raw Interrupt Status (HIBRIS) register is set when the battery level is low. If the VABORT bit in the HIBCTL register is also set, then the module is prevented from entering Hibernation mode when a low battery is detected. The module can also be configured to generate an interrupt for the low-battery condition (see “Interrupts and Status” on page 274). Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under nominal conditions or else the Hibernation module draws power from the battery even when VDD is available. 6.3.4 Real-Time Clock The Hibernation module includes a 32-bit counter that increments once per second with the proper configuration (see “Hibernation Clock Source” on page 271). The 32.768-kHz clock signal, either directly from the 32.768-kHz oscillator or from the 4.194304-MHz crystal divided by 128, is fed into a predivider register that counts down the 32.768-kHz clock ticks to achieve a once per second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and is used for one second out of every 64 seconds to divide the input clock. This configuration allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC rate and down from 0x7FFF in order to speed up the RTC rate. The Hibernation module includes two 32-bit match registers that are compared to the value of the RTC counter. The match registers can be used to wake the processor from Hibernation mode or to generate an interrupt to the processor if it is not in hibernation. The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1 registers. The RTC can be configured to generate interrupts by using the interrupt registers (see “Interrupts and Status” on page 274). 6.3.5 Non-Volatile Memory The Hibernation module contains 64 32-bit words of memory that are powered from the battery or auxiliary power supply and therefore retained during hibernation. The processor software can save state information in this memory prior to hibernation and recover the state upon waking. The non-volatile memory can be accessed through the HIBDATA registers. July 24, 2011 273 Texas Instruments-Production Data Hibernation Module 6.3.6 Power Control Using HIB Important: The Hibernation Module requires special system implementation considerations when using HIB to control power, as it is intended to power-down all other sections of the microcontroller. All system signals and power supplies that connect to the chip must be driven to 0 VDC or powered down with the same regulator controlled by HIB. See “Hibernation Module” on page 895 for more details. The Hibernation module controls power to the microcontroller through the use of the HIB pin which is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V to the microcontroller and other circuits. When the HIB signal is asserted by the Hibernation module, the external regulator is turned off and no longer powers the microcontroller and any parts of the system that are powered by the regulator. The Hibernation module remains powered from the VBAT supply (which could be a battery or an auxiliary power source) until a Wake event. Power to the microcontroller is restored by deasserting the HIB signal, which causes the external regulator to turn power back on to the chip. 6.3.7 Power Control Using VDD3ON Mode The Hibernation module may also be configured to cut power to all internal modules. While in this state, all pins are configured as inputs. In the VDD3ON mode, the regulator should maintain 3.3 V power to the microcontroller during Hibernate. This power control mode is enabled by setting the VDD3ON bit in HIBCTL. 6.3.8 Initiating Hibernate Prior to initiating hibernation, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC match. Hibernation mode is initiated when the HIBREQ bit of the HIBCTL register is set. If a Flash memory write operation is in progress, an interlock feature holds off the transition into Hibernation mode until the write has completed. The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either one or both of these bits must be set prior to going into hibernation. Note that the WAKE pin uses the Hibernation module's internal power supply as the logic 1 reference. Upon either external wake-up or RTC match, the Hibernation module delays coming out of hibernation until VDD is above the minimum specified voltage, see Table 21-2 on page 887. When the Hibernation module wakes, the microcontroller performs a normal power-on reset. Software can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see “Interrupts and Status” on page 274) and by looking for state data in the non-volatile memory (see “Non-Volatile Memory” on page 273). 6.3.9 Interrupts and Status The Hibernation module can generate interrupts when the following conditions occur: ■ Assertion of WAKE pin ■ RTC match ■ Low battery detected All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time. The software 274 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller interrupt handler can service multiple interrupt events by reading the Hibernation Masked Interrupt Status (HIBMIS) register. Software can also read the status of the Hibernation module at any time by reading the HIBRIS register which shows all of the pending events. This register can be used after waking from hibernation to see if the wake condition was caused by the WAKE signal or the RTC match. The events that can trigger an interrupt are configured by setting the appropriate bits in the Hibernation Interrupt Mask (HIBIM) register. Pending interrupts can be cleared by writing the corresponding bit in the Hibernation Interrupt Clear (HIBIC) register. 6.4 Initialization and Configuration The Hibernation module has several different configurations. The following sections show the recommended programming sequence for various scenarios. The examples below assume that a 32.768-kHz oscillator is used, and thus always set the CLKSEL bit of the HIBCTL register. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the Hibernation module runs at 32.768 kHz and is asynchronous to the rest of the microcontroller, which is run off the system clock, software must allow a delay of tHIB_REG_ACCESS after writes to certain registers (see “Register Access Timing” on page 270). The registers that require a delay are listed in a note in “Register Map” on page 277 as well as in each register description. 6.4.1 Initialization The Hibernation module comes out of reset with the system clock enabled to the module, but if the system clock to the module has been disabled, then it must be re-enabled, even if the RTC feature is not used. See page 240. If a 4.194304-MHz crystal is used as the Hibernation module clock source, perform the following steps: 1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128 input path. 2. Wait until the WC interrupt in the HIBMIS register has been triggered before performing any other operations with the Hibernation module. If a 32.678-kHz single-ended oscillator is used as the Hibernation module clock source, then perform the following steps: 1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input and bypass the on-chip oscillator. 2. No delay is necessary. The above steps are only necessary when the entire system is initialized for the first time. If the microcontroller has been in hibernation, then the Hibernation module has already been powered up and the above steps are not necessary. The software can detect that the Hibernation module and clock are already powered by examining the CLK32EN bit of the HIBCTL register. Table 6-3 on page 275 illustrates how the clocks function with various bit setting both in normal operation and in hibernation. Table 6-3. Hibernation Module Clock Operation CLK32EN PINWEN RTCWEN CLKSEL RTCEN Result Normal Operation 0 X X X X Hibernation module disabled July 24, 2011 Result Hibernation Hibernation module disabled 275 Texas Instruments-Production Data Hibernation Module Table 6-3. Hibernation Module Clock Operation (continued) CLK32EN PINWEN RTCWEN CLKSEL RTCEN Result Normal Operation 6.4.2 Result Hibernation 1 0 0 0 1 RTC match capability enabled. Module clocked from 4.184304-MHz crystal. No hibernation 1 0 0 1 1 RTC match capability enabled. Module clocked from 32.768-kHz oscillator. No hibernation 1 0 1 X 1 Module clocked from selected source RTC match for wake-up event 1 1 0 X 0 Module clocked from selected source Clock is powered down during hibernation and powered up again on external wake-up event. 1 1 0 X 1 Module clocked from selected source Clock is powered up during hibernation for RTC. Wake up on external event. 1 1 1 X 1 Module clocked from selected source RTC match or external wake-up event, whichever occurs first. RTC Match Functionality (No Hibernation) Use the following steps to implement the RTC match functionality of the Hibernation module: 1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the HIBIM register at offset 0x014. 4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting. 6.4.3 RTC Match/Wake-Up from Hibernation Use the following steps to implement the RTC match and wake-up functionality of the Hibernation module: 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the HIBCTL register at offset 0x010. 6.4.4 External Wake-Up from Hibernation Use the following steps to implement the Hibernation module with the external WAKE pin as the wake-up source for the microcontroller: 1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the HIBCTL register at offset 0x010. 276 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Note that in this mode, if the RTC is disabled, then the Hibernation clock source is powered down during Hibernation mode and is powered up again on the external wake event to save power during hibernation. If the RTC is enabled before hibernation, it continues to operate during hibernation. 6.4.5 RTC or External Wake-Up from Hibernation 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F to the HIBCTL register at offset 0x010. 6.4.6 Register Reset The Hibernation module handles resets according to the following conditions: ■ Cold Reset When the Hibernation module has no voltage applied to either VDD or VBAT, and a voltage is subsequently applied to either VDD or VBAT, all Hibernation module registers are reset to the value in Table 6-4 on page 278. ■ Reset During Hibernation Module Disable When the module has either not been enabled or has been disabled by software, the reset is passed through to the Hibernation module circuitry, and the internal state of the module is reset. Non-volatile memory contents are not reset to zero and contents after reset are indeterminate. ■ Reset While Hibernation Module is in Hibernation Mode While in Hibernation mode, or while transitioning from Hibernation mode to run mode, the reset generated by the POR circuitry of the microcontroller is suppressed, and the state of the Hibernation module's registers is unaffected. ■ Reset While Hibernation Module is in Normal Mode While in normal mode (not hibernating), any reset is suppressed if either the RTCEN or the PINWEN bit is set in the HIBCTL register, and the content/state of the control and data registers is unaffected. Software must initialize any control or data registers in this condition. Therefore, software is the only mechanism to set or clear the CLK32EN bit and real-time clock operation, or to clear contents of the data memory. The only state that must be cleared by a reset operation while not in Hibernation mode is any state that prevents software from managing the interface. Note: 6.5 If VDD drops below operational range while in normal mode (not hibernating), all Hibernation module registers are reset to the value in Table 6-4 on page 278, regardless of whether the proper voltage is applied to VBAT. Register Map Table 6-4 on page 278 lists the Hibernation registers. All addresses given are relative to the Hibernation Module base address at 0x400F.C000. Note that the system clock to the Hibernation module must be enabled before the registers can be programmed (see page 240). There must be a delay of 3 July 24, 2011 277 Texas Instruments-Production Data Hibernation Module system clocks after the Hibernation module clock is enabled before any Hibernation module registers are accessed. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access Timing” on page 270. Important: Reset values apply only to a cold reset. Once configured, the Hibernate module ignores any system reset, other than power on reset, as long as VBAT is present. Table 6-4. Hibernation Module Register Map Offset Name 0x000 Reset HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 279 0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 280 0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 281 0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 282 0x010 HIBCTL R/W 0x8000.0000 Hibernation Control 283 0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 286 0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 288 0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 290 0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 292 0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 293 0x0300x12C HIBDATA R/W - Hibernation Data 294 6.6 Description See page Type Register Descriptions The remainder of this section lists and describes the Hibernation module registers, in numerical order by address offset. 278 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 This register is the current 32-bit value of the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access Timing” on page 270. Hibernation RTC Counter (HIBRTCC) Base 0x400F.C000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RTCC Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RTCC Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type 31:0 RTCC RO RO 0 Reset RO 0 Description 0x0000.0000 RTC Counter A read returns the 32-bit counter value, which represents the seconds elapsed since the RTC was enabled. This register is read-only. To change the value, use the HIBRTCLD register. July 24, 2011 279 Texas Instruments-Production Data Hibernation Module Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit match 0 register for the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access Timing” on page 270. Hibernation RTC Match 0 (HIBRTCM0) Base 0x400F.C000 Offset 0x004 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM0 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RTCM0 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 RTCM0 R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF RTC Match 0 A write loads the value into the RTC match register. A read returns the current match value. 280 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 This register is the 32-bit match 1 register for the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access Timing” on page 270. Hibernation RTC Match 1 (HIBRTCM1) Base 0x400F.C000 Offset 0x008 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM1 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RTCM1 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 RTCM1 R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF RTC Match 1 A write loads the value into the RTC match register. A read returns the current match value. July 24, 2011 281 Texas Instruments-Production Data Hibernation Module Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C This register is used to load a 32-bit value loaded into the RTC counter. The load occurs immediately upon this register being written. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access Timing” on page 270. Hibernation RTC Load (HIBRTCLD) Base 0x400F.C000 Offset 0x00C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCLD Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RTCLD Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 RTCLD R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. 282 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 5: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. This register must be written last before a hibernate event is issued. Writes to other registers after the HIBREQ bit is set are not guaranteed to complete before hibernation is entered. Hibernation Control (HIBCTL) Base 0x400F.C000 Offset 0x010 Type R/W, reset 0x8000.0000 31 30 29 28 27 26 25 24 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WRC Type Reset 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 HIBREQ RTCEN R/W 0 R/W 0 reserved reserved Type Reset 23 RO 0 VDD3ON VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL Bit/Field Name Type Reset 31 WRC RO 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Write Complete/Capable Value Description 0 The interface is processing a prior write and is busy. Any write operation that is attempted while WRC is 0 results in undetermined behavior. 1 The interface is ready to accept a write. Software must poll this bit between write requests and defer writes until WRC=1 to ensure proper operation. The bit name WRC means "Write Complete," which is the normal use of the bit (between write accesses). However, because the bit is set out-of-reset, the name can also mean "Write Capable" which simply indicates that the interface may be written to by software. This difference may be exploited by software at reset time to detect which method of programming is appropriate: 0 = software delay loops required; 1 = WRC paced available. 30:9 reserved RO 0x000 8 VDD3ON R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. VDD Powered Value Description 1 The internal switches control the power to the on-chip modules (VDD3ON mode). 0 The internal switches are not used. The HIB signal should be used to control an external switch or regulator. Note that regardless of the status of the VDD3ON bit, the HIB signal is asserted during Hibernate mode. Thus, when VDD3ON is set, the HIB signal should not be connected to the 3.3V regulator, and the 3.3V power source should remain connected. July 24, 2011 283 Texas Instruments-Production Data Hibernation Module Bit/Field Name Type Reset 7 VABORT R/W 0 6 CLK32EN R/W 0 Description Power Cut Abort Enable Value Description 1 When this bit is set, the battery voltage level is checked before entering hibernation. If VBAT is less than VLOWBAT, the microcontroller does not go into hibernation. 0 The microcontroller goes into hibernation regardless of the voltage level of the battery. Clocking Enable This bit must be enabled to use the Hibernation module. 5 4 3 2 LOWBATEN PINWEN RTCWEN CLKSEL R/W R/W R/W R/W 0 0 0 0 Value Description 1 The Hibernation module clock source is enabled. 0 The Hibernation module clock source is disabled. Low Battery Monitoring Enable Value Description 1 Low battery voltage detection is enabled. When this bit is set, the battery voltage level is checked before entering hibernation. If VBAT is less than VLOWBAT, the LOWBAT bit in the HIBRIS register is set. 0 Low battery monitoring is disabled. External WAKE Pin Enable Value Description 1 An assertion of the WAKE pin takes the microcontroller out of hibernation. 0 The status of the WAKE pin has no effect on hibernation. RTC Wake-up Enable Value Description 1 An RTC match event (the value the HIBRTCC register matches the value of the HIBRTCM0 or HIBRTCM1 register) takes the microcontroller out of hibernation. 0 An RTC match event has no effect on hibernation. Hibernation Module Clock Select Value Description 1 Use raw output. Use this value for a 32.768-kHz oscillator. 0 Use Divide-by-128 output. Use this value for a 4.194304-MHz crystal. 284 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 1 HIBREQ R/W 0 Description Hibernation Request Value Description 1 Set this bit to initiate hibernation. 0 No hibernation request. After a wake-up event, this bit is automatically cleared by hardware. 0 RTCEN R/W 0 RTC Timer Enable Value Description 1 The Hibernation module RTC is enabled. The RTC remains active during hibernation. 0 The Hibernation module RTC is disabled. When this bit is clear and PINWEN is set, enabling an external wake event, the RTC stops during hibernation to save power. July 24, 2011 285 Texas Instruments-Production Data Hibernation Module Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Each bit in this register masks the corresponding bit in the Hibernation Raw Interrupt Status (HIBRIS) register. If a bit is unmasked, the interrupt is sent to the interrupt controller. If the bit is masked, the interrupt is not sent to the interrupt controller. Hibernation Interrupt Mask (HIBIM) Base 0x400F.C000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset EXTW Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 EXTW R/W 0 R/W 0 LOWBAT RTCALT1 RTCALT0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Interrupt Mask Value Description 2 LOWBAT R/W 0 1 An interrupt is sent to the interrupt controller when the EXTW bit in the HIBRIS register is set. 0 The EXTW interrupt is suppressed and not sent to the interrupt controller. Low Battery Voltage Interrupt Mask Value Description 1 RTCALT1 R/W 0 1 An interrupt is sent to the interrupt controller when the LOWBAT bit in the HIBRIS register is set. 0 The LOWBAT interrupt is suppressed and not sent to the interrupt controller. RTC Alert 1 Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the RTCALT1 bit in the HIBRIS register is set. 0 The RTCALT1 interrupt is suppressed and not sent to the interrupt controller. 286 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 RTCALT0 R/W 0 Description RTC Alert 0 Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the RTCALT0 bit in the HIBRIS register is set. 0 The RTCALT0 interrupt is suppressed and not sent to the interrupt controller. July 24, 2011 287 Texas Instruments-Production Data Hibernation Module Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Each bit can be masked by clearing the corresponding bit in the HIBIM register. When a bit is masked, the interrupt is not sent to the interrupt controller. Bits in this register are cleared by writing a 1 to the corresponding bit in the Hibernation Interrupt Clear (HIBIC) register or by entering hibernation. Hibernation Raw Interrupt Status (HIBRIS) Base 0x400F.C000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset EXTW Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 EXTW RO 0 RO 0 LOWBAT RTCALT1 RTCALT0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Raw Interrupt Status Value Description 1 The WAKE pin has been asserted. 0 The WAKE pin has not been asserted. This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register. 2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status Value Description 1 The battery voltage dropped below VLOWBAT. 0 The battery voltage has not dropped below VLOWBAT. This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register. 1 RTCALT1 RO 0 RTC Alert 1 Raw Interrupt Status Value Description 1 The value of the HIBRTCC register matches the value in the HIBRTCM1 register. 0 No match This bit is cleared by writing a 1 to the RTCALT1 bit in the HIBIC register. 288 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 RTCALT0 RO 0 Description RTC Alert 0 Raw Interrupt Status Value Description 1 The value of the HIBRTCC register matches the value in the HIBRTCM0 register. 0 No match This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register. July 24, 2011 289 Texas Instruments-Production Data Hibernation Module Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Bits in this register are the AND of the corresponding bits in the HIBRIS and HIBIM registers. When both corresponding bits are set, the bit in this register is set, and the interrupt is sent to the interrupt controller. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset EXTW Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 EXTW RO 0 RO 0 LOWBAT RTCALT1 RTCALT0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a WAKE pin assertion. 0 An external wake-up interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register. 2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a low battery voltage condition. 0 A low battery voltage interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register. 1 RTCALT1 RO 0 RTC Alert 1 Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to an RTC match. 0 An RTC match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RTCALT1 bit in the HIBIC register. 290 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 RTCALT0 RO 0 Description RTC Alert 0 Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to an RTC match. 0 An RTC match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register. July 24, 2011 291 Texas Instruments-Production Data Hibernation Module Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Writing a 1 to a bit clears the corresponding interrupt in the HIBRIS register. Hibernation Interrupt Clear (HIBIC) Base 0x400F.C000 Offset 0x020 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 reserved Type Reset reserved Type Reset EXTW Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 EXTW R/W1C 0 LOWBAT RTCALT1 RTCALT0 R/W1C 0 R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Masked Interrupt Clear Writing a 1 to this bit clears the EXTW bit in the HIBRIS and HIBMIS registers. Reads return an indeterminate value. 2 LOWBAT R/W1C 0 Low Battery Voltage Masked Interrupt Clear Writing a 1 to this bit clears the LOWBAT bit in the HIBRIS and HIBMIS registers. Reads return an indeterminate value. 1 RTCALT1 R/W1C 0 RTC Alert1 Masked Interrupt Clear Writing a 1 to this bit clears the RTCALT1 bit in the HIBRIS and HIBMIS registers. Reads return an indeterminate value. 0 RTCALT0 R/W1C 0 RTC Alert0 Masked Interrupt Clear Writing a 1 to this bit clears the RTCALT0 bit in the HIBRIS and HIBMIS registers. Reads return an indeterminate value. 292 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles, where N is the number of clock cycles to add or subtract every 63 seconds. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access Timing” on page 270. Hibernation RTC Trim (HIBRTCT) Base 0x400F.C000 Offset 0x024 Type R/W, reset 0x0000.7FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 TRIM Type Reset R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TRIM R/W 0x7FFF RTC Trim Value This value is loaded into the RTC predivider every 64 seconds. It is used to adjust the RTC rate to account for drift and inaccuracy in the clock source. Compensation can be adjusted by software by moving the default value of 0x7FFF up or down. Moving the value up slows down the RTC and moving the value down speeds up the RTC. July 24, 2011 293 Texas Instruments-Production Data Hibernation Module Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the system processor in order to store any non-volatile state data and does not lose power during a power cut operation. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access Timing” on page 270. Hibernation Data (HIBDATA) Base 0x400F.C000 Offset 0x030-0x12C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - RTD Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 RTD Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 RTD R/W - R/W - Description Hibernation Module NV Data 294 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 7 Internal Memory The LM3S1F11 microcontroller comes with 48 KB of bit-banded SRAM, internal ROM,and 384 KB of Flash memory. The Flash memory controller provides a user-friendly interface, making Flash memory programming a simple task. Flash memory protection can be applied to the Flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1 on page 295 illustrates the internal memory blocks and control logic. The dashed boxes in the figure indicate registers residing in the System Control module. Figure 7-1. Internal Memory Block Diagram ROM Control ROM Array RMCTL Flash Control Icode Bus Cortex-M3 FMA FMD FMC FCRIS FCIM FCMISC Dcode Bus Flash Array System Bus Flash Write Buffer FMC2 FWBVAL FWBn 32 words Flash Protection Bridge FMPREn FMPRE FMPPEn FMPPE User Registers Flash Timing BOOTCFG USECRL USER_REG0 USER_REG1 USER_REG2 USER_REG3 SRAM Array 7.2 Functional Description This section describes the functionality of the SRAM, ROM, and Flash memories. Note: The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. July 24, 2011 295 Texas Instruments-Production Data Internal Memory 7.2.1 SRAM ® The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM provides bit-banding technology in the processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band base is located at address 0x2200.0000. The bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, see “Bit-Banding” on page 77. Note: 7.2.2 The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays). The banks are partitioned such that one bank contains all even words (the even bank) and the other contains all odd words (the odd bank). A write access that is followed immediately by a read access to the same bank incurs a stall of a single clock cycle. However, a write to one bank followed by a read of the other bank can occur in successive clock cycles without incurring any delay. ROM The internal ROM of the Stellaris device is located at address 0x0100.0000 of the device memory map. Detailed information on the ROM contents can be found in the Stellaris® ROM User’s Guide. The ROM contains the following components: ■ Stellaris Boot Loader and vector table ■ Stellaris Peripheral Driver Library (DriverLib) release for product-specific peripherals and interfaces ■ Advanced Encryption Standard (AES) cryptography tables ■ Cyclic Redundancy Check (CRC) error detection functionality The boot loader is used as an initial program loader (when the Flash memory is empty) as well as an application-initiated firmware upgrade mechanism (by calling back to the boot loader). The Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory requirements and freeing the Flash memory to be used for other purposes (such as additional features in the application). Advance Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government and Cyclic Redundancy Check (CRC) is a technique to validate a span of data has the same contents as when previously checked. 7.2.2.1 Boot Loader Overview The Stellaris Boot Loader is used to download code to the Flash memory of a device without the use of a debug interface. When the core is reset, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal in Ports A-H as configured in the Boot Configuration (BOOTCFG) register. 296 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always executed. The boot sequence executed from ROM is as follows: 1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is mapped to address 0x0. 2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. The boot loader uses a simple packet interface to provide synchronous communication with the device. The speed of the boot loader is determined by the internal oscillator (PIOSC) frequency as it does not enable the PLL. The following serial interfaces can be used: ■ UART0 ■ SSI0 ■ I2C0 For simplicity, both the data format and communication protocol are identical for all serial interfaces. See the Stellaris® Boot Loader User's Guide for information on the boot loader software. 7.2.2.2 Stellaris Peripheral Driver Library The Stellaris Peripheral Driver Library contains a file called driverlib/rom.h that assists with calling the peripheral driver library functions in the ROM. The detailed description of each function is available in the Stellaris® ROM User’s Guide. See the "Using the ROM" chapter of the Stellaris® Peripheral Driver Library User's Guide for more details on calling the ROM functions and using driverlib/rom.h. A table at the beginning of the ROM points to the entry points for the APIs that are provided in the ROM. Accessing the API through these tables provides scalability; while the API locations may change in future versions of the ROM, the API tables will not. The tables are split into two levels; the main table contains one pointer per peripheral which points to a secondary table that contains one pointer per API that is associated with that peripheral. The main table is located at 0x0100.0010, right after the Cortex-M3 vector table in the ROM. DriverLib functions are described in detail in the Stellaris® Peripheral Driver Library User's Guide. Additional APIs are available for graphics and USB functions, but are not preloaded into ROM. The Stellaris Graphics Library provides a set of graphics primitives and a widget set for creating graphical user interfaces on Stellaris microcontroller-based boards that have a graphical display (for more information, see the Stellaris® Graphics Library User's Guide). July 24, 2011 297 Texas Instruments-Production Data Internal Memory 7.2.2.3 Advanced Encryption Standard (AES) Cryptography Tables AES is a strong encryption method with reasonable performance and size. AES is fast in both hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for applications that can use pre-arranged keys, such as setup during manufacturing or configuration. Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the forward S-box substitution table, the second is the reverse S-box substitution table, the third is the forward polynomial table, and the final is the reverse polynomial table. See the Stellaris® ROM User’s Guide for more information on AES. 7.2.2.4 Cyclic Redundancy Check (CRC) Error Detection The CRC technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that Flash memory contents have not been changed, and for other cases where the data needs to be validated. A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more readily. See the Stellaris® ROM User’s Guide for more information on CRC. 7.2.3 Flash Memory At system clock speeds of 50 MHz and below, the Flash memory is read in a single cycle. The Flash memory is organized as a set of 1-KB blocks that can be individually erased. An individual 32-bit word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability to concurrently program 32 continuous words in Flash memory. Erasing a block causes the entire contents of the block to be reset to all 1s. The 1-KB blocks are paired into sets of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. Caution – The Stellaris Flash memory array has ECC which uses a test port into the Flash memory to continually scan the array for ECC errors and to correct any that are detected. This operation is transparent to the microcontroller. The BIST must scan the entire memory array occasionally to ensure integrity, taking about five minutes to do so. In systems where the microcontroller is frequently powered for less than five minutes, power should be removed from the microcontroller in a controlled manner to ensure proper operation. This controlled manner can either be through entering Hibernation mode or software can request permission to power down the part using the USDREQ bit in the Flash Control (FCTL) register and wait to receive an acknowledge from the USDACK bit prior to removing power. If the microcontroller is powered down using this controlled method, the BIST engine keeps track of where it was in the memory array and it always scans the complete array after any aggregate of five minutes powered-on, regardless of the number of intervening power cycles. If the microcontroller is powered down before five minutes of being powered up, BIST starts again from wherever it left off before the last controlled power-down or from 0 if there never was a controlled power down. An occasional short power down is not a concern, but the microcontroller should not always be powered down frequently in an uncontrolled manner. The microcontroller can be power-cycled as frequently as necessary if it is powered-down in a controlled manner. 7.2.3.1 Prefetch Buffer The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency is greater than 50 MHz. In this mode, the Flash memory operates at half of the system clock. The prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait states while code is executing linearly. The fetch buffer includes a branch speculation mechanism 298 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short loop branches often stay in the buffer. As a result, some branches can be executed with no wait states. Other branches incur a single wait state. 7.2.3.2 Flash Memory Protection The user is provided two forms of Flash memory protection per 2-KB Flash memory block in six pairs of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If a bit is set, the corresponding block may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may be executed or read by software or debuggers. If a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. The policies may be combined as shown in Table 7-1 on page 299. Table 7-1. Flash Memory Protection Policy Combinations FMPPEn FMPREn 0 0 Protection Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. 1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. 0 1 Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 1 1 No protection. The block may be written, erased, executed or read. A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited and generates a bus fault. A Flash memory access that attempts to program or erase a program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt (by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. These settings create a policy of open access and programmability. The register bits may be changed by clearing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The changes are committed using the Flash Memory Control (FMC) register. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 302. 7.2.3.3 Interrupts The Flash memory controller can generate interrupts when the following conditions are observed: ■ Programming Interrupt - signals when a program or erase action is complete. ■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block of memory that is protected by its corresponding FMPPEn bit. July 24, 2011 299 Texas Instruments-Production Data Internal Memory The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller Masked Interrupt Status (FCMIS) register (see page 311) by setting the corresponding MASK bits. If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw Interrupt Status (FCRIS) register (see page 310). Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register (see page 312). 7.2.3.4 Flash Memory Programming The Stellaris devices provide a user-friendly interface for Flash memory programming. All erase/program operations are handled via three registers: Flash Memory Address (FMA), Flash Memory Data (FMD), and Flash Memory Control (FMC). Note that if the debug capabilities of the microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be performed in order to reactivate the debug module. See “Recovering a "Locked" Microcontroller” on page 168. During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation is complete. If instruction execution is required during a Flash memory operation, the code that is executing must be placed in SRAM and executed from there while the flash operation is in progress. Caution – The Flash memory is divided into sectors of electrically separated address ranges of 4 KB each, aligned on 4 KB boundaries. Erase/program operations on a 1-KB page have an electrical effect on the other three 1-KB pages within the sector. A specific 1-KB page must be erased after 6 total erase/program cycles occur to the other pages within its 4-KB sector. The following sequence of operations on a 4-KB sector of Flash memory (Page 0..3) provides an example: ■ Page 3 is erase and programmed with values. ■ Page 0, Page 1, and Page 2 are erased and then programmed with values. At this point Page 3 has been affected by 3 erase/program cycles. ■ Page 0, Page 1, and Page 2 are again erased and then programmed with values. At this point Page 3 has been affected by 6 erase/program cycles. ■ If the contents of Page 3 must continue to be valid, Page 3 must be erased and reprogrammed before any other page in this sector has another erase or program operation. To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the Flash memory write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. Important: To ensure proper operation, two writes to the same word must be separated by an ERASE. The following two sequences are allowed: 300 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ ERASE -> PROGRAM value -> PROGRAM 0x0000.0000 ■ ERASE -> PROGRAM value -> ERASE The following sequence is NOT allowed: ■ ERASE -> PROGRAM value -> PROGRAM value To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the Flash memory write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared or, alternatively, enable the programming interrupt using the PMASK bit in the FCIM register. To perform a mass erase of the Flash memory 1. Write the Flash memory write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared or, alternatively, enable the programming interrupt using the PMASK bit in the FCIM register. 7.2.3.5 32-Word Flash Memory Write Buffer A 32-word write buffer provides the capability to perform faster write accesses to the Flash memory by concurrently programing 32 words with a single buffered Flash memory write operation. The buffered Flash memory write operation takes the same amount of time as the single word write operation controlled by bit 0 in the FMC register. The data for the buffered write is written to the Flash Write Buffer (FWBn) registers. The registers are 32-word aligned with Flash memory, and therefore the register FWB0 corresponds with the address in FMA where bits [6:0] of FMA are all 0. FWB1 corresponds with the address in FMA + 0x4 and so on. Only the FWBn registers that have been updated since the previous buffered Flash memory write operation are written. The Flash Write Buffer Valid (FWBVAL) register shows which registers have been written since the last buffered Flash memory write operation. This register contains a bit for each of the 32 FWBn registers, where bit[n] of FWBVAL corresponds to FWBn. The FWBn register has been updated if the corresponding bit in the FWBVAL register is set. To program 32 words with a single buffered Flash memory write operation 1. Write the source data to the FWBn registers. 2. Write the target address to the FMA register. This must be a 32-word aligned address (that is, bits [6:0] in FMA must be 0s). 3. Write the Flash memory write key and the WRBUF bit (a value of 0xA442.0001) to the FMC2 register. 4. Poll the FMC2 register until the WRBUF bit is cleared or wait for the PMIS interrupt to be signaled. July 24, 2011 301 Texas Instruments-Production Data Internal Memory 7.2.3.6 Nonvolatile Register Programming This section discusses how to update registers that are resident within the Flash memory itself. These registers exist in a separate space from the main Flash memory array and are not affected by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0 with a write operation. The register contents are unaffected by any reset condition except power-on reset, which returns the register contents to 0xFFFF.FFFF. By committing the register values using the COMT bit in the FMC register, the register contents become nonvolatile and are therefore retained following power cycling. Once the register contents are committed, the only way to restore the factory default values is to perform the sequence described in “Recovering a "Locked" Microcontroller” on page 168. With the exception of the Boot Configuration (BOOTCFG) register, the settings in these registers can be tested before committing them to Flash memory. For the BOOTCFG register, the data to be written is loaded into the FMD register before it is committed. The FMD register is read only and does not allow the BOOTCFG operation to be tried before committing it to nonvolatile memory. Important: The Flash memory resident registers can only have bits changed from 1 to 0 by user programming and can only be committed once. After being committed, these registers can only be restored to their factory default values only by performing the sequence described in “Recovering a "Locked" Microcontroller” on page 168. The mass erase of the main Flash memory array caused by the sequence is performed prior to restoring these registers. In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and BOOTCFG registers each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be changed from 1 to 0. Table 7-2 on page 302 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 7-2. User-Programmable Flash Memory Resident Registers Register to be Committed FMA Value Data Source FMPRE0 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPRE2 0x0000.0004 FMPRE2 FMPRE3 0x0000.0006 FMPRE3 FMPRE4 0x0000.0008 FMPRE4 FMPRE5 0x0000.000A FMPRE5 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 FMPPE2 0x0000.0005 FMPPE2 FMPPE3 0x0000.0007 FMPPE3 FMPRE4 0x0000.0009 FMPRE4 FMPRE5 0x0000.000B FMPRE5 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.0001 USER_REG1 USER_REG2 0x8000.0002 USER_REG2 USER_REG3 0x8000.0003 USER_REG3 BOOTCFG 0x7510.0000 FMD 302 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 7.3 Register Map Table 7-3 on page 303 lists the ROM Controller register and the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, FCMISC, FMC2, FWBVAL, and FWBn register offsets are relative to the Flash memory control base address of 0x400F.D000. The ROM and Flash memory protection register offsets are relative to the System Control base address of 0x400F.E000. Table 7-3. Flash Register Map Offset Name Type Reset Description See page Flash Memory Registers (Flash Control Offset) 0x000 FMA R/W 0x0000.0000 Flash Memory Address 305 0x004 FMD R/W 0x0000.0000 Flash Memory Data 306 0x008 FMC R/W 0x0000.0000 Flash Memory Control 307 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 310 0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 311 0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 312 0x020 FMC2 R/W 0x0000.0000 Flash Memory Control 2 313 0x030 FWBVAL R/W 0x0000.0000 Flash Write Buffer Valid 314 0x0F8 FCTL R/W 0x0000.0000 Flash Control 315 0x100 0x17C FWBn R/W 0x0000.0000 Flash Write Buffer n 316 ROM Control 317 Memory Registers (System Control Offset) 0x0F0 RMCTL R/W1C - 0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 318 0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 318 0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 319 0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 319 0x1D0 BOOTCFG R/W 0xFFFF.FFFE Boot Configuration 320 0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 322 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 323 0x1E8 USER_REG2 R/W 0xFFFF.FFFF User Register 2 324 0x1EC USER_REG3 R/W 0xFFFF.FFFF User Register 3 325 0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 326 0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 327 0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 328 0x210 FMPRE4 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 4 329 July 24, 2011 303 Texas Instruments-Production Data Internal Memory Table 7-3. Flash Register Map (continued) See page Offset Name Type Reset 0x214 FMPRE5 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 5 330 0x218 FMPRE6 R/W 0x0000.0000 Flash Memory Protection Read Enable 6 331 0x21C FMPRE7 R/W 0x0000.0000 Flash Memory Protection Read Enable 7 332 0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 333 0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 334 0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 335 0x410 FMPPE4 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 4 336 0x414 FMPPE5 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 5 337 0x418 FMPPE6 R/W 0x0000.0000 Flash Memory Protection Program Enable 6 338 0x41C FMPPE7 R/W 0x0000.0000 Flash Memory Protection Program Enable 7 339 7.4 Description Flash Memory Register Descriptions (Flash Control Offset) This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. 304 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned CPU byte address and specifies which block is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 25 24 23 22 21 20 19 18 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 17 16 OFFSET OFFSET Type Reset Bit/Field Name Type Reset Description 31:19 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18:0 OFFSET R/W 0x0 Address Offset Address offset in Flash memory where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 302 for details on values for this field). July 24, 2011 305 Texas Instruments-Production Data Internal Memory Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DATA Type Reset DATA Type Reset Bit/Field Name Type 31:0 DATA R/W Reset Description 0x0000.0000 Data Value Data value for write operation. 306 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 305). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 306) is written to the specified address. This register must be the final register written and initiates the memory operation. The four control bits in the lower byte of this register are used to initiate memory operations. Care must be taken not to set multiple control bits as the results of such an operation are unpredictable. Caution – If any of bits [15:4] are written to 1, the device may become inoperable. These bits should always be written to 0. In all registers, the value of a reserved bit should be preserved across a read-modify-write operation. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 COMT MERASE ERASE WRITE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 WRKEY Type Reset reserved Type Reset Bit/Field Name Type Reset 31:16 WRKEY WO 0x0000 Description Flash Memory Write Key This field contains a write key, which is used to minimize the incidence of accidental Flash memory writes. The value 0xA442 must be written into this field for a Flash memory write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 15:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 307 Texas Instruments-Production Data Internal Memory Bit/Field Name Type Reset 3 COMT R/W 0 Description Commit Register Value This bit is used to commit writes to Flash-memory-resident registers and to monitor the progress of that process. Value Description 1 Set this bit to commit (write) the register value to a Flash-memory-resident register. When read, a 1 indicates that the previous commit access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous commit access is complete. See “Nonvolatile Register Programming” on page 302 for more information on programming Flash-memory-resident registers. 2 MERASE R/W 0 Mass Erase Flash Memory This bit is used to mass erase the Flash main memory and to monitor the progress of that process. Value Description 1 Set this bit to erase the Flash main memory. When read, a 1 indicates that the previous mass erase access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous mass erase access is complete. For information on erase time, see “Flash Memory ” on page 897. 1 ERASE R/W 0 Erase a Page of Flash Memory This bit is used to erase a page of Flash memory and to monitor the progress of that process. Value Description 1 Set this bit to erase the Flash memory page specified by the contents of the FMA register. When read, a 1 indicates that the previous page erase access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous page erase access is complete. For information on erase time, see “Flash Memory ” on page 897. 308 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 WRITE R/W 0 Description Write a Word into Flash Memory This bit is used to write a word into Flash memory and to monitor the progress of that process. Value Description 1 Set this bit to write the data stored in the FMD register into the Flash memory location specified by the contents of the FMA register. When read, a 1 indicates that the write update access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous write update access is complete. For information on programming time, see “Flash Memory ” on page 897. July 24, 2011 309 Texas Instruments-Production Data Internal Memory Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the Flash memory controller has an interrupt condition. An interrupt is sent to the interrupt controller only if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PRIS ARIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 PRIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Raw Interrupt Status This bit provides status on programming cycles which are write or erase actions generated through the FMC or FMC2 register bits (see page 307 and page 313). Value Description 1 The programming or erase cycle has completed. 0 The programming or erase cycle has not completed. This status is sent to the interrupt controller when the PMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register. 0 ARIS RO 0 Access Raw Interrupt Status Value Description 1 A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. 0 No access has tried to improperly program or erase the Flash memory. This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register. 310 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the Flash memory controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PMASK AMASK RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 PMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the interrupt controller. Value Description 0 AMASK R/W 0 1 An interrupt is sent to the interrupt controller when the PRIS bit is set. 0 The PRIS interrupt is suppressed and not sent to the interrupt controller. Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the interrupt controller. Value Description 1 An interrupt is sent to the interrupt controller when the ARIS bit is set. 0 The ARIS interrupt is suppressed and not sent to the interrupt controller. July 24, 2011 311 Texas Instruments-Production Data Internal Memory Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 PMISC R/W1C 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 1 0 PMISC AMISC R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. Writing a 1 to this bit clears PMISC and also the PRIS bit in the FCRIS register (see page 310). 0 When read, a 0 indicates that a programming cycle complete interrupt has not occurred. A write of 0 has no effect on the state of this bit. 0 AMISC R/W1C 0 Access Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. Writing a 1 to this bit clears AMISC and also the ARIS bit in the FCRIS register (see page 310). 0 When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit. 312 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 7: Flash Memory Control 2 (FMC2), offset 0x020 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 305). If the access is a write access, the data contained in the Flash Write Buffer (FWB) registers is written. This register must be the final register written as it initiates the memory operation. Flash Memory Control 2 (FMC2) Base 0x400F.D000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 WRKEY Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:16 WRKEY WO 0x0000 RO 0 0 WRBUF RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 Description Flash Memory Write Key This field contains a write key, which is used to minimize the incidence of accidental Flash memory writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC2 register without this WRKEY value are ignored. A read of this field returns the value 0. 15:1 reserved RO 0x000 0 WRBUF R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Buffered Flash Memory Write This bit is used to start a buffered write to Flash memory. Value Description 1 Set this bit to write the data stored in the FWBn registers to the location specified by the contents of the FMA register. When read, a 1 indicates that the previous buffered Flash memory write access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous buffered Flash memory write access is complete. For information on programming time, see “Flash Memory ” on page 897. July 24, 2011 313 Texas Instruments-Production Data Internal Memory Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 This register provides a bitwise status of which FWBn registers have been written by the processor since the last write of the Flash memory write buffer. The entries with a 1 are written on the next write of the Flash memory write buffer. This register is cleared after the write operation by hardware. A protection violation on the write operation also clears this status. Software can program the same 32 words to various Flash memory locations by setting the FWB[n] bits after they are cleared by the write operation. The next write operation then uses the same data as the previous one. In addition, if a FWBn register change should not be written to Flash memory, software can clear the corresponding FWB[n] bit to preserve the existing data when the next write operation occurs. Flash Write Buffer Valid (FWBVAL) Base 0x400F.D000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FWB[n] Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 FWB[n] Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:0 FWB[n] R/W 0x0 R/W 0 Description Flash Memory Write Buffer Value Description 1 The corresponding FWBn register has been updated since the last buffer write operation and is ready to be written to Flash memory. 0 The corresponding FWBn register has no new data to be written. Bit 0 corresponds to FWB0, offset 0x100, and bit 31 corresponds to FWB31, offset 0x13C. 314 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 9: Flash Control (FCTL), offset 0x0F8 This register is used to ensure that the microcontroller is powered down in a controlled fashion in systems where power is cycled more frequently than once every five minutes. The USDREQ bit should be set to indicate that power is going to be turned off. Software should poll the USDACK bit to determine when it is acceptable to power down. Note that this power-down process is not required if the microcontroller enters hibernation mode prior to power being removed. Flash Control (FCTL) Base 0x400F.D000 Offset 0x0F8 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 USDACK RO 0 USDACK USDREQ RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. User Shut Down Acknowledge Value Description 1 The microcontroller can be powered down. 0 The microcontroller cannot yet be powered down. This bit should be set within 50 ms of setting the USDREQ bit. 0 USDREQ R/W 0 User Shut Down Request Value Description 1 Requests permission to power down the microcontroller. 0 No effect. July 24, 2011 315 Texas Instruments-Production Data Internal Memory Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C These 32 registers hold the contents of the data to be written into the Flash memory on a buffered Flash memory write operation. The offset selects one of the 32-bit registers. Only FWBn registers that have been updated since the preceding buffered Flash memory write operation are written into the Flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or 2 words. The FWBn registers are written into the Flash memory with the FWB0 register corresponding to the address contained in FMA. FWB1 is written to the address FMA+0x4 etc. Note that only data bits that are 0 result in the Flash memory being modified. A data bit that is 1 leaves the content of the Flash memory bit at its previous value. Flash Write Buffer n (FWBn) Base 0x400F.D000 Offset 0x100 - 0x17C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DATA Type Reset DATA Type Reset Bit/Field Name Type 31:0 DATA R/W Reset Description 0x0000.0000 Data Data to be written into the Flash memory. 7.5 Memory Register Descriptions (System Control Offset) The remainder of this section lists and describes the registers that reside in the System Control address space, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. 316 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 11: ROM Control (RMCTL), offset 0x0F0 This register provides control of the ROM controller state. This register offset is relative to the System Control base address of 0x400F.E000. At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always executed. The boot sequence executed from ROM is as follows: 1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is mapped to address 0x0. 2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. ROM Control (RMCTL) Base 0x400F.E000 Offset 0x0F0 Type R/W1C, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 BA R/W1C 1 RO 0 0 BA RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Boot Alias Value Description 1 The microcontroller's ROM appears at address 0x0. 0 The Flash memory is at address 0x0. This bit is cleared by writing a 1 to this bit position. July 24, 2011 317 Texas Instruments-Production Data Internal Memory Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.E000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. 318 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 13: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.E000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 PROG_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. July 24, 2011 319 Texas Instruments-Production Data Internal Memory Register 14: Boot Configuration (BOOTCFG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides configuration of a GPIO pin to enable the ROM Boot Loader as well as a write-once mechanism to disable external debugger access to the device. Upon reset, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal from Ports A-H as configured by the bits in this register. If the EN bit is set or the specified pin does not have the required polarity, the system control module checks address 0x000.0004 to see if the Flash memory has a valid reset vector. If the data at address 0x0000.0004 is 0xFFFF.FFFF, then it is assumed that the Flash memory has not yet been programmed, and the core executes the ROM Boot Loader. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Clearing the DBG1 bit disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. Boot Configuration (BOOTCFG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 30 29 28 27 26 25 24 NW Type Reset R/W 1 15 RO 1 RO 1 RO 1 14 13 12 PORT Type Reset R/W 1 23 22 21 20 19 18 17 16 RO 1 RO 1 reserved R/W 1 RO 1 RO 1 11 10 PIN R/W 1 R/W 1 R/W 1 R/W 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 9 8 POL EN R/W 1 R/W 1 reserved RO 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written RO 1 RO 1 RO 1 RO 1 RO 1 1 0 DBG1 DBG0 R/W 1 R/W 0 When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:16 reserved RO 0x7FFF Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 320 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 15:13 PORT R/W 0x7 Description Boot GPIO Port This field selects the port of the GPIO port pin that enables the ROM boot loader at reset. Value Description 12:10 PIN R/W 0x7 0x0 Port A 0x1 Port B 0x2 Port C 0x3 Port D 0x4 Port E 0x5 Port F 0x6 Port G 0x7 Port H Boot GPIO Pin This field selects the pin number of the GPIO port pin that enables the ROM boot loader at reset. Value Description 9 POL R/W 0x1 0x0 Pin 0 0x1 Pin 1 0x2 Pin 2 0x3 Pin 3 0x4 Pin 4 0x5 Pin 5 0x6 Pin 6 0x7 Pin 7 Boot GPIO Polarity When set, this bit selects a high level for the GPIO port pin to enable the ROM boot loader at reset. When clear, this bit selects a low level for the GPIO port pin. 8 EN R/W 0x1 Boot GPIO Enable Clearing this bit enables the use of a GPIO pin to enable the ROM Boot Loader at reset. When this bit is set, the contents of address 0x0000.0004 are checked to see if the Flash memory has been programmed. If the contents are not 0xFFFF.FFFF, the core executes out of Flash memory. If the Flash has not been programmed, the core executes out of ROM. 7:2 reserved RO 0x3F 1 DBG1 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0x0 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. July 24, 2011 321 Texas Instruments-Production Data Internal Memory Register 15: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. The only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG section. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 322 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 16: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. July 24, 2011 323 Texas Instruments-Production Data Internal Memory Register 17: User Register 2 (USER_REG2), offset 0x1E8 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 2 (USER_REG2) Base 0x400F.E000 Offset 0x1E8 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 324 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 18: User Register 3 (USER_REG3), offset 0x1EC Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 3 (USER_REG3) Base 0x400F.E000 Offset 0x1EC Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. July 24, 2011 325 Texas Instruments-Production Data Internal Memory Register 19: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. 326 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 20: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 129 to 192 KB. July 24, 2011 327 Texas Instruments-Production Data Internal Memory Register 21: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 193 to 256 KB. 328 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 22: Flash Memory Protection Read Enable 4 (FMPRE4), offset 0x210 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 4 (FMPRE4) Base 0x400F.E000 Offset 0x210 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 257 to 320 KB. July 24, 2011 329 Texas Instruments-Production Data Internal Memory Register 23: Flash Memory Protection Read Enable 5 (FMPRE5), offset 0x214 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 5 (FMPRE5) Base 0x400F.E000 Offset 0x214 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 321 to 384 KB. 330 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 24: Flash Memory Protection Read Enable 6 (FMPRE6), offset 0x218 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 6 (FMPRE6) Base 0x400F.E000 Offset 0x218 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 0 Reset R/W 0 R/W 0 Description 0x00000000 Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 385 to 448 KB. July 24, 2011 331 Texas Instruments-Production Data Internal Memory Register 25: Flash Memory Protection Read Enable 7 (FMPRE7), offset 0x21C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 7 (FMPRE7) Base 0x400F.E000 Offset 0x21C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 0 Reset R/W 0 R/W 0 Description 0x00000000 Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 449 to 512 KB. 332 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 26: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. July 24, 2011 333 Texas Instruments-Production Data Internal Memory Register 27: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 129 to 192 KB. 334 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 28: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 193 to 256 KB. July 24, 2011 335 Texas Instruments-Production Data Internal Memory Register 29: Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 4 (FMPPE4) Base 0x400F.E000 Offset 0x410 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 257 to 320 KB. 336 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 30: Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 5 (FMPPE5) Base 0x400F.E000 Offset 0x414 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 321 to 384 KB. July 24, 2011 337 Texas Instruments-Production Data Internal Memory Register 31: Flash Memory Protection Program Enable 6 (FMPPE6), offset 0x418 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 6 (FMPPE6) Base 0x400F.E000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 0 R/W 0 Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 385 to 448 KB. 338 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 32: Flash Memory Protection Program Enable 7 (FMPPE7), offset 0x41C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 7 (FMPPE7) Base 0x400F.E000 Offset 0x41C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 0 R/W 0 Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 449 to 512 KB. July 24, 2011 339 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 8 Micro Direct Memory Access (μDMA) The LM3S1F11 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex™-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: ® ® ■ ARM PrimeCell 32-channel configurable µDMA controller ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Primary and secondary channel assignments – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable priority scheme – Optional software-initiated requests for any channel ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping – Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Transfer size is programmable in binary steps from 1 to 1024 ■ Source and destination address increment size of byte, half-word, word, or no increment ■ Maskable peripheral requests 340 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ Interrupt on transfer completion, with a separate interrupt per channel 8.1 Block Diagram Figure 8-1. μDMA Block Diagram uDMA Controller DMA error System Memory CH Control Table Peripheral DMA Channel 0 • • • Peripheral DMA Channel N-1 Nested Vectored Interrupt Controller (NVIC) IRQ General Peripheral N Registers request done request done request done DMASTAT DMACFG DMACTLBASE DMAALTBASE DMAWAITSTAT DMASWREQ DMAUSEBURSTSET DMAUSEBURSTCLR DMAREQMASKSET DMAREQMASKCLR DMAENASET DMAENACLR DMAALTSET DMAALTCLR DMAPRIOSET DMAPRIOCLR DMAERRCLR DMACHASGN DMACHIS DMASRCENDP DMADSTENDP DMACHCTRL • • • DMASRCENDP DMADSTENDP DMACHCTRL Transfer Buffers Used by µDMA ARM Cortex-M3 8.2 Functional Description The μDMA controller is a flexible and highly configurable DMA controller designed to work efficiently with the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow for sophisticated programmed data transfers. The μDMA controller's usage of the bus is always subordinate to the processor core, so it never holds up a bus transaction by the processor. Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth it provides is essentially free, with no impact on the rest of the system. The bus architecture has been optimized to greatly enhance the ability of the processor core and the μDMA controller to efficiently share the on-chip bus, thus improving performance. The optimizations include RAM striping and peripheral bus segmentation, which in many cases allow both the processor core and the μDMA controller to access the bus and perform simultaneous data transfers. The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. Each peripheral function that is supported has a dedicated channel on the μDMA controller that can be configured independently. The μDMA controller implements a unique configuration method using channel control structures that are maintained in system memory by the processor. While simple transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that allow the μDMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The μDMA controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or from a peripheral. July 24, 2011 341 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Each channel also has a configurable arbitration size. The arbitration size is the number of items that are transferred in a burst before the μDMA controller rearbitrates for channel priority. Using the arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time it makes a μDMA service request. 8.2.1 Channel Assignments μDMA channels 0-31 are assigned to peripherals according to the following table. The DMA Channel Assignment (DMACHASGN) register (see page 389) can be used to specify the primary or secondary assignment. If the primary function is not available on this microcontroller, the secondary function becomes the primary function. If the secondary function is not available, the primary function is the only option. Note: Channels noted in the table as "Available for software" may be assigned to peripherals in the future. However, they are currently available for software use. Channel 30 is dedicated for software use. Because of the way the μDMA controller interacts with peripherals, the μDMA channel for the peripheral must be enabled in order for the μDMA controller to be able to read and write the peripheral registers, even if a different μDMA channel is used to perform the μDMA transfer. To minimize confusion and chance of software errors, it is best practice to use a peripheral's μDMA channel for performing all μDMA transfers for that peripheral, even if it is processor-triggered and using AUTO mode, which could be considered a software transfer. Note that if the software channel is used, interrupts occur on the dedicated μDMA interrupt vector. If the peripheral channel is used, then the interrupt occurs on the interrupt vector for the peripheral. Table 8-1. μDMA Channel Assignments μDMA Channel Primary Assignment Secondary Assignment 0 Available for software UART2 Receive 1 Available for software UART2 Transmit 2 Available for software General-Purpose Timer 3A 3 Available for software General-Purpose Timer 3B 4 Available for software General-Purpose Timer 2A 5 Available for software General-Purpose Timer 2B 6 Available for software General-Purpose Timer 2A 7 Available for software General-Purpose Timer 2B 8 UART0 Receive UART1 Receive 9 UART0 Transmit UART1 Transmit 10 SSI0 Receive SSI1 Receive 11 SSI0 Transmit SSI1 Transmit 12 Available for software UART2 Receive 13 Available for software UART2 Transmit 14 ADC0 Sample Sequencer 0 General-Purpose Timer 2A 15 ADC0 Sample Sequencer 1 General-Purpose Timer 2B 16 ADC0 Sample Sequencer 2 Available for software 17 ADC0 Sample Sequencer 3 Available for software 18 General-Purpose Timer 0A General-Purpose Timer 1A 19 General-Purpose Timer 0B General-Purpose Timer 1B 342 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 8-1. μDMA Channel Assignments (continued) μDMA Channel 8.2.2 Primary Assignment Secondary Assignment 20 General-Purpose Timer 1A EPI0 NBRFIFO 21 General-Purpose Timer 1B EPI0 WFIFO 22 UART1 Receive Available for software 23 UART1 Transmit Available for software 24 SSI1 Receive Available for software 25 SSI1 Transmit Available for software 26 Available for software Available for software 27 Available for software Available for software 28 Available for software Available for software 29 Available for software Available for software 30 Dedicated for software use 31 Reserved Priority The μDMA controller assigns priority to each channel based on the channel number and the priority level bit for the channel. Channel number 0 has the highest priority and as the channel number increases, the priority of a channel decreases. Each channel has a priority level bit to provide two levels of priority: default priority and high priority. If the priority level bit is set, then that channel has higher priority than all other channels at default priority. If multiple channels are set for high priority, then the channel number is used to determine relative priority among all the high priority channels. The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET) register and cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register. 8.2.3 Arbitration Size When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels making a request and services the μDMA channel with the highest priority. Once a transfer begins, it continues for a selectable number of transfers before rearbitrating among the requesting channels again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers. After the μDMA controller transfers the number of items specified by the arbitration size, it then checks among all the channels making a request and services the channel with the highest priority. If a lower priority μDMA channel uses a large arbitration size, the latency for higher priority channels is increased because the μDMA controller completes the lower priority burst before checking for higher priority requests. Therefore, lower priority channels should not use a large arbitration size for best response on high priority channels. The arbitration size can also be thought of as a burst size. It is the maximum number of items that are transferred at any one time in a burst. Here, the term arbitration refers to determination of μDMA channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the processor always takes priority. Furthermore, the μDMA controller is held off whenever the processor must perform a bus transaction on the same bus, even in the middle of a burst transfer. 8.2.4 Request Types The μDMA controller responds to two types of requests from a peripheral: single or burst. Each peripheral may support either or both types of requests. A single request means that the peripheral July 24, 2011 343 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple items. The μDMA controller responds differently depending on whether the peripheral is making a single request or a burst request. If both are asserted, and the μDMA channel has been set up for a burst transfer, then the burst request takes precedence. See Table 8-2 on page 344, which shows how each peripheral supports the two request types. Table 8-2. Request Type Support 8.2.4.1 Peripheral Single Request Signal Burst Request Signal ADC None Sequencer IE bit EPI WFIFO None WFIFO Level (configurable) EPI NBRFIFO None NBRFIFO Level (configurable) General-Purpose Timer Raw interrupt pulse None SSI TX TX FIFO Not Full TX FIFO Level (fixed at 4) SSI RX RX FIFO Not Empty RX FIFO Level (fixed at 4) UART TX TX FIFO Not Full TX FIFO Level (configurable) UART RX RX FIFO Not Empty RX FIFO Level (configurable) Single Request When a single request is detected, and not a burst request, the μDMA controller transfers one item and then stops to wait for another request. 8.2.4.2 Burst Request When a burst request is detected, the μDMA controller transfers the number of items that is the lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration size should be the same as the number of data items that the peripheral can accommodate when making a burst request. For example, the UART generates a burst request based on the FIFO trigger level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer when the trigger level is reached. A burst transfer runs to completion once it is started, and cannot be interrupted, even by a higher priority channel. Burst transfers complete in a shorter time than the same number of non-burst transfers. It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps the nature of the data is such that it only makes sense when transferred together as a single unit rather than one piece at a time. The single request can be disabled by using the DMA Channel Useburst Set (DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the μDMA controller only responds to burst requests for that channel. 8.2.5 Channel Configuration The μDMA controller uses an area of system memory to store a set of channel control structures in a table. The control table may have one or two entries for each μDMA channel. Each entry in the table structure contains source and destination pointers, transfer size, and transfer mode. The control table can be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary. Table 8-3 on page 345 shows the layout in memory of the channel control table. Each channel may have one or two control structures in the control table: a primary control structure and an optional alternate control structure. The table is organized so that all of the primary entries are in the first half of the table, and all the alternate structures are in the second half of the table. The primary entry 344 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller is used for simple transfer modes where transfers can be reconfigured and restarted after each transfer is complete. In this case, the alternate control structures are not used and therefore only the first half of the table must be allocated in memory; the second half of the control table is not necessary, and that memory can be used for something else. If a more complex transfer mode is used such as ping-pong or scatter-gather, then the alternate control structure is also used and memory space should be allocated for the entire table. Any unused memory in the control table may be used by the application. This includes the control structures for any channels that are unused by the application as well as the unused control word for each channel. Table 8-3. Control Structure Memory Map Offset Channel 0x0 0, Primary 0x10 1, Primary ... ... 0x1F0 31, Primary 0x200 0, Alternate 0x210 1, Alternate ... 0x3F0 ... 31, Alternate Table 8-4 shows an individual control structure entry in the control table. Each entry is aligned on a 16-byte boundary. The entry contains four long words: the source end pointer, the destination end pointer, the control word, and an unused entry. The end pointers point to the ending address of the transfer and are inclusive. If the source or destination is non-incrementing (as for a peripheral register), then the pointer should point to the transfer address. Table 8-4. Channel Control Structure Offset Description 0x000 Source End Pointer 0x004 Destination End Pointer 0x008 Control Word 0x00C Unused The control word contains the following fields: ■ Source and destination data sizes ■ Source and destination address increment size ■ Number of transfers before bus arbitration ■ Total number of items to transfer ■ Useburst flag ■ Transfer mode The control word and each field are described in detail in “μDMA Channel Control Structure” on page 363. The μDMA controller updates the transfer size and transfer mode fields as July 24, 2011 345 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) the transfer is performed. At the end of a transfer, the transfer size indicates 0, and the transfer mode indicates "stopped." Because the control word is modified by the μDMA controller, it must be reconfigured before each new transfer. The source and destination end pointers are not modified, so they can be left unchanged if the source or destination addresses remain the same. Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the DMA Channel Enable Set (DMAENASET) register. A channel can be disabled by setting the channel bit in the DMA Channel Enable Clear (DMAENACLR) register. At the end of a complete μDMA transfer, the controller automatically disables the channel. 8.2.6 Transfer Modes The μDMA controller supports several transfer modes. Two of the modes support simple one-time transfers. Several complex modes support a continuous flow of data. 8.2.6.1 Stop Mode While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word. When the mode field has this value, the μDMA controller does not perform any transfers and disables the channel if it is enabled. At the end of a transfer, the μDMA controller updates the control word to set the mode to Stop. 8.2.6.2 Basic Mode In Basic mode, the μDMA controller performs transfers as long as there are more items to transfer, and a transfer request is present. This mode is used with peripherals that assert a μDMA request signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any situation where the request is momentary even though the entire transfer should be completed. For example, a software-initiated transfer creates a momentary request, and in Basic mode, only the number of transfers specified by the ARBSIZE field in the DMA Channel Control Word (DMACHCTL) register is transferred on a software request, even if there is more data to transfer. When all of the items have been transferred using Basic mode, the μDMA controller sets the mode for that channel to Stop. 8.2.6.3 Auto Mode Auto mode is similar to Basic mode, except that once a transfer request is received, the transfer runs to completion, even if the μDMA request is removed. This mode is suitable for software-triggered transfers. Generally, Auto mode is not used with a peripheral. When all the items have been transferred using Auto mode, the μDMA controller sets the mode for that channel to Stop. 8.2.6.4 Ping-Pong Ping-Pong mode is used to support a continuous data flow to or from a peripheral. To use Ping-Pong mode, both the primary and alternate data structures must be implemented. Both structures are set up by the processor for data transfer between memory and a peripheral. The transfer is started using the primary control structure. When the transfer using the primary control structure is complete, the μDMA controller reads the alternate control structure for that channel to continue the transfer. Each time this happens, an interrupt is generated, and the processor can reload the control structure for the just-completed transfer. Data flow can continue indefinitely this way, using the primary and alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. Refer to Figure 8-2 on page 347 for an example showing operation in Ping-Pong mode. 346 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 8-2. Example of Ping-Pong μDMA Transaction µDMA Controller SOURCE DEST CONTROL Unused transfers using BUFFER A transfer continues using alternate Primary Structure Cortex-M3 Processor SOURCE DEST CONTROL Unused Pe rip he ral /µD M AI nte Time transfers using BUFFER B SOURCE DEST CONTROL Unused Alternate Structure 8.2.6.5 SOURCE DEST CONTROL Unused BUFFER B · Process data in BUFFER A · Reload primary structure Pe rip he ral /µD M AI nte r transfers using BUFFER A rup t BUFFER A · Process data in BUFFER B · Reload alternate structure transfer continues using alternate Primary Structure rru p t transfer continues using primary Alternate Structure BUFFER A Pe rip he ral /µD M AI nte transfers using BUFFER B rru pt BUFFER B · Process data in BUFFER B · Reload alternate structure Memory Scatter-Gather Memory Scatter-Gather mode is a complex mode used when data must be transferred to or from varied locations in memory instead of a set of contiguous locations in a memory buffer. For example, a gather μDMA operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer. July 24, 2011 347 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) In Memory Scatter-Gather mode, the primary control structure is used to program the alternate control structure from a table in memory. The table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode. Each entry in the table is copied in turn to the alternate structure where it is then executed. The μDMA controller alternates between using the primary control structure to copy the next transfer instruction from the list and then executing the new transfer instruction. The end of the list is marked by programming the control word for the last entry to use Auto transfer mode. Once the last transfer is performed using Auto mode, the μDMA controller stops. A completion interrupt is generated only after the last transfer. It is possible to loop the list by having the last entry copy the primary control structure to point back to the beginning of the list (or to a new list). It is also possible to trigger a set of other channels to perform a transfer, either directly, by programming a write to the software trigger for another channel, or indirectly, by causing a peripheral action that results in a μDMA request. By programming the μDMA controller using this method, a set of arbitrary transfers can be performed based on a single μDMA request. Refer to Figure 8-3 on page 349 and Figure 8-4 on page 350, which show an example of operation in Memory Scatter-Gather mode. This example shows a gather operation, where data in three separate buffers in memory is copied together into one buffer. Figure 8-3 on page 349 shows how the application sets up a μDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. Figure 8-4 on page 350 shows the sequence as the μDMA controller performs the three sets of copy operations. First, using the primary control structure, the μDMA controller loads the alternate control structure with task A. It then performs the copy operation specified by task A, copying the data from the source buffer A to the destination buffer. Next, the μDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. 348 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 8-3. Memory Scatter-Gather, Setup and Configuration 1 2 3 Source and Destination Buffer in Memory Task List in Memory Channel Control Table in Memory 4 WORDS (SRC A) SRC A DST ITEMS=4 16 WORDS (SRC B) SRC Unused DST SRC ITEMS=12 DST B “TASK” A ITEMS=16 Channel Primary Control Structure “TASK” B Unused SRC DST ITEMS=1 “TASK” C Unused SRC DST Channel Alternate Control Structure ITEMS=n 1 WORD (SRC C) C 4 (DEST A) 16 (DEST B) 1 (DEST C) NOTES: 1. Application has a need to copy data items from three separate locations in memory into one combined buffer. 2. Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three µDMA copy “tasks.” 3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller. July 24, 2011 349 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI COPIED DST TASK A TASK B SRC SRC C ALT COPIED DST TASK C DEST A DEST B DEST C Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer A to the destination buffer. Using the channel’s primary control structure, the µDMA controller copies task A configuration to the channel’s alternate control structure. Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC B SRC PRI DST TASK A SRC TASK B TASK C SRC C COPIED ALT COPIED DST DEST A DEST B DEST C Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer B to the destination buffer. Using the channel’s primary control structure, the µDMA controller copies task B configuration to the channel’s alternate control structure. Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI DST TASK A SRC TASK B TASK C SRC C ALT DST DEST A COPIED COPIED DEST B DEST C Using the channel’s primary control structure, the µDMA controller copies task C configuration to the channel’s alternate control structure. Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer C to the destination buffer. 350 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 8.2.6.6 Peripheral Scatter-Gather Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers are controlled by a peripheral making a μDMA request. Upon detecting a request from the peripheral, the μDMA controller uses the primary control structure to copy one entry from the list to the alternate control structure and then performs the transfer. At the end of this transfer, the next transfer is started only if the peripheral again asserts a μDMA request. The μDMA controller continues to perform transfers from the list only when the peripheral is making a request, until the last transfer is complete. A completion interrupt is generated only after the last transfer. By using this method, the μDMA controller can transfer data to or from a peripheral from a set of arbitrary locations whenever the peripheral is ready to transfer data. Refer to Figure 8-5 on page 352 and Figure 8-6 on page 353, which show an example of operation in Peripheral Scatter-Gather mode. This example shows a gather operation, where data from three separate buffers in memory is copied to a single peripheral data register. Figure 8-5 on page 352 shows how the application sets up a µDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. Figure 8-6 on page 353 shows the sequence as the µDMA controller performs the three sets of copy operations. First, using the primary control structure, the µDMA controller loads the alternate control structure with task A. It then performs the copy operation specified by task A, copying the data from the source buffer A to the peripheral data register. Next, the µDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. July 24, 2011 351 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration 1 2 3 Source Buffer in Memory Task List in Memory Channel Control Table in Memory 4 WORDS (SRC A) SRC A DST ITEMS=4 16 WORDS (SRC B) SRC DST SRC ITEMS=12 DST B “TASK” A Unused ITEMS=16 Channel Primary Control Structure “TASK” B Unused SRC DST ITEMS=1 “TASK” C Unused SRC DST Channel Alternate Control Structure ITEMS=n 1 WORD (SRC C) C Peripheral Data Register DEST NOTES: 1. Application has a need to copy data items from three separate locations in memory into a peripheral data register. 2. Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three µDMA copy “tasks.” 3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller. 352 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI COPIED DST TASK A TASK B SRC SRC C ALT COPIED DST TASK C Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer A to the peripheral data register. Using the channel’s primary control structure, the µDMA controller copies task A configuration to the channel’s alternate control structure. Task List in Memory Peripheral Data Register Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI DST TASK A SRC TASK B TASK C SRC C COPIED ALT COPIED DST Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer B to the peripheral data register. Using the channel’s primary control structure, the µDMA controller copies task B configuration to the channel’s alternate control structure. Task List in Memory Peripheral Data Register Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI DST TASK A SRC TASK B TASK C SRC C ALT DST COPIED COPIED Peripheral Data Register Using the channel’s primary control structure, the µDMA controller copies task C configuration to the channel’s alternate control structure. Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer C to the peripheral data register. July 24, 2011 353 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 8.2.7 Transfer Size and Increment The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size must be the same for any given transfer. The source and destination address can be auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and destination address increment values can be set independently, and it is not necessary for the address increment to match the data size as long as the increment is the same or larger than the data size. For example, it is possible to perform a transfer using 8-bit data size, but using an address increment of full words (4 bytes). The data to be transferred must be aligned in memory according to the data size (8, 16, or 32 bits). Table 8-5 shows the configuration to read from a peripheral that supplies 8-bit data. Table 8-5. μDMA Read Example: 8-Bit Peripheral 8.2.8 Field Configuration Source data size 8 bits Destination data size 8 bits Source address increment No increment Destination address increment Byte Source end pointer Peripheral read FIFO register Destination end pointer End of the data buffer in memory Peripheral Interface Each peripheral that supports μDMA has a single request and/or burst request signal that is asserted when the peripheral is ready to transfer data (see Table 8-2 on page 344). The request signal can be disabled or enabled using the DMA Channel Request Mask Set (DMAREQMASKSET) and DMA Channel Request Mask Clear (DMAREQMASKCLR) registers. The μDMA request signal is disabled, or masked, when the channel request mask bit is set. When the request is not masked, the μDMA channel is configured correctly and enabled, and the peripheral asserts the request signal, the μDMA controller begins the transfer. Note: When using μDMA to transfer data to and from a peripheral, the peripheral must disable all interrupts to the NVIC. When a μDMA transfer is complete, the μDMA controller generates an interrupt, see “Interrupts and Errors” on page 355 for more information. For more information on how a specific peripheral interacts with the μDMA controller, refer to the DMA Operation section in the chapter that discusses that peripheral. 8.2.9 Software Request One μDMA channel is dedicated to software-initiated transfers. This channel also has a dedicated interrupt to signal completion of a μDMA transfer. A transfer is initiated by software by first configuring and enabling the transfer, and then issuing a software request using the DMA Channel Software Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should be used. It is possible to initiate a transfer on any channel using the DMASWREQ register. If a request is initiated by software using a peripheral μDMA channel, then the completion interrupt occurs on the interrupt vector for the peripheral instead of the software interrupt vector. Any channel may be used for software requests as long as the corresponding peripheral is not using μDMA for data transfer. 354 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 8.2.10 Interrupts and Errors When a μDMA transfer is complete, the μDMA controller generates a completion interrupt on the interrupt vector of the peripheral. Therefore, if μDMA is used to transfer data for a peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed to handle the μDMA transfer completion interrupt. If the transfer uses the software μDMA channel, then the completion interrupt occurs on the dedicated software μDMA interrupt vector (see Table 8-6 on page 355). When μDMA is enabled for a peripheral, the μDMA controller stops the normal transfer interrupts for a peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's interrupt registers). Thus, when a large amount of data is transferred using μDMA, instead of receiving multiple interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt when the transfer is complete. Unmasked peripheral error interrupts continue to be sent to the interrupt controller. When a μDMA channel generates a completion interrupt, the CHIS bit corresponding to the peripheral channel is set in the DMA Channel Interrupt Status (DMACHIS) register (see page 390). This register can be used by the peripheral interrupt handler code to determine if the interrupt was caused by the μDMA channel or an error event reported by the peripheral's interrupt registers. The completion interrupt request from the μDMA controller is automatically cleared when the interrupt handler is activated. If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data transfer, it disables the μDMA channel that caused the error and generates an interrupt on the μDMA error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be cleared by writing a 1 to the ERRCLR bit. Table 8-6 shows the dedicated interrupt assignments for the μDMA controller. Table 8-6. μDMA Interrupt Assignments Interrupt Assignment 46 μDMA Software Channel Transfer 47 μDMA Error 8.3 Initialization and Configuration 8.3.1 Module Initialization Before the μDMA controller can be used, it must be enabled in the System Control block and in the peripheral. The location of the channel control structure must also be programmed. The following steps should be performed one time during system initialization: 1. The μDMA peripheral must be enabled in the System Control block. To do this, set the UDMA bit of the System Control RCGC2 register (see page 255). 2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG) register. 3. Program the location of the channel control table by writing the base address of the table to the DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be aligned on a 1024-byte boundary. July 24, 2011 355 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 8.3.2 Configuring a Memory-to-Memory Transfer μDMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used for software-initiated, memory-to-memory transfer if the associated peripheral is not being used. 8.3.2.1 Configure the Channel Attributes First, configure the channel attributes: 1. Program bit 30 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 30 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 30 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 30 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 8.3.2.2 Configure the Channel Control Structure Now the channel control structure must be configured. This example transfers 256 words from one memory buffer to another. Channel 30 is used for a software transfer, and the control structure for channel 30 is at offset 0x1E0 of the channel control table. The channel control structure for channel 30 is located at the offsets shown in Table 8-7. Table 8-7. Channel Control Structure Offsets for Channel 30 Offset Description Control Table Base + 0x1E0 Channel 30 Source End Pointer Control Table Base + 0x1E4 Channel 30 Destination End Pointer Control Table Base + 0x1E8 Channel 30 Control Word Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). 1. Program the source end pointer at offset 0x1E0 to the address of the source buffer + 0x3FC. 2. Program the destination end pointer at offset 0x1E4 to the address of the destination buffer + 0x3FC. The control word at offset 0x1E8 must be programmed according to Table 8-8. Table 8-8. Channel Control Word Configuration for Memory Transfer Example Field in DMACHCTL Bits Value DSTINC 31:30 2 32-bit destination address increment DSTSIZE 29:28 2 32-bit destination data size SRCINC 27:26 2 32-bit source address increment SRCSIZE 25:24 2 32-bit source data size reserved 23:18 0 Reserved 356 Description July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 8-8. Channel Control Word Configuration for Memory Transfer Example (continued) Field in DMACHCTL Bits Description ARBSIZE 17:14 3 XFERSIZE 13:4 255 3 0 N/A for this transfer type 2:0 2 Use Auto-request transfer mode NXTUSEBURST XFERMODE 8.3.2.3 Value Arbitrates after 8 transfers Transfer 256 items Start the Transfer Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 30 of the DMA Channel Enable Set (DMAENASET) register. 2. Issue a transfer request by setting bit 30 of the DMA Channel Software Request (DMASWREQ) register. The μDMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt when the transfer is complete. If needed, the status can be checked by reading bit 30 of the DMAENASET register. This bit is automatically cleared when the transfer is complete. The status can also be checked by reading the XFERMODE field of the channel control word at offset 0x1E8. This field is automatically cleared at the end of the transfer. 8.3.3 Configuring a Peripheral for Simple Transmit This example configures the μDMA controller to transmit a buffer of data to a peripheral. The peripheral has a transmit FIFO with a trigger level of 4. The example peripheral uses μDMA channel 7. 8.3.3.1 Configure the Channel Attributes First, configure the channel attributes: 1. Configure bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 8.3.3.2 Configure the Channel Control Structure This example transfers 64 bytes from a memory buffer to the peripheral's transmit FIFO register using μDMA channel 7. The control structure for channel 7 is at offset 0x070 of the channel control table. The channel control structure for channel 7 is located at the offsets shown in Table 8-9. Table 8-9. Channel Control Structure Offsets for Channel 7 Offset Description Control Table Base + 0x070 Channel 7 Source End Pointer July 24, 2011 357 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Table 8-9. Channel Control Structure Offsets for Channel 7 (continued) Offset Description Control Table Base + 0x074 Channel 7 Destination End Pointer Control Table Base + 0x078 Channel 7 Control Word Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). Because the peripheral pointer does not change, it simply points to the peripheral's data register. 1. Program the source end pointer at offset 0x070 to the address of the source buffer + 0x3F. 2. Program the destination end pointer at offset 0x074 to the address of the peripheral's transmit FIFO register. The control word at offset 0x078 must be programmed according to Table 8-10. Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example Field in DMACHCTL Bits Value DSTINC 31:30 3 Destination address does not increment DSTSIZE 29:28 0 8-bit destination data size SRCINC 27:26 0 8-bit source address increment SRCSIZE 25:24 0 8-bit source data size reserved 23:18 0 Reserved ARBSIZE 17:14 2 Arbitrates after 4 transfers XFERSIZE 13:4 63 Transfer 64 items 3 0 N/A for this transfer type 2:0 1 Use Basic transfer mode NXTUSEBURST XFERMODE Note: 8.3.3.3 Description In this example, it is not important if the peripheral makes a single request or a burst request. Because the peripheral has a FIFO that triggers at a level of 4, the arbitration size is set to 4. If the peripheral does make a burst request, then 4 bytes are transferred, which is what the FIFO can accommodate. If the peripheral makes a single request (if there is any space in the FIFO), then one byte is transferred at a time. If it is important to the application that transfers only be made in bursts, then the Channel Useburst SET[7] bit should be set in the DMA Channel Useburst Set (DMAUSEBURSTSET) register. Start the Transfer Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 7 of the DMA Channel Enable Set (DMAENASET) register. The μDMA controller is now configured for transfer on channel 7. The controller makes transfers to the peripheral whenever the peripheral asserts a μDMA request. The transfers continue until the entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller disables the channel and sets the XFERMODE field of the channel control word to 0 (Stopped). The status of the transfer can be checked by reading bit 7 of the DMA Channel Enable Set (DMAENASET) register. This bit is automatically cleared when the transfer is complete. The status can also be checked by reading the XFERMODE field of the channel control word at offset 0x078. This field is automatically cleared at the end of the transfer. 358 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller If peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when the entire transfer is complete. 8.3.4 Configuring a Peripheral for Ping-Pong Receive This example configures the μDMA controller to continuously receive 8-bit data from a peripheral into a pair of 64-byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example peripheral uses μDMA channel 8. 8.3.4.1 Configure the Channel Attributes First, configure the channel attributes: 1. Configure bit 8 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 8 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 8 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 8 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 8.3.4.2 Configure the Channel Control Structure This example transfers bytes from the peripheral's receive FIFO register into two memory buffers of 64 bytes each. As data is received, when one buffer is full, the μDMA controller switches to use the other. To use Ping-Pong buffering, both primary and alternate channel control structures must be used. The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the alternate channel control structure is at offset 0x280. The channel control structures for channel 8 are located at the offsets shown in Table 8-11. Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 Offset Description Control Table Base + 0x080 Channel 8 Primary Source End Pointer Control Table Base + 0x084 Channel 8 Primary Destination End Pointer Control Table Base + 0x088 Channel 8 Primary Control Word Control Table Base + 0x280 Channel 8 Alternate Source End Pointer Control Table Base + 0x284 Channel 8 Alternate Destination End Pointer Control Table Base + 0x288 Channel 8 Alternate Control Word Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). Because the peripheral pointer does not change, it simply points to the peripheral's data register. Both the primary and alternate sets of pointers must be configured. 1. Program the primary source end pointer at offset 0x080 to the address of the peripheral's receive buffer. July 24, 2011 359 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 2. Program the primary destination end pointer at offset 0x084 to the address of ping-pong buffer A + 0x3F. 3. Program the alternate source end pointer at offset 0x280 to the address of the peripheral's receive buffer. 4. Program the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer B + 0x3F. The primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially programmed the same way. 1. Program the primary channel control word at offset 0x088 according to Table 8-12. 2. Program the alternate channel control word at offset 0x288 according to Table 8-12. Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example Field in DMACHCTL Bits Value DSTINC 31:30 0 8-bit destination address increment DSTSIZE 29:28 0 8-bit destination data size SRCINC 27:26 3 Source address does not increment SRCSIZE 25:24 0 8-bit source data size reserved 23:18 0 Reserved ARBSIZE 17:14 3 Arbitrates after 8 transfers XFERSIZE 13:4 63 Transfer 64 items 3 0 N/A for this transfer type 2:0 3 Use Ping-Pong transfer mode NXTUSEBURST XFERMODE Note: 8.3.4.3 Description In this example, it is not important if the peripheral makes a single request or a burst request. Because the peripheral has a FIFO that triggers at a level of 8, the arbitration size is set to 8. If the peripheral does make a burst request, then 8 bytes are transferred, which is what the FIFO can accommodate. If the peripheral makes a single request (if there is any data in the FIFO), then one byte is transferred at a time. If it is important to the application that transfers only be made in bursts, then the Channel Useburst SET[8] bit should be set in the DMA Channel Useburst Set (DMAUSEBURSTSET) register. Configure the Peripheral Interrupt An interrupt handler should be configured when using μDMA Ping-Pong mode, it is best to use an interrupt handler. However, the Ping-Pong mode can be configured without interrupts by polling. The interrupt handler is triggered after each buffer is complete. 1. Configure and enable an interrupt handler for the peripheral. 8.3.4.4 Enable the μDMA Channel Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 8 of the DMA Channel Enable Set (DMAENASET) register. 360 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 8.3.4.5 Process Interrupts The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral asserts the μDMA request signal, the μDMA controller makes transfers into buffer A using the primary channel control structure. When the primary transfer to buffer A is complete, it switches to the alternate channel control structure and makes transfers into buffer B. At the same time, the primary channel control word mode field is configured to indicate Stopped, and an interrupt is When an interrupt is triggered, the interrupt handler must determine which buffer is complete and process the data or set a flag that the data must be processed by non-interrupt buffer processing code. Then the next buffer transfer must be set up. In the interrupt handler: 1. Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the field is 0, this means buffer A is complete. If buffer A is complete, then: a. Process the newly received data in buffer A or signal the buffer processing code that buffer A has data available. b. Reprogram the primary channel control word at offset 0x88 according to Table 8-12 on page 360. 2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the field is 0, this means buffer B is complete. If buffer B is complete, then: a. Process the newly received data in buffer B or signal the buffer processing code that buffer B has data available. b. Reprogram the alternate channel control word at offset 0x288 according to Table 8-12 on page 360. 8.3.5 Configuring Channel Assignments Channel assignments for each μDMA channel can be changed using the DMACHASGN register. Each bit represents a μDMA channel. If the bit is set, then the secondary function is used for the channel. Refer to Table 8-1 on page 342 for channel assignments. For example, to use SSI1 Receive on channel 8 instead of UART0, set bit 8 of the DMACHASGN register. 8.4 Register Map Table 8-13 on page 362 lists the μDMA channel control structures and registers. The channel control structure shows the layout of one entry in the channel control table. The channel control table is located in system memory, and the location is determined by the application, that is, the base address is n/a (not applicable). In the table below, the offset for the channel control structures is the offset from the entry in the channel control table. See “Channel Configuration” on page 344 and Table 8-3 on page 345 for a description of how the entries in the channel control table are located in memory. The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers can be programmed (see page 255). There must be a delay of 3 system clocks after the μDMA module clock is enabled before any μDMA module registers are accessed. July 24, 2011 361 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Table 8-13. μDMA Register Map Offset Name Type Reset Description See page μDMA Channel Control Structure (Offset from Channel Control Table Base) 0x000 DMASRCENDP R/W - DMA Channel Source Address End Pointer 364 0x004 DMADSTENDP R/W - DMA Channel Destination Address End Pointer 365 0x008 DMACHCTL R/W - DMA Channel Control Word 366 DMA Status 371 DMA Configuration 373 μDMA Registers (Offset from μDMA Base Address) 0x000 DMASTAT RO 0x001F.0000 0x004 DMACFG WO - 0x008 DMACTLBASE R/W 0x0000.0000 DMA Channel Control Base Pointer 374 0x00C DMAALTBASE RO 0x0000.0200 DMA Alternate Channel Control Base Pointer 375 0x010 DMAWAITSTAT RO 0xFFFF.FFC0 DMA Channel Wait-on-Request Status 376 0x014 DMASWREQ WO - DMA Channel Software Request 377 0x018 DMAUSEBURSTSET R/W 0x0000.0000 DMA Channel Useburst Set 378 0x01C DMAUSEBURSTCLR WO - DMA Channel Useburst Clear 379 0x020 DMAREQMASKSET R/W 0x0000.0000 DMA Channel Request Mask Set 380 0x024 DMAREQMASKCLR WO - DMA Channel Request Mask Clear 381 0x028 DMAENASET R/W 0x0000.0000 DMA Channel Enable Set 382 0x02C DMAENACLR WO - DMA Channel Enable Clear 383 0x030 DMAALTSET R/W 0x0000.0000 DMA Channel Primary Alternate Set 384 0x034 DMAALTCLR WO - DMA Channel Primary Alternate Clear 385 0x038 DMAPRIOSET R/W 0x0000.0000 DMA Channel Priority Set 386 0x03C DMAPRIOCLR WO - DMA Channel Priority Clear 387 0x04C DMAERRCLR R/W 0x0000.0000 DMA Bus Error Clear 388 0x500 DMACHASGN R/W 0x0000.0000 DMA Channel Assignment 389 0x504 DMACHIS R/W1C 0x0000.0000 DMA Channel Interrupt Status 390 0xFD0 DMAPeriphID4 RO 0x0000.0004 DMA Peripheral Identification 4 395 0xFE0 DMAPeriphID0 RO 0x0000.0030 DMA Peripheral Identification 0 391 0xFE4 DMAPeriphID1 RO 0x0000.00B2 DMA Peripheral Identification 1 392 0xFE8 DMAPeriphID2 RO 0x0000.000B DMA Peripheral Identification 2 393 0xFEC DMAPeriphID3 RO 0x0000.0000 DMA Peripheral Identification 3 394 0xFF0 DMAPCellID0 RO 0x0000.000D DMA PrimeCell Identification 0 396 0xFF4 DMAPCellID1 RO 0x0000.00F0 DMA PrimeCell Identification 1 397 0xFF8 DMAPCellID2 RO 0x0000.0005 DMA PrimeCell Identification 2 398 362 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 8-13. μDMA Register Map (continued) Offset Name 0xFFC DMAPCellID3 8.5 Type Reset RO 0x0000.00B1 Description DMA PrimeCell Identification 3 See page 399 μDMA Channel Control Structure The μDMA Channel Control Structure holds the transfer settings for a μDMA channel. Each channel has two control structures, which are located in a table in system memory. Refer to “Channel Configuration” on page 344 for an explanation of the Channel Control Table and the Channel Control Structure. The channel control structure is one entry in the channel control table. Each channel has a primary and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. July 24, 2011 363 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 DMA Channel Source Address End Pointer (DMASRCENDP) is part of the Channel Control Structure and is used to specify the source address for a μDMA transfer. The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address. DMA Channel Source Address End Pointer (DMASRCENDP) Base n/a Offset 0x000 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Source Address End Pointer This field points to the last address of the μDMA transfer source (inclusive). If the source address is not incrementing (the SRCINC field in the DMACHCTL register is 0x3), then this field points at the source location itself (such as a peripheral data register). 364 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 DMA Channel Destination Address End Pointer (DMADSTENDP) is part of the Channel Control Structure and is used to specify the destination address for a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address. DMA Channel Destination Address End Pointer (DMADSTENDP) Base n/a Offset 0x004 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset ADDR Type Reset Bit/Field Name Type Reset 31:0 ADDR R/W - Description Destination Address End Pointer This field points to the last address of the μDMA transfer destination (inclusive). If the destination address is not incrementing (the DSTINC field in the DMACHCTL register is 0x3), then this field points at the destination location itself (such as a peripheral data register). July 24, 2011 365 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used to specify parameters of a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address. DMA Channel Control Word (DMACHCTL) Base n/a Offset 0x008 Type R/W, reset 31 30 DSTINC Type Reset 29 28 27 DSTSIZE 26 24 23 22 21 SRCSIZE 20 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 R/W - XFERSIZE R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:30 DSTINC R/W - 18 17 R/W - R/W - 3 2 R/W - R/W - R/W - R/W - R/W - R/W - R/W - 1 0 XFERMODE NXTUSEBURST R/W - 16 ARBSIZE R/W - R/W - 19 reserved R/W - ARBSIZE Type Reset 25 SRCINC R/W - R/W - R/W - Description Destination Address Increment This field configures the destination address increment. The address increment value must be equal or greater than the value of the destination size (DSTSIZE). Value Description 0x0 Byte Increment by 8-bit locations 0x1 Half-word Increment by 16-bit locations 0x2 Word Increment by 32-bit locations 0x3 No increment Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel 29:28 DSTSIZE R/W - Destination Data Size This field configures the destination item data size. Note: DSTSIZE must be the same as SRCSIZE. Value Description 0x0 Byte 8-bit data size 0x1 Half-word 16-bit data size 0x2 Word 32-bit data size 0x3 Reserved 366 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 27:26 SRCINC R/W - Description Source Address Increment This field configures the source address increment. The address increment value must be equal or greater than the value of the source size (SRCSIZE). Value Description 0x0 Byte Increment by 8-bit locations 0x1 Half-word Increment by 16-bit locations 0x2 Word Increment by 32-bit locations 0x3 No increment Address remains set to the value of the Source Address End Pointer (DMASRCENDP) for the channel 25:24 SRCSIZE R/W - Source Data Size This field configures the source item data size. Note: DSTSIZE must be the same as SRCSIZE. Value Description 0x0 Byte 8-bit data size. 0x1 Half-word 16-bit data size. 0x2 Word 32-bit data size. 0x3 23:18 reserved R/W - Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 367 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset 17:14 ARBSIZE R/W - Description Arbitration Size This field configures the number of transfers that can occur before the μDMA controller re-arbitrates. The possible arbitration rate configurations represent powers of 2 and are shown below. Value Description 0x0 1 Transfer Arbitrates after each μDMA transfer 0x1 2 Transfers 0x2 4 Transfers 0x3 8 Transfers 0x4 16 Transfers 0x5 32 Transfers 0x6 64 Transfers 0x7 128 Transfers 0x8 256 Transfers 0x9 512 Transfers 0xA-0xF 1024 Transfers In this configuration, no arbitration occurs during the μDMA transfer because the maximum transfer size is 1024. 13:4 XFERSIZE R/W - Transfer Size (minus 1) This field configures the total number of items to transfer. The value of this field is 1 less than the number to transfer (value 0 means transfer 1 item). The maximum value for this 10-bit field is 1023 which represents a transfer size of 1024 items. The transfer size is the number of items, not the number of bytes. If the data size is 32 bits, then this value is the number of 32-bit words to transfer. The μDMA controller updates this field immediately prior to entering the arbitration process, so it contains the number of outstanding items that is necessary to complete the μDMA cycle. 3 NXTUSEBURST R/W - Next Useburst This field controls whether the Useburst SET[n] bit is automatically set for the last transfer of a peripheral scatter-gather operation. Normally, for the last transfer, if the number of remaining items to transfer is less than the arbitration size, the μDMA controller uses single transfers to complete the transaction. If this bit is set, then the controller uses a burst transfer to complete the last transfer. 368 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 2:0 XFERMODE R/W - Description μDMA Transfer Mode This field configures the operating mode of the μDMA cycle. Refer to “Transfer Modes” on page 346 for a detailed explanation of transfer modes. Because this register is in system RAM, it has no reset value. Therefore, this field should be initialized to 0 before the channel is enabled. Value Description 0x0 Stop 0x1 Basic 0x2 Auto-Request 0x3 Ping-Pong 0x4 Memory Scatter-Gather 0x5 Alternate Memory Scatter-Gather 0x6 Peripheral Scatter-Gather 0x7 Alternate Peripheral Scatter-Gather XFERMODE Bit Field Values. Stop Channel is stopped or configuration data is invalid. No more transfers can occur. Basic For each trigger (whether from a peripheral or a software request), the μDMA controller performs the number of transfers specified by the ARBSIZE field. Auto-Request The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer of XFERSIZE items without any further requests. Ping-Pong This mode uses both the primary and alternate control structures for this channel. When the number of transfers specified by the XFERSIZE field have completed for the current control structure (primary or alternate), the µDMA controller switches to the other one. These switches continue until one of the control structures is not set to ping-pong mode. At that point, the µDMA controller stops. An interrupt is generated on completion of the transfers configured by each control structure. See “Ping-Pong” on page 346. Memory Scatter-Gather When using this mode, the primary control structure for the channel is configured to allow a list of operations (tasks) to be performed. The source address pointer specifies the start of a table of tasks to be copied to the alternate control structure for this channel. The XFERMODE field for the alternate control structure should be configured to 0x5 (Alternate memory scatter-gather) to perform the task. When the task completes, the µDMA switches back to the primary channel control structure, which then copies the next task to the alternate control structure. This process continues until the table of tasks is empty. The last task must have an XFERMODE value other than 0x5. Note that for continuous operation, the last task can update the primary channel control structure back to the start of the list or to another list. See “Memory Scatter-Gather” on page 347. July 24, 2011 369 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Alternate Memory Scatter-Gather This value must be used in the alternate channel control data structure when the μDMA controller operates in Memory Scatter-Gather mode. Peripheral Scatter-Gather This value must be used in the primary channel control data structure when the μDMA controller operates in Peripheral Scatter-Gather mode. In this mode, the μDMA controller operates exactly the same as in Memory Scatter-Gather mode, except that instead of performing the number of transfers specified by the XFERSIZE field in the alternate control structure at one time, the μDMA controller only performs the number of transfers specified by the ARBSIZE field per trigger; see Basic mode for details. See “Peripheral Scatter-Gather” on page 351. Alternate Peripheral Scatter-Gather This value must be used in the alternate channel control data structure when the μDMA controller operates in Peripheral Scatter-Gather mode. 8.6 μDMA Register Descriptions The register addresses given are relative to the μDMA base address of 0x400F.F000. 370 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 4: DMA Status (DMASTAT), offset 0x000 The DMA Status (DMASTAT) register returns the status of the μDMA controller. You cannot read this register when the μDMA controller is in the reset state. DMA Status (DMASTAT) Base 0x400F.F000 Offset 0x000 Type RO, reset 0x001F.0000 31 30 29 28 27 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 26 25 24 23 22 21 20 19 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 10 9 8 7 6 5 4 3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset STATE RO 0 17 16 RO 1 RO 1 RO 1 2 1 0 DMACHANS reserved Type Reset 18 reserved RO 0 MASTEN RO 0 RO 0 Bit/Field Name Type Reset Description 31:21 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20:16 DMACHANS RO 0x1F Available μDMA Channels Minus 1 This field contains a value equal to the number of μDMA channels the μDMA controller is configured to use, minus one. The value of 0x1F corresponds to 32 μDMA channels. 15:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 STATE RO 0x0 Control State Machine Status This field shows the current status of the control state machine. Status can be one of the following. Value Description 0x0 Idle 0x1 Reading channel controller data. 0x2 Reading source end pointer. 0x3 Reading destination end pointer. 0x4 Reading source data. 0x5 Writing destination data. 0x6 Waiting for µDMA request to clear. 0x7 Writing channel controller data. 0x8 Stalled 0x9 Done 0xA-0xF Undefined 3:1 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 371 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset 0 MASTEN RO 0 Description Master Enable Status Value Description 0 The μDMA controller is disabled. 1 The μDMA controller is enabled. 372 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 5: DMA Configuration (DMACFG), offset 0x004 The DMACFG register controls the configuration of the μDMA controller. DMA Configuration (DMACFG) Base 0x400F.F000 Offset 0x004 Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - reserved Type Reset reserved Type Reset WO - MASTEN WO - Bit/Field Name Type Reset Description 31:1 reserved WO - Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 MASTEN WO - Controller Master Enable Value Description 0 Disables the μDMA controller. 1 Enables μDMA controller. July 24, 2011 373 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 The DMACTLBASE register must be configured so that the base pointer points to a location in system memory. The amount of system memory that must be assigned to the μDMA controller depends on the number of μDMA channels used and whether the alternate channel control data structure is used. See “Channel Configuration” on page 344 for details about the Channel Control Table. The base address must be aligned on a 1024-byte boundary. This register cannot be read when the μDMA controller is in the reset state. DMA Channel Control Base Pointer (DMACTLBASE) Base 0x400F.F000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR Type Reset R/W 0 R/W 0 R/W 0 15 14 13 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 ADDR Type Reset R/W 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 R/W 0 RO 0 Bit/Field Name Type Reset 31:10 ADDR R/W 0x0000.00 RO 0 RO 0 RO 0 RO 0 Description Channel Control Base Address This field contains the pointer to the base address of the channel control table. The base address must be 1024-byte aligned. 9:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 374 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C The DMAALTBASE register returns the base address of the alternate channel control data. This register removes the necessity for application software to calculate the base address of the alternate channel control structures. This register cannot be read when the μDMA controller is in the reset state. DMA Alternate Channel Control Base Pointer (DMAALTBASE) Base 0x400F.F000 Offset 0x00C Type RO, reset 0x0000.0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 ADDR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 ADDR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type 31:0 ADDR RO RO 1 Reset RO 0 Description 0x0000.0200 Alternate Channel Address Pointer This field provides the base address of the alternate channel control structures. July 24, 2011 375 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can hold off the μDMA from performing a single request until the peripheral is ready for a burst request to enhance the μDMA performance. The use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. This register cannot be read when the μDMA controller is in the reset state. DMA Channel Wait-on-Request Status (DMAWAITSTAT) Base 0x400F.F000 Offset 0x010 Type RO, reset 0xFFFF.FFC0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WAITREQ[n] Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 8 7 6 5 4 3 2 1 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WAITREQ[n] Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type 31:0 WAITREQ[n] RO RO 1 Reset RO 1 RO 1 Description 0xFFFF.FFC0 Channel [n] Wait Status These bits provide the channel wait-on-request status. Bit 0 corresponds to channel 0. Value Description 1 The corresponding channel is waiting on a request. 0 The corresponding channel is not waiting on a request. 376 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 Each bit of the DMASWREQ register represents the corresponding μDMA channel. Setting a bit generates a request for the specified μDMA channel. DMA Channel Software Request (DMASWREQ) Base 0x400F.F000 Offset 0x014 Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - SWREQ[n] Type Reset SWREQ[n] Type Reset Bit/Field Name Type Reset 31:0 SWREQ[n] WO - WO - Description Channel [n] Software Request These bits generate software requests. Bit 0 corresponds to channel 0. Value Description 1 Generate a software request for the corresponding channel. 0 No request generated. These bits are automatically cleared when the software request has been completed. July 24, 2011 377 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 Each bit of the DMAUSEBURSTSET register represents the corresponding μDMA channel. Setting a bit disables the channel's single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST. If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET[n] bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than the arbitration (burst) size, the μDMA controller automatically clears the corresponding SET[n] bit, allowing the remaining items to transfer using single requests. In order to resume transfers using burst requests, the corresponding bit must be set again. A bit should not be set if the corresponding peripheral does not support the burst request model. Refer to “Request Types” on page 343 for more details about request types. DMA Channel Useburst Set (DMAUSEBURSTSET) Base 0x400F.F000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset SET[n] Type Reset Bit/Field Name Type 31:0 SET[n] R/W Reset Description 0x0000.0000 Channel [n] Useburst Set Value Description 0 μDMA channel [n] responds to single or burst requests. 1 μDMA channel [n] responds only to burst requests. Bit 0 corresponds to channel 0. This bit is automatically cleared as described above. A bit can also be manually cleared by setting the corresponding CLR[n] bit in the DMAUSEBURSTCLR register. 378 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C Each bit of the DMAUSEBURSTCLR register represents the corresponding μDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register. DMA Channel Useburst Clear (DMAUSEBURSTCLR) Base 0x400F.F000 Offset 0x01C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset CLR[n] Type Reset Bit/Field Name Type Reset 31:0 CLR[n] WO - Description Channel [n] Useburst Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register meaning that µDMA channel [n] responds to single and burst requests. July 24, 2011 379 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 Each bit of the DMAREQMASKSET register represents the corresponding μDMA channel. Setting a bit disables μDMA requests for the channel. Reading the register returns the request mask status. When a μDMA channel's request is masked, that means the peripheral can no longer request μDMA transfers. The channel can then be used for software-initiated transfers. DMA Channel Request Mask Set (DMAREQMASKSET) Base 0x400F.F000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SET[n] Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 SET[n] R/W R/W 0 Reset R/W 0 Description 0x0000.0000 Channel [n] Request Mask Set Value Description 0 The peripheral associated with channel [n] is enabled to request μDMA transfers. 1 The peripheral associated with channel [n] is not able to request μDMA transfers. Channel [n] may be used for software-initiated transfers. Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAREQMASKCLR register. 380 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 Each bit of the DMAREQMASKCLR register represents the corresponding μDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register. DMA Channel Request Mask Clear (DMAREQMASKCLR) Base 0x400F.F000 Offset 0x024 Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - Bit/Field Name Type Reset 31:0 CLR[n] WO - WO - Description Channel [n] Request Mask Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register meaning that the peripheral associated with channel [n] is enabled to request μDMA transfers. July 24, 2011 381 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit enables the corresponding µDMA channel. Reading the register returns the enable status of the channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be used for software-initiated transfers. DMA Channel Enable Set (DMAENASET) Base 0x400F.F000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset SET[n] Type Reset Bit/Field Name Type 31:0 SET[n] R/W Reset Description 0x0000.0000 Channel [n] Enable Set Value Description 0 µDMA Channel [n] is disabled. 1 µDMA Channel [n] is enabled. Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAENACLR register. 382 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAENASET register. DMA Channel Enable Clear (DMAENACLR) Base 0x400F.F000 Offset 0x02C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset CLR[n] Type Reset Bit/Field Name Type Reset 31:0 CLR[n] WO - Description Clear Channel [n] Enable Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAENASET register meaning that channel [n] is disabled for μDMA transfers. Note: The controller disables a channel when it completes the μDMA cycle. July 24, 2011 383 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 Each bit of the DMAALTSET register represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding µDMA channel. DMA Channel Primary Alternate Set (DMAALTSET) Base 0x400F.F000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset SET[n] Type Reset Bit/Field Name Type 31:0 SET[n] R/W Reset Description 0x0000.0000 Channel [n] Alternate Set Value Description 0 µDMA channel [n] is using the primary control structure. 1 µDMA channel [n] is using the alternate control structure. Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAALTCLR register. Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these bits to select the alternate channel control data structure. 384 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 Each bit of the DMAALTCLR register represents the corresponding μDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register. DMA Channel Primary Alternate Clear (DMAALTCLR) Base 0x400F.F000 Offset 0x034 Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - Bit/Field Name Type Reset 31:0 CLR[n] WO - WO - Description Channel [n] Alternate Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register meaning that channel [n] is using the primary control structure. Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these bits to select the alternate channel control data structure. July 24, 2011 385 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 Each bit of the DMAPRIOSET register represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to have a high priority level. Reading the register returns the status of the channel priority mask. DMA Channel Priority Set (DMAPRIOSET) Base 0x400F.F000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset SET[n] Type Reset Bit/Field Name Type 31:0 SET[n] R/W Reset Description 0x0000.0000 Channel [n] Priority Set Value Description 0 µDMA channel [n] is using the default priority level. 1 µDMA channel [n] is using a high priority level. Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAPRIOCLR register. 386 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C Each bit of the DMAPRIOCLR register represents the corresponding µDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register. DMA Channel Priority Clear (DMAPRIOCLR) Base 0x400F.F000 Offset 0x03C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset CLR[n] Type Reset Bit/Field Name Type Reset 31:0 CLR[n] WO - Description Channel [n] Priority Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register meaning that channel [n] is using the default priority level. July 24, 2011 387 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C The DMAERRCLR register is used to read and clear the µDMA bus error status. The error status is set if the μDMA controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that channel is automatically disabled by the μDMA controller. The other channels are unaffected. DMA Bus Error Clear (DMAERRCLR) Base 0x400F.F000 Offset 0x04C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 ERRCLR R/W1C 0 RO 0 ERRCLR R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Bus Error Status Value Description 0 No bus error is pending. 1 A bus error is pending. This bit is cleared by writing a 1 to it. 388 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 Each bit of the DMACHASGN register represents the corresponding µDMA channel. Setting a bit selects the secondary channel assignment as specified in Table 8-1 on page 342. DMA Channel Assignment (DMACHASGN) Base 0x400F.F000 Offset 0x500 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - CHASGN[n] Type Reset CHASGN[n] Type Reset Bit/Field Name Type Reset 31:0 CHASGN[n] R/W - R/W - Description Channel [n] Assignment Select Value Description 0 Use the primary channel assignment. 1 Use the secondary channel assignment. July 24, 2011 389 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504 Each bit of the DMACHIS register represents the corresponding µDMA channel. A bit is set when that μDMA channel causes a completion interrupt. The bits are cleared by a writing a 1. DMA Channel Interrupt Status (DMACHIS) Base 0x400F.F000 Offset 0x504 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 CHIS[n] Type Reset CHIS[n] Type Reset Bit/Field Name Type 31:0 CHIS[n] R/W1C Reset Description 0x0000.0000 Channel [n] Interrupt Status Value Description 1 The corresponding μDMA channel caused an interrupt. 0 The corresponding μDMA channel has not caused an interrupt. This bit is cleared by writing a 1 to it. 390 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 23: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 0 (DMAPeriphID0) Base 0x400F.F000 Offset 0xFE0 Type RO, reset 0x0000.0030 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x30 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. July 24, 2011 391 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 24: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 1 (DMAPeriphID1) Base 0x400F.F000 Offset 0xFE4 Type RO, reset 0x0000.00B2 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0xB2 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. 392 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 25: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 2 (DMAPeriphID2) Base 0x400F.F000 Offset 0xFE8 Type RO, reset 0x0000.000B 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x0B Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. July 24, 2011 393 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 26: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. DMA Peripheral Identification 3 (DMAPeriphID3) Base 0x400F.F000 Offset 0xFEC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. 394 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 27: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 4 (DMAPeriphID4) Base 0x400F.F000 Offset 0xFD0 Type RO, reset 0x0000.0004 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x04 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register Can be used by software to identify the presence of this peripheral. July 24, 2011 395 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 28: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 0 (DMAPCellID0) Base 0x400F.F000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 396 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 29: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 1 (DMAPCellID1) Base 0x400F.F000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. July 24, 2011 397 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 30: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 2 (DMAPCellID2) Base 0x400F.F000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 μDMA PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 398 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 31: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 3 (DMAPCellID3) Base 0x400F.F000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 μDMA PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. July 24, 2011 399 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) 9 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of nine physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H, Port J). The GPIO module supports up to 67 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ Up to 67 GPIOs, depending on configuration ■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions ■ 5-V-tolerant in input configuration ■ Fast toggle capable of a change every two clock cycles ■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with existing code ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can be used to initiate an ADC sample sequence ■ Pins configured as digital inputs are Schmitt-triggered ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 9.1 Signal Description GPIO signals have alternate hardware functions. The following table lists the GPIO pins and their analog and digital alternate functions. The AINx and VREFA analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to their circuitry (C0-, C0+, C1-, C1+). These 400 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. All GPIO signals are 5-V tolerant when configured as inputs except for PB0 and PB1, which are limited to 3.6 V. The digital alternate hardware functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric encoding shown in the table below. Note that each pin must be programmed individually; no type of grouping is implied by the columns in the table. Table entries that are shaded gray are the default values for the corresponding GPIO pin. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 9-1. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 GPIOPCTL 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 Table 9-2. GPIO Pins and Alternate Functions (100LQFP) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PA0 26 - U0Rx - - - - - - I2C1SCL U1Rx - - PA1 27 - U0Tx - - - - - - I2C1SDA U1Tx - - PA2 28 - SSI0Clk - - - - - - - - - - PA3 29 - SSI0Fss - - - - - - - - - - PA4 30 - SSI0Rx - - - - - - - - - - PA5 31 - SSI0Tx - - - - - - - - - - PA6 34 - I2C1SCL CCP1 - - - - - - U1CTS - - PA7 35 - I2C1SDA CCP4 - - - - CCP3 - U1DCD - - PB0 66 - CCP0 - - - U1Rx - - - - - - PB1 67 - CCP2 - - CCP1 U1Tx - - - - - - PB2 72 - I2C0SCL - - CCP3 CCP0 - - - - - - PB3 65 - I2C0SDA - - - - - - - - - - PB4 92 C0- - - - U2Rx - - U1Rx EPI0S23 - - - PB5 91 C1- C0o CCP5 CCP6 CCP0 - CCP2 U1Tx EPI0S22 - - - PB6 90 VREFA C0+ CCP1 CCP7 C0o - - CCP5 - - - - - PB7 89 - - - - NMI - - - - - - - PC0 80 - - - TCK SWCLK - - - - - - - - PC1 79 - - - TMS SWDIO - - - - - - - - PC2 78 - - - TDI - - - - - - - - July 24, 2011 401 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 9-2. GPIO Pins and Alternate Functions (100LQFP) (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PC3 77 - - - TDO SWO - - - - - - - - PC4 25 - CCP5 - - - CCP2 CCP4 - EPI0S2 CCP1 - - PC5 24 C1+ CCP1 C1o C0o - CCP3 - - EPI0S3 - - - PC6 23 - CCP3 - - - U1Rx CCP0 - EPI0S4 - - - PC7 22 - CCP4 - - CCP0 U1Tx - C1o EPI0S5 - - - PD0 10 - - - - U2Rx U1Rx CCP6 - - U1CTS - - PD1 11 - - - - U2Tx U1Tx CCP7 - - U1DCD CCP2 - PD2 12 - U1Rx CCP6 - CCP5 - - - EPI0S20 - - - PD3 13 - U1Tx CCP7 - CCP0 - - - EPI0S21 - - - PD4 97 AIN7 CCP0 CCP3 - - - - - - U1RI EPI0S19 - PD5 98 AIN6 CCP2 CCP4 - - - - - - U2Rx EPI0S28 - PD6 99 AIN5 - - - - - - - - U2Tx EPI0S29 - PD7 100 AIN4 - C0o CCP1 - - - - - U1DTR EPI0S30 - PE0 74 - - SSI1Clk CCP3 - - - - EPI0S8 - - - PE1 75 - - SSI1Fss - CCP2 CCP6 - - EPI0S9 - - - PE2 95 - CCP4 SSI1Rx - - CCP2 - - EPI0S24 - - - PE3 96 - CCP1 SSI1Tx - - CCP7 - - EPI0S25 - - - PE4 6 AIN3 CCP3 - - - U2Tx CCP2 - - - - - PE5 5 AIN2 CCP5 - - - - - - - - - - PE6 2 AIN1 - C1o - - - - - - U1CTS - - PE7 1 AIN0 - - - - - - - - U1DCD - - PF0 47 - - - - - - - - - U1DSR - - PF1 61 - - - - - - - - - U1RTS CCP3 - PF2 60 - - - - - - - - - SSI1Clk - - PF3 59 - - - - - - - - - SSI1Fss - - PF4 58 - CCP0 C0o - - - - - EPI0S12 SSI1Rx - - PF5 46 - CCP2 C1o - - - - - EPI0S15 SSI1Tx - - PF6 43 - CCP1 - - - - - - - - U1RTS - PF7 42 - CCP4 - - - - - - EPI0S12 - - - PG0 19 - U2Rx - I2C1SCL - - - - EPI0S13 - - - PG1 18 - U2Tx - I2C1SDA - - - - EPI0S14 - - - PG2 17 - - - - - - - - - - - - PG3 16 - - - - - - - - - - - - PG4 41 - CCP3 - - - - - - EPI0S15 - U1RI - PG5 40 - CCP5 - - - - - - - - U1DTR - PG6 37 - - - - - - - - - - U1RI - PG7 36 - - - - - - - - CCP5 EPI0S31 - - PH0 86 - CCP6 - - - - - - EPI0S6 - - - PH1 85 - CCP7 - - - - - - EPI0S7 - - - 402 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 9-2. GPIO Pins and Alternate Functions (100LQFP) (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PH2 84 - - C1o - - - - - EPI0S1 - - - PH3 83 - - - - - - - - EPI0S0 - - - PH4 76 - - - - - - - - EPI0S10 - - SSI1Clk PH5 63 - - - - - - - - EPI0S11 - - SSI1Fss PH6 62 - - - - - - - - EPI0S26 - - SSI1Rx PH7 15 - - - - - - - - EPI0S27 - - SSI1Tx PJ0 14 - - - - - - - - EPI0S16 - - I2C1SCL PJ1 87 - - - - - - - - EPI0S17 - - I2C1SDA PJ2 39 - - - - - - - - EPI0S18 CCP0 - - a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. Table 9-3. GPIO Pins and Alternate Functions (108BGA) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PA0 L3 - U0Rx - - - - - - I2C1SCL U1Rx - - PA1 M3 - U0Tx - - - - - - I2C1SDA U1Tx - - PA2 M4 - SSI0Clk - - - - - - - - - - PA3 L4 - SSI0Fss - - - - - - - - - - PA4 L5 - SSI0Rx - - - - - - - - - - PA5 M5 - SSI0Tx - - - - - - - - - - PA6 L6 - I2C1SCL CCP1 - - - - - - U1CTS - - PA7 M6 - I2C1SDA CCP4 - - - - CCP3 - U1DCD - - PB0 E12 - CCP0 - - - U1Rx - - - - - - PB1 D12 - CCP2 - - CCP1 U1Tx - - - - - - PB2 A11 - I2C0SCL - - CCP3 CCP0 - - - - - - PB3 E11 - I2C0SDA - - - - - - - - - - PB4 A6 C0- - - - U2Rx - - U1Rx EPI0S23 - - - PB5 B7 C1- C0o CCP5 CCP6 CCP0 - CCP2 U1Tx EPI0S22 - - - PB6 A7 VREFA C0+ CCP1 CCP7 C0o - - CCP5 - - - - - PB7 A8 - - - - NMI - - - - - - - PC0 A9 - - - TCK SWCLK - - - - - - - - PC1 B9 - - - TMS SWDIO - - - - - - - - PC2 B8 - - - TDI - - - - - - - - PC3 A10 - - - TDO SWO - - - - - - - - PC4 L1 - CCP5 - - - CCP2 CCP4 - EPI0S2 CCP1 - - PC5 M1 C1+ CCP1 C1o C0o - CCP3 - - EPI0S3 - - - PC6 M2 - CCP3 - - - U1Rx CCP0 - EPI0S4 - - - July 24, 2011 403 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 9-3. GPIO Pins and Alternate Functions (108BGA) (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PC7 L2 - CCP4 - - CCP0 U1Tx - C1o EPI0S5 - - - PD0 G1 - - - - U2Rx U1Rx CCP6 - - U1CTS - - PD1 G2 - - - - U2Tx U1Tx CCP7 - - U1DCD CCP2 - PD2 H2 - U1Rx CCP6 - CCP5 - - - EPI0S20 - - - PD3 H1 - U1Tx CCP7 - CCP0 - - - EPI0S21 - - - PD4 B5 AIN7 CCP0 CCP3 - - - - - - U1RI EPI0S19 - PD5 C6 AIN6 CCP2 CCP4 - - - - - - U2Rx EPI0S28 - PD6 A3 AIN5 - - - - - - - - U2Tx EPI0S29 - PD7 A2 AIN4 - C0o CCP1 - - - - - U1DTR EPI0S30 - PE0 B11 - - SSI1Clk CCP3 - - - - EPI0S8 - - - PE1 A12 - - SSI1Fss - CCP2 CCP6 - - EPI0S9 - - - PE2 A4 - CCP4 SSI1Rx - - CCP2 - - EPI0S24 - - - PE3 B4 - CCP1 SSI1Tx - - CCP7 - - EPI0S25 - - - PE4 B2 AIN3 CCP3 - - - U2Tx CCP2 - - - - - PE5 B3 AIN2 CCP5 - - - - - - - - - - PE6 A1 AIN1 - C1o - - - - - - U1CTS - - PE7 B1 AIN0 - - - - - - - - U1DCD - - PF0 M9 - - - - - - - - - U1DSR - - PF1 H12 - - - - - - - - - U1RTS CCP3 - PF2 J11 - - - - - - - - - SSI1Clk - - PF3 J12 - - - - - - - - - SSI1Fss - - PF4 L9 - CCP0 C0o - - - - - EPI0S12 SSI1Rx - - PF5 L8 - CCP2 C1o - - - - - EPI0S15 SSI1Tx - - PF6 M8 - CCP1 - - - - - - - - U1RTS - PF7 K4 - CCP4 - - - - - - EPI0S12 - - - PG0 K1 - U2Rx - I2C1SCL - - - - EPI0S13 - - - PG1 K2 - U2Tx - I2C1SDA - - - - EPI0S14 - - - PG2 J1 - - - - - - - - - - - - PG3 J2 - - - - - - - - - - - - PG4 K3 - CCP3 - - - - - - EPI0S15 - U1RI - PG5 M7 - CCP5 - - - - - - - - U1DTR - PG6 L7 - - - - - - - - - - U1RI - PG7 C10 - - - - - - - - CCP5 EPI0S31 - - PH0 C9 - CCP6 - - - - - - EPI0S6 - - - PH1 C8 - CCP7 - - - - - - EPI0S7 - - - PH2 D11 - - C1o - - - - - EPI0S1 - - - PH3 D10 - - - - - - - - EPI0S0 - - - PH4 B10 - - - - - - - - EPI0S10 - - SSI1Clk PH5 F10 - - - - - - - - EPI0S11 - - SSI1Fss PH6 G3 - - - - - - - - EPI0S26 - - SSI1Rx 404 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 9-3. GPIO Pins and Alternate Functions (108BGA) (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PH7 H3 - - - - - - - - EPI0S27 - - SSI1Tx PJ0 F3 - - - - - - - - EPI0S16 - - I2C1SCL PJ1 B6 - - - - - - - - EPI0S17 - - I2C1SDA PJ2 K6 - - - - - - - - EPI0S18 CCP0 - - a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. 9.2 Functional Description Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 9-1 on page 405 and Figure 9-2 on page 406). The LM3S1F11 microcontroller contains nineports and thus nine of these physical GPIO blocks. Note that not all pins may be implemented on every block. Some GPIO pins can function as I/O signals for the on-chip peripheral modules. For information on which GPIO pins are used for alternate hardware functions, refer to Table 19-5 on page 854. Figure 9-1. Digital I/O Pads Commit Control GPIOLOCK GPIOCR Port Control GPIOPCTL Mode Control GPIOAFSEL Periph 1 DEMUX Alternate Input Alternate Output Alternate Output Enable MUX Periph 0 Pad Input Periph n GPIO Output GPIO Output Enable Interrupt Control Pad Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN MUX GPIODATA GPIODIR Interrupt MUX GPIO Input Data Control Pad Output Digital I/O Pad Package I/O Pin Pad Output Enable Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 July 24, 2011 405 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Figure 9-2. Analog/Digital I/O Pads Commit Control GPIOLOCK GPIOCR Port Control GPIOPCTL Mode Control GPIOAFSEL Periph 1 DEMUX Alternate Input Alternate Output Alternate Output Enable MUX Periph 0 Pad Input Periph n MUX MUX Data Control Pad Output Pad Output Enable Analog/Digital I/O Pad Package I/O Pin GPIO Input GPIO Output GPIODATA GPIODIR Interrupt GPIO Output Enable Interrupt Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Pad Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN GPIOAMSEL Analog Circuitry Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 9.2.1 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 ADC (for GPIO pins that connect to the ADC input MUX) Isolation Circuit Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. 9.2.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 415) is used to configure each individual pin as an input or output. When the data direction bit is cleared, the GPIO is configured as an input, and the corresponding data register bit captures and stores the value on the GPIO port. When the data direction bit is set, the GPIO is configured as an output, and the corresponding data register bit is driven out on the GPIO port. 406 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 9.2.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 414) by using bits [9:2] of the address bus as a mask. In this manner, software drivers can modify individual GPIO pins in a single instruction without affecting the state of the other pins. This method is more efficient than the conventional method of performing a read-modify-write operation to set or clear an individual GPIO pin. To implement this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set, the value of the GPIODATA register is altered. If the address bit is cleared, the data bit is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 has the results shown in Figure 9-3, where u indicates that data is unchanged by the write. Figure 9-3. GPIODATA Write Example ADDR[9:2] 0x098 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 0 0 0 0xEB 1 1 1 0 1 0 1 1 GPIODATA u u 1 u u 0 1 u 7 6 5 4 3 2 1 0 During a read, if the address bit associated with the data bit is set, the value is read. If the address bit associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-4. Figure 9-4. GPIODATA Read Example 9.2.2 ADDR[9:2] 0x0C4 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 1 0 0 GPIODATA 1 0 1 1 1 1 1 0 Returned Value 0 0 1 1 0 0 0 0 7 6 5 4 3 2 1 0 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. These registers are used to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, the external source must hold the level constant for the interrupt to be recognized by the controller. Three registers define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 416) July 24, 2011 407 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 417) ■ GPIO Interrupt Event (GPIOIEV) register (see page 418) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 419). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 420 and page 421). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the interrupt controller. Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR) register (see page 423). When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts should be masked (GPIOIM cleared). Writing any value to an interrupt control register can generate a spurious interrupt if the corresponding bits are enabled. 9.2.2.1 ADC Trigger Source In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set), an interrupt for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. See page 632. If no other Port B pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0) register can disable the Port B interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts on PB4 and wait for the ADC interrupt, or the ADC interrupt must be disabled in the EN0 register and the Port B interrupt handler must poll the ADC registers until the conversion is completed. See page 111 for more information. 9.2.3 Mode Control The GPIO pins can be controlled by either software or hardware. Software control is the default for most signals and corresponds to the GPIO mode, where the GPIODATA register is used to read or write the corresponding pins. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 424), the pin state is controlled by its alternate function (that is, the peripheral). Further pin muxing options are provided through the GPIO Port Control (GPIOPCTL) register which selects one of several peripheral functions for each GPIO. For information on the configuration options, refer to Table 19-5 on page 854. Note: 9.2.4 If any pin is to be used as an ADC input, the appropriate bit in the GPIOAMSEL register must be set to disable the analog isolation circuit. Commit Control The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 424), GPIO Pull Up Select (GPIOPUR) register (see page 430), GPIO Pull-Down Select (GPIOPDR) register (see page 432), and GPIO Digital Enable (GPIODEN) register (see 408 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller page 435) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 437) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 438) have been set. 9.2.5 Pad Control The pad control registers allow software to configure the GPIO pads based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable for each GPIO. For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. 9.2.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 9.3 Initialization and Configuration The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides better back-to-back access performance than the APB bus. These apertures are mutually exclusive. The aperture enabled for a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL register (see page 209). To use the pins in a particular GPIO port, the clock for the port must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register (see page 255). When the internal POR signal is asserted and until otherwise configured, all GPIO pins are configured to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0, except for the pins shown in Table 9-1 on page 401. Table 9-4 on page 409 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 9-5 on page 410 shows how a rising edge interrupt is configured for pin 2 of a GPIO port. Table 9-4. GPIO Pad Configuration Examples a Configuration Digital Input (GPIO) GPIO Register Bit Value AFSEL 0 DIR ODR 0 0 DEN 1 PUR ? PDR ? DR2R DR4R DR8R X X X SLR X Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ? Open Drain Output (GPIO) 0 1 1 1 X X ? ? ? ? Open Drain Input/Output (I2C) 1 X 1 1 X X ? ? ? ? Digital Input (Timer CCP) 1 X 0 1 ? ? X X X X July 24, 2011 409 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 9-4. GPIO Pad Configuration Examples (continued) a GPIO Register Bit Value Configuration DR2R DR4R DR8R Digital Output (Timer PWM) AFSEL 1 DIR X ODR 0 DEN 1 PUR ? PDR ? ? ? ? SLR ? Digital Input/Output (SSI) 1 X 0 1 ? ? ? ? ? ? Digital Input/Output (UART) 1 X 0 1 ? ? ? ? ? ? Analog Input (Comparator) 0 0 0 0 0 0 X X X X Digital Output (Comparator) 1 X 0 1 ? ? ? ? ? ? a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 9-5. GPIO Interrupt Configuration Example Desired Interrupt Event Trigger Register GPIOIS 0=edge a Pin 2 Bit Value 7 6 5 4 3 2 1 0 X X X X X 0 X X X X X X X 0 X X X X X X X 1 X X 0 0 0 0 0 1 0 0 1=level GPIOIBE 0=single edge 1=both edges GPIOIEV 0=Low level, or falling edge 1=High level, or rising edge GPIOIM 0=masked 1=not masked a. X=Ignored (don’t care bit) 9.4 Register Map Table 9-7 on page 411 lists the GPIO registers. Each GPIO port can be accessed through one of two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides better back-to-back access performance than the APB bus. Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to unconnected bits has no effect, and reading unconnected bits returns no meaningful data. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: ■ ■ ■ ■ GPIO Port A (APB): 0x4000.4000 GPIO Port A (AHB): 0x4005.8000 GPIO Port B (APB): 0x4000.5000 GPIO Port B (AHB): 0x4005.9000 410 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ GPIO Port C (APB): 0x4000.6000 GPIO Port C (AHB): 0x4005.A000 GPIO Port D (APB): 0x4000.7000 GPIO Port D (AHB): 0x4005.B000 GPIO Port E (APB): 0x4002.4000 GPIO Port E (AHB): 0x4005.C000 GPIO Port F (APB): 0x4002.5000 GPIO Port F (AHB): 0x4005.D000 GPIO Port G (APB): 0x4002.6000 GPIO Port G (AHB): 0x4005.E000 GPIO Port H (APB): 0x4002.7000 GPIO Port H (AHB): 0x4005.F000 GPIO Port J (APB): 0x4003.D000 GPIO Port J (AHB): 0x4006.0000 Note that each GPIO module clock must be enabled before the registers can be programmed (see page 255). There must be a delay of 3 system clocks after the GPIO module clock is enabled before any GPIO module registers are accessed. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 9-6. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL PA[1:0] UART0 0 1 0 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as GPIO pins, the PC[3:0] pins default to non-committable. Similarly, to ensure that the NMI pin is not accidentally programmed as a GPIO pin, the PB7 pin defaults to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 9-7. GPIO Register Map Description See page Offset Name Type Reset 0x000 GPIODATA R/W 0x0000.0000 GPIO Data 414 0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 415 0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 416 July 24, 2011 411 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 9-7. GPIO Register Map (continued) Description See page Offset Name Type Reset 0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 417 0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 418 0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 419 0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 420 0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 421 0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 423 0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 424 0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 426 0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 427 0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 428 0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 429 0x510 GPIOPUR R/W - GPIO Pull-Up Select 430 0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 432 0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 434 0x51C GPIODEN R/W - GPIO Digital Enable 435 0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 437 0x524 GPIOCR - - GPIO Commit 438 0x528 GPIOAMSEL R/W 0x0000.0000 GPIO Analog Mode Select 440 0x52C GPIOPCTL R/W - GPIO Port Control 442 0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 444 0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 445 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 446 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 447 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 448 0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 449 0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 450 0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 451 0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 452 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 453 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 454 0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 455 412 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 9.5 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. July 24, 2011 413 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 415). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be set. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are set in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are clear in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DATA R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and written to the registers are masked by the eight address lines [9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ADDR[9:2] and are configured as outputs. See “Data Register Operation” on page 407 for examples of reads and writes. 414 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be an input. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DIR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DIR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Data Direction Value Description 0 Corresponding pin is an input. 1 Corresponding pins is an output. July 24, 2011 415 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 IS R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Sense Value Description 0 The edge on the corresponding pin is detected (edge-sensitive). 1 The level on the corresponding pin is detected (level-sensitive). 416 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 416) is set to detect edges, setting a bit in the GPIOIBE register configures the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 418). Clearing a bit configures the pin to be controlled by the GPIOIEV register. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IBE RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 IBE R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Both Edges Value Description 0 Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 418). 1 Both edges on the corresponding pin trigger an interrupt. July 24, 2011 417 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 416). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in the GPIOIS register. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IEV RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 IEV R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Event Value Description 0 A falling edge or a Low level on the corresponding pin triggers an interrupt. 1 A rising edge or a High level on the corresponding pin triggers an interrupt. 418 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IME RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 IME R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Mask Enable Value Description 0 The interrupt from the corresponding pin is masked. 1 The interrupt from the corresponding pin is sent to the interrupt controller. July 24, 2011 419 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin. If the corresponding bit in the GPIO Interrupt Mask (GPIOIM) register (see page 419) is set, the interrupt is sent to the interrupt controller. Bits read as zero indicate that corresponding input pins have not initiated an interrupt. A bit in this register can be cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 RIS RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Raw Status Value Description 1 An interrupt condition has occurred on the corresponding pin. 0 An interrupt condition has not occurred on the corresponding pin. A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register. 420 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set), an interrupt for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. See page 632. If no other Port B pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0) register can disable the Port B interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts on PB4 and wait for the ADC interrupt, or the ADC interrupt must be disabled in the EN0 register and the Port B interrupt handler must poll the ADC registers until the conversion is completed. See page 111 for more information. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 MIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 421 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset Description 7:0 MIS RO 0x00 GPIO Masked Interrupt Status Value Description 1 An interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller. 0 An interrupt condition on the corresponding pin is masked or has not occurred. A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register. 422 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt bit in the GPIORIS and GPIOMIS registers. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 W1C 0 W1C 0 W1C 0 W1C 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IC RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 IC W1C 0x00 RO 0 W1C 0 W1C 0 W1C 0 W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Clear Value Description 1 The corresponding interrupt is cleared. 0 The corresponding interrupt is unaffected. July 24, 2011 423 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. If a bit is clear, the pin is used as a GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral functions are multiplexed on each GPIO. The GPIO Port Control (GPIOPCTL) register is used to select one of the possible functions. Table 19-5 on page 854 details which functions are muxed on each GPIO pin. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in the table below. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 9-8. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 0 GPIOPCTL 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 424), GPIO Pull Up Select (GPIOPUR) register (see page 430), GPIO Pull-Down Select (GPIOPDR) register (see page 432), and GPIO Digital Enable (GPIODEN) register (see page 435) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 437) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 438) have been set. When using the I2C module, in addition to setting the GPIOAFSEL register bits for the I2C clock and data pins, the data pins should be set to open drain using the GPIO Open Drain Select (GPIOODR) register (see examples in “Initialization and Configuration” on page 409). 424 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x420 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 AFSEL RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 AFSEL R/W - RO 0 R/W - R/W - R/W - R/W - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Alternate Function Select Value Description 0 The associated pin functions as a GPIO and is controlled by the GPIO registers. 1 The associated pin functions as a peripheral signal and is controlled by the alternate hardware function. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 9-1 on page 401. July 24, 2011 425 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default, all GPIO pins have 2-mA drive. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV2 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DRV2 R/W 0xFF RO 0 R/W 1 R/W 1 R/W 1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 2-mA Drive Enable Value Description 1 The corresponding GPIO pin has 2-mA drive. 0 The drive for the corresponding GPIO pin is controlled by the GPIODR4R or GPIODR8R register. Setting a bit in either the GPIODR4 register or the GPIODR8 register clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. 426 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV4 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DRV4 R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 4-mA Drive Enable Value Description 1 The corresponding GPIO pin has 4-mA drive. 0 The drive for the corresponding GPIO pin is controlled by the GPIODR2R or GPIODR8R register. Setting a bit in either the GPIODR2 register or the GPIODR8 register clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. July 24, 2011 427 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and DRV4 bit in the GPIODR4R register are automatically cleared by hardware. The 8-mA setting is also used for high-current operation. Note: There is no configuration difference between 8-mA and high-current operation. The additional current capacity results from a shift in the VOH/VOL levels. See “Recommended Operating Conditions” on page 887 for further information. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV8 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DRV8 R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 8-mA Drive Enable Value Description 1 The corresponding GPIO pin has 8-mA drive. 0 The drive for the corresponding GPIO pin is controlled by the GPIODR2R or GPIODR4R register. Setting a bit in either the GPIODR2 register or the GPIODR4 register clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. 428 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 435). Corresponding bits in the drive strength and slew rate control registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts as an input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no effect until the GPIO is changed to an output. When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set (see examples in “Initialization and Configuration” on page 409). GPIO Open Drain Select (GPIOODR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 ODE RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 ODE R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad Open Drain Enable Value Description 1 The corresponding pin is configured as open drain. 0 The corresponding pin is not configured as open drain. July 24, 2011 429 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 432). Write access to this register is protected with the GPIOCR register. Bits in GPIOCR that are cleared prevent writes to the equivalent bit in this register. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 9-9. GPIO Pins With Non-Zero Reset Values Note: GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 GPIOPCTL 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 424), GPIO Pull Up Select (GPIOPUR) register (see page 430), GPIO Pull-Down Select (GPIOPDR) register (see page 432), and GPIO Digital Enable (GPIODEN) register (see page 435) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 437) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 438) have been set. GPIO Pull-Up Select (GPIOPUR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x510 Type R/W, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - reserved Type Reset reserved Type Reset RO 0 PUE 430 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PUE R/W - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Pad Weak Pull-Up Enable Value Description 1 The corresponding pin has a weak pull-up resistor. 0 The corresponding pin is not affected. Setting a bit in the GPIOPDR register clears the corresponding bit in the GPIOPUR register. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 9-1 on page 401. July 24, 2011 431 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set, a weak pull-down resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 430). Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 9-10. GPIO Pins With Non-Zero Reset Values Note: GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 GPIOPCTL 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 424), GPIO Pull Up Select (GPIOPUR) register (see page 430), GPIO Pull-Down Select (GPIOPDR) register (see page 432), and GPIO Digital Enable (GPIODEN) register (see page 435) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 437) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 438) have been set. GPIO Pull-Down Select (GPIOPDR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 PDE 432 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PDE R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Pad Weak Pull-Down Enable Value Description 1 The corresponding pin has a weak pull-down resistor. 0 The corresponding pin is not affected. Setting a bit in the GPIOPUR register clears the corresponding bit in the GPIOPDR register. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. July 24, 2011 433 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 428). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 SRL RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 SRL R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Slew Rate Limit Enable (8-mA drive only) Value Description 1 Slew rate control is enabled for the corresponding pin. 0 Slew rate control is disabled for the corresponding pin. 434 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin as a digital input or output (either GPIO or alternate function), the corresponding GPIODEN bit must be set. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 9-11. GPIO Pins With Non-Zero Reset Values Note: GPIO Pins Default State GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL PA[1:0] UART0 0 1 0 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 424), GPIO Pull Up Select (GPIOPUR) register (see page 430), GPIO Pull-Down Select (GPIOPDR) register (see page 432), and GPIO Digital Enable (GPIODEN) register (see page 435) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 437) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 438) have been set. July 24, 2011 435 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) GPIO Digital Enable (GPIODEN) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x51C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DEN RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DEN R/W - RO 0 R/W - R/W - R/W - R/W - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Enable Value Description 0 The digital functions for the corresponding pin are disabled. 1 The digital functions for the corresponding pin are enabled. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 9-1 on page 401. 436 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 438). Writing 0x4C4F.434B to the GPIOLOCK register unlocks the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x0000.0001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x0000.0000. GPIO Lock (GPIOLOCK) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 LOCK R/W R/W 0 Reset R/W 0 Description 0x0000.0001 GPIO Lock A write of the value 0x4C4F.434B unlocks the GPIO Commit (GPIOCR) register for write access.A write of any other value or a write to the GPIOCR register reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x1 The GPIOCR register is locked and may not be modified. 0x0 The GPIOCR register is unlocked and may be modified. July 24, 2011 437 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN registers are committed when a write to these registers is performed. If a bit in the GPIOCR register is cleared, the data being written to the corresponding bit in the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers cannot be committed and retains its previous value. If a bit in the GPIOCR register is set, the data being written to the corresponding bit of the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers is committed to the register and reflects the new value. The contents of the GPIOCR register can only be modified if the status in the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the status in the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the registers that control connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the NMI and JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the corresponding registers. Because this protection is currently only implemented on the NMI and JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN register bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x524 Type -, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 - - - - - - - - reserved Type Reset reserved Type Reset RO 0 CR 438 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CR - - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Commit Value Description 1 The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits can be written. 0 The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits cannot be written. Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as GPIO pins, the PC[3:0] pins default to non-committable. Similarly, to ensure that the NMI pin is not accidentally programmed as a GPIO pin, the PB7 pin defaults to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. July 24, 2011 439 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 Important: This register is only valid for ports D and E; the corresponding base addresses for the remaining ports are not valid. If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be set to disable the analog isolation circuit. The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because the GPIOs may be driven by a 5-V source and affect analog operation, analog circuitry requires isolation from the pins when they are not used in their analog function. Each bit of this register controls the isolation circuitry for the corresponding GPIO signal. For information on which GPIO pins can be used for ADC functions, refer to Table 19-5 on page 854. GPIO Analog Mode Select (GPIOAMSEL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x528 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset GPIOAMSEL RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 440 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 7:0 GPIOAMSEL R/W 0x00 GPIO Analog Mode Select Value Description 1 The analog function of the pin is enabled, the isolation is disabled, and the pin is capable of analog functions. 0 The analog function of the pin is disabled, the isolation is enabled, and the pin is capable of digital functions as specified by the other GPIO configuration registers. Note: This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. The reset state of this register is 0 for all signals. July 24, 2011 441 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the GPIOAFSEL register are cleared on reset, therefore most GPIO pins are configured as GPIOs by default. When a bit is set in the GPIOAFSEL register, the corresponding GPIO signal is controlled by an associated peripheral. The GPIOPCTL register selects one out of a set of peripheral functions for each GPIO, providing additional flexibility in signal definition. For information on the defined encodings for the bit fields in this register, refer to Table 19-5 on page 854. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in the table below. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 9-12. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 GPIOPCTL 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 GPIO Port Control (GPIOPCTL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x52C Type R/W, reset 31 30 29 28 27 26 PMC7 Type Reset R/W - R/W - 15 14 R/W - R/W - R/W - R/W - 13 12 11 10 PMC3 Type Reset R/W - R/W - 25 24 23 22 PMC6 R/W - R/W - R/W - R/W - 9 8 7 6 PMC2 R/W - R/W - R/W - R/W - 21 20 19 18 PMC5 R/W - R/W - R/W - R/W - 5 4 3 2 PMC1 R/W - Bit/Field Name Type Reset 31:28 PMC7 R/W - R/W - R/W - R/W - 17 16 R/W - R/W - 1 0 R/W - R/W - PMC4 PMC0 R/W - R/W - R/W - R/W - Description Port Mux Control 7 This field controls the configuration for GPIO pin 7. 442 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 27:24 PMC6 R/W - Description Port Mux Control 6 This field controls the configuration for GPIO pin 6. 23:20 PMC5 R/W - Port Mux Control 5 This field controls the configuration for GPIO pin 5. 19:16 PMC4 R/W - Port Mux Control 4 This field controls the configuration for GPIO pin 4. 15:12 PMC3 R/W - Port Mux Control 3 This field controls the configuration for GPIO pin 3. 11:8 PMC2 R/W - Port Mux Control 2 This field controls the configuration for GPIO pin 2. 7:4 PMC1 R/W - Port Mux Control 1 This field controls the configuration for GPIO pin 1. 3:0 PMC0 R/W - Port Mux Control 0 This field controls the configuration for GPIO pin 0. July 24, 2011 443 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 23: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID4 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [7:0] 444 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 24: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID5 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [15:8] July 24, 2011 445 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 25: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID6 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [23:16] 446 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 26: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID7 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [31:24] July 24, 2011 447 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 27: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x61 RO 0 RO 0 RO 1 RO 1 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 448 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 28: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 24, 2011 449 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 29: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID2 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x18 RO 0 RO 0 RO 0 RO 0 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 450 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 30: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x01 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 24, 2011 451 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 31: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 452 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 32: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID1 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 RO 0 RO 1 RO 1 RO 1 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. July 24, 2011 453 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 33: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID2 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID2 RO 0x05 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 454 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 34: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID3 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID3 RO 0xB1 RO 0 RO 1 RO 0 RO 1 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. July 24, 2011 455 Texas Instruments-Production Data External Peripheral Interface (EPI) 10 External Peripheral Interface (EPI) The External Peripheral Interface is a high-speed parallel bus for external peripherals or memory. It has several modes of operation to interface gluelessly to many types of external devices. The External Peripheral Interface is similar to a standard microprocessor address/data bus, except that it must typically be connected to just one type of external device. Enhanced capabilities include µDMA support, clocking control and support for external FIFO buffers. The EPI has the following features: ■ 8/16/32-bit dedicated parallel bus for external peripherals and memory ■ Memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from SDRAM, SRAM and Flash memory ■ Blocking and non-blocking reads ■ Separates processor from timing details through use of an internal write FIFO ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for read and write – Read channel request asserted by programmable levels on the internal non-blocking read FIFO (NBRFIFO) – Write channel request asserted by empty on the internal write FIFO (WFIFO) The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory (SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same way as a communication mechanism and is speed-controlled using clocking. ■ Synchronous Dynamic Random Access Memory (SDRAM) mode – Supports x16 (single data rate) SDRAM at up to 50 MHz – Supports low-cost SDRAMs up to 64 MB (512 megabits) – Includes automatic refresh and access to all banks/rows – Includes a Sleep/Standby mode to keep contents active with minimal power draw – Multiplexed address/data interface for reduced pin count ■ Host-Bus mode – Traditional x8 and x16 MCU bus interface capabilities – Similar device compatibility options as PIC, ATmega, 8051, and others – Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with no byte selects) 456 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller – Support of both muxed and de-muxed address and data – Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant, with support for external FIFO (XFIFO) EMPTY and FULL signals – Speed controlled, with read and write data wait-state counters – Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn – Manual chip-enable (or use extra address pins) ■ General-Purpose mode – Wide parallel interfaces for fast communications with CPLDs and FPGAs – Data widths up to 32 bits – Data rates up to 150 MB/second – Optional "address" sizes from 4 bits to 20 bits – Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input ■ General parallel GPIO – 1 to 32 bits, FIFOed with speed control – Useful for custom peripherals or for digital data acquisition and actuator controls 10.1 EPI Block Diagram ® Figure 10-1 on page 458 provides a block diagram of a Stellaris EPI module. July 24, 2011 457 Texas Instruments-Production Data External Peripheral Interface (EPI) Figure 10-1. EPI Block Diagram General Parallel GPIO NBRFIFO 8 x 32 bits WFIFO SDRAM 4 x 32 bits AHB Bus Interface With DMA AHB EPI 31:0 Host Bus Baud Rate Control (Clock) Wide Parallel Interface 10.2 Signal Description The following table lists the external signals of the EPI controller and describes the function of each. The EPI controller signals are alternate functions for GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the EPI signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 424) should be set to choose the EPI controller function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 442) to assign the EPI signals to the specified GPIO port pins. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 400. Table 10-1. Signals for External Peripheral Interface (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment Pin Type a Buffer Type Description EPI0S0 83 PH3 (8) I/O TTL EPI module 0 signal 0. EPI0S1 84 PH2 (8) I/O TTL EPI module 0 signal 1. EPI0S2 25 PC4 (8) I/O TTL EPI module 0 signal 2. EPI0S3 24 PC5 (8) I/O TTL EPI module 0 signal 3. EPI0S4 23 PC6 (8) I/O TTL EPI module 0 signal 4. EPI0S5 22 PC7 (8) I/O TTL EPI module 0 signal 5. EPI0S6 86 PH0 (8) I/O TTL EPI module 0 signal 6. EPI0S7 85 PH1 (8) I/O TTL EPI module 0 signal 7. EPI0S8 74 PE0 (8) I/O TTL EPI module 0 signal 8. EPI0S9 75 PE1 (8) I/O TTL EPI module 0 signal 9. EPI0S10 76 PH4 (8) I/O TTL EPI module 0 signal 10. 458 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 10-1. Signals for External Peripheral Interface (100LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description EPI0S11 63 PH5 (8) I/O TTL EPI module 0 signal 11. EPI0S12 42 58 PF7 (8) PF4 (8) I/O TTL EPI module 0 signal 12. EPI0S13 19 PG0 (8) I/O TTL EPI module 0 signal 13. EPI0S14 18 PG1 (8) I/O TTL EPI module 0 signal 14. EPI0S15 41 46 PG4 (8) PF5 (8) I/O TTL EPI module 0 signal 15. EPI0S16 14 PJ0 (8) I/O TTL EPI module 0 signal 16. EPI0S17 87 PJ1 (8) I/O TTL EPI module 0 signal 17. EPI0S18 39 PJ2 (8) I/O TTL EPI module 0 signal 18. EPI0S19 97 PD4 (10) I/O TTL EPI module 0 signal 19. EPI0S20 12 PD2 (8) I/O TTL EPI module 0 signal 20. EPI0S21 13 PD3 (8) I/O TTL EPI module 0 signal 21. EPI0S22 91 PB5 (8) I/O TTL EPI module 0 signal 22. EPI0S23 92 PB4 (8) I/O TTL EPI module 0 signal 23. EPI0S24 95 PE2 (8) I/O TTL EPI module 0 signal 24. EPI0S25 96 PE3 (8) I/O TTL EPI module 0 signal 25. EPI0S26 62 PH6 (8) I/O TTL EPI module 0 signal 26. EPI0S27 15 PH7 (8) I/O TTL EPI module 0 signal 27. EPI0S28 98 PD5 (10) I/O TTL EPI module 0 signal 28. EPI0S29 99 PD6 (10) I/O TTL EPI module 0 signal 29. EPI0S30 100 PD7 (10) I/O TTL EPI module 0 signal 30. EPI0S31 36 PG7 (9) I/O TTL EPI module 0 signal 31. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 10-2. Signals for External Peripheral Interface (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment EPI0S0 D10 PH3 (8) a Pin Type Buffer Type I/O TTL Description EPI module 0 signal 0. EPI0S1 D11 PH2 (8) I/O TTL EPI module 0 signal 1. EPI0S2 L1 PC4 (8) I/O TTL EPI module 0 signal 2. EPI0S3 M1 PC5 (8) I/O TTL EPI module 0 signal 3. EPI0S4 M2 PC6 (8) I/O TTL EPI module 0 signal 4. EPI0S5 L2 PC7 (8) I/O TTL EPI module 0 signal 5. EPI0S6 C9 PH0 (8) I/O TTL EPI module 0 signal 6. EPI0S7 C8 PH1 (8) I/O TTL EPI module 0 signal 7. EPI0S8 B11 PE0 (8) I/O TTL EPI module 0 signal 8. EPI0S9 A12 PE1 (8) I/O TTL EPI module 0 signal 9. EPI0S10 B10 PH4 (8) I/O TTL EPI module 0 signal 10. EPI0S11 F10 PH5 (8) I/O TTL EPI module 0 signal 11. EPI0S12 K4 L9 PF7 (8) PF4 (8) I/O TTL EPI module 0 signal 12. July 24, 2011 459 Texas Instruments-Production Data External Peripheral Interface (EPI) Table 10-2. Signals for External Peripheral Interface (108BGA) (continued) Pin Name EPI0S13 Pin Number Pin Mux / Pin Assignment K1 PG0 (8) a Pin Type Buffer Type I/O TTL Description EPI module 0 signal 13. EPI0S14 K2 PG1 (8) I/O TTL EPI module 0 signal 14. EPI0S15 K3 L8 PG4 (8) PF5 (8) I/O TTL EPI module 0 signal 15. EPI0S16 F3 PJ0 (8) I/O TTL EPI module 0 signal 16. EPI0S17 B6 PJ1 (8) I/O TTL EPI module 0 signal 17. EPI0S18 K6 PJ2 (8) I/O TTL EPI module 0 signal 18. EPI0S19 B5 PD4 (10) I/O TTL EPI module 0 signal 19. EPI0S20 H2 PD2 (8) I/O TTL EPI module 0 signal 20. EPI0S21 H1 PD3 (8) I/O TTL EPI module 0 signal 21. EPI0S22 B7 PB5 (8) I/O TTL EPI module 0 signal 22. EPI0S23 A6 PB4 (8) I/O TTL EPI module 0 signal 23. EPI0S24 A4 PE2 (8) I/O TTL EPI module 0 signal 24. EPI0S25 B4 PE3 (8) I/O TTL EPI module 0 signal 25. EPI0S26 G3 PH6 (8) I/O TTL EPI module 0 signal 26. EPI0S27 H3 PH7 (8) I/O TTL EPI module 0 signal 27. EPI0S28 C6 PD5 (10) I/O TTL EPI module 0 signal 28. EPI0S29 A3 PD6 (10) I/O TTL EPI module 0 signal 29. EPI0S30 A2 PD7 (10) I/O TTL EPI module 0 signal 30. EPI0S31 C10 PG7 (9) I/O TTL EPI module 0 signal 31. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 10.3 Functional Description The EPI controller provides a glueless, programmable interface to a variety of common external peripherals such as SDRAM, Host Bus x8 and x16 devices, RAM, NOR Flash memory, CPLDs and FPGAs. In addition, the EPI controller provides custom GPIO that can use a FIFO with speed control by using either the internal write FIFO (WFIFO) or the non-blocking read FIFO (NBRFIFO). The WFIFO can hold 4 words of data that are written to the external interface at the rate controlled by the EPI Main Baud Rate (EPIBAUD) register. The NBRFIFO can hold 8 words of data and samples at the rate controlled by the EPIBAUD register. The EPI controller provides predictable operation and thus has an advantage over regular GPIO which has more variable timing due to on-chip bus arbitration and delays across bus bridges. Blocking reads stall the CPU until the transaction completes. Non-blocking reads are performed in the background and allow the processor to continue operation. In addition, write data can also be stored in the WFIFO to allow multiple writes with no stalls. Main read and write operations can be performed in subsets of the range 0x6000.0000 to 0xDFFF.FFFF. A read from an address mapped location uses the offset and size to control the address and size of the external operation. When performing a multi-value load, the read is done as a burst (when available) to maximize performance. A write to an address mapped location uses the offset and size to control the address and size of the external operation. When performing a multi-value store, the write is done as a burst (when available) to maximize performance. 460 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller NAND Flash memory (x8) can be read natively. Automatic programming support is not provided; programming must be done by the user following the manufacturer's protocol. Automatic page ECC is also not supported, but can be performed in software. 10.3.1 Non-Blocking Reads The EPI Controller supports a special kind of read called a non-blocking read, also referred to as a posted read. Where a normal read stalls the processor or μDMA until the data is returned, a non-blocking read is performed in the background. A non-blocking read is configured by writing the start address into a EPIRADDRn register, the size per transaction into a EPIRSIZEn register, and then the count of operations into a EPIRPSTDn register. After each read is completed, the result is written into the NBRFIFO and the EPIRADDRn register is incremented by the size (1, 2, or 4). If the NBRFIFO is filled, then the reads pause until space is made available. The NBRFIFO can be configured to interrupt the processor or trigger the μDMA based on fullness using the EPIFIFOLVL register. By using the trigger/interrupt method, the μDMA (or processor) can keep space available in the NBRFIFO and allow the reads to continue unimpeded. When performing non-blocking reads, the SDRAM controller issues two additional read transactions after the burst request is terminated. The data for these additional transfers is discarded. This situation is transparent to the user other than the additional EPI bus activity and can safely be ignored. Two non-blocking read register sets are available to allow sequencing and ping-pong use. When one completes, the other then activates. So, for example, if 20 words are to be read from 0x100 and 10 words from 0x200, the EPIRPSTD0 register can be set up with the read from 0x100 (with a count of 20), and the EPIRPSTD1 register can be set up with the read from 0x200 (with a count of 10). When EPIRPSTD0 finishes (count goes to 0), the EPIRPSTD1 register then starts its operation. The NBRFIFO has then passed 30 values. When used with the μDMA, it may transfer 30 values (simple sequence), or the primary/alternate model may be used to handle the first 20 in one way and the second 10 in another. It is also possible to reload the EPIRPSTD0 register when it is finished (and the EPIRPSTD1 register is active); thereby, keeping the interface constantly busy. To cancel a non-blocking read, the EPIRPSTDn register is cleared. Care must be taken, however if the register set was active to drain away any values read into the NBRFIFO and ensure that any read in progress is allowed to complete. To ensure that the cancel is complete, the following algorithm is used (using the EPIRPSTD0 register for example): EPIRPSTD0 = 0; while ((EPISTAT & 0x11) == 0x10) ; // we are active and busy // if here, then other one is active or interface no longer busy cnt = (EPIRADDR0 – original_address) / EPIRSIZE0; // count of values read cnt -= values_read_so_far; // cnt is now number left in FIFO while (cnt--) value = EPIREADFIFO; // drain July 24, 2011 461 Texas Instruments-Production Data External Peripheral Interface (EPI) The above algorithm can be optimized in code; however, the important point is to wait for the cancel to complete because the external interface could have been in the process of reading a value when the cancel came in, and it must be allowed to complete. 10.3.2 DMA Operation The µDMA can be used to achieve maximum transfer rates on the EPI through the NBRFIFO and the WFIFO. The µDMA has one channel for write and one for read. The write channel copies values to the WFIFO when the WFIFO is at the level specified by the EPI FIFO Level Selects (EPIFIFOLVL) register. The non-blocking read channel copies values from the NBRFIFO when the NBRFIFO is at the level specified by the EPIFIFOLVL register. For non-blocking reads, the start address, the size per transaction, and the count of elements must be programmed in the µDMA. Note that both non-blocking read register sets can be used, and they fill the NBRFIFO such that one runs to completion, then the next one starts (they do not interleave). Using the NBRFIFO provides the best possible transfer rate. For blocking reads, the µDMA software channel (or another unused channel) is used for memory-to-memory transfers (or memory to peripheral, where some other peripheral is used). In this situation, the µDMA stalls until the read is complete and is not able to service another channel until the read is done. As a result, the arbitration size should normally be programmed to one access at a time. The µDMA controller can also transfer from and to the NBRFIFO and the WFIFO using the µDMA software channel in memory mode, however, the µDMA is stalled once the NBRFIFO is empty or the WFIFO is full. Note that when the µDMA controller is stalled, the core continues operation. See “Micro Direct Memory Access (μDMA)” on page 340 for more information on configuring the µDMA. The size of the FIFOs must be taken into consideration when configuring the µDMA to transfer data to and from the EPI. The arbitration size should be 4 or less when writing to EPI address space and 8 or less when reading from EPI address space. 10.4 Initialization and Configuration To enable and initialize the EPI controller, the following steps are necessary: 1. Enable the EPI module using the RCGC1 register. See page 246. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register. See page 255. To find out which GPIO port to enable, refer to “Signal Description” on page 458. 3. Set the GPIO AFSEL bits for the appropriate pins. See page 424. To determine which GPIOs to configure, see Table 19-4 on page 848. 4. Configure the GPIO current level and/or slew rate as specified for the mode selected. See page 426 and page 434. 5. Configure the PMCn fields in the GPIOPCTL register to assign the EPI signals to the appropriate pins. See page 442 and Table 19-5 on page 854. 6. Select the mode for the EPI block to SDRAM, HB8, HB16, or general parallel use, using the MODE field in the EPI Configuration (EPICFG) register. Set the mode-specific details (if needed) using the appropriate mode configuration EPI xxx Configuration (EPIxxxCFG) and EPI xxx Configuration 2 (EPIxxxCFG2) registers. Set the EPI Main Baud Rate (EPIBAUD) register if the baud rate must be slower than the system clock rate. 462 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 7. Configure the address mapping using the EPI Address Map (EPIADDRMAP) register. The selected start address and range is dependent on the type of external device and maximum address (as appropriate). For example, for a 512-megabit SDRAM, program the ERADR field to 0x1 for address 0x6000.0000 or 0x2 for address 0x8000.0000; and program the ERSZ field to 0x3 for 256 MB. If using General-Purpose mode and no address at all, program the EPADR field to 0x1 for address 0xA000.0000 or 0x2 for address 0xC000.0000; and program the EPSZ field to 0x0 for 256 bytes. 8. To read or write directly, use the mapped address area (configured with the EPIADDRMAP register). Up to 4 or 5 writes can be performed at once without blocking. Each read is blocked until the value is retrieved. 9. To perform a non-blocking read, see “Non-Blocking Reads” on page 461. The following sub-sections describe the initialization and configuration for each of the modes of operation. Care must be taken to initialize everything properly to ensure correct operation. Control of the GPIO states is also important, as changes may cause the external device to interpret pin states as actions or commands (see “Register Descriptions” on page 413). Normally, a pull-up or pull-down is needed on the board to at least control the chip-select or chip-enable as the Stellaris GPIOs come out of reset in tri-state. 10.4.1 SDRAM Mode When activating the SDRAM mode, it is important to consider a few points: 1. Generally, it takes over 100 μs from when the mode is activated to when the first operation is allowed. The SDRAM controller begins the SDRAM initialization sequence as soon as the mode is selected and enabled via the EPICFG register. It is important that the GPIOs are properly configured before the SDRAM mode is enabled, as the EPI controller is relying on the GPIO block's ability to drive the pins immediately. As part of the initialization sequence, the LOAD MODE REGISTER command is automatically sent to the SDRAM with a value of 0x27, which sets a CAS latency of 2 and a full page burst length. 2. The INITSEQ bit in the EPI Status (EPISTAT) register can be checked to determine when the initialization sequence is complete. 3. When using a frequency range and/or refresh value other than the default value, it is important to configure the FREQ and RFSH fields in the EPI SDRAM Configuration (EPISDRAMCFG) register shortly after activating the mode. After the 100-μs startup time, the EPI block must be configured properly to keep the SDRAM contents stable. 4. The SLEEP bit in the EPISDRAMCFG register may be configured to put the SDRAM into a low-power self-refreshing state. It is important to note that the SDRAM mode must not be disabled once enabled, or else the SDRAM is no longer clocked and the contents are lost. The SIZE field of the EPISDRAMCFG register must be configured correctly based on the amount of SDRAM in the system. The FREQ field must be configured according to the value that represents the range being used. Based on the range selected, the number of external clocks used between certain operations (for example, PRECHARGE or ACTIVATE) is determined. If a higher frequency is given than is used, then the only downside is that the peripheral is slower (uses more cycles for these delays). If a lower frequency is given, incorrect operation occurs. See “External Peripheral Interface (EPI)” on page 897 for timing details for the SDRAM mode. July 24, 2011 463 Texas Instruments-Production Data External Peripheral Interface (EPI) 10.4.1.1 External Signal Connections Table 10-3 on page 464 defines how EPI module signals should be connected to SDRAMs. The table applies when using a x16 SDRAM up to 512 megabits. Note that the EPI signals must use 8-mA drive when interfacing to SDRAM, see page 428. Any unused EPI controller signals can be used as GPIOs or another alternate function. Table 10-3. EPI SDRAM Signal Connections a EPI Signal SDRAM Signal EPI0S0 A0 D0 EPI0S1 A1 D1 EPI0S2 A2 D2 EPI0S3 A3 D3 EPI0S4 A4 D4 EPI0S5 A5 D5 EPI0S6 A6 D6 EPI0S7 A7 D7 EPI0S8 A8 D8 EPI0S9 A9 D9 EPI0S10 A10 D10 EPI0S11 A11 EPI0S12 A12 b D12 D11 EPI0S13 BA0 D13 EPI0S14 BA1 D14 EPI0S15 D15 EPI0S16 DQML EPI0S17 DQMH EPI0S18 CASn EPI0S19 RASn EPI0S20-EPI0S27 not used EPI0S28 WEn EPI0S29 CSn EPI0S30 CKE EPI0S31 CLK a. If 2 signals are listed, connect the EPI signal to both pins. b. Only for 256/512 megabit SDRAMs 10.4.1.2 Refresh Configuration The refresh count is based on the external clock speed and the number of rows per bank as well as the refresh period. The RFSH field represents how many external clock cycles remain before an AUTO-REFRESH is required. The normal formula is: RFSH = (tRefresh_us / number_rows) / ext_clock_period A refresh period is normally 64 ms, or 64000 μs. The number of rows is normally 4096 or 8192. The ext_clock_period is a value expressed in μsec and is derived by dividing 1000 by the clock speed expressed in MHz. So, 50 MHz is 1000/50=20 ns, or 0.02 μs. A typical SDRAM is 4096 rows per bank if the system clock is running at 50 MHz with an EPIBAUD register value of 0: 464 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller RFSH = (64000/4096) / 0.02 = 15.625 μs / 0.02 μs = 781.25 The default value in the RFSH field is 750 decimal or 0x2EE to allow for a margin of safety and providing 15 μs per refresh. It is important to note that this number should always be smaller or equal to what is required by the above equation. For example, if running the external clock at 25 MHz (40 ns per clock period), 390 is the highest number that may be used. Note that the external clock may be 25 MHz when the system clock is 25 MHz or when the system clock is 50 MHz and configuring the COUNT0 field in the EPIBAUD register to 1 (divide by 2). If a number larger than allowed is used, the SDRAM is not refreshed often enough, and data is lost. 10.4.1.3 Bus Interface Speed The EPI Controller SDRAM interface can operate up to 50 MHz. The COUNT0 field in the EPIBAUD register configures the speed of the EPI clock. For system clock (SysClk) speeds up to 50 MHz, the COUNT0 field can be 0x0000, and the SDRAM interface can run at the same speed as SysClk. However, if SysClk is running at higher speeds, the bus interface can run only as fast as half speed, and the COUNT0 field must be configured to at least 0x0001. 10.4.1.4 Non-Blocking Read Cycle Figure 10-2 on page 465 shows a non-blocking read cycle of n halfwords; n can be any number greater than or equal to 1. The cycle begins with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed CAS latency of 2, the Read command with the column address on the EPI0S[15:0] signals follows after 2 clock cycles. Following one more NOP cycle, data is read in on the EPI0S[15:0] signals on every rising clock edge. The Burst Terminate command is issued during the cycle when the next-to-last halfword is read in. The DQMH and DQML signals are deasserted after the last halfword of data is received; the CSn signal deasserts on the following clock cycle, signaling the end of the read cycle. At least one clock period of inactivity separates any two SDRAM cycles. Figure 10-2. SDRAM Non-Blocking Read Cycle CLK (EPI0S31) CKE (EPI0S30) CSn (EPI0S29) WEn (EPI0S28) RASn (EPI0S19) CASn (EPI0S18) DQMH, DQML (EPI0S [17:16]) AD [15:0] (EPI0S [15:0]) Row Activate Column NOP NOP Read Data 0 Data 1 ... Data n Burst Term NOP AD [15:0] driven in AD [15:0] driven out 10.4.1.5 AD [15:0] driven out Normal Read Cycle Figure 10-3 on page 466 shows a normal read cycle of n halfwords; n can be 1 or 2. The cycle begins with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed CAS latency of 2, the Read command with the column address on the EPI0S[15:0] signals follows July 24, 2011 465 Texas Instruments-Production Data External Peripheral Interface (EPI) after 2 clock cycles. Following one more NOP cycle, data is read in on the EPI0S[15:0] signals on every rising clock edge. The DQMH, DQML, and CSn signals are deasserted after the last halfword of data is received, signaling the end of the cycle. At least one clock period of inactivity separates any two SDRAM cycles. Figure 10-3. SDRAM Normal Read Cycle CLK (EPI0S31) CKE (EPI0S30) CSn (EPI0S29) WEn (EPI0S28) RASn (EPI0S19) CASn (EPI0S18) DQMH, DQML (EPI0S [17:16]) AD [15:0] (EPI0S [15:0]) Row Activate Column NOP NOP Read Data 0 Data 1 NOP AD [15:0] driven in AD [15:0] driven out 10.4.1.6 AD [15:0] driven out Write Cycle Figure 10-4 on page 467 shows a write cycle of n halfwords; n can be any number greater than or equal to 1. The cycle begins with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed CAS latency of 2, the Write command with the column address on the EPI0S[15:0] signals follows after 2 clock cycles. When writing to SDRAMs, the Write command is presented with the first halfword of data. Because the address lines and the data lines are multiplexed, the column address is modified to be (programmed address -1). During the Write command, the DQMH and DQML signals are high, so no data is written to the SDRAM. On the next clock, the DQMH and DQML signals are asserted, and the data associated with the programmed address is written. The Burst Terminate command occurs during the clock cycle following the write of the last halfword of data. The WEn, DQMH, DQML, and CSn signals are deasserted after the last halfword of data is received, signaling the end of the access. At least one clock period of inactivity separates any two SDRAM cycles. 466 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 10-4. SDRAM Write Cycle CLK (EPI0S31) CKE (EPI0S30) CSn (EPI0S29) WEn (EPI0S28) RASn (EPI0S19) CASn (EPI0S18) DQMH, DQML (EPI0S [17:16]) AD [15:0] (EPI0S [15:0]) Row Activate Column-1 NOP NOP Data 0 Data 1 ... Data n Burst Term Write AD [15:0] driven out AD [15:0] driven out 10.4.2 Host Bus Mode Host Bus supports the traditional 8-bit and 16-bit interfaces popularized by the 8051devices and SRAM devices. This interface is asynchronous and uses strobe pins to control activity. 10.4.2.1 Control Pins The main three strobes are ALE (Address latch enable), WRn (write), and RDn (sometimes called OEn, used for read). Note that the timings are designed for older logic and so are hold-time vs. setup-time specific. To ensure proper operation on this bus, the EPI block uses two system clocks per transition to allow significant skewing of control vs. data signals. So, for example, ALE rises one EPI clock before ADDR/DATA is asserted. Likewise, ALE falls (latch point) one EPI clock before DATA changes or tri-states. The same approach is used for the WRn and RDn/OEn strobes. The polarity of the read and write strobes can be active High or active Low by clearing or setting the RDHIGH and WRHIGH bits in the EPI Host-Bus n Configuration 2 (EPIHBnCFG2) register. The ALE can be changed to an active-low chip select signal, CSn, through the EPIHBnCFG2 register. The ALE is best used for Host-Bus muxed mode in which EPI address and data pins are shared. All Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an external latch to capture the address then hold it until the data phase. CSn is best used for Host-Bus unmuxed mode in which EPI address and data pins are separate. The CSn indicates when the address and data phases of a read or write access is occurring. Both the ALE and the CSn modes can be enhanced to access two external devices using settings in the EPIHBnCFG2 register. Wait states can be added to the data phase of the access using the WRWS and RDWS bits in the EPIHBnCFG2 register. For FIFO mode, the ALE is not used, and two input holds are optionally supported to gate input and output to what the XFIFO can handle. Host-Bus 8 and Host-Bus 16 modes are very configurable. The user has the ability to connect 1 or 2 external devices to the EPI signals as well as control whether byte select signals are provided in HB16 mode. These capabilities depend on the configuration of the MODE field in the EPIHBnCFG register, the CSCFG field in the EPIHBnCFG2 register, and the BSEL bit in the EPIHB16CFG register. July 24, 2011 467 Texas Instruments-Production Data External Peripheral Interface (EPI) If one of the Dual-Chip-Select modes is selected (CSCFG=0x2 or 0x3 in the EPIHBnCFG2 register), both chip selects can share the peripheral or the memory space, or one chip select can use the peripheral space and the other can use the memory space. In the EPIADDRMAP register, if the EPADR field is not 0x0 and the ERADR field is 0x0, then the address specified by EPADR is used for both chip selects, with CS0n being asserted when the MSB of the address range is 0 and CS1n being asserted when the MSB of the address range is 1. If the ERADR field is not 0x0 and the EPADR field is 0x0, then the address specified by ERADR is used for both chip selects, with the MSB performing the same delineation. If both the EPADR and the ERADR are not 0x0, then CS0n is asserted for the address range defined by EPADR and CS1n is asserted for the address range defined by ERADR. If the CSBAUD bit in the EPIHBnCFG2 register is set, the 2 chip selects can use different clock frequencies, wait states and strobe polarity. If the CSBAUD bit is clear, both chip selects use the clock frequency, wait states, and strobe polarity defined for CS0n. When BSEL=1 in the EPIHB16CFG register, byte select signals are provided, so byte-sized data can be read and written at any address, however these signals reduce the available address width by 2 pins. The byte select signals are active Low. BSEL0n corresponds to the LSB of the halfword, and BSEL1n corresponds to the MSB of the halfword. When BSEL=0, byte reads and writes at odd addresses only act on the even byte, and byte writes at even addresses write invalid values into the odd byte. As a result, accesses should be made as half-words (16-bits) or words (32-bits). In C/C++, programmers should use only short int and long int for accesses. Also, because data accesses in HB16 mode with no byte selects are on 2-byte boundaries, the available address space is doubled. For example, 28 bits of address accesses 512 MB in this mode. Table 10-4 on page 468 shows the capabilities of the HB8 and HB16 modes as well as the available address bits with the possible combinations of these bits. Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not required and should be configured as a GPIO to reduce EMI in the system. Table 10-4. Capabilities of Host Bus 8 and Host Bus 16 Modes Host Bus Type MODE CSCFG Max # of External Devices BSEL Byte Access Available Address HB8 0x0 0x0, 0x1 1 N/A Always 28 bits HB8 0x0 0x2 2 N/A Always 27 bits HB8 0x0 0x3 2 N/A Always 26 bits HB8 0x1 0x0, 0x1 1 N/A Always 20 bits HB8 0x1 0x2 2 N/A Always 19 bits HB8 0x1 0x3 2 N/A Always 18 bits HB8 0x3 0x1 1 N/A Always none HB8 0x3 0x3 2 N/A Always none HB16 0x0 0x0, 0x1 1 0 No 28 bits HB16 0x0 0x0, 0x1 1 1 Yes 26 bits HB16 0x0 0x2 2 0 No 27 bits HB16 0x0 0x2 2 1 Yes 25 bits HB16 0x0 0x3 2 0 No 26 bits HB16 0x0 0x3 2 1 Yes 24 bits HB16 0x1 0x0, 0x1 1 0 No 12 bits HB16 0x1 0x0, 0x1 1 1 Yes 10 bits HB16 0x1 0x2 2 0 No 11 bits 468 a a a a a July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 10-4. Capabilities of Host Bus 8 and Host Bus 16 Modes (continued) Host Bus Type MODE CSCFG Max # of External Devices BSEL Byte Access Available Address HB16 0x1 0x2 2 1 Yes 9 bits HB16 0x1 0x3 2 0 No 10 bits HB16 0x1 0x3 2 1 Yes 8 bits HB16 0x3 0x1 1 0 No none HB16 0x3 0x1 1 1 Yes none HB16 0x3 0x3 2 0 No none HB16 0x3 0x3 2 1 Yes none a a. If byte selects are not used, data accesses are on 2-byte boundaries. As a result, the available address space is doubled. Table 10-5 on page 469 shows how the EPI[31:0] signals function while in Host-Bus 8 mode. Notice that the signal configuration changes based on the address/data mode selected by the MODE field in the EPIHB8CFG2 register and on the chip select configuration selected by the CSCFG field in the same register. Any unused EPI controller signals can be used as GPIOs or another alternate function. Table 10-5. EPI Host-Bus 8 Signal Connections EPI Signal CSCFG HB8 Signal (MODE =ADMUX) HB8 Signal (MODE =ADNOMUX (Cont. Read)) HB8 Signal (MODE =XFIFO) EPI0S0 X a AD0 D0 D0 EPI0S1 X AD1 D1 D1 EPI0S2 X AD2 D2 D2 EPI0S3 X AD3 D3 D3 EPI0S4 X AD4 D4 D4 EPI0S5 X AD5 D5 D5 EPI0S6 X AD6 D6 D6 EPI0S7 X AD7 D7 D7 EPI0S8 X A8 A0 - EPI0S9 X A9 A1 - EPI0S10 X A10 A2 - EPI0S11 X A11 A3 - EPI0S12 X A12 A4 - EPI0S13 X A13 A5 - EPI0S14 X A14 A6 - EPI0S15 X A15 A7 - EPI0S16 X A16 A8 - EPI0S17 X A17 A9 - EPI0S18 X A18 A10 - EPI0S19 X A19 A11 - EPI0S20 X A20 A12 - EPI0S21 X A21 A13 - EPI0S22 X A22 A14 - July 24, 2011 469 Texas Instruments-Production Data External Peripheral Interface (EPI) Table 10-5. EPI Host-Bus 8 Signal Connections (continued) EPI Signal CSCFG HB8 Signal (MODE =ADMUX) HB8 Signal (MODE =ADNOMUX (Cont. Read)) HB8 Signal (MODE =XFIFO) EPI0S23 X A23 A15 - EPI0S24 X A24 A16 - b A17 0x0 - 0x1 EPI0S25 A25 0x2 CS1n 0x3 - 0x0 0x1 EPI0S26 A26 A18 CS0n CS0n A27 A19 CS1n CS1n FEMPTY 0x2 0x3 0x0 0x1 EPI0S27 FFULL 0x2 0x3 EPI0S28 X RDn/OEn RDn/OEn RDn EPI0S29 X WRn WRn WRn EPI0S30 EPI0S31 0x0 ALE ALE - 0x1 CSn CSn CSn 0x2 CS0n CS0n CS0n 0x3 ALE ALE - c X c Clock Clock c Clock a. "X" indicates the state of this field is a don't care. b. When an entry straddles several row, the signal configuration is the same for all rows. c. The clock signal is not required for this mode and has unspecified timing relationships to other signals. Table 10-6 on page 470 shows how the EPI[31:0] signals function while in Host-Bus 16 mode. Notice that the signal configuration changes based on the address/data mode selected by the MODE field in the EPIHB16CFG2 register, on the chip select configuration selected by the CSCFG field in the same register, and on whether byte selects are used as configured by the BSEL bit in the EPIHB16CFG register. Any unused EPI controller signals can be used as GPIOs or another alternate function. Table 10-6. EPI Host-Bus 16 Signal Connections EPI Signal CSCFG BSEL HB16 Signal (MODE =ADMUX) HB16 Signal (MODE =ADNOMUX (Cont. Read)) HB16 Signal (MODE =XFIFO) EPI0S0 X a X AD0 b D0 D0 EPI0S1 X X AD1 D1 D1 EPI0S2 EPI0S3 X X AD2 D2 D2 X X AD3 D3 D3 EPI0S4 X X AD4 D4 D4 EPI0S5 X X AD5 D5 D5 470 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 10-6. EPI Host-Bus 16 Signal Connections (continued) EPI Signal CSCFG BSEL HB16 Signal (MODE =ADMUX) HB16 Signal (MODE =ADNOMUX (Cont. Read)) HB16 Signal (MODE =XFIFO) EPI0S6 X X AD6 D6 D6 EPI0S7 X X AD7 D7 D7 EPI0S8 X X AD8 D8 D8 EPI0S9 X X AD9 D9 D9 EPI0S10 X X AD10 D10 D10 EPI0S11 X X AD11 D11 D11 EPI0S12 X X AD12 D12 D12 EPI0S13 X X AD13 D13 D13 EPI0S14 X X AD14 D14 D14 D15 EPI0S15 X X AD15 D15 EPI0S16 X X A16 A0 b - EPI0S17 X X A17 A1 - EPI0S18 X X A18 A2 - EPI0S19 X X A19 A3 - EPI0S20 X X A20 A4 - EPI0S21 X X A21 A5 - EPI0S22 X X A22 A6 - c 0 A23 A7 - A24 A8 1 BSEL0n BSEL0n X A25 A9 0 A25 A9 1 BSEL0n BSEL0n 0 A25 A9 1 BSEL1n BSEL1n 0 A26 A10 1 BSEL0n BSEL0n EPI0S23 X 0x0 0x1 EPI0S24 0x2 0x3 0x0 0x1 EPI0S25 0x2 0x3 0x0 EPI0S26 0x1 0x2 0x3 1 0 1 0 1 0 - 1 0 0 A26 A10 1 BSEL0n BSEL0n 0 A26 A10 1 BSEL1n BSEL1n X CS0n CS0n July 24, 2011 - CS1n -- FEMPTY 471 Texas Instruments-Production Data External Peripheral Interface (EPI) Table 10-6. EPI Host-Bus 16 Signal Connections (continued) EPI Signal CSCFG 0x0 EPI0S27 EPI0S28 EPI0S29 EPI0S30 EPI0S31 0x1 BSEL HB16 Signal (MODE =ADMUX) HB16 Signal (MODE =ADNOMUX (Cont. Read)) 0 A27 A11 1 BSEL1n BSEL1n 0 A27 A11 1 BSEL1n BSEL1n CS1n CS1n HB16 Signal (MODE =XFIFO) FFULL 0x2 X 0x3 X X X RDn/OEn RDn/OEn RDn X X WRn WRn WRn 0x0 X ALE ALE - 0x1 X CSn CSn CSn 0x2 X CS0n CS0n CS0n 0x3 X ALE X X Clock ALE d d Clock d Clock a. "X" indicates the state of this field is a don't care. b. In this mode, half-word accesses are used. A0 is the LSB of the address and is equivalent to the internal Cortex-M3 A1 address. This pin should be connected to A0 of 16-bit memories. c. When an entry straddles several row, the signal configuration is the same for all rows. d. The clock signal is not required for this mode and has unspecified timing relationships to other signals. Figure 10-5 on page 473 shows how to connect the EPI signals to a 16-bit SRAM and a 16-bit Flash memory with muxed address and memory using byte selects and dual chip selects with ALE. This schematic is just an example of how to connect the signals; timing and loading have not been analyzed. In addition, not all bypass capacitors are shown. 472 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 10-5. Example Schematic for Muxed Host-Bus 16 Mode EPI_16_BUS A[0:15] U1 EPI0 EPI1 EPI2 EPI3 EPI4 EPI5 EPI6 EPI7 47 46 44 43 41 40 38 37 EPI8 EPI9 EPI10 EPI11 EPI12 EPI13 EPI14 EPI15 36 35 33 32 30 29 27 26 EPI30 25 2LE 48 1LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 1 1OE 24 2OE +3.3V 7 VCC 18 VCC 31 VCC 42 VCC GND GND GND GND GND GND GND GND GND 2 3 5 6 8 9 11 12 A0 A1 A2 A3 A4 A5 A6 A7 13 14 16 17 19 20 22 23 A8 A9 A10 A11 A12 A13 A14 A15 4 10 15 21 28 34 39 45 GND 74X16373 EPI_16_BUS EPI_16_BUS EPI_16_BUS EPI_16_BUS A[0:15] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 EPI16 EPI17 U2 5 4 3 2 1 44 43 42 27 26 25 24 23 22 21 20 19 18 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 NC +3.3V 11 VCC 33 VCC GND EPI0 EPI1 EPI2 EPI3 EPI4 EPI5 EPI6 EPI7 EPI8 EPI9 EPI10 EPI11 EPI12 EPI13 EPI14 EPI15 EPI16 EPI17 EPI18 28 17 EPI29 6 EPI26 41 EPI28 40 BHE 39 BLE EPI25 EPI24 WE CE OE 12 VSS 34 VSS 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 A[0:15] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 U3 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10 12 13 14 15 47 CY62147 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 NC NC NC NC NC NC NC 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 EPI0 EPI1 EPI2 EPI3 EPI4 EPI5 EPI6 EPI7 EPI8 EPI9 EPI10 EPI11 EPI12 EPI13 EPI14 EPI15 11 WE 28 OE 26 CE EPI29 EPI28 EPI27 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 +3.3V VDD 37 46 VSS 27 VSS SST39VF800A 10.4.2.2 GND Speed of Transactions The COUNT0 field in the EPIBAUD register must be configured to set the main transaction rate based on what the slave device can support (including wiring considerations). The main control DESIGNER REVISION DATE transitions are normally ½ the baud rate (COUNT0 = 1) because the EPI block forces data INSTRUMENTS vs. control TEXAS ??? ?REV? 1/6/2011 R to change on alternating clocks. When using dual chip-selects, each chip selectSTELLARIS can access the bus MICROCONTROLLERS PROJECT using differing baud rates by setting the CSBAUD bit in the EPIHBnCFG2 register.108 InWILD this BASIN case,ROAD, the SUITE 350 ?PROJECT NAME? COUNT0 field controls the CS0n transactions, and the COUNT1 field controls the CS1n transactions. AUSTIN TX, 78746 DESCRIPTION www.ti.com/stellaris Additionally, the Host-Bus?DESC1? mode provides read and write wait states for the data portion to support different classes of device. These wait states stretch the data period (hold the rising edge of data ?DESC2? FILENAME epi16_example.sch July 24, 2011 PART NO. ?PART NUMBER? SHEET 473 Texas Instruments-Production Data 1 OF 1 External Peripheral Interface (EPI) strobe) and may be used in all four sub-modes. The wait states are set using the WRWS and RDWS bits in the EPI Host-Bus n Configuration (EPIHBnCFG) register. 10.4.2.3 Sub-Modes of Host Bus 8/16 The EPI controller supports four variants of the Host-Bus model using 8 or 16 bits of data in all four cases. The four sub-modes are selected using the MODE bits in the EPIHBnCFG register, and are: 1. Address and data are muxed. This scheme is used by many 8051 devices, some Microchip PIC parts, and some ATmega parts. When used for standard SRAMs, a latch must be used between the microcontroller and the SRAM. This sub-mode is provided for compatibility with existing devices that support data transfers without a latch (for example, LCD controllers or CPLDs). In general, the de-muxed sub-mode should normally be used. The ALE configuration should be used in this mode, as all Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an external latch to capture the address then hold until the data phase. The ALE configuration is controlled by configuring the CSCFG field to be 0x0 in the EPIHBnCFG2 register. The ALE can be enhanced to access two external devices with the addition of two separate CSn signals. By configuring the CSCFG field in the to be 0x3 in the EPIHBnCFG2 register, EPI0S30 functions as ALE, EPI0S27 functions as CS1n, and EPI0S26 functions as CS0n. The CSn is best used for Host-Bus unmuxed mode which EPI address and data pins are separate. The CSn indicates when the address and data phases of a read or write access are occurring. 2. Address and data are separate with 8 or 16 bits of data and up to 20 bits of address (1 MB). This scheme is used by more modern 8051 devices, as well as some PIC and ATmega parts. This mode is generally used with real SRAMs, many EEPROMs, and many NOR Flash memory devices. Note that there is no hardware command write support for Flash memory devices; this mode should only be used for Flash memory devices programmed at manufacturing time. If a Flash memory device must be written and does not support a direct programming model, the command mechanism must be performed in software. The CSn configuration should be used in this mode. The CSn signal indicates when the address and data phases of a read or write access is occurring. The CSn configuration is controlled by configuring the CSCFG field to be 0x1 in the EPIHBnCFG2 register. 3. Continuous read mode where address and data are separate. This sub-mode is used for real SRAMs which can be read more quickly by only changing the address (and not using RDn/OEn strobing). In this sub-mode, reads are performed by keeping the read mode selected (output enable is asserted) and then changing the address pins. The data pins are changed by the SRAM after the address pins change. For example, to read data from address 0x100 and then 0x101, the EPI controller asserts the output-enable signal and then configures the address pins to 0x100; the EPI controller then captures what is on the data pins and increments A0 to 1 (so the address is now 0x101); the EPI controller then captures what is on the data pins. Note that this mode consumes higher power because the SRAM must continuously drive the data pins. This mode is not practical in HB16 mode for normal SRAMs because there are generally not enough address bits available. 4. FIFO mode uses 8 or 16 bits of data, removes ALE and address pins and optionally adds external XFIFO FULL/EMPTY flag inputs. This scheme is used by many devices, such as radios, communication devices (including USB2 devices), and some FPGA configurations (FIFO through block RAM). This sub-mode provides the data side of the normal Host-Bus interface, but is paced by the FIFO control signals. It is important to consider that the XFIFO FULL/EMPTY control signals may stall the interface and could have an impact on blocking read latency from the processor or μDMA. 474 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller The WORD bit in the EPIHBnCFG2 register can be set to use memory more efficiently. By default, the EPI controller uses data bits [7:0] for Host-Bus 8 accesses or bits [15:0] for Host-Bus 16 accesses. When the WORD bit is set, the EPI controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:8] (HB8) or [31:16] (HB16). In addition, for the three modes above (1, 2, 4) that the Host-Bus 16 mode supports, byte select signals can be optionally implemented by setting the BSEL bit in the EPIHB16CFG register. See “External Peripheral Interface (EPI)” on page 897 for timing details for the Host-Bus mode. 10.4.2.4 Bus Operation Bus operation is the same in Host-Bus 8 and Host-Bus 16 modes and is asynchronous. Timing diagrams show both ALE and CSn operation, but only one signal or the other is used in all modes except for ALE with dual chip selects mode (CSCFG field is 0x3 in the EPIHBnCFG2 register). Address and data on write cycles are held after the CSn signal is deasserted. The optional HB16 byte select signals have the same timing as the address signals. If wait states are required in the bus access, they can be inserted during the data phase of the access using the WRWS and RDWS bits in the EPIHBnCFG2 register. Each wait state adds 2 EPI clock cycles to the duration of the WRn or RDn strobe. During idle cycles, the address and muxed address data signals maintain the state of the last cycle. Figure 10-6 on page 475 shows a basic Host-Bus read cycle. Figure 10-7 on page 476 shows a basic Host-Bus write cycle. Both of these figures show address and data signals in the non-multiplexed mode (MODE field ix 0x1 in the EPIHBnCFG register). Figure 10-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 ALE (EPI0S30) CSn (EPI0S30) WRn (EPI0S29) RDn/OEn (EPI0S28) BSEL0n/ BSEL1na Address Data a Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. July 24, 2011 475 Texas Instruments-Production Data External Peripheral Interface (EPI) Figure 10-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 ALE (EPI0S30) CSn (EPI0S30) WRn (EPI0S29) RDn/OEn (EPI0S28) BSEL0n/ BSEL1na Address Data a Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. Figure 10-8 on page 476 shows a write cycle with the address and data signals multiplexed (MODE field is 0x0 in the EPIHBnCFG register). A read cycle would look similar, with the RDn strobe being asserted along with CSn and data being latched on the rising edge of RDn. Figure 10-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH = 0, RDHIGH =0 ALE (EPI0S30) CSn (EPI0S30) WRn (EPI0S29) RDn/OEn (EPI0S28) BSEL0n/ BSEL1na Address (high order, non muxed) Muxed Address/Data a Address Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. When using ALE with dual CSn configuration (CSCFG field in the EPIHBnCFG2 register is 0x3), the appropriate CSn signal is asserted at the same time as ALE as shown in Figure 10-9 on page 477. 476 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 10-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual CSn ALE (EPI0S30) CS0n/CS1n (EPI0S26/EPI0S27) WRn (EPI0S29) RDn/OEn (EPI0S28) BSEL0n/ BSEL1na Address (high order, non muxed) Muxed Address/Data a Address Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. Figure 10-10 on page 477 shows continuous read mode accesses. In this mode, reads are performed by keeping the read mode selected (output enable is asserted) and then changing the address pins. The data pins are changed by the SRAM after the address pins change. Figure 10-10. Continuous Read Mode Accesses OEn Address Data Addr1 Data1 Addr2 Data2 Addr3 Data3 FIFO mode accesses are the same as normal read and write accesses, except that the ALE signal and address pins are not present. Two input signals can be used to indicate when the XFIFO is full or empty to gate transactions and avoid overruns and underruns. The FFULL and FEMPTY signals are synchronized and must be recognized as asserted by the microcontroller for 2 system clocks before they affect transaction status. The MAXWAIT field in the EPIHBnCFG register defines the maximum number of EPI clocks to wait while the FEMPTY or FFULL signal is holding off a transaction. Figure 10-11 on page 478 shows how the FEMPTY signal should respond to a write and read from the XFIFO. Figure 10-12 on page 478 shows how the FEMPTY and FFULL signals should respond to 2 writes and 1 read from an external FIFO that contains two entries. July 24, 2011 477 Texas Instruments-Production Data External Peripheral Interface (EPI) Figure 10-11. Write Followed by Read to External FIFO FFULL (EPI0S27) FEMPTY (EPI0S26) CSn (EPI0S30) WRn (EPI0S29) RDn (EPI0S28) Data Data Data Figure 10-12. Two-Entry FIFO FFULL (EPI0S27) FEMPTY (EPI0S26) CSn (EPI0S30) WRn (EPI0S29) RDn (EPI0S28) Data 10.4.3 Data Data Data General-Purpose Mode The General-Purpose Mode Configuration (EPIGPCFG) register is used to configure the control, data, and address pins, if used. Any unused EPI controller signals can be used as GPIOs or another alternate function. The general-purpose configuration can be used for custom interfaces with FPGAs, CPLDs, and digital data acquisition and actuator control. Important: The RD2CYC bit in the EPIGPCFG register must be set at all times in General-Purpose mode to ensure proper operation. General-Purpose mode is designed for three general types of use: ■ Extremely high-speed clocked interfaces to FPGAs and CPLDs. Three sizes of data and optional address are supported. Framing and clock-enable functions permit more optimized interfaces. ■ General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely controlled by the EPIBAUD register baud rate (when used with the WFIFO and/or the NBRFIFO) or by the rate of accesses from software or μDMA. Examples of this type of use include: – Reading 20 sensors at fixed time periods by configuring 20 pins to be inputs, configuring the COUNT0 field in the EPIBAUD register to some divider, and then using non-blocking reads. 478 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller – Implementing a very wide ganged PWM/PCM with fixed frequency for driving actuators, LEDs, etc. – Implementing SDIO 4-bit mode where commands are driven or captured on 6 pins with fixed timing, fed by the µDMA. ■ General custom interfaces of any speed. The configuration allows for choice of an output clock (free-running or gated), a framing signal (with frame size), a ready input (to stretch transactions), a read and write strobe, an address (of varying sizes), and data (of varying sizes). Additionally, provisions are made for separating data and address phases. The interface has the following optional features: ■ Use of the EPI clock output is controlled by the CLKPIN bit in the EPIGPCFG register. Unclocked uses include general-purpose I/O and asynchronous interfaces (optionally using RD and WR strobes). Clocked interfaces allow for higher speeds and are much easier to connect to FPGAs and CPLDs (which usually include input clocks). ■ EPI clock, if used, may be free running or gated depending on the CLKGATE bit in the EPIGPCFG register. A free-running EPI clock requires another method for determining when data is live, such as the frame pin or RD/WR strobes. A gated clock approach uses a setup-time model in which the EPI clock controls when transactions are starting and stopping. The gated clock is held high until a new transaction is started and goes high at the end of the cycle where RD/WR/FRAME and address (and data if write) are emitted. ■ Use of the ready input (iRDY) from the external device is controlled by the RDYEN bit in the EPIGPCFG register. The iRDY signal uses EPI0S27 and may only be used with a free-running clock. iRDY gates transactions, no matter what state they are in. When iRDY is deasserted, the transaction is held off from completing. ■ Use of the frame output (FRAME) is controlled by the FRMPIN bit in the EPIGPCFG register. The frame pin may be used whether the clock is output or not, and whether the clock is free running or not. It may also be used along with the iRDY signal. The frame may be a pulse (one clock) or may be 50/50 split across the frame size (controlled by the FRM50 bit in the EPIGPCFG register). The frame count (the size of the frame as specified by the FRMCNT field in the EPIGPCFG register) may be between 1 and 15 clocks for pulsed and between 2 and 30 clocks for 50/50. The frame pin counts transactions and not clocks; a transaction is any clock where the RD or WR strobe is high (if used). So, if the FRMCNT bit is set, then the frame pin pulses every other transaction; if 2-cycle reads and writes are used, it pulses every other address phase. FRM50 must be used with this in mind as it may hold state for many clocks waiting for the next transaction. ■ Use of the RD and WR outputs is controlled by the RW bit in the EPIGPCFG register. For interfaces where the direction is known (in advance, related to frame size, or other means), these strobes are not needed. For most other interfaces, RD and WR are used so the external peripheral knows what transaction is taking place, and if any transaction is taking place. ■ Separation of address/request and data phases may be used on writes using the WR2CYC bit in the EPIGPCFG register. This configuration allows the external peripheral extra time to act. Address and data phases must be separated on reads, and the RD2CYC bit in the EPIGPCFG register must be set. When configured to use an address as specified by the ASIZE field in the EPIGPCFG register, the address is emitted on the with the RD strobe (first cycle) and data is July 24, 2011 479 Texas Instruments-Production Data External Peripheral Interface (EPI) expected to be returned on the next cycle (when RD is not asserted). If no address is used, then RD is asserted on the first cycle and data is captured on the second cycle (when RD is not asserted), allowing more setup time for data. For writes, the output may be in one or two cycles. In the two-cycle case, the address (if any) is emitted on the first cycle with the WR strobe and the data is emitted on the second cycle (with WR not asserted). Although split address and write data phases are not normally needed for logic reasons, it may be useful to make read and write timings match. If 2-cycle reads or writes are used, the RW bit is automatically set. ■ Address may be emitted (controlled by the ASIZE field in the EPIGPCFG register). The address may be up to 4 bits (16 possible values), up to 12 bits (4096 possible values), or up to 20 bits (1 M possible values). Size of address limits size of data, for example, 4 bits of address support up to 24 bits data. 4-bit address uses EPI0S[27:24]; 12-bit address uses EPI0S[27:16]; 20-bit address uses EPI0S[27:8]. The address signals may be used by the external peripheral as an address, code (command), or for other unrelated uses (such as a chip enable). If the chosen address/data combination does not use all of the EPI signals, the unused pins can be used as GPIOs or for other functions. For example, when using a 4-bit address with an 8-bit data, the pins assigned to EPIS0[23:8] can be assigned to other functions. ■ Data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by the DSIZE field in the EPIGPCFG register). 32-bit data cannot be used with address or EPI clock or any other signal. 24-bit data can only be used with 4-bit address or no address. 32-bit data requires that either the WR2CYC bit or the RD2CYC bit in the EPIGPCFG register is set. ■ Memory can be used more efficiently by using the Word Access Mode. By default, the EPI controller uses data bits [7:0] when the DSIZE field in the EPIGPCFG register is 0x0; data bits [15:0] when the DSIZE field is 0x1; data bits [23:0] when the DSIZE field is 0x2; and data bits [31:0] when the DSIZE field is 0x3. When the WORD bit in the EPIGPCFG2 register is set, the EPI controller automatically routes bytes of data onto the correct byte lanes such that data can be stored in bits [31:8] for DSIZE=0x0 and bits [31:16] for DSIZE=0x1. ■ When using the EPI controller as a GPIO interface, writes are FIFOed (up to 4 can be held at any time), and up to 32 pins are changed using the EPIBAUD clock rate specified by COUNT0. As a result, output pin control can be very precisely controlled as a function of time. By contrast, when writing to normal GPIOs, writes can only occur 8-bits at a time and take up to two clock cycles to complete. In addition, the write itself may be further delayed by the bus due to μDMA or draining of a previous write. With both GPIO and the EPI controller, reads may be performed directly, in which case the current pin states are read back. With the EPI controller, the non-blocking interface may also be used to perform reads based on a fixed time rule via the EPIBAUD clock rate. Table 10-7 on page 480 shows how the EPI0S[31:0] signals function while in General-Purpose mode. Notice that the address connections vary depending on the data-width restrictions of the external peripheral. Table 10-7. EPI General Purpose Signal Connections EPI Signal General-Purpose Signal (D8, A20) General- Purpose Signal (D16, A12) General- Purpose Signal (D24, A4) General- Purpose Signal (D32) EPI0S0 D0 D0 D0 D0 EPI0S1 D1 D1 D1 D1 EPI0S2 D2 D2 D2 D2 480 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 10-7. EPI General Purpose Signal Connections (continued) EPI Signal General-Purpose Signal (D8, A20) General- Purpose Signal (D16, A12) General- Purpose Signal (D24, A4) General- Purpose Signal (D32) EPI0S3 D3 D3 D3 D3 EPI0S4 D4 D4 D4 D4 EPI0S5 D5 D5 D5 D5 EPI0S6 D6 D6 D6 D6 EPI0S7 D7 D7 D7 D7 EPI0S8 A0 D8 D8 D8 EPI0S9 A1 D9 D9 D9 EPI0S10 A2 D10 D10 D10 EPI0S11 A3 D11 D11 D11 EPI0S12 A4 D12 D12 D12 EPI0S13 A5 D13 D13 D13 EPI0S14 A6 D14 D14 D14 EPI0S15 A7 D15 D15 D15 EPI0S16 A8 A0 a D16 D16 EPI0S17 A9 A1 D17 D17 EPI0S18 A10 A2 D18 D18 EPI0S19 A11 A3 D19 D19 EPI0S20 A12 A4 D20 D20 EPI0S21 A13 A5 D21 D21 EPI0S22 A14 A6 D22 D22 EPI0S23 A15 A7 D23 D23 EPI0S24 A16 A8 A0 b D24 EPI0S25 A17 A9 A1 D25 EPI0S26 A18 A10 A2 D26 EPI0S27 A19/iRDY A11/iRDY A3/iRDY c c c D27 EPI0S28 WR WR WR D28 EPI0S29 RD RD RD D29 EPI0S30 Frame Frame Frame D30 EPI0S31 Clock Clock Clock D31 a. In this mode, half-word accesses are used. AO is the LSB of the address and is equivalent to the system A1 address. b. In this mode, word accesses are used. AO is the LSB of the address and is equivalent to the system A2 address. c. This signal is iRDY if the RDYEN bit in the EPIGPCFG register is set. 10.4.3.1 Bus Operation A basic access is 1 EPI clock for write cycles and 2 EPI clocks for read cycles. An additional EPI clock can be inserted into a write cycle by setting the WR2CYC bit in the EPIGPCFG register. Note that the RD2CYC bit must always be set in the EPIGPCFG register. If the iRDY signal is deasserted, further transactions are held off until the iRDY signal is asserted again. July 24, 2011 481 Texas Instruments-Production Data External Peripheral Interface (EPI) Figure 10-13. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 Clock (EPI0S31) Frame (EPI0S30) RD (EPI0S29) WR (EPI0S28) Address Data Data Figure 10-14. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1, WRCYC=1 CLOCK (EPI0S31) FRAME (EPI0S30) RD (EPI0S29) WR (EPI0S28) Address Data Data Read Data Write 482 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 10-15. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 CLOCK (EPI0S31) FRAME (EPI0S30) RD (EPI0S29) WR (EPI0S28) Addr1 Address Addr2 Data1 Data Addr3 Data2 Data3 FRAME Signal Operation The operation of the FRAME signal is controlled by the FRMCNT and FRM50 bits. When FRM50 is clear, the FRAME signal is high whenever the WR or RD strobe is high. When FRMCNT is clear, the FRAME signal is simply the logical OR of the WR and RD strobes so the FRAME signal is high during every read or write access, see Figure 10-16 on page 483. Figure 10-16. FRAME Signal Operation, FRM50=0 and FRMCNT=0 Clock (EPI0S31) WR (EPI0S28) RD (EPI0S29) Frame (EPI0S30) If the FRMCNT field is 0x1, then the FRAME signal pulses high during every other read or write access, see Figure 10-17 on page 483. Figure 10-17. FRAME Signal Operation, FRM50=0 and FRMCNT=1 Clock (EPI0S31) WR (EPI0S28) RD (EPI0S29) Frame (EPI0S30) If the FRMCNT field is 0x2 and FRM50 is clear, then the FRAME signal pulses high during every third access, and so on for every value of FRMCNT, see Figure 10-18 on page 484. July 24, 2011 483 Texas Instruments-Production Data External Peripheral Interface (EPI) Figure 10-18. FRAME Signal Operation, FRM50=0 and FRMCNT=2 Clock (EPI0S31) WR (EPI0S28) RD (EPI0S29) Frame (EPI0S30) When FRM50 is set, the FRAME signal transitions on the rising edge of either the WR or RD strobes. When FRMCNT=0, the FRAME signal transitions on the rising edge of WR or RD for every access, see Figure 10-19 on page 484. Figure 10-19. FRAME Signal Operation, FRM50=1 and FRMCNT=0 Clock (EPI0S31) WR (EPI0S28) RD (EPI0S29) Frame (EPI0S30) When FRMCNT=1, the FRAME signal transitions on the rising edge of the WR or RD strobes for every other access, see Figure 10-20 on page 484. Figure 10-20. FRAME Signal Operation, FRM50=1 and FRMCNT=1 Clock (EPI0S31) WR (EPI0S28) RD (EPI0S29) Frame (EPI0S30) When FRMCNT=2, the FRAME signal transitions the rising edge of the WR or RD strobes for every third access, and so on for every value of FRMCNT, see Figure 10-21 on page 484. Figure 10-21. FRAME Signal Operation, FRM50=1 and FRMCNT=2 CLOCK (EPI0S31) WR (EPI0S28) RD (EPI0S29) FRAME (EPI0S30) 484 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller iRDY Signal Operation The ready input (iRDY) from the external device is enabled by the RDYEN bit in the EPIGPCFG register. iRDY is input on EPI0S27 and may only be used with a free-running clock (CLKGATE is clear). iRDY is sampled on the falling edge of the EPI clock and gates transactions, no matter what state they are in. Figure 10-22 on page 485 shows the iRDY signal being recognized as deasserted on the falling edge of T1. The FRAME, RD, Address, Data signals behave as they would during a normal transaction in T1. T2 is the frozen state, and signals are held in this state until iRDY is recognized as asserted again. At the falling edge of T2, when iRDY is asserted again, the cycle continues and completes in T3. Figure 10-22. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 T0 T1 T2 T3 Clock (EPI0S31) Frame (EPI0S30) RD (EPI0S29) iRDY (EPI0S27) Address Data EPI Clock Operation If the CLKGATE bit in the EPIGPCFG register is clear, the EPI clock always toggles when General-purpose mode is enabled. If CLKGATE is set, the clock is output only when a transaction is occurring, otherwise the clock is held high. If the WR2CYC bit is clear, the EPI clock begins toggling 1 cycle before the WR strobe goes high. If the WR2CYC bit is set, the EPI clock begins toggling when the WR strobe goes high. The clock stops toggling after the first rising edge after the WR strobe is deasserted. The RD strobe operates in the same manner as the WR strobe when the WR2CYC bit is set, as the RD2CYC bit must always be set. See Figure 10-23 on page 485 and Figure 10-24 on page 486. Figure 10-23. EPI Clock Operation, CLKGATE=1, WR2CYC=0 Clock (EPI0S31) WR (EPI0S28) Address Data July 24, 2011 485 Texas Instruments-Production Data External Peripheral Interface (EPI) Figure 10-24. EPI Clock Operation, CLKGATE=1, WR2CYC=1 Clock (EPI0S31) WR (EPI0S28) Address Data 10.5 Register Map Table 10-8 on page 486 lists the EPI registers. The offset listed is a hexadecimal increment to the register’s address, relative to the base address of 0x400D.0000. Note that the EPI controller clock must be enabled before the registers can be programmed (see page 246). There must be a delay of 3 system clocks after the EPI module clock is enabled before any EPI module registers are accessed. Note: A back-to-back write followed by a read of the same register reads the value that written by the first write access, not the value from the second write access. (This situation only occurs when the processor core attempts this action, the μDMA does not do this.). To read back what was just written, another instruction must be generated between the write and read. Read-write does not have this issue, so use of read-write for clear of error interrupt cause is not affected. Table 10-8. External Peripheral Interface (EPI) Register Map Description See page Offset Name Type Reset 0x000 EPICFG R/W 0x0000.0000 EPI Configuration 488 0x004 EPIBAUD R/W 0x0000.0000 EPI Main Baud Rate 489 0x010 EPISDRAMCFG R/W 0x42EE.0000 EPI SDRAM Configuration 491 0x010 EPIHB8CFG R/W 0x0000.0000 EPI Host-Bus 8 Configuration 493 0x010 EPIHB16CFG R/W 0x0000.0000 EPI Host-Bus 16 Configuration 496 0x010 EPIGPCFG R/W 0x0000.0000 EPI General-Purpose Configuration 500 0x014 EPIHB8CFG2 R/W 0x0000.0000 EPI Host-Bus 8 Configuration 2 505 0x014 EPIHB16CFG2 R/W 0x0000.0000 EPI Host-Bus 16 Configuration 2 508 0x014 EPIGPCFG2 R/W 0x0000.0000 EPI General-Purpose Configuration 2 511 0x01C EPIADDRMAP R/W 0x0000.0000 EPI Address Map 512 0x020 EPIRSIZE0 R/W 0x0000.0003 EPI Read Size 0 514 0x024 EPIRADDR0 R/W 0x0000.0000 EPI Read Address 0 515 0x028 EPIRPSTD0 R/W 0x0000.0000 EPI Non-Blocking Read Data 0 516 0x030 EPIRSIZE1 R/W 0x0000.0003 EPI Read Size 1 514 0x034 EPIRADDR1 R/W 0x0000.0000 EPI Read Address 1 515 486 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 10-8. External Peripheral Interface (EPI) Register Map (continued) Name Type Reset 0x038 EPIRPSTD1 R/W 0x0000.0000 EPI Non-Blocking Read Data 1 516 0x060 EPISTAT RO 0x0000.0000 EPI Status 518 0x06C EPIRFIFOCNT RO - EPI Read FIFO Count 520 0x070 EPIREADFIFO RO - EPI Read FIFO 521 0x074 EPIREADFIFO1 RO - EPI Read FIFO Alias 1 521 0x078 EPIREADFIFO2 RO - EPI Read FIFO Alias 2 521 0x07C EPIREADFIFO3 RO - EPI Read FIFO Alias 3 521 0x080 EPIREADFIFO4 RO - EPI Read FIFO Alias 4 521 0x084 EPIREADFIFO5 RO - EPI Read FIFO Alias 5 521 0x088 EPIREADFIFO6 RO - EPI Read FIFO Alias 6 521 0x08C EPIREADFIFO7 RO - EPI Read FIFO Alias 7 521 0x200 EPIFIFOLVL R/W 0x0000.0033 EPI FIFO Level Selects 522 0x204 EPIWFIFOCNT RO 0x0000.0004 EPI Write FIFO Count 524 0x210 EPIIM R/W 0x0000.0000 EPI Interrupt Mask 525 0x214 EPIRIS RO 0x0000.0004 EPI Raw Interrupt Status 526 0x218 EPIMIS RO 0x0000.0000 EPI Masked Interrupt Status 528 0x21C EPIEISC R/W1C 0x0000.0000 EPI Error Interrupt Status and Clear 529 10.6 Description See page Offset Register Descriptions This section lists and describes the EPI registers, in numerical order by address offset. July 24, 2011 487 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 1: EPI Configuration (EPICFG), offset 0x000 Important: The MODE field determines which configuration register is accessed for offsets 0x010 and 0x014. Any write to the EPICFG register resets the register contents at offsets 0x010 and 0x014. The configuration register is used to enable the block, select a mode, and select the basic pin use (based on the mode). Note that attempting to program an undefined MODE field clears the BLKEN bit and disables the EPI controller. EPI Configuration (EPICFG) Base 0x400D.0000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 BLKEN Bit/Field Name Type Reset 31:5 reserved RO 0x0000.000 4 BLKEN R/W 0 R/W 0 MODE Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Block Enable Value Description 3:0 MODE R/W 0x0 1 The EPI controller is enabled. 0 The EPI controller is disabled. Mode Select Value Description 0x0 General Purpose General-Purpose mode. Control, address, and data pins are configured using the EPIGPCFG and EPIGPCFG2 registers. 0x1 SDRAM Supports SDR SDRAM. Control, address, and data pins are configured using the EPISDRAMCFG register. 0x2 8-Bit Host-Bus (HB8) Host-bus 8-bit interface (also known as the MCU interface). Control, address, and data pins are configured using the EPIHB8CFG and EPIHB8CFG2 registers. 0x3 16-Bit Host-Bus (HB16) Host-bus 16-bit interface (standard SRAM). Control, address, and data pins are configured using the EPIHB16CFG and EPIHB16CFG2 registers. 0x3-0xF Reserved 488 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004 The system clock is used internally to the EPI Controller. The baud rate counter can be used to divide the system clock down to control the speed on the external interface. If the mode selected emits an external EPI clock, this register defines the EPI clock emitted. If the mode selected does not use an EPI clock, this register controls the speed of changes on the external interface. Care must be taken to program this register properly so that the speed of the external bus corresponds to the speed of the external peripheral and puts acceptable current load on the pins. COUNT0 is the bit field used in all modes except in HB8 and HB16 modes with dual chip selects when different baud rates are selected, see page 505. If different baud rates are used, COUNT0 is associated with the address range specified by CS0 and COUNT1 is associated with the address range specified by CS1. The COUNTn field is not a straight divider or count. The EPI Clock on EPI0S31 is related to the COUNTn field and the system clock as follows: If COUNTn = 0, EPIClockFreq = SystemClockFreq otherwise: EPIClockFreq = SystemClockFreq ⎛ ⎢COUNTn ⎥ ⎞ + 1⎟ × 2 ⎜⎢ ⎥ 2 ⎣ ⎦ ⎝ ⎠ where the symbol around COUNTn/2 is the floor operator, meaning the largest integer less than or equal to COUNTn/2. So, for example, a COUNTn of 0x0001 results in a clock rate of ½(system clock); a COUNTn of 0x0002 or 0x0003 results in a clock rate of ¼(system clock). EPI Main Baud Rate (EPIBAUD) Base 0x400D.0000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 COUNT1 Type Reset COUNT0 Type Reset Bit/Field Name Type Reset 31:16 COUNT1 RO 0x0000 Description Baud Rate Counter 1 This bit field is only valid when the CSCFG field is 0x2 or 0x3 and the CSBAUD bit is set in the EPIHBnCFG2 register. This bit field contains a counter used to divide the system clock by the count. The maximum frequency for the external EPI clock is 50 MHz. A count of 0 means the system clock is used as is. July 24, 2011 489 Texas Instruments-Production Data External Peripheral Interface (EPI) Bit/Field Name Type Reset 15:0 COUNT0 R/W 0x0000 Description Baud Rate Counter 0 This bit field contains a counter used to divide the system clock by the count. The maximum frequency for the external EPI clock is 50 MHz. A count of 0 means the system clock is used as is. 490 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 3: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPISDRAMCFG, the MODE field must be 0x1. The SDRAM Configuration register is used to specify several parameters for the SDRAM controller. Note that this register is reset when the MODE field in the EPICFG register is changed. If another mode is selected and the SDRAM mode is selected again, the values must be reinitialized. The SDRAM interface designed to interface to x16 SDR SDRAMs of 64 MHz or higher, with the address and data pins overlapped (wire ORed on the board). See Table 10-3 on page 464 for pin assignments. EPI SDRAM Configuration (EPISDRAMCFG) Base 0x400D.0000 Offset 0x010 Type R/W, reset 0x42EE.0000 31 30 29 R/W 0 R/W 1 RO 0 15 14 13 RO 0 RO 0 RO 0 FREQ Type Reset 28 27 26 25 24 23 22 RO 0 RO 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 1 12 11 10 9 8 7 6 RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 20 19 18 17 16 R/W 1 R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 RFSH reserved Type Reset 21 SLEEP R/W 0 Bit/Field Name Type Reset 31:30 FREQ R/W 0x1 reserved RO 0 SIZE R/W 0 Description Frequency Range This field configures the frequency range of the system clock. This field must be configured correctly to ensure proper operation. This field does not affect the refresh counting, which is configured separately using the RFSH field (and is based on system clock rate and number of rows per bank). The ranges are: Value Description 29:27 reserved RO 0x0 26:16 RFSH R/W 0x2EE 0x0 0 - 15 MHz 0x1 15 - 30 MHz 0x2 30 - 50 MHz 0x3 50 - 100 MHz Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Refresh Counter This field contains the refresh counter in system clocks. The reset value of 0x2EE provides a refresh period of 64 ms when using a 50 MHz clock. 15:10 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 491 Texas Instruments-Production Data External Peripheral Interface (EPI) Bit/Field Name Type Reset Description 9 SLEEP R/W 0 Sleep Mode Value Description 1 The SDRAM is put into low power state, but is self-refreshed. 0 No effect. 8:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1:0 SIZE R/W 0x0 Size of SDRAM The value of this field affects address pins and behavior. Value Description 0x0 64 megabits (8MB) 0x1 128 megabits (16MB) 0x2 256 megabits (32MB) 0x3 512 megabits (64MB) 492 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 4: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB8CFG, the MODE field must be 0x2. The Host Bus 8 Configuration register is activated when the HB8 mode is selected. The HB8 mode supports muxed address/data (overlay of lower 8 address and all 8 data pins), separated address/data, and address-less FIFO mode. Note that this register is reset when the MODE field in the EPICFG register is changed. If another mode is selected and the HB8 mode is selected again, the values must be reinitialized. This mode is intended to support SRAMs, Flash memory (read), FIFOs, CPLDs/FPGAs, and devices with an MCU/HostBus slave or 8-bit FIFO interface support. Refer to Table 10-5 on page 469 for information on signal configuration controlled by this register and the EPIHB8CFG2 register. If less address pins are required, the corresponding AFSEL bit (page 424) should not be enabled so the EPI controller does not drive those pins, and they are available as standard GPIOs. There is no direct chip enable (CE) model. Instead, CE can be handled in one of three ways: 1. Manually control via GPIOs. 2. Associate one or more upper address pins to CE. Because CE is normally CEn, lower addresses are not used. For example, if pins EPI0S27 and EPI0S26 are used for Device 1 and 0 respectively, then address 0x6800.0000 accesses Device 0 (Device 1 has its CEn high), and 0x6400.0000 accesses Device 1 (Device 0 has its CEn high). The pull-up behavior on the corresponding GPIOs must be properly configured to ensure that the pins are disabled when the interface is not in use. 3. With certain SRAMs, the ALE can be used as CEn because the address remains stable after the ALE strobe. The subsequent WRn or RDn signals write or read when ALE is low thus providing CEn functionality. EPI Host-Bus 8 Configuration (EPIHB8CFG) Base 0x400D.0000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 reserved Type Reset 22 XFEEN 21 20 19 18 WRHIGH RDHIGH 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R/W 0 R/W 0 R/W 0 R/W 0 WRWS R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RDWS R/W 0 R/W 0 16 reserved RO 0 MAXWAIT Type Reset 23 XFFEN reserved RO 0 RO 0 RO 0 0 MODE R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 493 Texas Instruments-Production Data External Peripheral Interface (EPI) Bit/Field Name Type Reset 23 XFFEN R/W 0 Description External FIFO FULL Enable Value Description 22 XFEEN R/W 0 1 An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL full signal is high, XFIFO writes are stalled. 0 No effect. External FIFO EMPTY Enable Value Description 21 WRHIGH R/W 0 1 An external FIFO empty signal can be used to control read cycles. If this bit is set and the FEMPTY signal is high, XFIFO reads are stalled. 0 No effect. CS0n WRITE Strobe Polarity Value Description 20 RDHIGH R/W 0 1 The WRITE strobe for CS0n accesses is WR (active High). 0 The WRITE strobe for CS0n accesses is WRn (active Low). CS0n READ Strobe Polarity Value Description 1 The READ strobe for CS0n accesses is RD (active High). 0 The READ strobe for CS0n accesses is RDn (active Low). 19:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 MAXWAIT R/W 0x00 Maximum Wait This field defines the maximum number of external clocks to wait while an external FIFO ready signal is holding off a transaction (FFULL and FEMPTY). When this field is clear, the transaction is held off forever. Note: When the MODE field is configured to be 0x2 and the BLKEN bit is set in the EPICFG register, enabling HB8 mode, this field defaults to 0xFF. 494 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 7:6 WRWS R/W 0x0 Description Write Wait States This field adds wait states to the data phase of CS0n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. Value Description 0x0 No wait states. 0x1 1 wait state. 0x2 2 wait states. 0x3 3 wait states. This field is used in conjunction with the EPIBAUD register. 5:4 RDWS R/W 0x0 Read Wait States This field adds wait states to the data phase of CS0n accesses (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. Value Description 0x0 No wait states. 0x1 1 wait state. 0x2 2 wait states. 0x3 3 wait states. This field is used in conjunction with the EPIBAUD register. 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1:0 MODE R/W 0x0 Host Bus Sub-Mode This field determines which of four Host Bus 8 sub-modes to use. Sub-mode use is determined by the connected external peripheral. See Table 10-5 on page 469 for information on how this bit field affects the operation of the EPI signals. Value Description 0x0 ADMUX – AD[7:0] Data and Address are muxed. 0x1 ADNONMUX – D[7:0] Data and address are separate. 0x2 Continuous Read - D[7:0] This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OEn strobing. 0x3 XFIFO – D[7:0] This mode adds XFIFO controls with sense of XFIFO full and XFIFO empty. This mode uses no address or ALE. July 24, 2011 495 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 5: EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB16CFG, the MODE field must be 0x3. The Host Bus 16 sub-configuration register is activated when the HB16 mode is selected. The HB16 mode supports muxed address/data (overlay of lower 16 address and all 16 data pins), separated address/data, and address-less FIFO mode. Note that this register is reset when the MODE field in the EPICFG register is changed. If another mode is selected and the HB16 mode is selected again, the values must be reinitialized. This mode is intended to support SRAMs, Flash memory (read), FIFOs, and CPLDs/FPGAs, and devices with an MCU/HostBus slave or 16-bit FIFO interface support. Refer to Table 10-6 on page 470 for information on signal configuration controlled by this register and the EPIHB16CFG2 register. If less address pins are required, the corresponding AFSEL bit (page 424) should not be enabled so the EPI controller does not drive those pins, and they are available as standard GPIOs. There is no direct chip enable (CE) model. Instead, CE can be handled in one of three ways: 1. Manually control via GPIOs. 2. Associate one or more upper address pins to CE. Because CE is normally CEn, lower addresses are not used. For example, if pins EPI0S27 and EPI0S26 are used for Device 1 and 0 respectively, then address 0x6800.0000 accesses Device 0 (Device 1 has its CEn high), and 0x6400.0000 accesses Device 1 (Device 0 has its CEn high). The pull-up behavior on the corresponding GPIOs must be properly configured to ensure that the pins are disabled when the interface is not in use. 3. With certain SRAMs, the ALE can be used as CEn because the address remains stable after the ALE strobe. The subsequent WRn or RDn signals write or read when ALE is low thus providing CEn functionality. EPI Host-Bus 16 Configuration (EPIHB16CFG) Base 0x400D.0000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 reserved Type Reset 22 XFEEN 21 20 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 WRWS R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 19 18 WRHIGH RDHIGH RO 0 MAXWAIT Type Reset 23 XFFEN RDWS R/W 0 R/W 0 17 16 reserved RO 0 RO 0 RO 0 1 3 2 reserved BSEL RO 0 R/W 0 RO 0 0 MODE R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 496 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 23 XFFEN R/W 0 Description External FIFO FULL Enable Value Description 22 XFEEN R/W 0 1 An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL signal is high, XFIFO writes are stalled. 0 No effect. External FIFO EMPTY Enable Value Description 21 WRHIGH R/W 0 1 An external FIFO empty signal can be used to control read cycles. If this bit is set and the FEMPTY signal is high, XFIFO reads are stalled. 0 No effect. WRITE Strobe Polarity Value Description 20 RDHIGH R/W 0 1 The WRITE strobe for CS0n accesses is WR (active High). 0 The WRITE strobe for CS0n accesses is WRn (active Low). READ Strobe Polarity Value Description 1 The READ strobe for CS0n accesses is RD (active High). 0 The READ strobe for CS0n accesses is RDn (active Low). 19:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 MAXWAIT R/W 0x00 Maximum Wait This field defines the maximum number of external clocks to wait while an external FIFO ready signal is holding off a transaction (FFULL and FEMPTY). When this field is clear, the transaction is held off forever. Note: When the MODE field is configured to be 0x3 and the BLKEN bit is set in the EPICFG register, enabling HB16 mode, this field defaults to 0xFF. July 24, 2011 497 Texas Instruments-Production Data External Peripheral Interface (EPI) Bit/Field Name Type Reset 7:6 WRWS R/W 0x0 Description CS0n Write Wait States This field adds wait states to the data phase of CS0n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. Value Description 0x0 No wait states. 0x1 1 wait state. 0x2 2 wait states. 0x3 3 wait states. This field is used in conjunction with the EPIBAUD register. 5:4 RDWS R/W 0x0 CS0n Read Wait States This field adds wait states to the data phase of CS0n accesses (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. Value Description 0x0 No wait states. 0x1 1 wait state. 0x2 2 wait states. 0x3 3 wait states. This field is used in conjunction with the EPIBAUD register. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 BSEL R/W 0 Byte Select Configuration This bit enables byte select operation. Value Description 0 No Byte Selects Data is read and written as 16 bits. 1 Enable Byte Selects Two EPI signals function as byte select signals to allow 8-bit transfers. See Table 10-6 on page 470 for details on which EPI signals are used. 498 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 1:0 MODE R/W 0x0 Description Host Bus Sub-Mode This field determines which of three Host Bus 16 sub-modes to use. Sub-mode use is determined by the connected external peripheral. See Table 10-6 on page 470 for information on how this bit field affects the operation of the EPI signals. Value Description 0x0 ADMUX – AD[15:0] Data and Address are muxed. 0x1 ADNONMUX – D[15:0] Data and address are separate. This mode is not practical in HB16 mode for normal peripherals because there are generally not enough address bits available. 0x2 Continuous Read - D[15:0] This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OEn strobing. This mode is not practical in HB16 mode for normal SRAMs because there are generally not enough address bits available. 0x3 XFIFO – D[15:0] This mode adds XFIFO controls with sense of XFIFO full and XFIFO empty. This mode uses no address or ALE. July 24, 2011 499 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 6: EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIGPCFG, the MODE field must be 0x0. The RD2CYC bit must be set at all times in General-Purpose mode to ensure proper operation. The General-Purpose configuration register is used to configure the control, data, and address pins. This mode can be used for custom interfaces with FPGAs, CPLDs, and for digital data acquisition and actuator control. Note that this register is reset when the MODE field in the EPICFG register is changed. If another mode is selected and the General-purpose mode is selected again, the register the values must be reinitialized. This mode is designed for 3 general types of use: ■ Extremely high-speed clocked interfaces to FPGAs and CPLDs, with 3 sizes of data and optional address. Framing and clock-enable permit more optimized interfaces. ■ General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely controlled by the baud rate in the EPIBAUD register (when used with the NBRFIFO and/or the WFIFO) or by rate of accesses from software or μDMA. ■ General custom interfaces of any speed. The configuration allows for choice of an output clock (free running or gated), a framing signal (with frame size), a ready input (to stretch transactions), read and write strobes, address of varying sizes, and data of varying sizes. Additionally, provisions are made for splitting address and data phases on the external interface. EPI General-Purpose Configuration (EPIGPCFG) Base 0x400D.0000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 CLKPIN CLKGATE Type Reset 29 28 27 26 reserved 25 24 22 FRMCNT 21 20 19 18 17 RDYEN FRMPIN FRM50 RW R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 reserved R/W 0 Bit/Field Name Type Reset 31 CLKPIN R/W 0 ASIZE WR2CYC RD2CYC 16 reserved MAXWAIT Type Reset 23 reserved reserved DSIZE R/W 0 Description Clock Pin Value Description 1 EPI0S31 functions as the EPI clock output. 0 No clock output. The EPI clock is generated from the COUNT0 field in the EPIBAUD register (as is the system clock which is divided down from it). 500 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 30 CLKGATE R/W 0 Clock Gated Value Description 1 The EPI clock is output only when there is data to write or read (current transaction); otherwise the EPI clock is held low. 0 The EPI clock is free running. Note that EPI0S27 is an iRDY signal if RDYEN is set. CLKGATE is ignored if CLKPIN is 0 or if the COUNT0 field in the EPIBAUD register is cleared. 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 RDYEN R/W 0 Ready Enable Value Description 1 The external peripheral drives an iRDY signal into pin EPI0S27. 0 The external peripheral does not drive an iRDY signal and is assumed to be ready always. The ready enable signal may only be used with a free-running EPI clock (CLKGATE=0). The external iRDY signal is sampled on the falling edge of the EPI clock. Setup and hold times must be met to ensure registration on the next falling EPI clock edge. This bit is ignored if CLKPIN is 0 or CLKGATE is 1. 27 FRMPIN R/W 0 Framing Pin Value Description 1 A framing signal is output on EPI0S30. 0 No framing signal is output. Framing has no impact on data itself, but forms a context for the external peripheral. When used with a free-running EPI clock, the FRAME signal forms the valid signal. When used with a gated EPI clock, it is usually used to form a frame size. 26 FRM50 R/W 0 50/50 Frame Value Description 1 The FRAME signal is output as 50/50 duty cycle using count (see FRMCNT). 0 The FRAME signal is output as a single pulse, and then held low for the count. This bit is ignored if FRMPIN is 0. July 24, 2011 501 Texas Instruments-Production Data External Peripheral Interface (EPI) Bit/Field Name Type Reset 25:22 FRMCNT R/W 0x0 Description Frame Count This field specifies the size of the frame in EPI clocks. The frame counter is used to determine the frame size. The count is FRMCNT+1. So, a FRMCNT of 0 forms a pure transaction valid signal (held high during transactions, low otherwise). A FRMCNT of 0 with FRM50 set inverts the FRAME signal on each transaction. A FRMCNT of 1 means the FRAME signal is inverted every other transaction; a value of 15 means every sixteenth transaction. If FRM50 is set, the frame is held high for FRMCNT+1 transactions, then held low for that many transactions, and so on. If FRM50 is clear, the frame is pulsed high for one EPI clock and then low for FRMCNT EPI clocks. This field is ignored if FRMPIN is 0. 21 RW R/W 0 Read and Write Value Description 1 RD and WR strobes are asserted on EPI0S29 and EPI0S28. RD is asserted high on the rising edge of the EPI clock when a read is being performed. WR is asserted high on the rising edge of the EPI clock when a write is being performed 0 RD and WR strobes are not output. This bit is forced to 1 when RD2CYC and/or WR2CYC is 1. 20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 WR2CYC R/W 0 2-Cycle Writes Value Description 1 Writes are two EPI clock cycles long, with address on one EPI clock cycle (with the WR strobe asserted) and data written on the following EPI clock cycle (with WR strobe de-asserted). The next address (if any) is in the cycle following. 0 Data is output on the same EPI clock cycle as the address. When this bit is set, then the RW bit is forced to be set. 18 RD2CYC R/W 0 2-Cycle Reads Value Description 1 Reads are two EPI clock cycles, with address on one EPI clock cycle (with the RD strobe asserted) and data captured on the following EPI clock cycle (with the RD strobe de-asserted). The next address (if any) is in the cycle following. 0 Data is captured on the EPI clock cycle with READ strobe asserted. When this bit is set, then the RW bit is forced to be set. Caution – This bit must be set at all times in General-Purpose mode to ensure proper operation. 502 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 17:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 MAXWAIT R/W 0x00 Maximum Wait This field defines the maximum number of EPI clocks to wait while the iRDY signal (see RDYEN) is holding off a transaction. If this field is 0, the transaction is held forever. If the maximum wait of 255 clocks (MAXWAIT=0xFF) is exceeded, an error interrupt occurs and the transaction is aborted/ignored. Note: When the MODE field is configured to be 0x0 and the BLKEN bit is set in the EPICFG register, enabling General-Purpose mode, this field defaults to 0xFF. 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 ASIZE R/W 0x0 Address Bus Size This field defines the size of the address bus. The address can be up to 4-bits wide with a 24-bit data bus, up to 12-bits wide with a 16-bit data bus, and up to 20-bits wide with an 8-bit data bus. If the full address bus is not used, use the least significant address bits. Any unused address bits can be used as GPIOs by clearing the AFSEL bit for the corresponding GPIOs. Also, if RDYEN is 1, then the address sizes are 1 smaller (3, 11, 19). The values are: Value Description 3:2 reserved RO 0x0 0x0 No address 0x1 Up to 4 bits wide. 0x2 Up to 12 bits wide. This size cannot be used with 24-bit data. 0x3 Up to 20 bits wide. This size cannot be used with data sizes other than 8. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 503 Texas Instruments-Production Data External Peripheral Interface (EPI) Bit/Field Name Type Reset 1:0 DSIZE R/W 0x0 Description Size of Data Bus This field defines the size of the data bus (starting at EPI0S0). Subsets of these numbers can be created by clearing the AFSEL bit for the corresponding GPIOs. Note that size 32 may not be used with clock, frame, address, or other control. The values are: Value Description 0x0 8 Bits Wide (EPI0S0 to EPI0S7) 0x1 16 Bits Wide (EPI0S0 to EPI0S15) 0x2 24 Bits Wide (EPI0S0 to EPI0S23) 0x3 32 Bits Wide (EPI0S0 to EPI0S31) This size may not be used with an EPI clock. This value is normally used for acquisition input and actuator control as well as other general-purpose uses that require 32 bits per direction. 504 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 7: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB8CFG2, the MODE field must be 0x2. This register is used to configure operation while in Host-Bus 8 mode. Note that this register is reset when the MODE field in the EPICFG register is changed. If another mode is selected and the Host-Bus 8 mode is selected again, the values must be reinitialized. EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2) Base 0x400D.0000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 WORD Type Reset 29 28 27 reserved 26 25 CSBAUD 24 R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 15 14 13 12 11 10 9 8 7 RO 0 RO 0 RO 0 RO 0 22 reserved reserved Type Reset 23 CSCFG 21 RO 0 RO 0 Bit/Field Name Type Reset 31 WORD R/W 0 RO 0 R/W 0 19 18 17 16 reserved RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 RO 0 RO 0 WRWS RO 0 20 WRHIGH RDHIGH R/W 0 RDWS R/W 0 R/W 0 reserved RO 0 RO 0 Description Word Access Mode By default, the EPI controller uses data bits [7:0] for Host-Bus 8 accesses. When using Word Access mode, the EPI controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:8]. When WORD is set, short and long variables can be used in C programs. Value Description 30:27 reserved RO 0x0 26 CSBAUD R/W 0 0 Word Access mode is disabled. 1 Word Access mode is enabled. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Chip Select Baud Rate Value Description 0 Same Baud Rate Both CS0n and CS1n use the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register. 1 Different Baud Rates CS0n uses the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register. CS1n uses the baud rate defined by the COUNT1 field in the EPIBAUD register. July 24, 2011 505 Texas Instruments-Production Data External Peripheral Interface (EPI) Bit/Field Name Type Reset 25:24 CSCFG R/W 0x0 Description Chip Select Configuration Value Description 0x0 ALE Configuration EPI0S30 is used as an address latch (ALE). The ALE signal is generally used when the address and data are muxed (HB8MODE field in the EPIHB8CFG register is 0x0). The ALE signal is used by an external latch to hold the address through the bus cycle. 0x1 CSn Configuration EPI0S30 is used as a Chip Select (CSn). When using this mode, the address and data are generally not muxed (HB8MODE field in the EPIHB8CFG register is 0x1). However, if address and data muxing is needed, the WR signal (EPI0S29) and the RD signal (EPI0S28) can be used to latch the address when CSn is low. 0x2 Dual CSn Configuration EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map. This configuration can be used for a RAM bank split between 2 devices as well as when using both an external RAM and an external peripheral. 0x3 ALE with Dual CSn Configuration EPI0S30 is used as address latch (ALE), EPI0S27 is used as CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map. 23:22 reserved RO 0x0 21 WRHIGH R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CS1n WRITE Strobe Polarity Value Description 20 RDHIGH R/W 0 1 The WRITE strobe for CS1n accesses is WR (active High). 0 The WRITE strobe for CS1n accesses is WRn (active Low). CS1n READ Strobe Polarity Value Description 19:8 reserved RO 0x000 1 The READ strobe for CS1n accesses is RD (active High). 0 The READ strobe for CS1n accesses is RDn (active Low). Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 506 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 7:6 WRWS R/W 0x0 Description CS1n Write Wait States This field adds wait states to the data phase of CS1n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. Value Description 0x0 No wait states. 0x1 1 wait state. 0x2 2 wait states. 0x3 3 wait states. This field is used in conjunction with the EPIBAUD register. 5:4 RDWS R/W 0x0 CS1n Read Wait States This field adds wait states to the data phase of CS1n accesses (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. Value Description 0x0 No wait states. 0x1 1 wait state. 0x2 2 wait states. 0x3 3 wait states. This field is used in conjunction with the EPIBAUD register. 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 507 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 8: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIHB16CFG2, the MODE field must be 0x3. This register is used to configure operation while in Host-Bus 16 mode. Note that this register is reset when the MODE field in the EPICFG register is changed. If another mode is selected and the Host-Bus 16 mode is selected again, the values must be reinitialized. EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2) Base 0x400D.0000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 WORD Type Reset 29 28 27 reserved 26 25 CSBAUD 24 R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 15 14 13 12 11 10 9 8 7 RO 0 RO 0 RO 0 RO 0 22 reserved reserved Type Reset 23 CSCFG 21 RO 0 RO 0 Bit/Field Name Type Reset 31 WORD R/W 0 RO 0 R/W 0 19 18 17 16 reserved RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 RO 0 RO 0 WRWS RO 0 20 WRHIGH RDHIGH R/W 0 RDWS R/W 0 R/W 0 reserved RO 0 RO 0 Description Word Access Mode By default, the EPI controller uses data bits [15:0] for Host-Bus 16 accesses. When using Word Access mode, the EPI controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:16]. When WORD is set, long variables can be used in C programs. Value Description 30:27 reserved RO 0x0 26 CSBAUD R/W 0 0 Word Access mode is disabled. 1 Word Access mode is enabled. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Chip Select Baud Rate Value Description 0 Same Baud Rate Both CS0n and CS1n use the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register. 1 Different Baud Rates CS0n uses the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register. CS1n uses the baud rate defined by the COUNT1 field in the EPIBAUD register. 508 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 25:24 CSCFG R/W 0x0 Description Chip Select Configuration This field controls the chip select options, including an ALE format, a single chip select, two chip selects, and an ALE combined with two chip selects. Value Description 0x0 ALE Configuration EPI0S30 is used as an address latch (ALE). When using this mode, the address and data should be muxed (HB16MODE field in the EPIHB16CFG register should be configured to 0x0). If needed, the address can be latched by external logic. 0x1 CSn Configuration EPI0S30 is used as a Chip Select (CSn). When using this mode, the address and data should not be muxed (HB816MODE field in the EPIHB16CFG register should be configured to 0x1). In this mode, the WR signal (EPI0S29) and the RD signal (EPI0S28) are used to latch the address when CSn is low. 0x2 Dual CSn Configuration EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map. This configuration can be used for a RAM bank split between 2 devices as well as when using both an external RAM and an external peripheral. 0x3 ALE with Dual CSn Configuration EPI0S30 is used as address latch (ALE), EPI0S27 is used as CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map. 23:22 reserved RO 0x0 21 WRHIGH R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CS1n WRITE Strobe Polarity Value Description 20 RDHIGH R/W 0 1 The WRITE strobe for CS1n accesses is WR (active High). 0 The WRITE strobe for CS1n accesses is WRn (active Low). CS1n READ Strobe Polarity Value Description 19:8 reserved RO 0x000 1 The READ strobe for CS1n accesses is RD (active High). 0 The READ strobe for CS1n accesses is RDn (active Low). Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 509 Texas Instruments-Production Data External Peripheral Interface (EPI) Bit/Field Name Type Reset 7:6 WRWS R/W 0x0 Description CS1n Write Wait States This field adds wait states to the data phase of CS1n accesses (the address phase is not affected). The effect is to delay the rising edge of WRn (or the falling edge of WR). Each wait state adds 2 EPI clock cycles to the access time. Value Description 0x0 No wait states. 0x1 1 wait state. 0x2 2 wait states. 0x3 3 wait states. This field is used in conjunction with the EPIBAUD register. 5:4 RDWS R/W 0x0 CS1n Read Wait States This field adds wait states to the data phase of CS1n accesses (the address phase is not affected). The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD). Each wait state adds 2 EPI clock cycles to the access time. Value Description 0x0 No wait states. 0x1 1 wait state. 0x2 2 wait states. 0x3 3 wait states. This field is used in conjunction with the EPIBAUD register. 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 510 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 9: EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 Important: The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014. To access EPIGPCFG2, the MODE field must be 0x0. This register is used to configure operation while in General-Purpose mode. Note that this register is reset when the MODE field in the EPICFG register is changed. If another mode is selected and the General-Purpose mode is selected again, the values must be reinitialized. EPI General-Purpose Configuration 2 (EPIGPCFG2) Base 0x400D.0000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 WORD Type Reset 23 22 21 20 19 18 17 16 reserved R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31 WORD R/W 0x0 RO 0 Description Word Access Mode By default, the EPI controller uses data bits [7:0] when the DSIZE field in the EPIGPCFG register is 0x0; data bits [15:0] when the DSIZE field is 0x1; data bits [23:0] when the DSIZE field is 0x2; and data bits [31:0] when the DSIZE field is 0x3. When using Word Access mode, the EPI controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:8] for DSIZE=0x0 and bits [31:16] for DSIZE=0x1. For DSIZE=0x2 or 0x3, this bit must be clear. Value Description 30:0 reserved RO 0x000.0000 0 Word Access mode is disabled. 1 Word Access mode is enabled. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 511 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 10: EPI Address Map (EPIADDRMAP), offset 0x01C This register enables address mapping. The EPI controller can directly address memory and peripherals. In addition, the EPI controller supports address mapping to allow indirect accesses in the External RAM and External Peripheral areas. If the external device is a peripheral, including a FIFO or a directly addressable device, the EPSZ and EPADR bit fields should be configured for the address space. If the external device is SDRAM, SRAM, or NOR Flash memory, the ERADR and ERSZ bit fields should be configured for the address space. If one of the Dual-Chip-Select modes is selected (CSCFG=0x2 or 0x3 in the EPIHBnCFG2 register), both chip selects can share the peripheral or the memory space, or one chip select can use the peripheral space and the other can use the memory space. If the EPADR field is not 0x0 and the ERADR field is 0x0, then the address specified by EPADR is used for both chip selects, with CS0n being asserted when the MSB of the address range is 0 and CS1n being asserted when the MSB of the address range is 1. If the ERADR field is not 0x0 and the EPADR field is 0x0, then the address specified by ERADR is used for both chip selects, with the MSB performing the same delineation. If both the EPADR and the ERADR are not 0x0, then CS0n is asserted for the address range defined by EPADR and CS1n is asserted for the address range defined by ERADR. EPI Address Map (EPIADDRMAP) Base 0x400D.0000 Offset 0x01C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 EPSZ RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:6 EPSZ R/W 0x0 RO 0 R/W 0 EPADR R/W 0 R/W 0 R/W 0 ERSZ R/W 0 ERADR R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Peripheral Size This field selects the size of the external peripheral. If the size of the external peripheral is larger, a bus fault occurs. If the size of the external peripheral is smaller, it wraps (upper address bits unused). Note: When not using byte selects in Host-Bus 16, data is accessed on 2-byte boundaries. As a result, the available address space is double the amount shown below. Value Description 0x0 256 bytes; lower address range: 0x00 to 0xFF 0x1 64 KB; lower address range: 0x0000 to 0xFFFF 0x2 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF 0x3 256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF 512 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 5:4 EPADR R/W 0x0 Description External Peripheral Address This field selects address mapping for the external peripheral area. Value Description 3:2 ERSZ R/W 0x0 0x0 Not mapped 0x1 At 0xA000.0000 0x2 At 0xC000.0000 0x3 reserved External RAM Size This field selects the size of mapped RAM. If the size of the external memory is larger, a bus fault occurs. If the size of the external memory is smaller, it wraps (upper address bits unused): Value Description 1:0 ERADR R/W 0x0 0x0 256 bytes; lower address range: 0x00 to 0xFF 0x1 64 KB; lower address range: 0x0000 to 0xFFFF 0x2 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF 0x3 256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF External RAM Address Selects address mapping for external RAM area: Value Description 0x0 Not mapped 0x1 At 0x6000.0000 0x2 At 0x8000.0000 0x3 reserved July 24, 2011 513 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 11: EPI Read Size 0 (EPIRSIZE0), offset 0x020 Register 12: EPI Read Size 1 (EPIRSIZE1), offset 0x030 This register selects the size of transactions when performing non-blocking reads with the EPIRPSTDn registers. This size affects how the external address is incremented. The SIZE field must match the external data width as configured in the EPIHBnCFG or EPIGPCFG register if the WORD bit is clear in the EPIHBnCFG2 or EPIGPCFG2 register. If the WORD bit is set, the SIZE field must be greater than or equal to the external data width. SDRAM mode uses a 16-bit data interface. If SIZE is 0x1, data is returned on the least significant bits (D[7:0]), and the remaining bits D[31:8] are all zeros, therefore the data on bits D[15:8] is lost. If SIZE is 0x2, data is returned on the least significant bits (D[15:0]), and the remaining bits D[31:16] are all zeros. Note that changing this register while a read is active has an unpredictable effect. EPI Read Size 0 (EPIRSIZE0) Base 0x400D.0000 Offset 0x020 Type R/W, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1:0 SIZE R/W 0x3 0 SIZE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Current Size Value Description 0x0 reserved 0x1 Byte (8 bits) 0x2 Half-word (16 bits) 0x3 Word (32 bits) 514 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 13: EPI Read Address 0 (EPIRADDR0), offset 0x024 Register 14: EPI Read Address 1 (EPIRADDR1), offset 0x034 This register holds the current address value. When performing non-blocking reads via the EPIRPSTDn registers, this register’s value forms the address (when used by the mode). That is, when an EPIRPSTDn register is written with a non-0 value, this register is used as the first address. After each read, it is incremented by the size specified by the corresponding EPIRSIZEn register. Thus at the end of a read, this register contains the next address for the next read. For example, if the last read was 0x20, and the size is word, then the register contains 0x24. When a non-blocking read is cancelled, this register contains the next address that would have been read had it not been cancelled. For example, if reading by bytes and 0x103 had been read but not 0x104, this register contains 0x104. In this manner, the system can determine the number of values in the NBRFIFO to drain. Note that changing this register while a read is active has an unpredictable effect due to race condition. EPI Read Address 0 (EPIRADDR0) Base 0x400D.0000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 reserved Type Reset 22 21 20 19 18 17 16 ADDR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ADDR Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:29 reserved RO 0x0 28:0 ADDR R/W 0x000.0000 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Current Address Next address to read. July 24, 2011 515 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 This register sets up a non-blocking read via the external interface. A non-blocking read is started by writing to this register with the count (other than 0). Clearing this register terminates an active non-blocking read as well as cancelling any that are pending. This register should always be cleared before writing a value other than 0; failure to do so can cause improper operation. Note that both NBR channels can be enabled at the same time, but NBR channel 0 has the highest priority and channel 1 does not start until channel 0 is finished. The first address is based on the corresponding EPIRADDRn register. The address register is incremented by the size specified by the EPIRSIZEn register after each read. If the size is less than a word, only the least significant bits of data are filled into the NBRFIFO; the most significant bits are cleared. Note that all three registers may be written using one STM instruction, such as with a structure copy in C/C++. The data may be read from the EPIREADFIFO register after the read cycle is completed. The interrupt mechanism is normally used to trigger the FIFO reads via ISR or μDMA. If the countdown has not reached 0 and the NBRFIFO is full, the external interface waits until a NBRFIFO entry becomes available to continue. Note: if a blocking read or write is performed through the address mapped area (at 0x6000.0000 through 0xDFFF.FFFF), any current non-blocking read is paused (at the next safe boundary), and the blocking request is inserted. After completion of any blocking reads or writes, the non-blocking reads continue from where they were paused. The other way to read data is via the address mapped locations (see the EPIADDRMAP register), but this method is blocking (core or μDMA waits until result is returned). To cancel a non-blocking read, clear this register. To make sure that all values read are drained from the NBRFIFO, the EPISTAT register must be consulted to be certain that bits NBRBUSY and ACTIVE are cleared. One of these registers should not be cleared until either the other EPIRPSTDn register becomes active or the external interface is not busy. At that point, the corresponding EPIRADDRn register indicates how many values were read. EPI Non-Blocking Read Data 0 (EPIRPSTD0) Base 0x400D.0000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 15 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 14 13 12 11 10 9 8 7 reserved Type Reset RO 0 RO 0 POSTCNT RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:13 reserved RO 0x0000.0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 516 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 12:0 POSTCNT R/W 0x000 Post Count A write of a non-zero value starts a read operation for that count. Note that it is the software's responsibility to handle address wraparound. Reading this register provides the current count. A write of 0 cancels a non-blocking read (whether active now or pending). Prior to writing a non-zero value, this register must first be cleared. July 24, 2011 517 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 17: EPI Status (EPISTAT), offset 0x060 This register indicates which non-blocking read register is currently active; it also indicates whether the external interface is busy performing a write or non-blocking read (it cannot be performing a blocking read, as the bus would be blocked and as a result, this register could not be accessed). This register is useful to determining which non-blocking read register is active when both are loaded with values and when implementing sequencing or sharing. This register is also useful when canceling non-blocking reads, as it shows how many values were read by the canceled side. EPI Status (EPISTAT) Base 0x400D.0000 Offset 0x060 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset reserved Type Reset RO 0 CELOW XFFULL XFEMPTY INITSEQ RO 0 Bit/Field Name Type Reset 31:10 reserved RO 0x0000.00 9 CELOW RO 0 RO 0 RO 0 WBUSY NBRBUSY RO 0 RO 0 RO 0 reserved RO 0 RO 0 ACTIVE RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Enable Low This bit provides information on the clock status when in general-purpose mode and the RDYEN bit is set. Value Description 1 The external device is gating the clock (iRDY is low). Attempts to read or write in this situation are stalled until the clock is enabled or the counter times out as specified by the MAXWAIT field. 0 8 XFFULL RO 0 The external device is not gating the clock. External FIFO Full This bit provides information on the XFIFO when in the FIFO sub-mode of the Host Bus n mode with the XFFEN bit set in the EPIHBnCFG register. The EPI0S26 signal reflects the status of this bit. Value Description 1 The XFIFO is signaling as full (the FIFO full signal is high). Attempts to write in this case are stalled until the XFIFO full signal goes low or the counter times out as specified by the MAXWAIT field. 0 The external device is not gating the clock. 518 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 7 XFEMPTY RO 0 Description External FIFO Empty This bit provides information on the XFIFO when in the FIFO sub-mode of the Host Bus n mode with the XFEEN bit set in the EPIHBnCFG register. The EPI0S27 signal reflects the status of this bit. Value Description 1 The XFIFO is signaling as empty (the FIFO empty signal is high). Attempts to read in this case are stalled until the XFIFO empty signal goes low or the counter times out as specified by the MAXWAIT field. 0 6 INITSEQ RO 0 The external device is not gating the clock. Initialization Sequence Value Description 1 The SDRAM interface is running through the wakeup period (greater than 100 μs). If an attempt is made to read or write the SDRAM during this period, the access is held off until the wakeup period is complete. 0 5 WBUSY RO 0 The SDRAM interface is not in the wakeup period. Write Busy Value Description 4 NBRBUSY RO 0 1 The external interface is performing a write. 0 The external interface is not performing a write. Non-Blocking Read Busy Value Description 3:1 reserved RO 0x0 0 ACTIVE RO 0 1 The external interface is performing a non-blocking read, or if the non-blocking read is paused due to a write. 0 The external interface is not performing a non-blocking read. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Register Active Value Description 1 The EPIRPSTD1 register is active. 0 If NBRBUSY is set, the EPIRPSTD0 register is active. If the NBRBUSY bit is clear, then neither EPIRPSTDx register is active. July 24, 2011 519 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 18: EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C This register returns the number of values in the NBRFIFO (the data in the NBRFIFO can be read via the EPIREADFIFO register). A race is possible, but that only means that more values may come in after this register has been read. EPI Read FIFO Count (EPIRFIFOCNT) Base 0x400D.0000 Offset 0x06C Type RO, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO - reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 COUNT RO - COUNT RO - RO - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Count Number of filled entries in the NBRFIFO. 520 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 19: EPI Read FIFO (EPIREADFIFO), offset 0x070 Register 20: EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 Register 21: EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 Register 22: EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C Register 23: EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 Register 24: EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 Register 25: EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 Register 26: EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C Important: This register is read-sensitive. See the register description for details. This register returns the contents of the NBRFIFO or 0 if the NBRFIFO is empty. Each read returns the data that is at the top of the NBRFIFO, and then empties that value from the NBRFIFO. The alias registers can be used with the LDMIA instruction for more efficient operation (for up to 8 registers). See Cortex™-M3 Instruction Set Technical User's Manual for more information on the LDMIA instruction. EPI Read FIFO (EPIREADFIFO) Base 0x400D.0000 Offset 0x070 Type RO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - DATA Type Reset DATA Type Reset Bit/Field Name Type Reset Description 31:0 DATA RO - Reads Data This field contains the data that is at the top of the NBRFIFO. After being read, the NBRFIFO entry is removed. July 24, 2011 521 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 27: EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 This register allows selection of the FIFO levels which trigger an interrupt to the interrupt controller or, more efficiently, a DMA request to the μDMA. The NBRFIFO select triggers on fullness such that it triggers on match or above (more full). The WFIFO triggers on emptiness such that it triggers on match or below (less entries). It should be noted that the FIFO triggers are not identical to other such FIFOs in Stellaris peripherals. In particular, empty and full triggers are provided to avoid wait states when using blocking operations. The settings in this register are only meaningful if the μDMA is active or the interrupt is enabled. Additionally, this register allows protection against writes stalling and notification of performing blocking reads which stall for extra time due to preceding writes. The two functions behave in a non-orthogonal way because read and write are not orthogonal. The write error bit configures the system such that an attempted write to an already full WFIFO abandons the write and signals an error interrupt to prevent accidental latencies due to stalling writes. The read error bit configures the system such that after a read has been stalled due to any preceding writes in the WFIFO, the error interrupt is generated. Note that the excess stall is not prevented, but an interrupt is generated after the fact to notify that it has happened. EPI FIFO Level Selects (EPIFIFOLVL) Base 0x400D.0000 Offset 0x200 Type R/W, reset 0x0000.0033 31 30 29 28 27 26 25 24 23 22 21 20 19 18 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 WRFIFO RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 RO 0 RO 0 3 2 RO 0 16 RSERR R/W 0 R/W 0 1 0 RDFIFO reserved R/W 1 17 WFERR R/W 0 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:18 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 17 WFERR R/W 0 Write Full Error Value Description 1 This bit enables the Write Full error interrupt (WTFULL in the EPIIC register) to be generated when a write is attempted and the WFIFO is full. The write stalls until a WFIFO entry becomes available. 0 The Write Full error interrupt is disabled. Writes are stalled when the WFIFO is full until a space becomes available but an error is not generated. Note that the Cortex-M3 write buffer may hide that stall if no other memory transactions are attempted during that time. 522 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 16 RSERR R/W 0 Description Read Stall Error Value Description 1 This bit enables the Read Stalled error interrupt (RSTALL in the EPIIC register) to be generated when a read is attempted and the WFIFO is not empty. The read is still stalled during the time the WFIFO drains, but this error notifies the application that this excess delay has occurred. 0 The Read Stalled error interrupt is disabled. Reads behave as normal and are stalled until any preceding writes have completed and the read has returned a result. Note that the configuration of this bit has no effect on non-blocking reads. 15:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:4 WRFIFO R/W 0x3 Write FIFO This field configures the trigger point for the WFIFO. Value Description 0x0 Trigger when there are 1 to 4 spaces available in the WFIFO. 0x1 reserved 0x2 Trigger when there are 1 to 3 spaces available in the WFIFO. 0x3 Trigger when there are 1 to 2 spaces available in the WFIFO. 0x4 Trigger when there is 1 space available in the WFIFO. 0x5-0x7 reserved 3 reserved RO 0 2:0 RDFIFO R/W 0x3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Read FIFO This field configures the trigger point for the NBRFIFO. Value Description 0x0 reserved 0x1 Trigger when there are 1 or more entries in the NBRFIFO. 0x2 Trigger when there are 2 or more entries in the NBRFIFO. 0x3 Trigger when there are 4 or more entries in the NBRFIFO. 0x4 Trigger when there are 6 or more entries in the NBRFIFO. 0x5 Trigger when there are 7 or more entries in the NBRFIFO. 0x6 Trigger when there are 8 entries in the NBRFIFO. 0x7 reserved July 24, 2011 523 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 This register contains the number of slots currently available in the WFIFO. This register may be used for polled writes to avoid stalling and for blocking reads to avoid excess stalling (due to undrained writes). An example use for writes may be: for (idx = 0; idx < cnt; idx++) { while (EPIWFIFOCNT == 0) ; *ext_ram = *mydata++; } The above code ensures that writes to the address mapped location do not occur unless the WFIFO has room. Although polling makes the code wait (spinning in the loop), it does not prevent interrupts being serviced due to bus stalling. EPI Write FIFO Count (EPIWFIFOCNT) Base 0x400D.0000 Offset 0x204 Type RO, reset 0x0000.0004 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 WTAV RO 0x4 WTAV RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Available Write Transactions The number of write transactions available in the WFIFO. When clear, a write is stalled waiting for a slot to become free (from a preceding write completing). 524 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 29: EPI Interrupt Mask (EPIIM), offset 0x210 This register is the interrupt mask set or clear register. For each interrupt source (read, write, and error), a mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller; a mask value of 0 prevents the interrupt source from triggering an interrupt. Note that interrupt masking has no effect on μDMA, which operates off the raw source of the read and write interrupts. EPI Interrupt Mask (EPIIM) Base 0x400D.0000 Offset 0x210 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 WRIM RDIM ERRIM R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 WRIM R/W 0 Write Interrupt Mask Value Description 1 RDIM R/W 0 1 WRRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller. 0 WRRIS in the EPIRIS register is masked and does not cause an interrupt. Read Interrupt Mask Value Description 0 ERRIM R/W 0 1 RDRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller. 0 RDRIS in the EPIRIS register is masked and does not cause an interrupt. Error Interrupt Mask Value Description 1 ERRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller. 0 ERRIS in the EPIRIS register is masked and does not cause an interrupt. July 24, 2011 525 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 30: EPI Raw Interrupt Status (EPIRIS), offset 0x214 This register is the raw interrupt status register. On a read, it gives the current state of each interrupt source. A write has no effect. Note that raw status for read and write is set or cleared based on FIFO fullness as controlled by EPIFIFOLVL. Raw status for error is held until the error is cleared by writing to the EPIIC register. EPI Raw Interrupt Status (EPIRIS) Base 0x400D.0000 Offset 0x214 Type RO, reset 0x0000.0004 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 WRRIS RDRIS ERRRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 WRRIS RO 1 Write Raw Interrupt Status Value Description 1 The number of available entries in the WFIFO is within the range specified by the trigger level (the WRFIFO field in the EPIFIFOLVL register). 0 The number of available entries in the WFIFO is above the range specified by the trigger level. This bit is cleared when the level in the WFIFO is above the trigger point programmed by the WRFIFO field. 1 RDRIS RO 0 Read Raw Interrupt Status Value Description 1 The number of valid entries in the NBRFIFO is within the range specified by the trigger level (the RDFIFO field in the EPIFIFOLVL register). 0 The number of valid entries in the NBRFIFO is below the range specified by the trigger level. This bit is cleared when the level in the NBRFIFO is below the trigger point programmed by the RDFIFO field. 526 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 ERRRIS RO 0 Description Error Raw Interrupt Status The error interrupt occurs in the following situations: ■ WFIFO Full. For a full WFIFO to generate an error interrupt, the WFERR bit in the EPIFIFOLVL register must be set. ■ Read Stalled. For a stalled read to generate an error interrupt, the RSERR bit in the EPIFIFOLVL register must be set. ■ Timeout. If the MAXWAIT field in the EPIGPCFG register is configured to a value other than 0, a timeout error occurs when iRDY or XFIFO not-ready signals hold a transaction for more than the count in the MAXWAIT field. Value Description 1 A WFIFO Full, a Read Stalled, or a Timeout error has occurred. 0 An error has not occurred. To determine which error occurred, read the status of the EPI Error Interrupt Status and Clear (EPIEISC) register. This bit is cleared by writing a 1 to the bit in the EPIEISC register that caused the interrupt. July 24, 2011 527 Texas Instruments-Production Data External Peripheral Interface (EPI) Register 31: EPI Masked Interrupt Status (EPIMIS), offset 0x218 This register is the masked interrupt status register. On read, it gives the current state of each interrupt source (read, write, and error) after being masked via the EPIIM register. A write has no effect. The values returned are the ANDing of the EPIIM and EPIRIS registers. If a bit is set in this register, the interrupt is sent to the interrupt controller. EPI Masked Interrupt Status (EPIMIS) Base 0x400D.0000 Offset 0x218 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 WRMIS RDMIS ERRMIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 WRMIS RO 0 Write Masked Interrupt Status Value Description 1 RDMIS RO 0 1 The number of available entries in the WFIFO is within the range specified by the trigger level (the WRFIFO field in the EPIFIFOLVL register) and the WRIM bit in the EPIIM register is set, triggering an interrupt to the interrupt controller. 0 The number of available entries in the WFIFO is above the range specified by the trigger level or the interrupt is masked. Read Masked Interrupt Status Value Description 0 ERRMIS RO 0 1 The number of valid entries in the NBRFIFO is within the range specified by the trigger level (the RDFIFO field in the EPIFIFOLVL register) and the RDIM bit in the EPIIM register is set, triggering an interrupt to the interrupt controller. 0 The number of valid entries in the NBRFIFO is below the range specified by the trigger level or the interrupt is masked. Error Masked Interrupt Status Value Description 1 A WFIFO Full, a Read Stalled, or a Timeout error has occurred and the ERIM bit in the EPIIM register is set, triggering an interrupt to the interrupt controller. 0 An error has not occurred or the interrupt is masked. 528 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 32: EPI Error Interrupt Status and Clear (EPIEISC), offset 0x21C This register is used to clear a pending error interrupt. If any of these bits are set, the ERRRIS bit in the EPIRIS register is set, and an EPI controller error is sent to the interrupt controller if the ERIM bit in the EPIIM register is set. Clearing any defined bit has no effect; setting a bit clears the error source and the raw error returns to 0. Note that writing to this register and reading back immediately (pipelined by the processor) returns the old register contents. One cycle is needed between write and read. EPI Error Interrupt Status and Clear (EPIEISC) Base 0x400D.0000 Offset 0x21C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 WTFULL RSTALL TOUT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 WTFULL R/W1C 0 Write FIFO Full Error Value Description 1 The WFERR bit is enabled and a write is stalled due to the WFIFO being full. 0 The WFERR bit is not enabled or no writes are stalled. Writing a 1 to this bit clears it and the WFERR bit in the EPIFIFOLVL register. 1 RSTALL R/W1C 0 Read Stalled Error Value Description 1 The RSERR bit is enabled and a pending read is stalled due to writes in the WFIFO. 0 The RSERR bit is not enabled pr no pending reads are stalled. Writing a 1 to this bit clears it and the RSERR bit in the EPIFIFOLVL register. July 24, 2011 529 Texas Instruments-Production Data External Peripheral Interface (EPI) Bit/Field Name Type Reset 0 TOUT R/W1C 0 Description Timeout Error This bit is the timeout error source. The timeout error occurs when the iRDY or XFIFO not-ready signals hold a transaction for more than the count in theMAXWAIT field (when not 0). Value Description 1 A timeout error has occurred. 0 No timeout error has occurred. Writing a 1 to bit this clears it. 530 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 11 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. ® The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM block provides two 16-bit timers/counters (referred to as Timer A and Timer B) that can be configured to operate independently as timers or event counters, or concatenated to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger μDMA transfers. In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events. The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer resources include the System Timer (SysTick) (see 96). The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional options: ■ Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 16-bit input-edge count- or time-capture modes – 16-bit PWM mode with software-programmable output inversion of the PWM signal ■ Count up or down ■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events ■ ADC event trigger ■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding RTC mode) ■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each timer – Burst request generated on timer interrupt 11.1 Block Diagram In the block diagram, the specific Capture Compare PWM (CCP) pins available depend on the Stellaris device. See Table 11-1 on page 532 for the available CCP pins and their timer assignments. July 24, 2011 531 Texas Instruments-Production Data General-Purpose Timers Figure 11-1. GPTM Module Block Diagram 0x0000 (Down Counter Modes) 0xFFFF (Up Counter Modes) Timer A Free-Running Value Timer A Control GPTMTAPMR GPTMTAPR TA Comparator GPTMTAMATCHR Clock / Edge Detect GPTMTAILR Interrupt / Config Timer A Interrupt GPTMTAMR GPTMTAR En GPTMCTL GPTMTAV GPTMIMR Timer B Interrupt 32 KHz or Even CCP Pin GPTMCFG RTC Divider GPTMRIS GPTMTBV GPTMMIS GPTMICR GPTMTBR En Clock / Edge Detect Timer B Control GPTMTBMR GPTMTBILR Timer B Free-Running Value Odd CCP Pin TB Comparator GPTMTBMATCHR GPTMTBPR GPTMTBPMR 0x0000 (Down Counter Modes) 0xFFFF (Up Counter Modes) System Clock Table 11-1. Available CCP Pins Timer Timer 0 Timer 1 11.2 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin TimerA CCP0 - TimerB - CCP1 TimerA CCP2 - TimerB - CCP3 Timer 2 TimerA CCP4 - TimerB - CCP5 Timer 3 TimerA CCP6 - TimerB - CCP7 Signal Description The following table lists the external signals of the GP Timer module and describes the function of each. The GP Timer signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these GP Timer signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 424) should be set to choose the GP Timer function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 442) to assign the GP Timer signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 400. 532 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 11-2. Signals for General-Purpose Timers (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP0 13 22 23 39 58 66 72 91 97 PD3 (4) PC7 (4) PC6 (6) PJ2 (9) PF4 (1) PB0 (1) PB2 (5) PB5 (4) PD4 (1) I/O TTL Capture/Compare/PWM 0. CCP1 24 25 34 43 67 90 96 100 PC5 (1) PC4 (9) PA6 (2) PF6 (1) PB1 (4) PB6 (1) PE3 (1) PD7 (3) I/O TTL Capture/Compare/PWM 1. CCP2 6 11 25 46 67 75 91 95 98 PE4 (6) PD1 (10) PC4 (5) PF5 (1) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) I/O TTL Capture/Compare/PWM 2. CCP3 6 23 24 35 41 61 72 74 97 PE4 (1) PC6 (1) PC5 (5) PA7 (7) PG4 (1) PF1 (10) PB2 (4) PE0 (3) PD4 (2) I/O TTL Capture/Compare/PWM 3. CCP4 22 25 35 42 95 98 PC7 (1) PC4 (6) PA7 (2) PF7 (1) PE2 (1) PD5 (2) I/O TTL Capture/Compare/PWM 4. CCP5 5 12 25 36 40 90 91 PE5 (1) PD2 (4) PC4 (1) PG7 (8) PG5 (1) PB6 (6) PB5 (2) I/O TTL Capture/Compare/PWM 5. CCP6 10 12 75 86 91 PD0 (6) PD2 (2) PE1 (5) PH0 (1) PB5 (3) I/O TTL Capture/Compare/PWM 6. July 24, 2011 533 Texas Instruments-Production Data General-Purpose Timers Table 11-2. Signals for General-Purpose Timers (100LQFP) (continued) Pin Name CCP7 Pin Number Pin Mux / Pin Assignment 11 13 85 90 96 PD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) a Pin Type Buffer Type I/O TTL Description Capture/Compare/PWM 7. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 11-3. Signals for General-Purpose Timers (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP0 H1 L2 M2 K6 L9 E12 A11 B7 B5 PD3 (4) PC7 (4) PC6 (6) PJ2 (9) PF4 (1) PB0 (1) PB2 (5) PB5 (4) PD4 (1) I/O TTL Capture/Compare/PWM 0. CCP1 M1 L1 L6 M8 D12 A7 B4 A2 PC5 (1) PC4 (9) PA6 (2) PF6 (1) PB1 (4) PB6 (1) PE3 (1) PD7 (3) I/O TTL Capture/Compare/PWM 1. CCP2 B2 G2 L1 L8 D12 A12 B7 A4 C6 PE4 (6) PD1 (10) PC4 (5) PF5 (1) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) I/O TTL Capture/Compare/PWM 2. CCP3 B2 M2 M1 M6 K3 H12 A11 B11 B5 PE4 (1) PC6 (1) PC5 (5) PA7 (7) PG4 (1) PF1 (10) PB2 (4) PE0 (3) PD4 (2) I/O TTL Capture/Compare/PWM 3. CCP4 L2 L1 M6 K4 A4 C6 PC7 (1) PC4 (6) PA7 (2) PF7 (1) PE2 (1) PD5 (2) I/O TTL Capture/Compare/PWM 4. 534 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 11-3. Signals for General-Purpose Timers (108BGA) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP5 B3 H2 L1 C10 M7 A7 B7 PE5 (1) PD2 (4) PC4 (1) PG7 (8) PG5 (1) PB6 (6) PB5 (2) I/O TTL Capture/Compare/PWM 5. CCP6 G1 H2 A12 C9 B7 PD0 (6) PD2 (2) PE1 (5) PH0 (1) PB5 (3) I/O TTL Capture/Compare/PWM 6. CCP7 G2 H1 C8 A7 B4 PD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) I/O TTL Capture/Compare/PWM 7. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 11.3 Functional Description The main components of each GPTM block are two free-running up/down counters (referred to as Timer A and Timer B), two match registers, two prescaler match registers, two shadow registers, and two load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Timer A and Timer B can be used individually, in which case they have a 16-bit counting range. In addition, Timer A and Timer B can be concatenated to provide a 32-bit counting range. Note that the prescaler can only be used when the timers are used individually. The available modes for each GPTM block are shown in Table 11-4 on page 535. Note that when counting down, the prescaler acts as a true prescaler and contains the least-significant bits of the count. When counting up, the prescaler acts as a timer extension and holds the most-significant bits of the count. Table 11-4. General-Purpose Timer Capabilities Mode a Timer Use Count Direction Counter Size Prescaler Size Individual Up or Down 16-bit 8-bit Concatenated Up or Down 32-bit - Individual Up or Down 16-bit 8-bit Concatenated Up or Down 32-bit - RTC Concatenated Up 32-bit - Edge Count Individual Down 16-bit 8-bit Edge Time Individual Down 16-bit - PWM Individual Down 16-bit - One-shot Periodic a. The prescaler is only available when the timers are used individually Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 547), the GPTM Timer A Mode (GPTMTAMR) register (see page 548), and the GPTM Timer B Mode (GPTMTBMR) register (see page 550). When in one of the concatentated modes, Timer A and Timer July 24, 2011 535 Texas Instruments-Production Data General-Purpose Timers B can only operate in one mode. However, when configured in an individual mode, Timer A and Timer B can be independently configured in any combination of the individual modes. 11.3.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all 1s, along with their corresponding load registers: the GPTM Timer A Interval Load (GPTMTAILR) register (see page 565) and the GPTM Timer B Interval Load (GPTMTBILR) register (see page 566) and shadow registers: the GPTM Timer A Value (GPTMTAV) register (see page 575) and the GPTM Timer B Value (GPTMTBV) register (see page 576). The prescale counters are initialized to 0x00: the GPTM Timer A Prescale (GPTMTAPR) register (see page 569) and the GPTM Timer B Prescale (GPTMTBPR) register (see page 570). 11.3.2 Timer Modes This section describes the operation of the various timer modes. When using Timer A and Timer B in concatenated mode, only the Timer A control and status bits must be used; there is no need to use Timer B control and status bits. The GPTM is placed into individual mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 547). In the following sections, the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer B function. The prescaler is only available in the 16-bit one-shot, periodic, and input edge count timer mode. Note that when counting down, the prescaler acts as a true prescaler and contains the least-significant bits of the count. When counting up, the prescaler acts as a timer extension and holds the most-significant bits of the count. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count mode is the value in the GPTM Timer n Match (GPTMTnMATCH) and the optional GPTM Timer n Prescale Match (GPTMTnPMR) registers. 11.3.2.1 One-Shot/Periodic Timer Mode The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTM Timer n Mode (GPTMTnMR) register (see page 548). The timer is configured to count up or down using the TnCDIR bit in the GPTMTnMR register. When software sets the TnEN bit in the GPTM Control (GPTMCTL) register (see page 552), the timer begins counting up from 0x0 or down from its preloaded value. Alternatively, if the TnWOT bit is set in the GPTMTnMR register, once the TnEN bit is set, the timer waits for a trigger to begin counting (see the section called “Wait-for-Trigger Mode” on page 537). When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start value from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is counting up and it reaches the timeout event (the value in the GPTMTnILR and the GPTMTnPR registers), the timer reloads with 0x0. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, the timer starts counting again on the next cycle. In periodic, snap-shot mode (TnSNAPS bit in the GPTMTnMR register is set), the actual free-running value of the timer at the time-out event is loaded into the GPTMTnR register. In this manner, software can determine the time elapsed from the interrupt assertion to the ISR entry. In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the time-out event. The GPTM sets the TnTORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 557), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 563). If the timeout interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register (see page 555), the GPTM also sets the TnTOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 560). By setting the TnMIE bit in the GPTMTAMR register, an interrupt 536 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller can also be generated when the Timer value equals the value loaded into the GPTM Timer n Match (GPTMTnMATCH) and GPTM Timer n Prescale Match (GPTMTnPMR) registers. This interrupt has the same status, masking, and clearing functions as the timeout interrupt. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL. The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 344. If software updates the GPTMTnILR register while the counter is counting down, the counter loads the new value on the next clock cycle and continues counting down from the new value. If software updates the GPTMTnILR register while the counter is counting up, the timeout event is changed on the next cycle to the new value. If software updates the GPTM Timer n Value (GPTMTnV) register while the counter is counting up or down, the counter loads the new value on the next clock cycle and continues counting from the new value. If software updates the GPTMTnMATCHR register while the counter is counting, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. The following table shows a variety of configurations for a 16-bit free-running timer while using the prescaler. All values assume an 80-MHz clock with Tc=12.5 ns (clock period). Table 11-5. 16-Bit Timer With Prescaler Configurations a Prescale #Clock (Tc) Max Time Units 00000000 1 0.8192 ms 00000001 2 1.6384 ms 00000010 3 2.4576 ms ------------ -- -- -- 11111101 254 208.0768 ms 11111110 255 208.896 ms 11111111 256 209.7152 ms a. Tc is the clock period. Wait-for-Trigger Mode The Wait-for-Trigger mode allows daisy chaining of the timer modules such that once configured, a single timer can initiate mulitple timing events using the Timer triggers. Wait-for-Trigger mode is enabled by setting the TnWOT bit in the GPTMTnMR register. When the TnWOT bit is set, Timer N+1 does not begin counting until the timer in the previous position in the daisy chain (Timer N) reaches its time-out event. The daisy chain is configured such that GPTM1 always follows GPTM0, GPTM2 follows GPTM1, and so on. If Timer A is in 32-bit mode (controlled by the GPTMCFG bit in the GPTMCFG register), it triggers Timer A in the next module. If Timer A is in 16-bit mode, it triggers Timer B in the same module, and Timer B triggers Timer A in the next module. Care must be taken that the TAWOT bit is never set in GPTM0. Figure 11-2 on page 538 shows how the GPTMCFG bit affects the daisy chain. This function is valid for both one-shot and periodic modes. July 24, 2011 537 Texas Instruments-Production Data General-Purpose Timers Figure 11-2. Timer Daisy Chain GP Timer N+1 1 0 GPTMCFG Timer B ADC Trigger Timer B Timer A Timer A ADC Trigger GP Timer N 1 0 GPTMCFG Timer B ADC Trigger Timer B Timer A 11.3.2.2 Timer A ADC Trigger Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers are configured as an up-counter. When RTC mode is selected for the first time after reset, the counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM Timer A Interval Load (GPTMTAILR) register (see page 565). The input clock on a CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1-Hz rate and is passed along to the input of the counter. When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from its preloaded value of 0x1. When the current count value matches the preloaded value in the GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 344. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 11.3.2.3 Input Edge-Count Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. In Edge-Count mode, the timer is configured as a 24-bit down-counter including the optional prescaler with the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR) register and the lower bits in the GPTMTnR register. In this mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of the GPTMTnMR register must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted. 538 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL.The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 344. After the match value is reached, the counter is then reloaded using the value in GPTMTnILR and GPTMTnPR registers, and stopped because the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 11-3 on page 539 shows how Input Edge-Count mode works. In this case, the timer start value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted because the timer automatically clears the TnEN bit after the current count matches the value in the GPTMTnMATCHR register. Figure 11-3. Input Edge-Count Mode Example Timer stops, flags asserted Count Timer reload on next cycle Ignored Ignored 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal 11.3.2.4 Input Edge-Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. The prescaler is not available in 16-Bit Input Edge-Time mode. In Edge-Time mode, the timer is configured as a 16-bit down-counter. In this mode, the timer is initialized to the value loaded in the GPTMTnILRregister. The timer is capable of capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time mode by July 24, 2011 539 Texas Instruments-Production Data General-Purpose Timers setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current timer counter value is captured in the GPTMTnR register and is available to be read by the microcontroller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). The GPTMTnV contains the free-running value of the timer and can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR. In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL.The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 344. After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with the value from the GPTMTnILR register. Figure 11-4 on page 540 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into the GPTMTnR register). Figure 11-4. 16-Bit Input Edge-Time Mode Example Count 0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z Z X Y Time Input Signal 11.3.2.5 PWM Mode Note: The prescaler is not available in 16-Bit PWM mode. The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 16-bit down-counter with a start value (and thus period) defined by the GPTMTnILR register. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x1 or 0x2. 540 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0 state. On the next counter cycle in periodic mode, the counter reloads its start value from the GPTMTnILR register and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTMTnMATCHR register. Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 11-5 on page 541 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMTnILR=0xC350 and the match value is GPTMTnMATCHR=0x411A. Figure 11-5. 16-Bit PWM Mode Example Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 11.3.3 DMA Operation The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs. The arbitration size of the μDMA transfer should be set to the amount of data that should be transferred whenever a timer event occurs. For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of 8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items have been transferred. No other special steps are needed to enable Timers for μDMA operation. Refer to “Micro Direct Memory Access (μDMA)” on page 340 for more details about programming the μDMA controller. July 24, 2011 541 Texas Instruments-Production Data General-Purpose Timers 11.3.4 Accessing Concatenated Register Values The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in the GPTM Configuration (GPTMCFG) register. In both configurations, certain registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 565 ■ GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 566 ■ GPTM Timer A (GPTMTAR) register [15:0], see page 573 ■ GPTM Timer B (GPTMTBR) register [15:0], see page 574 ■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 575 ■ GPTM Timer B Value (GPTMTBV) register [15:0], see page 576 ■ GPTM Timer A Match (GPTMTAMATCHR) register [15:0], see page 567 ■ GPTM Timer B Match (GPTMTBMATCHR) register [15:0], see page 568 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a 32-bit read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] A 32-bit read access to GPTMTAV returns the value: GPTMTBV[15:0]:GPTMTAV[15:0] 11.4 Initialization and Configuration To use a GPTM, the appropriate TIMERn bit must be set in the RCGC1 register (see page 246). If using any CCP pins, the clock to the appropriate GPIO module must be enabled via the RCGC1 register (see page 246). To find out which GPIO port to enable, refer to Table 19-4 on page 848. Configure the PMCn fields in the GPIOPCTL register to assign the CCP signals to the appropriate pins (see page 442 and Table 19-5 on page 854). This section shows module initialization and configuration examples for each of the supported timer modes. 11.4.1 One-Shot/Periodic Timer Mode The GPTM is configured for One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000. 3. Configure the TnMR field in the GPTM Timer n Mode Register (GPTMTnMR): 542 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in the GPTMTnMR register to select whether to capture the value of the free-running timer at time-out, use an external trigger to start counting, configure an additional trigger or interrupt, and count up or down. 5. Load the start value into the GPTM Timer n Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTMCTL register to enable the timer and start counting. 8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear Register (GPTMICR). If the TnMIE bit in the GPTMTnMR register is set, the RTCRIS bit in the GPTMRIS register is set, and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out event. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode reloads the timer and continues counting after the time-out event. 11.4.2 Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0001. 3. Write the match value to the GPTM Timer n Match Register (GPTMTnMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as needed. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTnMATCHR register, the GPTM asserts the RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register. 11.4.3 Input Edge-Count Mode A timer is configured to Input Edge-Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. July 24, 2011 543 Texas Instruments-Production Data General-Purpose Timers 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register (GPTMTnPR). 6. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 7. Load the event count into the GPTM Timer n Match (GPTMTnMATCHR) register. 8. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 9. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 10. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. When counting down in Input Edge-Count Mode, the timer stops after the programmed number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 544 through step 9 on page 544. 11.4.4 Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timer n (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 11.4.5 PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 544 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 6. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 11.5 Register Map Table 11-6 on page 545 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s address, relative to that timer’s base address: ■ ■ ■ ■ Timer 0: 0x4003.0000 Timer 1: 0x4003.1000 Timer 2: 0x4003.2000 Timer 3: 0x4003.3000 Note that the GP Timer module clock must be enabled before the registers can be programmed (see page 246). There must be a delay of 3 system clocks after the Timer module clock is enabled before any Timer module registers are accessed. Table 11-6. Timers Register Map Description See page Offset Name Type Reset 0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 547 0x004 GPTMTAMR R/W 0x0000.0000 GPTM Timer A Mode 548 0x008 GPTMTBMR R/W 0x0000.0000 GPTM Timer B Mode 550 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 552 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 555 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 557 0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 560 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 563 0x028 GPTMTAILR R/W 0xFFFF.FFFF GPTM Timer A Interval Load 565 0x02C GPTMTBILR R/W 0x0000.FFFF GPTM Timer B Interval Load 566 0x030 GPTMTAMATCHR R/W 0xFFFF.FFFF GPTM Timer A Match 567 July 24, 2011 545 Texas Instruments-Production Data General-Purpose Timers Table 11-6. Timers Register Map (continued) Name Type Reset 0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM Timer B Match 568 0x038 GPTMTAPR R/W 0x0000.0000 GPTM Timer A Prescale 569 0x03C GPTMTBPR R/W 0x0000.0000 GPTM Timer B Prescale 570 0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 571 0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 572 0x048 GPTMTAR RO 0xFFFF.FFFF GPTM Timer A 573 0x04C GPTMTBR RO 0x0000.FFFF GPTM Timer B 574 0x050 GPTMTAV RW 0xFFFF.FFFF GPTM Timer A Value 575 0x054 GPTMTBV RW 0x0000.FFFF GPTM Timer B Value 576 11.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. 546 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. Important: Bits in this register should only be changed when the TAEN and TBEN bits in the GPTMCTL register are cleared. GPTM Configuration (GPTMCFG) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 GPTMCFG R/W 0x0 GPTMCFG R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Configuration The GPTMCFG values are defined as follows: Value Description 0x0 32-bit timer configuration. 0x1 32-bit real-time clock (RTC) counter configuration. 0x2-0x3 Reserved 0x4 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 0x5-0x7 Reserved July 24, 2011 547 Texas Instruments-Production Data General-Purpose Timers Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in PWM mode, set the TAAMS bit, clear the TACMR bit, and configure the TAMR field to 0x1 or 0x2. This register controls the modes for Timer A when it is used individually. When Timer A and Timer B are concatenated, this register controls the modes for both Timer A and Timer B, and the contents of GPTMTBMR are ignored. Important: Bits in this register should only be changed when the TAEN bit in the GPTMCTL register is cleared. GPTM Timer A Mode (GPTMTAMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TASNAPS TAWOT RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 TASNAPS R/W 0 RO 0 R/W 0 R/W 0 5 4 3 2 TAMIE TACDIR TAAMS TACMR R/W 0 R/W 0 R/W 0 R/W 0 0 TAMR R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer A Snap-Shot Mode Value Description 6 TAWOT R/W 0 0 Snap-shot mode is disabled. 1 If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPTM Timer A (GPTMTAR) register. GPTM Timer A Wait-on-Trigger Value Description 0 Timer A begins counting as soon as it is enabled. 1 If Timer A is enabled (TAEN is set in the GPTMCTL register), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain, see Figure 11-2 on page 538. This function is valid for both one-shot and periodic modes. This bit must be clear for GP Timer Module 0, Timer A. 548 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 5 TAMIE R/W 0 Description GPTM Timer A Match Interrupt Enable Value Description 4 TACDIR R/W 0 0 The match interrupt is disabled. 1 An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes. GPTM Timer A Count Direction Value Description 0 The timer counts down. 1 When in one-shot or periodic mode, the timer counts up. When counting up, the timer starts from a value of 0x0. When in PWM or RTC mode, the status of this bit is ignored. PWM mode always counts down and RTC mode always counts up. 3 TAAMS R/W 0 GPTM Timer A Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TACMR R/W 0 To enable PWM mode, you must also clear the TACMR bit and configure the TAMR field to 0x1 or 0x2. GPTM Timer A Capture Mode The TACMR values are defined as follows: Value Description 1:0 TAMR R/W 0x0 0 Edge-Count mode 1 Edge-Time mode GPTM Timer A Mode The TAMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. July 24, 2011 549 Texas Instruments-Production Data General-Purpose Timers Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in PWM mode, set the TBAMS bit, clear the TBCMR bit, and configure the TBMR field to 0x1 or 0x2. This register controls the modes for Timer B when it is used individually. When Timer A and Timer B are concatenated, this register is ignored and GPTMTBMR controls the modes for both Timer A and Timer B. Important: Bits in this register should only be changed when the TBEN bit in the GPTMCTL register is cleared. GPTM Timer B Mode (GPTMTBMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TBSNAPS TBWOT RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 TBSNAPS R/W 0 RO 0 R/W 0 R/W 0 5 4 3 2 TBMIE TBCDIR TBAMS TBCMR R/W 0 R/W 0 R/W 0 R/W 0 0 TBMR R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Snap-Shot Mode Value Description 6 TBWOT R/W 0 0 Snap-shot mode is disabled. 1 If Timer B is configured in the periodic mode, the actual free-running value of Timer B is loaded at the time-out event into the GPTM Timer B (GPTMTBR) register. GPTM Timer B Wait-on-Trigger Value Description 0 Timer B begins counting as soon as it is enabled. 1 If Timer B is enabled (TBEN is set in the GPTMCTL register), Timer B does not begin counting until it receives an it receives a trigger from the timer in the previous position in the daisy chain, see Figure 11-2 on page 538. This function is valid for both one-shot and periodic modes. 550 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 5 TBMIE R/W 0 Description GPTM Timer B Match Interrupt Enable Value Description 4 TBCDIR R/W 0 0 The match interrupt is disabled. 1 An interrupt is generated when the match value in the GPTMTBMATCHR register is reached in the one-shot and periodic modes. GPTM Timer B Count Direction Value Description 0 The timer counts down. 1 When in one-shot or periodic mode, the timer counts up. When counting up, the timer starts from a value of 0x0. When in PWM or RTC mode, the status of this bit is ignored. PWM mode always counts down and RTC mode always counts up. 3 TBAMS R/W 0 GPTM Timer B Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TBCMR R/W 0 To enable PWM mode, you must also clear the TBCMR bit and configure the TBMR field to 0x1 or 0x2. GPTM Timer B Capture Mode The TBCMR values are defined as follows: Value Description 1:0 TBMR R/W 0x0 0 Edge-Count mode 1 Edge-Time mode GPTM Timer B Mode The TBMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. July 24, 2011 551 Texas Instruments-Production Data General-Purpose Timers Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. Important: Bits in this register should only be changed when the TnEN bit for the respective timer is cleared. GPTM Control (GPTMCTL) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 reserved TBPWML TBOTE reserved RO 0 R/W 0 R/W 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TBSTALL TBEN reserved TAPWML TAOTE RTCEN TASTALL TAEN R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset TBEVENT R/W 0 R/W 0 Bit/Field Name Type Reset 31:15 reserved RO 0x0000.0 14 TBPWML R/W 0 TAEVENT R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B PWM Output Level The TBPWML values are defined as follows: Value Description 13 TBOTE R/W 0 0 Output is unaffected. 1 Output is inverted. GPTM Timer B Output Trigger Enable The TBOTE values are defined as follows: Value Description 0 The output Timer B ADC trigger is disabled. 1 The output Timer B ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see page 632). 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 552 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 11:10 TBEVENT R/W 0x0 Description GPTM Timer B Event Mode The TBEVENT values are defined as follows: Value Description 9 TBSTALL R/W 0 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges GPTM Timer B Stall Enable The TBSTALL values are defined as follows: Value Description 0 Timer B continues counting while the processor is halted by the debugger. 1 Timer B freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TBSTALL bit is ignored. 8 TBEN R/W 0 GPTM Timer B Enable The TBEN values are defined as follows: Value Description 0 Timer B is disabled. 1 Timer B is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 TAPWML R/W 0 GPTM Timer A PWM Output Level The TAPWML values are defined as follows: Value Description 5 TAOTE R/W 0 0 Output is unaffected. 1 Output is inverted. GPTM Timer A Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 The output Timer A ADC trigger is disabled. 1 The output Timer A ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see page 632). July 24, 2011 553 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 4 RTCEN R/W 0 Description GPTM RTC Enable The RTCEN values are defined as follows: Value Description 3:2 TAEVENT R/W 0x0 0 RTC counting is disabled. 1 RTC counting is enabled. GPTM Timer A Event Mode The TAEVENT values are defined as follows: Value Description 1 TASTALL R/W 0 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges GPTM Timer A Stall Enable The TASTALL values are defined as follows: Value Description 0 Timer A continues counting while the processor is halted by the debugger. 1 Timer A freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TASTALL bit is ignored. 0 TAEN R/W 0 GPTM Timer A Enable The TAEN values are defined as follows: Value Description 0 Timer A is disabled. 1 Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 554 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables the corresponding interrupt, while clearing a bit disables it. GPTM Interrupt Mask (GPTMIMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 11 10 9 8 TBMIM CBEIM CBMIM TBTOIM R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TBMIM R/W 0 reserved RO 0 RO 0 RO 0 4 3 2 1 0 TAMIM RTCIM CAEIM CAMIM TATOIM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Mode Match Interrupt Mask The TBMIM values are defined as follows: Value Description 10 CBEIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Capture B Event Interrupt Mask The CBEIM values are defined as follows: Value Description 9 CBMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Capture B Match Interrupt Mask The CBMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. July 24, 2011 555 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 8 TBTOIM R/W 0 Description GPTM Timer B Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 TAMIM R/W 0 GPTM Timer A Mode Match Interrupt Mask The TAMIM values are defined as follows: Value Description 3 RTCIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 2 CAEIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Capture A Event Interrupt Mask The CAEIM values are defined as follows: Value Description 1 CAMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Capture A Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 TATOIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Timer A Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 556 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 TBMRIS CBERIS RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 CBMRIS TBTORIS RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TBMRIS RO 0 RO 0 reserved RO 0 RO 0 RO 0 4 3 2 TAMRIS RTCRIS CAERIS RO 0 RO 0 RO 0 CAMRIS TATORIS RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Mode Match Raw Interrupt Value Description 1 The TBMIE bit is set in the GPTMTBMR register, and the match value in the GPTMTBMATCHR register has been reached when in the one-shot and periodic modes. 0 The match value has not been reached. This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register. 10 CBERIS RO 0 GPTM Capture B Event Raw Interrupt Value Description 1 The Capture B event has occurred. 0 The Capture B event has not occurred. This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register. 9 CBMRIS RO 0 GPTM Capture B Match Raw Interrupt Value Description 1 The Capture B match has occurred. 0 The Capture B match has not occurred. This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register. July 24, 2011 557 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 8 TBTORIS RO 0 Description GPTM Timer B Time-Out Raw Interrupt Value Description 1 Timer B has timed out. 0 Timer B has not timed out. This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 TAMRIS RO 0 GPTM Timer A Mode Match Raw Interrupt Value Description 1 The TAMIE bit is set in the GPTMTAMR register, and the match value in the GPTMTAMATCHR register has been reached when in the one-shot and periodic modes. 0 The match value has not been reached. This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register. 3 RTCRIS RO 0 GPTM RTC Raw Interrupt Value Description 1 The RTC event has occurred. 0 The RTC event has not occurred. This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR register. 2 CAERIS RO 0 GPTM Capture A Event Raw Interrupt Value Description 1 The Capture A event has occurred. 0 The Capture A event has not occurred. This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register. 1 CAMRIS RO 0 GPTM Capture A Match Raw Interrupt Value Description 1 The Capture A match has occurred. 0 The Capture A match has not occurred. This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register. 558 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 TATORIS RO 0 Description GPTM Timer A Time-Out Raw Interrupt Value Description 1 Timer A has timed out. 0 Timer A has not timed out. This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register. July 24, 2011 559 Texas Instruments-Production Data General-Purpose Timers Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 reserved Type Reset RO 0 RO 0 RO 0 11 TBMMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 CBEMIS CBMMIS TBTOMIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TBMMIS RO 0 RO 0 reserved RO 0 RO 0 RO 0 4 3 TAMMIS RTCMIS RO 0 RO 0 CAEMIS CAMMIS TATOMIS RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Mode Match Masked Interrupt Value Description 1 An unmasked Timer B Mode Match interrupt has occurred. 0 A Timer B Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register. 10 CBEMIS RO 0 GPTM Capture B Event Masked Interrupt Value Description 1 An unmasked Capture B event interrupt has occurred. 0 A Capture B event interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register. 560 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 9 CBMMIS RO 0 Description GPTM Capture B Match Masked Interrupt Value Description 1 An unmasked Capture B Match interrupt has occurred. 0 A Capture B Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register. 8 TBTOMIS RO 0 GPTM Timer B Time-Out Masked Interrupt Value Description 1 An unmasked Timer B Time-Out interrupt has occurred. 0 A Timer B Time-Out interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 TAMMIS RO 0 GPTM Timer A Mode Match Masked Interrupt Value Description 1 An unmasked Timer A Mode Match interrupt has occurred. 0 A Timer A Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register. 3 RTCMIS RO 0 GPTM RTC Masked Interrupt Value Description 1 An unmasked RTC event interrupt has occurred. 0 An RTC event interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR register. 2 CAEMIS RO 0 GPTM Capture A Event Masked Interrupt Value Description 1 An unmasked Capture A event interrupt has occurred. 0 A Capture A event interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register. July 24, 2011 561 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 1 CAMMIS RO 0 Description GPTM Capture A Match Masked Interrupt Value Description 1 An unmasked Capture A Match interrupt has occurred. 0 A Capture A Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register. 0 TATOMIS RO 0 GPTM Timer A Time-Out Masked Interrupt Value Description 1 An unmasked Timer A Time-Out interrupt has occurred. 0 A Timer A Time-Out interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register. 562 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 TBMCINT CBECINT CBMCINT TBTOCINT RO 0 RO 0 W1C 0 W1C 0 W1C 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TBMCINT W1C 0 W1C 0 reserved RO 0 RO 0 TAMCINT RTCCINT CAECINT CAMCINT TATOCINT RO 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Mode Match Interrupt Clear Writing a 1 to this bit clears the TBMRIS bit in the GPTMRIS register and the TBMMIS bit in the GPTMMIS register. 10 CBECINT W1C 0 GPTM Capture B Event Interrupt Clear Writing a 1 to this bit clears the CBERIS bit in the GPTMRIS register and the CBEMIS bit in the GPTMMIS register. 9 CBMCINT W1C 0 GPTM Capture B Match Interrupt Clear Writing a 1 to this bit clears the CBMRIS bit in the GPTMRIS register and the CBMMIS bit in the GPTMMIS register. 8 TBTOCINT W1C 0 GPTM Timer B Time-Out Interrupt Clear Writing a 1 to this bit clears the TBTORIS bit in the GPTMRIS register and the TBTOMIS bit in the GPTMMIS register. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 TAMCINT W1C 0 GPTM Timer A Mode Match Interrupt Clear Writing a 1 to this bit clears the TAMRIS bit in the GPTMRIS register and the TAMMIS bit in the GPTMMIS register. 3 RTCCINT W1C 0 GPTM RTC Interrupt Clear Writing a 1 to this bit clears the RTCRIS bit in the GPTMRIS register and the RTCMIS bit in the GPTMMIS register. 2 CAECINT W1C 0 GPTM Capture A Event Interrupt Clear Writing a 1 to this bit clears the CAERIS bit in the GPTMRIS register and the CAEMIS bit in the GPTMMIS register. July 24, 2011 563 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 1 CAMCINT W1C 0 Description GPTM Capture A Match Interrupt Clear Writing a 1 to this bit clears the CAMRIS bit in the GPTMRIS register and the CAMMIS bit in the GPTMMIS register. 0 TATOCINT W1C 0 GPTM Timer A Time-Out Raw Interrupt Writing a 1 to this bit clears the TATORIS bit in the GPTMRIS register and the TATOMIS bit in the GPTMMIS register. 564 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 9: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 When the timer is counting down, this register is used to load the starting count value into the timer. When the timer is counting up, this register sets the upper bound for the timeout event. When a GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Interval Load (GPTMTBILR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM Timer A Interval Load (GPTMTAILR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x028 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAILR Type Reset TAILR Type Reset Bit/Field Name Type 31:0 TAILR R/W Reset Description 0xFFFF.FFFF GPTM Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value of GPTMTAILR. July 24, 2011 565 Texas Instruments-Production Data General-Purpose Timers Register 10: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C When the timer is counting down, this register is used to load the starting count value into the timer. When the timer is counting up, this register sets the upper bound for the timeout event. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAILR register. Reads from this register return the current value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load value. Bits 31:16 are reserved in both cases. GPTM Timer B Interval Load (GPTMTBILR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TBILR Type Reset TBILR Type Reset Bit/Field Name Type 31:0 TBILR R/W Reset Description 0x0000.FFFF GPTM Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value of GPTMTBILR. When a GPTM is in 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 566 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 11: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. In PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When a GPTM is configured to one of the 32-bit modes, GPTMTAMATCHR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Match (GPTMTBMATCHR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBMATCHR. GPTM Timer A Match (GPTMTAMATCHR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x030 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAMR Type Reset TAMR Type Reset Bit/Field Name Type 31:0 TAMR R/W Reset Description 0xFFFF.FFFF GPTM Timer A Match Register This value is compared to the GPTMTAR register to determine match events. July 24, 2011 567 Texas Instruments-Production Data General-Purpose Timers Register 12: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. In PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAMATCHR register. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. GPTM Timer B Match (GPTMTBMATCHR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TBMR Type Reset TBMR Type Reset Bit/Field Name Type 31:0 TBMR R/W Reset Description 0x0000.FFFF GPTM Timer B Match Register This value is compared to the GPTMTBR register to determine match events. 568 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. In Edge-Count mode, this register is the MSB of the 24-bit count value. GPTM Timer A Prescale (GPTMTAPR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TAPSR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000 7:0 TAPSR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer A Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 11-5 on page 537 for more details and an example. July 24, 2011 569 Texas Instruments-Production Data General-Purpose Timers Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. In Edge-Count mode, this register is the MSB of the 24-bit count value. GPTM Timer B Prescale (GPTMTBPR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TBPSR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000 7:0 TBPSR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 11-5 on page 537 for more details and an example. 570 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TAPSMR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000 7:0 TAPSMR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. July 24, 2011 571 Texas Instruments-Production Data General-Purpose Timers Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TBPSMR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000 7:0 TBPSMR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 572 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 17: GPTM Timer A (GPTMTAR), offset 0x048 This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. Also in Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, GPTMTAR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B (GPTMTBR) register). In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the GPTMTAV register. GPTM Timer A (GPTMTAR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x048 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 TAR Type Reset TAR Type Reset Bit/Field Name Type 31:0 TAR RO Reset Description 0xFFFF.FFFF GPTM Timer A Register A read returns the current value of the GPTM Timer A Count Register, in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. July 24, 2011 573 Texas Instruments-Production Data General-Purpose Timers Register 18: GPTM Timer B (GPTMTBR), offset 0x04C This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. Also in Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAR register. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. GPTM Timer B (GPTMTBR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 TBR Type Reset TBR Type Reset Bit/Field Name Type 31:0 TBR RO Reset Description 0x0000.FFFF GPTM Timer B Register A read returns the current value of the GPTM Timer B Count Register, in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 574 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 19: GPTM Timer A Value (GPTMTAV), offset 0x050 When read, this register shows the current, free-running value of Timer A in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. In Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, GPTMTAV appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (GPTMTBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. Note: The GPTMTAV register cannot be written in Edge-Count mode. GPTM Timer A Value (GPTMTAV) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x050 Type RW, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 7 6 5 4 3 2 1 0 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 TAV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 15 14 13 12 11 10 9 8 TAV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 Bit/Field Name Type 31:0 TAV RW RW 1 Reset RW 1 Description 0xFFFF.FFFF GPTM Timer A Value A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. July 24, 2011 575 Texas Instruments-Production Data General-Purpose Timers Register 20: GPTM Timer B Value (GPTMTBV), offset 0x054 When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the GPTMTBR register on the next clock cycle. In Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAV register. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the current, free-running value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. GPTM Timer B Value (GPTMTBV) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x054 Type RW, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 TBV Type Reset TBV Type Reset Bit/Field Name Type 31:0 TBV RW Reset Description 0x0000.FFFF GPTM Timer B Value A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. 576 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 12 Watchdog Timers A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The LM3S1F11 microcontroller has two Watchdog Timer Modules, one module is clocked by the system clock (Watchdog Timer 0) and the other is clocked by the PIOSC (Watchdog Timer 1). The two modules are identical except that WDT1 is in a different clock domain, and therefore requires synchronizers. As a result, WDT1 has a bit defined in the Watchdog Timer Control (WDTCTL) register to indicate when a write to a WDT1 register is complete. Software can use this bit to ensure that the previous access has completed before starting the next access. ® The Stellaris LM3S1F11 controller has two Watchdog Timer modules with the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. July 24, 2011 577 Texas Instruments-Production Data Watchdog Timers 12.1 Block Diagram Figure 12-1. WDT Module Block Diagram WDTLOAD Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt WDTRIS 32-Bit Down Counter WDTMIS 0x0000.0000 WDTLOCK System Clock/ PIOSC WDTTEST Comparator WDTVALUE Identification Registers 12.2 WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled by setting the RESEN bit in the WDTCTL register, the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. 578 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 12.2.1 Register Access Timing Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. Software must guarantee that this delay is inserted between back-to-back writes to WDT1 registers or between a write followed by a read to the registers. The timing for back-to-back reads from the WDT1 module has no restrictions. The WRC bit in the Watchdog Control (WDTCTL) register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. Software should poll WDTCTL for WRC=1 prior to accessing another register. Note that WDT0 does not have this restriction as it runs off the system clock. 12.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register, see page 240. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If WDT1, wait for the WRC bit in the WDTCTL register to be set. 3. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 4. If WDT1, wait for the WRC bit in the WDTCTL register to be set. 5. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 12.4 Register Map Table 12-1 on page 580 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address: ■ WDT0: 0x4000.0000 ■ WDT1: 0x4000.1000 Note that the Watchdog Timer module clock must be enabled before the registers can be programmed (see page 240). July 24, 2011 579 Texas Instruments-Production Data Watchdog Timers Table 12-1. Watchdog Timers Register Map Name Type Reset 0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 581 0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 582 0x008 WDTCTL R/W 0x0000.0000 (WDT0) 0x8000.0000 (WDT1) Watchdog Control 583 0x00C WDTICR WO - Watchdog Interrupt Clear 585 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 586 0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 587 0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 588 0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 589 0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 590 0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 591 0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 592 0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 593 0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 594 0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 595 0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 596 0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 597 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 598 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 599 0xFF8 WDTPCellID2 RO 0x0000.0006 Watchdog PrimeCell Identification 2 600 0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 601 12.5 Description See page Offset Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 580 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 WDTLOAD Type Reset WDTLOAD Type Reset Bit/Field Name Type 31:0 WDTLOAD R/W Reset R/W 1 Description 0xFFFF.FFFF Watchdog Load Value July 24, 2011 581 Texas Instruments-Production Data Watchdog Timers Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 WDTVALUE Type Reset WDTVALUE Type Reset Bit/Field Name Type 31:0 WDTVALUE RO Reset RO 1 Description 0xFFFF.FFFF Watchdog Value Current value of the 32-bit down counter. 582 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled by setting the INTEN bit, all subsequent writes to the INTEN bit are ignored. The only mechanism that can re-enable writes to this bit is a hardware reset. Important: Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. Software must guarantee that this delay is inserted between back-to-back writes to WDT1 registers or between a write followed by a read to the registers. The timing for back-to-back reads from the WDT1 module has no restrictions. The WRC bit in the Watchdog Control (WDTCTL) register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. Software should poll WDTCTL for WRC=1 prior to accessing another register. Note that WDT0 does not have this restriction as it runs off the system clock and therefore does not have a WRC bit. Watchdog Control (WDTCTL) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x008 Type R/W, reset 0x0000.0000 (WDT0) and 0x8000.0000 (WDT1) 31 30 29 28 27 26 25 24 22 21 20 19 18 17 16 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RESEN INTEN RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 WRC Type Reset 23 reserved reserved Type Reset Bit/Field Name Type Reset 31 WRC RO 1 Description Write Complete The WRC values are defined as follows: Value Description 0 A write access to one of the WDT1 registers is in progress. 1 A write access is not in progress, and WDT1 registers can be read or written. Note: 30:2 reserved RO 0x000.000 This bit is reserved for WDT0 and has a reset value of 0. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 583 Texas Instruments-Production Data Watchdog Timers Bit/Field Name Type Reset 1 RESEN R/W 0 Description Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 INTEN R/W 0 0 Disabled. 1 Enable the Watchdog module reset output. Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description 0 Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 1 Interrupt event enabled. Once enabled, all writes are ignored. 584 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x00C Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WDTINTCLR Type Reset WDTINTCLR Type Reset Bit/Field Name Type Reset 31:0 WDTINTCLR WO - WO - Description Watchdog Interrupt Clear July 24, 2011 585 Texas Instruments-Production Data Watchdog Timers Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 WDTRIS RO 0 RO 0 WDTRIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Raw Interrupt Status Value Description 1 A watchdog time-out event has occurred. 0 The watchdog has not timed out. 586 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 WDTMIS RO 0 RO 0 WDTMIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Masked Interrupt Status Value Description 1 A watchdog time-out event has been signalled to the interrupt controller. 0 The watchdog has not timed out or the watchdog timer interrupt is masked. July 24, 2011 587 Texas Instruments-Production Data Watchdog Timers Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STALL Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 STALL R/W 0 R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Stall Enable Value Description 7:0 reserved RO 0x00 1 If the microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. 0 The watchdog timer continues counting if the microcontroller is stopped with a debugger. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 588 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 WDTLOCK Type Reset WDTLOCK Type Reset Bit/Field Name Type 31:0 WDTLOCK R/W Reset R/W 0 Description 0x0000.0000 Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked July 24, 2011 589 Texas Instruments-Production Data Watchdog Timers Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register [7:0] 590 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID5 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register [15:8] July 24, 2011 591 Texas Instruments-Production Data Watchdog Timers Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID6 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register [23:16] 592 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID7 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register [31:24] July 24, 2011 593 Texas Instruments-Production Data Watchdog Timers Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x05 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register [7:0] 594 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0x18 RO 0 RO 0 RO 0 RO 0 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register [15:8] July 24, 2011 595 Texas Instruments-Production Data Watchdog Timers Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID2 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x18 RO 0 RO 0 RO 0 RO 0 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register [23:16] 596 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x01 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register [31:24] July 24, 2011 597 Texas Instruments-Production Data Watchdog Timers Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register [7:0] 598 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register [15:8] July 24, 2011 599 Texas Instruments-Production Data Watchdog Timers Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFF8 Type RO, reset 0x0000.0006 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID2 RO 0x06 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register [23:16] 600 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID3 RO 0xB1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register [31:24] July 24, 2011 601 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) 13 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. ® The Stellaris ADC module features 12-bit conversion resolution and supports eight input channels, plus an internal temperature sensor. The ADC module contains four programmable sequencers allowing the sampling of multiple analog input sources without controller intervention. Each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. A digital comparator function is included which allows the conversion value to be diverted to a digital comparator module. The ADC module provides eight digital comparators. Each digital comparator evaluates the ADC conversion value against its two user-defined values to determine the operational range of the signal. The Stellaris LM3S1F11 microcontroller provides one ADC module with the following features: ■ Eight analog input channels ■ 12-bit precision ADC with an accurate 10-bit data compatibility mode ■ Single-ended and differential-input configurations ■ On-chip internal temperature sensor ■ Maximum sample rate of one million samples/second ■ Optional phase shift in sample time programmable from 22.5º to 337.5º ■ Four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – GPIO ■ Hardware averaging of up to 64 samples ■ Digital comparison unit providing eight digital comparators ■ Converter uses an internal 3-V reference or an external reference ■ Power and ground for the analog circuitry is separate from the digital power and ground ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each sample sequencer – ADC module uses burst requests for DMA 602 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 13.1 Block Diagram Figure 13-1 on page 603 provides details on the internal configuration of the ADC controls and data registers. Figure 13-1. ADC Module Block Diagram External Voltage Ref (VREFA) Internal Voltage Ref Trigger Events Comparator GPIO (PB4) Timer PWM SS3 Comparator GPIO (PB4) Timer PWM Sample Sequencer 0 Control/Status ADCSSMUX0 ADCACTSS ADCSSCTL0 ADCOSTAT ADCSSFSTAT0 Analog-to-Digital Converter Analog Inputs (AINx) ADCUSTAT SS2 Comparator GPIO (PB4) Timer PWM ADCSSPRI ADCCTL Sample Sequencer 1 ADCSPC ADCSSMUX1 ADCSSCTL1 SS1 Hardware Averager ADCSSFSTAT1 ADCSAC Sample Sequencer 2 Comparator GPIO (PB4) Timer PWM SS0 ADCSSMUX2 FIFO Block ADCSSCTL2 ADCSSOPn ADCSSFSTAT2 ADCEMUX ADCPSSI Interrupt Control SS0 Interrupt SS1 Interrupt SS2 Interrupt SS3 Interrupt ADCIM Sample Sequencer 3 ADCSSFIFO0 ADCSSDCn ADCSSFIFO1 ADCDCCTLn ADCSSFIFO2 ADCDCCMPn ADCSSFIFO3 ADCDCRIC ADCSSMUX3 ADCRIS ADCSSCTL3 ADCISC ADCSSFSTAT3 Digital Comparator ADCDCISC DC Interrupts PWM Trigger 13.2 Signal Description The following table lists the external signals of the ADC module and describes the function of each. The ADC signals are analog functions for some GPIO signals. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the ADC signals. The AINx and VREFA analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 400. Table 13-1. Signals for ADC (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description AIN0 1 PE7 I Analog Analog-to-digital converter input 0. AIN1 2 PE6 I Analog Analog-to-digital converter input 1. AIN2 5 PE5 I Analog Analog-to-digital converter input 2. AIN3 6 PE4 I Analog Analog-to-digital converter input 3. AIN4 100 PD7 I Analog Analog-to-digital converter input 4. AIN5 99 PD6 I Analog Analog-to-digital converter input 5. July 24, 2011 603 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Table 13-1. Signals for ADC (100LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description AIN6 98 PD5 I Analog Analog-to-digital converter input 6. AIN7 97 PD4 I Analog Analog-to-digital converter input 7. VREFA 90 PB6 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 4095. The VREFA input is limited to the range specified in Table 21-26 on page 904. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 13-2. Signals for ADC (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description AIN0 B1 PE7 I Analog Analog-to-digital converter input 0. AIN1 A1 PE6 I Analog Analog-to-digital converter input 1. AIN2 B3 PE5 I Analog Analog-to-digital converter input 2. AIN3 B2 PE4 I Analog Analog-to-digital converter input 3. AIN4 A2 PD7 I Analog Analog-to-digital converter input 4. AIN5 A3 PD6 I Analog Analog-to-digital converter input 5. AIN6 C6 PD5 I Analog Analog-to-digital converter input 6. AIN7 B5 PD4 I Analog Analog-to-digital converter input 7. VREFA A7 PB6 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 4095. The VREFA input is limited to the range specified in Table 21-26 on page 904. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 13.3 Functional Description The Stellaris ADC collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approaches found on many ADC modules. Each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC to collect data from multiple input sources without having to be re-configured or serviced by the processor. The programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. In addition, the μDMA can be used to more efficiently move data from the sample sequencers without CPU intervention. 13.3.1 Sample Sequencers The sampling control and data capture is handled by the sample sequencers. All of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the FIFO. Table 13-3 on page 605 shows the maximum number of samples that each sequencer can capture and its corresponding FIFO depth. Each sample that is captured is stored in the FIFO. 604 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller In this implementation, each FIFO entry is a 32-bit word, with the lower 12 bits containing the conversion result. Table 13-3. Samples and FIFO Depth of Sequencers Sequencer Number of Samples Depth of FIFO SS3 1 1 SS2 4 4 SS1 4 4 SS0 8 8 For a given sample sequence, each sample is defined by bit fields in the ADC Sample Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn fields select the input pin, while the ADCSSCTLn fields contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. Sample sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register and should be configured before being enabled. Sampling is then initiated by setting the SSn bit in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. When configuring a sample sequence, multiple uses of the same input pin within the same sequence are allowed. In the ADCSSCTLn register, the IEn bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete execution of the sample sequence after the fifth sample. After a sample sequence completes execution, the result data can be retrieved from the ADC Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers that read a single address to "pop" result data. For software debug purposes, the positions of the FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn) registers along with FULL and EMPTY status flags. If a write is attempted when the FIFO is full, the write does not occur and an overflow condition is indicated. Overflow and underflow conditions are monitored using the ADCOSTAT and ADCUSTAT registers. 13.3.2 Module Control Outside of the sample sequencers, the remainder of the control logic is responsible for tasks such as: ■ Interrupt generation ■ DMA operation ■ Sequence prioritization ■ Trigger configuration ■ Comparator configuration ■ External voltage reference ■ Sample phase control July 24, 2011 605 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is configured for 16-MHz operation automatically by hardware when the system XTAL is selected. 13.3.2.1 Interrupts The register configurations of the sample sequencers and digital comparators dictate which events generate raw interrupts, but do not have control over whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signals are controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of the various interrupt signals; and the ADC Interrupt Status and Clear (ADCISC) register, which shows active interrupts that are enabled by the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the corresponding IN bit in ADCISC. Digital comparator interrupts are cleared by writing a 1 to the ADC Digital Comparator Interrupt Status and Clear (ADCDCISC) register. 13.3.2.2 DMA Operation DMA may be used to increase efficiency by allowing each sample sequencer to operate independently and transfer data without processor intervention or reconfiguration. The ADC module provides a request signal from each sample sequencer to the associated dedicated channel of the μDMA controller. The ADC does not support single transfer requests. A burst transfer request is asserted when the interrupt bit for the sample sequence is set (IE bit in the ADCSSCTLn register is set). The arbitration size of the μDMA transfer must be a power of 2, and the associated IE bits in the ADDSSCTLn register must be set. For example, if the μDMA channel of SS0 has an arbitration size of four, the IE3 bit (4th sample) and the IE7 bit (8th sample) must be set. Thus the μDMA request occurs every time 4 samples have been acquired. No other special steps are needed to enable the ADC module for μDMA operation. Refer to the “Micro Direct Memory Access (μDMA)” on page 340 for more details about programming the μDMA controller. 13.3.2.3 Prioritization When sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample sequencer units with the same priority do not provide consistent results, so software must ensure that all active sample sequencer units have a unique priority value. 13.3.2.4 Sampling Events Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select (ADCEMUX) register. Trigger sources include processor (default), analog comparators, an external signal on GPIO PB4, a GP Timer, and continuous sampling. The processor triggers sampling by setting the SSx bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. Care must be taken when using the continuous sampling trigger. If a sequencer's priority is too high, it is possible to starve other lower priority sequencers. Generally, a sample sequencer using continuous sampling should be set to the lowest priority. Continuous sampling can be used with a digital comparator to cause an interrupt when a particular voltage is seen on an input. 13.3.2.5 Sample Phase Control The sample time can be delayed from the standard sampling time in 22.5° increments up to 337.5º using the ADC Sample Phase Control (ADCSPC) register. Figure 13-2 on page 607 shows an example of various phase relationships at a 1 Msps rate. 606 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 13-2. ADC Sample Phases 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ADC Sample Clock PHASE 0x0 (0.0°) PHASE 0x1 (22.5°) . . . . . . . . . . . . PHASE 0xE (315.0°) PHASE 0xF (337.5°) 13.3.3 Hardware Sample Averaging Circuit Higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the number of samples in the averaging calculation. For example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. By default the averaging circuit is off, and all data from the converter passes through to the sequencer FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC) register (see page 642). A single averaging circuit has been implemented, thus all input channels receive the same amount of averaging whether they are single-ended or differential. Figure 13-3 on page 607 shows an example in which the ADCSAC register is set to 0x2 for 4x hardware oversampling and the IE1 bit is set for the sample sequence, resulting in an interrupt after the second averaged value is stored in the FIFO. Figure 13-3. Sample Averaging Example A+B+C+D 4 A+B+C+D 4 INT July 24, 2011 607 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) 13.3.4 Analog-to-Digital Converter The Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR) architecture to deliver a 12-bit, low-power, high-precision conversion value. The ADC defaults to a 10-bit conversion result, providing backwards compatibility with previous generations of Stellaris microcontrollers. To enable 12-bit resolution, set the RES bit in the ADC Control (ADCCTL) register. The successive-approximation algorithm uses a current mode D/A converter to achieve lower settling time, resulting in higher conversion speeds for the A/D converter. In addition, built-in sample-and-hold circuitry with offset-calibration circuitry improves conversion accuracy. The ADC must be run from the PLL or a 14- to 18-MHz clock source. The ADC operates from both the 3.3-V analog and 1.2-V digital power supplies. The ADC clock can be configured to reduce power consumption when ADC conversions are not required (see “System Control” on page 188). The analog inputs are connected to the ADC through custom pads and specially balanced input paths to minimize the distortion on the inputs. Detailed information on the ADC power supplies and analog inputs can be found in “Analog-to-Digital Converter (ADC)” on page 903. 13.3.4.1 Internal Voltage Reference The band-gap circuitry generates an internal 3.0 V reference that can be used by the ADC to produce a conversion value from the selected analog input. The range of this conversion value is from 0x000 to 0xFFF in 12-bit mode, or 0x3FF in 10-bit mode. In single-ended-input mode, the 0x000 value corresponds to an analog input voltage of 0.0 V; the 0xFFF in 12-bit mode, or 0x3FF in 10-bit mode value corresponds to an analog input voltage of 3.0 V. This configuration results in a resolution of approximately 0.7 mV in 12-bit mode and 2.9 mV per ADC code in 10-bit mode. While the analog input pads can handle voltages beyond this range, the ADC conversions saturate in under-voltage and over-voltage cases. Figure 13-4 on page 609 shows the ADC conversion function of the analog inputs. 608 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 13-4. Internal Voltage Conversion Result 12-bit/ 10-bit 0xFFF/ 0x3FF 0xBFF/ 0x2FF 0x7FF/ 0x1FF 0x3FF/ 0x0FF 0.00 V 0.75 V 1.50 V 2.25 V 3.00 V VIN - Input Saturation 13.3.4.2 External Voltage Reference The ADC can use an external voltage reference to produce the conversion value from the selected analog input by configuring the VREF field in the ADC Control (ADCCTL) register. The VREF field specifies whether to use the internal, an external reference in the 3.0 V range, or an external reference in the 1.0 V range. While the range of the conversion value remains the same (0x000 to 0xFFF or 0x3FF), the analog voltage associated with the 0xFFF or 0x3FF value corresponds to the value of the voltage when using the 3.0-V setting and three times the voltage when using the 1.0-V setting, resulting in a smaller voltage resolution per ADC code. Ground is always used as the reference level for the minimum conversion value. Analog input voltages above the external voltage reference saturate to 0xFFF or 0x3FF while those below 0.0 V continue to saturate at 0x000. The VREFA specification defines the useful range for the external voltage reference, see Table 21-26 on page 904. Care must be taken to supply a reference voltage of acceptable quality. Figure 13-5 on page 610 shows the ADC conversion function of the analog inputs when using anthe 3.0-V setting on the external voltage reference. Figure 13-6 on page 610 shows the ADC conversion function when using the 1.0-V setting on the external voltage reference. The external voltage reference can be more accurate than the internal reference by using a high-precision source or trimming the source. July 24, 2011 609 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 13-5. External Voltage Conversion Result with 3.0-V Setting 12-bit/ 10-bit 0xFFF/ 0x3FF 0xBFF/ 0x2FF 0x7FF/ 0x1FF 0x3FF/ 0x0FF 0.00 V ½ VREFA VREFA VDD VIN - Input Saturation Figure 13-6. External Voltage Conversion Result with 1.0-V Setting 12-bit/ 10-bit 0xFFF/ 0x3FF 0xBFF/ 0x2FF 0x7FF/ 0x1FF 0x3FF/ 0x0FF 0.00 V 1.5*VREFA 3*VREFA VDD VIN - Input Saturation 610 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 13.3.5 Differential Sampling In addition to traditional single-ended sampling, the ADC module supports differential sampling of two analog input channels. To enable differential sampling, software must set the Dn bit in the ADCSSCTL0n register in a step's configuration nibble. When a sequence step is configured for differential sampling, the input pair to sample must be configured in the ADCSSMUXn register. Differential pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see Table 13-4 on page 611). The ADC does not support other differential pairings such as analog input 0 with analog input 3. Table 13-4. Differential Sampling Pairs Differential Pair Analog Inputs 0 0 and 1 1 2 and 3 2 4 and 5 3 6 and 7 The voltage sampled in differential mode is the difference between the odd and even channels: ∆V (differential voltage) = VIN_EVEN (even channel) – VIN_ODD (odd channel), therefore: ■ If ∆V = 0, then the conversion result = 0x1FF for 10-bit and 0x7FF for 12-bit ■ If ∆V > 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF) for 10-bit and > 0x7FF (range is 0x7FF - 0xFFF) for 12-bit ■ If ∆V < 0, then the conversion result < 0x1FF (range is 0–0x1FF) for 10-bit and < 0x7FF (range is 0 - 0x7FF) for 12-bit The differential pairs assign polarities to the analog inputs: the even-numbered input is always positive, and the odd-numbered input is always negative. In order for a valid conversion result to appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped, meaning it appears as either 3 V or 0 V , respectively, to the ADC. Figure 13-7 on page 612 shows an example of the negative input centered at 1.5 V. In this configuration, the differential range spans from -1.5 V to 1.5 V. Figure 13-8 on page 612 shows an example where the negative input is centered at 0.75 V, meaning inputs on the positive input saturate past a differential voltage of -0.75 V because the input voltage is less than 0 V. Figure 13-9 on page 613 shows an example of the negative input centered at 2.25 V, where inputs on the positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater than 3 V. July 24, 2011 611 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 13-7. Differential Sampling Range, VIN_ODD = 1.5 V 12-bit 10-bit 0xFFF 0x3FF 0x7FF 0x1FF 0 -1.5 1.5 0 3.0 VIN_EVEN 1.5 DV VIN_ODD = 1.5 V - Input Saturation Figure 13-8. Differential Sampling Range, VIN_ODD = 0.75 V -1.5 V 0V -0.75 V 12-bit 10-bit 0xFFF 0x3FF 0x7FF 0x1FF 0x3FF 0x0FF +0.75 V +2.25 V +1.5 V VIN_EVEN DV - Input Saturation 612 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 13-9. Differential Sampling Range, VIN_ODD = 2.25 V 0.75 V -1.5 V 12-bit 10-bit 0xFFF 0x3FF 0xBFF 0x2FF 0x7FF 0x1FF 2.25 V 3.0 V 0.75 V 1.5 V VIN_EVEN DV - Input Saturation 13.3.6 Internal Temperature Sensor The temperature sensor serves two primary purposes: 1) to notify the system that internal temperature is too high or low for reliable operation and 2) to provide temperature measurements for calibration of the Hibernate module RTC trim value. The temperature sensor does not have a separate enable, because it also contains the bandgap reference and must always be enabled. The reference is supplied to other analog modules; not just the ADC. In addition, the temperature sensor has a second power-down input in the 3.3 V domain which provides control by the Hibernation module. The internal temperature sensor provides an analog temperature reading as well as a reference voltage. This reference voltage, SENSO, is given by the following equation: SENSO = 2.7 - ((T + 55) / 75) This relation is shown in Figure 13-10 on page 614. July 24, 2011 613 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 13-10. Internal Temperature Sensor Characteristic Sensor = 2.7 V – (T+55) 75 Sensor 2.7 V 1.633 V 0.3 V -55° C 25° C 125° C Temp The temperature sensor reading can be sampled in a sample sequence by setting the TSn bit in the ADCSSCTLn register. The temperature reading from the temperature sensor can also be given as a function of the ADC value. The following formula calculates temperature (in ℃) based on the ADC reading: Temperature = 147.5 - ((225 × ADC) / 4095) 13.3.7 Digital Comparator Unit An ADC is commonly used to sample an external signal and to monitor its value to ensure that it remains in a given range. To automate this monitoring procedure and reduce the amount of processor overhead that is required, eight digital comparators are provided. Conversions from the ADC that are sent to the digital comparators are compared against the user programmable limits in the ADC Digital Comparator Range (ADCDCCMPn) registers. If the observed signal moves out of the acceptable range, a processor interrupt can be generated. The digital comparators four operational modes (Once, Always, Hysteresis Once, Hysteresis Always) can be applied to three separate regions (low band, mid band, high band) as defined by the user. 13.3.7.1 Output Functions ADC conversions can either be stored in the ADC Sample Sequence FIFOs or compared using the digital comparator resources as defined by the SnDCOP bits in the ADC Sample Sequence n Operation (ADCSSOPn) register. These selected ADC conversions are used by their respective digital comparator to monitor the external signal. Each comparator has two possible output functions: processor interrupts and triggers. 614 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Each function has its own state machine to track the monitored signal. Even though the interrupt and trigger functions can be enabled individually or both at the same time, the same conversion data is used by each function to determine if the right conditions have been met to assert the associated output. Interrupts The digital comparator interrupt function is enabled by setting the CIE bit in the ADC Digital Comparator Control (ADCDCCTLn) register. This bit enables the interrupt function state machine to start monitoring the incoming ADC conversions. When the appropriate set of conditions is met, and the DCONSSx bit is set in the ADCIM register, an interrupt is sent to the interrupt controller. 13.3.7.2 Operational Modes Four operational modes are provided to support a broad range of applications and multiple possible signaling requirements: Always, Once, Hysteresis Always, and Hysteresis Once. The operational mode is selected using the CIM field in the ADCDCCTLn register. Always Mode In the Always operational mode, the associated interrupt or trigger is asserted whenever the ADC conversion value meets its comparison criteria. The result is a string of assertions on the interrupt or trigger while the conversions are within the appropriate range. Once Mode In the Once operational mode, the associated interrupt or trigger is asserted whenever the ADC conversion value meets its comparison criteria, and the previous ADC conversion value did not. The result is a single assertion of the interrupt or trigger when the conversions are within the appropriate range. Hysteresis-Always Mode The Hysteresis-Always operational mode can only be used in conjunction with the low-band or high-band regions because the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. In the Hysteresis-Always mode, the associated interrupt or trigger is asserted in the following cases: 1) the ADC conversion value meets its comparison criteria or 2) a previous ADC conversion value has met the comparison criteria, and the hysteresis condition has not been cleared by entering the opposite region. The result is a string of assertions on the interrupt or trigger that continue until the opposite region is entered. Hysteresis-Once Mode The Hysteresis-Once operational mode can only be used in conjunction with the low-band or high-band regions because the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. In the Hysteresis-Once mode, the associated interrupt or trigger is asserted only when the ADC conversion value meets its comparison criteria, the hysteresis condition is clear, and the previous ADC conversion did not meet the comparison criteria. The result is a single assertion on the interrupt or trigger. 13.3.7.3 Function Ranges The two comparison values, COMP0 and COMP1, in the ADC Digital Comparator Range (ADCDCCMPn) register effectively break the conversion area into three distinct regions. These regions are referred to as the low-band (less than or equal to COMP0), mid-band (greater than COMP0 but less than or equal to COMP1), and high-band (greater than COMP1) regions. COMP0 and COMP1 may be programmed to the same value, effectively creating two regions, but COMP1 must always July 24, 2011 615 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) be greater than or equal to the value of COMP0. A COMP1 value that is less than COMP0 generates unpredictable results. Low-Band Operation To operate in the low-band region, either the CIC field field in the ADCDCCTLn register must be programmed to 0x0. This setting causes interrupts or triggers to be generated in the low-band region as defined by the programmed operational mode. An example of the state of the interrupt/trigger signal in the low-band region for each of the operational modes is shown in Figure 13-11 on page 616. Note that a "0" in a column following the operational mode name (Always, Once, Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. Figure 13-11. Low-Band Operation (CIC=0x0) COMP1 COMP0 Always – 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 Once – 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 Hysteresis Always – 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 Hysteresis Once – 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 Mid-Band Operation To operate in the mid-band region, either the CIC field field in the ADCDCCTLn register must be programmed to 0x1. This setting causes interrupts or triggers to be generated in the mid-band region according the operation mode. Only the Always and Once operational modes are available in the mid-band region. An example of the state of the interrupt/trigger signal in the mid-band region for each of the allowed operational modes is shown in Figure 13-12 on page 617. Note that a "0" in a column following the operational mode name (Always or Once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. 616 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 13-12. Mid-Band Operation (CIC=0x1) COMP1 COMP0 Always – 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 Once – 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 Hysteresis Always – - - - - - - - - - - - - - - - - Hysteresis Once – - - - - - - - - - - - - - - - - High-Band Operation To operate in the high-band region, either the CIC field field in the ADCDCCTLn register must be programmed to 0x3. This setting causes interrupts or triggers to be generated in the high-band region according the operation mode. An example of the state of the interrupt/trigger signal in the high-band region for each of the allowed operational modes is shown in Figure 13-13 on page 618. Note that a "0" in a column following the operational mode name (Always, Once, Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. July 24, 2011 617 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 13-13. High-Band Operation (CIC=0x3) COMP1 COMP0 13.4 Always – 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 Once – 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 Hysteresis Always – 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 Hysteresis Once – 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 Initialization and Configuration In order for the ADC module to be used, the PLL must be enabled and programmed to a supported crystal frequency in the RCC register (see page 204). Using unsupported frequencies can cause faulty operation in the ADC module. 13.4.1 Module Initialization Initialization of the ADC module is a simple process with very few steps: enabling the clock to the ADC, disabling the analog isolation circuit associated with all inputs that are to be used, and reconfiguring the sample sequencer priorities (if needed). The initialization sequence for the ADC is as follows: 1. Enable the ADC clock by using the RCGC0 register (see page 240). 2. Enable the clock to the appropriate GPIO modules via the RCGC2 register (see page 255). To find out which GPIO ports to enable, refer to “Signal Description” on page 603. 3. Set the GPIO AFSEL bits for the ADC input pins (see page 424). To determine which GPIOs to configure, see Table 19-4 on page 848. 4. Configure the AINx and VREFA signals to be analog inputs by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register (see page 435). 5. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to the appropriate bits of the GPIOAMSEL register (see page 440) in the associated GPIO block. 618 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 6. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI register. The default configuration has Sample Sequencer 0 with the highest priority and Sample Sequencer 3 as the lowest priority. 13.4.2 Sample Sequencer Configuration Configuration of the sample sequencers is slightly more complex than the module initialization because each sample sequencer is completely programmable. The configuration for each sample sequencer should be as follows: 1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the ADCACTSS register. Programming of the sample sequencers is allowed without having them enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. Configure the trigger event for the sample sequencer in the ADCEMUX register. 3. For each sample in the sample sequence, configure the corresponding input source in the ADCSSMUXn register. 4. For each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. 5. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register. 6. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS register. 13.5 Register Map Table 13-5 on page 619 lists the ADC registers. The offset listed is a hexadecimal increment to the register’s address, relative to that ADC module's base address of: ■ ADC0: 0x4003.8000 Note that the ADC module clock must be enabled before the registers can be programmed (see page 240). There must be a delay of 3 system clocks after the ADC module clock is enabled before any ADC module registers are accessed. Table 13-5. ADC Register Map Description See page Offset Name Type Reset 0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 622 0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 623 0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 625 0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 627 0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 630 0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 632 July 24, 2011 619 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Table 13-5. ADC Register Map (continued) Offset Name 0x018 See page Type Reset Description ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 636 0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 637 0x024 ADCSPC R/W 0x0000.0000 ADC Sample Phase Control 639 0x028 ADCPSSI R/W - ADC Processor Sample Sequence Initiate 640 0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 642 0x034 ADCDCISC R/W1C 0x0000.0000 ADC Digital Comparator Interrupt Status and Clear 643 0x038 ADCCTL R/W 0x0000.0000 ADC Control 645 0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 646 0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 648 0x048 ADCSSFIFO0 RO - ADC Sample Sequence Result FIFO 0 651 0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 652 0x050 ADCSSOP0 R/W 0x0000.0000 ADC Sample Sequence 0 Operation 654 0x054 ADCSSDC0 R/W 0x0000.0000 ADC Sample Sequence 0 Digital Comparator Select 656 0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 658 0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 659 0x068 ADCSSFIFO1 RO - ADC Sample Sequence Result FIFO 1 651 0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 652 0x070 ADCSSOP1 R/W 0x0000.0000 ADC Sample Sequence 1 Operation 661 0x074 ADCSSDC1 R/W 0x0000.0000 ADC Sample Sequence 1 Digital Comparator Select 662 0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 658 0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 659 0x088 ADCSSFIFO2 RO - ADC Sample Sequence Result FIFO 2 651 0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 652 0x090 ADCSSOP2 R/W 0x0000.0000 ADC Sample Sequence 2 Operation 661 0x094 ADCSSDC2 R/W 0x0000.0000 ADC Sample Sequence 2 Digital Comparator Select 662 0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 664 0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 665 0x0A8 ADCSSFIFO3 RO - ADC Sample Sequence Result FIFO 3 651 0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 652 0x0B0 ADCSSOP3 R/W 0x0000.0000 ADC Sample Sequence 3 Operation 666 0x0B4 ADCSSDC3 R/W 0x0000.0000 ADC Sample Sequence 3 Digital Comparator Select 667 0xD00 ADCDCRIC R/W 0x0000.0000 ADC Digital Comparator Reset Initial Conditions 668 620 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 13-5. ADC Register Map (continued) Name Type Reset 0xE00 ADCDCCTL0 R/W 0x0000.0000 ADC Digital Comparator Control 0 673 0xE04 ADCDCCTL1 R/W 0x0000.0000 ADC Digital Comparator Control 1 673 0xE08 ADCDCCTL2 R/W 0x0000.0000 ADC Digital Comparator Control 2 673 0xE0C ADCDCCTL3 R/W 0x0000.0000 ADC Digital Comparator Control 3 673 0xE10 ADCDCCTL4 R/W 0x0000.0000 ADC Digital Comparator Control 4 673 0xE14 ADCDCCTL5 R/W 0x0000.0000 ADC Digital Comparator Control 5 673 0xE18 ADCDCCTL6 R/W 0x0000.0000 ADC Digital Comparator Control 6 673 0xE1C ADCDCCTL7 R/W 0x0000.0000 ADC Digital Comparator Control 7 673 0xE40 ADCDCCMP0 R/W 0x0000.0000 ADC Digital Comparator Range 0 675 0xE44 ADCDCCMP1 R/W 0x0000.0000 ADC Digital Comparator Range 1 675 0xE48 ADCDCCMP2 R/W 0x0000.0000 ADC Digital Comparator Range 2 675 0xE4C ADCDCCMP3 R/W 0x0000.0000 ADC Digital Comparator Range 3 675 0xE50 ADCDCCMP4 R/W 0x0000.0000 ADC Digital Comparator Range 4 675 0xE54 ADCDCCMP5 R/W 0x0000.0000 ADC Digital Comparator Range 5 675 0xE58 ADCDCCMP6 R/W 0x0000.0000 ADC Digital Comparator Range 6 675 0xE5C ADCDCCMP7 R/W 0x0000.0000 ADC Digital Comparator Range 7 675 13.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the ADC registers, in numerical order by address offset. July 24, 2011 621 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the sample sequencers. Each sample sequencer can be enabled or disabled independently. ADC Active Sample Sequencer (ADCACTSS) ADC0 base: 0x4003.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 ASEN3 ASEN2 ASEN1 ASEN0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 ASEN3 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC SS3 Enable Value Description 2 ASEN2 R/W 0 1 Sample Sequencer 3 is enabled. 0 Sample Sequencer 3 is disabled. ADC SS2 Enable Value Description 1 ASEN1 R/W 0 1 Sample Sequencer 2 is enabled. 0 Sample Sequencer 2 is disabled. ADC SS1 Enable Value Description 0 ASEN0 R/W 0 1 Sample Sequencer 1 is enabled. 0 Sample Sequencer 1 is disabled. ADC SS0 Enable Value Description 1 Sample Sequencer 0 is enabled. 0 Sample Sequencer 0 is disabled. 622 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each sample sequencer. These bits may be polled by software to look for interrupt conditions without sending the interrupts to the interrupt controller. ADC Raw Interrupt Status (ADCRIS) ADC0 base: 0x4003.8000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 1 0 INR3 INR2 INR1 INR0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset INRDC reserved Type Reset 16 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 INRDC RO 0 Digital Comparator Raw Interrupt Status Value Description 1 At least one bit in the ADCDCISC register is set, meaning that a digital comparator interrupt has occurred. 0 All bits in the ADCDCISC register are clear. 15:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 INR3 RO 0 SS3 Raw Interrupt Status Value Description 1 A sample has completed conversion and the respective ADCSSCTL3 IEn bit is set, enabling a raw interrupt. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN3 bit in the ADCISC register. 2 INR2 RO 0 SS2 Raw Interrupt Status Value Description 1 A sample has completed conversion and the respective ADCSSCTL2 IEn bit is set, enabling a raw interrupt. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN2 bit in the ADCISC register. July 24, 2011 623 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 1 INR1 RO 0 Description SS1 Raw Interrupt Status Value Description 1 A sample has completed conversion and the respective ADCSSCTL1 IEn bit is set, enabling a raw interrupt. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN1 bit in the ADCISC register. 0 INR0 RO 0 SS0 Raw Interrupt Status Value Description 1 A sample has completed conversion and the respective ADCSSCTL0 IEn bit is set, enabling a raw interrupt. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN0 bit in the ADCISC register. 624 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the sample sequencer and digital comparator raw interrupt signals are sent to the interrupt controller. Each raw interrupt signal can be masked independently. Only a single DCONSSn bit should be set at any given time. Setting more than one of these bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is generated on any of the sample sequencer interrupt lines. ADC Interrupt Mask (ADCIM) ADC0 base: 0x4003.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 25 24 23 22 21 20 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 9 8 7 6 5 4 3 2 1 0 MASK3 MASK2 MASK1 MASK0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 18 17 16 DCONSS3 DCONSS2 DCONSS1 DCONSS0 reserved Type Reset 19 Bit/Field Name Type Reset Description 31:20 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 DCONSS3 R/W 0 Digital Comparator Interrupt on SS3 Value Description 18 DCONSS2 R/W 0 1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS3 interrupt line. 0 The status of the digital comparators does not affect the SS3 interrupt status. Digital Comparator Interrupt on SS2 Value Description 17 DCONSS1 R/W 0 1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS2 interrupt line. 0 The status of the digital comparators does not affect the SS2 interrupt status. Digital Comparator Interrupt on SS1 Value Description 1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS1 interrupt line. 0 The status of the digital comparators does not affect the SS1 interrupt status. July 24, 2011 625 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 16 DCONSS0 R/W 0 Description Digital Comparator Interrupt on SS0 Value Description 1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS0 interrupt line. 0 The status of the digital comparators does not affect the SS0 interrupt status. 15:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 MASK3 R/W 0 SS3 Interrupt Mask Value Description 2 MASK2 R/W 0 1 The raw interrupt signal from Sample Sequencer 3 (ADCRIS register INR3 bit) is sent to the interrupt controller. 0 The status of Sample Sequencer 3 does not affect the SS3 interrupt status. SS2 Interrupt Mask Value Description 1 MASK1 R/W 0 1 The raw interrupt signal from Sample Sequencer 2 (ADCRIS register INR2 bit) is sent to the interrupt controller. 0 The status of Sample Sequencer 2 does not affect the SS2 interrupt status. SS1 Interrupt Mask Value Description 0 MASK0 R/W 0 1 The raw interrupt signal from Sample Sequencer 1 (ADCRIS register INR1 bit) is sent to the interrupt controller. 0 The status of Sample Sequencer 1 does not affect the SS1 interrupt status. SS0 Interrupt Mask Value Description 1 The raw interrupt signal from Sample Sequencer 0 (ADCRIS register INR0 bit) is sent to the interrupt controller. 0 The status of Sample Sequencer 0 does not affect the SS0 interrupt status. 626 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing sample sequencer interrupt conditions and shows the status of interrupts generated by the sample sequencers and the digital comparators which have been sent to the interrupt controller. When read, each bit field is the logical AND of the respective INR and MASK bits. Sample sequencer interrupts are cleared by writing a 1 to the corresponding bit position. Digital comparator interrupts are cleared by writing a 1 to the appropriate bits in the ADCDCISC register. If software is polling the ADCRIS instead of generating interrupts, the sample sequence INRn bits are still cleared via the ADCISC register, even if the INn bit is not set. ADC Interrupt Status and Clear (ADCISC) ADC0 base: 0x4003.8000 Offset 0x00C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 25 24 23 22 21 20 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 1 0 IN3 IN2 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset 18 17 16 DCINSS3 DCINSS2 DCINSS1 DCINSS0 reserved Type Reset 19 Bit/Field Name Type Reset Description 31:20 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 DCINSS3 RO 0 Digital Comparator Interrupt Status on SS3 Value Description 1 Both the INRDC bit in the ADCRIS register and the DCONSS3 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the ADCRIS register. 18 DCINSS2 RO 0 Digital Comparator Interrupt Status on SS2 Value Description 1 Both the INRDC bit in the ADCRIS register and the DCONSS2 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the ADCRIS register. July 24, 2011 627 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 17 DCINSS1 RO 0 Description Digital Comparator Interrupt Status on SS1 Value Description 1 Both the INRDC bit in the ADCRIS register and the DCONSS1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the ADCRIS register. 16 DCINSS0 RO 0 Digital Comparator Interrupt Status on SS0 Value Description 1 Both the INRDC bit in the ADCRIS register and the DCONSS0 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the ADCRIS register. 15:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 IN3 R/W1C 0 SS3 Interrupt Status and Clear Value Description 1 Both the INR3 bit in the ADCRIS register and the MASK3 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INR3 bit in the ADCRIS register. 2 IN2 R/W1C 0 SS2 Interrupt Status and Clear Value Description 1 Both the INR2 bit in the ADCRIS register and the MASK2 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INR2 bit in the ADCRIS register. 628 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 1 IN1 R/W1C 0 Description SS1 Interrupt Status and Clear Value Description 1 Both the INR1 bit in the ADCRIS register and the MASK1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INR1 bit in the ADCRIS register. 0 IN0 R/W1C 0 SS0 Interrupt Status and Clear Value Description 1 Both the INR0 bit in the ADCRIS register and the MASK0 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INR0 bit in the ADCRIS register. July 24, 2011 629 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) ADC0 base: 0x4003.8000 Offset 0x010 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 OV3 OV2 OV1 OV0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 OV3 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Overflow Value Description 1 The FIFO for Sample Sequencer 3 has hit an overflow condition, meaning that the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. 0 The FIFO has not overflowed. This bit is cleared by writing a 1. 2 OV2 R/W1C 0 SS2 FIFO Overflow Value Description 1 The FIFO for Sample Sequencer 2 has hit an overflow condition, meaning that the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. 0 The FIFO has not overflowed. This bit is cleared by writing a 1. 1 OV1 R/W1C 0 SS1 FIFO Overflow Value Description 1 The FIFO for Sample Sequencer 1 has hit an overflow condition, meaning that the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. 0 The FIFO has not overflowed. This bit is cleared by writing a 1. 630 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 OV0 R/W1C 0 Description SS0 FIFO Overflow Value Description 1 The FIFO for Sample Sequencer 0 has hit an overflow condition, meaning that the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. 0 The FIFO has not overflowed. This bit is cleared by writing a 1. July 24, 2011 631 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each sample sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) ADC0 base: 0x4003.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset EM3 Type Reset EM2 EM1 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15:12 EM3 R/W 0x0 EM0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Trigger Select This field selects the trigger source for Sample Sequencer 3. The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 828). 0x2 Analog Comparator 1 This trigger is configured by the Analog Comparator Control 1 (ACCTL1) register (page 828). 0x3 reserved 0x4 External (GPIO PB4) This trigger is connected to the GPIO interrupt for PB4 (see “ADC Trigger Source” on page 408). 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (page 552). 0x6 reserved 0x7 reserved 0x8 reserved 0x9 reserved 0xA-0xE reserved 0xF Always (continuously sample) 632 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 11:8 EM2 R/W 0x0 Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 828). 0x2 Analog Comparator 1 This trigger is configured by the Analog Comparator Control 1 (ACCTL1) register (page 828). 0x3 reserved 0x4 External (GPIO PB4) This trigger is connected to the GPIO interrupt for PB4 (see “ADC Trigger Source” on page 408). 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (page 552). 0x6 reserved 0x7 reserved 0x8 reserved 0x9 reserved 0xA-0xE reserved 0xF Always (continuously sample) July 24, 2011 633 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 7:4 EM1 R/W 0x0 Description SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 828). 0x2 Analog Comparator 1 This trigger is configured by the Analog Comparator Control 1 (ACCTL1) register (page 828). 0x3 reserved 0x4 External (GPIO PB4) This trigger is connected to the GPIO interrupt for PB4 (see “ADC Trigger Source” on page 408). 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (page 552). 0x6 reserved 0x7 reserved 0x8 reserved 0x9 reserved 0xA-0xE reserved 0xF Always (continuously sample) 634 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 3:0 EM0 R/W 0x0 Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0 The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 828). 0x2 Analog Comparator 1 This trigger is configured by the Analog Comparator Control 1 (ACCTL1) register (page 828). 0x3 reserved 0x4 External (GPIO PB4) This trigger is connected to the GPIO interrupt for PB4 (see “ADC Trigger Source” on page 408). 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (page 552). 0x6 reserved 0x7 reserved 0x8 reserved 0x9 reserved 0xA-0xE reserved 0xF Always (continuously sample) July 24, 2011 635 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding underflow condition is cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) ADC0 base: 0x4003.8000 Offset 0x018 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 UV3 UV2 UV1 UV0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 UV3 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Underflow The valid configurations for this field are shown below. This bit is cleared by writing a 1. Value Description 2 UV2 R/W1C 0 1 The FIFO for the Sample Sequencer has hit an underflow condition, meaning that the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. 0 The FIFO has not underflowed. SS2 FIFO Underflow The valid configurations are the same as those for the UV3 field. This bit is cleared by writing a 1. 1 UV1 R/W1C 0 SS1 FIFO Underflow The valid configurations are the same as those for the UV3 field. This bit is cleared by writing a 1. 0 UV0 R/W1C 0 SS0 FIFO Underflow The valid configurations are the same as those for the UV3 field. This bit is cleared by writing a 1. 636 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority for the ADC to operate properly. ADC Sample Sequencer Priority (ADCSSPRI) ADC0 base: 0x4003.8000 Offset 0x020 Type R/W, reset 0x0000.3210 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 1 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 RO 0 RO 0 R/W 0 R/W 1 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 SS3 R/W 1 reserved RO 0 SS2 R/W 1 Bit/Field Name Type Reset 31:14 reserved RO 0x0000.0 13:12 SS3 R/W 0x3 reserved SS1 reserved SS0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 3. A priority encoding of 0x0 is highest and 0x3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 11:10 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9:8 SS2 R/W 0x2 SS2 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 2. A priority encoding of 0x0 is highest and 0x3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 SS1 R/W 0x1 SS1 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 1. A priority encoding of 0x0 is highest and 0x3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 637 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 1:0 SS0 R/W 0x0 SS0 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. A priority encoding of 0x0 is highest and 0x3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 638 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024 This register allows the ADC module to sample at one of 16 different discrete phases from 0.0° through 337.5°. Note: Care should be taken when the PHASE field is non-zero, as the resulting delay in sampling the AINx input may result in undesirable system consequences. The time from ADC trigger to sample is increased and could make the response time longer than anticipated. The added latency could have ramifications in the system design. Designers should carefully consider the impact of this delay. ADC Sample Phase Control (ADCSPC) ADC0 base: 0x4003.8000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3:0 PHASE R/W 0x0 PHASE RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Phase Difference This field selects the sample phase difference from the standard sample time. Value Description 0x0 ADC sample lags by 0.0° 0x1 ADC sample lags by 22.5° 0x2 ADC sample lags by 45.0° 0x3 ADC sample lags by 67.5° 0x4 ADC sample lags by 90.0° 0x5 ADC sample lags by 112.5° 0x6 ADC sample lags by 135.0° 0x7 ADC sample lags by 157.5° 0x8 ADC sample lags by 180.0° 0x9 ADC sample lags by 202.5° 0xA ADC sample lags by 225.0° 0xB ADC sample lags by 247.5° 0xC ADC sample lags by 270.0° 0xD ADC sample lags by 292.5° 0xE ADC sample lags by 315.0° 0xF ADC sample lags by 337.5° July 24, 2011 639 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the sample sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. ADC Processor Sample Sequence Initiate (ADCPSSI) ADC0 base: 0x4003.8000 Offset 0x028 Type R/W, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SS3 SS2 SS1 SS0 RO 0 RO 0 RO 0 RO 0 RO 0 WO - WO - WO - WO - reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 SS3 WO - SS3 Initiate Value Description 1 Begin sampling on Sample Sequencer 3, if the sequencer is enabled in the ADCACTSS register. 0 No effect. Only a write by software is valid; a read of this register returns no meaningful data. 2 SS2 WO - SS2 Initiate Value Description 1 Begin sampling on Sample Sequencer 2, if the sequencer is enabled in the ADCACTSS register. 0 No effect. Only a write by software is valid; a read of this register returns no meaningful data. 1 SS1 WO - SS1 Initiate Value Description 1 Begin sampling on Sample Sequencer 1, if the sequencer is enabled in the ADCACTSS register. 0 No effect. Only a write by software is valid; a read of this register returns no meaningful data. 640 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 0 SS0 WO - SS0 Initiate Value Description 1 Begin sampling on Sample Sequencer 0, if the sequencer is enabled in the ADCACTSS register. 0 No effect. Only a write by software is valid; a read of this register returns no meaningful data. July 24, 2011 641 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An AVG=7 provides unpredictable results. ADC Sample Averaging Control (ADCSAC) ADC0 base: 0x4003.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 AVG R/W 0x0 AVG R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hardware Averaging Control Specifies the amount of hardware averaging that will be applied to ADC samples. The AVG field can be any value between 0 and 6. Entering a value of 7 creates unpredictable results. Value Description 0x0 No hardware oversampling 0x1 2x hardware oversampling 0x2 4x hardware oversampling 0x3 8x hardware oversampling 0x4 16x hardware oversampling 0x5 32x hardware oversampling 0x6 64x hardware oversampling 0x7 reserved 642 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 This register provides status and acknowledgement of digital comparator interrupts. One bit is provided for each comparator. ADC Digital Comparator Interrupt Status and Clear (ADCDCISC) ADC0 base: 0x4003.8000 Offset 0x034 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 DCINT7 R/W1C 0 RO 0 RO 0 7 6 5 4 3 2 1 0 DCINT7 DCINT6 DCINT5 DCINT4 DCINT3 DCINT2 DCINT1 DCINT0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Comparator 7 Interrupt Status and Clear Value Description 1 Digital Comparator 7 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 6 DCINT6 R/W1C 0 Digital Comparator 6 Interrupt Status and Clear Value Description 1 Digital Comparator 6 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 5 DCINT5 R/W1C 0 Digital Comparator 5 Interrupt Status and Clear Value Description 1 Digital Comparator 5 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 4 DCINT4 R/W1C 0 Digital Comparator 4 Interrupt Status and Clear Value Description 1 Digital Comparator 4 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. July 24, 2011 643 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 3 DCINT3 R/W1C 0 Description Digital Comparator 3 Interrupt Status and Clear Value Description 1 Digital Comparator 3 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 2 DCINT2 R/W1C 0 Digital Comparator 2 Interrupt Status and Clear Value Description 1 Digital Comparator 2 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 1 DCINT1 R/W1C 0 Digital Comparator 1 Interrupt Status and Clear Value Description 1 Digital Comparator 1 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 0 DCINT0 R/W1C 0 Digital Comparator 0 Interrupt Status and Clear Value Description 1 Digital Comparator 0 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 644 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 13: ADC Control (ADCCTL), offset 0x038 This register configures various ADC module attributes, including the ADC resolution and the voltage reference. The resolution of the ADC defaults to 10-bit for backwards compatibility with other members of the Stellaris family, but can be configured to 12-bit resolution. The voltage reference for the conversion can be the internal 3.0-V reference, an external voltage reference in the range of 2.4 V to 3.06 V, or an external voltage reference in the range of 0.8 V to 1.02 V. ADC Control (ADCCTL) ADC0 base: 0x4003.8000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RES Bit/Field Name Type Reset 31:5 reserved RO 0x0000.000 4 RES R/W 0 R/W 0 reserved RO 0 VREF R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample Resolution Value Description 1 The ADC returns 12-bit data to the FIFOs. 0 The ADC returns 10-bit data to the FIFOs. 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1:0 VREF R/W 0x0 Voltage Reference Select Value Description 0x0 Internal Reference The internal reference as the voltage reference. The conversion range is from 0 V to 3.0 V. 0x1 3.0 V External Reference A 3.0 V external VREFA input is the voltage reference. The ADC conversion range is 0.0 V to the voltage of the VREFA input. 0x2 Reserved 0x3 1.0 V External Reference A 1.0 V external VREFA input is the voltage reference. The ADC conversion range is 0.0 V to three times the voltage of the VREFA input. July 24, 2011 645 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 14: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. This register is 32 bits wide and contains information for eight possible samples. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0) ADC0 base: 0x4003.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 Type Reset RO 0 R/W 0 15 14 RO 0 28 R/W 0 R/W 0 R/W 0 13 12 R/W 0 27 26 RO 0 R/W 0 11 10 24 RO 0 R/W 0 R/W 0 R/W 0 9 8 R/W 0 Bit/Field Name Type Reset 31 reserved RO 0 30:28 MUX7 R/W 0x0 23 22 RO 0 R/W 0 7 6 RO 0 20 R/W 0 R/W 0 R/W 0 5 4 R/W 0 19 18 RO 0 R/W 0 3 2 RO 0 16 R/W 0 R/W 0 1 0 MUX0 reserved R/W 0 17 MUX4 reserved MUX1 reserved R/W 0 21 MUX5 reserved MUX2 reserved R/W 0 25 MUX6 reserved MUX3 reserved Type Reset 29 MUX7 reserved R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. The value set here indicates the corresponding pin, for example, a value of 0x1 indicates the input is AIN1. 27 reserved RO 0 26:24 MUX6 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7th Sample Input Select The MUX6 field is used during the seventh sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 23 reserved RO 0 22:20 MUX5 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6th Sample Input Select The MUX5 field is used during the sixth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 646 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 18:16 MUX4 R/W 0x0 Description 5th Sample Input Select The MUX4 field is used during the fifth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 15 reserved RO 0 14:12 MUX3 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Input Select The MUX3 field is used during the fourth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 11 reserved RO 0 10:8 MUX2 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3rd Sample Input Select The MUX2 field is used during the third sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 7 reserved RO 0 6:4 MUX1 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2nd Sample Input Select The MUX1 field is used during the second sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 3 reserved RO 0 2:0 MUX0 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select The MUX0 field is used during the first sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. July 24, 2011 647 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 15: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with a sample sequencer. When configuring a sample sequence, the END bit must be set for the final sample, whether it be after the first sample, eighth sample, or any sample in between. This register is 32 bits wide and contains information for eight possible samples. ADC Sample Sequence Control 0 (ADCSSCTL0) ADC0 base: 0x4003.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 Type Reset Type Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31 TS7 R/W 0 Description 8th Sample Temp Sensor Select Value Description 30 IE7 R/W 0 1 The temperature sensor is read during the eighth sample of the sample sequence. 0 The input pin specified by the ADCSSMUXn register is read during the eighth sample of the sample sequence. 8th Sample Interrupt Enable Value Description 1 The raw interrupt signal (INR0 bit) is asserted at the end of the eighth sample's conversion. If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to the interrupt controller. 0 The raw interrupt is not asserted to the interrupt controller. It is legal to have multiple samples within a sequence generate interrupts. 29 END7 R/W 0 8th Sample is End of Sequence Value Description 1 The eighth sample is the last sample of the sequence. 0 Another sample in the sequence is the final sample. It is possible to end the sequence on any sample position. Software must set an ENDn bit somewhere within the sequence. Samples defined after the sample containing a set ENDn bit are not requested for conversion even though the fields may be non-zero. 648 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 28 D7 R/W 0 Description 8th Sample Diff Input Select Value Description 1 The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". 0 The analog inputs are not differentially sampled. Because the temperature sensor does not have a differential option, this bit must not be set when the TS7 bit is set. 27 TS6 R/W 0 7th Sample Temp Sensor Select Same definition as TS7 but used during the seventh sample. 26 IE6 R/W 0 7th Sample Interrupt Enable Same definition as IE7 but used during the seventh sample. 25 END6 R/W 0 7th Sample is End of Sequence Same definition as END7 but used during the seventh sample. 24 D6 R/W 0 7th Sample Diff Input Select Same definition as D7 but used during the seventh sample. 23 TS5 R/W 0 6th Sample Temp Sensor Select Same definition as TS7 but used during the sixth sample. 22 IE5 R/W 0 6th Sample Interrupt Enable Same definition as IE7 but used during the sixth sample. 21 END5 R/W 0 6th Sample is End of Sequence Same definition as END7 but used during the sixth sample. 20 D5 R/W 0 6th Sample Diff Input Select Same definition as D7 but used during the sixth sample. 19 TS4 R/W 0 5th Sample Temp Sensor Select Same definition as TS7 but used during the fifth sample. 18 IE4 R/W 0 5th Sample Interrupt Enable Same definition as IE7 but used during the fifth sample. 17 END4 R/W 0 5th Sample is End of Sequence Same definition as END7 but used during the fifth sample. 16 D4 R/W 0 5th Sample Diff Input Select Same definition as D7 but used during the fifth sample. 15 TS3 R/W 0 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. July 24, 2011 649 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 13 END3 R/W 0 Description 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 TS2 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 10 IE2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 8 D2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 7 TS1 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 6 IE1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 TS0 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 650 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 16: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 18: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 19: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 Important: This register is read-sensitive. See the register description for details. This register contains the conversion results for samples collected with the sample sequencer (the ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1, ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT registers. ADC Sample Sequence Result FIFO n (ADCSSFIFOn) ADC0 base: 0x4003.8000 Offset 0x048 Type RO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 DATA RO 0 RO 0 RO - RO - RO - Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11:0 DATA RO - RO - RO - RO - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Conversion Result Data July 24, 2011 651 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C Register 23: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC This register provides a window into the sample sequencer, providing full/empty status information as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty FIFO with the head and tail pointers both pointing to index 0. The ADCSSFSTAT0 register provides status on FIFO0, which has 8 entries; ADCSSFSTAT1 on FIFO1, which has 4 entries; ADCSSFSTAT2 on FIFO2, which has 4 entries; and ADCSSFSTAT3 on FIFO3 which has a single entry. ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0) ADC0 base: 0x4003.8000 Offset 0x04C Type RO, reset 0x0000.0100 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RO 0 FULL RO 0 RO 0 reserved RO 0 RO 0 EMPTY RO 0 Bit/Field Name Type Reset 31:13 reserved RO 0x0000.0 12 FULL RO 0 RO 1 HPTR TPTR Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Full Value Description 11:9 reserved RO 0x0 8 EMPTY RO 1 1 The FIFO is currently full. 0 The FIFO is not currently full. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Empty Value Description 1 The FIFO is currently empty. 0 The FIFO is not currently empty. 652 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 7:4 HPTR RO 0x0 Description FIFO Head Pointer This field contains the current "head" pointer index for the FIFO, that is, the next entry to be written. Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and 0x0 for FIFO3. 3:0 TPTR RO 0x0 FIFO Tail Pointer This field contains the current "tail" pointer index for the FIFO, that is, the next entry to be read. Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and 0x0 for FIFO3. July 24, 2011 653 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 24: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 This register determines whether the sample from the given conversion on Sample Sequence 0 is saved in the Sample Sequence FIFO0 or sent to the digital comparator unit. ADC Sample Sequence 0 Operation (ADCSSOP0) ADC0 base: 0x4003.8000 Offset 0x050 Type R/W, reset 0x0000.0000 31 30 29 reserved Type Reset 27 S7DCOP 26 25 reserved 24 23 S6DCOP 22 21 reserved 20 19 S5DCOP 18 17 reserved 16 S4DCOP RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Type Reset 28 RO 0 RO 0 S3DCOP RO 0 R/W 0 reserved RO 0 RO 0 S2DCOP RO 0 Bit/Field Name Type Reset 31:29 reserved RO 0x0 28 S7DCOP R/W 0 R/W 0 reserved RO 0 RO 0 S1DCOP RO 0 R/W 0 reserved RO 0 RO 0 S0DCOP RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 7 Digital Comparator Operation Value Description 27:25 reserved RO 0x0 24 S6DCOP R/W 0 1 The eighth sample is sent to the digital comparator unit specified by the S7DCSEL bit in the ADCSSDC0 register, and the value is not written to the FIFO. 0 The eighth sample is saved in Sample Sequence FIFO0. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 6 Digital Comparator Operation Same definition as S7DCOP but used during the seventh sample. 23:21 reserved RO 0x0 20 S5DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 5 Digital Comparator Operation Same definition as S7DCOP but used during the sixth sample. 19:17 reserved RO 0x0 16 S4DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 4 Digital Comparator Operation Same definition as S7DCOP but used during the fifth sample. 15:13 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 654 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 12 S3DCOP R/W 0 Description Sample 3 Digital Comparator Operation Same definition as S7DCOP but used during the fourth sample. 11:9 reserved RO 0x0 8 S2DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 2 Digital Comparator Operation Same definition as S7DCOP but used during the third sample. 7:5 reserved RO 0x0 4 S1DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 1 Digital Comparator Operation Same definition as S7DCOP but used during the second sample. 3:1 reserved RO 0x0 0 S0DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 0 Digital Comparator Operation Same definition as S7DCOP but used during the first sample. July 24, 2011 655 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 25: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 This register determines which digital comparator receives the sample from the given conversion on Sample Sequence 0, if the corresponding SnDCOP bit in the ADCSSOP0 register is set. ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0) ADC0 base: 0x4003.8000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 S7DCSEL Type Reset 24 23 22 21 20 19 S5DCSEL 18 17 16 S4DCSEL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S3DCSEL Type Reset 25 S6DCSEL R/W 0 R/W 0 S2DCSEL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:28 S7DCSEL R/W 0x0 S1DCSEL R/W 0 R/W 0 R/W 0 R/W 0 S0DCSEL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Sample 7 Digital Comparator Select When the S7DCOP bit in the ADCSSOP0 register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the eighth sample from Sample Sequencer 0. Note: Values not listed are reserved. Value Description 27:24 S6DCSEL R/W 0x0 0x0 Digital Comparator Unit 0 (ADCDCCMP0 and ADCDCCTL0) 0x1 Digital Comparator Unit 1 (ADCDCCMP1 and ADCDCCTL1) 0x2 Digital Comparator Unit 2 (ADCDCCMP2 and ADCDCCTL2) 0x3 Digital Comparator Unit 3 (ADCDCCMP3 and ADCDCCTL3) 0x4 Digital Comparator Unit 4 (ADCDCCMP4 and ADCDCCTL4) 0x5 Digital Comparator Unit 5 (ADCDCCMP5 and ADCDCCTL5) 0x6 Digital Comparator Unit 6 (ADCDCCMP6 and ADCDCCTL6) 0x7 Digital Comparator Unit 7 (ADCDCCMP7 and ADCDCCTL7) Sample 6 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the seventh sample. 23:20 S5DCSEL R/W 0x0 Sample 5 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the sixth sample. 19:16 S4DCSEL R/W 0x0 Sample 4 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the fifth sample. 15:12 S3DCSEL R/W 0x0 Sample 3 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the fourth sample. 656 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 11:8 S2DCSEL R/W 0x0 Description Sample 2 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the third sample. 7:4 S1DCSEL R/W 0x0 Sample 1 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the second sample. 3:0 S0DCSEL R/W 0x0 Sample 0 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the first sample. July 24, 2011 657 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 26: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 27: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. These registers are 16 bits wide and contain information for four possible samples. See the ADCSSMUX0 register on page 646 for detailed bit descriptions. The ADCSSMUX1 register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2. ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1) ADC0 base: 0x4003.8000 Offset 0x060 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset MUX3 reserved Type Reset RO 0 R/W 0 R/W 0 MUX2 reserved R/W 0 RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:15 reserved RO 0x0000 14:12 MUX3 R/W 0x0 11 reserved RO 0 10:8 MUX2 R/W 0x0 7 reserved RO 0 6:4 MUX1 R/W 0x0 3 reserved RO 0 2:0 MUX0 R/W 0x0 MUX1 reserved R/W 0 RO 0 R/W 0 R/W 0 MUX0 reserved R/W 0 RO 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3rd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2nd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select 658 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 28: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 29: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set for the final sample, whether it be after the first sample, fourth sample, or any sample in between. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0 register on page 648 for detailed bit descriptions. The ADCSSCTL1 register configures Sample Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2. ADC Sample Sequence Control 1 (ADCSSCTL1) ADC0 base: 0x4003.8000 Offset 0x064 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 TS3 IE3 END3 D3 TS2 IE2 END2 D2 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TS1 IE1 END1 D1 TS0 IE0 END0 D0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 TS3 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 13 END3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 TS2 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 10 IE2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 8 D2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 7 TS1 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. July 24, 2011 659 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 6 IE1 R/W 0 Description 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 TS0 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 660 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 30: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 Register 31: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 This register determines whether the sample from the given conversion on Sample Sequence n is saved in the Sample Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1 register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2. ADC Sample Sequence 1 Operation (ADCSSOP1) ADC0 base: 0x4003.8000 Offset 0x070 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset reserved Type Reset RO 0 RO 0 S3DCOP RO 0 R/W 0 reserved RO 0 RO 0 S2DCOP RO 0 Bit/Field Name Type Reset 31:13 reserved RO 0x0000.0 12 S3DCOP R/W 0 R/W 0 reserved RO 0 RO 0 S1DCOP RO 0 R/W 0 reserved RO 0 RO 0 S0DCOP RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 3 Digital Comparator Operation Value Description 11:9 reserved RO 0x0 8 S2DCOP R/W 0 1 The fourth sample is sent to the digital comparator unit specified by the S3DCSEL bit in the ADCSSDC0n register, and the value is not written to the FIFO. 0 The fourth sample is saved in Sample Sequence FIFOn. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 2 Digital Comparator Operation Same definition as S3DCOP but used during the third sample. 7:5 reserved RO 0x0 4 S1DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 1 Digital Comparator Operation Same definition as S3DCOP but used during the second sample. 3:1 reserved RO 0x0 0 S0DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 0 Digital Comparator Operation Same definition as S3DCOP but used during the first sample. July 24, 2011 661 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 32: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 Register 33: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 These registers determine which digital comparator receives the sample from the given conversion on Sample Sequence n if the corresponding SnDCOP bit in the ADCSSOPn register is set. The ADCSSDC1 register controls the selection for Sample Sequencer 1 and the ADCSSDC2 register controls the selection for Sample Sequencer 2. ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1) ADC0 base: 0x4003.8000 Offset 0x074 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset S3DCSEL Type Reset S2DCSEL R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15:12 S3DCSEL R/W 0x0 S1DCSEL R/W 0 S0DCSEL R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 3 Digital Comparator Select When the S3DCOP bit in the ADCSSOPn register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the eighth sample from Sample Sequencer n. Note: Values not listed are reserved. Value Description 11:8 S2DCSEL R/W 0x0 0x0 Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0) 0x1 Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1) 0x2 Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2) 0x3 Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3) 0x4 Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4) 0x5 Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5) 0x6 Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6) 0x7 Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7) Sample 2 Digital Comparator Select This field has the same encodings as S3DCSEL but is used during the third sample. 662 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 7:4 S1DCSEL R/W 0x0 Description Sample 1 Digital Comparator Select This field has the same encodings as S3DCSEL but is used during the second sample. 3:0 S0DCSEL R/W 0x0 Sample 0 Digital Comparator Select This field has the same encodings as S3DCSEL but is used during the first sample. July 24, 2011 663 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 34: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register defines the analog input configuration for the sample executed with Sample Sequencer 3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSMUX0 register on page 646 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) ADC0 base: 0x4003.8000 Offset 0x0A0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 MUX0 R/W 0 MUX0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select 664 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 35: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for a sample executed with Sample Sequencer 3. The END0 bit is always set as this sequencer can execute only one sample. This register is 4 bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 648 for detailed bit descriptions. ADC Sample Sequence Control 3 (ADCSSCTL3) ADC0 base: 0x4003.8000 Offset 0x0A4 Type R/W, reset 0x0000.0002 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TS0 IE0 END0 D0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 TS0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 1 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Because this sequencer has only one entry, this bit must be set. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. July 24, 2011 665 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 36: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 This register determines whether the sample from the given conversion on Sample Sequence 3 is saved in the Sample Sequence 3 FIFO or sent to the digital comparator unit. ADC Sample Sequence 3 Operation (ADCSSOP3) ADC0 base: 0x4003.8000 Offset 0x0B0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 S0DCOP R/W 0 RO 0 S0DCOP R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 0 Digital Comparator Operation Value Description 1 The sample is sent to the digital comparator unit specified by the S0DCSEL bit in the ADCSSDC03 register, and the value is not written to the FIFO. 0 The sample is saved in Sample Sequence FIFO3. 666 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 37: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 This register determines which digital comparator receives the sample from the given conversion on Sample Sequence 3 if the corresponding SnDCOP bit in the ADCSSOP3 register is set. ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3) ADC0 base: 0x4003.8000 Offset 0x0B4 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3:0 S0DCSEL R/W 0x0 S0DCSEL RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 0 Digital Comparator Select When the S0DCOP bit in the ADCSSOP3 register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the sample from Sample Sequencer 3. Note: Values not listed are reserved. Value Description 0x0 Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0) 0x1 Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1) 0x2 Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2) 0x3 Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3) 0x4 Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4) 0x5 Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5) 0x6 Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6) 0x7 Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7) July 24, 2011 667 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 38: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 This register provides the ability to reset any of the digital comparator interrupt or trigger functions back to their initial conditions. Resetting these functions ensures that the data that is being used by the interrupt and trigger functions in the digital comparator unit is not stale. ADC Digital Comparator Reset Initial Conditions (ADCDCRIC) ADC0 base: 0x4003.8000 Offset 0xD00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 DCTRIG7 DCTRIG6 DCTRIG5 DCTRIG4 DCTRIG3 DCTRIG2 DCTRIG1 DCTRIG0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 DCINT7 DCINT6 DCINT5 DCINT4 DCINT3 DCINT2 DCINT1 DCINT0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23 DCTRIG7 R/W 0 Digital Comparator Trigger 7 Value Description 1 Resets the Digital Comparator 7 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. After setting this bit, software should wait until the bit clears before continuing. 22 DCTRIG6 R/W 0 Digital Comparator Trigger 6 Value Description 1 Resets the Digital Comparator 6 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 668 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 21 DCTRIG5 R/W 0 Description Digital Comparator Trigger 5 Value Description 1 Resets the Digital Comparator 5 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 20 DCTRIG4 R/W 0 Digital Comparator Trigger 4 Value Description 1 Resets the Digital Comparator 4 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 19 DCTRIG3 R/W 0 Digital Comparator Trigger 3 Value Description 1 Resets the Digital Comparator 3 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 18 DCTRIG2 R/W 0 Digital Comparator Trigger 2 Value Description 1 Resets the Digital Comparator 2 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. July 24, 2011 669 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 17 DCTRIG1 R/W 0 Description Digital Comparator Trigger 1 Value Description 1 Resets the Digital Comparator 1 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 16 DCTRIG0 R/W 0 Digital Comparator Trigger 0 Value Description 1 Resets the Digital Comparator 0 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 15:8 reserved RO 0x00 7 DCINT7 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Comparator Interrupt 7 Value Description 1 Resets the Digital Comparator 7 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 6 DCINT6 R/W 0 Digital Comparator Interrupt 6 Value Description 1 Resets the Digital Comparator 6 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 670 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 5 DCINT5 R/W 0 Description Digital Comparator Interrupt 5 Value Description 1 Resets the Digital Comparator 5 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 4 DCINT4 R/W 0 Digital Comparator Interrupt 4 Value Description 1 Resets the Digital Comparator 4 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 3 DCINT3 R/W 0 Digital Comparator Interrupt 3 Value Description 1 Resets the Digital Comparator 3 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 2 DCINT2 R/W 0 Digital Comparator Interrupt 2 Value Description 1 Resets the Digital Comparator 2 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. July 24, 2011 671 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 1 DCINT1 R/W 0 Description Digital Comparator Interrupt 1 Value Description 1 Resets the Digital Comparator 1 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 DCINT0 R/W 0 Digital Comparator Interrupt 0 Value Description 1 Resets the Digital Comparator 0 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 672 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 39: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 Register 40: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 Register 41: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 Register 42: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C Register 43: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 Register 44: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 Register 45: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 Register 46: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C This register provides the comparison encodings that generate an interrupt. ADC Digital Comparator Control 0 (ADCDCCTL0) ADC0 base: 0x4003.8000 Offset 0xE00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 CIE Bit/Field Name Type Reset 31:5 reserved RO 0x0000.0 4 CIE R/W 0 CIC R/W 0 CIM R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparison Interrupt Enable Value Description 1 Enables the comparison interrupt. The ADC conversion data is used to determine if an interrupt should be generated according to the programming of the CIC and CIM fields. 0 Disables the comparison interrupt. ADC conversion data has no effect on interrupt generation. July 24, 2011 673 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 3:2 CIC R/W 0x0 Description Comparison Interrupt Condition This field specifies the operational region in which an interrupt is generated when the ADC conversion data is compared against the values of COMP0 and COMP1. The COMP0 and COMP1 fields are defined in the ADCDCCMPx registers. Value Description 0x0 Low Band ADC Data < COMP0 ≤ COMP1 0x1 Mid Band COMP0 ≤ ADC Data < COMP1 0x2 reserved 0x3 High Band COMP0 < COMP1 ≤ ADC Data 1:0 CIM R/W 0x0 Comparison Interrupt Mode This field specifies the mode by which the interrupt comparison is made. Value Description 0x0 Always This mode generates an interrupt every time the ADC conversion data falls within the selected operational region. 0x1 Once This mode generates an interrupt the first time that the ADC conversion data enters the selected operational region. 0x2 Hysteresis Always This mode generates an interrupt when the ADC conversion data falls within the selected operational region and continues to generate the interrupt until the hysteresis condition is cleared by entering the opposite operational region. 0x3 Hysteresis Once This mode generates an interrupt the first time that the ADC conversion data falls within the selected operational region. No additional interrupts are generated until the hysteresis condition is cleared by entering the opposite operational region. 674 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 47: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 Register 48: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 Register 49: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 Register 50: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C Register 51: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 Register 52: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 Register 53: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 Register 54: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C This register defines the comparison values that are used to determine if the ADC conversion data falls in the appropriate operating region. Note: The value in the COMP1 field must be greater than or equal to the value in the COMP0 field or unexpected results can occur. If the RES bit in the ADCCTL register is clear, selecting 10-bit resolution, use only bits [25:16] in the COMP1 field and bits [9:0] in the COMP0 field; otherwise unexpected results can occur. ADC Digital Comparator Range 0 (ADCDCCMP0) ADC0 base: 0x4003.8000 Offset 0xE40 Type R/W, reset 0x0000.0000 31 30 RO 0 RO 0 15 14 RO 0 RO 0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset COMP1 reserved Type Reset COMP0 RO 0 Bit/Field Name Type Reset 31:28 reserved RO 0x0 27:16 COMP1 R/W 0x000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Compare 1 The value in this field is compared against the ADC conversion data. The result of the comparison is used to determine if the data lies within the high-band region. Note that the value of COMP1 must be greater than or equal to the value of COMP0. 15:12 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 675 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 11:0 COMP0 R/W 0x000 Compare 0 The value in this field is compared against the ADC conversion data. The result of the comparison is used to determine if the data lies within the low-band region. 676 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 14 Universal Asynchronous Receivers/Transmitters (UARTs) ® The Stellaris LM3S1F11 controller includes three Universal Asynchronous Receiver/Transmitter (UART) with the following features: ■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by 16) and 10 Mbps for high speed (divide by 8) ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Standard asynchronous communication bits for start, stop, and parity ■ Line-break generation and detection ■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Support for communication with ISO 7816 smart cards ■ Full modem handshake support (on UART1) ■ LIN protocol support ■ Standard FIFO-level and End-of-Transmission interrupts ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level July 24, 2011 677 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level 14.1 Block Diagram Figure 14-1. UART Module Block Diagram System Clock DMA Request DMA Control UARTDMACTL Interrupt Interrupt Control Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 14.2 UARTIFLS UARTIM UARTMIS UARTRIS UARTICR TxFIFO 16 x 8 . . . Baud Rate Generator UARTDR UARTRSR/ECR UARTFR UARTLCRH UARTCTL UARTILPR UARTLCTL UARTLSS UARTLTIM UnTx UARTIBRD UARTFBRD Control/Status Transmitter (with SIR Transmit Encoder) RxFIFO 16 x 8 Receiver (with SIR Receive Decoder) UnRx . . . Signal Description The following table lists the external signals of the UART module and describes the function of each. The UART signals are alternate functions for some GPIO signals and default to be GPIO signals at reset, with the exception of the U0Rx and U0Tx pins which default to the UART function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 424) should be set to choose the UART function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 442) to assign the UART signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 400. 678 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 14-1. Signals for UART (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description U0Rx 26 PA0 (1) I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 PA1 (1) O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS 2 10 34 PE6 (9) PD0 (9) PA6 (9) I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD 1 11 35 PE7 (9) PD1 (9) PA7 (9) I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR 47 PF0 (9) I TTL UART module 1 Data Set Ready modem output control line. U1DTR 40 100 PG5 (10) PD7 (9) O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI 37 41 97 PG6 (10) PG4 (10) PD4 (9) I TTL UART module 1 Ring Indicator modem status input signal. U1RTS 43 61 PF6 (10) PF1 (9) O TTL UART module 1 Request to Send modem flow control output line. U1Rx 10 12 23 26 66 92 PD0 (5) PD2 (1) PC6 (5) PA0 (9) PB0 (5) PB4 (7) I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 11 13 22 27 67 91 PD1 (5) PD3 (1) PC7 (5) PA1 (9) PB1 (5) PB5 (7) O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx 10 19 92 98 PD0 (4) PG0 (1) PB4 (4) PD5 (9) I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx 6 11 18 99 PE4 (5) PD1 (4) PG1 (1) PD6 (9) O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 14-2. Signals for UART (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description U0Rx L3 PA0 (1) I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 PA1 (1) O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS A1 G1 L6 PE6 (9) PD0 (9) PA6 (9) I TTL UART module 1 Clear To Send modem flow control input signal. July 24, 2011 679 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Table 14-2. Signals for UART (108BGA) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description U1DCD B1 G2 M6 PE7 (9) PD1 (9) PA7 (9) I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR M9 PF0 (9) I TTL UART module 1 Data Set Ready modem output control line. U1DTR M7 A2 PG5 (10) PD7 (9) O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI L7 K3 B5 PG6 (10) PG4 (10) PD4 (9) I TTL UART module 1 Ring Indicator modem status input signal. U1RTS M8 H12 PF6 (10) PF1 (9) O TTL UART module 1 Request to Send modem flow control output line. U1Rx G1 H2 M2 L3 E12 A6 PD0 (5) PD2 (1) PC6 (5) PA0 (9) PB0 (5) PB4 (7) I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx G2 H1 L2 M3 D12 B7 PD1 (5) PD3 (1) PC7 (5) PA1 (9) PB1 (5) PB5 (7) O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx G1 K1 A6 C6 PD0 (4) PG0 (1) PB4 (4) PD5 (9) I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx B2 G2 K2 A3 PE4 (5) PD1 (4) PG1 (1) PD6 (9) O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 14.3 Functional Description Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 704). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. 14.3.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits 680 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 14-2 on page 681 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 14-2. UART Character Frame UnTX LSB 1 5-8 data bits 0 n Parity bit if enabled Start 14.3.2 1-2 stop bits MSB Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 700) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 701). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.) BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate) where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in UARTCTL is clear) or 8 (if HSE is set). The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5) in UARTCTL). This reference clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations. Note that the state of the HSE bit has no effect on clock generation in ISO 7816 smart card mode (when the SMART bit in the UARTCTL register is set). Along with the UART Line Control, High Byte (UARTLCRH) register (see page 702), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write July 24, 2011 681 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) ■ UARTFBRD write and UARTLCRH write 14.3.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 696) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL (described in “Transmit/Receive Logic” on page 680). The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE clear) or the fourth cycle of Baud 8 (HSE set), otherwise it is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one bit period later) according to the programmed length of the data characters and value of the HSE bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO along with any error bits associated with that word. 14.3.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream and a half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output and decoded input to the UART. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol. These signals should be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception.The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as a high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW and driving the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. See page 699 for more information on IrDA low-power pulse-duration configuration. Figure 14-3 on page 683 shows the UART transmit and receive signals, with and without IrDA modulation. 682 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 14-3. IrDA Data Modulation Data bits Start bit UnTx 1 0 0 0 1 Stop bit 0 0 1 1 1 UnTx with IrDA 3 16 Bit period Bit period UnRx with IrDA UnRx 0 1 0 Start 1 0 0 1 1 Data bits 0 1 Stop In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10-ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency or receiver setup time. 14.3.5 ISO 7816 Support The UART offers basic support to allow communication with an ISO 7816 smartcard. When bit 3 (SMART) of the UARTCTL register is set, the UnTx signal is used as a bit clock, and the UnRx signal is used as the half-duplex communication line connected to the smartcard. A GPIO signal can be used to generate the reset signal to the smartcard. The remaining smartcard signals should be provided by the system design. The maximum clock rate in this mode is system clock / 16. When using ISO 7816 mode, the UARTLCRH register must be set to transmit 8-bit words (WLEN bits 6:5 configured to 0x3) with EVEN parity (PEN set and EPS set). In this mode, the UART automatically uses 2 stop bits, and the STP2 bit of the UARTLCRH register is ignored. If a parity error is detected during transmission, UnRx is pulled Low during the second stop bit. In this case, the UART aborts the transmission, flushes the transmit FIFO and discards any data it contains, and raises a parity error interrupt, allowing software to detect the problem and initiate retransmission of the affected data. Note that the UART does not support automatic retransmission in this case. 14.3.6 Modem Handshake Support This section describes how to configure and use the modem flow control and status signals for UART1 when connected as a DTE (data terminal equipment) or as a DCE (data communications equipment). In general, a modem is a DCE and a computing device that connects to a modem is the DTE. July 24, 2011 683 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) 14.3.6.1 Signaling The status signals provided by UART1 differ based on whether the UART is used as a DTE or DCE. When used as a DTE, the modem flow control and status signals are defined as: ■ U1CTS is Clear To Send ■ U1DSR is Data Set Ready ■ U1DCD is Data Carrier Detect ■ U1RI is Ring Indicator ■ U1RTS is Request To Send ■ U1DTR is Data Terminal Ready When used as a DCE, the the modem flow control and status signals are defined as: ■ U1CTS is Request To Send ■ U1DSR is Data Terminal Ready ■ U1RTS is Clear To Send ■ U1DTR is Data Set Ready Note that the support for DCE functions Data Carrier Detect and Ring Indicator are not provided. If these signals are required, their function can be emulated by using a general-purpose I/O signal and providing software support. 14.3.6.2 Flow Control Flow control can be accomplished by either hardware or software. The following sections describe the different methods. Hardware Flow Control (RTS/CTS) Hardware flow control between two devices is accomplished by connecting the U1RTS output to the Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the receiving device to the U1CTS input. The U1CTS input controls the transmitter. The transmitter may only transmit data when the U1CTS input is asserted. The U1RTS output signal indicates the state of the receive FIFO. U1CTS remains asserted until the preprogrammed watermark level is reached, indicating that the Receive FIFO has no space to store additional characters. The UARTCTL register bits 15 (CTSEN) and 14 (RTSEN) specify the flow control mode as shown in Table 14-3 on page 684. Table 14-3. Flow Control Mode Description CTSEN RTSEN 1 1 RTS and CTS flow control enabled 1 0 Only CTS flow control enabled 0 1 Only RTS flow control enabled 684 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 14-3. Flow Control Mode (continued) CTSEN RTSEN 0 0 Description Both RTS and CTS flow control disabled Note that when RTSEN is 1, software cannot modify the U1RTS output value through the UARTCTL register Request to Send (RTS) bit, and the status of the RTS bit should be ignored. Software Flow Control (Modem Status Interrupts) Software flow control between two devices is accomplished by using interrupts to indicate the status of the UART. Interrupts may be generated for the U1DSR, U1DCD, U1CTS, and U1RI signals using bits 3:0 of the UARTIM register, respectively. The raw and masked interrupt status may be checked using the UARTRIS and UARTMIS register. These interrupts may be cleared using the UARTICR register. 14.3.7 LIN Support The UART module offers hardware support for the LIN protocol as either a master or a slave. The LIN mode is enabled by setting the LIN bit in the UARTCTL register. A LIN message is identified by the use of a Sync Break at the beginning of the message. The Sync Break is a transmission of a series of 0s. The Sync Break is followed by the Sync data field (0x55). Figure 14-4 on page 685 illustrates the structure of a LIN message. Figure 14-4. LIN Message Message Frame Header Synch Break Synch Field Response Ident Field Data Field(s) In-Frame Response Data Field Checksum Field Interbyte Space The UART should be configured as followed to operate in LIN mode: 1. Configure the UART for 1 start bit, 8 data bits, no parity, and 1 stop bit. Enable the Transmit FIFO. 2. Set the LIN bit in the UARTCTL register. When preparing to send a LIN message, the TXFIFO should contain the Sync data (0x55) at FIFO location 0 and the Identifier data at location 1, followed by the data to be transmitted, and with the checksum in the final FIFO entry. July 24, 2011 685 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) 14.3.7.1 LIN Master The UART is enabled to be the LIN master by setting the MASTER bit in the UARTLCTL register. The length of the Sync Break is programmable using the BLEN field in the UARTLCTL register and can be 13-16 bits (baud clock cycles). 14.3.7.2 LIN Slave The LIN UART slave is required to adjust its baud rate to that of the LIN master. In slave mode, the LIN UART recognizes the Sync Break, which must be at least 13 bits in duration. A timer is provided to capture timing data on the 1st and 5th falling edges of the Sync field so that the baud rate can be adjusted to match the master. After detecting a Sync Break, the UART waits for the synchronization field. The first falling edge generates an interrupt using the LME1RIS bit in the UARTRIS register, and the timer value is captured and stored in the UARTLSS register (T1). On the fifth falling edge, a second interrupt is generated using the LME5RIS bit in the UARTRIS register, and the timer value is captured again (T2). The actual baud rate can be calculated using (T2-T1)/8, and the local baud rate should be adjusted as needed. Figure 14-5 on page 686 illustrates the synchronization field. Figure 14-5. LIN Synchronization Field Sync Break 0 1 2 3 4 5 6 7 8 Synch Field 9 10 11 12 13 0 1 2 Edge 1 3 4 5 6 Edge 5 7 8 8 Tbit Sync Break Detect 14.3.8 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 691). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 702). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 696) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 708). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include ⅛, ¼, ½, ¾, and ⅞. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 14.3.9 Interrupts The UART can generate interrupts when the following conditions are observed: 686 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ Overrun Error ■ Break Error ■ Parity Error ■ Framing Error ■ Receive Timeout ■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer) ■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 717). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM) register (see page 710) by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 714). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a 1 to the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 720). The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register. 14.3.10 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work by setting the LBE bit in the UARTCTL register (see page 704). In loopback mode, data transmitted on the UnTx output is received on the UnRx input. Note that the LBE bit should be set before the UART is enabled. 14.3.11 DMA Operation The UART provides an interface to the μDMA controller with separate channels for transmit and receive. The DMA operation of the UART is enabled through the UART DMA Control (UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger level configured in the UARTIFLS register. For the transmit channel, a single transfer request is asserted whenever there is at least one empty location in the transmit FIFO. The burst request is asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The single and burst DMA transfer requests are handled automatically by the μDMA controller depending on how the DMA channel is configured. To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control (UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit July 24, 2011 687 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive error occurs, the DMA receive requests are automatically disabled. This error condition can be cleared by clearing the appropriate UART error interrupt. If DMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The interrupt occurs on the UART interrupt vector. Therefore, if interrupts are used for UART operation and DMA is enabled, the UART interrupt handler must be designed to handle the μDMA completion interrupt. See “Micro Direct Memory Access (μDMA)” on page 340 for more details about programming the μDMA controller. 14.4 Initialization and Configuration To enable and initialize the UART, the following steps are necessary: 1. The peripheral clock must be enabled by setting the UART0, UART1, or UART2 bits in the RCGC1 register (see page 246). 2. The clock to the appropriate GPIO module must be enabled via the RCGC2 register in the System Control module (see page 255). 3. Set the GPIO AFSEL bits for the appropriate pins (see page 424). To determine which GPIOs to configure, see Table 19-4 on page 848. 4. Configure the GPIO current level and/or slew rate as specified for the mode selected (see page 426 and page 434). 5. Configure the PMCn fields in the GPIOPCTL register to assign the UART signals to the appropriate pins (see page 442 and Table 19-5 on page 854). To use the UART, the peripheral clock must be enabled by setting the appropriate bit in the RCGC1 register (page 246). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2 register (page 255) in the System Control module. To find out which GPIO port to enable, refer to Table 19-5 on page 854. This section discusses the steps that are required to use a UART module. For this example, the UART clock is assumed to be 20 MHz, and the desired UART configuration is: ■ 115200 baud rate ■ Data length of 8 bits ■ One stop bit ■ No parity ■ FIFOs disabled ■ No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), because the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 681, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 688 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller which means that the DIVINT field of the UARTIBRD register (see page 700) should be set to 10 decimal or 0xA. The value to be loaded into the UARTFBRD register (see page 701) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 340) and enable the DMA option(s) in the UARTDMACTL register. 6. Enable the UART by setting the UARTEN bit in the UARTCTL register. 14.5 Register Map Table 14-4 on page 689 lists the UART registers. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address: ■ UART0: 0x4000.C000 ■ UART1: 0x4000.D000 ■ UART2: 0x4000.E000 Note that the UART module clock must be enabled before the registers can be programmed (see page 246). There must be a delay of 3 system clocks after the UART module clock is enabled before any UART module registers are accessed. Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 704) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 14-4. UART Register Map Offset Name Type Reset Description See page 0x000 UARTDR R/W 0x0000.0000 UART Data 691 0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 693 0x018 UARTFR RO 0x0000.0090 UART Flag 696 0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 699 0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 700 0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 701 0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 702 0x030 UARTCTL R/W 0x0000.0300 UART Control 704 July 24, 2011 689 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Table 14-4. UART Register Map (continued) Name Type Reset 0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 708 0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 710 0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 714 0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 717 0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 720 0x048 UARTDMACTL R/W 0x0000.0000 UART DMA Control 722 0x090 UARTLCTL R/W 0x0000.0000 UART LIN Control 723 0x094 UARTLSS RO 0x0000.0000 UART LIN Snap Shot 724 0x098 UARTLTIM RO 0x0000.0000 UART LIN Timer 725 0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 726 0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 727 0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 728 0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 729 0xFE0 UARTPeriphID0 RO 0x0000.0060 UART Peripheral Identification 0 730 0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 731 0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 732 0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 733 0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 734 0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 735 0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 736 0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 737 14.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. 690 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: UART Data (UARTDR), offset 0x000 Important: This register is read-sensitive. See the register description for details. This register is the data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 OE BE PE FE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 OE RO 0 DATA Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Value Description 10 BE RO 0 1 New data was received when the FIFO was full, resulting in data loss. 0 No data has been lost due to a FIFO overrun. UART Break Error Value Description 1 A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0 No break condition has occurred In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state), and the next valid start bit is received. July 24, 2011 691 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 9 PE RO 0 Description UART Parity Error Value Description 1 The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0 No parity error has occurred In FIFO mode, this error is associated with the character at the top of the FIFO. 8 FE RO 0 UART Framing Error Value Description 7:0 DATA R/W 0x00 1 The received character does not have a valid stop bit (a valid stop bit is 1). 0 No framing error has occurred Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 692 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared on reset. Read-Only Status Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 OE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 OE BE PE FE RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Value Description 1 New data was received when the FIFO was full, resulting in data loss. 0 No data has been lost due to a FIFO overrun. This bit is cleared by a write to UARTECR. The FIFO contents remain valid because no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. July 24, 2011 693 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 2 BE RO 0 Description UART Break Error Value Description 1 A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0 No break condition has occurred This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 1 PE RO 0 UART Parity Error Value Description 1 The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0 No parity error has occurred This bit is cleared to 0 by a write to UARTECR. 0 FE RO 0 UART Framing Error Value Description 1 The received character does not have a valid stop bit (a valid stop bit is 1). 0 No framing error has occurred This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. Write-Only Error Clear Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset WO 0 DATA 694 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 31:8 reserved WO 0x0000.00 7:0 DATA WO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. July 24, 2011 695 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. The RI, DCD, DSR and CTS bits indicate the modem flow control and status. Note that the modem bits are only implemented on UART1 and are reserved on UART0 and UART2. UART Flag (UARTFR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RI TXFE RXFF TXFF RXFE BUSY DCD DSR CTS RO 0 RO 1 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 RI RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Ring Indicator Value Description 1 The U1RI signal is asserted. 0 The U1RI signal is not asserted. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 7 TXFE RO 1 UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. Value Description 1 If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0 The transmitter has data to transmit. 696 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 6 RXFF RO 0 Description UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. Value Description 1 If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0 5 TXFF RO 0 The receiver can receive data. UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. Value Description 1 If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0 4 RXFE RO 1 The transmitter is not full. UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. Value Description 1 If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0 3 BUSY RO 0 The receiver is not empty. UART Busy Value Description 1 The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. 0 The UART is not busy. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 2 DCD RO 0 Data Carrier Detect Value Description 1 The U1DCD signal is asserted. 0 The U1DCD signal is not asserted. This bit is implemented only on UART1 and is reserved for UART0 and UART2. July 24, 2011 697 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 1 DSR RO 0 Description Data Set Ready Value Description 1 The U1DSR signal is asserted. 0 The U1DSR signal is not asserted. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 0 CTS RO 0 Clear To Send Value Description 1 The U1CTS signal is asserted. 0 The U1CTS signal is not asserted. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 698 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when reset. The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. The divisor must be programmed such that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, resulting in a low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but pulses greater than 1.4 μs are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset ILPDVSR RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 ILPDVSR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. IrDA Low-Power Divisor This field contains the 8-bit low-power divisor value. July 24, 2011 699 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 681 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset DIVINT Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor 700 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 681 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 DIVFRAC Bit/Field Name Type Reset 31:6 reserved RO 0x0000.000 5:0 DIVFRAC R/W 0x0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fractional Baud-Rate Divisor July 24, 2011 701 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 SPS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 SPS R/W 0 RO 0 R/W 0 5 WLEN R/W 0 R/W 0 4 3 2 1 0 FEN STP2 EPS PEN BRK R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 6:5 WLEN R/W 0x0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 4 FEN R/W 0 0x0 5 bits (default) 0x1 6 bits 0x2 7 bits 0x3 8 bits UART Enable FIFOs Value Description 1 The transmit and receive FIFO buffers are enabled (FIFO mode). 0 The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 702 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 3 STP2 R/W 0 Description UART Two Stop Bits Select Value Description 1 Two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. When in 7816 smartcard mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0 2 EPS R/W 0 One stop bit is transmitted at the end of a frame. UART Even Parity Select Value Description 1 Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 0 Odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 1 PEN R/W 0 UART Parity Enable Value Description 0 BRK R/W 0 1 Parity checking and generation is enabled. 0 Parity is disabled and no parity bit is added to the data frame. UART Send Break Value Description 1 A Low level is continually output on the UnTx signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). 0 Normal use. July 24, 2011 703 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set. To enable the UART module, the UARTEN bit must be set. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. Note that bits [15:14,11:10] are only implemented on UART1. These bits are reserved on UART0 and UART2. Note: The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register. 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by clearing bit 4 (FEN) in the line control register (UARTLCRH). 4. Reprogram the control register. 5. Enable the UART. UART Control (UARTCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 Type Reset RO 0 RO 0 RO 0 13 12 15 14 CTSEN RTSEN R/W 0 R/W 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 6 5 4 3 2 1 0 RTS DTR RXE TXE LBE LIN HSE EOT SMART SIRLP SIREN UARTEN R/W 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 704 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 15 CTSEN R/W 0 Description Enable Clear To Send Value Description 1 CTS hardware flow control is enabled. Data is only transmitted when the U1CTS signal is asserted. 0 CTS hardware flow control is disabled. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 14 RTSEN R/W 0 Enable Request to Send Value Description 1 RTS hardware flow control is enabled. Data is only requested (by asserting U1RTS) when the receive FIFO has available entries. 0 RTS hardware flow control is disabled. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 13:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 RTS R/W 0 Request to Send When RTSEN is clear, the status of this bit is reflected on the U1RTS signal. If RTSEN is set, this bit is ignored on a write and should be ignored on read. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 10 DTR R/W 0 Data Terminal Ready This bit sets the state of the U1DTR output. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 9 RXE R/W 1 UART Receive Enable Value Description 1 The receive section of the UART is enabled. 0 The receive section of the UART is disabled. If the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: To enable reception, the UARTEN bit must also be set. July 24, 2011 705 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 8 TXE R/W 1 Description UART Transmit Enable Value Description 1 The transmit section of the UART is enabled. 0 The transmit section of the UART is disabled. If the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: 7 LBE R/W 0 To enable transmission, the UARTEN bit must also be set. UART Loop Back Enable Value Description 6 LIN R/W 0 1 The UnTx path is fed through the UnRx path. 0 Normal operation. LIN Mode Enable Value Description 5 HSE R/W 0 1 The UART operates in LIN mode. 0 Normal operation. High-Speed Enable Value Description 0 The UART is clocked using the system clock divided by 16. 1 The UART is clocked using the system clock divided by 8. Note: System clock used is also dependent on the baud-rate divisor configuration (see page 700) and page 701). The state of this bit has no effect on clock generation in ISO 7816 smart card mode (the SMART bit is set). 4 EOT R/W 0 End of Transmission This bit determines the behavior of the TXRIS bit in the UARTRIS register. Value Description 1 The TXRIS bit is set only after all transmitted data, including stop bits, have cleared the serializer. 0 The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met. 706 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 3 SMART R/W 0 Description ISO 7816 Smart Card Support Value Description 1 The UART operates in Smart Card mode. 0 Normal operation. The application must ensure that it sets 8-bit word length (WLEN set to 0x3) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO 7816 mode. In this mode, the value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. Note that the UART does not support automatic retransmission on parity errors. If a parity error is detected on transmission, all further transmit operations are aborted and software must handle retransmission of the affected byte or message. 2 SIRLP R/W 0 UART SIR Low-Power Mode This bit selects the IrDA encoding mode. Value Description 1 The UART operates in SIR Low-Power mode. Low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. 0 Low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. Setting this bit uses less power, but might reduce transmission distances. See page 699 for more information. 1 SIREN R/W 0 UART SIR Enable Value Description 0 UARTEN R/W 0 1 The IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 0 Normal operation. UART Enable Value Description 1 The UART is enabled. 0 The UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. July 24, 2011 707 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x034 Type R/W, reset 0x0000.0012 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RXIFLSEL Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:3 RXIFLSEL R/W 0x2 R/W 1 TXIFLSEL R/W 1 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Value Description 0x0 RX FIFO ≥ ⅛ full 0x1 RX FIFO ≥ ¼ full 0x2 RX FIFO ≥ ½ full (default) 0x3 RX FIFO ≥ ¾ full 0x4 RX FIFO ≥ ⅞ full 0x5-0x7 Reserved 708 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 2:0 TXIFLSEL R/W 0x2 Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value Description 0x0 TX FIFO ≤ ⅞ empty 0x1 TX FIFO ≤ ¾ empty 0x2 TX FIFO ≤ ½ empty (default) 0x3 TX FIFO ≤ ¼ empty 0x4 TX FIFO ≤ ⅛ empty 0x5-0x7 Reserved Note: If the EOT bit in UARTCTL is set (see page 704), the transmit interrupt is generated once the FIFO is completely empty and all data including stop bits have left the transmit serializer. In this case, the setting of TXIFLSEL is ignored. July 24, 2011 709 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller. Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2. UART Interrupt Mask (UARTIM) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 LME5IM LME1IM LMSBIM OEIM R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BEIM PEIM FEIM RTIM TXIM RXIM DSRIM DCDIM CTSIM RIIM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 LME5IM R/W 0 LIN Mode Edge 5 Interrupt Mask Value Description 14 LME1IM R/W 0 1 An interrupt is sent to the interrupt controller when the LME5RIS bit in the UARTRIS register is set. 0 The LME5RIS interrupt is suppressed and not sent to the interrupt controller. LIN Mode Edge 1 Interrupt Mask Value Description 13 LMSBIM R/W 0 1 An interrupt is sent to the interrupt controller when the LME1RIS bit in the UARTRIS register is set. 0 The LME1RIS interrupt is suppressed and not sent to the interrupt controller. LIN Mode Sync Break Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the LMSBRIS bit in the UARTRIS register is set. 0 The LMSBRIS interrupt is suppressed and not sent to the interrupt controller. 710 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 12:11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIM R/W 0 UART Overrun Error Interrupt Mask Value Description 9 BEIM R/W 0 1 An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set. 0 The OERIS interrupt is suppressed and not sent to the interrupt controller. UART Break Error Interrupt Mask Value Description 8 PEIM R/W 0 1 An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set. 0 The BERIS interrupt is suppressed and not sent to the interrupt controller. UART Parity Error Interrupt Mask Value Description 7 FEIM R/W 0 1 An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set. 0 The PERIS interrupt is suppressed and not sent to the interrupt controller. UART Framing Error Interrupt Mask Value Description 6 RTIM R/W 0 1 An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set. 0 The FERIS interrupt is suppressed and not sent to the interrupt controller. UART Receive Time-Out Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set. 0 The RTRIS interrupt is suppressed and not sent to the interrupt controller. July 24, 2011 711 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 5 TXIM R/W 0 Description UART Transmit Interrupt Mask Value Description 4 RXIM R/W 0 1 An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set. 0 The TXRIS interrupt is suppressed and not sent to the interrupt controller. UART Receive Interrupt Mask Value Description 3 DSRIM R/W 0 1 An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set. 0 The RXRIS interrupt is suppressed and not sent to the interrupt controller. UART Data Set Ready Modem Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the DSRRIS bit in the UARTRIS register is set. 0 The DSRRIS interrupt is suppressed and not sent to the interrupt controller. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 2 DCDIM R/W 0 UART Data Carrier Detect Modem Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the DCDRIS bit in the UARTRIS register is set. 0 The DCDRIS interrupt is suppressed and not sent to the interrupt controller. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 1 CTSIM R/W 0 UART Clear to Send Modem Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the CTSRIS bit in the UARTRIS register is set. 0 The CTSRIS interrupt is suppressed and not sent to the interrupt controller. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 712 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 RIIM R/W 0 Description UART Ring Indicator Modem Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the RIRIS bit in the UARTRIS register is set. 0 The RIRIS interrupt is suppressed and not sent to the interrupt controller. This bit is implemented only on UART1 and is reserved for UART0 and UART2. July 24, 2011 713 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x03C Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 LME5RIS LME1RIS LMSBRIS Type Reset RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 3 2 1 0 OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS DSRRIS DCDRIS CTSRIS RIRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 LME5RIS RO 0 LIN Mode Edge 5 Raw Interrupt Status Value Description 1 The timer value at the 5th falling edge of the LIN Sync Field has been captured. 0 No interrupt This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR register. 14 LME1RIS RO 0 LIN Mode Edge 1 Raw Interrupt Status Value Description 1 The timer value at the 1st falling edge of the LIN Sync Field has been captured. 0 No interrupt This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR register. 13 LMSBRIS RO 0 LIN Mode Sync Break Raw Interrupt Status Value Description 1 A LIN Sync Break has been detected. 0 No interrupt This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR register. 714 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset Description 12:11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OERIS RO 0 UART Overrun Error Raw Interrupt Status Value Description 1 An overrun error has occurred. 0 No interrupt This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register. 9 BERIS RO 0 UART Break Error Raw Interrupt Status Value Description 1 A break error has occurred. 0 No interrupt This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register. 8 PERIS RO 0 UART Parity Error Raw Interrupt Status Value Description 1 A parity error has occurred. 0 No interrupt This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register. 7 FERIS RO 0 UART Framing Error Raw Interrupt Status Value Description 1 A framing error has occurred. 0 No interrupt This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register. 6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status Value Description 1 A receive time out has occurred. 0 No interrupt This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register. 5 TXRIS RO 0 UART Transmit Raw Interrupt Status Value Description 1 If the EOT bit in the UARTCTL register is clear, the transmit FIFO level has passed through the condition defined in the UARTIFLS register. If the EOT bit is set, the last bit of all transmitted data and flags has left the serializer. 0 No interrupt This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register. July 24, 2011 715 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 4 RXRIS RO 0 Description UART Receive Raw Interrupt Status Value Description 1 The receive FIFO level has passed through the condition defined in the UARTIFLS register. 0 No interrupt This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register. 3 DSRRIS RO 0 UART Data Set Ready Modem Raw Interrupt Status Value Description 1 Data Set Ready used for software flow control. 0 No interrupt This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 2 DCDRIS RO 0 UART Data Carrier Detect Modem Raw Interrupt Status Value Description 1 Data Carrier Detect used for software flow control. 0 No interrupt This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 1 CTSRIS RO 0 UART Clear to Send Modem Raw Interrupt Status Value Description 1 Clear to Send used for software flow control. 0 No interrupt This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 0 RIRIS RO 0 UART Ring Indicator Modem Raw Interrupt Status Value Description 1 Ring Indicator used for software flow control. 0 No interrupt This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 716 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x040 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 LME5MIS LME1MIS LMSBMIS Type Reset RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 DSRMIS DCDMIS RO 0 RO 0 1 0 CTSMIS RIMIS RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 LME5MIS RO 0 LIN Mode Edge 5 Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to the 5th falling edge of the LIN Sync Field. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR register. 14 LME1MIS RO 0 LIN Mode Edge 1 Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to the 1st falling edge of the LIN Sync Field. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR register. 13 LMSBMIS RO 0 LIN Mode Sync Break Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to the receipt of a LIN Sync Break. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR register. July 24, 2011 717 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description 12:11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEMIS RO 0 UART Overrun Error Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to an overrun error. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register. 9 BEMIS RO 0 UART Break Error Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a break error. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register. 8 PEMIS RO 0 UART Parity Error Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a parity error. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register. 7 FEMIS RO 0 UART Framing Error Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a framing error. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register. 6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a receive time out. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register. 5 TXMIS RO 0 UART Transmit Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to passing through the specified transmit FIFO level (if the EOT bit is clear) or due to the transmission of the last data bit (if the EOT bit is set). 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register. 718 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 4 RXMIS RO 0 Description UART Receive Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to passing through the specified receive FIFO level. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register. 3 DSRMIS RO 0 UART Data Set Ready Modem Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to Data Set Ready. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 2 DCDMIS RO 0 UART Data Carrier Detect Modem Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to Data Carrier Detect. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 1 CTSMIS RO 0 UART Clear to Send Modem Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to Clear to Send. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 0 RIMIS RO 0 UART Ring Indicator Modem Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to Ring Indicator. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. July 24, 2011 719 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x044 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 reserved Type Reset RO 0 Type Reset RO 0 RO 0 RO 0 RO 0 12 11 15 14 13 LME5IC LME1IC LMSBIC W1C 0 W1C 0 W1C 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 OEIC BEIC PEIC FEIC RTIC TXIC RXIC W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 DSRMIC DCDMIC CTSMIC W1C 0 W1C 0 W1C 0 0 RIMIC W1C 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 LME5IC W1C 0 LIN Mode Edge 5 Interrupt Clear Writing a 1 to this bit clears the LME5RIS bit in the UARTRIS register and the LME5MIS bit in the UARTMIS register. 14 LME1IC W1C 0 LIN Mode Edge 1 Interrupt Clear Writing a 1 to this bit clears the LME1RIS bit in the UARTRIS register and the LME1MIS bit in the UARTMIS register. 13 LMSBIC W1C 0 LIN Mode Sync Break Interrupt Clear Writing a 1 to this bit clears the LMSBRIS bit in the UARTRIS register and the LMSBMIS bit in the UARTMIS register. 12:11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIC W1C 0 Overrun Error Interrupt Clear Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and the OEMIS bit in the UARTMIS register. 9 BEIC W1C 0 Break Error Interrupt Clear Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and the BEMIS bit in the UARTMIS register. 8 PEIC W1C 0 Parity Error Interrupt Clear Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and the PEMIS bit in the UARTMIS register. 720 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 7 FEIC W1C 0 Description Framing Error Interrupt Clear Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and the FEMIS bit in the UARTMIS register. 6 RTIC W1C 0 Receive Time-Out Interrupt Clear Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and the RTMIS bit in the UARTMIS register. 5 TXIC W1C 0 Transmit Interrupt Clear Writing a 1 to this bit clears the TXRIS bit in the UARTRIS register and the TXMIS bit in the UARTMIS register. 4 RXIC W1C 0 Receive Interrupt Clear Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and the RXMIS bit in the UARTMIS register. 3 DSRMIC W1C 0 UART Data Set Ready Modem Interrupt Clear Writing a 1 to this bit clears the DSRRIS bit in the UARTRIS register and the DSRMIS bit in the UARTMIS register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 2 DCDMIC W1C 0 UART Data Carrier Detect Modem Interrupt Clear Writing a 1 to this bit clears the DCDRIS bit in the UARTRIS register and the DCDMIS bit in the UARTMIS register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 1 CTSMIC W1C 0 UART Clear to Send Modem Interrupt Clear Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register and the CTSMIS bit in the UARTMIS register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 0 RIMIC W1C 0 UART Ring Indicator Modem Interrupt Clear Writing a 1 to this bit clears the RIRIS bit in the UARTRIS register and the RIMIS bit in the UARTMIS register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. July 24, 2011 721 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 14: UART DMA Control (UARTDMACTL), offset 0x048 The UARTDMACTL register is the DMA control register. UART DMA Control (UARTDMACTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x048 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type 31:3 reserved RO 2 DMAERR R/W RO 0 Reset DMAERR TXDMAE RXDMAE R/W 0 R/W 0 R/W 0 Description 0x00000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DMA on Error Value Description 1 TXDMAE R/W 0 1 µDMA receive requests are automatically disabled when a receive error occurs. 0 µDMA receive requests are unaffected when a receive error occurs. Transmit DMA Enable Value Description 0 RXDMAE R/W 0 1 µDMA for the transmit FIFO is enabled. 0 µDMA for the transmit FIFO is disabled. Receive DMA Enable Value Description 1 µDMA for the receive FIFO is enabled. 0 µDMA for the receive FIFO is disabled. 722 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 15: UART LIN Control (UARTLCTL), offset 0x090 The UARTLCTL register is the configures the operation of the UART when in LIN mode. UART LIN Control (UARTLCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x090 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset RO 0 BLEN Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:4 BLEN R/W 0x0 reserved RO 0 MASTER RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sync Break Length Value Description 3:1 reserved RO 0x0 0 MASTER R/W 0 0x3 Sync break length is 16T bits 0x2 Sync break length is 15T bits 0x1 Sync break length is 14T bits 0x0 Sync break length is 13T bits (default) Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LIN Master Enable Value Description 1 The UART operates as a LIN master. 0 The UART operates as a LIN slave. July 24, 2011 723 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094 The UARTLSS register captures the free-running timer value when either the Sync Edge 1 or the Sync Edge 5 is detected in LIN mode. UART LIN Snap Shot (UARTLSS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x094 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset TSS Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TSS RO 0x0000 Timer Snap Shot This field contains the value of the free-running timer when either the Sync Edge 5 or the Sync Edge 1 was detected. 724 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 17: UART LIN Timer (UARTLTIM), offset 0x098 The UARTLTIM register contains the current timer value for the free-running timer that is used to calculate the baud rate when in LIN slave mode. The value in this register is used along with the value in the UART LIN Snap Shot (UARTLSS) register to adjust the baud rate to match that of the master. UART LIN Timer (UARTLTIM) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x098 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset TIMER Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TIMER RO 0x0000 Timer Value This field contains the value of the free-running timer. July 24, 2011 725 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 18: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 726 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 19: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID5 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 24, 2011 727 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 20: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID6 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 728 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 21: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID7 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 24, 2011 729 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 22: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE0 Type RO, reset 0x0000.0060 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x60 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 730 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 23: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 24, 2011 731 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 24: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x18 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 732 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 25: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x01 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 24, 2011 733 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 26: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 734 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 27: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. July 24, 2011 735 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 28: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID2 RO 0x05 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 736 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 29: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID3 RO 0xB1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. July 24, 2011 737 Texas Instruments-Production Data Synchronous Serial Interface (SSI) 15 Synchronous Serial Interface (SSI) ® The Stellaris microcontroller includes two Synchronous Serial Interface (SSI) modules. Each SSI is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. The Stellaris LM3S1F11 controller includes two SSI modules with the following features: ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Master or slave operation ■ Programmable clock bit rate and prescaler ■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing ■ Standard FIFO-based interrupts and End-of-Transmission interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries – Transmit single request asserted when there is space in the FIFO; burst request asserted when FIFO contains 4 entries 738 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 15.1 Block Diagram Figure 15-1. SSI Module Block Diagram DMA Request DMA Control SSIDMACTL Interrupt Interrupt Control TxFIFO 8 x 16 SSIIM SSIMIS SSIRIS SSIICR . . . Control/Status SSITx SSICR0 SSICR1 SSISR SSIRx Transmit/ Receive Logic SSIDR RxFIFO 8 x 16 Clock Prescaler System Clock SSIClk SSIFss . . . SSICPSR Identification Registers SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 15.2 SSIPeriphID0 SSIPeriphID1 SSIPeriphID2 SSIPeriphID3 SSIPeriphID4 SSIPeriphID5 SSIPeriphID6 SSIPeriphID7 Signal Description The following table lists the external signals of the SSI module and describes the function of each. The SSI signals are alternate functions for some GPIO signals and default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 424) should be set to choose the SSI function. The number in July 24, 2011 739 Texas Instruments-Production Data Synchronous Serial Interface (SSI) parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 442) to assign the SSI signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 400. Table 15-1. Signals for SSI (100LQFP) Pin Name SSI0Clk Pin Number Pin Mux / Pin Assignment 28 a Pin Type Buffer Type PA2 (1) I/O TTL Description SSI module 0 clock. SSI0Fss 29 PA3 (1) I/O TTL SSI module 0 frame. SSI0Rx 30 PA4 (1) I TTL SSI module 0 receive. SSI0Tx 31 PA5 (1) O TTL SSI module 0 transmit. SSI1Clk 60 74 76 PF2 (9) PE0 (2) PH4 (11) I/O TTL SSI module 1 clock. SSI1Fss 59 63 75 PF3 (9) PH5 (11) PE1 (2) I/O TTL SSI module 1 frame. SSI1Rx 58 62 95 PF4 (9) PH6 (11) PE2 (2) I TTL SSI module 1 receive. SSI1Tx 15 46 96 PH7 (11) PF5 (9) PE3 (2) O TTL SSI module 1 transmit. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 15-2. Signals for SSI (108BGA) Pin Name SSI0Clk Pin Number Pin Mux / Pin Assignment M4 a Pin Type Buffer Type PA2 (1) I/O TTL Description SSI module 0 clock. SSI0Fss L4 PA3 (1) I/O TTL SSI module 0 frame. SSI0Rx L5 PA4 (1) I TTL SSI module 0 receive. SSI0Tx M5 PA5 (1) O TTL SSI module 0 transmit. SSI1Clk J11 B11 B10 PF2 (9) PE0 (2) PH4 (11) I/O TTL SSI module 1 clock. SSI1Fss J12 F10 A12 PF3 (9) PH5 (11) PE1 (2) I/O TTL SSI module 1 frame. SSI1Rx L9 G3 A4 PF4 (9) PH6 (11) PE2 (2) I TTL SSI module 1 receive. SSI1Tx H3 L8 B4 PH7 (11) PF5 (9) PE3 (2) O TTL SSI module 1 transmit. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 15.3 Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit 740 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller and receive modes. The SSI also supports the µDMA interface. The transmit and receive FIFOs can be programmed as destination/source addresses in the µDMA module. µDMA operation is enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 767). 15.3.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 760). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register (see page 753). The frequency of the output clock SSIClk is defined by: SSIClk = SysClk / (CPSDVSR * (1 + SCR)) Note: For master mode, the system clock must be at least two times faster than the SSIClk, with the restriction that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock must be at least 12 times faster than the SSIClk. See “Synchronous Serial Interface (SSI)” on page 904 to view SSI timing parameters. 15.3.2 FIFO Operation 15.3.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 757), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or a µDMA request when the FIFO is empty. 15.3.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 15.3.3 Interrupts The SSI can generate interrupts when the following conditions are observed: ■ Transmit FIFO service (when the transmit FIFO is half full or less) ■ Receive FIFO service (when the receive FIFO is half full or more) July 24, 2011 741 Texas Instruments-Production Data Synchronous Serial Interface (SSI) ■ Receive FIFO time-out ■ Receive FIFO overrun ■ End of transmission All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI generates a single interrupt request to the controller regardless of the number of active interrupts. Each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt Mask (SSIIM) register (see page 761). Setting the appropriate mask bit enables the interrupt. The individual outputs, along with a combined interrupt output, allow use of either a global interrupt service routine or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 762 and page 764, respectively). The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is emptied before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing a 1 to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared so late that the ISR returns before the interrupt is actually cleared, or the ISR may be re-activated unnecessarily. The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This interrupt can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In addition, because transmitted data and received data complete at exactly the same time, the interrupt can also indicate that read data is ready immediately, without waiting for the receive FIFO time-out period to complete. 15.3.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: ■ Texas Instruments synchronous serial ■ Freescale SPI ■ MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk and latch data from the other device on the falling edge. 742 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 15.3.4.1 Texas Instruments Synchronous Serial Frame Format Figure 15-2 on page 743 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on each falling edge of SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 15-3 on page 743 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits July 24, 2011 743 Texas Instruments-Production Data Synchronous Serial Interface (SSI) 15.3.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits in the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is clear, it produces a steady state Low value on the SSIClk pin. If the SPO bit is set, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is clear, data is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second clock edge transition. 15.3.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 15-4 on page 744 and Figure 15-5 on page 744. Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB MSB Q 4 to 16 bits SSITx MSB Note: LSB Q is undefined. Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB LSB MSB MSB 4 to16 bits SSITx LSB MSB LSB MSB In this configuration, during idle periods: ■ SSIClk is forced Low 744 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, causing slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Once both the master and slave data have been set, the SSIClk master clock pin goes High after one additional half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 15.3.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 15-6 on page 745, which covers both single and continuous transfers. Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 SSIClk SSIFss SSIRx Q Q MSB LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad July 24, 2011 745 Texas Instruments-Production Data Synchronous Serial Interface (SSI) ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After an additional one-half SSIClk period, both master and slave valid data are enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words, and termination is the same as that of the single word transfer. 15.3.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 15-7 on page 746 and Figure 15-8 on page 746. Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSIRx MSB LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRx MSB LSB LSB MSB 4 to 16 bits In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad 746 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, causing slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One-half period later, valid master data is transferred to the SSITx line. Once both the master and slave data have been set, the SSIClk master clock pin becomes Low after one additional half SSIClk period, meaning that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 15.3.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 15-9 on page 747, which covers both single and continuous transfers. Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 SSIClk SSIFss SSIRx Q MSB LSB Q 4 to 16 bits MSB SSITx Note: LSB Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After an additional one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. July 24, 2011 747 Texas Instruments-Production Data Synchronous Serial Interface (SSI) After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state until the final bit of the last word has been captured and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 15.3.4.7 MICROWIRE Frame Format Figure 15-10 on page 748 shows the MICROWIRE frame format for a single frame. Figure 15-11 on page 749 shows the same format when back-to-back frames are transmitted. Figure 15-10. MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSITx LSB MSB 8-bit control 0 SSIRx MSB LSB 4 to 16 bits output data MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex and uses a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, causing the data to be transferred to the receive FIFO. 748 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) SSIClk SSIFss SSITx LSB MSB LSB 8-bit control SSIRx 0 MSB MSB LSB 4 to 16 bits output data In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 15-12 on page 749 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements tSetup=(2*tSSIClk) tHold=tSSIClk SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave 15.3.5 DMA Operation The SSI peripheral provides an interface to the μDMA controller with separate channels for transmit and receive. The µDMA operation of the SSI is enabled through the SSI DMA Control (SSIDMACTL) register. When µDMA operation is enabled, the SSI asserts a µDMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is 4 or more items. For the transmit channel, a single transfer request is asserted whenever at least one empty location is in the transmit FIFO. The burst request is asserted whenever the transmit FIFO has 4 or more empty slots. The July 24, 2011 749 Texas Instruments-Production Data Synchronous Serial Interface (SSI) single and burst µDMA transfer requests are handled automatically by the μDMA controller depending how the µDMA channel is configured. To enable µDMA operation for the receive channel, the RXDMAE bit of the DMA Control (SSIDMACTL) register should be set. To enable µDMA operation for the transmit channel, the TXDMAE bit of SSIDMACTL should be set. If µDMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The interrupt occurs on the SSI interrupt vector. Therefore, if interrupts are used for SSI operation and µDMA is enabled, the SSI interrupt handler must be designed to handle the μDMA completion interrupt. See “Micro Direct Memory Access (μDMA)” on page 340 for more details about programming the μDMA controller. 15.4 Initialization and Configuration To enable and initialize the SSI, the following steps are necessary: 1. Enable the SSI module by setting the SSI bit in the RCGC1 register (see page 246). 2. Enable the clock to the appropriate GPIO module via the RCGC2 register (see page 255). To find out which GPIO port to enable, refer to Table 19-5 on page 854. 3. Set the GPIO AFSEL bits for the appropriate pins (see page 424). To determine which GPIOs to configure, see Table 19-4 on page 848. 4. Configure the PMCn fields in the GPIOPCTL register to assign the SSI signals to the appropriate pins. See page 442 and Table 19-5 on page 854. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x0000.0000. b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. 4. Write the SSICR0 register with the following configuration: ■ Serial clock rate (SCR) ■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) ■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) ■ The data size (DSS) 5. Optionally, configure the μDMA channel (see “Micro Direct Memory Access (μDMA)” on page 340) and enable the DMA option(s) in the SSIDMACTL register. 6. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: 750 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller ■ Master operation ■ Freescale SPI mode (SPO=1, SPH=1) ■ 1 Mbps bit rate ■ 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: SSIClk = SysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=0x2, SCR must be 0x9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is clear. 2. Write the SSICR1 register with a value of 0x0000.0000. 3. Write the SSICPSR register with a value of 0x0000.0002. 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register. 15.5 Register Map Table 15-3 on page 751 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s address, relative to that SSI module’s base address: ■ SSI0: 0x4000.8000 ■ SSI1: 0x4000.9000 Note that the SSI module clock must be enabled before the registers can be programmed (see page 246). There must be a delay of 3 system clocks after the SSI module clock is enabled before any SSI module registers are accessed. Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. Table 15-3. SSI Register Map Offset Name Type Reset Description See page 0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 753 0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 755 0x008 SSIDR R/W 0x0000.0000 SSI Data 757 0x00C SSISR RO 0x0000.0003 SSI Status 758 0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 760 0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 761 July 24, 2011 751 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Table 15-3. SSI Register Map (continued) Name Type Reset 0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 762 0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 764 0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 766 0x024 SSIDMACTL R/W 0x0000.0000 SSI DMA Control 767 0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 768 0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 769 0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 770 0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 771 0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 772 0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 773 0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 774 0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 775 0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 776 0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 777 0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 778 0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 779 15.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. 752 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: SSI Control 0 (SSICR0), offset 0x000 The SSICR0 register contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 SPH SPO R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset SCR Type Reset Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15:8 SCR R/W 0x00 FRF R/W 0 DSS Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Serial Clock Rate This bit field is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=SysClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 7 SPH R/W 0 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. This bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. Value Description 6 SPO R/W 0 0 Data is captured on the first clock edge transition. 1 Data is captured on the second clock edge transition. SSI Serial Clock Polarity Value Description 0 A steady state Low value is placed on the SSIClk pin. 1 A steady state High value is placed on the SSIClk pin when data is not being transferred. July 24, 2011 753 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 5:4 FRF R/W 0x0 Description SSI Frame Format Select Value Frame Format 3:0 DSS R/W 0x0 0x0 Freescale SPI Frame Format 0x1 Texas Instruments Synchronous Serial Frame Format 0x2 MICROWIRE Frame Format 0x3 Reserved SSI Data Size Select Value Data Size 0x0-0x2 Reserved 0x3 4-bit data 0x4 5-bit data 0x5 6-bit data 0x6 7-bit data 0x7 8-bit data 0x8 9-bit data 0x9 10-bit data 0xA 11-bit data 0xB 12-bit data 0xC 13-bit data 0xD 14-bit data 0xE 15-bit data 0xF 16-bit data 754 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 2: SSI Control 1 (SSICR1), offset 0x004 The SSICR1 register contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 EOT SOD MS SSE LBM RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.0 4 EOT R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. End of Transmission Value Description 3 SOD R/W 0 0 The TXRIS interrupt indicates that the transmit FIFO is half full or less. 1 The End of Transmit interrupt mode for the TXRIS interrupt is enabled. SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. Value Description 2 MS R/W 0 0 SSI can drive the SSITx output in Slave mode. 1 SSI must not drive the SSITx output in Slave mode. SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when the SSI is disabled (SSE=0). Value Description 0 The SSI is configured as a master. 1 The SSI is configured as a slave. July 24, 2011 755 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 1 SSE R/W 0 Description SSI Synchronous Serial Port Enable Value Description 0 SSI operation is disabled. 1 SSI operation is enabled. Note: 0 LBM R/W 0 This bit must be cleared before any control registers are reprogrammed. SSI Loopback Mode Value Description 0 Normal serial port operation enabled. 1 Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. 756 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 3: SSI Data (SSIDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. The SSIDR register is 16-bits wide. When the SSIDR register is read, the entry in the receive FIFO that is pointed to by the current FIFO read pointer is accessed. When a data value is removed by the SSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO pointed to by the current FIFO write pointer. When the SSIDR register is written to, the entry in the transmit FIFO that is pointed to by the write pointer is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. Each data value is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is cleared, allowing the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 DATA R/W 0x0000 SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. July 24, 2011 757 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 4: SSI Status (SSISR), offset 0x00C The SSISR register contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x00C Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BSY RFF RNE TNF TFE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.00 4 BSY RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Busy Bit Value Description 3 RFF RO 0 0 The SSI is idle. 1 The SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. SSI Receive FIFO Full Value Description 2 RNE RO 0 0 The receive FIFO is not full. 1 The receive FIFO is full. SSI Receive FIFO Not Empty Value Description 1 TNF RO 1 0 The receive FIFO is empty. 1 The receive FIFO is not empty. SSI Transmit FIFO Not Full Value Description 0 The transmit FIFO is full. 1 The transmit FIFO is not full. 758 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 TFE RO 1 Description SSI Transmit FIFO Empty Value Description 0 The transmit FIFO is not empty. 1 The transmit FIFO is empty. July 24, 2011 759 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 The SSICPSR register specifies the division factor which is used to derive the SSIClk from the system clock. The clock is further divided by a value from 1 to 256, which is 1 + SCR. SCR is programmed in the SSICR0 register. The frequency of the SSIClk is defined by: SSIClk = SysClk / (CPSDVSR * (1 + SCR)) The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset CPSDVSR RO 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CPSDVSR R/W 0x00 SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. 760 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared on reset. On a read, this register gives the current value of the mask on the corresponding interrupt. Setting a bit sets the mask, preventing the interrupt from being signaled to the interrupt controller. Clearing a bit clears the corresponding mask, enabling the interrupt to be sent to the interrupt controller. SSI Interrupt Mask (SSIIM) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 TXIM RXIM RTIM RORIM R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXIM R/W 0 SSI Transmit FIFO Interrupt Mask Value Description 2 RXIM R/W 0 0 The transmit FIFO interrupt is masked. 1 The transmit FIFO interrupt is not masked. SSI Receive FIFO Interrupt Mask Value Description 1 RTIM R/W 0 0 The receive FIFO interrupt is masked. 1 The receive FIFO interrupt is not masked. SSI Receive Time-Out Interrupt Mask Value Description 0 RORIM R/W 0 0 The receive FIFO time-out interrupt is masked. 1 The receive FIFO time-out interrupt is not masked. SSI Receive Overrun Interrupt Mask Value Description 0 The receive FIFO overrun interrupt is masked. 1 The receive FIFO overrun interrupt is not masked. July 24, 2011 761 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x018 Type RO, reset 0x0000.0008 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXRIS RXRIS RTRIS RORRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXRIS RO 1 SSI Transmit FIFO Raw Interrupt Status Value Description 0 No interrupt. 1 If the EOT bit in the SSICR1 register is clear, the transmit FIFO is half full or less. If the EOT bit is set, the transmit FIFO is empty, and the last bit has been transmitted out of the serializer. This bit is cleared when the transmit FIFO is more than half full (if the EOT bit is clear) or when it has any data in it (if the EOT bit is set). 2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status Value Description 0 No interrupt. 1 The receive FIFO is half full or more. This bit is cleared when the receive FIFO is less than half full. 1 RTRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Value Description 0 No interrupt. 1 The receive time-out has occurred. This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. 762 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 RORRIS RO 0 Description SSI Receive Overrun Raw Interrupt Status Value Description 0 No interrupt. 1 The receive FIFO has overflowed This bit is cleared when a 1 is written to the RORIC bit in the SSI Interrupt Clear (SSIICR) register. July 24, 2011 763 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXMIS RXMIS RTMIS RORMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXMIS RO 0 SSI Transmit FIFO Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the transmit FIFO being half full or less (if the EOT bit is clear) or due to the transmission of the last data bit (if the EOT bit is set). This bit is cleared when the transmit FIFO is more than half full (if the EOT bit is clear) or when it has any data in it (if the EOT bit is set). 2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the receive FIFO being half full or less. This bit is cleared when the receive FIFO is less than half full. 1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the receive time out. This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. 764 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 0 RORMIS RO 0 Description SSI Receive Overrun Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the receive FIFO overflowing. This bit is cleared when a 1 is written to the RORIC bit in the SSI Interrupt Clear (SSIICR) register. July 24, 2011 765 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x020 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RTIC RORIC RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 W1C 0 W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 RTIC W1C 0 SSI Receive Time-Out Interrupt Clear Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and the RTMIS bit in the SSIMIS register. 0 RORIC W1C 0 SSI Receive Overrun Interrupt Clear Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register and the RORMIS bit in the SSIMIS register. 766 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 The SSIDMACTL register is the µDMA control register. SSI DMA Control (SSIDMACTL) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 TXDMAE R/W 0 TXDMAE RXDMAE R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Transmit DMA Enable Value Description 0 RXDMAE R/W 0 0 µDMA for the transmit FIFO is disabled. 1 µDMA for the transmit FIFO is enabled. Receive DMA Enable Value Description 0 µDMA for the receive FIFO is disabled. 1 µDMA for the receive FIFO is enabled. July 24, 2011 767 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 768 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID5 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 24, 2011 769 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID6 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 770 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID7 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 24, 2011 771 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFE0 Type RO, reset 0x0000.0022 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x22 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 772 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 24, 2011 773 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x18 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 774 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x01 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 24, 2011 775 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 776 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. July 24, 2011 777 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID2 RO 0x05 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 778 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID3 RO 0xB1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. July 24, 2011 779 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface 16 Inter-Integrated Circuit (I2C) Interface The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S1F11 microcontroller includes two I2C modules, providing the ability to interact (both transmit and receive) with other I2C devices on the bus. ® The Stellaris LM3S1F11 controller includes two I2C modules with the following features: ■ Devices on the I2C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation ■ Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive ■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) ■ Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected ■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 780 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 16.1 Block Diagram Figure 16-1. I2C Block Diagram I2CSCL I2C Control Interrupt I2CMSA I2CSOAR I2CMCS I2CSCSR I2CMDR I2CSDR I2CMTPR I2CSIMR I2CMIMR I2CSRIS I2CMRIS I2CSMIS I2CMMIS I2CSICR I2C Master Core I2CSDA I2CSCL 2 I C I/O Select I2CSDA I2CSCL I2C Slave Core I2CMICR I2CSDA I2CMCR 16.2 Signal Description The following table lists the external signals of the I2C interface and describes the function of each. The I2C interface signals are alternate functions for some GPIO signals and default to be GPIO signals at reset., with the exception of the I2C0SCL and I2CSDA pins which default to the I2C function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 424) should be set to choose the I2C function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 442) to assign the I2C signal to the specified GPIO port pin. Note that the I2C pins should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 400. Table 16-1. Signals for I2C (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description I2C0SCL 72 PB2 (1) I/O OD I2C module 0 clock. I2C0SDA 65 PB3 (1) I/O OD I2C module 0 data. I2C1SCL 14 19 26 34 PJ0 (11) PG0 (3) PA0 (8) PA6 (1) I/O OD I2C module 1 clock. I2C1SDA 18 27 35 87 PG1 (3) PA1 (8) PA7 (1) PJ1 (11) I/O OD I2C module 1 data. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 16-2. Signals for I2C (108BGA) Pin Name I2C0SCL Pin Number Pin Mux / Pin Assignment A11 PB2 (1) a Pin Type Buffer Type I/O OD Description I2C module 0 clock. July 24, 2011 781 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Table 16-2. Signals for I2C (108BGA) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description I2C0SDA E11 PB3 (1) I/O OD I2C module 0 data. I2C1SCL F3 K1 L3 L6 PJ0 (11) PG0 (3) PA0 (8) PA6 (1) I/O OD I2C module 1 clock. I2C1SDA K2 M3 M6 B6 PG1 (3) PA1 (8) PA7 (1) PJ1 (11) I/O OD I2C module 1 data. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 16.3 Functional Description Each I2C module is comprised of both master and slave functions. For proper operation, the SDA and SCL pins must be configured as open-drain signals. A typical I2C bus configuration is shown in Figure 16-2. See “Inter-Integrated Circuit (I2C) Interface” on page 906 for I2C timing diagrams. Figure 16-2. I2C Bus Configuration RPUP SCL SDA I2C Bus I2CSCL I2CSDA Stellaris® 16.3.1 RPUP SCL SDA 3rd Party Device with I2C Interface SCL SDA 3rd Party Device with I2C Interface I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines are High. Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in “START and STOP Conditions” on page 782) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. 16.3.1.1 START and STOP Conditions The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition, and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition. See Figure 16-3. 782 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 16-3. START and STOP Conditions SDA SDA SCL SCL START condition STOP condition The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and the Control register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the I2C Master Data (I2CMDR) register. When the I2C module operates in Master receiver mode, the ACK bit is normally set causing the I2C bus controller to transmit an acknowledge automatically after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter. When operating in slave mode, two bits in the I2C Slave Raw Interrupt Status (I2CSRIS) register indicate detection of start and stop conditions on the bus; while two bits in the I2C Slave Masked Interrupt Status (I2CSMIS) register allow start and stop conditions to be promoted to controller interrupts (when interrupts are enabled). 16.3.1.2 Data Format with 7-Bit Address Data transfers follow the format shown in Figure 16-4. After the START condition, a slave address is transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). If the R/S bit is clear, it indicates a transmit operation (send), and if it is set, it indicates a request for data (receive). A data transfer is always terminated by a STOP condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/transmit formats are then possible within a single transfer. Figure 16-4. Complete Data Transfer with a 7-Bit Address SDA MSB SCL 1 Start 2 LSB R/S ACK 7 8 9 MSB 1 2 Slave address 7 Data LSB ACK 8 9 Stop The first seven bits of the first byte make up the slave address (see Figure 16-5). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master transmits (sends) data to the selected slave, and a one in this position means that the master receives data from the slave. July 24, 2011 783 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 16-5. R/S Bit in First Byte MSB LSB R/S Slave address 16.3.1.3 Data Validity The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is Low (see Figure 16-6). Figure 16-6. Data Validity During Bit Transfer on the I2C Bus SDA SCL Data line Change stable of data allowed 16.3.1.4 Acknowledge All bus transactions have a required acknowledge clock cycle that is generated by the master. During the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line. To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data transmitted out by the receiver during the acknowledge cycle must comply with the data validity requirements described in “Data Validity” on page 784. When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave so that the master can generate a STOP condition and abort the current transfer. If the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Because the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to allow the master to generate the STOP or a repeated START condition. 16.3.1.5 Arbitration A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate a START condition within minimum hold time of the START condition. In these situations, an arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of the competing master devices to place a '1' (High) on SDA while another master transmits a '0' (Low) switches off its data output stage and retires until the bus is idle again. Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 16.3.2 Available Speed Modes The I2C bus can run in either Standard mode (100 kbps) or Fast mode (400 kbps). The selected mode should match the speed of the other I2C devices on the bus. 784 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 16.3.2.1 Standard and Fast Modes Standard and Fast modes are selected using a value in the I2C Master Timer Period (I2CMTPR) register that results in an SCL frequency of 100 kbps for Standard mode or 400 kbps for Fast mode. The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP where: CLK_PRD is the system clock period SCL_LP is the low phase of SCL (fixed at 6) SCL_HP is the high phase of SCL (fixed at 4) TIMER_PRD is the programmed value in the I2CMTPR register (see page 803). The I2C clock period is calculated as follows: SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD For example: CLK_PRD = 50 ns TIMER_PRD = 2 SCL_LP=6 SCL_HP=4 yields a SCL frequency of: 1/SCL_PERIOD = 333 Khz Table 16-3 gives examples of the timer periods that should be used to generate both Standard and Fast mode SCL frequencies based on various system clock frequencies. Table 16-3. Examples of I2C Master Timer Period versus Speed Mode 16.3.3 System Clock Timer Period Standard Mode Timer Period Fast Mode 4 MHz 0x01 100 Kbps - - 6 MHz 0x02 100 Kbps - - 12.5 MHz 0x06 89 Kbps 0x01 312 Kbps 16.7 MHz 0x08 93 Kbps 0x02 278 Kbps 20 MHz 0x09 100 Kbps 0x02 333 Kbps 25 MHz 0x0C 96.2 Kbps 0x03 312 Kbps 33 MHz 0x10 97.1 Kbps 0x04 330 Kbps 40 MHz 0x13 100 Kbps 0x04 400 Kbps 50 MHz 0x18 100 Kbps 0x06 357 Kbps 80 MHz 0x27 100 Kbps 0x09 400 Kbps Interrupts The I2C can generate interrupts when the following conditions are observed: ■ Master transaction completed ■ Master arbitration lost July 24, 2011 785 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface ■ Master transaction error ■ Slave transaction received ■ Slave transaction requested ■ Stop condition on bus detected ■ Start condition on bus detected The I2C master and I2C slave modules have separate interrupt signals. While both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller. 16.3.3.1 I2C Master Interrupts The I2C master module generates an interrupt when a transaction completes (either transmit or receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration, the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in the I2C Master Interrupt Clear (I2CMICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Master Raw Interrupt Status (I2CMRIS) register. 16.3.3.2 I2C Slave Interrupts The slave module can generate an interrupt when data has been received or requested. This interrupt is enabled by setting the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register. Software determines whether the module should write (transmit) or read (receive) data from the I2C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by setting the DATAIC bit in the I2C Slave Interrupt Clear (I2CSICR) register. In addition, the slave module can generate an interrupt when a start and stop condition is detected. These interrupts are enabled by setting the STARTIM and STOPIM bits of the I2C Slave Interrupt Mask (I2CSIMR) register and cleared by writing a 1 to the STOPIC and STARTIC bits of the I2C Slave Interrupt Clear (I2CSICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Slave Raw Interrupt Status (I2CSRIS) register. 16.3.4 Loopback Operation The I2C modules can be placed into an internal loopback mode for diagnostic or debug work by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL signals from the master and slave modules are tied together. 786 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 16.3.5 Command Sequence Flow Charts This section details the steps required to perform the various I2C transfer types in both master and slave mode. 16.3.5.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master. July 24, 2011 787 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 16-7. Master Single TRANSMIT Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Write data to I2CMDR Read I2CMCS NO BUSBSY bit=0? YES Write ---0-111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle 788 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 16-8. Master Single RECEIVE Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS NO BUSBSY bit=0? YES Write ---00111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Read data from I2CMDR Idle July 24, 2011 789 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 16-9. Master TRANSMIT with Repeated START Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS Write data to I2CMDR BUSY bit=0? YES Read I2CMCS ERROR bit=0? NO NO NO BUSBSY bit=0? YES Write data to I2CMDR YES Write ---0-011 to I2CMCS NO ARBLST bit=1? YES Write ---0-001 to I2CMCS NO Index=n? YES Write ---0-101 to I2CMCS Write ---0-100 to I2CMCS Error Service Idle Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle 790 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 16-10. Master RECEIVE with Repeated START Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS BUSY bit=0? Read I2CMCS NO YES NO BUSBSY bit=0? ERROR bit=0? NO YES Write ---01011 to I2CMCS NO Read data from I2CMDR ARBLST bit=1? YES Write ---01001 to I2CMCS NO Write ---0-100 to I2CMCS Index=m-1? Error Service YES Write ---00101 to I2CMCS Idle Read I2CMCS BUSY bit=0? NO YES NO ERROR bit=0? YES Error Service Read data from I2CMDR Idle July 24, 2011 791 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated START Idle Master operates in Master Transmit mode STOP condition is not generated Write Slave Address to I2CMSA Write ---01011 to I2CMCS Master operates in Master Receive mode Repeated START condition is generated with changing data direction Idle 792 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated START Idle Master operates in Master Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write ---0-011 to I2CMCS Master operates in Master Transmit mode Repeated START condition is generated with changing data direction Idle 16.3.5.2 I2C Slave Command Sequences Figure 16-13 on page 794 presents the command sequence available for the I2C slave. July 24, 2011 793 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 16-13. Slave Command Sequence Idle Write OWN Slave Address to I2CSOAR Write -------1 to I2CSCSR Read I2CSCSR NO TREQ bit=1? YES Write data to I2CSDR 16.4 NO RREQ bit=1? FBR is also valid YES Read data from I2CSDR Initialization and Configuration The following example shows how to configure the I2C module to transmit a single byte as a master. This assumes the system clock is 20 MHz. 1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System Control module (see page 246). 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module (see page 255). To find out which GPIO port to enable, refer to Table 19-5 on page 854. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register (see page 424). To determine which GPIOs to configure, see Table 19-4 on page 848. 4. Enable the I2C pins for Open Drain operation. See page 429. 5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate pins. See page 442 and Table 19-5 on page 854. 6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010. 794 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by the following equation: TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1; TPR = (20MHz/(2*(6+4)*100000))-1; TPR = 9 Write the I2CMTPR register with the value of 0x0000.0009. 8. Specify the slave address of the master and that the next operation is a Transmit by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B. 9. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the desired data. 10. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register with a value of 0x0000.0007 (STOP, START, RUN). 11. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has been cleared. 12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged. 16.5 Register Map Table 16-4 on page 795 lists the I2C registers. All addresses given are relative to the I2C base address: ■ I2C 0: 0x4002.0000 ■ I2C 1: 0x4002.1000 Note that the I2C module clock must be enabled before the registers can be programmed (see page 246). There must be a delay of 3 system clocks after the I2C module clock is enabled before any I2C module registers are accessed. ® The hw_i2c.h file in the StellarisWare Driver Library uses a base address of 0x800 for the I2C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare uses an offset between 0x000 and 0x018 with the slave base address. Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map Offset Description See page Name Type Reset 0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 797 0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 798 0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 802 0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 803 0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 804 0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 805 I2C Master July 24, 2011 795 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued) Offset Name 0x018 Description See page Type Reset I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 806 0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 807 0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 808 0x800 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 809 0x804 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 810 0x808 I2CSDR R/W 0x0000.0000 I2C Slave Data 812 0x80C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 813 0x810 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 814 0x814 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 815 0x818 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 816 I2C Slave 16.6 Register Descriptions (I2C Master) The remainder of this section lists and describes the I2C master registers, in numerical order by address offset. 796 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Transmit (Low). I2C Master Slave Address (I2CMSA) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset SA RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:1 SA R/W 0x00 R/S Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Address This field specifies bits A6 through A0 of the slave address. 0 R/S R/W 0 Receive/Send The R/S bit specifies if the next operation is a Receive (High) or Transmit (Low). Value Description 0 Transmit 1 Receive July 24, 2011 797 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit is normally set, causing the I2C bus controller to transmit an acknowledge automatically after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter. Read-Only Status Register I2C Master Control/Status (I2CMCS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BUSBSY IDLE ARBLST ERROR BUSY RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6 BUSBSY RO 0 DATACK ADRACK RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bus Busy Value Description 0 The I2C bus is idle. 1 The I2C bus is busy. The bit changes based on the START and STOP conditions. 5 IDLE RO 0 I2C Idle Value Description 0 The I2C controller is not idle. 1 The I2C controller is idle. 798 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 4 ARBLST RO 0 Description Arbitration Lost Value Description 3 DATACK RO 0 0 The I2C controller won arbitration. 1 The I2C controller lost arbitration. Acknowledge Data Value Description 2 ADRACK RO 0 0 The transmitted data was acknowledged 1 The transmitted data was not acknowledged. Acknowledge Address Value Description 1 ERROR RO 0 0 The transmitted address was acknowledged 1 The transmitted address was not acknowledged. Error Value Description 0 No error was detected on the last operation. 1 An error occurred on the last operation. The error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0 BUSY RO 0 I2C Busy Value Description 0 The controller is idle. 1 The controller is busy. When the BUSY bit is set, the other status bits are not valid. Write-Only Control Register I2C Master Control/Status (I2CMCS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 ACK STOP START RUN RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset July 24, 2011 799 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 ACK WO 0 Data Acknowledge Enable Value Description 2 STOP WO 0 0 The received data byte is not acknowledged automatically by the master. 1 The received data byte is acknowledged automatically by the master. See field decoding in Table 16-5 on page 800. Generate STOP Value Description 1 START WO 0 0 The controller does not generate the STOP condition. 1 The controller generates the STOP condition. See field decoding in Table 16-5 on page 800. Generate START Value Description 0 RUN WO 0 The controller does not generate the START condition. 1 The controller generates the START or repeated START condition. See field decoding in Table 16-5 on page 800. I2C Master Enable 0 Value Description 0 The master is disabled. 1 The master is enabled to transmit or receive data. See field decoding in Table 16-5 on page 800. Table 16-5. Write Field Decoding for I2CMCS[3:0] Field Current I2CMSA[0] State R/S Idle I2CMCS[3:0] ACK STOP START RUN Description 0 X a 0 1 1 START condition followed by TRANSMIT (master goes to the Master Transmit state). 0 X 1 1 1 START condition followed by a TRANSMIT and STOP condition (master remains in Idle state). 1 0 0 1 1 START condition followed by RECEIVE operation with negative ACK (master goes to the Master Receive state). 1 0 1 1 1 START condition followed by RECEIVE and STOP condition (master remains in Idle state). 1 1 0 1 1 START condition followed by RECEIVE (master goes to the Master Receive state). 1 1 1 1 1 Illegal All other combinations not listed are non-operations. NOP 800 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 16-5. Write Field Decoding for I2CMCS[3:0] Field (continued) Current I2CMSA[0] State R/S Master Transmit I2CMCS[3:0] Description ACK STOP START RUN X X 0 0 1 TRANSMIT operation (master remains in Master Transmit state). X X 1 0 0 STOP condition (master goes to Idle state). X X 1 0 1 TRANSMIT followed by STOP condition (master goes to Idle state). 0 X 0 1 1 Repeated START condition followed by a TRANSMIT (master remains in Master Transmit state). 0 X 1 1 1 Repeated START condition followed by TRANSMIT and STOP condition (master goes to Idle state). 1 0 0 1 1 Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive state). 1 0 1 1 1 Repeated START condition followed by a TRANSMIT and STOP condition (master goes to Idle state). 1 1 0 1 1 Repeated START condition followed by RECEIVE (master goes to Master Receive state). 1 1 1 1 1 Illegal. All other combinations not listed are non-operations. NOP. X 0 0 0 1 RECEIVE operation with negative ACK (master remains in Master Receive state). X X 1 0 0 STOP condition (master goes to Idle state). X 0 1 0 1 RECEIVE followed by STOP condition (master goes to Idle state). X 1 0 0 1 RECEIVE operation (master remains in Master Receive state). X 1 1 0 1 Illegal. 1 0 0 1 1 Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receive state). 1 0 1 1 1 Repeated START condition followed by RECEIVE and STOP condition (master goes to Idle state). 1 1 0 1 1 Repeated START condition followed by RECEIVE (master remains in Master Receive state). 0 X 0 1 1 Repeated START condition followed by TRANSMIT (master goes to Master Transmit state). 0 X 1 1 1 Repeated START condition followed by TRANSMIT and STOP condition (master goes to Idle state). Master Receive All other combinations not listed are non-operations. b NOP. a. An X in a table cell indicates the bit can be 0 or 1. b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave. July 24, 2011 801 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 3: I2C Master Data (I2CMDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state. I2C Master Data (I2CMDR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DATA R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data Transferred Data transferred during transaction. 802 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register specifies the period of the SCL clock. Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur. I2C Master Timer Period (I2CMTPR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x00C Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset reserved Type Reset TPR RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6:0 TPR R/W 0x1 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SCL Clock Period This field specifies the period of the SCL clock. SCL_PRD = 2×(1 + TPR)×(SCL_LP + SCL_HP)×CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the system clock period in ns. July 24, 2011 803 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Master Interrupt Mask (I2CMIMR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 IM Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 IM R/W 0 Interrupt Mask Value Description 1 The master interrupt is sent to the interrupt controller when the RIS bit in the I2CMRIS register is set. 0 The RIS interrupt is suppressed and not sent to the interrupt controller. 804 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending. I2C Master Raw Interrupt Status (I2CMRIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RIS RO 0 Raw Interrupt Status Value Description 1 A master interrupt is pending. 0 No interrupt. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register. July 24, 2011 805 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled. I2C Master Masked Interrupt Status (I2CMMIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 MIS RO 0 Masked Interrupt Status Value Description 1 An unmasked master interrupt was signaled and is pending. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register. 806 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw and masked interrupts. I2C Master Interrupt Clear (I2CMICR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x01C Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 IC Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 IC WO 0 Interrupt Clear Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the MIS bit in the I2CMMIS register. A read of this register returns no meaningful data. July 24, 2011 807 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave) and sets the interface for test mode loopback. I2C Master Configuration (I2CMCR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SFE MFE RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 SFE R/W 0 reserved RO 0 RO 0 LPBK RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Function Enable Value Description 4 MFE R/W 0 1 Slave mode is enabled. 0 Slave mode is disabled. I2C Master Function Enable Value Description 3:1 reserved RO 0x0 0 LPBK R/W 0 1 Master mode is enabled. 0 Master mode is disabled. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Loopback Value Description 16.7 1 The controller in a test mode loopback configuration. 0 Normal operation. Register Descriptions (I2C Slave) The remainder of this section lists and describes the I2C slave registers, in numerical order by address offset. 808 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus. I2C Slave Own Address (I2CSOAR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x800 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset OAR RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6:0 OAR R/W 0x00 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. July 24, 2011 809 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 This register functions as a control register when written, and a status register when read. Read-Only Status Register I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x804 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2 FBR RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 FBR TREQ RREQ RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. First Byte Received Value Description 1 The first byte following the slave’s own address has been received. 0 The first byte has not been received. This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the I2CSDR register. Note: 1 TREQ RO 0 This bit is not used for slave transmit operations. Transmit Request Value Description 0 RREQ RO 0 1 The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the I2CSDR register. 0 No outstanding transmit request. Receive Request Value Description 1 The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until the data has been read from the I2CSDR register. 0 No outstanding receive data. 810 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Write-Only Control Register I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x804 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 DA WO 0 RO 0 DA Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Active Value Description 0 Disables the I2C slave operation. 1 Enables the I2C slave operation. July 24, 2011 811 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 12: I2C Slave Data (I2CSDR), offset 0x808 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. I2C Slave Data (I2CSDR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x808 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DATA R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. 812 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Slave Interrupt Mask (I2CSIMR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x80C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STOPIM STARTIM DATAIM R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 STOPIM R/W 0 Stop Condition Interrupt Mask Value Description 1 STARTIM R/W 0 1 The STOP condition interrupt is sent to the interrupt controller when the STOPRIS bit in the I2CSRIS register is set. 0 The STOPRIS interrupt is suppressed and not sent to the interrupt controller. Start Condition Interrupt Mask Value Description 0 DATAIM R/W 0 1 The START condition interrupt is sent to the interrupt controller when the STARTRIS bit in the I2CSRIS register is set. 0 The STARTRIS interrupt is suppressed and not sent to the interrupt controller. Data Interrupt Mask Value Description 1 The data received or data requested interrupt is sent to the interrupt controller when the DATARIS bit in the I2CSRIS register is set. 0 The DATARIS interrupt is suppressed and not sent to the interrupt controller. July 24, 2011 813 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 This register specifies whether an interrupt is pending. I2C Slave Raw Interrupt Status (I2CSRIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x810 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STOPRIS STARTRIS DATARIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 STOPRIS RO 0 Stop Condition Raw Interrupt Status Value Description 1 A STOP condition interrupt is pending. 0 No interrupt. This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register. 1 STARTRIS RO 0 Start Condition Raw Interrupt Status Value Description 1 A START condition interrupt is pending. 0 No interrupt. This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register. 0 DATARIS RO 0 Data Raw Interrupt Status Value Description 1 A data received or data requested interrupt is pending. 0 No interrupt. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. 814 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 This register specifies whether an interrupt was signaled. I2C Slave Masked Interrupt Status (I2CSMIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x814 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STOPMIS STARTMIS DATAMIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 STOPMIS RO 0 Stop Condition Masked Interrupt Status Value Description 1 An unmasked STOP condition interrupt was signaled is pending. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register. 1 STARTMIS RO 0 Start Condition Masked Interrupt Status Value Description 1 An unmasked START condition interrupt was signaled is pending. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register. 0 DATAMIS RO 0 Data Masked Interrupt Status Value Description 1 An unmasked data received or data requested interrupt was signaled is pending. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. July 24, 2011 815 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 This register clears the raw interrupt. A read of this register returns no meaningful data. I2C Slave Interrupt Clear (I2CSICR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x818 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STOPIC STARTIC WO 0 WO 0 DATAIC WO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 STOPIC WO 0 Stop Condition Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. 1 STARTIC WO 0 Start Condition Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. 0 DATAIC WO 0 Data Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. 816 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 17 Analog Comparators An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. Note: Not all comparators have the option to drive an output pin. See “Signal Description” on page 818 for more information. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board. In addition, the comparator can signal the application via interrupts or trigger the start of a sample sequence in the ADC. The interrupt generation and ADC triggering logic is separate and independent. This flexibility means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. ® The Stellaris LM3S1F11 microcontroller provides two independent integrated analog comparators with the following functions: ■ Compare external pin input to external pin input or to internal programmable voltage reference ■ Compare a test voltage against any one of the following voltages: – An individual external reference voltage – A shared single external reference voltage – A shared internal reference voltage 17.1 Block Diagram Figure 17-1. Analog Comparator Module Block Diagram C1- -ve input C1+ +ve input Comparator 1 output +ve input (alternate) trigger ACCTL1 C1o trigger ACSTAT1 interrupt reference input C0- -ve input C0+ +ve input Comparator 0 output +ve input (alternate) trigger ACCTL0 C0o trigger ACSTAT0 interrupt reference input Voltage Ref internal bus ACREFCTL Interrupt Control ACRIS ACMIS ACINTEN interrupt July 24, 2011 817 Texas Instruments-Production Data Analog Comparators 17.2 Signal Description The following table lists the external signals of the Analog Comparators and describes the function of each. The Analog Comparator output signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the Analog Comparator signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 424) should be set to choose the Analog Comparator function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 442) to assign the Analog Comparator signal to the specified GPIO port pin. The positive and negative input signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 400. Table 17-1. Signals for Analog Comparators (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment PB6 a Pin Type Buffer Type Description I Analog Analog comparator 0 positive input. Analog comparator 0 negative input. C0+ 90 C0- 92 PB4 I Analog C0o 24 58 90 91 100 PC5 (3) PF4 (2) PB6 (3) PB5 (1) PD7 (2) O TTL C1+ 24 PC5 I Analog Analog comparator 1 positive input. C1- 91 PB5 I Analog Analog comparator 1 negative input. C1o 2 22 24 46 84 PE6 (2) PC7 (7) PC5 (2) PF5 (2) PH2 (2) O TTL Analog comparator 0 output. Analog comparator 1 output. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 17-2. Signals for Analog Comparators (108BGA) Pin Name C0+ Pin Number Pin Mux / Pin Assignment A7 PB6 a Pin Type Buffer Type I Analog Analog comparator 0 positive input. Analog comparator 0 negative input. C0- A6 PB4 I Analog C0o M1 L9 A7 B7 A2 PC5 (3) PF4 (2) PB6 (3) PB5 (1) PD7 (2) O TTL Description Analog comparator 0 output. C1+ M1 PC5 I Analog Analog comparator 1 positive input. C1- B7 PB5 I Analog Analog comparator 1 negative input. C1o A1 L2 M1 L8 D11 PE6 (2) PC7 (7) PC5 (2) PF5 (2) PH2 (2) O TTL Analog comparator 1 output. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 818 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 17.3 Functional Description The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT. VIN- < VIN+, VOUT = 1 VIN- > VIN+, VOUT = 0 As shown in Figure 17-2 on page 819, the input source for VIN- is an external input, Cn-. In addition to an external input, Cn+, input sources for VIN+ can be the C0+ or an internal reference, VIREF. Figure 17-2. Structure of Comparator Unit - ve input + ve input (alternate) reference input 0 output CINV 1 IntGen 2 TrigGen internal bus ACCTL ACSTAT trigger interrupt + ve input A comparator is configured through two status/control registers, Analog Comparator Control (ACCTL) and Analog Comparator Status (ACSTAT). The internal reference is configured through one control register, Analog Comparator Reference Voltage Control (ACREFCTL). Interrupt status and control are configured through three registers, Analog Comparator Masked Interrupt Status (ACMIS), Analog Comparator Raw Interrupt Status (ACRIS), and Analog Comparator Interrupt Enable (ACINTEN). Typically, the comparator output is used internally to generate an interrupt as controlled by the ISEN bit in the ACCTL register. The output may also be used to drive an external pin, Co or generate an analog-to-digital converter (ADC) trigger. Important: The ASRCP bits in the ACCTL register must be set before using the analog comparators. 17.3.1 Internal Reference Programming The structure of the internal reference is shown in Figure 17-3 on page 820. The internal reference is controlled by a single configuration register (ACREFCTL). Table 17-3 on page 820 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally (VIREF). July 24, 2011 819 Texas Instruments-Production Data Analog Comparators Figure 17-3. Comparator Internal Reference Structure 8R VDDA 8R R R R ••• EN 15 14 ••• 1 0 Decoder VREF internal reference VIREF RNG Table 17-3. Internal Reference Voltage and ACREFCTL Field Values ACREFCTL Register EN Bit Value EN=0 RNG Bit Value Output Reference Voltage Based on VREF Field Value RNG=X 0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0 for the least noisy ground reference. RNG=0 Total resistance in ladder is 31 R. RVREF RT RVREF VIREF = VDDA × RVREF RT + 8) VIREF = VDDA × (VREF VIREF = VDDA × RT 31 + 8) (VREF VIREF = VDDA × (VREF + 8) RVREF 31 × VREF V DDA 0DDA .85× .106 IREF = VIREF = V V ×+R0VREF RT 31 IREF = VDDA × VIREF V = 0.85 +R0VREF R.T 106 × VREF IREF = DDA V V ×+R0VREF V IREF = 0 . 85 ( ) VREF VIREF = VDDA × VREF R.T 106+ ×8VREF VIREF = VDDA × R R T IREF = VDDA × (VREF VIREF 31 + 8) V = VDDAreference × RVREF RTin 31 The range this mode is 0.85-2.448 V. IREF of=internal DDA × VREF V V VIREF = VDDA × (VREF + 8) R T Total resistance in ladder is 23 R. VIREF = V 0DDA .85×+VREF 023 .106 × VREF 31 × VREF VIREF = V 0DDA .85×+VREF 0.106 23 VREF R × × VREF V IREF = V 0DDA .143 IREF = V 23 VIREF = V 0DDA .85×+R0VREF .T 106 × VREF IREF = VIREF × ×RVREF V = V 0DDA .143 RVREF T R V IREF = 0.143 VREF ×VREF IREF = VDDA × V VIREF = VDDA × VREF RT VIREF = VDDA × 23 23 VREF × × VREF VIREF = V 0DDA .143 VIREF = 0.143 × 23 VREF VIREF = VDDA × EN=1 RNG=1 VIREF = 0.143 × VREF The range of internal reference for this mode is 0-2.152 V. 820 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 17.4 Initialization and Configuration The following example shows how to configure an analog comparator to read back its output value from an internal register. 1. Enable the analog comparator clock by writing a value of 0x0010.0000 to the RCGC1 register in the System Control module (see page 246). 2. Enable the clock to the appropriate GPIO modules via the RCGC2 register (see page 255). To find out which GPIO ports to enable, refer to Table 19-5 on page 854. 3. In the GPIO module, enable the GPIO port/pin associated with the input signals as GPIO inputs. To determine which GPIO to configure, see Table 19-4 on page 848. 4. Configure the PMCn fields in the GPIOPCTL register to assign the analog comparator output signals to the appropriate pins (see page 442 and Table 19-5 on page 854). 5. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the value 0x0000.030C. 6. Configure the comparator to use the internal voltage reference and to not invert the output by writing the ACCTLn register with the value of 0x0000.040C. 7. Delay for 10 µs. 8. Read the comparator output value by reading the ACSTATn register’s OVAL value. Change the level of the comparator negative input signal C- to see the OVAL value change. 17.5 Register Map Table 17-4 on page 821 lists the comparator registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Analog Comparator base address of 0x4003.C000. Note that the analog comparator clock must be enabled before the registers can be programmed (see page 246). There must be a delay of 3 system clocks after the analog comparator module clock is enabled before any analog comparator module registers are accessed. Table 17-4. Analog Comparators Register Map Description See page Offset Name Type Reset 0x000 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 823 0x004 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 824 0x008 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 825 0x010 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 826 0x020 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 827 0x024 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 828 0x040 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 827 0x044 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 828 July 24, 2011 821 Texas Instruments-Production Data Analog Comparators 17.6 Register Descriptions The remainder of this section lists and describes the Analog Comparator registers, in numerical order by address offset. 822 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 This register provides a summary of the interrupt status (masked) of the comparators. Analog Comparator Masked Interrupt Status (ACMIS) Base 0x4003.C000 Offset 0x000 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 IN1 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator 1 Masked Interrupt Status Value Description 1 The IN1 bits in the ACRIS register and the ACINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the IN1 bit in the ACRIS register. 0 IN0 R/W1C 0 Comparator 0 Masked Interrupt Status Value Description 1 The IN0 bits in the ACRIS register and the ACINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the IN0 bit in the ACRIS register. July 24, 2011 823 Texas Instruments-Production Data Analog Comparators Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 This register provides a summary of the interrupt status (raw) of the comparators. The bits in this register must be enabled to generate interrupts using the ACINTEN register. Analog Comparator Raw Interrupt Status (ACRIS) Base 0x4003.C000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 IN1 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator 1 Interrupt Status Value Description 1 Comparator 1 has generated an interruptfor an event as configured by the ISEN bit in the ACCTL1 register. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN1 bit in the ACMIS register. 0 IN0 RO 0 Comparator 0 Interrupt Status Value Description 1 Comparator 0 has generated an interrupt for an event as configured by the ISEN bit in the ACCTL0 register. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN0 bit in the ACMIS register. 824 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 This register provides the interrupt enable for the comparators. Analog Comparator Interrupt Enable (ACINTEN) Base 0x4003.C000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 IN1 R/W 0 Comparator 1 Interrupt Enable Value Description 0 IN0 R/W 0 1 The raw interrupt signal comparator 1 is sent to the interrupt controller. 0 A comparator 1 interrupt does not affect the interrupt status. Comparator 0 Interrupt Enable Value Description 1 The raw interrupt signal comparator 0 is sent to the interrupt controller. 0 A comparator 0 interrupt does not affect the interrupt status. July 24, 2011 825 Texas Instruments-Production Data Analog Comparators Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 This register specifies whether the resistor ladder is powered on as well as the range and tap. Analog Comparator Reference Voltage Control (ACREFCTL) Base 0x4003.C000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 9 8 EN RNG R/W 0 R/W 0 Bit/Field Name Type Reset 31:10 reserved RO 0x0000.0 9 EN R/W 0 reserved RO 0 RO 0 RO 0 VREF RO 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Resistor Ladder Enable Value Description 0 The resistor ladder is unpowered. 1 Powers on the resistor ladder. The resistor ladder is connected to VDDA. This bit is cleared at reset so that the internal reference consumes the least amount of power if it is not used. 8 RNG R/W 0 Resistor Ladder Range Value Description 0 The resistor ladder has a total resistance of 31 R. 1 The resistor ladder has a total resistance of 23 R. 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 VREF R/W 0x0 Resistor Ladder Voltage Ref The VREF bit field specifies the resistor ladder tap that is passed through an analog multiplexer. The voltage corresponding to the tap position is the internal reference voltage available for comparison. See Table 17-3 on page 820 for some output reference voltage examples. 826 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 These registers specify the current output value of the comparator. Analog Comparator Status 0 (ACSTAT0) Base 0x4003.C000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 OVAL reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 OVAL RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator Output Value Value Description 0 VIN- > VIN+ 1 VIN- < VIN+ VIN - is the voltage on the Cn- pin. VIN+ is the voltage on the Cn+ pin, the C0+ pin, or the internal voltage reference (VIREF) as defined by the ASRCP bit in the ACCTL register. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 827 Texas Instruments-Production Data Analog Comparators Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 These registers configure the comparator’s input and output. Analog Comparator Control 0 (ACCTL0) Base 0x4003.C000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 reserved TSLVAL CINV reserved RO 0 R/W 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset TOEN RO 0 RO 0 ASRCP R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TOEN R/W 0 TSEN R/W 0 ISLVAL R/W 0 R/W 0 ISEN R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Trigger Output Enable Value Description 10:9 ASRCP R/W 0x0 0 ADC events are suppressed and not sent to the ADC. 1 ADC events are sent to the ADC. Analog Source Positive The ASRCP field specifies the source of input voltage to the VIN+ terminal of the comparator. The encodings for this field are as follows: Value Description 0x0 Pin value of Cn+ 0x1 Pin value of C0+ 0x2 Internal voltage reference (VIREF) 0x3 Reserved 8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 TSLVAL R/W 0 Trigger Sense Level Value Value Description 0 An ADC event is generated if the comparator output is Low. 1 An ADC event is generated if the comparator output is High. 828 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Bit/Field Name Type Reset 6:5 TSEN R/W 0x0 Description Trigger Sense The TSEN field specifies the sense of the comparator output that generates an ADC event. The sense conditioning is as follows: Value Description 4 ISLVAL R/W 0 0x0 Level sense, see TSLVAL 0x1 Falling edge 0x2 Rising edge 0x3 Either edge Interrupt Sense Level Value Value Description 3:2 ISEN R/W 0x0 0 An interrupt is generated if the comparator output is Low. 1 An interrupt is generated if the comparator output is High. Interrupt Sense The ISEN field specifies the sense of the comparator output that generates an interrupt. The sense conditioning is as follows: Value Description 1 CINV R/W 0 0x0 Level sense, see ISLVAL 0x1 Falling edge 0x2 Rising edge 0x3 Either edge Comparator Output Invert Value Description 0 reserved RO 0 0 The output of the comparator is unchanged. 1 The output of the comparator is inverted prior to being processed by hardware. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 24, 2011 829 Texas Instruments-Production Data Pin Diagram 18 Pin Diagram The LM3S1F11 microcontroller pin diagram is shown below. Each GPIO signal is identified by its GPIO port unless it defaults to an alternate function on reset. In this case, the GPIO port name is followed by the default alternate function. To see a complete list of possible functions for each pin, see Table 19-5 on page 854. Figure 18-1. 100-Pin LQFP Package Pin Diagram 830 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) July 24, 2011 831 Texas Instruments-Production Data Signal Tables 19 Signal Tables The following tables list the signals available for each pin. Signals are configured as GPIOs on reset, except for those noted below. Use the GPIOAMSEL register (see page 440) to select analog mode. For a GPIO pin to be used for an alternate digital function, the corresponding bit in the GPIOAFSEL register (see page 424) must be set. Further pin muxing options are provided through the PMCx bit field in the GPIOPCTL register (see page 442), which selects one of several available peripheral functions for that GPIO. Important: All GPIO pins are configured as GPIOs by default with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 19-1. GPIO Pins With Default Alternate Functions GPIO Pin Default State GPIOAFSEL Bit GPIOPCTL PMCx Bit Field PA[1:0] UART0 0 0x1 PA[5:2] SSI0 0 0x1 PB[3:2] I2C0 0 0x1 PC[3:0] JTAG/SWD 1 0x3 Table 19-2 on page 833 shows the pin-to-signal-name mapping, including functional characteristics of the signals. Each possible alternate analog and digital function is listed for each pin. Table 19-3 on page 841 lists the signals in alphabetical order by signal name. If it is possible for a signal to be on multiple pins, each possible pin assignment is listed. The "Pin Mux" column indicates the GPIO and the encoding needed in the PMCx bit field in the GPIOPCTL register. Table 19-4 on page 848 groups the signals by functionality, except for GPIOs. If it is possible for a signal to be on multiple pins, each possible pin assignment is listed. Table 19-5 on page 854 lists the GPIO pins and their analog and digital alternate functions. The AINx and VREFA analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to their circuitry (C0-, C0+, C1-, C1+). These signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. The digital signals are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric enoding shown in the table below. Table entries that are shaded gray are the default values for the corresponding GPIO pin. Table 19-6 on page 856 lists the signals based on number of possible pin assignments. This table can be used to plan how to configure the pins for a particular functionality. Application Note AN01274 ® Configuring Stellaris Microcontrollers with Pin Multiplexing provides an overview of the pin muxing implementation, an explanation of how a system designer defines a pin configuration, and examples of the pin configuration process. Note: All digital inputs are Schmitt triggered. 832 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 19.1 100-Pin LQFP Package Pin Tables Table 19-2. Signals by Pin Number Pin Number 1 a Pin Name Pin Type Buffer Type PE7 I/O TTL GPIO port E bit 7. AIN0 I Analog U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. Analog-to-digital converter input 0. GPIO port E bit 6. PE6 I/O TTL AIN1 I Analog C1o O TTL Analog comparator 1 output. 2 Analog-to-digital converter input 1. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. VDDA - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. GNDA - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. PE5 I/O TTL AIN2 I Analog CCP5 I/O TTL Capture/Compare/PWM 5. GPIO port E bit 4. 3 4 5 Description GPIO port E bit 5. Analog-to-digital converter input 2. PE4 I/O TTL AIN3 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. CCP3 I/O TTL Capture/Compare/PWM 3. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. LDO - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). 8 VDD - Power Positive supply for I/O and some logic. 9 GND - Power Ground reference for logic and I/O pins. PD0 I/O TTL GPIO port D bit 0. 6 7 10 Analog-to-digital converter input 3. CCP6 I/O TTL Capture/Compare/PWM 6. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. July 24, 2011 833 Texas Instruments-Production Data Signal Tables Table 19-2. Signals by Pin Number (continued) Pin Number 11 12 a Pin Name Pin Type Buffer Type Description PD1 I/O TTL GPIO port D bit 1. CCP2 I/O TTL Capture/Compare/PWM 2. CCP7 I/O TTL Capture/Compare/PWM 7. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PD2 I/O TTL GPIO port D bit 2. CCP5 I/O TTL Capture/Compare/PWM 5. CCP6 I/O TTL Capture/Compare/PWM 6. EPI0S20 I/O TTL EPI module 0 signal 20. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. PD3 I/O TTL GPIO port D bit 3. CCP0 I/O TTL Capture/Compare/PWM 0. CCP7 I/O TTL Capture/Compare/PWM 7. EPI0S21 I/O TTL EPI module 0 signal 21. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PJ0 I/O TTL GPIO port J bit 0. EPI0S16 I/O TTL EPI module 0 signal 16. I2C1SCL I/O OD I2C module 1 clock. PH7 I/O TTL GPIO port H bit 7. EPI0S27 I/O TTL EPI module 0 signal 27. SSI1Tx O TTL SSI module 1 transmit. 16 PG3 I/O TTL GPIO port G bit 3. 17 PG2 I/O TTL GPIO port G bit 2. PG1 I/O TTL GPIO port G bit 1. EPI0S14 I/O TTL EPI module 0 signal 14. I2C1SDA I/O OD I2C module 1 data. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PG0 I/O TTL GPIO port G bit 0. EPI0S13 I/O TTL EPI module 0 signal 13. I2C1SCL I/O OD I2C module 1 clock. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. 20 VDD - Power Positive supply for I/O and some logic. 21 GND - Power Ground reference for logic and I/O pins. 13 14 15 18 19 834 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-2. Signals by Pin Number (continued) Pin Number 22 23 24 Pin Type Buffer Type PC7 I/O TTL GPIO port C bit 7. C1o O TTL Analog comparator 1 output. CCP0 I/O TTL Capture/Compare/PWM 0. 27 Description CCP4 I/O TTL Capture/Compare/PWM 4. EPI0S5 I/O TTL EPI module 0 signal 5. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PC6 I/O TTL GPIO port C bit 6. CCP0 I/O TTL Capture/Compare/PWM 0. CCP3 I/O TTL Capture/Compare/PWM 3. EPI0S4 I/O TTL EPI module 0 signal 4. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. PC5 I/O TTL GPIO port C bit 5. C0o O TTL Analog comparator 0 output. C1+ I Analog C1o O TTL Analog comparator 1 output. CCP1 I/O TTL Capture/Compare/PWM 1. CCP3 I/O TTL Capture/Compare/PWM 3. EPI0S3 I/O TTL EPI module 0 signal 3. Analog comparator 1 positive input. PC4 I/O TTL GPIO port C bit 4. CCP1 I/O TTL Capture/Compare/PWM 1. CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. CCP5 I/O TTL Capture/Compare/PWM 5. EPI0S2 I/O TTL EPI module 0 signal 2. PA0 I/O TTL GPIO port A bit 0. I2C1SCL I/O OD I2C module 1 clock. U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. 25 26 a Pin Name PA1 I/O TTL GPIO port A bit 1. I2C1SDA I/O OD I2C module 1 data. U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PA2 I/O TTL GPIO port A bit 2. SSI0Clk I/O TTL SSI module 0 clock. PA3 I/O TTL GPIO port A bit 3. SSI0Fss I/O TTL SSI module 0 frame. 28 29 July 24, 2011 835 Texas Instruments-Production Data Signal Tables Table 19-2. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type Description PA4 I/O TTL GPIO port A bit 4. SSI0Rx I TTL SSI module 0 receive. PA5 I/O TTL GPIO port A bit 5. SSI module 0 transmit. 30 31 SSI0Tx O TTL 32 VDD - Power Positive supply for I/O and some logic. 33 GND - Power Ground reference for logic and I/O pins. PA6 I/O TTL GPIO port A bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. I2C1SCL I/O OD I2C module 1 clock. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. PA7 I/O TTL GPIO port A bit 7. CCP3 I/O TTL Capture/Compare/PWM 3. CCP4 I/O TTL Capture/Compare/PWM 4. I2C1SDA I/O OD I2C module 1 data. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. PG7 I/O TTL GPIO port G bit 7. 34 35 36 CCP5 I/O TTL Capture/Compare/PWM 5. EPI0S31 I/O TTL EPI module 0 signal 31. PG6 I/O TTL GPIO port G bit 6. U1RI I TTL UART module 1 Ring Indicator modem status input signal. VDDC - Power Positive supply for most of the logic function, including the processor core and most peripherals. PJ2 I/O TTL GPIO port J bit 2. 37 38 39 40 CCP0 I/O TTL Capture/Compare/PWM 0. EPI0S18 I/O TTL EPI module 0 signal 18. PG5 I/O TTL GPIO port G bit 5. CCP5 I/O TTL Capture/Compare/PWM 5. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. PG4 I/O TTL GPIO port G bit 4. CCP3 I/O TTL Capture/Compare/PWM 3. EPI0S15 I/O TTL EPI module 0 signal 15. U1RI I TTL UART module 1 Ring Indicator modem status input signal. PF7 I/O TTL GPIO port F bit 7. 41 42 CCP4 I/O TTL Capture/Compare/PWM 4. EPI0S12 I/O TTL EPI module 0 signal 12. PF6 I/O TTL GPIO port F bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. U1RTS O TTL UART module 1 Request to Send modem flow control output line. 44 VDD - Power Positive supply for I/O and some logic. 45 GND - Power Ground reference for logic and I/O pins. 43 836 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-2. Signals by Pin Number (continued) Pin Number 46 Pin Type Buffer Type PF5 I/O TTL GPIO port F bit 5. C1o O TTL Analog comparator 1 output. CCP2 I/O TTL Capture/Compare/PWM 2. EPI0S15 I/O TTL EPI module 0 signal 15. SSI1Tx O TTL SSI module 1 transmit. 49 50 51 PF0 I/O TTL GPIO port F bit 0. I TTL UART module 1 Data Set Ready modem output control line. OSC0 I Analog Main oscillator crystal input or an external clock reference input. OSC1 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. WAKE I TTL An external input that brings the processor out of Hibernate mode when asserted. An output that indicates the processor is in Hibernate mode. HIB O OD XOSC0 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a 4.194304-MHz crystal or a 32.768-kHz oscillator for the Hibernation module RTC. See the CLKSEL bit in the HIBCTL register. XOSC1 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. 52 53 Description U1DSR 47 48 a Pin Name GND - Power Ground reference for logic and I/O pins. VBAT - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. 56 VDD - Power Positive supply for I/O and some logic. 57 GND - Power Ground reference for logic and I/O pins. PF4 I/O TTL GPIO port F bit 4. 54 55 58 C0o O TTL Analog comparator 0 output. CCP0 I/O TTL Capture/Compare/PWM 0. EPI0S12 I/O TTL EPI module 0 signal 12. SSI1Rx I TTL SSI module 1 receive. PF3 I/O TTL GPIO port F bit 3. SSI1Fss I/O TTL SSI module 1 frame. PF2 I/O TTL GPIO port F bit 2. SSI1Clk I/O TTL SSI module 1 clock. PF1 I/O TTL GPIO port F bit 1. CCP3 I/O TTL Capture/Compare/PWM 3. U1RTS O TTL UART module 1 Request to Send modem flow control output line. PH6 I/O TTL GPIO port H bit 6. EPI0S26 I/O TTL EPI module 0 signal 26. SSI1Rx I TTL SSI module 1 receive. PH5 I/O TTL GPIO port H bit 5. EPI0S11 I/O TTL EPI module 0 signal 11. SSI1Fss I/O TTL SSI module 1 frame. RST I TTL System reset input. 59 60 61 62 63 64 July 24, 2011 837 Texas Instruments-Production Data Signal Tables Table 19-2. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type Description PB3 I/O TTL GPIO port B bit 3. I2C0SDA I/O OD I2C module 0 data. PB0 I/O TTL GPIO port B bit 0. This pin is not 5-V tolerant. CCP0 I/O TTL Capture/Compare/PWM 0. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. PB1 I/O TTL GPIO port B bit 1. This pin is not 5-V tolerant. CCP1 I/O TTL Capture/Compare/PWM 1. CCP2 I/O TTL Capture/Compare/PWM 2. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. 68 VDD - Power Positive supply for I/O and some logic. 69 GND - Power Ground reference for logic and I/O pins. 70 NC - - No connect. Leave the pin electrically unconnected/isolated. 71 NC - - No connect. Leave the pin electrically unconnected/isolated. 65 66 67 PB2 I/O TTL GPIO port B bit 2. CCP0 I/O TTL Capture/Compare/PWM 0. 72 73 CCP3 I/O TTL Capture/Compare/PWM 3. I2C0SCL I/O OD I2C module 0 clock. NC - - PE0 I/O TTL GPIO port E bit 0. CCP3 I/O TTL Capture/Compare/PWM 3. 74 75 76 77 EPI0S8 I/O TTL EPI module 0 signal 8. SSI1Clk I/O TTL SSI module 1 clock. PE1 I/O TTL GPIO port E bit 1. CCP2 I/O TTL Capture/Compare/PWM 2. CCP6 I/O TTL Capture/Compare/PWM 6. EPI0S9 I/O TTL EPI module 0 signal 9. SSI1Fss I/O TTL SSI module 1 frame. PH4 I/O TTL GPIO port H bit 4. EPI0S10 I/O TTL EPI module 0 signal 10. SSI1Clk I/O TTL SSI module 1 clock. PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI. PC1 I/O TTL GPIO port C bit 1. SWDIO I/O TTL JTAG TMS and SWDIO. TMS I TTL JTAG TMS and SWDIO. 78 79 No connect. Leave the pin electrically unconnected/isolated. 838 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-2. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type PC0 I/O TTL GPIO port C bit 0. 80 SWCLK I TTL JTAG/SWD CLK. TCK I TTL JTAG/SWD CLK. 81 VDD - Power Positive supply for I/O and some logic. 82 GND - Power Ground reference for logic and I/O pins. PH3 I/O TTL GPIO port H bit 3. EPI0S0 I/O TTL EPI module 0 signal 0. PH2 I/O TTL GPIO port H bit 2. 83 84 85 86 87 88 C1o O TTL Analog comparator 1 output. EPI0S1 I/O TTL EPI module 0 signal 1. PH1 I/O TTL GPIO port H bit 1. CCP7 I/O TTL Capture/Compare/PWM 7. EPI0S7 I/O TTL EPI module 0 signal 7. PH0 I/O TTL GPIO port H bit 0. CCP6 I/O TTL Capture/Compare/PWM 6. EPI0S6 I/O TTL EPI module 0 signal 6. PJ1 I/O TTL GPIO port J bit 1. EPI0S17 I/O TTL EPI module 0 signal 17. I2C1SDA I/O OD I2C module 1 data. VDDC - Power PB7 I/O TTL GPIO port B bit 7. NMI I TTL Non-maskable interrupt. PB6 I/O TTL GPIO port B bit 6. C0+ I Analog C0o O TTL Analog comparator 0 output. CCP1 I/O TTL Capture/Compare/PWM 1. CCP5 I/O TTL Capture/Compare/PWM 5. CCP7 I/O TTL Capture/Compare/PWM 7. VREFA I Analog 89 90 Description Positive supply for most of the logic function, including the processor core and most peripherals. Analog comparator 0 positive input. This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 4095. The VREFA input is limited to the range specified in Table 21-26 on page 904. July 24, 2011 839 Texas Instruments-Production Data Signal Tables Table 19-2. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type PB5 I/O TTL GPIO port B bit 5. C0o O TTL Analog comparator 0 output. C1- I Analog CCP0 I/O TTL Capture/Compare/PWM 0. CCP2 I/O TTL Capture/Compare/PWM 2. CCP5 I/O TTL Capture/Compare/PWM 5. CCP6 I/O TTL Capture/Compare/PWM 6. EPI0S22 I/O TTL EPI module 0 signal 22. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PB4 I/O TTL GPIO port B bit 4. C0- I Analog EPI0S23 I/O TTL EPI module 0 signal 23. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. 93 VDD - Power Positive supply for I/O and some logic. 94 GND - Power Ground reference for logic and I/O pins. 91 92 95 96 Analog comparator 1 negative input. Analog comparator 0 negative input. PE2 I/O TTL GPIO port E bit 2. CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. EPI0S24 I/O TTL EPI module 0 signal 24. SSI1Rx I TTL SSI module 1 receive. PE3 I/O TTL GPIO port E bit 3. CCP1 I/O TTL Capture/Compare/PWM 1. CCP7 I/O TTL Capture/Compare/PWM 7. EPI0S25 I/O TTL EPI module 0 signal 25. SSI1Tx O TTL SSI module 1 transmit. PD4 I/O TTL GPIO port D bit 4. AIN7 I Analog CCP0 I/O TTL Capture/Compare/PWM 0. 97 98 Description Analog-to-digital converter input 7. CCP3 I/O TTL Capture/Compare/PWM 3. EPI0S19 I/O TTL EPI module 0 signal 19. U1RI I TTL UART module 1 Ring Indicator modem status input signal. GPIO port D bit 5. PD5 I/O TTL AIN6 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. EPI0S28 I/O TTL EPI module 0 signal 28. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. Analog-to-digital converter input 6. 840 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-2. Signals by Pin Number (continued) Pin Number 99 Pin Name Pin Type a Buffer Type Description PD6 I/O TTL AIN5 I Analog GPIO port D bit 6. EPI0S29 I/O TTL EPI module 0 signal 29. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PD7 I/O TTL GPIO port D bit 7. AIN4 I Analog Analog-to-digital converter input 5. Analog-to-digital converter input 4. C0o O TTL Analog comparator 0 output. CCP1 I/O TTL Capture/Compare/PWM 1. EPI0S30 I/O TTL EPI module 0 signal 30. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. 100 a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 19-3. Signals by Signal Name Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description AIN0 1 PE7 I Analog Analog-to-digital converter input 0. AIN1 2 PE6 I Analog Analog-to-digital converter input 1. AIN2 5 PE5 I Analog Analog-to-digital converter input 2. AIN3 6 PE4 I Analog Analog-to-digital converter input 3. AIN4 100 PD7 I Analog Analog-to-digital converter input 4. AIN5 99 PD6 I Analog Analog-to-digital converter input 5. AIN6 98 PD5 I Analog Analog-to-digital converter input 6. AIN7 97 PD4 I Analog Analog-to-digital converter input 7. C0+ 90 PB6 I Analog Analog comparator 0 positive input. C0- 92 PB4 I Analog Analog comparator 0 negative input. C0o 24 58 90 91 100 PC5 (3) PF4 (2) PB6 (3) PB5 (1) PD7 (2) O TTL C1+ 24 PC5 I Analog Analog comparator 1 positive input. C1- 91 PB5 I Analog Analog comparator 1 negative input. C1o 2 22 24 46 84 PE6 (2) PC7 (7) PC5 (2) PF5 (2) PH2 (2) O TTL Analog comparator 1 output. CCP0 13 22 23 39 58 66 72 91 97 PD3 (4) PC7 (4) PC6 (6) PJ2 (9) PF4 (1) PB0 (1) PB2 (5) PB5 (4) PD4 (1) I/O TTL Capture/Compare/PWM 0. Analog comparator 0 output. July 24, 2011 841 Texas Instruments-Production Data Signal Tables Table 19-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP1 24 25 34 43 67 90 96 100 PC5 (1) PC4 (9) PA6 (2) PF6 (1) PB1 (4) PB6 (1) PE3 (1) PD7 (3) I/O TTL Capture/Compare/PWM 1. CCP2 6 11 25 46 67 75 91 95 98 PE4 (6) PD1 (10) PC4 (5) PF5 (1) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) I/O TTL Capture/Compare/PWM 2. CCP3 6 23 24 35 41 61 72 74 97 PE4 (1) PC6 (1) PC5 (5) PA7 (7) PG4 (1) PF1 (10) PB2 (4) PE0 (3) PD4 (2) I/O TTL Capture/Compare/PWM 3. CCP4 22 25 35 42 95 98 PC7 (1) PC4 (6) PA7 (2) PF7 (1) PE2 (1) PD5 (2) I/O TTL Capture/Compare/PWM 4. CCP5 5 12 25 36 40 90 91 PE5 (1) PD2 (4) PC4 (1) PG7 (8) PG5 (1) PB6 (6) PB5 (2) I/O TTL Capture/Compare/PWM 5. CCP6 10 12 75 86 91 PD0 (6) PD2 (2) PE1 (5) PH0 (1) PB5 (3) I/O TTL Capture/Compare/PWM 6. CCP7 11 13 85 90 96 PD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) I/O TTL Capture/Compare/PWM 7. EPI0S0 83 PH3 (8) I/O TTL EPI module 0 signal 0. EPI0S1 84 PH2 (8) I/O TTL EPI module 0 signal 1. EPI0S2 25 PC4 (8) I/O TTL EPI module 0 signal 2. EPI0S3 24 PC5 (8) I/O TTL EPI module 0 signal 3. 842 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-3. Signals by Signal Name (continued) Pin Name EPI0S4 Pin Number Pin Mux / Pin Assignment 23 PC6 (8) a Pin Type Buffer Type I/O TTL Description EPI module 0 signal 4. EPI0S5 22 PC7 (8) I/O TTL EPI module 0 signal 5. EPI0S6 86 PH0 (8) I/O TTL EPI module 0 signal 6. EPI0S7 85 PH1 (8) I/O TTL EPI module 0 signal 7. EPI0S8 74 PE0 (8) I/O TTL EPI module 0 signal 8. EPI0S9 75 PE1 (8) I/O TTL EPI module 0 signal 9. EPI0S10 76 PH4 (8) I/O TTL EPI module 0 signal 10. EPI0S11 63 PH5 (8) I/O TTL EPI module 0 signal 11. EPI0S12 42 58 PF7 (8) PF4 (8) I/O TTL EPI module 0 signal 12. EPI0S13 19 PG0 (8) I/O TTL EPI module 0 signal 13. EPI0S14 18 PG1 (8) I/O TTL EPI module 0 signal 14. EPI0S15 41 46 PG4 (8) PF5 (8) I/O TTL EPI module 0 signal 15. EPI0S16 14 PJ0 (8) I/O TTL EPI module 0 signal 16. EPI0S17 87 PJ1 (8) I/O TTL EPI module 0 signal 17. EPI0S18 39 PJ2 (8) I/O TTL EPI module 0 signal 18. EPI0S19 97 PD4 (10) I/O TTL EPI module 0 signal 19. EPI0S20 12 PD2 (8) I/O TTL EPI module 0 signal 20. EPI0S21 13 PD3 (8) I/O TTL EPI module 0 signal 21. EPI0S22 91 PB5 (8) I/O TTL EPI module 0 signal 22. EPI0S23 92 PB4 (8) I/O TTL EPI module 0 signal 23. EPI0S24 95 PE2 (8) I/O TTL EPI module 0 signal 24. EPI0S25 96 PE3 (8) I/O TTL EPI module 0 signal 25. EPI0S26 62 PH6 (8) I/O TTL EPI module 0 signal 26. EPI0S27 15 PH7 (8) I/O TTL EPI module 0 signal 27. EPI0S28 98 PD5 (10) I/O TTL EPI module 0 signal 28. EPI0S29 99 PD6 (10) I/O TTL EPI module 0 signal 29. EPI0S30 100 PD7 (10) I/O TTL EPI module 0 signal 30. EPI0S31 36 PG7 (9) I/O TTL EPI module 0 signal 31. GND 9 21 33 45 54 57 69 82 94 fixed - Power Ground reference for logic and I/O pins. GNDA 4 fixed - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. HIB 51 fixed O OD An output that indicates the processor is in Hibernate mode. July 24, 2011 843 Texas Instruments-Production Data Signal Tables Table 19-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description I2C0SCL 72 PB2 (1) I/O OD I2C module 0 clock. I2C0SDA 65 PB3 (1) I/O OD I2C module 0 data. I2C1SCL 14 19 26 34 PJ0 (11) PG0 (3) PA0 (8) PA6 (1) I/O OD I2C module 1 clock. I2C1SDA 18 27 35 87 PG1 (3) PA1 (8) PA7 (1) PJ1 (11) I/O OD I2C module 1 data. LDO 7 fixed - Power NC 70 71 73 fixed - - NMI 89 PB7 (4) I TTL OSC0 48 fixed I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. PA0 26 - I/O TTL Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). No connect. Leave the pin electrically unconnected/isolated. Non-maskable interrupt. GPIO port A bit 0. PA1 27 - I/O TTL GPIO port A bit 1. PA2 28 - I/O TTL GPIO port A bit 2. PA3 29 - I/O TTL GPIO port A bit 3. PA4 30 - I/O TTL GPIO port A bit 4. PA5 31 - I/O TTL GPIO port A bit 5. PA6 34 - I/O TTL GPIO port A bit 6. PA7 35 - I/O TTL GPIO port A bit 7. PB0 66 - I/O TTL GPIO port B bit 0. This pin is not 5-V tolerant. PB1 67 - I/O TTL GPIO port B bit 1. This pin is not 5-V tolerant. PB2 72 - I/O TTL GPIO port B bit 2. PB3 65 - I/O TTL GPIO port B bit 3. PB4 92 - I/O TTL GPIO port B bit 4. PB5 91 - I/O TTL GPIO port B bit 5. PB6 90 - I/O TTL GPIO port B bit 6. PB7 89 - I/O TTL GPIO port B bit 7. PC0 80 - I/O TTL GPIO port C bit 0. PC1 79 - I/O TTL GPIO port C bit 1. PC2 78 - I/O TTL GPIO port C bit 2. PC3 77 - I/O TTL GPIO port C bit 3. PC4 25 - I/O TTL GPIO port C bit 4. 844 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-3. Signals by Signal Name (continued) Pin Name PC5 Pin Number Pin Mux / Pin Assignment 24 - a Pin Type Buffer Type I/O TTL Description GPIO port C bit 5. PC6 23 - I/O TTL GPIO port C bit 6. PC7 22 - I/O TTL GPIO port C bit 7. PD0 10 - I/O TTL GPIO port D bit 0. PD1 11 - I/O TTL GPIO port D bit 1. PD2 12 - I/O TTL GPIO port D bit 2. PD3 13 - I/O TTL GPIO port D bit 3. PD4 97 - I/O TTL GPIO port D bit 4. PD5 98 - I/O TTL GPIO port D bit 5. PD6 99 - I/O TTL GPIO port D bit 6. PD7 100 - I/O TTL GPIO port D bit 7. PE0 74 - I/O TTL GPIO port E bit 0. PE1 75 - I/O TTL GPIO port E bit 1. PE2 95 - I/O TTL GPIO port E bit 2. PE3 96 - I/O TTL GPIO port E bit 3. PE4 6 - I/O TTL GPIO port E bit 4. PE5 5 - I/O TTL GPIO port E bit 5. PE6 2 - I/O TTL GPIO port E bit 6. PE7 1 - I/O TTL GPIO port E bit 7. PF0 47 - I/O TTL GPIO port F bit 0. PF1 61 - I/O TTL GPIO port F bit 1. PF2 60 - I/O TTL GPIO port F bit 2. PF3 59 - I/O TTL GPIO port F bit 3. PF4 58 - I/O TTL GPIO port F bit 4. PF5 46 - I/O TTL GPIO port F bit 5. PF6 43 - I/O TTL GPIO port F bit 6. PF7 42 - I/O TTL GPIO port F bit 7. PG0 19 - I/O TTL GPIO port G bit 0. PG1 18 - I/O TTL GPIO port G bit 1. PG2 17 - I/O TTL GPIO port G bit 2. PG3 16 - I/O TTL GPIO port G bit 3. PG4 41 - I/O TTL GPIO port G bit 4. PG5 40 - I/O TTL GPIO port G bit 5. PG6 37 - I/O TTL GPIO port G bit 6. PG7 36 - I/O TTL GPIO port G bit 7. PH0 86 - I/O TTL GPIO port H bit 0. PH1 85 - I/O TTL GPIO port H bit 1. PH2 84 - I/O TTL GPIO port H bit 2. PH3 83 - I/O TTL GPIO port H bit 3. PH4 76 - I/O TTL GPIO port H bit 4. PH5 63 - I/O TTL GPIO port H bit 5. July 24, 2011 845 Texas Instruments-Production Data Signal Tables Table 19-3. Signals by Signal Name (continued) Pin Name PH6 Pin Number Pin Mux / Pin Assignment 62 - a Pin Type Buffer Type I/O TTL Description GPIO port H bit 6. PH7 15 - I/O TTL GPIO port H bit 7. PJ0 14 - I/O TTL GPIO port J bit 0. PJ1 87 - I/O TTL GPIO port J bit 1. PJ2 39 - I/O TTL GPIO port J bit 2. RST 64 fixed I TTL System reset input. SSI0Clk 28 PA2 (1) I/O TTL SSI module 0 clock. SSI0Fss 29 PA3 (1) I/O TTL SSI module 0 frame. SSI0Rx 30 PA4 (1) I TTL SSI module 0 receive. SSI0Tx 31 PA5 (1) O TTL SSI module 0 transmit. SSI1Clk 60 74 76 PF2 (9) PE0 (2) PH4 (11) I/O TTL SSI module 1 clock. SSI1Fss 59 63 75 PF3 (9) PH5 (11) PE1 (2) I/O TTL SSI module 1 frame. SSI1Rx 58 62 95 PF4 (9) PH6 (11) PE2 (2) I TTL SSI module 1 receive. SSI1Tx 15 46 96 PH7 (11) PF5 (9) PE3 (2) O TTL SSI module 1 transmit. SWCLK 80 PC0 (3) I TTL JTAG/SWD CLK. SWDIO 79 PC1 (3) I/O TTL JTAG TMS and SWDIO. SWO 77 PC3 (3) O TTL JTAG TDO and SWO. TCK 80 PC0 (3) I TTL JTAG/SWD CLK. TDI 78 PC2 (3) I TTL JTAG TDI. TDO 77 PC3 (3) O TTL JTAG TDO and SWO. TMS 79 PC1 (3) I TTL JTAG TMS and SWDIO. U0Rx 26 PA0 (1) I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 PA1 (1) O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS 2 10 34 PE6 (9) PD0 (9) PA6 (9) I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD 1 11 35 PE7 (9) PD1 (9) PA7 (9) I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR 47 PF0 (9) I TTL UART module 1 Data Set Ready modem output control line. U1DTR 40 100 PG5 (10) PD7 (9) O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI 37 41 97 PG6 (10) PG4 (10) PD4 (9) I TTL UART module 1 Ring Indicator modem status input signal. 846 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description U1RTS 43 61 PF6 (10) PF1 (9) O TTL UART module 1 Request to Send modem flow control output line. U1Rx 10 12 23 26 66 92 PD0 (5) PD2 (1) PC6 (5) PA0 (9) PB0 (5) PB4 (7) I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 11 13 22 27 67 91 PD1 (5) PD3 (1) PC7 (5) PA1 (9) PB1 (5) PB5 (7) O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx 10 19 92 98 PD0 (4) PG0 (1) PB4 (4) PD5 (9) I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx 6 11 18 99 PE4 (5) PD1 (4) PG1 (1) PD6 (9) O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. VBAT 55 fixed - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. VDD 8 20 32 44 56 68 81 93 fixed - Power Positive supply for I/O and some logic. VDDA 3 fixed - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. VDDC 38 88 fixed - Power Positive supply for most of the logic function, including the processor core and most peripherals. VREFA 90 PB6 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 4095. The VREFA input is limited to the range specified in Table 21-26 on page 904. WAKE 50 fixed I TTL An external input that brings the processor out of Hibernate mode when asserted. July 24, 2011 847 Texas Instruments-Production Data Signal Tables Table 19-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description XOSC0 52 fixed I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a 4.194304-MHz crystal or a 32.768-kHz oscillator for the Hibernation module RTC. See the CLKSEL bit in the HIBCTL register. XOSC1 53 fixed O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 19-4. Signals by Function, Except for GPIO Function ADC Pin Name a Pin Number Pin Type Buffer Type AIN0 1 I Analog Analog-to-digital converter input 0. Description AIN1 2 I Analog Analog-to-digital converter input 1. AIN2 5 I Analog Analog-to-digital converter input 2. AIN3 6 I Analog Analog-to-digital converter input 3. AIN4 100 I Analog Analog-to-digital converter input 4. AIN5 99 I Analog Analog-to-digital converter input 5. AIN6 98 I Analog Analog-to-digital converter input 6. AIN7 97 I Analog Analog-to-digital converter input 7. VREFA 90 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 4095. The VREFA input is limited to the range specified in Table 21-26 on page 904. C0+ 90 I Analog Analog comparator 0 positive input. C0- 92 I Analog Analog comparator 0 negative input. C0o 24 58 90 91 100 O TTL C1+ 24 I Analog Analog comparator 1 positive input. C1- 91 I Analog Analog comparator 1 negative input. C1o 2 22 24 46 84 O TTL Analog Comparators Analog comparator 0 output. Analog comparator 1 output. 848 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-4. Signals by Function, Except for GPIO (continued) Function External Peripheral Interface Pin Name a Pin Number Pin Type Buffer Type Description EPI0S0 83 I/O TTL EPI module 0 signal 0. EPI0S1 84 I/O TTL EPI module 0 signal 1. EPI0S2 25 I/O TTL EPI module 0 signal 2. EPI0S3 24 I/O TTL EPI module 0 signal 3. EPI0S4 23 I/O TTL EPI module 0 signal 4. EPI0S5 22 I/O TTL EPI module 0 signal 5. EPI0S6 86 I/O TTL EPI module 0 signal 6. EPI0S7 85 I/O TTL EPI module 0 signal 7. EPI0S8 74 I/O TTL EPI module 0 signal 8. EPI0S9 75 I/O TTL EPI module 0 signal 9. EPI0S10 76 I/O TTL EPI module 0 signal 10. EPI0S11 63 I/O TTL EPI module 0 signal 11. EPI0S12 42 58 I/O TTL EPI module 0 signal 12. EPI0S13 19 I/O TTL EPI module 0 signal 13. EPI0S14 18 I/O TTL EPI module 0 signal 14. EPI0S15 41 46 I/O TTL EPI module 0 signal 15. EPI0S16 14 I/O TTL EPI module 0 signal 16. EPI0S17 87 I/O TTL EPI module 0 signal 17. EPI0S18 39 I/O TTL EPI module 0 signal 18. EPI0S19 97 I/O TTL EPI module 0 signal 19. EPI0S20 12 I/O TTL EPI module 0 signal 20. EPI0S21 13 I/O TTL EPI module 0 signal 21. EPI0S22 91 I/O TTL EPI module 0 signal 22. EPI0S23 92 I/O TTL EPI module 0 signal 23. EPI0S24 95 I/O TTL EPI module 0 signal 24. EPI0S25 96 I/O TTL EPI module 0 signal 25. EPI0S26 62 I/O TTL EPI module 0 signal 26. EPI0S27 15 I/O TTL EPI module 0 signal 27. EPI0S28 98 I/O TTL EPI module 0 signal 28. EPI0S29 99 I/O TTL EPI module 0 signal 29. EPI0S30 100 I/O TTL EPI module 0 signal 30. EPI0S31 36 I/O TTL EPI module 0 signal 31. July 24, 2011 849 Texas Instruments-Production Data Signal Tables Table 19-4. Signals by Function, Except for GPIO (continued) Function General-Purpose Timers Pin Name a Pin Number Pin Type Buffer Type CCP0 13 22 23 39 58 66 72 91 97 I/O TTL Capture/Compare/PWM 0. CCP1 24 25 34 43 67 90 96 100 I/O TTL Capture/Compare/PWM 1. CCP2 6 11 25 46 67 75 91 95 98 I/O TTL Capture/Compare/PWM 2. CCP3 6 23 24 35 41 61 72 74 97 I/O TTL Capture/Compare/PWM 3. CCP4 22 25 35 42 95 98 I/O TTL Capture/Compare/PWM 4. CCP5 5 12 25 36 40 90 91 I/O TTL Capture/Compare/PWM 5. CCP6 10 12 75 86 91 I/O TTL Capture/Compare/PWM 6. I/O TTL Capture/Compare/PWM 7. CCP7 Description 850 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-4. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Number a Pin Type Buffer Type Description 11 13 85 90 96 HIB 51 O OD VBAT 55 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE 50 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 52 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a 4.194304-MHz crystal or a 32.768-kHz oscillator for the Hibernation module RTC. See the CLKSEL bit in the HIBCTL register. XOSC1 53 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. I2C0SCL 72 I/O OD I2C module 0 clock. I2C0SDA 65 I/O OD I2C module 0 data. I2C1SCL 14 19 26 34 I/O OD I2C module 1 clock. I2C1SDA 18 27 35 87 I/O OD I2C module 1 data. SWCLK 80 I TTL JTAG/SWD CLK. SWDIO 79 I/O TTL JTAG TMS and SWDIO. SWO 77 O TTL JTAG TDO and SWO. TCK 80 I TTL JTAG/SWD CLK. TDI 78 I TTL JTAG TDI. TDO 77 O TTL JTAG TDO and SWO. TMS 79 I TTL JTAG TMS and SWDIO. Hibernate I2C JTAG/SWD/SWO An output that indicates the processor is in Hibernate mode. July 24, 2011 851 Texas Instruments-Production Data Signal Tables Table 19-4. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type GND 9 21 33 45 54 57 69 82 94 - Power Ground reference for logic and I/O pins. GNDA 4 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. LDO 7 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). VDD 8 20 32 44 56 68 81 93 - Power Positive supply for I/O and some logic. VDDA 3 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. VDDC 38 88 - Power Positive supply for most of the logic function, including the processor core and most peripherals. SSI0Clk 28 I/O TTL SSI module 0 clock. SSI0Fss 29 I/O TTL SSI module 0 frame. SSI0Rx 30 I TTL SSI module 0 receive. SSI0Tx 31 O TTL SSI module 0 transmit. SSI1Clk 60 74 76 I/O TTL SSI module 1 clock. SSI1Fss 59 63 75 I/O TTL SSI module 1 frame. SSI1Rx 58 62 95 I TTL SSI module 1 receive. SSI1Tx 15 46 96 O TTL SSI module 1 transmit. Power SSI Description 852 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-4. Signals by Function, Except for GPIO (continued) Function System Control & Clocks Pin Name a Pin Number Pin Type NMI 89 I TTL OSC0 48 I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 64 I TTL System reset input. U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS 2 10 34 I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD 1 11 35 I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR 47 I TTL UART module 1 Data Set Ready modem output control line. U1DTR 40 100 O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI 37 41 97 I TTL UART module 1 Ring Indicator modem status input signal. U1RTS 43 61 O TTL UART module 1 Request to Send modem flow control output line. U1Rx 10 12 23 26 66 92 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 11 13 22 27 67 91 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx 10 19 92 98 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx 6 11 18 99 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. UART Buffer Type Description Non-maskable interrupt. a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 24, 2011 853 Texas Instruments-Production Data Signal Tables Table 19-5. GPIO Pins and Alternate Functions a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PA0 26 - U0Rx - - - - - - I2C1SCL U1Rx - - PA1 27 - U0Tx - - - - - - I2C1SDA U1Tx - - PA2 28 - SSI0Clk - - - - - - - - - - PA3 29 - SSI0Fss - - - - - - - - - - PA4 30 - SSI0Rx - - - - - - - - - - PA5 31 - SSI0Tx - - - - - - - - - - PA6 34 - I2C1SCL CCP1 - - - - - - U1CTS - - PA7 35 - I2C1SDA CCP4 - - - - CCP3 - U1DCD - - PB0 66 - CCP0 - - - U1Rx - - - - - - PB1 67 - CCP2 - - CCP1 U1Tx - - - - - - PB2 72 - I2C0SCL - - CCP3 CCP0 - - - - - - PB3 65 - I2C0SDA - - - - - - - - - - PB4 92 C0- - - - U2Rx - - U1Rx EPI0S23 - - - PB5 91 C1- C0o CCP5 CCP6 CCP0 - CCP2 U1Tx EPI0S22 - - - PB6 90 VREFA C0+ CCP1 CCP7 C0o - - CCP5 - - - - - PB7 89 - - - - NMI - - - - - - - PC0 80 - - - TCK SWCLK - - - - - - - - PC1 79 - - - TMS SWDIO - - - - - - - - PC2 78 - - - TDI - - - - - - - - PC3 77 - - - TDO SWO - - - - - - - - PC4 25 - CCP5 - - - CCP2 CCP4 - EPI0S2 CCP1 - - PC5 24 C1+ CCP1 C1o C0o - CCP3 - - EPI0S3 - - - PC6 23 - CCP3 - - - U1Rx CCP0 - EPI0S4 - - - PC7 22 - CCP4 - - CCP0 U1Tx - C1o EPI0S5 - - - PD0 10 - - - - U2Rx U1Rx CCP6 - - U1CTS - - PD1 11 - - - - U2Tx U1Tx CCP7 - - U1DCD CCP2 - PD2 12 - U1Rx CCP6 - CCP5 - - - EPI0S20 - - - PD3 13 - U1Tx CCP7 - CCP0 - - - EPI0S21 - - - PD4 97 AIN7 CCP0 CCP3 - - - - - - U1RI EPI0S19 - PD5 98 AIN6 CCP2 CCP4 - - - - - - U2Rx EPI0S28 - PD6 99 AIN5 - - - - - - - - U2Tx EPI0S29 - PD7 100 AIN4 - C0o CCP1 - - - - - U1DTR EPI0S30 - PE0 74 - - SSI1Clk CCP3 - - - - EPI0S8 - - - PE1 75 - - SSI1Fss - CCP2 CCP6 - - EPI0S9 - - - PE2 95 - CCP4 SSI1Rx - - CCP2 - - EPI0S24 - - - PE3 96 - CCP1 SSI1Tx - - CCP7 - - EPI0S25 - - - PE4 6 AIN3 CCP3 - - - U2Tx CCP2 - - - - - 854 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-5. GPIO Pins and Alternate Functions (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PE5 5 AIN2 CCP5 - - - - - - - - - - PE6 2 AIN1 - C1o - - - - - - U1CTS - - PE7 1 AIN0 - - - - - - - - U1DCD - - PF0 47 - - - - - - - - - U1DSR - - PF1 61 - - - - - - - - - U1RTS CCP3 - PF2 60 - - - - - - - - - SSI1Clk - - PF3 59 - - - - - - - - - SSI1Fss - - PF4 58 - CCP0 C0o - - - - - EPI0S12 SSI1Rx - - PF5 46 - CCP2 C1o - - - - - EPI0S15 SSI1Tx - - PF6 43 - CCP1 - - - - - - - - U1RTS - PF7 42 - CCP4 - - - - - - EPI0S12 - - - PG0 19 - U2Rx - I2C1SCL - - - - EPI0S13 - - - PG1 18 - U2Tx - I2C1SDA - - - - EPI0S14 - - - PG2 17 - - - - - - - - - - - - PG3 16 - - - - - - - - - - - - PG4 41 - CCP3 - - - - - - EPI0S15 - U1RI - PG5 40 - CCP5 - - - - - - - - U1DTR - PG6 37 - - - - - - - - - - U1RI - PG7 36 - - - - - - - - CCP5 EPI0S31 - - PH0 86 - CCP6 - - - - - - EPI0S6 - - - PH1 85 - CCP7 - - - - - - EPI0S7 - - - PH2 84 - - C1o - - - - - EPI0S1 - - - PH3 83 - - - - - - - - EPI0S0 - - - PH4 76 - - - - - - - - EPI0S10 - - SSI1Clk PH5 63 - - - - - - - - EPI0S11 - - SSI1Fss PH6 62 - - - - - - - - EPI0S26 - - SSI1Rx PH7 15 - - - - - - - - EPI0S27 - - SSI1Tx PJ0 14 - - - - - - - - EPI0S16 - - I2C1SCL PJ1 87 - - - - - - - - EPI0S17 - - I2C1SDA PJ2 39 - - - - - - - - EPI0S18 CCP0 - - a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. July 24, 2011 855 Texas Instruments-Production Data Signal Tables Table 19-6. Possible Pin Assignments for Alternate Functions # of Possible Assignments one Alternate Function GPIO Function AIN0 PE7 AIN1 PE6 AIN2 PE5 AIN3 PE4 AIN4 PD7 AIN5 PD6 AIN6 PD5 AIN7 PD4 C0+ PB6 C0- PB4 C1+ PC5 C1- PB5 EPI0S0 PH3 EPI0S1 PH2 EPI0S10 PH4 EPI0S11 PH5 EPI0S13 PG0 EPI0S14 PG1 EPI0S16 PJ0 EPI0S17 PJ1 EPI0S18 PJ2 EPI0S19 PD4 EPI0S2 PC4 EPI0S20 PD2 EPI0S21 PD3 EPI0S22 PB5 EPI0S23 PB4 EPI0S24 PE2 EPI0S25 PE3 EPI0S26 PH6 EPI0S27 PH7 EPI0S28 PD5 EPI0S29 PD6 EPI0S3 PC5 EPI0S30 PD7 EPI0S31 PG7 EPI0S4 PC6 EPI0S5 PC7 EPI0S6 PH0 EPI0S7 PH1 EPI0S8 PE0 856 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-6. Possible Pin Assignments for Alternate Functions (continued) # of Possible Assignments Alternate Function GPIO Function EPI0S9 PE1 I2C0SCL PB2 I2C0SDA PB3 NMI PB7 SSI0Clk PA2 SSI0Fss PA3 SSI0Rx PA4 SSI0Tx PA5 SWCLK PC0 SWDIO PC1 SWO PC3 TCK PC0 TDI PC2 TDO PC3 TMS PC1 U0Rx PA0 U0Tx PA1 U1DSR PF0 VREFA PB6 EPI0S12 PF4 PF7 EPI0S15 PF5 PG4 U1DTR PD7 PG5 U1RTS PF1 PF6 SSI1Clk PE0 PF2 PH4 SSI1Fss PE1 PF3 PH5 SSI1Rx PE2 PF4 PH6 SSI1Tx PE3 PF5 PH7 U1CTS PA6 PD0 PE6 two three U1DCD PA7 PD1 PE7 U1RI PD4 PG4 PG6 I2C1SCL PA0 PA6 PG0 PJ0 I2C1SDA PA1 PA7 PG1 PJ1 U2Rx PB4 PD0 PD5 PG0 four U2Tx PD1 PD6 PE4 PG1 C0o PB5 PB6 PC5 PD7 PF4 C1o PC5 PC7 PE6 PF5 PH2 CCP6 PB5 PD0 PD2 PE1 PH0 CCP7 PB6 PD1 PD3 PE3 PH1 five six CCP4 PA7 PC4 PC7 PD5 PE2 PF7 U1Rx PA0 PB0 PB4 PC6 PD0 PD2 U1Tx PA1 PB1 PB5 PC7 PD1 PD3 July 24, 2011 857 Texas Instruments-Production Data Signal Tables Table 19-6. Possible Pin Assignments for Alternate Functions (continued) # of Possible Assignments Alternate Function seven CCP5 PB5 PB6 PC4 PD2 PE5 PG5 PG7 eight CCP1 PA6 PB1 PB6 PC4 PC5 PD7 PE3 PF6 nine 19.2 GPIO Function CCP0 PB0 PB2 PB5 PC6 PC7 PD3 PD4 PF4 PJ2 CCP2 PB1 PB5 PC4 PD1 PD5 PE1 PE2 PE4 PF5 CCP3 PA7 PB2 PC5 PC6 PD4 PE0 PE4 PF1 PG4 108-Ball BGA Package Pin Tables Table 19-7. Signals by Pin Number Pin Number Pin Type Buffer Type PE6 I/O TTL AIN1 I Analog A1 A4 GPIO port E bit 6. Analog-to-digital converter input 1. C1o O TTL Analog comparator 1 output. I TTL UART module 1 Clear To Send modem flow control input signal. GPIO port D bit 7. PD7 I/O TTL AIN4 I Analog C0o O TTL Analog comparator 0 output. Analog-to-digital converter input 4. CCP1 I/O TTL Capture/Compare/PWM 1. EPI0S30 I/O TTL EPI module 0 signal 30. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. GPIO port D bit 6. PD6 I/O TTL AIN5 I Analog EPI0S29 I/O TTL EPI module 0 signal 29. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PE2 I/O TTL GPIO port E bit 2. CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. EPI0S24 I/O TTL EPI module 0 signal 24. SSI module 1 receive. Analog-to-digital converter input 5. SSI1Rx I TTL GNDA - Power PB4 I/O TTL C0- I Analog EPI0S23 I/O TTL EPI module 0 signal 23. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. A5 A6 Description U1CTS A2 A3 a Pin Name The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GPIO port B bit 4. Analog comparator 0 negative input. 858 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-7. Signals by Pin Number (continued) Pin Number A7 Pin Type PB6 I/O TTL C0+ I Analog C0o O TTL Analog comparator 0 output. CCP1 I/O TTL Capture/Compare/PWM 1. CCP5 I/O TTL Capture/Compare/PWM 5. A10 B1 B2 B3 Description Capture/Compare/PWM 7. GPIO port B bit 6. Analog comparator 0 positive input. CCP7 I/O TTL I Analog PB7 I/O TTL GPIO port B bit 7. NMI I TTL Non-maskable interrupt. PC0 I/O TTL GPIO port C bit 0. SWCLK I TTL JTAG/SWD CLK. TCK I TTL JTAG/SWD CLK. PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. PB2 I/O TTL GPIO port B bit 2. CCP0 I/O TTL Capture/Compare/PWM 0. CCP3 I/O TTL Capture/Compare/PWM 3. I2C0SCL I/O OD I2C module 0 clock. PE1 I/O TTL GPIO port E bit 1. CCP2 I/O TTL Capture/Compare/PWM 2. A11 A12 Buffer Type VREFA A8 A9 a Pin Name This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 4095. The VREFA input is limited to the range specified in Table 21-26 on page 904. CCP6 I/O TTL Capture/Compare/PWM 6. EPI0S9 I/O TTL EPI module 0 signal 9. SSI1Fss I/O TTL SSI module 1 frame. PE7 I/O TTL GPIO port E bit 7. AIN0 I Analog U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. PE4 I/O TTL GPIO port E bit 4. AIN3 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. CCP3 I/O TTL Capture/Compare/PWM 3. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. GPIO port E bit 5. PE5 I/O TTL AIN2 I Analog CCP5 I/O TTL Analog-to-digital converter input 0. Analog-to-digital converter input 3. Analog-to-digital converter input 2. Capture/Compare/PWM 5. July 24, 2011 859 Texas Instruments-Production Data Signal Tables Table 19-7. Signals by Pin Number (continued) Pin Number B4 Pin Type Buffer Type B7 PE3 I/O TTL GPIO port E bit 3. I/O TTL Capture/Compare/PWM 1. CCP7 I/O TTL Capture/Compare/PWM 7. EPI0S25 I/O TTL EPI module 0 signal 25. SSI1Tx O TTL SSI module 1 transmit. GPIO port D bit 4. PD4 I/O TTL AIN7 I Analog CCP0 I/O TTL Capture/Compare/PWM 0. CCP3 I/O TTL Capture/Compare/PWM 3. EPI0S19 I/O TTL EPI module 0 signal 19. U1RI I TTL UART module 1 Ring Indicator modem status input signal. PJ1 I/O TTL GPIO port J bit 1. EPI0S17 I/O TTL EPI module 0 signal 17. I2C1SDA I/O OD I2C module 1 data. PB5 I/O TTL GPIO port B bit 5. C0o O TTL Analog comparator 0 output. B10 Analog-to-digital converter input 7. C1- I Analog CCP0 I/O TTL Capture/Compare/PWM 0. CCP2 I/O TTL Capture/Compare/PWM 2. CCP5 I/O TTL Capture/Compare/PWM 5. CCP6 I/O TTL Capture/Compare/PWM 6. EPI0S22 I/O TTL EPI module 0 signal 22. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI. PC1 I/O TTL GPIO port C bit 1. SWDIO I/O TTL JTAG TMS and SWDIO. TMS I TTL JTAG TMS and SWDIO. PH4 I/O TTL GPIO port H bit 4. EPI0S10 I/O TTL EPI module 0 signal 10. SSI1Clk I/O TTL SSI module 1 clock. PE0 I/O TTL GPIO port E bit 0. B8 B9 Description CCP1 B5 B6 a Pin Name Analog comparator 1 negative input. CCP3 I/O TTL Capture/Compare/PWM 3. EPI0S8 I/O TTL EPI module 0 signal 8. SSI1Clk I/O TTL SSI module 1 clock. B12 NC - - No connect. Leave the pin electrically unconnected/isolated. C1 NC - - No connect. Leave the pin electrically unconnected/isolated. No connect. Leave the pin electrically unconnected/isolated. B11 C2 C3 C4 NC - - VDDC - Power Positive supply for most of the logic function, including the processor core and most peripherals. GND - Power Ground reference for logic and I/O pins. 860 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-7. Signals by Pin Number (continued) Pin Number Pin Name C5 C6 a Pin Type Buffer Type GND - Power PD5 I/O TTL AIN6 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. EPI0S28 I/O TTL EPI module 0 signal 28. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. VDDA - Power PH1 I/O TTL GPIO port H bit 1. C7 C8 C9 C10 Description Ground reference for logic and I/O pins. GPIO port D bit 5. Analog-to-digital converter input 6. The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. CCP7 I/O TTL Capture/Compare/PWM 7. EPI0S7 I/O TTL EPI module 0 signal 7. PH0 I/O TTL GPIO port H bit 0. CCP6 I/O TTL Capture/Compare/PWM 6. EPI0S6 I/O TTL EPI module 0 signal 6. PG7 I/O TTL GPIO port G bit 7. CCP5 I/O TTL Capture/Compare/PWM 5. EPI0S31 I/O TTL EPI module 0 signal 31. C11 NC - - No connect. Leave the pin electrically unconnected/isolated. C12 NC - - No connect. Leave the pin electrically unconnected/isolated. D1 NC - - No connect. Leave the pin electrically unconnected/isolated. D2 NC - - No connect. Leave the pin electrically unconnected/isolated. VDDC - Power D3 Positive supply for most of the logic function, including the processor core and most peripherals. PH3 I/O TTL GPIO port H bit 3. EPI0S0 I/O TTL EPI module 0 signal 0. PH2 I/O TTL GPIO port H bit 2. D10 C1o O TTL Analog comparator 1 output. EPI0S1 I/O TTL EPI module 0 signal 1. PB1 I/O TTL GPIO port B bit 1. This pin is not 5-V tolerant. CCP1 I/O TTL Capture/Compare/PWM 1. CCP2 I/O TTL Capture/Compare/PWM 2. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. E1 NC - - No connect. Leave the pin electrically unconnected/isolated. E2 NC - - No connect. Leave the pin electrically unconnected/isolated. LDO - Power D11 D12 E3 Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). July 24, 2011 861 Texas Instruments-Production Data Signal Tables Table 19-7. Signals by Pin Number (continued) Pin Number Pin Name E10 Buffer Type VDD - Power PB3 I/O TTL GPIO port B bit 3. I2C0SDA I/O OD I2C module 0 data. E11 E12 F1 F2 a Pin Type Description Positive supply for I/O and some logic. PB0 I/O TTL GPIO port B bit 0. This pin is not 5-V tolerant. CCP0 I/O TTL Capture/Compare/PWM 0. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. NC - - No connect. Leave the pin electrically unconnected/isolated. No connect. Leave the pin electrically unconnected/isolated. NC - - PJ0 I/O TTL GPIO port J bit 0. EPI0S16 I/O TTL EPI module 0 signal 16. I2C1SCL I/O OD I2C module 1 clock. PH5 I/O TTL GPIO port H bit 5. EPI0S11 I/O TTL EPI module 0 signal 11. SSI1Fss I/O TTL SSI module 1 frame. F11 GND - Power Ground reference for logic and I/O pins. F12 GND - Power Ground reference for logic and I/O pins. PD0 I/O TTL GPIO port D bit 0. F3 F10 G1 G2 G3 CCP6 I/O TTL Capture/Compare/PWM 6. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. PD1 I/O TTL GPIO port D bit 1. CCP2 I/O TTL Capture/Compare/PWM 2. CCP7 I/O TTL Capture/Compare/PWM 7. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PH6 I/O TTL GPIO port H bit 6. EPI0S26 I/O TTL EPI module 0 signal 26. SSI module 1 receive. SSI1Rx I TTL G10 VDD - Power Positive supply for I/O and some logic. G11 VDD - Power Positive supply for I/O and some logic. G12 VDD - Power Positive supply for I/O and some logic. 862 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-7. Signals by Pin Number (continued) Pin Number H1 H2 a Pin Name Pin Type Buffer Type Description PD3 I/O TTL GPIO port D bit 3. CCP0 I/O TTL Capture/Compare/PWM 0. CCP7 I/O TTL Capture/Compare/PWM 7. EPI0S21 I/O TTL EPI module 0 signal 21. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PD2 I/O TTL GPIO port D bit 2. CCP5 I/O TTL Capture/Compare/PWM 5. CCP6 I/O TTL Capture/Compare/PWM 6. EPI0S20 I/O TTL EPI module 0 signal 20. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. PH7 I/O TTL GPIO port H bit 7. EPI0S27 I/O TTL EPI module 0 signal 27. SSI1Tx O TTL SSI module 1 transmit. H10 VDD - Power H11 RST I TTL System reset input. PF1 I/O TTL GPIO port F bit 1. H12 CCP3 I/O TTL Capture/Compare/PWM 3. U1RTS O TTL UART module 1 Request to Send modem flow control output line. J1 PG2 I/O TTL GPIO port G bit 2. J2 PG3 I/O TTL GPIO port G bit 3. J3 GND - Power Ground reference for logic and I/O pins. J10 GND - Power Ground reference for logic and I/O pins. PF2 I/O TTL GPIO port F bit 2. SSI1Clk I/O TTL SSI module 1 clock. PF3 I/O TTL GPIO port F bit 3. SSI1Fss I/O TTL SSI module 1 frame. PG0 I/O TTL GPIO port G bit 0. EPI0S13 I/O TTL EPI module 0 signal 13. I2C1SCL I/O OD I2C module 1 clock. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. PG1 I/O TTL GPIO port G bit 1. EPI0S14 I/O TTL EPI module 0 signal 14. I2C1SDA I/O OD I2C module 1 data. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PG4 I/O TTL GPIO port G bit 4. CCP3 I/O TTL Capture/Compare/PWM 3. EPI0S15 I/O TTL EPI module 0 signal 15. U1RI I TTL UART module 1 Ring Indicator modem status input signal. H3 J11 J12 K1 K2 K3 Positive supply for I/O and some logic. July 24, 2011 863 Texas Instruments-Production Data Signal Tables Table 19-7. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type PF7 I/O TTL GPIO port F bit 7. K4 CCP4 I/O TTL Capture/Compare/PWM 4. EPI0S12 I/O TTL EPI module 0 signal 12. GND - Power PJ2 I/O TTL GPIO port J bit 2. K5 Description Ground reference for logic and I/O pins. CCP0 I/O TTL Capture/Compare/PWM 0. EPI0S18 I/O TTL EPI module 0 signal 18. K7 VDD - Power Positive supply for I/O and some logic. K8 VDD - Power Positive supply for I/O and some logic. K9 VDD - Power Positive supply for I/O and some logic. K6 K10 GND - Power Ground reference for logic and I/O pins. XOSC0 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a 4.194304-MHz crystal or a 32.768-kHz oscillator for the Hibernation module RTC. See the CLKSEL bit in the HIBCTL register. XOSC1 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. K11 K12 PC4 I/O TTL GPIO port C bit 4. CCP1 I/O TTL Capture/Compare/PWM 1. CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. CCP5 I/O TTL Capture/Compare/PWM 5. EPI0S2 I/O TTL EPI module 0 signal 2. PC7 I/O TTL GPIO port C bit 7. L1 L2 L3 C1o O TTL Analog comparator 1 output. CCP0 I/O TTL Capture/Compare/PWM 0. CCP4 I/O TTL Capture/Compare/PWM 4. EPI0S5 I/O TTL EPI module 0 signal 5. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PA0 I/O TTL GPIO port A bit 0. I2C1SCL I/O OD I2C module 1 clock. U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. PA3 I/O TTL GPIO port A bit 3. SSI0Fss I/O TTL SSI module 0 frame. PA4 I/O TTL GPIO port A bit 4. SSI0Rx I TTL SSI module 0 receive. L4 L5 864 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-7. Signals by Pin Number (continued) Pin Number Pin Type Buffer Type Description PA6 I/O TTL GPIO port A bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. I2C1SCL I/O OD I2C module 1 clock. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. PG6 I/O TTL GPIO port G bit 6. U1RI I TTL UART module 1 Ring Indicator modem status input signal. PF5 I/O TTL GPIO port F bit 5. C1o O TTL Analog comparator 1 output. L6 L7 L8 a Pin Name CCP2 I/O TTL Capture/Compare/PWM 2. EPI0S15 I/O TTL EPI module 0 signal 15. SSI1Tx O TTL SSI module 1 transmit. PF4 I/O TTL GPIO port F bit 4. C0o O TTL Analog comparator 0 output. CCP0 I/O TTL Capture/Compare/PWM 0. EPI0S12 I/O TTL EPI module 0 signal 12. SSI1Rx I TTL SSI module 1 receive. L10 GND - Power Ground reference for logic and I/O pins. L11 OSC0 I Analog Main oscillator crystal input or an external clock reference input. VBAT - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. PC5 I/O TTL GPIO port C bit 5. C0o O TTL Analog comparator 0 output. C1+ I Analog C1o O TTL Analog comparator 1 output. CCP1 I/O TTL Capture/Compare/PWM 1. CCP3 I/O TTL Capture/Compare/PWM 3. EPI0S3 I/O TTL EPI module 0 signal 3. L9 L12 M1 M2 M3 Analog comparator 1 positive input. PC6 I/O TTL GPIO port C bit 6. CCP0 I/O TTL Capture/Compare/PWM 0. CCP3 I/O TTL Capture/Compare/PWM 3. EPI0S4 I/O TTL EPI module 0 signal 4. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. PA1 I/O TTL GPIO port A bit 1. I2C1SDA I/O OD I2C module 1 data. U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PA2 I/O TTL GPIO port A bit 2. SSI0Clk I/O TTL SSI module 0 clock. M4 July 24, 2011 865 Texas Instruments-Production Data Signal Tables Table 19-7. Signals by Pin Number (continued) Pin Number Pin Type Buffer Type M7 M8 PA5 I/O TTL GPIO port A bit 5. O TTL SSI module 0 transmit. PA7 I/O TTL GPIO port A bit 7. CCP3 I/O TTL Capture/Compare/PWM 3. CCP4 I/O TTL Capture/Compare/PWM 4. I2C1SDA I/O OD I2C module 1 data. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. PG5 I/O TTL GPIO port G bit 5. CCP5 I/O TTL Capture/Compare/PWM 5. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. PF6 I/O TTL GPIO port F bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. U1RTS O TTL UART module 1 Request to Send modem flow control output line. PF0 I/O TTL GPIO port F bit 0. U1DSR I TTL UART module 1 Data Set Ready modem output control line. WAKE I TTL An external input that brings the processor out of Hibernate mode when asserted. OSC1 O Analog HIB O OD M9 M10 M11 M12 Description SSI0Tx M5 M6 a Pin Name Main oscillator crystal output. Leave unconnected when using a single-ended clock source. An output that indicates the processor is in Hibernate mode. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 19-8. Signals by Signal Name Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description AIN0 B1 PE7 I Analog Analog-to-digital converter input 0. AIN1 A1 PE6 I Analog Analog-to-digital converter input 1. AIN2 B3 PE5 I Analog Analog-to-digital converter input 2. AIN3 B2 PE4 I Analog Analog-to-digital converter input 3. AIN4 A2 PD7 I Analog Analog-to-digital converter input 4. AIN5 A3 PD6 I Analog Analog-to-digital converter input 5. AIN6 C6 PD5 I Analog Analog-to-digital converter input 6. AIN7 B5 PD4 I Analog Analog-to-digital converter input 7. C0+ A7 PB6 I Analog Analog comparator 0 positive input. Analog comparator 0 negative input. C0- A6 PB4 I Analog C0o M1 L9 A7 B7 A2 PC5 (3) PF4 (2) PB6 (3) PB5 (1) PD7 (2) O TTL C1+ M1 PC5 I Analog Analog comparator 1 positive input. C1- B7 PB5 I Analog Analog comparator 1 negative input. Analog comparator 0 output. 866 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description C1o A1 L2 M1 L8 D11 PE6 (2) PC7 (7) PC5 (2) PF5 (2) PH2 (2) O TTL Analog comparator 1 output. CCP0 H1 L2 M2 K6 L9 E12 A11 B7 B5 PD3 (4) PC7 (4) PC6 (6) PJ2 (9) PF4 (1) PB0 (1) PB2 (5) PB5 (4) PD4 (1) I/O TTL Capture/Compare/PWM 0. CCP1 M1 L1 L6 M8 D12 A7 B4 A2 PC5 (1) PC4 (9) PA6 (2) PF6 (1) PB1 (4) PB6 (1) PE3 (1) PD7 (3) I/O TTL Capture/Compare/PWM 1. CCP2 B2 G2 L1 L8 D12 A12 B7 A4 C6 PE4 (6) PD1 (10) PC4 (5) PF5 (1) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) I/O TTL Capture/Compare/PWM 2. CCP3 B2 M2 M1 M6 K3 H12 A11 B11 B5 PE4 (1) PC6 (1) PC5 (5) PA7 (7) PG4 (1) PF1 (10) PB2 (4) PE0 (3) PD4 (2) I/O TTL Capture/Compare/PWM 3. CCP4 L2 L1 M6 K4 A4 C6 PC7 (1) PC4 (6) PA7 (2) PF7 (1) PE2 (1) PD5 (2) I/O TTL Capture/Compare/PWM 4. CCP5 B3 H2 L1 C10 M7 A7 B7 PE5 (1) PD2 (4) PC4 (1) PG7 (8) PG5 (1) PB6 (6) PB5 (2) I/O TTL Capture/Compare/PWM 5. July 24, 2011 867 Texas Instruments-Production Data Signal Tables Table 19-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP6 G1 H2 A12 C9 B7 PD0 (6) PD2 (2) PE1 (5) PH0 (1) PB5 (3) I/O TTL Capture/Compare/PWM 6. CCP7 G2 H1 C8 A7 B4 PD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) I/O TTL Capture/Compare/PWM 7. EPI0S0 D10 PH3 (8) I/O TTL EPI module 0 signal 0. EPI0S1 D11 PH2 (8) I/O TTL EPI module 0 signal 1. EPI0S2 L1 PC4 (8) I/O TTL EPI module 0 signal 2. EPI0S3 M1 PC5 (8) I/O TTL EPI module 0 signal 3. EPI0S4 M2 PC6 (8) I/O TTL EPI module 0 signal 4. EPI0S5 L2 PC7 (8) I/O TTL EPI module 0 signal 5. EPI0S6 C9 PH0 (8) I/O TTL EPI module 0 signal 6. EPI0S7 C8 PH1 (8) I/O TTL EPI module 0 signal 7. EPI0S8 B11 PE0 (8) I/O TTL EPI module 0 signal 8. EPI0S9 A12 PE1 (8) I/O TTL EPI module 0 signal 9. EPI0S10 B10 PH4 (8) I/O TTL EPI module 0 signal 10. EPI0S11 F10 PH5 (8) I/O TTL EPI module 0 signal 11. EPI0S12 K4 L9 PF7 (8) PF4 (8) I/O TTL EPI module 0 signal 12. EPI0S13 K1 PG0 (8) I/O TTL EPI module 0 signal 13. EPI0S14 K2 PG1 (8) I/O TTL EPI module 0 signal 14. EPI0S15 K3 L8 PG4 (8) PF5 (8) I/O TTL EPI module 0 signal 15. EPI0S16 F3 PJ0 (8) I/O TTL EPI module 0 signal 16. EPI0S17 B6 PJ1 (8) I/O TTL EPI module 0 signal 17. EPI0S18 K6 PJ2 (8) I/O TTL EPI module 0 signal 18. EPI0S19 B5 PD4 (10) I/O TTL EPI module 0 signal 19. EPI0S20 H2 PD2 (8) I/O TTL EPI module 0 signal 20. EPI0S21 H1 PD3 (8) I/O TTL EPI module 0 signal 21. EPI0S22 B7 PB5 (8) I/O TTL EPI module 0 signal 22. EPI0S23 A6 PB4 (8) I/O TTL EPI module 0 signal 23. EPI0S24 A4 PE2 (8) I/O TTL EPI module 0 signal 24. EPI0S25 B4 PE3 (8) I/O TTL EPI module 0 signal 25. EPI0S26 G3 PH6 (8) I/O TTL EPI module 0 signal 26. EPI0S27 H3 PH7 (8) I/O TTL EPI module 0 signal 27. EPI0S28 C6 PD5 (10) I/O TTL EPI module 0 signal 28. EPI0S29 A3 PD6 (10) I/O TTL EPI module 0 signal 29. EPI0S30 A2 PD7 (10) I/O TTL EPI module 0 signal 30. EPI0S31 C10 PG7 (9) I/O TTL EPI module 0 signal 31. 868 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description GND C4 C5 J3 K5 L10 K10 J10 F11 F12 fixed - Power Ground reference for logic and I/O pins. GNDA A5 fixed - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. HIB M12 fixed O OD An output that indicates the processor is in Hibernate mode. I2C0SCL A11 PB2 (1) I/O OD I2C module 0 clock. I2C0SDA E11 PB3 (1) I/O OD I2C module 0 data. I2C1SCL F3 K1 L3 L6 PJ0 (11) PG0 (3) PA0 (8) PA6 (1) I/O OD I2C module 1 clock. I2C1SDA K2 M3 M6 B6 PG1 (3) PA1 (8) PA7 (1) PJ1 (11) I/O OD I2C module 1 data. LDO E3 fixed - Power NC C11 C12 B12 C1 C2 D2 D1 E1 E2 F1 F2 fixed - - NMI A8 PB7 (4) I TTL OSC0 L11 fixed I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). No connect. Leave the pin electrically unconnected/isolated. Non-maskable interrupt. PA0 L3 - I/O TTL GPIO port A bit 0. PA1 M3 - I/O TTL GPIO port A bit 1. PA2 M4 - I/O TTL GPIO port A bit 2. PA3 L4 - I/O TTL GPIO port A bit 3. July 24, 2011 869 Texas Instruments-Production Data Signal Tables Table 19-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment PA4 L5 - a Pin Type Buffer Type I/O TTL Description GPIO port A bit 4. PA5 M5 - I/O TTL GPIO port A bit 5. PA6 L6 - I/O TTL GPIO port A bit 6. PA7 M6 - I/O TTL GPIO port A bit 7. PB0 E12 - I/O TTL GPIO port B bit 0. This pin is not 5-V tolerant. PB1 D12 - I/O TTL GPIO port B bit 1. This pin is not 5-V tolerant. PB2 A11 - I/O TTL GPIO port B bit 2. PB3 E11 - I/O TTL GPIO port B bit 3. PB4 A6 - I/O TTL GPIO port B bit 4. PB5 B7 - I/O TTL GPIO port B bit 5. PB6 A7 - I/O TTL GPIO port B bit 6. PB7 A8 - I/O TTL GPIO port B bit 7. PC0 A9 - I/O TTL GPIO port C bit 0. PC1 B9 - I/O TTL GPIO port C bit 1. PC2 B8 - I/O TTL GPIO port C bit 2. PC3 A10 - I/O TTL GPIO port C bit 3. PC4 L1 - I/O TTL GPIO port C bit 4. PC5 M1 - I/O TTL GPIO port C bit 5. PC6 M2 - I/O TTL GPIO port C bit 6. PC7 L2 - I/O TTL GPIO port C bit 7. PD0 G1 - I/O TTL GPIO port D bit 0. PD1 G2 - I/O TTL GPIO port D bit 1. PD2 H2 - I/O TTL GPIO port D bit 2. PD3 H1 - I/O TTL GPIO port D bit 3. PD4 B5 - I/O TTL GPIO port D bit 4. PD5 C6 - I/O TTL GPIO port D bit 5. PD6 A3 - I/O TTL GPIO port D bit 6. PD7 A2 - I/O TTL GPIO port D bit 7. PE0 B11 - I/O TTL GPIO port E bit 0. PE1 A12 - I/O TTL GPIO port E bit 1. PE2 A4 - I/O TTL GPIO port E bit 2. PE3 B4 - I/O TTL GPIO port E bit 3. PE4 B2 - I/O TTL GPIO port E bit 4. PE5 B3 - I/O TTL GPIO port E bit 5. PE6 A1 - I/O TTL GPIO port E bit 6. PE7 B1 - I/O TTL GPIO port E bit 7. PF0 M9 - I/O TTL GPIO port F bit 0. PF1 H12 - I/O TTL GPIO port F bit 1. PF2 J11 - I/O TTL GPIO port F bit 2. PF3 J12 - I/O TTL GPIO port F bit 3. PF4 L9 - I/O TTL GPIO port F bit 4. 870 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment PF5 L8 - a Pin Type Buffer Type I/O TTL Description GPIO port F bit 5. PF6 M8 - I/O TTL GPIO port F bit 6. PF7 K4 - I/O TTL GPIO port F bit 7. PG0 K1 - I/O TTL GPIO port G bit 0. PG1 K2 - I/O TTL GPIO port G bit 1. PG2 J1 - I/O TTL GPIO port G bit 2. PG3 J2 - I/O TTL GPIO port G bit 3. PG4 K3 - I/O TTL GPIO port G bit 4. PG5 M7 - I/O TTL GPIO port G bit 5. PG6 L7 - I/O TTL GPIO port G bit 6. PG7 C10 - I/O TTL GPIO port G bit 7. PH0 C9 - I/O TTL GPIO port H bit 0. PH1 C8 - I/O TTL GPIO port H bit 1. PH2 D11 - I/O TTL GPIO port H bit 2. PH3 D10 - I/O TTL GPIO port H bit 3. PH4 B10 - I/O TTL GPIO port H bit 4. PH5 F10 - I/O TTL GPIO port H bit 5. PH6 G3 - I/O TTL GPIO port H bit 6. PH7 H3 - I/O TTL GPIO port H bit 7. PJ0 F3 - I/O TTL GPIO port J bit 0. PJ1 B6 - I/O TTL GPIO port J bit 1. PJ2 K6 - I/O TTL GPIO port J bit 2. RST H11 fixed I TTL System reset input. SSI0Clk M4 PA2 (1) I/O TTL SSI module 0 clock. SSI0Fss L4 PA3 (1) I/O TTL SSI module 0 frame. SSI0Rx L5 PA4 (1) I TTL SSI module 0 receive. SSI0Tx M5 PA5 (1) O TTL SSI module 0 transmit. SSI1Clk J11 B11 B10 PF2 (9) PE0 (2) PH4 (11) I/O TTL SSI module 1 clock. SSI1Fss J12 F10 A12 PF3 (9) PH5 (11) PE1 (2) I/O TTL SSI module 1 frame. SSI1Rx L9 G3 A4 PF4 (9) PH6 (11) PE2 (2) I TTL SSI module 1 receive. SSI1Tx H3 L8 B4 PH7 (11) PF5 (9) PE3 (2) O TTL SSI module 1 transmit. SWCLK A9 PC0 (3) I TTL JTAG/SWD CLK. SWDIO B9 PC1 (3) I/O TTL JTAG TMS and SWDIO. SWO A10 PC3 (3) O TTL JTAG TDO and SWO. TCK A9 PC0 (3) I TTL JTAG/SWD CLK. July 24, 2011 871 Texas Instruments-Production Data Signal Tables Table 19-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description TDI B8 PC2 (3) I TTL JTAG TDI. TDO A10 PC3 (3) O TTL JTAG TDO and SWO. TMS B9 PC1 (3) I TTL JTAG TMS and SWDIO. U0Rx L3 PA0 (1) I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 PA1 (1) O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS A1 G1 L6 PE6 (9) PD0 (9) PA6 (9) I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD B1 G2 M6 PE7 (9) PD1 (9) PA7 (9) I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR M9 PF0 (9) I TTL UART module 1 Data Set Ready modem output control line. U1DTR M7 A2 PG5 (10) PD7 (9) O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI L7 K3 B5 PG6 (10) PG4 (10) PD4 (9) I TTL UART module 1 Ring Indicator modem status input signal. U1RTS M8 H12 PF6 (10) PF1 (9) O TTL UART module 1 Request to Send modem flow control output line. U1Rx G1 H2 M2 L3 E12 A6 PD0 (5) PD2 (1) PC6 (5) PA0 (9) PB0 (5) PB4 (7) I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx G2 H1 L2 M3 D12 B7 PD1 (5) PD3 (1) PC7 (5) PA1 (9) PB1 (5) PB5 (7) O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx G1 K1 A6 C6 PD0 (4) PG0 (1) PB4 (4) PD5 (9) I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx B2 G2 K2 A3 PE4 (5) PD1 (4) PG1 (1) PD6 (9) O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. VBAT L12 fixed - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. 872 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description VDD K7 G12 K8 K9 H10 G10 E10 G11 fixed - Power Positive supply for I/O and some logic. VDDA C7 fixed - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. VDDC D3 C3 fixed - Power Positive supply for most of the logic function, including the processor core and most peripherals. VREFA A7 PB6 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 4095. The VREFA input is limited to the range specified in Table 21-26 on page 904. WAKE M10 fixed I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 K11 fixed I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a 4.194304-MHz crystal or a 32.768-kHz oscillator for the Hibernation module RTC. See the CLKSEL bit in the HIBCTL register. XOSC1 K12 fixed O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 24, 2011 873 Texas Instruments-Production Data Signal Tables Table 19-9. Signals by Function, Except for GPIO Function ADC Pin Name a Pin Number Pin Type Buffer Type AIN0 B1 I Analog Analog-to-digital converter input 0. AIN1 A1 I Analog Analog-to-digital converter input 1. AIN2 B3 I Analog Analog-to-digital converter input 2. AIN3 B2 I Analog Analog-to-digital converter input 3. AIN4 A2 I Analog Analog-to-digital converter input 4. AIN5 A3 I Analog Analog-to-digital converter input 5. AIN6 C6 I Analog Analog-to-digital converter input 6. AIN7 B5 I Analog Analog-to-digital converter input 7. VREFA A7 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 4095. The VREFA input is limited to the range specified in Table 21-26 on page 904. C0+ A7 I Analog Analog comparator 0 positive input. C0- A6 I Analog Analog comparator 0 negative input. C0o M1 L9 A7 B7 A2 O TTL C1+ M1 I Analog Analog comparator 1 positive input. C1- B7 I Analog Analog comparator 1 negative input. C1o A1 L2 M1 L8 D11 O TTL Analog Comparators Description Analog comparator 0 output. Analog comparator 1 output. 874 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-9. Signals by Function, Except for GPIO (continued) Function External Peripheral Interface Pin Name a Pin Number Pin Type Buffer Type Description EPI0S0 D10 I/O TTL EPI module 0 signal 0. EPI0S1 D11 I/O TTL EPI module 0 signal 1. EPI0S2 L1 I/O TTL EPI module 0 signal 2. EPI0S3 M1 I/O TTL EPI module 0 signal 3. EPI0S4 M2 I/O TTL EPI module 0 signal 4. EPI0S5 L2 I/O TTL EPI module 0 signal 5. EPI0S6 C9 I/O TTL EPI module 0 signal 6. EPI0S7 C8 I/O TTL EPI module 0 signal 7. EPI0S8 B11 I/O TTL EPI module 0 signal 8. EPI0S9 A12 I/O TTL EPI module 0 signal 9. EPI0S10 B10 I/O TTL EPI module 0 signal 10. EPI0S11 F10 I/O TTL EPI module 0 signal 11. EPI0S12 K4 L9 I/O TTL EPI module 0 signal 12. EPI0S13 K1 I/O TTL EPI module 0 signal 13. EPI0S14 K2 I/O TTL EPI module 0 signal 14. EPI0S15 K3 L8 I/O TTL EPI module 0 signal 15. EPI0S16 F3 I/O TTL EPI module 0 signal 16. EPI0S17 B6 I/O TTL EPI module 0 signal 17. EPI0S18 K6 I/O TTL EPI module 0 signal 18. EPI0S19 B5 I/O TTL EPI module 0 signal 19. EPI0S20 H2 I/O TTL EPI module 0 signal 20. EPI0S21 H1 I/O TTL EPI module 0 signal 21. EPI0S22 B7 I/O TTL EPI module 0 signal 22. EPI0S23 A6 I/O TTL EPI module 0 signal 23. EPI0S24 A4 I/O TTL EPI module 0 signal 24. EPI0S25 B4 I/O TTL EPI module 0 signal 25. EPI0S26 G3 I/O TTL EPI module 0 signal 26. EPI0S27 H3 I/O TTL EPI module 0 signal 27. EPI0S28 C6 I/O TTL EPI module 0 signal 28. EPI0S29 A3 I/O TTL EPI module 0 signal 29. EPI0S30 A2 I/O TTL EPI module 0 signal 30. EPI0S31 C10 I/O TTL EPI module 0 signal 31. July 24, 2011 875 Texas Instruments-Production Data Signal Tables Table 19-9. Signals by Function, Except for GPIO (continued) Function General-Purpose Timers Pin Name a Pin Number Pin Type Buffer Type CCP0 H1 L2 M2 K6 L9 E12 A11 B7 B5 I/O TTL Capture/Compare/PWM 0. CCP1 M1 L1 L6 M8 D12 A7 B4 A2 I/O TTL Capture/Compare/PWM 1. CCP2 B2 G2 L1 L8 D12 A12 B7 A4 C6 I/O TTL Capture/Compare/PWM 2. CCP3 B2 M2 M1 M6 K3 H12 A11 B11 B5 I/O TTL Capture/Compare/PWM 3. CCP4 L2 L1 M6 K4 A4 C6 I/O TTL Capture/Compare/PWM 4. CCP5 B3 H2 L1 C10 M7 A7 B7 I/O TTL Capture/Compare/PWM 5. CCP6 G1 H2 A12 C9 B7 I/O TTL Capture/Compare/PWM 6. I/O TTL Capture/Compare/PWM 7. CCP7 Description 876 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-9. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Number a Pin Type Buffer Type Description G2 H1 C8 A7 B4 HIB M12 O OD VBAT L12 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE M10 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 K11 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a 4.194304-MHz crystal or a 32.768-kHz oscillator for the Hibernation module RTC. See the CLKSEL bit in the HIBCTL register. XOSC1 K12 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. I2C0SCL A11 I/O OD I2C module 0 clock. I2C0SDA E11 I/O OD I2C module 0 data. I2C1SCL F3 K1 L3 L6 I/O OD I2C module 1 clock. I2C1SDA K2 M3 M6 B6 I/O OD I2C module 1 data. SWCLK A9 I TTL JTAG/SWD CLK. SWDIO B9 I/O TTL JTAG TMS and SWDIO. SWO A10 O TTL JTAG TDO and SWO. TCK A9 I TTL JTAG/SWD CLK. Hibernate I2C JTAG/SWD/SWO An output that indicates the processor is in Hibernate mode. TDI B8 I TTL JTAG TDI. TDO A10 O TTL JTAG TDO and SWO. TMS B9 I TTL JTAG TMS and SWDIO. July 24, 2011 877 Texas Instruments-Production Data Signal Tables Table 19-9. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type GND C4 C5 J3 K5 L10 K10 J10 F11 F12 - Power Ground reference for logic and I/O pins. GNDA A5 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. LDO E3 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). VDD K7 G12 K8 K9 H10 G10 E10 G11 - Power Positive supply for I/O and some logic. VDDA C7 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. VDDC D3 C3 - Power Positive supply for most of the logic function, including the processor core and most peripherals. SSI0Clk M4 I/O TTL SSI module 0 clock. SSI0Fss L4 I/O TTL SSI module 0 frame. SSI0Rx L5 I TTL SSI module 0 receive. Power SSI Description SSI0Tx M5 O TTL SSI module 0 transmit. SSI1Clk J11 B11 B10 I/O TTL SSI module 1 clock. SSI1Fss J12 F10 A12 I/O TTL SSI module 1 frame. SSI1Rx L9 G3 A4 I TTL SSI module 1 receive. SSI1Tx H3 L8 B4 O TTL SSI module 1 transmit. 878 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-9. Signals by Function, Except for GPIO (continued) Function System Control & Clocks Pin Name a Pin Number Pin Type Buffer Type Description NMI A8 I TTL OSC0 L11 I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST Non-maskable interrupt. H11 I TTL System reset input. U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS A1 G1 L6 I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD B1 G2 M6 I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR M9 I TTL UART module 1 Data Set Ready modem output control line. U1DTR M7 A2 O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI L7 K3 B5 I TTL UART module 1 Ring Indicator modem status input signal. U1RTS M8 H12 O TTL UART module 1 Request to Send modem flow control output line. U1Rx G1 H2 M2 L3 E12 A6 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx G2 H1 L2 M3 D12 B7 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx G1 K1 A6 C6 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx B2 G2 K2 A3 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. UART a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 24, 2011 879 Texas Instruments-Production Data Signal Tables Table 19-10. GPIO Pins and Alternate Functions a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PA0 L3 - U0Rx - - - - - - I2C1SCL U1Rx - - PA1 M3 - U0Tx - - - - - - I2C1SDA U1Tx - - PA2 M4 - SSI0Clk - - - - - - - - - - PA3 L4 - SSI0Fss - - - - - - - - - - PA4 L5 - SSI0Rx - - - - - - - - - - PA5 M5 - SSI0Tx - - - - - - - - - - PA6 L6 - I2C1SCL CCP1 - - - - - - U1CTS - - PA7 M6 - I2C1SDA CCP4 - - - - CCP3 - U1DCD - - PB0 E12 - CCP0 - - - U1Rx - - - - - - PB1 D12 - CCP2 - - CCP1 U1Tx - - - - - - PB2 A11 - I2C0SCL - - CCP3 CCP0 - - - - - - PB3 E11 - I2C0SDA - - - - - - - - - - PB4 A6 C0- - - - U2Rx - - U1Rx EPI0S23 - - - PB5 B7 C1- C0o CCP5 CCP6 CCP0 - CCP2 U1Tx EPI0S22 - - - PB6 A7 VREFA C0+ CCP1 CCP7 C0o - - CCP5 - - - - - PB7 A8 - - - - NMI - - - - - - - PC0 A9 - - - TCK SWCLK - - - - - - - - PC1 B9 - - - TMS SWDIO - - - - - - - - PC2 B8 - - - TDI - - - - - - - - PC3 A10 - - - TDO SWO - - - - - - - - PC4 L1 - CCP5 - - - CCP2 CCP4 - EPI0S2 CCP1 - - PC5 M1 C1+ CCP1 C1o C0o - CCP3 - - EPI0S3 - - - PC6 M2 - CCP3 - - - U1Rx CCP0 - EPI0S4 - - - PC7 L2 - CCP4 - - CCP0 U1Tx - C1o EPI0S5 - - - PD0 G1 - - - - U2Rx U1Rx CCP6 - - U1CTS - - PD1 G2 - - - - U2Tx U1Tx CCP7 - - U1DCD CCP2 - PD2 H2 - U1Rx CCP6 - CCP5 - - - EPI0S20 - - - PD3 H1 - U1Tx CCP7 - CCP0 - - - EPI0S21 - - - PD4 B5 AIN7 CCP0 CCP3 - - - - - - U1RI EPI0S19 - PD5 C6 AIN6 CCP2 CCP4 - - - - - - U2Rx EPI0S28 - PD6 A3 AIN5 - - - - - - - - U2Tx EPI0S29 - PD7 A2 AIN4 - C0o CCP1 - - - - - U1DTR EPI0S30 - PE0 B11 - - SSI1Clk CCP3 - - - - EPI0S8 - - - PE1 A12 - - SSI1Fss - CCP2 CCP6 - - EPI0S9 - - - PE2 A4 - CCP4 SSI1Rx - - CCP2 - - EPI0S24 - - - PE3 B4 - CCP1 SSI1Tx - - CCP7 - - EPI0S25 - - - PE4 B2 AIN3 CCP3 - - - U2Tx CCP2 - - - - - 880 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-10. GPIO Pins and Alternate Functions (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PE5 B3 AIN2 CCP5 - - - - - - - - - - PE6 A1 AIN1 - C1o - - - - - - U1CTS - - PE7 B1 AIN0 - - - - - - - - U1DCD - - PF0 M9 - - - - - - - - - U1DSR - - PF1 H12 - - - - - - - - - U1RTS CCP3 - PF2 J11 - - - - - - - - - SSI1Clk - - PF3 J12 - - - - - - - - - SSI1Fss - - PF4 L9 - CCP0 C0o - - - - - EPI0S12 SSI1Rx - - PF5 L8 - CCP2 C1o - - - - - EPI0S15 SSI1Tx - - PF6 M8 - CCP1 - - - - - - - - U1RTS - PF7 K4 - CCP4 - - - - - - EPI0S12 - - - PG0 K1 - U2Rx - I2C1SCL - - - - EPI0S13 - - - PG1 K2 - U2Tx - I2C1SDA - - - - EPI0S14 - - - PG2 J1 - - - - - - - - - - - - PG3 J2 - - - - - - - - - - - - PG4 K3 - CCP3 - - - - - - EPI0S15 - U1RI - PG5 M7 - CCP5 - - - - - - - - U1DTR - PG6 L7 - - - - - - - - - - U1RI - PG7 C10 - - - - - - - - CCP5 EPI0S31 - - PH0 C9 - CCP6 - - - - - - EPI0S6 - - - PH1 C8 - CCP7 - - - - - - EPI0S7 - - - PH2 D11 - - C1o - - - - - EPI0S1 - - - PH3 D10 - - - - - - - - EPI0S0 - - - PH4 B10 - - - - - - - - EPI0S10 - - SSI1Clk PH5 F10 - - - - - - - - EPI0S11 - - SSI1Fss PH6 G3 - - - - - - - - EPI0S26 - - SSI1Rx PH7 H3 - - - - - - - - EPI0S27 - - SSI1Tx PJ0 F3 - - - - - - - - EPI0S16 - - I2C1SCL PJ1 B6 - - - - - - - - EPI0S17 - - I2C1SDA PJ2 K6 - - - - - - - - EPI0S18 CCP0 - - a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. July 24, 2011 881 Texas Instruments-Production Data Signal Tables Table 19-11. Possible Pin Assignments for Alternate Functions # of Possible Assignments one Alternate Function GPIO Function AIN0 PE7 AIN1 PE6 AIN2 PE5 AIN3 PE4 AIN4 PD7 AIN5 PD6 AIN6 PD5 AIN7 PD4 C0+ PB6 C0- PB4 C1+ PC5 C1- PB5 EPI0S0 PH3 EPI0S1 PH2 EPI0S10 PH4 EPI0S11 PH5 EPI0S13 PG0 EPI0S14 PG1 EPI0S16 PJ0 EPI0S17 PJ1 EPI0S18 PJ2 EPI0S19 PD4 EPI0S2 PC4 EPI0S20 PD2 EPI0S21 PD3 EPI0S22 PB5 EPI0S23 PB4 EPI0S24 PE2 EPI0S25 PE3 EPI0S26 PH6 EPI0S27 PH7 EPI0S28 PD5 EPI0S29 PD6 EPI0S3 PC5 EPI0S30 PD7 EPI0S31 PG7 EPI0S4 PC6 EPI0S5 PC7 EPI0S6 PH0 EPI0S7 PH1 EPI0S8 PE0 882 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-11. Possible Pin Assignments for Alternate Functions (continued) # of Possible Assignments Alternate Function GPIO Function EPI0S9 PE1 I2C0SCL PB2 I2C0SDA PB3 NMI PB7 SSI0Clk PA2 SSI0Fss PA3 SSI0Rx PA4 SSI0Tx PA5 SWCLK PC0 SWDIO PC1 SWO PC3 TCK PC0 TDI PC2 TDO PC3 TMS PC1 U0Rx PA0 U0Tx PA1 U1DSR PF0 VREFA PB6 EPI0S12 PF7 PF4 EPI0S15 PG4 PF5 U1DTR PG5 PD7 U1RTS PF6 PF1 SSI1Clk PF2 PE0 PH4 SSI1Fss PF3 PH5 PE1 SSI1Rx PF4 PH6 PE2 SSI1Tx PH7 PF5 PE3 U1CTS PE6 PD0 PA6 two three U1DCD PE7 PD1 PA7 U1RI PG6 PG4 PD4 I2C1SCL PJ0 PG0 PA0 PA6 I2C1SDA PG1 PA1 PA7 PJ1 U2Rx PD0 PG0 PB4 PD5 four U2Tx PE4 PD1 PG1 PD6 C0o PC5 PF4 PB6 PB5 PD7 C1o PE6 PC7 PC5 PF5 PH2 CCP6 PD0 PD2 PE1 PH0 PB5 CCP7 PD1 PD3 PH1 PB6 PE3 five six CCP4 PC7 PC4 PA7 PF7 PE2 PD5 U1Rx PD0 PD2 PC6 PA0 PB0 PB4 U1Tx PD1 PD3 PC7 PA1 PB1 PB5 July 24, 2011 883 Texas Instruments-Production Data Signal Tables Table 19-11. Possible Pin Assignments for Alternate Functions (continued) # of Possible Assignments Alternate Function seven CCP5 PE5 PD2 PC4 PG7 PG5 PB6 PB5 eight CCP1 PC5 PC4 PA6 PF6 PB1 PB6 PE3 PD7 nine 19.3 GPIO Function CCP0 PD3 PC7 PC6 PJ2 PF4 PB0 PB2 PB5 PD4 CCP2 PE4 PD1 PC4 PF5 PB1 PE1 PB5 PE2 PD5 CCP3 PE4 PC6 PC5 PA7 PG4 PF1 PB2 PE0 PD4 Connections for Unused Signals Table 19-12 on page 884 show how to handle signals for functions that are not used in a particular system implementation for devices that are in a 100-pin LQFP package. Two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx register. Table 19-12. Connections for Unused Signals (100-Pin LQFP) Function GPIO Hibernate No Connects System Control USB0RBIAS Signal Name Pin Number Acceptable Practice Preferred Practice All unused GPIOs - NC GND HIB 51 NC NC VBAT 55 NC GND WAKE 50 NC GND XOSC0 52 NC GND XOSC1 53 NC NC NC - NC NC OSC0 48 NC GND OSC1 49 NC NC RST 64 Pull up as shown in Figure 5-1 on page 177 Connect through a capacitor to GND as close to pin as possible 73 Connect to GND through 10-kΩ resistor. Connect to GND through 10-kΩ resistor. Table 19-13 on page 884 show how to handle signals for functions that are not used in a particular system implementation for devices that are in a 108-ball BGA package. Two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx register. Table 19-13. Connections for Unused Signals (108-Ball BGA) Function GPIO Signal Name Pin Number Acceptable Practice Preferred Practice All unused GPIOs - NC GND 884 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 19-13. Connections for Unused Signals (108-Ball BGA) (continued) Function Hibernate No Connects System Control Signal Name Pin Number Acceptable Practice Preferred Practice HIB M12 NC NC VBAT L12 NC GND WAKE M10 NC GND XOSC0 K11 NC GND XOSC1 K12 NC NC NC - NC NC OSC0 L11 NC GND OSC1 M11 NC NC RST H11 Pull up as shown in Figure Connect through a capacitor to 5-1 on page 177 GND as close to pin as possible July 24, 2011 885 Texas Instruments-Production Data Operating Characteristics 20 Operating Characteristics Table 20-1. Temperature Characteristics Characteristic Symbol Value Unit Industrial operating temperature range TA -40 to +85 °C Unpowered storage temperature range TS -65 to +150 °C Table 20-2. Thermal Characteristics Characteristic Symbol Value a Thermal resistance (junction to ambient) ΘJA Unit 33 (100LQFP) °C/W 31 (108BGA) b Junction temperature, -40 to +125 TJ TA + (P • ΘJA) °C a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator. b. Power dissipation is a function of temperature. a Table 20-3. ESD Absolute Maximum Ratings Parameter Name VESDHBM VESDCDM Min Nom Max Unit - - 2.0 kV - - 500 V ® a. All Stellaris parts are ESD tested following the JEDEC standard. 886 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 21 Electrical Characteristics 21.1 Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings. Table 21-1. Maximum Ratings Value a Parameter Parameter Name VDD Unit Min Max VDD supply voltage 0 4 V VDDA VDDA supply voltage 0 4 V VBAT VBAT battery supply voltage 0 4 V -0.3 5.5 V Input voltage VIN I VNON Input voltage for a GPIO configured as an analog input -0.3 VDD + 0.3 V Input voltage for PB0 and PB1 when configured as GPIO -0.3 VDD + 0.3 V Maximum current per output pin - 25 mA Maximum input voltage on a non-power pin when the microcontroller is unpowered - 300 mV a. Voltages are measured with respect to GND. Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (see “Connections for Unused Signals” on page 884). 21.2 Recommended Operating Conditions For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. Table 21-2. Recommended DC Operating Conditions Parameter Parameter Name Min Nom Max Unit VDD VDD supply voltage 3.0 3.3 3.6 V VDDA VDDA supply voltage 3.0 3.3 3.6 V VDDC VDDC supply voltage 1.235 1.3 1.365 V - 5.0 V VIH High-level input voltage 2.1 VIL Low-level input voltage -0.3 - 1.2 V High-level output voltage 2.4 - - V a VOH July 24, 2011 887 Texas Instruments-Production Data Electrical Characteristics Table 21-2. Recommended DC Operating Conditions (continued) Parameter VOLa Parameter Name Min Nom Max Unit - - 0.4 V 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 18 - - mA Low-level output voltage High-level source current, VOH=2.4 V IOH Low-level sink current, VOL=0.4 V IOL IOHC High-current sink, VOL=1.2 V a. VOL and VOH shift to 1.2 V when using high-current GPIOs. 21.3 Load Conditions Unless otherwise specified, the following conditions are true for all timing measurements. Figure 21-1. Load Conditions CL = 16 pF for EPI0S[31:0] signals 50 pF for other digital I/O signals pin GND 21.4 JTAG and Boundary Scan Table 21-3. JTAG Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit J1 FTCK TCK operational clock frequency 0 - 10 MHz J2 TTCK TCK operational clock period J3 TTCK_LOW TCK clock Low time 100 - - ns - tTCK - ns J4 TTCK_HIGH TCK clock High time - tTCK - ns J5 J6 TTCK_R TCK rise time 0 - 10 ns TTCK_F TCK fall time 0 - 10 ns J7 TTMS_SU TMS setup time to TCK rise 20 - - ns J8 TTMS_HLD TMS hold time from TCK rise 20 - - ns J9 TTDI_SU TDI setup time to TCK rise 25 - - ns J10 TTDI_HLD TDI hold time from TCK rise 25 - - ns a 888 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 21-3. JTAG Characteristics (continued) Parameter No. Parameter Parameter Name Min Nom Max Unit 23 35 ns 15 26 ns 14 25 ns TCK fall to Data Valid from High-Z, 8-mA drive with slew rate control 18 29 ns TCK fall to Data Valid from Data Valid, 2-mA drive 21 35 ns 14 25 ns 13 24 ns TCK fall to Data Valid from Data Valid, 8-mA drive with slew rate control 18 28 ns TCK fall to High-Z from Data Valid, 2-mA drive 9 11 ns 7 9 ns 6 8 ns 7 9 ns TCK fall to Data Valid from High-Z, 2-mA drive TCK fall to Data Valid from High-Z, 4-mA drive J11 TTDO_ZDV TCK fall to Data Valid from High-Z, 8-mA drive - TCK fall to Data Valid from Data Valid, 4-mA drive J12 TTDO_DV TCK fall to Data Valid from Data Valid, 8-mA drive - TCK fall to High-Z from Data Valid, 4-mA drive J13 TTDO_DVZ TCK fall to High-Z from Data Valid, 8-mA drive - TCK fall to High-Z from Data Valid, 8-mA drive with slew rate control a. A ratio of at least 8:1 must be kept between the system clock and TCK. Figure 21-2. JTAG Test Clock Input Timing J2 J3 J4 TCK J6 J5 Figure 21-3. JTAG Test Access Port (TAP) Timing TCK J7 TMS TDI J8 J8 TMS Input Valid TMS Input Valid J9 J9 J10 TDI Input Valid J11 TDO J7 J10 TDI Input Valid J12 TDO Output Valid July 24, 2011 J13 TDO Output Valid 889 Texas Instruments-Production Data Electrical Characteristics 21.5 Power and Brown-out Table 21-4. Power Characteristics Parameter No. Parameter P1 VTH Parameter Name Min Nom Max Unit Power-On Reset threshold - 2 - V P2 VBTH Brown-Out Reset threshold 2.85 2.9 2.95 V P3 TPOR Power-On Reset timeout 6 - 18 ms P4 TBOR Brown-Out timeout - 500 - µs P5 TIRPOR Internal reset timeout after POR - - 2 ms P6 TIRBOR Internal reset timeout after BOR - - 2 ms P7 TVDDRISE Supply voltage (VDD) rise time (0V-3.0V) - - 10 ms P8 TVDD2_3 Supply voltage (VDD) rise time (2.0V-3.0V) - - 6 ms Figure 21-4. Power-On Reset Timing P1 VDD P3 /POR (Internal) P5 /Reset (Internal) Figure 21-5. Brown-Out Reset Timing P2 VDD P4 /BOR (Internal) P6 /Reset (Internal) 890 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 21-6. Power-On Reset and Voltage Parameters VDD 3.0 P8 2.0 P7 21.6 Reset Table 21-5. Reset Characteristics Parameter No. Parameter Min Nom Max Unit R1 TIRHWR Internal reset timeout after hardware reset (RST pin) - - 2 ms R2 TIRSWR Internal reset timeout after software-initiated system reset - - 2 ms R3 TIRWDR Internal reset timeout after watchdog reset - - 2 ms R4 TIRMFR Internal reset timeout after MOSC failure reset - - 2 ms 2 - - µs R5 Parameter Name a Minimum RST pulse width TMIN a. This specification must be met in order to guarantee proper reset operation. Figure 21-7. External Reset Timing (RST) RST R1 R13 R5 /Reset (Internal) Figure 21-8. Software Reset Timing SW Reset R2 /Reset (Internal) July 24, 2011 891 Texas Instruments-Production Data Electrical Characteristics Figure 21-9. Watchdog Reset Timing WDOG Reset (Internal) R3 /Reset (Internal) Figure 21-10. MOSC Failure Reset Timing MOSC Fail Reset (Internal) R4 /Reset (Internal) 21.7 On-Chip Low Drop-Out (LDO) Regulator Table 21-6. LDO Regulator Characteristics Parameter 21.8 Parameter Name Min Nom Max Unit CLDO External filter capacitor size for internal power supply 1.0 - 3.0 µF VLDO LDO output voltage 1.235 1.3 1.365 V Clocks The following sections provide specifications on the various clock sources and mode. 21.8.1 PLL Specifications The following tables provide specifications for using the PLL. Table 21-7. Phase Locked Loop (PLL) Characteristics Parameter Parameter Name Min Nom Max Unit FREF_XTAL Crystal reference 3.579545 - 16.384 MHz FREF_EXT External clock referencea 3.579545 - 16.384 MHz 400 - MHz - 1.38 a b FPLL PLL frequency - TREADY PLL lock time 0.562 c d ms a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration (RCC) register. b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. c. Using a 16.384-MHz crystal d. Using 3.5795-MHz crystal Table 21-8 on page 893 shows the actual frequency of the PLL based on the crystal frequency used (defined by the XTAL field in the RCC register). 892 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 21-8. Actual PLL Frequency 21.8.2 XTAL Crystal Frequency (MHz) PLL Frequency (MHz) Error 0x04 0x05 3.5795 400.904 0.0023% 3.6864 398.1312 0.0047% 0x06 4.0 400 - 0x07 4.096 401.408 0.0035% 0x08 4.9152 398.1312 0.0047% 0x09 5.0 400 - 0x0A 5.12 399.36 0.0016% 0x0B 6.0 400 - 0x0C 6.144 399.36 0.0016% 0x0D 7.3728 398.1312 0.0047% 0x0E 8.0 400 - 0x0F 8.192 398.6773333 0.0033% 0x10 10.0 400 - 0x11 12.0 400 - 0x12 12.288 401.408 0.0035% 0x13 13.56 397.76 0.0056% 0x14 14.318 400.90904 0.0023% 0x15 16.0 400 - 0x16 16.384 404.1386667 0.010% PIOSC Specifications Table 21-9. PIOSC Clock Characteristics Parameter 21.8.3 Min Nom Max Unit FPIOSC25 Parameter Name Internal 16-MHz precision oscillator frequency variance, factory calibrated at 25 °C - ±0.25% ±1% - FPIOSCT Internal 16-MHz precision oscillator frequency variance, factory calibrated at 25 °C, across specified temperature range - - ±3% - FPIOSCUCAL Internal 16-MHz precision oscillator frequency variance, user calibrated at a chosen temperature - ±0.25% ±1% - Internal 30-kHz Oscillator Specifications Table 21-10. 30-kHz Clock Characteristics 21.8.4 Parameter Parameter Name FIOSC30KHZ Internal 30-KHz oscillator frequency Min Nom Max Unit 15 30 45 KHz Hibernation Clock Source Specifications Table 21-11. Hibernation Clock Characteristics Parameter FHIBOSC FHIBOSC_XTAL Parameter Name Min Nom Max Unit Hibernation module oscillator frequency - 4.194304 - MHz Crystal reference for hibernation oscillator - 4.194304 - MHz July 24, 2011 893 Texas Instruments-Production Data Electrical Characteristics Table 21-11. Hibernation Clock Characteristics (continued) Parameter Parameter Name Min a THIBOSC_START FHIBOSC_EXT DCHIBOSC_EXT Nom Max Unit Hibernation oscillator startup time - - 10 ms External clock reference for hibernation module - 32.768 - KHz 45 - 55 % External clock reference duty cycle a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance). Table 21-12. HIB Oscillator Input Characteristics Parameter FHIBOSC TOLHIBOSC 21.8.5 Parameter Name Min Nom Max Unit Hibernation module oscillator frequency - 4.194304 - MHz Hibernation oscillator frequency tolerance - Defined by customer application requirements - PPM Main Oscillator Specifications Table 21-13. Main Oscillator Clock Characteristics Parameter FMOSC TMOSC_PER TMOSC_SETTLE Parameter Name Min Nom Max Unit 1 - 16.384 MHz 61 - 1000 ns 17.5 - 20 ms Main oscillator frequency Main oscillator period a Main oscillator settling time TREF_XTAL_BYPASS Crystal reference using the main oscillator b (PLL in BYPASS mode) 1 - 16.384 MHz FREF_EXT_BYPASS External clock reference (PLL in BYPASS b mode) 0 - 50 MHz External clock reference duty cycle 45 - 55 % DCMOSC_EXT a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance). b. If the ADC is used, the crystal reference must be 16 MHz ± .03% when the PLL is bypassed. Table 21-14. Supported MOSC Crystal Frequencies Crystal Frequency (MHz) Not Using the PLL Crystal Frequency (MHz) Using the PLL 1.000 MHz reserved 1.8432 MHz reserved 2.000 MHz reserved 2.4576 MHz reserved 3.579545 MHz 3.6864 MHz 4 MHz 4.096 MHz 4.9152 MHz 5 MHz 5.12 MHz 6 MHz (reset value) 894 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 21-14. Supported MOSC Crystal Frequencies (continued) Crystal Frequency (MHz) Not Using the PLL Crystal Frequency (MHz) Using the PLL 6.144 MHz 7.3728 MHz 8 MHz 8.192 MHz 10.0 MHz 12.0 MHz 12.288 MHz 13.56 MHz 14.31818 MHz 16.0 MHz 16.384 MHz 21.8.6 System Clock Specification with ADC Operation Table 21-15. System Clock Characteristics with ADC Operation Parameter Fsysadc 21.9 Parameter Name System clock frequency when the ADC module is operating (when PLL is bypassed) Min Nom Max Unit 15.9952 16 16.0048 MHz Sleep Modes a Table 21-16. Sleep Modes AC Characteristics Parameter No Parameter D1 TWAKE_S D2 TWAKE_PLL_S D3 TENTER_DS Parameter Name Min Nom Max Unit Time to wake from interrupt in sleep or deep-sleep mode, not using the PLL - - 7 system clocks Time to wake from interrupt in sleep or deep-sleep mode when using the PLL - - TREADY ms Time to enter deep-sleep mode from sleep request - 0 35 b ms a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode. b. Nominal specification occurs 99.9995% of the time. 21.10 Hibernation Module The Hibernation module requires special system implementation considerations because it is intended to power down all other sections of its host device, refer to “Hibernation Module” on page 268. Table 21-17. Hibernation Module Battery Characteristics Parameter VBAT VLOWBAT Parameter Name Min Nominal Max Unit Battery supply voltage 2.4 3.0 3.6 V Low battery detect voltage 1.8 - 2.2 V July 24, 2011 895 Texas Instruments-Production Data Electrical Characteristics Table 21-18. Hibernation Module AC Characteristics Parameter No Parameter Parameter Name Min Nom Max Unit H1 THIB_LOW Internal 32.768 KHz clock reference rising edge to HIB asserted 20 - - μs H2 THIB_HIGH Internal 32.768 KHz clock reference rising edge to HIB deasserted - 30 - μs H3 TWAKE_TO_HIB WAKE assert to HIB desassert (wake up time), internal Hibernation oscillator running during a hibernation 62 - 124 μs H4 TWAKE_TO_HIB WAKE assert to HIB desassert (wake up time), internal Hibernation oscillator stopped during a hibernation - - 10 ms H5 TWAKE_CLOCK WAKE assertion time, internal Hibernation oscillator running during hibernation 62 - - μs H6 TWAKE_NOCLOCK WAKE assertion time, internal Hibernation oscillator b stopped during hibernation 10 - - ms H7 THIB_REG_ACCESS Time required for a write to a non-volatile register in the HIB module to complete 92 - - μs H8 THIB_TO_HIB HIB high time between assertions 100 - - H9 TENTER_HIB Time to enter hibernation mode from hibernation request - 0 ms c 35 ms a. Code begins executing after the time period specified by TIRPOR following the deassertion of HIB. b. This mode is used when the PINWEN bit is set and the RTCEN bit is clear in the HIBCTL register. c. Nominal specification occurs 99.998% of the time. Figure 21-11. Hibernation Module Timing with Internal Oscillator Running in Hibernation 32.768 KHz (internal) H1 H2 H8 HIB H3 WAKE H5 Figure 21-12. Hibernation Module Timing with Internal Oscillator Stopped in Hibernation 32.768 KHz (internal) H1 H2 H8 HIB H4 WAKE H6 896 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 21.11 Flash Memory Table 21-19. Flash Memory Characteristics Parameter PECYC TRET Parameter Name Number of guaranteed program/erase cycles a before failure Min Nom Max Unit 15,000 - - cycles 10 - - years Data retention, -40˚C to +85˚C TPROG Word program time - - 1 ms TBPROG Buffer program time - - 1 ms TERASE Page erase time - - 12 ms TME Mass erase time - - 16 ms a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 21.12 GPIO Module Note: All GPIOs are 5-V tolerant, except PB0 and PB1. See “Signal Description” on page 400 for more information on GPIO configuration. Table 21-20. GPIO Module Characteristics Parameter Parameter Name Min Nom Max Unit RGPIOPU GPIO internal pull-up resistor 100 - 300 kΩ RGPIOPD GPIO internal pull-down resistor 200 - 500 kΩ - ILKG a GPIO input leakage current - 2 µA b 14 20 ns b 7 10 ns 4 5 ns GPIO Rise Time, 2-mA drive TGPIOR GPIO Rise Time, 4-mA drive - b GPIO Rise Time, 8-mA drive b GPIO Rise Time, 8-mA drive with slew rate control 6 8 ns c 14 21 ns c 7 11 ns 4 6 ns 6 8 ns GPIO Fall Time, 2-mA drive TGPIOF GPIO Fall Time, 4-mA drive - c GPIO Fall Time, 8-mA drive c GPIO Fall Time, 8-mA drive with slew rate control a. The leakage current is measured with GND or VDD applied to the corresponding pin(s). The leakage of digital port pins is measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled. b. Time measured from 20% to 80% of VDD. c. Time measured from 80% to 20% of VDD. 21.13 External Peripheral Interface (EPI) When the EPI module is in SDRAM mode, the drive strength must be configured to 8 mA. Table 21-21 on page 897 shows the rise and fall times in SDRAM mode with 16 pF load conditions. When the EPI module is in Host-Bus or General-Purpose mode, the values in “GPIO Module” on page 897 should be used. Table 21-21. EPI SDRAM Characteristics Parameter TSDRAMR Parameter Name EPI Rise Time (from 20% to 80% of VDD) Condition 8-mA drive, CL = 16 pF July 24, 2011 Min Nom Max Unit - 2 3 ns 897 Texas Instruments-Production Data Electrical Characteristics Table 21-21. EPI SDRAM Characteristics (continued) Parameter TSDRAMF Parameter Name Condition EPI Fall Time (from 80% to 20% of VDD) 8-mA drive, CL = 16 pF Min Nom Max Unit - 2 3 ns a Table 21-22. EPI SDRAM Interface Characteristics Parameter No Parameter E1 TCK E2 E3 E4 Parameter Name Min Nom Max Unit SDRAM Clock period 20 - - ns TCH SDRAM Clock high time 10 - - ns TCL SDRAM Clock low time 10 - - ns TCOV CLK to output valid -5 - 5 ns E5 TCOI CLK to output invalid -5 - 5 ns E6 TCOT CLK to output tristate -5 - 5 ns E7 TS Input set up to CLK 10 - - ns E8 TH CLK to input hold 0 - - ns E9 TPU Power-up time 100 - - µs E10 TRP Precharge all banks 20 - - ns E11 TRFC Auto refresh 66 - - ns E12 TMRD Program mode register 40 - - ns a. The EPI SDRAM interface must use 8-mA drive. Figure 21-13. SDRAM Initialization and Load Mode Register Timing CLK (EPI0S31) E1 CKE (EPI0S30) E2 NOP Command (EPI0S[29:28,19:18]) NOP E3 NOP AREF PRE NOP PRE NOP NOP AREF LOAD NOP AREF Active DQMH, DQML (EPI0S[17:16]) AD11, AD[9:0] (EPI0S[11,9:0] Code Row Code Row All Banks AD10 (EPI0S[10]) Single Bank BAD[1:0] (EPI0S[14:13]) Bank AD [15,12] (EPI0S [15,12]) E9 E10 E11 E12 Notes: 1. If CS is high at clock high time, all applied commands are NOP. 2. The Mode register may be loaded prior to the auto refresh cycles if desired. 3. JEDEC and PC100 specify three clocks. 4. Outputs are guaranteed High-Z after command is issued. 898 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 21-14. SDRAM Read Timing CLK (EPI0S31) CKE (EPI0S30) E4 E5 E6 CSn (EPI0S29) WEn (EPI0S28) RASn (EPI0S19) CASn (EPI0S18) E7 DQMH, DQML (EPI0S [17:16]) AD [15:0] (EPI0S [15:0]) Row Column Activate NOP NOP Read E8 Data 0 Data 1 ... Data n Burst Term NOP AD [15:0] driven in AD [15:0] driven out AD [15:0] driven out Figure 21-15. SDRAM Write Timing CLK (EPI0S31) CKE (EPI0S30) E4 E5 E6 CSn (EPI0S29) WEn (EPI0S28) RASn (EPI0S19) CASn (EPI0S18) DQMH, DQML (EPI0S [17:16]) AD [15:0] (EPI0S [15:0]) Row Column-1 Activate NOP NOP Data 0 Data 1 ... Data n Burst Term Write AD [15:0] driven out AD [15:0] driven out Table 21-23. EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics Parameter No Parameter Min Nom Max Unit E14 TISU Read data set up time Parameter Name 10 - - ns E15 TIH Read data hold time 0 - - ns E16 TDV WEn to write data valid - - 5 ns E17 TDI Data hold from WEn invalid 2 - - EPI Clocks E18 TOV CSn to output valid -5 - 5 ns E19 TOINV E20 TSTLOW E21 TFIFO E22 TALEHIGH CSn to output invalid -5 - 5 ns WEn / RDn strobe width low 2 - - EPI Clocks FEMPTY and FFULL setup time to clock edge 2 - - System Clocks ALE width high - 1 - EPI Clocks July 24, 2011 899 Texas Instruments-Production Data Electrical Characteristics Table 21-23. EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics (continued) Parameter No Parameter E23 TCSLOW E24 TALEST E25 TALEADD Parameter Name Min Nom Max Unit CSn width low 4 - - EPI Clocks ALE rising to WEn / RDn strobe falling 2 - - EPI Clocks ALE falling to ADn tristate 1 - - EPI Clocks Figure 21-16. Host-Bus 8/16 Mode Read Timing E22 ALE (EPI0S30) E18 E23 CSn (EPI0S30) WRn (EPI0S29) E18 E24 E19 E20 RDn/OEn (EPI0S28) BSEL0n/ BSEL1na Address E15 E14 Data a Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. Figure 21-17. Host-Bus 8/16 Mode Write Timing E22 ALE (EPI0S30) E18 E23 CSn (EPI0S30) E18 E19 E20 WRn (EPI0S29) E24 RDn/Oen (EPI0S28) BSEL0n BSEL1na Address E16 Data a Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. 900 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 21-18. Host-Bus 8/16 Mode Muxed Read Timing E22 ALE (EPI0S30) E18 E23 CSn (EPI0S30) WRn (EPI0S29) E19 E18 E24 E20 RDn/OEn (EPI0S28) E25 BSEL0n/ BSEL1na a E15 E14 Muxed Address/Data Address Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. Figure 21-19. Host-Bus 8/16 Mode Muxed Write Timing E22 ALE (EPI0S30) E18 E23 CSn (EPI0S30) E18 E19 E20 WRn (EPI0S29) E24 RDn/Oen (EPI0S28) BSEL0n BSEL1na E16 Muxed Address/Data a Address Data BSEL0n and BSEL1n are available in Host-Bus 16 mode only. Table 21-24. EPI General-Purpose Interface Characteristics Parameter No Parameter Parameter Name Min Nom Max Unit E25 TCK General-Purpose Clock period 20 - - ns E26 TCH General-Purpose Clock high time 10 - - ns E27 TCL General-Purpose Clock low time 10 - - ns E28 TISU Input signal set up time to rising clock edge 10 - - ns E29 TIH Input signal hold time from rising clock edge 0 - - ns E30 TDV Falling clock edge to output valid -5 - 5 ns Falling clock edge to output invalid -5 - 5 ns iRDY assertion or deassertion set up time to falling clock edge 10 - - ns E31 TDI E32 TRDYSU July 24, 2011 901 Texas Instruments-Production Data Electrical Characteristics Figure 21-20. General-Purpose Mode Read and Write Timing E25 Clock (EPI0S31) E27 E30 Frame (EPI0S30) RD (EPI0S29) WR (EPI0S28) Address E30 E28 Data Data E31 Data E29 Read Write The above figure illustrates accesses where the FRM50 bit is clear, the FRMCNT field is 0x0, the RD2CYC bit is clear, and the WR2CYC bit is clear. Figure 21-21. General-Purpose Mode iRDY Timing Clock (EPI0S31) Frame (EPI0S30) E32 E32 RD (EPI0S29) iRDY (EPI0S27) Address Data 902 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 21.14 Analog-to-Digital Converter (ADC) a Table 21-25. ADC Characteristics Parameter Parameter Name VADCIN N FADC Min Nom Max Unit Maximum single-ended, full-scale analog input voltage, using internal reference - - 3.0 V Maximum single-ended, full-scale analog input voltage, using external reference - - VREFA V Minimum single-ended, full-scale analog input voltage 0.0 - - V Maximum differential, full-scale analog input voltage, using internal reference - - 1.5 V Maximum differential, full-scale analog input voltage, using external reference - - VREFA/2 V Minimum differential, full-scale analog input voltage 0.0 - Resolution b ADC internal clock frequency 15.9952 16 1 µs k samples/s TADCSAMP Sample time 125 - Latency from trigger to start of conversion - ADC input leakage - RADC ADC equivalent resistance CADC ADC equivalent capacitance ED EO EG ETS MHz 1000 Conversion rate EL 16.0048 c Conversion time FADCCONV IL V bits c TADCCONV TLT 12 - ns 2 - system clocks - 2.0 µA - - 10 kΩ 0.9 1.0 1.1 pF Integral nonlinearity (INL) error, 12-bit mode - - ±8 LSB Integral nonlinearity (INL) error, 10-bit mode - - ±2 LSB Differential nonlinearity (DNL) error, 12-bit mode - - ±4 LSB Differential nonlinearity (DNL) error, 10-bit mode - - ±2 LSB Offset error, 12-bit mode - - ±40 LSB Offset error, 10-bit mode - - ±10 LSB Full-scale gain error, 12-bit mode - - ±100 LSB Full-scale gain error, 10-bit mode - - ±25 LSB - - ±5 °C d Temperature sensor accuracy a. The ADC reference voltage is 3.0 V. This reference voltage is internally generated from the 3.3 VDDA supply by a band gap circuit. b. The ADC must be clocked from the PLL or directly from an external clock source to operate properly. c. The conversion time and rate scale from the specified number if the ADC internal clock frequency is any value other than 16 MHz. d. Note that this parameter does not include ADC error. July 24, 2011 903 Texas Instruments-Production Data Electrical Characteristics Figure 21-22. ADC Input Equivalency Diagram Stellaris® Microcontroller VDD ESD Clamp RADC ESD Clamp VIN 12-bit converter IL CADC Sample and hold ADC converter a Table 21-26. ADC Module External Reference Characteristics Parameter Parameter Name VREFA IL Min Nom Max Unit External voltage reference for ADC, when the VREF field b in the ADCCTL register is 0x1 2.97 - 3.03 V External voltage reference for ADC, when the VREF field c in the ADCCTL register is 0x3 0.99 - 1.01 V - - 2.0 µA External voltage reference leakage current a. Care must be taken to supply a reference voltage of acceptable quality. b. Ground is always used as the reference level for the minimum conversion value. c. Ground is always used as the reference level for the minimum conversion value. Table 21-27. ADC Module Internal Reference Characteristics Parameter VREFI 21.15 Parameter Name Internal voltage reference for ADC Min Nom Max Unit - 3.0 - V Synchronous Serial Interface (SSI) Table 21-28. SSI Characteristics Parameter No. Parameter Parameter Name Min S1 TCLK_PER SSIClk cycle time S2 TCLK_HIGH SSIClk high time S3 TCLK_LOW SSIClk low time a Nom Max 100 - - ns - 0.5 - t clk_per - 0.5 - t clk_per b Unit S4 TCLKRF SSIClk rise/fall time - 4 6 ns S5 TDMD Data from master valid delay time 0 - 1 system clocks S6 TDMS Data from master setup time 1 - - system clocks S7 TDMH Data from master hold time 2 - - system clocks S8 TDSS Data from slave setup time 1 - - system clocks 904 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 21-28. SSI Characteristics (continued) Parameter No. Parameter S9 TDSH Parameter Name Data from slave hold time Min Nom Max Unit 2 - - system clocks a. In master mode, the system clock must be at least twice as fast as the SSIClk; in slave mode, the system clock must be at least 12 times faster than the SSIClk. b. Note that the delays shown are using 8-mA drive strength. Figure 21-23. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement S1 S4 S2 SSIClk S3 SSIFss SSITx SSIRx MSB LSB 4 to 16 bits Figure 21-24. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer S2 S1 SSIClk S3 SSIFss SSITx MSB LSB 8-bit control SSIRx 0 MSB LSB 4 to 16 bits output data July 24, 2011 905 Texas Instruments-Production Data Electrical Characteristics Figure 21-25. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 S1 S4 S2 SSIClk (SPO=1) S3 SSIClk (SPO=0) S6 SSITx (master) S7 MSB S5 SSIRx (slave) S8 LSB S9 MSB LSB SSIFss 21.16 Inter-Integrated Circuit (I2C) Interface Table 21-29. I2C Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit a TSCH Start condition hold time 36 - - system clocks a TLP Clock Low period 36 - - system clocks b TSRT I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.4 V) - - (see note b) ns a TDH Data hold time 2 - - system clocks c TSFT I2CSCL/I2CSDA fall time (VIH =2.4 V to V IL =0.5 V) - 9 10 ns a THT Clock High time 24 - - system clocks a TDS Data setup time 18 - - system clocks a TSCSR Start condition setup time (for repeated start condition only) 36 - - system clocks a TSCS Stop condition setup time 24 - - system clocks I1 I2 I3 I4 I5 I6 I7 I8 I9 a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above values are minimum values. b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. c. Specified at a nominal 50 pF load. 906 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Figure 21-26. I2C Timing I2 I6 I5 I2CSCL I1 I4 I7 I8 I3 I9 I2CSDA 21.17 Ethernet Controller a Table 21-30. 100BASE-TX Transmitter Characteristics Parameter Name Min Nom Max Unit Peak output amplitude 950 - 1050 mVpk Output amplitude symmetry 98 - 102 % Output overshoot - - 5 % Rise/Fall time 3 - 5 ns Rise/Fall time imbalance - - 500 ps Duty cycle distortion - - ±250 ps Jitter - - 1.4 ns a. Measured at the line side of the transformer. a Table 21-31. 100BASE-TX Transmitter Characteristics (informative) Parameter Name Min Nom Max Unit Return loss 16 - - dB Open-circuit inductance 350 - - µH a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 21-32. 100BASE-TX Receiver Characteristics Parameter Name Min Nom Max Unit Signal detect assertion threshold 600 700 - mVppd Signal detect de-assertion threshold 350 425 - mVppd Differential input resistance - 3.6 - kΩ Jitter tolerance (pk-pk) 4 - - ns -80 - +80 % Signal detect assertion time Baseline wander tracking - - 1000 µs Signal detect de-assertion time - - 4 µs a Table 21-33. 10BASE-T Transmitter Characteristics Parameter Name Min Nom Max Peak differential output signal Harmonic content 2.2 - 2.7 V 27 - - dB Link pulse width - 100 - ns Start-of-idle pulse width, Last bit 0 - 300 - ns July 24, 2011 Unit 907 Texas Instruments-Production Data Electrical Characteristics Table 21-33. 10BASE-T Transmitter Characteristics (continued) Parameter Name Min Nom Max Unit - 350 - ns Start-of-idle pulse width, Last bit 1 a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. a Table 21-34. 10BASE-T Transmitter Characteristics (informative) Parameter Name Output return loss Min Nom Max Unit 15 - - dB 29-17log(f/10) - - dB Peak common-mode output voltage - - 50 mV Common-mode rejection - - 100 mV Common-mode rejection jitter - - 1 ns Output impedance balance a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 21-35. 10BASE-T Receiver Characteristics Parameter Name Min Nom Max Unit Jitter tolerance (pk-pk) 30 26 - ns Input squelched threshold 340 440 540 mVppd Differential input resistance - 3.6 - kΩ 25 - - V Common-mode rejection a Table 21-36. Isolation Transformers Name Value Condition 1 CT : 1 CT +/- 5% Open-circuit inductance 350 uH (min) @ 10 mV, 10 kHz Leakage inductance 0.40 uH (max) @ 1 MHz (min) Turns ratio Inter-winding capacitance 25 pF (max) DC resistance 0.9 Ohm (max) Insertion loss 0.4 dB (typ) 0-65 MHz 1500 Vrms HIPOT a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics. Note: 21.18 The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. Analog Comparator Table 21-37. Analog Comparator Characteristics Parameter Parameter Name Min Nom Max Unit VOS Input offset voltage - ±10 ±25 mV VCM Input common mode voltage range 0 - VDD-1.5 V CMRR Common mode rejection ratio 50 - - dB - - 1 µs TRT Response time 908 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 21-37. Analog Comparator Characteristics (continued) Parameter TMC Parameter Name Min Nom Max Unit - - 10 µs Comparator mode change to Output Valid Table 21-38. Analog Comparator Voltage Reference Characteristics Parameter 21.19 Min Nom Max Unit RHR Resolution high range Parameter Name - VDD/31 - LSB RLR Resolution low range - VDD/23 - LSB AHR Absolute accuracy high range - - ±1/2 LSB ALR Absolute accuracy low range - - ±1/4 LSB Current Consumption This section provides information on typical and maximum power consumption under various conditions. Unless otherwise indicated, current consumption numbers include use of the on-chip LDO regulator and therefore include IDDC. 21.19.1 Nominal Power Consumption The following table provides nominal figures for current consumption. Table 21-39. Nominal Power Consumption Parameter IDD_RUN Parameter Name Conditions Nom Unit Run mode 1 (Flash loop) VDD = 3.3 V 90 mA 550 µA 30 µA 44 µA Code= while(1){} executed out of Flash Peripherals = All ON System Clock = 80 MHz (with PLL) Temp = 25°C IDD_DEEPSLEEP Deep-sleep mode Peripherals = All OFF System Clock = IOSC30KHZ/64 Temp = 25°C IHIB_NORTC Hibernate mode (external wake, VBAT = 3.0 V a RTC disabled, I/O not powered ) V = 0 V DD VDDA = 0 V Peripherals = All OFF System Clock = OFF Hibernate Module = 0 kHz IHIB_RTC Hibernate mode (RTC enabled, a I/O not powered ) VBAT = 3.0 V VDD = 0 V VDDA = 0 V Peripherals = All OFF System Clock = OFF Hibernate Module = 32 kHz a. The VDD3ON mode must be disabled for the I/O ring to be unpowered. July 24, 2011 909 Texas Instruments-Production Data Electrical Characteristics 21.19.2 Maximum Current Consumption The current measurements specified in the table that follows are maximum values under the following conditions: ■ VDD = 3.6 V ■ VDDC = 1.3 V ■ VBAT = 3.25 V ■ VDDA = 3.6 V ■ Temperature = 25°C ■ Clock source (MOSC) =3.579545-MHz crystal oscillator Table 21-40. Detailed Current Specifications Parameter IDD_RUN Parameter Name Conditions Max Unit Run mode 1 (Flash loop) VDD = 3.6 V 135 mA 46 mA 1.6 mA Code= while(1){} executed out of Flash Peripherals = All ON System Clock = 80 MHz (with PLL) Temperature = 25°C IDD_SLEEP Sleep mode VDD = 3.6 V Peripherals = All Clock Gated System Clock = 80 MHz (with PLL) Temperature = 25°C IDD_DEEPSLEEP Deep-Sleep mode VDD = 3.6 V Peripherals = All Clock Gated System Clock = IOSC30/64 Temperature = 25°C Table 21-41. Hibernation Detailed Current Specifications Parameter Parameter Name Conditions Max Unit IHIB_NORTC Hibernate mode (external wake, a RTC disabled, I/O not powered ) VBAT = 3.25 V 118 µA VDD = 0 V VDDA = 0 V Peripherals = All OFF System Clock = OFF Hibernate Module = 0 kHz Temperature = 25°C 910 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller Table 21-41. Hibernation Detailed Current Specifications (continued) Parameter IHIB_RTC Parameter Name Conditions Hibernate mode (RTC enabled, I/O VBAT = 3.25 V a not powered ) VDD = 0 V Max Unit 141 µA VDDA = 0 V Peripherals = All OFF System Clock = OFF Hibernate Module = 32.768 kHz Temperature = 25°C a. The VDD3ON mode must be disabled for the I/O ring to be unpowered. Table 21-42. External VDDC Source Current Specifications Parameter IDDC_RUN Parameter Name Conditions Run mode 1 (Flash loop), VDDC VDD = 3.6 V current VDDC = 1.3 V Max Unit 98 mA Code= while(1){} executed out of Flash Peripherals = All ON System Clock = 80 MHz (with PLL) Temperature = 25°C July 24, 2011 911 Texas Instruments-Production Data Register Quick Reference A Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The Cortex-M3 Processor R0, type R/W, , reset - (see page 60) DATA DATA R1, type R/W, , reset - (see page 60) DATA DATA R2, type R/W, , reset - (see page 60) DATA DATA R3, type R/W, , reset - (see page 60) DATA DATA R4, type R/W, , reset - (see page 60) DATA DATA R5, type R/W, , reset - (see page 60) DATA DATA R6, type R/W, , reset - (see page 60) DATA DATA R7, type R/W, , reset - (see page 60) DATA DATA R8, type R/W, , reset - (see page 60) DATA DATA R9, type R/W, , reset - (see page 60) DATA DATA R10, type R/W, , reset - (see page 60) DATA DATA R11, type R/W, , reset - (see page 60) DATA DATA R12, type R/W, , reset - (see page 60) DATA DATA SP, type R/W, , reset - (see page 61) SP SP LR, type R/W, , reset 0xFFFF.FFFF (see page 62) LINK LINK PC, type R/W, , reset - (see page 63) PC PC 912 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR, type R/W, , reset 0x0100.0000 (see page 64) N Z C V Q ICI / IT THUMB ICI / IT ISRNUM PRIMASK, type R/W, , reset 0x0000.0000 (see page 68) PRIMASK FAULTMASK, type R/W, , reset 0x0000.0000 (see page 69) FAULTMASK BASEPRI, type R/W, , reset 0x0000.0000 (see page 70) BASEPRI CONTROL, type R/W, , reset 0x0000.0000 (see page 71) ASP TMPL INTEN ENABLE Cortex-M3 Peripherals System Timer (SysTick) Registers Base 0xE000.E000 STCTRL, type R/W, offset 0x010, reset 0x0000.0004 COUNT CLK_SRC STRELOAD, type R/W, offset 0x014, reset 0x0000.0000 RELOAD RELOAD STCURRENT, type R/WC, offset 0x018, reset 0x0000.0000 CURRENT CURRENT Cortex-M3 Peripherals Nested Vectored Interrupt Controller (NVIC) Registers Base 0xE000.E000 EN0, type R/W, offset 0x100, reset 0x0000.0000 INT INT EN1, type R/W, offset 0x104, reset 0x0000.0000 INT INT DIS0, type R/W, offset 0x180, reset 0x0000.0000 INT INT DIS1, type R/W, offset 0x184, reset 0x0000.0000 INT INT PEND0, type R/W, offset 0x200, reset 0x0000.0000 INT INT PEND1, type R/W, offset 0x204, reset 0x0000.0000 INT INT UNPEND0, type R/W, offset 0x280, reset 0x0000.0000 INT INT July 24, 2011 913 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNPEND1, type R/W, offset 0x284, reset 0x0000.0000 INT INT ACTIVE0, type RO, offset 0x300, reset 0x0000.0000 INT INT ACTIVE1, type RO, offset 0x304, reset 0x0000.0000 INT INT PRI0, type R/W, offset 0x400, reset 0x0000.0000 INTD INTC INTB INTA PRI1, type R/W, offset 0x404, reset 0x0000.0000 INTD INTC INTB INTA PRI2, type R/W, offset 0x408, reset 0x0000.0000 INTD INTC INTB INTA PRI3, type R/W, offset 0x40C, reset 0x0000.0000 INTD INTC INTB INTA PRI4, type R/W, offset 0x410, reset 0x0000.0000 INTD INTC INTB INTA PRI5, type R/W, offset 0x414, reset 0x0000.0000 INTD INTC INTB INTA PRI6, type R/W, offset 0x418, reset 0x0000.0000 INTD INTC INTB INTA PRI7, type R/W, offset 0x41C, reset 0x0000.0000 INTD INTC INTB INTA PRI8, type R/W, offset 0x420, reset 0x0000.0000 INTD INTC INTB INTA PRI9, type R/W, offset 0x424, reset 0x0000.0000 INTD INTC INTB INTA PRI10, type R/W, offset 0x428, reset 0x0000.0000 INTD INTC INTB INTA PRI11, type R/W, offset 0x42C, reset 0x0000.0000 INTD INTC INTB INTA PRI12, type R/W, offset 0x430, reset 0x0000.0000 INTD INTC INTB INTA PRI13, type R/W, offset 0x434, reset 0x0000.0000 INTD INTC INTB INTA 914 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWTRIG, type WO, offset 0xF00, reset 0x0000.0000 INTID Cortex-M3 Peripherals System Control Block (SCB) Registers Base 0xE000.E000 ACTLR, type R/W, offset 0x008, reset 0x0000.0000 DISFOLD DISWBUF DISMCYC CPUID, type RO, offset 0xD00, reset 0x412F.C230 IMP VAR CON PARTNO REV INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000 NMISET PENDSV UNPENDSV PENDSTSET PENDSTCLR VECPEND ISRPRE ISRPEND VECPEND RETBASE VECACT VTABLE, type R/W, offset 0xD08, reset 0x0000.0000 BASE OFFSET OFFSET APINT, type R/W, offset 0xD0C, reset 0xFA05.0000 VECTKEY PRIGROUP ENDIANESS SYSRESREQ VECTCLRACT VECTRESET SYSCTRL, type R/W, offset 0xD10, reset 0x0000.0000 SEVONPEND SLEEPDEEP SLEEPEXIT CFGCTRL, type R/W, offset 0xD14, reset 0x0000.0200 DIV0 STKALIGN BFHFNMIGN UNALIGNED MAINPEND BASETHR SYSPRI1, type R/W, offset 0xD18, reset 0x0000.0000 USAGE BUS MEM SYSPRI2, type R/W, offset 0xD1C, reset 0x0000.0000 SVC SYSPRI3, type R/W, offset 0xD20, reset 0x0000.0000 TICK PENDSV DEBUG SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000 USAGE SVC BUSP MEMP USAGEP TICK PNDSV MON SVCA USGA BUS MEM BUSA MEMA INVSTAT UNDEF DERR IERR FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000 BFARV BSTKE BUSTKE IMPRE DIV0 UNALIGN PRECISE IBUS NOCP MMARV MSTKE MUSTKE INVPC HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000 DBG FORCED VECT MMADDR, type R/W, offset 0xD34, reset ADDR ADDR FAULTADDR, type R/W, offset 0xD38, reset ADDR ADDR July 24, 2011 915 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cortex-M3 Peripherals Memory Protection Unit (MPU) Registers Base 0xE000.E000 MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800 IREGION DREGION SEPARATE MPUCTRL, type R/W, offset 0xD94, reset 0x0000.0000 PRIVDEFEN HFNMIENA ENABLE MPUNUMBER, type R/W, offset 0xD98, reset 0x0000.0000 NUMBER MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000 ADDR ADDR VALID REGION VALID REGION VALID REGION VALID REGION MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000 ADDR ADDR MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000 ADDR ADDR MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.0000 ADDR ADDR MPUATTR, type R/W, offset 0xDA0, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR1, type R/W, offset 0xDA8, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR2, type R/W, offset 0xDB0, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR3, type R/W, offset 0xDB8, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE System Control Base 0x400F.E000 DID0, type RO, offset 0x000, reset - (see page 193) VER CLASS MAJOR MINOR PBORCTL, type R/W, offset 0x030, reset 0x0000.0002 (see page 195) BORIOR RIS, type RO, offset 0x050, reset 0x0000.0000 (see page 196) MOSCPUPRIS PLLLRIS BORRIS MOSCPUPIM PLLLIM BORIM IMC, type R/W, offset 0x054, reset 0x0000.0000 (see page 198) 916 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MISC, type R/W1C, offset 0x058, reset 0x0000.0000 (see page 200) PLLLMIS MOSCPUPMIS BORMIS RESC, type R/W, offset 0x05C, reset - (see page 202) MOSCFAIL WDT1 SW WDT0 BOR POR EXT RCC, type R/W, offset 0x060, reset 0x0780.3AD1 (see page 204) ACG PWRDN SYSDIV BYPASS USESYSDIV XTAL OSCSRC IOSCDIS MOSCDIS PLLCFG, type RO, offset 0x064, reset - (see page 208) F R GPIOHBCTL, type R/W, offset 0x06C, reset 0x0000.0000 (see page 209) PORTJ PORTH PORTG PORTF PORTE PORTD PORTC PORTB PORTA RCC2, type R/W, offset 0x070, reset 0x07C0.6810 (see page 211) USERCC2 DIV400 SYSDIV2 PWRDN2 SYSDIV2LSB BYPASS2 OSCSRC2 MOSCCTL, type R/W, offset 0x07C, reset 0x0000.0000 (see page 214) CVAL DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 (see page 215) DSDIVORIDE DSOSCSRC PIOSCCAL, type R/W, offset 0x150, reset 0x0000.0000 (see page 217) UTEN CAL UPDATE UT PIOSCSTAT, type RO, offset 0x154, reset 0x0000.0040 (see page 219) DT RESULT CT DID1, type RO, offset 0x004, reset - (see page 220) VER FAM PARTNO PINCOUNT TEMP PKG ROHS QUAL DC0, type RO, offset 0x008, reset 0x00BF.00BF (see page 222) SRAMSZ FLASHSZ DC1, type RO, offset 0x010, reset - (see page 223) WDT1 ADC0 MINSYSDIV MAXADC0SPD MPU HIB TEMPSNS PLL SSI1 SSI0 ADC0AIN5 ADC0AIN4 GPIOF GPIOE WDT0 SWO SWD JTAG TIMER3 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 GPIOD GPIOC GPIOB GPIOA DC2, type RO, offset 0x014, reset 0x430F.5037 (see page 225) EPI0 COMP1 I2C1 COMP0 I2C0 DC3, type RO, offset 0x018, reset 0xBFFF.0FC0 (see page 227) 32KHZ CCP5 CCP4 CCP3 C1O CCP2 CCP1 C1PLUS C1MINUS CCP0 C0O ADC0AIN7 ADC0AIN6 C0PLUS C0MINUS DC4, type RO, offset 0x01C, reset 0x0004.F1FF (see page 229) PICAL CCP7 CCP6 UDMA ROM GPIOJ GPIOH GPIOG DC5, type RO, offset 0x020, reset 0x0000.0000 (see page 231) July 24, 2011 917 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DC6, type RO, offset 0x024, reset 0x0000.0000 (see page 232) DC7, type RO, offset 0x028, reset 0xFFFF.FFFF (see page 233) DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16 DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 DMACH3 DMACH2 DMACH1 DMACH0 DC8, type RO, offset 0x02C, reset 0x0000.00FF (see page 237) ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 DC9, type RO, offset 0x190, reset 0x0000.00FF (see page 238) ADC0DC7 ADC0DC6 ADC0DC5 ADC0DC4 ADC0DC3 ADC0DC2 ADC0DC1 ADC0DC0 NVMSTAT, type RO, offset 0x1A0, reset 0x0000.0001 (see page 239) FWB RCGC0, type R/W, offset 0x100, reset 0x00000040 (see page 240) WDT1 ADC0 MAXADC0SPD HIB WDT0 MAXADC0SPD HIB WDT0 HIB WDT0 SCGC0, type R/W, offset 0x110, reset 0x00000040 (see page 242) WDT1 ADC0 DCGC0, type R/W, offset 0x120, reset 0x00000040 (see page 244) WDT1 ADC0 RCGC1, type R/W, offset 0x104, reset 0x00000000 (see page 246) EPI0 COMP1 I2C1 COMP0 TIMER3 I2C0 SSI1 SSI0 SSI1 SSI0 SSI1 SSI0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 SCGC1, type R/W, offset 0x114, reset 0x00000000 (see page 249) EPI0 COMP1 I2C1 COMP0 TIMER3 I2C0 DCGC1, type R/W, offset 0x124, reset 0x00000000 (see page 252) EPI0 COMP1 I2C1 COMP0 TIMER3 I2C0 RCGC2, type R/W, offset 0x108, reset 0x00000000 (see page 255) UDMA GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SCGC2, type R/W, offset 0x118, reset 0x00000000 (see page 257) UDMA DCGC2, type R/W, offset 0x128, reset 0x00000000 (see page 259) UDMA SRCR0, type R/W, offset 0x040, reset 0x00000000 (see page 261) WDT1 ADC0 HIB WDT0 SRCR1, type R/W, offset 0x044, reset 0x00000000 (see page 263) EPI0 COMP1 I2C1 COMP0 TIMER3 I2C0 SSI1 SSI0 GPIOF GPIOE TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 GPIOC GPIOB GPIOA SRCR2, type R/W, offset 0x048, reset 0x00000000 (see page 266) UDMA GPIOJ GPIOH GPIOG 918 GPIOD July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HIBREQ RTCEN Hibernation Module Base 0x400F.C000 HIBRTCC, type RO, offset 0x000, reset 0x0000.0000 (see page 279) RTCC RTCC HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF (see page 280) RTCM0 RTCM0 HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF (see page 281) RTCM1 RTCM1 HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF (see page 282) RTCLD RTCLD HIBCTL, type R/W, offset 0x010, reset 0x8000.0000 (see page 283) WRC VDD3ON VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 286) EXTW LOWBAT RTCALT1 RTCALT0 EXTW LOWBAT RTCALT1 RTCALT0 EXTW LOWBAT RTCALT1 RTCALT0 EXTW LOWBAT RTCALT1 RTCALT0 HIBRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 288) HIBMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 290) HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000 (see page 292) HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF (see page 293) TRIM HIBDATA, type R/W, offset 0x030-0x12C, reset - (see page 294) RTD RTD Internal Memory Flash Memory Registers (Flash Control Offset) Base 0x400F.D000 FMA, type R/W, offset 0x000, reset 0x0000.0000 OFFSET OFFSET FMD, type R/W, offset 0x004, reset 0x0000.0000 DATA DATA FMC, type R/W, offset 0x008, reset 0x0000.0000 WRKEY COMT MERASE ERASE WRITE PRIS ARIS FCRIS, type RO, offset 0x00C, reset 0x0000.0000 July 24, 2011 919 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMASK AMASK PMISC AMISC FCIM, type R/W, offset 0x010, reset 0x0000.0000 FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000 FMC2, type R/W, offset 0x020, reset 0x0000.0000 WRKEY WRBUF FWBVAL, type R/W, offset 0x030, reset 0x0000.0000 FWB[n] FWB[n] FCTL, type R/W, offset 0x0F8, reset 0x0000.0000 USDACK USDREQ FWBn, type R/W, offset 0x100 - 0x17C, reset 0x0000.0000 DATA DATA Internal Memory Memory Registers (System Control Offset) Base 0x400F.E000 RMCTL, type R/W1C, offset 0x0F0, reset - BA FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE BOOTCFG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE NW PORT PIN POL EN DBG1 DBG0 USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF NW DATA DATA USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF NW DATA DATA USER_REG2, type R/W, offset 0x1E8, reset 0xFFFF.FFFF NW DATA DATA USER_REG3, type R/W, offset 0x1EC, reset 0xFFFF.FFFF NW DATA DATA FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE 920 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE4, type R/W, offset 0x210, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE5, type R/W, offset 0x214, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE6, type R/W, offset 0x218, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPRE7, type R/W, offset 0x21C, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE4, type R/W, offset 0x410, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE5, type R/W, offset 0x414, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE6, type R/W, offset 0x418, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE FMPPE7, type R/W, offset 0x41C, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE Micro Direct Memory Access (μDMA) μDMA Channel Control Structure (Offset from Channel Control Table Base) Base n/a DMASRCENDP, type R/W, offset 0x000, reset ADDR ADDR DMADSTENDP, type R/W, offset 0x004, reset ADDR ADDR DMACHCTL, type R/W, offset 0x008, reset DSTINC ARBSIZE DSTSIZE SRCINC SRCSIZE XFERSIZE July 24, 2011 ARBSIZE NXTUSEBURST XFERMODE 921 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Micro Direct Memory Access (μDMA) μDMA Registers (Offset from μDMA Base Address) Base 0x400F.F000 DMASTAT, type RO, offset 0x000, reset 0x001F.0000 DMACHANS STATE MASTEN DMACFG, type WO, offset 0x004, reset - MASTEN DMACTLBASE, type R/W, offset 0x008, reset 0x0000.0000 ADDR ADDR DMAALTBASE, type RO, offset 0x00C, reset 0x0000.0200 ADDR ADDR DMAWAITSTAT, type RO, offset 0x010, reset 0xFFFF.FFC0 WAITREQ[n] WAITREQ[n] DMASWREQ, type WO, offset 0x014, reset SWREQ[n] SWREQ[n] DMAUSEBURSTSET, type R/W, offset 0x018, reset 0x0000.0000 SET[n] SET[n] DMAUSEBURSTCLR, type WO, offset 0x01C, reset CLR[n] CLR[n] DMAREQMASKSET, type R/W, offset 0x020, reset 0x0000.0000 SET[n] SET[n] DMAREQMASKCLR, type WO, offset 0x024, reset CLR[n] CLR[n] DMAENASET, type R/W, offset 0x028, reset 0x0000.0000 SET[n] SET[n] DMAENACLR, type WO, offset 0x02C, reset CLR[n] CLR[n] DMAALTSET, type R/W, offset 0x030, reset 0x0000.0000 SET[n] SET[n] DMAALTCLR, type WO, offset 0x034, reset CLR[n] CLR[n] DMAPRIOSET, type R/W, offset 0x038, reset 0x0000.0000 SET[n] SET[n] DMAPRIOCLR, type WO, offset 0x03C, reset CLR[n] CLR[n] 922 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAERRCLR, type R/W, offset 0x04C, reset 0x0000.0000 ERRCLR DMACHASGN, type R/W, offset 0x500, reset 0x0000.0000 CHASGN[n] CHASGN[n] DMACHIS, type R/W1C, offset 0x504, reset 0x0000.0000 CHIS[n] CHIS[n] DMAPeriphID0, type RO, offset 0xFE0, reset 0x0000.0030 PID0 DMAPeriphID1, type RO, offset 0xFE4, reset 0x0000.00B2 PID1 DMAPeriphID2, type RO, offset 0xFE8, reset 0x0000.000B PID2 DMAPeriphID3, type RO, offset 0xFEC, reset 0x0000.0000 PID3 DMAPeriphID4, type RO, offset 0xFD0, reset 0x0000.0004 PID4 DMAPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 DMAPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 DMAPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 DMAPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 General-Purpose Input/Outputs (GPIOs) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 (see page 414) DATA July 24, 2011 923 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 (see page 415) DIR GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 (see page 416) IS GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 (see page 417) IBE GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 (see page 418) IEV GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 (see page 419) IME GPIORIS, type RO, offset 0x414, reset 0x0000.0000 (see page 420) RIS GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 (see page 421) MIS GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 (see page 423) IC GPIOAFSEL, type R/W, offset 0x420, reset - (see page 424) AFSEL GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF (see page 426) DRV2 GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 (see page 427) DRV4 GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 (see page 428) DRV8 GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 (see page 429) ODE GPIOPUR, type R/W, offset 0x510, reset - (see page 430) PUE GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 432) PDE GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 434) SRL GPIODEN, type R/W, offset 0x51C, reset - (see page 435) DEN 924 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 (see page 437) LOCK LOCK GPIOCR, type -, offset 0x524, reset - (see page 438) CR GPIOAMSEL, type R/W, offset 0x528, reset 0x0000.0000 (see page 440) GPIOAMSEL GPIOPCTL, type R/W, offset 0x52C, reset - (see page 442) PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 444) PID4 GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 445) PID5 GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 446) PID6 GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 447) PID7 GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 (see page 448) PID0 GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 449) PID1 GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 450) PID2 GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 451) PID3 GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 452) CID0 GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 453) CID1 GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 454) CID2 GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 455) CID3 External Peripheral Interface (EPI) Base 0x400D.0000 EPICFG, type R/W, offset 0x000, reset 0x0000.0000 (see page 488) BLKEN July 24, 2011 MODE 925 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EPIBAUD, type R/W, offset 0x004, reset 0x0000.0000 (see page 489) COUNT1 COUNT0 EPISDRAMCFG, type R/W, offset 0x010, reset 0x42EE.0000 (see page 491) FREQ RFSH SLEEP SIZE EPIHB8CFG, type R/W, offset 0x010, reset 0x0000.0000 (see page 493) XFFEN MAXWAIT XFEEN WRHIGH RDHIGH WRWS RDWS MODE EPIHB16CFG, type R/W, offset 0x010, reset 0x0000.0000 (see page 496) XFFEN MAXWAIT XFEEN WRHIGH RDHIGH WRWS RDWS BSEL MODE EPIGPCFG, type R/W, offset 0x010, reset 0x0000.0000 (see page 500) CLKPIN CLKGATE RDYEN FRMPIN FRM50 FRMCNT RW MAXWAIT WR2CYC RD2CYC ASIZE DSIZE EPIHB8CFG2, type R/W, offset 0x014, reset 0x0000.0000 (see page 505) WORD CSBAUD CSCFG WRHIGH RDHIGH WRWS RDWS EPIHB16CFG2, type R/W, offset 0x014, reset 0x0000.0000 (see page 508) WORD CSBAUD CSCFG WRHIGH RDHIGH WRWS RDWS EPSZ EPADR EPIGPCFG2, type R/W, offset 0x014, reset 0x0000.0000 (see page 511) WORD EPIADDRMAP, type R/W, offset 0x01C, reset 0x0000.0000 (see page 512) ERSZ ERADR EPIRSIZE0, type R/W, offset 0x020, reset 0x0000.0003 (see page 514) SIZE EPIRSIZE1, type R/W, offset 0x030, reset 0x0000.0003 (see page 514) SIZE EPIRADDR0, type R/W, offset 0x024, reset 0x0000.0000 (see page 515) ADDR ADDR EPIRADDR1, type R/W, offset 0x034, reset 0x0000.0000 (see page 515) ADDR ADDR EPIRPSTD0, type R/W, offset 0x028, reset 0x0000.0000 (see page 516) POSTCNT EPIRPSTD1, type R/W, offset 0x038, reset 0x0000.0000 (see page 516) POSTCNT EPISTAT, type RO, offset 0x060, reset 0x0000.0000 (see page 518) CELOW XFFULL XFEMPTY INITSEQ WBUSY NBRBUSY ACTIVE EPIRFIFOCNT, type RO, offset 0x06C, reset - (see page 520) COUNT 926 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WFERR RSERR EPIREADFIFO, type RO, offset 0x070, reset - (see page 521) DATA DATA EPIREADFIFO1, type RO, offset 0x074, reset - (see page 521) DATA DATA EPIREADFIFO2, type RO, offset 0x078, reset - (see page 521) DATA DATA EPIREADFIFO3, type RO, offset 0x07C, reset - (see page 521) DATA DATA EPIREADFIFO4, type RO, offset 0x080, reset - (see page 521) DATA DATA EPIREADFIFO5, type RO, offset 0x084, reset - (see page 521) DATA DATA EPIREADFIFO6, type RO, offset 0x088, reset - (see page 521) DATA DATA EPIREADFIFO7, type RO, offset 0x08C, reset - (see page 521) DATA DATA EPIFIFOLVL, type R/W, offset 0x200, reset 0x0000.0033 (see page 522) WRFIFO RDFIFO EPIWFIFOCNT, type RO, offset 0x204, reset 0x0000.0004 (see page 524) WTAV EPIIM, type R/W, offset 0x210, reset 0x0000.0000 (see page 525) WRIM RDIM ERRIM WRRIS RDRIS ERRRIS WRMIS RDMIS ERRMIS WTFULL RSTALL TOUT EPIRIS, type RO, offset 0x214, reset 0x0000.0004 (see page 526) EPIMIS, type RO, offset 0x218, reset 0x0000.0000 (see page 528) EPIEISC, type R/W1C, offset 0x21C, reset 0x0000.0000 (see page 529) General-Purpose Timers Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 (see page 547) GPTMCFG GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 (see page 548) TASNAPS TAWOT TAMIE July 24, 2011 TACDIR TAAMS TACMR TAMR 927 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBSNAPS TBWOT TBMIE TBCDIR TBAMS TBCMR TAPWML TAOTE RTCEN GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 (see page 550) TBMR GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 (see page 552) TBPWML TBOTE TBEVENT TBSTALL TBEN TAEVENT TASTALL TAEN GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 (see page 555) TBMIM CBEIM CBMIM TBTOIM TAMIM RTCIM CAEIM CAMIM TATOIM CBMRIS TBTORIS TAMRIS RTCRIS CAERIS CAMRIS TATORIS TAMMIS RTCMIS CAEMIS CAMMIS TATOMIS GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 557) TBMRIS CBERIS GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 (see page 560) TBMMIS CBEMIS CBMMIS TBTOMIS GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 (see page 563) TBMCINT CBECINT CBMCINT TBTOCINT TAMCINT RTCCINT CAECINT CAMCINT TATOCINT GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF (see page 565) TAILR TAILR GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 566) TBILR TBILR GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF (see page 567) TAMR TAMR GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF (see page 568) TBMR TBMR GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 (see page 569) TAPSR GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 (see page 570) TBPSR GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 (see page 571) TAPSMR GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 (see page 572) TBPSMR GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF (see page 573) TAR TAR GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (see page 574) TBR TBR GPTMTAV, type RW, offset 0x050, reset 0xFFFF.FFFF (see page 575) TAV TAV 928 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESEN INTEN GPTMTBV, type RW, offset 0x054, reset 0x0000.FFFF (see page 576) TBV TBV Watchdog Timers WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF (see page 581) WDTLOAD WDTLOAD WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF (see page 582) WDTVALUE WDTVALUE WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 (WDT0) and 0x8000.0000 (WDT1) (see page 583) WRC WDTICR, type WO, offset 0x00C, reset - (see page 585) WDTINTCLR WDTINTCLR WDTRIS, type RO, offset 0x010, reset 0x0000.0000 (see page 586) WDTRIS WDTMIS, type RO, offset 0x014, reset 0x0000.0000 (see page 587) WDTMIS WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 (see page 588) STALL WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 (see page 589) WDTLOCK WDTLOCK WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 590) PID4 WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 591) PID5 WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 592) PID6 WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 593) PID7 WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 (see page 594) PID0 WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 (see page 595) PID1 WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 596) PID2 July 24, 2011 929 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASEN3 ASEN2 ASEN1 ASEN0 INR3 INR2 INR1 WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 597) PID3 WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 598) CID0 WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 599) CID1 WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0006 (see page 600) CID2 WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 601) CID3 Analog-to-Digital Converter (ADC) ADC0 base: 0x4003.8000 ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000 (see page 622) ADCRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 623) INRDC INR0 ADCIM, type R/W, offset 0x008, reset 0x0000.0000 (see page 625) DCONSS3 DCONSS2 DCONSS1 DCONSS0 MASK3 MASK2 MASK1 MASK0 ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000 (see page 627) DCINSS3 DCINSS2 DCINSS1 DCINSS0 IN3 IN2 IN1 IN0 OV3 OV2 OV1 OV0 UV1 UV0 ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000 (see page 630) ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000 (see page 632) EM3 EM2 EM1 EM0 ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000 (see page 636) UV3 UV2 ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210 (see page 637) SS3 SS2 SS1 SS0 ADCSPC, type R/W, offset 0x024, reset 0x0000.0000 (see page 639) PHASE ADCPSSI, type R/W, offset 0x028, reset - (see page 640) SS3 SS2 SS1 SS0 ADCSAC, type R/W, offset 0x030, reset 0x0000.0000 (see page 642) AVG ADCDCISC, type R/W1C, offset 0x034, reset 0x0000.0000 (see page 643) DCINT7 DCINT6 DCINT5 930 DCINT4 DCINT3 DCINT2 DCINT1 DCINT0 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCCTL, type R/W, offset 0x038, reset 0x0000.0000 (see page 645) RES VREF ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000 (see page 646) MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000 (see page 648) TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 ADCSSFIFO0, type RO, offset 0x048, reset - (see page 651) DATA ADCSSFIFO1, type RO, offset 0x068, reset - (see page 651) DATA ADCSSFIFO2, type RO, offset 0x088, reset - (see page 651) DATA ADCSSFIFO3, type RO, offset 0x0A8, reset - (see page 651) DATA ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100 (see page 652) FULL EMPTY HPTR TPTR EMPTY HPTR TPTR EMPTY HPTR TPTR EMPTY HPTR TPTR ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100 (see page 652) FULL ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100 (see page 652) FULL ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100 (see page 652) FULL ADCSSOP0, type R/W, offset 0x050, reset 0x0000.0000 (see page 654) S7DCOP S6DCOP S5DCOP S4DCOP S3DCOP S2DCOP S1DCOP S0DCOP ADCSSDC0, type R/W, offset 0x054, reset 0x0000.0000 (see page 656) S7DCSEL S6DCSEL S5DCSEL S4DCSEL S3DCSEL S2DCSEL S1DCSEL S0DCSEL ADCSSMUX1, type R/W, offset 0x060, reset 0x0000.0000 (see page 658) MUX3 MUX2 MUX1 MUX0 MUX1 MUX0 ADCSSMUX2, type R/W, offset 0x080, reset 0x0000.0000 (see page 658) MUX3 MUX2 ADCSSCTL1, type R/W, offset 0x064, reset 0x0000.0000 (see page 659) TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 ADCSSCTL2, type R/W, offset 0x084, reset 0x0000.0000 (see page 659) TS3 IE3 END3 D3 TS2 IE2 END2 July 24, 2011 931 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCSSOP1, type R/W, offset 0x070, reset 0x0000.0000 (see page 661) S3DCOP S2DCOP S1DCOP S0DCOP S2DCOP S1DCOP S0DCOP ADCSSOP2, type R/W, offset 0x090, reset 0x0000.0000 (see page 661) S3DCOP ADCSSDC1, type R/W, offset 0x074, reset 0x0000.0000 (see page 662) S3DCSEL S2DCSEL S1DCSEL S0DCSEL S1DCSEL S0DCSEL ADCSSDC2, type R/W, offset 0x094, reset 0x0000.0000 (see page 662) S3DCSEL S2DCSEL ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 664) MUX0 ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002 (see page 665) TS0 IE0 END0 D0 ADCSSOP3, type R/W, offset 0x0B0, reset 0x0000.0000 (see page 666) S0DCOP ADCSSDC3, type R/W, offset 0x0B4, reset 0x0000.0000 (see page 667) S0DCSEL ADCDCRIC, type R/W, offset 0xD00, reset 0x0000.0000 (see page 668) DCTRIG7 DCTRIG6 DCTRIG5 DCTRIG4 DCTRIG3 DCTRIG2 DCTRIG1 DCTRIG0 DCINT7 DCINT6 DCINT5 DCINT4 DCINT3 DCINT2 DCINT1 DCINT0 ADCDCCTL0, type R/W, offset 0xE00, reset 0x0000.0000 (see page 673) CIE CIC CIM CIE CIC CIM CIE CIC CIM CIE CIC CIM CIE CIC CIM CIE CIC CIM CIE CIC CIM CIE CIC CIM ADCDCCTL1, type R/W, offset 0xE04, reset 0x0000.0000 (see page 673) ADCDCCTL2, type R/W, offset 0xE08, reset 0x0000.0000 (see page 673) ADCDCCTL3, type R/W, offset 0xE0C, reset 0x0000.0000 (see page 673) ADCDCCTL4, type R/W, offset 0xE10, reset 0x0000.0000 (see page 673) ADCDCCTL5, type R/W, offset 0xE14, reset 0x0000.0000 (see page 673) ADCDCCTL6, type R/W, offset 0xE18, reset 0x0000.0000 (see page 673) ADCDCCTL7, type R/W, offset 0xE1C, reset 0x0000.0000 (see page 673) 932 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OE BE PE FE BUSY DCD DSR CTS PEN BRK ADCDCCMP0, type R/W, offset 0xE40, reset 0x0000.0000 (see page 675) COMP1 COMP0 ADCDCCMP1, type R/W, offset 0xE44, reset 0x0000.0000 (see page 675) COMP1 COMP0 ADCDCCMP2, type R/W, offset 0xE48, reset 0x0000.0000 (see page 675) COMP1 COMP0 ADCDCCMP3, type R/W, offset 0xE4C, reset 0x0000.0000 (see page 675) COMP1 COMP0 ADCDCCMP4, type R/W, offset 0xE50, reset 0x0000.0000 (see page 675) COMP1 COMP0 ADCDCCMP5, type R/W, offset 0xE54, reset 0x0000.0000 (see page 675) COMP1 COMP0 ADCDCCMP6, type R/W, offset 0xE58, reset 0x0000.0000 (see page 675) COMP1 COMP0 ADCDCCMP7, type R/W, offset 0xE5C, reset 0x0000.0000 (see page 675) COMP1 COMP0 Universal Asynchronous Receivers/Transmitters (UARTs) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UARTDR, type R/W, offset 0x000, reset 0x0000.0000 (see page 691) OE BE PE FE DATA UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Read-Only Status Register) (see page 693) UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Write-Only Error Clear Register) (see page 693) DATA UARTFR, type RO, offset 0x018, reset 0x0000.0090 (see page 696) RI TXFE RXFF TXFF RXFE UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 (see page 699) ILPDVSR UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 (see page 700) DIVINT UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 (see page 701) DIVFRAC UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 (see page 702) SPS WLEN July 24, 2011 FEN STP2 EPS 933 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE TXE LBE LIN HSE EOT SMART SIRLP SIREN UARTEN UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 (see page 704) CTSEN RTSEN RTS DTR UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 (see page 708) RXIFLSEL TXIFLSEL UARTIM, type R/W, offset 0x038, reset 0x0000.0000 (see page 710) LME5IM LME1IM LMSBIM OEIM BEIM PEIM FEIM RTIM TXIM RXIM DSRIM DCDIM CTSIM RIIM PERIS FERIS RTRIS TXRIS RXRIS DSRRIS DCDRIS CTSRIS RIRIS PEMIS FEMIS RTMIS TXMIS RXMIS DSRMIS DCDMIS CTSMIS RIMIS PEIC FEIC RTIC TXIC RXIC DSRMIC DCDMIC CTSMIC RIMIC UARTRIS, type RO, offset 0x03C, reset 0x0000.000F (see page 714) LME5RIS LME1RIS LMSBRIS OERIS BERIS UARTMIS, type RO, offset 0x040, reset 0x0000.0000 (see page 717) LME5MIS LME1MIS LMSBMIS OEMIS BEMIS UARTICR, type W1C, offset 0x044, reset 0x0000.0000 (see page 720) LME5IC LME1IC LMSBIC OEIC BEIC UARTDMACTL, type R/W, offset 0x048, reset 0x0000.0000 (see page 722) DMAERR TXDMAE RXDMAE UARTLCTL, type R/W, offset 0x090, reset 0x0000.0000 (see page 723) BLEN MASTER UARTLSS, type RO, offset 0x094, reset 0x0000.0000 (see page 724) TSS UARTLTIM, type RO, offset 0x098, reset 0x0000.0000 (see page 725) TIMER UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 726) PID4 UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 727) PID5 UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 728) PID6 UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 729) PID7 UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0060 (see page 730) PID0 UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 731) PID1 UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 732) PID2 934 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 733) PID3 UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 734) CID0 UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 735) CID1 UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 736) CID2 UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 737) CID3 Synchronous Serial Interface (SSI) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 SSICR0, type R/W, offset 0x000, reset 0x0000.0000 (see page 753) SCR SPH SPO FRF DSS SSICR1, type R/W, offset 0x004, reset 0x0000.0000 (see page 755) EOT SOD MS SSE LBM BSY RFF RNE TNF TFE TXIM RXIM RTIM RORIM TXRIS RXRIS RTRIS RORRIS TXMIS RXMIS RTMIS RORMIS RTIC RORIC SSIDR, type R/W, offset 0x008, reset 0x0000.0000 (see page 757) DATA SSISR, type RO, offset 0x00C, reset 0x0000.0003 (see page 758) SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 (see page 760) CPSDVSR SSIIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 761) SSIRIS, type RO, offset 0x018, reset 0x0000.0008 (see page 762) SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 764) SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 766) SSIDMACTL, type R/W, offset 0x024, reset 0x0000.0000 (see page 767) TXDMAE RXDMAE SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 768) PID4 July 24, 2011 935 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 769) PID5 SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 770) PID6 SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 771) PID7 SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 (see page 772) PID0 SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 773) PID1 SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 774) PID2 SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 775) PID3 SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 776) CID0 SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 777) CID1 SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 778) CID2 SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 779) CID3 Inter-Integrated Circuit (I2C) Interface I2C Master I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2CMSA, type R/W, offset 0x000, reset 0x0000.0000 SA R/S I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Read-Only Status Register) BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY ACK STOP START RUN I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Write-Only Control Register) I2CMDR, type R/W, offset 0x008, reset 0x0000.0000 DATA I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001 TPR 936 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000 IM I2CMRIS, type RO, offset 0x014, reset 0x0000.0000 RIS I2CMMIS, type RO, offset 0x018, reset 0x0000.0000 MIS I2CMICR, type WO, offset 0x01C, reset 0x0000.0000 IC I2CMCR, type R/W, offset 0x020, reset 0x0000.0000 SFE Inter-Integrated Circuit (I2C) MFE LPBK Interface I2C Slave I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2CSOAR, type R/W, offset 0x800, reset 0x0000.0000 OAR I2CSCSR, type RO, offset 0x804, reset 0x0000.0000 (Read-Only Status Register) FBR TREQ RREQ I2CSCSR, type WO, offset 0x804, reset 0x0000.0000 (Write-Only Control Register) DA I2CSDR, type R/W, offset 0x808, reset 0x0000.0000 DATA I2CSIMR, type R/W, offset 0x80C, reset 0x0000.0000 STOPIM STARTIM DATAIM I2CSRIS, type RO, offset 0x810, reset 0x0000.0000 STOPRIS STARTRIS DATARIS I2CSMIS, type RO, offset 0x814, reset 0x0000.0000 STOPMIS STARTMIS DATAMIS I2CSICR, type WO, offset 0x818, reset 0x0000.0000 STOPIC STARTIC DATAIC IN1 IN0 IN1 IN0 Analog Comparators Base 0x4003.C000 ACMIS, type R/W1C, offset 0x000, reset 0x0000.0000 (see page 823) ACRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 824) July 24, 2011 937 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IN1 IN0 ACINTEN, type R/W, offset 0x008, reset 0x0000.0000 (see page 825) ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000 (see page 826) EN RNG VREF ACSTAT0, type RO, offset 0x020, reset 0x0000.0000 (see page 827) OVAL ACSTAT1, type RO, offset 0x040, reset 0x0000.0000 (see page 827) OVAL ACCTL0, type R/W, offset 0x024, reset 0x0000.0000 (see page 828) TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV TSLVAL TSEN ISLVAL ISEN CINV ACCTL1, type R/W, offset 0x044, reset 0x0000.0000 (see page 828) TOEN ASRCP 938 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller B Ordering and Contact Information B.1 Ordering Information LM3Snnnn–gppss–rrm Part Number nnn = Sandstorm-class parts nnnn = All other Stellaris® parts Shipping Medium T = Tape-and-reel Omitted = Default shipping (tray or tube) Temperature E = –40°C to +105°C I = –40°C to +85°C Revision Speed 20 = 20 MHz 25 = 25 MHz 50 = 50 MHz 80 = 80 MHz Package BZ = 108-ball BGA QC = 100-pin LQFP QN = 48-pin LQFP QR = 64-pin LQFP GZ = 48-pin QFN Table B-1. Part Ordering Information B.2 Orderable Part Number Description LM3S1F11-IQC80-A2 Stellaris LM3S1F11 Microcontroller Industrial Temperature 100-pin LQFP LM3S1F11-IBZ80-A2 Stellaris LM3S1F11 Microcontroller Industrial Temperature 108-ball BGA LM3S1F11-IQC80-A2T Stellaris LM3S1F11 Microcontroller Industrial Temperature 100-pin LQFP Tape-and-reel LM3S1F11-IBZ80-A2T Stellaris LM3S1F11 Microcontroller Industrial Temperature 108-ball BGA Tape-and-reel ® Part Markings The Stellaris microcontrollers are marked with an identifying number. This code contains the following information: ■ The first line indicates the part number. In the example figure below, this is the LM3S9B90. ■ In the second line, the first seven characters indicate the temperature, package, speed, and revision. In the example below, this is an Industrial temperature (I), 100-pin LQFP package (QC), 80-MHz (80), revision C0 (C0) device. ■ The remaining characters contain internal tracking numbers. July 24, 2011 939 Texas Instruments-Production Data Ordering and Contact Information B.3 Kits The Stellaris Family provides the hardware and software tools that engineers need to begin development quickly. ■ Reference Design Kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files ■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers before purchase ■ Development Kits provide you with all the tools you need to develop and prototype embedded applications right out of the box See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor. B.4 Support Information For support on Stellaris products, contact the TI Worldwide Product Information Center nearest you: http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm. 940 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller C Package Information C.1 100-Pin LQFP Package C.1.1 Package Dimensions Figure C-1. 100-Pin LQFP Package Dimensions Note: The following notes apply to the package drawing. 1. All dimensions shown in mm. 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane. July 24, 2011 941 Texas Instruments-Production Data Package Information Body +2.00 mm Footprint, 1.4 mm package thickness Symbols Leads 100L A Max. 1.60 A1 - 0.05 Min./0.15 Max. A2 ±0.05 1.40 D ±0.20 16.00 D1 ±0.05 14.00 E ±0.20 16.00 E1 ±0.05 14.00 L +0.15/-0.10 0.60 e Basic 0.50 b +0.05 0.22 θ - 0˚-7˚ ddd Max. 0.08 ccc Max. 0.08 JEDEC Reference Drawing MS-026 Variation Designator BED 942 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller C.1.2 Tray Dimensions Figure C-2. 100-Pin LQFP Tray Dimensions C.1.3 Tape and Reel Dimensions Note: In the figure that follows, pin 1 is located in the top right corner of the device. July 24, 2011 943 Texas Instruments-Production Data Package Information Figure C-3. 100-Pin LQFP Tape and Reel Dimensions THIS IS A COMPUTER GENERATED UNCONTROLLED DOCUMENT PRINTED ON 06.01.2003 06.01.2003 06.01.2003 MUST NOT BE REPRODUCED WITHOUT WRITTEN PERMISSION FROM SUMICARRIER (S) PTE LTD 06.01.2003 06.01.2003 944 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller C.2 108-Ball BGA Package C.2.1 Package Dimensions Figure C-4. 108-Ball BGA Package Dimensions July 24, 2011 945 Texas Instruments-Production Data Package Information Note: The following notes apply to the package drawing. Symbols MIN NOM MAX A 1.22 1.36 1.50 A1 0.29 0.34 0.39 A3 0.65 0.70 0.75 c 0.28 0.32 0.36 D 9.85 10.00 10.15 D1 E 8.80 BSC 9.85 E1 b 10.00 8.80 BSC 0.43 0.48 bbb 0.53 .20 ddd .12 e 0.80 BSC f 10.15 - 0.60 M 12 n 108 - REF: JEDEC MO-219F 946 July 24, 2011 Texas Instruments-Production Data ® Stellaris LM3S1F11 Microcontroller C.2.2 Tray Dimensions Figure C-5. 108-Ball BGA Tray Dimensions July 24, 2011 947 Texas Instruments-Production Data Package Information C.2.3 Tape and Reel Dimensions Figure C-6. 108-Ball BGA Tape and Reel Dimensions C-PAK PTE LTD 948 July 24, 2011 Texas Instruments-Production Data PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) LM3S1F11-IBZ50-A1 ACTIVE NFBGA ZCR 108 184 TBD Call TI Call TI LM3S1F11-IBZ50-A1T ACTIVE NFBGA ZCR 108 1500 TBD Call TI Call TI LM3S1F11-IBZ80-A2 PREVIEW NFBGA ZCR 108 184 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR LM3S1F11-IBZ80-A2T PREVIEW NFBGA ZCR 108 1500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR LM3S1F11-IQC50-A0 PREVIEW LQFP PZ 100 90 TBD Call TI Call TI LM3S1F11-IQC50-A0T PREVIEW LQFP PZ 100 1000 TBD Call TI Call TI LM3S1F11-IQC50-A1 ACTIVE LQFP PZ 100 90 TBD Call TI Call TI LM3S1F11-IQC50-A1T ACTIVE LQFP PZ 100 1000 TBD Call TI Call TI LM3S1F11-IQC80-A2 PREVIEW LQFP PZ 100 90 Green (RoHS & no Sb/Br) Level-3-260C-168 HR LM3S1F11-IQC80-A2T PREVIEW LQFP PZ 100 1000 Green (RoHS & no Sb/Br) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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