LM3S5732-IQR50-A0T

TE X AS I NS TRUM E NTS - P RO DUCTION D ATA ® Stellaris LM3S5732 Microcontroller D ATA SHE E T D S -LM3S 5732 - 1 5 8 5 2 . 2 7 4 3 S P M S 090H C o p yri g h t © 2 0 07-2014 Te xa s In stru me n ts In co rporated Copyright Copyright © 2007-2014 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare® are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm 2 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table of Contents Revision History ............................................................................................................................. 26 About This Document .................................................................................................................... 33 Audience .............................................................................................................................................. About This Manual ................................................................................................................................ Related Documents ............................................................................................................................... Documentation Conventions .................................................................................................................. 33 33 33 34 1 Architectural Overview .......................................................................................... 36 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 Product Features .......................................................................................................... Target Applications ........................................................................................................ High-Level Block Diagram ............................................................................................. Functional Overview ...................................................................................................... ARM Cortex™-M3 ......................................................................................................... Motor Control Peripherals .............................................................................................. Analog Peripherals ........................................................................................................ Serial Communications Peripherals ................................................................................ System Peripherals ....................................................................................................... Memory Peripherals ...................................................................................................... Additional Features ....................................................................................................... Hardware Details .......................................................................................................... 36 44 45 47 47 48 48 49 50 51 52 52 2 The Cortex-M3 Processor ...................................................................................... 53 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.5 2.5.1 2.5.2 2.5.3 Block Diagram .............................................................................................................. 54 Overview ...................................................................................................................... 55 System-Level Interface .................................................................................................. 55 Integrated Configurable Debug ...................................................................................... 55 Trace Port Interface Unit (TPIU) ..................................................................................... 56 Cortex-M3 System Component Details ........................................................................... 56 Programming Model ...................................................................................................... 57 Processor Mode and Privilege Levels for Software Execution ........................................... 57 Stacks .......................................................................................................................... 57 Register Map ................................................................................................................ 58 Register Descriptions .................................................................................................... 59 Exceptions and Interrupts .............................................................................................. 72 Data Types ................................................................................................................... 72 Memory Model .............................................................................................................. 72 Memory Regions, Types and Attributes ........................................................................... 74 Memory System Ordering of Memory Accesses .............................................................. 74 Behavior of Memory Accesses ....................................................................................... 74 Software Ordering of Memory Accesses ......................................................................... 75 Bit-Banding ................................................................................................................... 76 Data Storage ................................................................................................................ 78 Synchronization Primitives ............................................................................................. 79 Exception Model ........................................................................................................... 80 Exception States ........................................................................................................... 81 Exception Types ............................................................................................................ 81 Exception Handlers ....................................................................................................... 84 July 17, 2014 3 Texas Instruments-Production Data Table of Contents 2.5.4 2.5.5 2.5.6 2.5.7 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.7.1 2.7.2 2.8 Vector Table .................................................................................................................. 84 Exception Priorities ....................................................................................................... 85 Interrupt Priority Grouping .............................................................................................. 86 Exception Entry and Return ........................................................................................... 86 Fault Handling .............................................................................................................. 88 Fault Types ................................................................................................................... 89 Fault Escalation and Hard Faults .................................................................................... 89 Fault Status Registers and Fault Address Registers ........................................................ 90 Lockup ......................................................................................................................... 90 Power Management ...................................................................................................... 90 Entering Sleep Modes ................................................................................................... 91 Wake Up from Sleep Mode ............................................................................................ 91 Instruction Set Summary ............................................................................................... 92 3 Cortex-M3 Peripherals ........................................................................................... 95 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.3 3.4 3.5 3.6 Functional Description ................................................................................................... 95 System Timer (SysTick) ................................................................................................. 95 Nested Vectored Interrupt Controller (NVIC) .................................................................... 96 System Control Block (SCB) .......................................................................................... 98 Memory Protection Unit (MPU) ....................................................................................... 98 Register Map .............................................................................................................. 103 System Timer (SysTick) Register Descriptions .............................................................. 105 NVIC Register Descriptions .......................................................................................... 109 System Control Block (SCB) Register Descriptions ........................................................ 122 Memory Protection Unit (MPU) Register Descriptions .................................................... 149 4 JTAG Interface ...................................................................................................... 159 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.5 4.5.1 4.5.2 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. JTAG Interface Pins ..................................................................................................... JTAG TAP Controller ................................................................................................... Shift Registers ............................................................................................................ Operational Considerations .......................................................................................... Initialization and Configuration ..................................................................................... Register Descriptions .................................................................................................. Instruction Register (IR) ............................................................................................... Data Registers ............................................................................................................ 160 160 161 161 162 163 163 166 166 167 169 5 System Control ..................................................................................................... 171 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 5.4 5.5 Signal Description ....................................................................................................... Functional Description ................................................................................................. Device Identification .................................................................................................... Reset Control .............................................................................................................. Non-Maskable Interrupt ............................................................................................... Power Control ............................................................................................................. Clock Control .............................................................................................................. System Control ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 4 171 171 171 171 175 176 176 182 183 183 185 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 6 Hibernation Module .............................................................................................. 238 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 6.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Register Access Timing ............................................................................................... Clock Source .............................................................................................................. Battery Management ................................................................................................... Real-Time Clock .......................................................................................................... Battery-Backed Memory .............................................................................................. Power Control ............................................................................................................. Initiating Hibernate ...................................................................................................... Interrupts and Status ................................................................................................... Initialization and Configuration ..................................................................................... Initialization ................................................................................................................. RTC Match Functionality (No Hibernation) .................................................................... RTC Match/Wake-Up from Hibernation ......................................................................... External Wake-Up from Hibernation .............................................................................. RTC/External Wake-Up from Hibernation ...................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 239 239 240 240 240 242 242 242 243 243 243 244 244 244 244 245 245 245 246 7 Internal Memory ................................................................................................... 260 7.1 7.2 7.2.1 7.2.2 7.2.3 7.3 7.3.1 7.3.2 7.4 7.5 7.6 7.7 Block Diagram ............................................................................................................ 260 Functional Description ................................................................................................. 260 SRAM Memory ............................................................................................................ 260 ROM Memory ............................................................................................................. 261 Flash Memory ............................................................................................................. 261 Flash Memory Initialization and Configuration ............................................................... 264 Flash Programming ..................................................................................................... 264 Nonvolatile Register Programming ............................................................................... 264 Register Map .............................................................................................................. 265 ROM Register Descriptions (System Control Offset) ...................................................... 266 Flash Register Descriptions (Flash Control Offset) ......................................................... 267 Flash Register Descriptions (System Control Offset) ...................................................... 275 8 Micro Direct Memory Access (μDMA) ................................................................ 290 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.3 8.3.1 Block Diagram ............................................................................................................ 291 Functional Description ................................................................................................. 291 Channel Assigments .................................................................................................... 292 Priority ........................................................................................................................ 292 Arbitration Size ............................................................................................................ 292 Request Types ............................................................................................................ 293 Channel Configuration ................................................................................................. 293 Transfer Modes ........................................................................................................... 295 Transfer Size and Increment ........................................................................................ 303 Peripheral Interface ..................................................................................................... 303 Software Request ........................................................................................................ 303 Interrupts and Errors .................................................................................................... 304 Initialization and Configuration ..................................................................................... 304 Module Initialization ..................................................................................................... 304 July 17, 2014 5 Texas Instruments-Production Data Table of Contents 8.3.2 8.3.3 8.3.4 8.4 8.5 8.6 Configuring a Memory-to-Memory Transfer ................................................................... Configuring a Peripheral for Simple Transmit ................................................................ Configuring a Peripheral for Ping-Pong Receive ............................................................ Register Map .............................................................................................................. μDMA Channel Control Structure ................................................................................. μDMA Register Descriptions ........................................................................................ 304 306 307 310 311 317 9 General-Purpose Input/Outputs (GPIOs) ........................................................... 351 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.3 9.4 9.5 Signal Description ....................................................................................................... 351 Functional Description ................................................................................................. 354 Data Control ............................................................................................................... 355 Interrupt Control .......................................................................................................... 356 Mode Control .............................................................................................................. 357 Commit Control ........................................................................................................... 357 Pad Control ................................................................................................................. 357 Identification ............................................................................................................... 358 Initialization and Configuration ..................................................................................... 358 Register Map .............................................................................................................. 359 Register Descriptions .................................................................................................. 361 10 General-Purpose Timers ...................................................................................... 399 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.5 10.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. GPTM Reset Conditions .............................................................................................. 32-Bit Timer Operating Modes ...................................................................................... 16-Bit Timer Operating Modes ...................................................................................... Initialization and Configuration ..................................................................................... 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 16-Bit Input Edge Count Mode ..................................................................................... 16-Bit Input Edge Timing Mode .................................................................................... 16-Bit PWM Mode ....................................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 400 400 401 401 401 403 406 406 407 407 408 408 409 409 410 11 Watchdog Timer ................................................................................................... 433 11.1 11.2 11.3 11.4 11.5 Block Diagram ............................................................................................................ Functional Description ................................................................................................. Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 434 434 435 435 436 12 Analog-to-Digital Converter (ADC) ..................................................................... 457 12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 Block Diagram ............................................................................................................ 457 Signal Description ....................................................................................................... 458 Functional Description ................................................................................................. 458 Sample Sequencers .................................................................................................... 459 Module Control ............................................................................................................ 459 Hardware Sample Averaging Circuit ............................................................................. 460 6 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 12.3.4 12.3.5 12.3.6 12.4 12.4.1 12.4.2 12.5 12.6 Analog-to-Digital Converter .......................................................................................... Differential Sampling ................................................................................................... Internal Temperature Sensor ........................................................................................ Initialization and Configuration ..................................................................................... Module Initialization ..................................................................................................... Sample Sequencer Configuration ................................................................................. Register Map .............................................................................................................. Register Descriptions .................................................................................................. 460 461 463 464 464 464 465 466 13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 492 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.3.8 13.3.9 13.4 13.5 13.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Transmit/Receive Logic ............................................................................................... Baud-Rate Generation ................................................................................................. Data Transmission ...................................................................................................... Serial IR (SIR) ............................................................................................................. FIFO Operation ........................................................................................................... Interrupts .................................................................................................................... Loopback Operation .................................................................................................... DMA Operation ........................................................................................................... IrDA SIR block ............................................................................................................ Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 493 493 494 494 494 495 495 496 497 498 498 498 499 499 501 14 Synchronous Serial Interface (SSI) .................................................................... 536 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.4 14.5 14.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Bit Rate Generation ..................................................................................................... FIFO Operation ........................................................................................................... Interrupts .................................................................................................................... Frame Formats ........................................................................................................... DMA Operation ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 15 Inter-Integrated Circuit (I2C) Interface ................................................................ 576 15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.4 15.5 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. I2C Bus Functional Overview ........................................................................................ Available Speed Modes ............................................................................................... Interrupts .................................................................................................................... Loopback Operation .................................................................................................... Command Sequence Flow Charts ................................................................................ Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. July 17, 2014 537 537 538 538 538 539 539 547 547 548 549 577 577 577 578 580 581 581 582 589 590 7 Texas Instruments-Production Data Table of Contents 15.6 15.7 Register Descriptions (I2C Master) ............................................................................... 591 Register Descriptions (I2C Slave) ................................................................................. 604 16 Controller Area Network (CAN) Module ............................................................. 613 16.1 Block Diagram ............................................................................................................ 614 16.2 Signal Description ....................................................................................................... 614 16.3 Functional Description ................................................................................................. 615 16.3.1 Initialization ................................................................................................................. 616 16.3.2 Operation ................................................................................................................... 616 16.3.3 Transmitting Message Objects ..................................................................................... 617 16.3.4 Configuring a Transmit Message Object ........................................................................ 617 16.3.5 Updating a Transmit Message Object ........................................................................... 619 16.3.6 Accepting Received Message Objects .......................................................................... 619 16.3.7 Receiving a Data Frame .............................................................................................. 619 16.3.8 Receiving a Remote Frame .......................................................................................... 620 16.3.9 Receive/Transmit Priority ............................................................................................. 620 16.3.10 Configuring a Receive Message Object ........................................................................ 620 16.3.11 Handling of Received Message Objects ........................................................................ 621 16.3.12 Handling of Interrupts .................................................................................................. 624 16.3.13 Test Mode ................................................................................................................... 624 16.3.14 Bit Timing Configuration Error Considerations ............................................................... 626 16.3.15 Bit Time and Bit Rate ................................................................................................... 626 16.3.16 Calculating the Bit Timing Parameters .......................................................................... 628 16.4 Register Map .............................................................................................................. 631 16.5 CAN Register Descriptions .......................................................................................... 633 17 Universal Serial Bus (USB) Controller ............................................................... 659 17.1 17.2 17.3 17.3.1 17.3.2 17.3.3 17.4 17.4.1 17.4.2 17.5 17.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Operation as a Device ................................................................................................. Operation as a Host .................................................................................................... DMA Operation ........................................................................................................... Initialization and Configuration ..................................................................................... Pin Configuration ......................................................................................................... Endpoint Configuration ................................................................................................ Register Map .............................................................................................................. Register Descriptions .................................................................................................. 18 Pin Diagram .......................................................................................................... 753 660 660 660 661 666 670 671 671 671 672 675 19 Signal Tables ........................................................................................................ 754 19.1 19.2 19.3 19.4 19.5 Signals by Pin Number ................................................................................................ 754 Signals by Signal Name ............................................................................................... 757 Signals by Function, Except for GPIO ........................................................................... 760 GPIO Pins and Alternate Functions .............................................................................. 762 Connections for Unused Signals ................................................................................... 763 20 Operating Characteristics ................................................................................... 765 21 Electrical Characteristics .................................................................................... 766 21.1 DC Characteristics ...................................................................................................... 766 21.1.1 Maximum Ratings ....................................................................................................... 766 8 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 21.1.2 Recommended DC Operating Conditions ...................................................................... 766 21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 767 21.1.4 GPIO Module Characteristics ....................................................................................... 767 21.1.5 Power Specifications ................................................................................................... 767 21.1.6 Flash Memory Characteristics ...................................................................................... 769 21.1.7 Hibernation ................................................................................................................. 769 21.1.8 USB ........................................................................................................................... 769 21.2 AC Characteristics ....................................................................................................... 770 21.2.1 Load Conditions .......................................................................................................... 770 21.2.2 Clocks ........................................................................................................................ 770 21.2.3 JTAG and Boundary Scan ............................................................................................ 772 21.2.4 Reset ......................................................................................................................... 773 21.2.5 Sleep Modes ............................................................................................................... 775 21.2.6 Hibernation Module ..................................................................................................... 775 21.2.7 General-Purpose I/O (GPIO) ........................................................................................ 775 21.2.8 Analog-to-Digital Converter .......................................................................................... 776 21.2.9 Synchronous Serial Interface (SSI) ............................................................................... 777 21.2.10 Inter-Integrated Circuit (I2C) Interface ........................................................................... 779 21.2.11 Universal Serial Bus (USB) Controller ........................................................................... 780 A Boot Loader .......................................................................................................... 781 A.1 A.2 A.2.1 A.2.2 A.2.3 A.3 A.3.1 A.3.2 A.3.3 A.4 A.4.1 A.4.2 A.4.3 A.4.4 A.4.5 A.4.6 Boot Loader ................................................................................................................ Interfaces ................................................................................................................... UART ......................................................................................................................... SSI ............................................................................................................................. I2C ............................................................................................................................. Packet Handling .......................................................................................................... Packet Format ............................................................................................................ Sending Packets ......................................................................................................... Receiving Packets ....................................................................................................... Commands ................................................................................................................. COMMAND_PING (0X20) ............................................................................................ COMMAND_DOWNLOAD (0x21) ................................................................................. COMMAND_RUN (0x22) ............................................................................................. COMMAND_GET_STATUS (0x23) ............................................................................... COMMAND_SEND_DATA (0x24) ................................................................................. COMMAND_RESET (0x25) ......................................................................................... 781 781 781 782 782 782 782 782 783 783 783 783 784 784 784 785 B ROM DriverLib Functions .................................................................................... 786 B.1 DriverLib Functions Included in the Integrated ROM ...................................................... 786 C Register Quick Reference ................................................................................... 797 D Ordering and Contact Information ..................................................................... 826 D.1 D.2 D.3 D.4 Ordering Information .................................................................................................... 826 Part Markings .............................................................................................................. 826 Kits ............................................................................................................................. 826 Support Information ..................................................................................................... 827 E Package Information ............................................................................................ 828 E.1 E.1.1 64-Pin LQFP Package ................................................................................................. 828 Package Dimensions ................................................................................................... 828 July 17, 2014 9 Texas Instruments-Production Data Table of Contents E.1.2 E.1.3 Tray Dimensions ......................................................................................................... 830 Tape and Reel Dimensions .......................................................................................... 831 10 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 6-1. Figure 6-2. Figure 6-3. Figure 7-1. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 8-5. Figure 8-6. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 11-1. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 13-1. Figure 13-2. Figure 13-3. Figure 14-1. Stellaris LM3S5732 Microcontroller High-Level Block Diagram ............................... 46 CPU Block Diagram ............................................................................................. 55 TPIU Block Diagram ............................................................................................ 56 Cortex-M3 Register Set ........................................................................................ 58 Bit-Band Mapping ................................................................................................ 78 Data Storage ....................................................................................................... 79 Vector Table ........................................................................................................ 85 Exception Stack Frame ........................................................................................ 87 SRD Use Example ............................................................................................. 101 JTAG Module Block Diagram .............................................................................. 160 Test Access Port State Machine ......................................................................... 163 IDCODE Register Format ................................................................................... 169 BYPASS Register Format ................................................................................... 169 Boundary Scan Register Format ......................................................................... 170 Basic RST Configuration .................................................................................... 173 External Circuitry to Extend Power-On Reset ....................................................... 173 Reset Circuit Controlled by Switch ...................................................................... 174 Main Clock Tree ................................................................................................ 178 Hibernation Module Block Diagram ..................................................................... 239 Clock Source Using Crystal ................................................................................ 241 Clock Source Using Dedicated Oscillator ............................................................. 241 Flash Block Diagram .......................................................................................... 260 μDMA Block Diagram ......................................................................................... 291 Example of Ping-Pong DMA Transaction ............................................................. 296 Memory Scatter-Gather, Setup and Configuration ................................................ 298 Memory Scatter-Gather, μDMA Copy Sequence .................................................. 299 Peripheral Scatter-Gather, Setup and Configuration ............................................. 301 Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 302 Digital I/O Pads ................................................................................................. 354 Analog/Digital I/O Pads ...................................................................................... 355 GPIODATA Write Example ................................................................................. 356 GPIODATA Read Example ................................................................................. 356 GPTM Module Block Diagram ............................................................................ 400 16-Bit Input Edge Count Mode Example .............................................................. 404 16-Bit Input Edge Time Mode Example ............................................................... 405 16-Bit PWM Mode Example ................................................................................ 406 WDT Module Block Diagram .............................................................................. 434 ADC Module Block Diagram ............................................................................... 458 Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 462 Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 462 Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 463 Internal Temperature Sensor Characteristic ......................................................... 464 UART Module Block Diagram ............................................................................. 493 UART Character Frame ..................................................................................... 494 IrDA Data Modulation ......................................................................................... 496 SSI Module Block Diagram ................................................................................. 537 July 17, 2014 11 Texas Instruments-Production Data Table of Contents Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 14-6. Figure 14-7. Figure 14-8. Figure 14-9. Figure 14-10. Figure 14-11. Figure 14-12. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 15-5. Figure 15-6. Figure 15-7. Figure 15-8. Figure 15-9. Figure 15-10. Figure 15-11. Figure 15-12. Figure 15-13. Figure 16-1. Figure 16-2. Figure 16-3. Figure 16-4. Figure 17-1. Figure 18-1. Figure 21-1. Figure 21-2. Figure 21-3. Figure 21-4. Figure 21-5. Figure 21-6. Figure 21-7. Figure 21-8. Figure 21-9. Figure 21-10. Figure 21-11. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 540 TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 541 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 541 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 542 Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 543 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 543 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 544 Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 545 MICROWIRE Frame Format (Single Frame) ........................................................ 545 MICROWIRE Frame Format (Continuous Transfer) ............................................. 546 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 547 I2C Block Diagram ............................................................................................. 577 I2C Bus Configuration ........................................................................................ 578 START and STOP Conditions ............................................................................. 578 Complete Data Transfer with a 7-Bit Address ....................................................... 579 R/S Bit in First Byte ............................................................................................ 579 Data Validity During Bit Transfer on the I2C Bus ................................................... 579 Master Single SEND .......................................................................................... 583 Master Single RECEIVE ..................................................................................... 584 Master Burst SEND ........................................................................................... 585 Master Burst RECEIVE ...................................................................................... 586 Master Burst RECEIVE after Burst SEND ............................................................ 587 Master Burst SEND after Burst RECEIVE ............................................................ 588 Slave Command Sequence ................................................................................ 589 CAN Controller Block Diagram ............................................................................ 614 CAN Data/Remote Frame .................................................................................. 615 Message Objects in a FIFO Buffer ...................................................................... 623 CAN Bit Time .................................................................................................... 627 USB Module Block Diagram ............................................................................... 660 64-Pin LQFP Package Pin Diagram .................................................................... 753 Load Conditions ................................................................................................ 770 JTAG Test Clock Input Timing ............................................................................. 772 JTAG Test Access Port (TAP) Timing .................................................................. 773 External Reset Timing (RST) .............................................................................. 773 Power-On Reset Timing ..................................................................................... 774 Brown-Out Reset Timing .................................................................................... 774 Software Reset Timing ....................................................................................... 774 Watchdog Reset Timing ..................................................................................... 774 Hibernation Module Timing ................................................................................. 775 ADC Input Equivalency Diagram ......................................................................... 777 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................... 778 Figure 21-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 778 Figure 21-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 779 Figure 21-14. I2C Timing ......................................................................................................... 780 Figure E-1. Stellaris LM3S5732 64-Pin LQFP Package .......................................................... 828 Figure E-2. 64-Pin LQFP Tray Dimensions ........................................................................... 830 Figure E-3. 64-Pin LQFP Tape and Reel Dimensions ............................................................. 831 12 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller List of Tables Table 1. Table 2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 4-1. Table 4-2. Table 4-3. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 6-1. Table 6-2. Table 7-1. Table 7-2. Table 7-3. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table 8-7. Revision History .................................................................................................. 26 Documentation Conventions ................................................................................ 34 Summary of Processor Mode, Privilege Level, and Stack Use ................................ 58 Processor Register Map ....................................................................................... 59 PSR Register Combinations ................................................................................. 64 Memory Map ....................................................................................................... 72 Memory Access Behavior ..................................................................................... 74 SRAM Memory Bit-Banding Regions .................................................................... 77 Peripheral Memory Bit-Banding Regions ............................................................... 77 Exception Types .................................................................................................. 82 Interrupts ............................................................................................................ 83 Exception Return Behavior ................................................................................... 88 Faults ................................................................................................................. 89 Fault Status and Fault Address Registers .............................................................. 90 Cortex-M3 Instruction Summary ........................................................................... 92 Core Peripheral Register Regions ......................................................................... 95 Memory Attributes Summary ................................................................................ 98 TEX, S, C, and B Bit Field Encoding ................................................................... 101 Cache Policy for Memory Attribute Encoding ....................................................... 102 AP Bit Field Encoding ........................................................................................ 102 Memory Region Attributes for Stellaris Microcontrollers ........................................ 102 Peripherals Register Map ................................................................................... 103 Interrupt Priority Levels ...................................................................................... 128 Example SIZE Field Values ................................................................................ 156 JTAG_SWD_SWO Signals (64LQFP) ................................................................. 160 JTAG Port Pins Reset State ............................................................................... 161 JTAG Instruction Register Commands ................................................................. 167 System Control & Clocks Signals (64LQFP) ........................................................ 171 Reset Sources ................................................................................................... 172 Clock Source Options ........................................................................................ 177 Possible System Clock Frequencies Using the SYSDIV Field ............................... 179 Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 179 System Control Register Map ............................................................................. 183 RCC2 Fields that Override RCC fields ................................................................. 201 Hibernate Signals (64LQFP) ............................................................................... 239 Hibernation Module Register Map ....................................................................... 245 Flash Protection Policy Combinations ................................................................. 262 User-Programmable Flash Memory Resident Registers ....................................... 265 Flash Register Map ............................................................................................ 265 DMA Channel Assignments ............................................................................... 292 Request Type Support ....................................................................................... 293 Control Structure Memory Map ........................................................................... 294 Channel Control Structure .................................................................................. 294 μDMA Read Example: 8-Bit Peripheral ................................................................ 303 μDMA Interrupt Assignments .............................................................................. 304 Channel Control Structure Offsets for Channel 30 ................................................ 305 July 17, 2014 13 Texas Instruments-Production Data Table of Contents Table 8-8. Table 8-9. Table 8-10. Table 8-11. Table 8-12. Table 8-13. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 10-1. Table 10-2. Table 10-3. Table 10-4. Table 11-1. Table 12-1. Table 12-2. Table 12-3. Table 12-4. Table 13-1. Table 13-2. Table 14-1. Table 14-2. Table 15-1. Table 15-2. Table 15-3. Table 15-4. Table 16-1. Table 16-2. Table 16-3. Table 16-4. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 17-5. Table 19-1. Table 19-2. Table 19-3. Table 19-4. Table 19-5. Table 20-1. Table 20-2. Table 20-3. Table 21-1. Channel Control Word Configuration for Memory Transfer Example ...................... 305 Channel Control Structure Offsets for Channel 7 .................................................. 306 Channel Control Word Configuration for Peripheral Transmit Example .................. 307 Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 308 Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............................................................................................................ 309 μDMA Register Map .......................................................................................... 310 GPIO Pins With Non-Zero Reset Values .............................................................. 352 GPIO Pins and Alternate Functions (64LQFP) ..................................................... 352 GPIO Signals (64LQFP) ..................................................................................... 353 GPIO Pad Configuration Examples ..................................................................... 358 GPIO Interrupt Configuration Example ................................................................ 359 GPIO Register Map ........................................................................................... 360 Available CCP Pins ............................................................................................ 400 General-Purpose Timers Signals (64LQFP) ......................................................... 401 16-Bit Timer With Prescaler Configurations ......................................................... 403 Timers Register Map .......................................................................................... 410 Watchdog Timer Register Map ............................................................................ 435 ADC Signals (64LQFP) ...................................................................................... 458 Samples and FIFO Depth of Sequencers ............................................................ 459 Differential Sampling Pairs ................................................................................. 461 ADC Register Map ............................................................................................. 465 UART Signals (64LQFP) .................................................................................... 493 UART Register Map ........................................................................................... 500 SSI Signals (64LQFP) ........................................................................................ 538 SSI Register Map .............................................................................................. 549 I2C Signals (64LQFP) ........................................................................................ 577 Examples of I2C Master Timer Period versus Speed Mode ................................... 580 Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 590 Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 595 Controller Area Network Signals (64LQFP) .......................................................... 614 CAN Protocol Ranges ........................................................................................ 627 CANBIT Register Values .................................................................................... 627 CAN Register Map ............................................................................................. 631 USB Signals (64LQFP) ...................................................................................... 660 Remainder (MAXLOAD/4) .................................................................................. 670 Actual Bytes Read ............................................................................................. 670 Packet Sizes That Clear RXRDY ........................................................................ 670 Universal Serial Bus (USB) Controller Register Map ............................................ 672 Signals by Pin Number ....................................................................................... 754 Signals by Signal Name ..................................................................................... 757 Signals by Function, Except for GPIO ................................................................. 760 GPIO Pins and Alternate Functions ..................................................................... 762 Connections for Unused Signals (64-pin LQFP) ................................................... 763 Temperature Characteristics ............................................................................... 765 Thermal Characteristics ..................................................................................... 765 ESD Absolute Maximum Ratings ........................................................................ 765 Maximum Ratings .............................................................................................. 766 14 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 21-2. Table 21-3. Table 21-4. Table 21-5. Table 21-6. Table 21-7. Table 21-8. Table 21-9. Table 21-10. Table 21-11. Table 21-12. Table 21-13. Table 21-14. Table 21-15. Table 21-16. Table 21-17. Table 21-18. Table 21-19. Table 21-20. Table 21-21. Table 21-22. Table 21-23. Recommended DC Operating Conditions ............................................................ 766 LDO Regulator Characteristics ........................................................................... 767 GPIO Module DC Characteristics ........................................................................ 767 Detailed Power Specifications ............................................................................ 768 Flash Memory Characteristics ............................................................................ 769 Hibernation Module DC Characteristics ............................................................... 769 USB Controller DC Characteristics ...................................................................... 769 Phase Locked Loop (PLL) Characteristics ........................................................... 770 Actual PLL Frequency ........................................................................................ 770 Clock Characteristics ......................................................................................... 771 Crystal Characteristics ....................................................................................... 771 System Clock Characteristics with ADC Operation ............................................... 771 System Clock Characteristics with USB Operation ............................................... 772 JTAG Characteristics ......................................................................................... 772 Reset Characteristics ......................................................................................... 773 Sleep Modes AC Characteristics ......................................................................... 775 Hibernation Module AC Characteristics ............................................................... 775 GPIO Characteristics ......................................................................................... 776 ADC Characteristics ........................................................................................... 776 ADC Module Internal Reference Characteristics .................................................. 777 SSI Characteristics ............................................................................................ 777 I2C Characteristics ............................................................................................. 779 July 17, 2014 15 Texas Instruments-Production Data Table of Contents List of Registers The Cortex-M3 Processor ............................................................................................................. 53 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Cortex General-Purpose Register 0 (R0) ........................................................................... 60 Cortex General-Purpose Register 1 (R1) ........................................................................... 60 Cortex General-Purpose Register 2 (R2) ........................................................................... 60 Cortex General-Purpose Register 3 (R3) ........................................................................... 60 Cortex General-Purpose Register 4 (R4) ........................................................................... 60 Cortex General-Purpose Register 5 (R5) ........................................................................... 60 Cortex General-Purpose Register 6 (R6) ........................................................................... 60 Cortex General-Purpose Register 7 (R7) ........................................................................... 60 Cortex General-Purpose Register 8 (R8) ........................................................................... 60 Cortex General-Purpose Register 9 (R9) ........................................................................... 60 Cortex General-Purpose Register 10 (R10) ....................................................................... 60 Cortex General-Purpose Register 11 (R11) ........................................................................ 60 Cortex General-Purpose Register 12 (R12) ....................................................................... 60 Stack Pointer (SP) ........................................................................................................... 61 Link Register (LR) ............................................................................................................ 62 Program Counter (PC) ..................................................................................................... 63 Program Status Register (PSR) ........................................................................................ 64 Priority Mask Register (PRIMASK) .................................................................................... 68 Fault Mask Register (FAULTMASK) .................................................................................. 69 Base Priority Mask Register (BASEPRI) ............................................................................ 70 Control Register (CONTROL) ........................................................................................... 71 Cortex-M3 Peripherals ................................................................................................................... 95 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 106 SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 108 SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 109 Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 110 Interrupt 32-47 Set Enable (EN1), offset 0x104 ................................................................ 111 Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 112 Interrupt 32-47 Clear Enable (DIS1), offset 0x184 ............................................................ 113 Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 114 Interrupt 32-47 Set Pending (PEND1), offset 0x204 ......................................................... 115 Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 116 Interrupt 32-47 Clear Pending (UNPEND1), offset 0x284 .................................................. 117 Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 118 Interrupt 32-47 Active Bit (ACTIVE1), offset 0x304 ........................................................... 119 Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 120 Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 120 Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 120 Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 120 Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 120 Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 120 Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 120 Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 120 Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 120 16 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 120 Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 120 Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 120 Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 122 CPU ID Base (CPUID), offset 0xD00 ............................................................................... 123 Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 124 Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 127 Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 128 System Control (SYSCTRL), offset 0xD10 ....................................................................... 130 Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 132 System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 134 System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 135 System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 136 System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 137 Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 141 Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 147 Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 148 Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 149 MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 150 MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 151 MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 153 MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 154 MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 154 MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 154 MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 154 MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 156 MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 156 MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 156 MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 156 System Control ............................................................................................................................ 171 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Device Identification 0 (DID0), offset 0x000 ..................................................................... 186 Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 188 LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 189 Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 190 Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 191 Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 192 Reset Cause (RESC), offset 0x05C ................................................................................ 193 Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 194 XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 198 GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 199 Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 201 Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 203 Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 204 Device Identification 1 (DID1), offset 0x004 ..................................................................... 205 Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 207 Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 208 Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 210 Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 211 July 17, 2014 17 Texas Instruments-Production Data Table of Contents Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 212 Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 213 Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 214 Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 215 Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 217 Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 219 Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 221 Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 223 Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 225 Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 227 Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 229 Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 231 Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 233 Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 235 Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 236 Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 237 Hibernation Module ..................................................................................................................... 238 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... Hibernation Control (HIBCTL), offset 0x010 ..................................................................... Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 247 248 249 250 251 254 255 256 257 258 259 Internal Memory ........................................................................................................................... 260 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 267 Flash Memory Address (FMA), offset 0x000 .................................................................... 268 Flash Memory Data (FMD), offset 0x004 ......................................................................... 269 Flash Memory Control (FMC), offset 0x008 ..................................................................... 270 Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 272 Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 273 Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 274 USec Reload (USECRL), offset 0x140 ............................................................................ 276 Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 277 Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 278 User Debug (USER_DBG), offset 0x1D0 ......................................................................... 279 User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 280 User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 281 User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 282 User Register 3 (USER_REG3), offset 0x1EC ................................................................. 283 Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 284 Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 285 Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 286 Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 287 18 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 20: Register 21: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 288 Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 289 Micro Direct Memory Access (μDMA) ........................................................................................ 290 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 312 DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 313 DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 314 DMA Status (DMASTAT), offset 0x000 ............................................................................ 318 DMA Configuration (DMACFG), offset 0x004 ................................................................... 320 DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 321 DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 322 DMA Channel Wait on Request Status (DMAWAITSTAT), offset 0x010 ............................. 323 DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 324 DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 325 DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 327 DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 328 DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 330 DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 331 DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 333 DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 334 DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 336 DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 337 DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 339 DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 340 DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 342 DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 343 DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 344 DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 345 DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 346 DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 347 DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 348 DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 349 DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 350 General-Purpose Input/Outputs (GPIOs) ................................................................................... 351 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 362 GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 363 GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 364 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 365 GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 366 GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 367 GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 368 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 369 GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 370 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 371 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 373 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 374 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 375 GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 376 GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 377 July 17, 2014 19 Texas Instruments-Production Data Table of Contents Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 379 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 380 GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 381 GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 383 GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 384 GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 386 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 387 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 388 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 389 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 390 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 391 GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 392 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 393 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 394 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 395 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 396 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 397 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 398 General-Purpose Timers ............................................................................................................. 399 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 411 GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 412 GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 414 GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 416 GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 419 GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 421 GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 422 GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 423 GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 425 GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 426 GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 427 GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 428 GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 429 GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 430 GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 431 GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 432 Watchdog Timer ........................................................................................................................... 433 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 437 Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 438 Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 439 Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 440 Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 441 Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 442 Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 443 Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 444 Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 445 Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 446 Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 447 Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 448 20 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 449 450 451 452 453 454 455 456 Analog-to-Digital Converter (ADC) ............................................................................................. 457 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 467 ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 468 ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 469 ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 470 ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 471 ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 472 ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 475 ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 476 ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 478 ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 479 ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 480 ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 482 ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 485 ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 485 ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 485 ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 485 ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 486 ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 486 ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 486 ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 486 ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 487 ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 487 ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 488 ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 488 ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 490 ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 491 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 492 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: UART Data (UARTDR), offset 0x000 ............................................................................... 502 UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 504 UART Flag (UARTFR), offset 0x018 ................................................................................ 506 UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 508 UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 509 UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 510 UART Line Control (UARTLCRH), offset 0x02C ............................................................... 511 UART Control (UARTCTL), offset 0x030 ......................................................................... 513 UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 515 UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 517 UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 519 UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 520 July 17, 2014 21 Texas Instruments-Production Data Table of Contents Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 521 UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 523 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 524 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 525 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 526 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 527 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 528 UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 529 UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 530 UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 531 UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 532 UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 533 UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 534 UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 535 Synchronous Serial Interface (SSI) ............................................................................................ 536 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 550 SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 552 SSI Data (SSIDR), offset 0x008 ...................................................................................... 554 SSI Status (SSISR), offset 0x00C ................................................................................... 555 SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 557 SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 558 SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 560 SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 561 SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 562 SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 563 SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 564 SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 565 SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 566 SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 567 SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 568 SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 569 SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 570 SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 571 SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 572 SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 573 SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 574 SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 575 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 576 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 592 I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 593 I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 597 I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 598 I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 599 I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 600 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 601 I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 602 I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 603 22 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 605 606 608 609 610 611 612 Controller Area Network (CAN) Module ..................................................................................... 613 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: CAN Control (CANCTL), offset 0x000 ............................................................................. 634 CAN Status (CANSTS), offset 0x004 ............................................................................... 636 CAN Error Counter (CANERR), offset 0x008 ................................................................... 638 CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 639 CAN Interrupt (CANINT), offset 0x010 ............................................................................. 640 CAN Test (CANTST), offset 0x014 .................................................................................. 641 CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 643 CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 644 CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 644 CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 645 CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 645 CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 647 CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 647 CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 648 CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 648 CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 649 CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 649 CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 650 CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 650 CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 652 CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 652 CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 654 CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 654 CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 654 CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 654 CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 654 CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 654 CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 654 CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 654 CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 655 CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 655 CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 656 CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 656 CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 657 CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 657 CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 658 CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 658 Universal Serial Bus (USB) Controller ....................................................................................... 659 Register 1: Register 2: USB Device Functional Address (USBFADDR), offset 0x000 ............................................ 676 USB Power (USBPOWER), offset 0x001 ......................................................................... 677 July 17, 2014 23 Texas Instruments-Production Data Table of Contents Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: USB Transmit Interrupt Status (USBTXIS), offset 0x002 ................................................... 680 USB Receive Interrupt Status (USBRXIS), offset 0x004 ................................................... 681 USB Transmit Interrupt Enable (USBTXIE), offset 0x006 .................................................. 682 USB Receive Interrupt Enable (USBRXIE), offset 0x008 .................................................. 683 USB General Interrupt Status (USBIS), offset 0x00A ........................................................ 684 USB Interrupt Enable (USBIE), offset 0x00B .................................................................... 687 USB Frame Value (USBFRAME), offset 0x00C ................................................................ 690 USB Endpoint Index (USBEPIDX), offset 0x00E .............................................................. 691 USB Test Mode (USBTEST), offset 0x00F ....................................................................... 692 USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 ............................................................. 694 USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 ............................................................. 694 USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 ............................................................. 694 USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C ............................................................ 694 USB Device Control (USBDEVCTL), offset 0x060 ............................................................ 695 USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 ................................. 696 USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 .................................. 696 USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 ................................. 697 USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 .................................. 697 USB Connect Timing (USBCONTIM), offset 0x07A .......................................................... 698 USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D ...... 699 USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E ...... 700 USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 ........... 701 USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 ........... 701 USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 ........... 701 USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 ........... 701 USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 ...................... 702 USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A ...................... 702 USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 ...................... 702 USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A ...................... 702 USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 ............................. 703 USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B ............................ 703 USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 ............................. 703 USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B ............................ 703 USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C ........... 704 USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 ........... 704 USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C ........... 704 USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E ...................... 705 USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 ....................... 705 USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E ...................... 705 USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F ............................. 706 USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 ............................. 706 USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F ............................. 706 USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 .......................... 707 USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 .......................... 707 USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 .......................... 707 USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 ................................. 708 USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 ............................... 712 USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 ................................... 714 24 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: Register 69: Register 70: Register 71: Register 72: Register 73: Register 74: Register 75: Register 76: Register 77: Register 78: Register 79: Register 80: Register 81: Register 82: Register 83: Register 84: Register 85: Register 86: Register 87: Register 88: Register 89: Register 90: Register 91: Register 92: Register 93: Register 94: Register 95: USB Type Endpoint 0 (USBTYPE0), offset 0x10A ............................................................ 715 USB NAK Limit (USBNAKLMT), offset 0x10B .................................................................. 716 USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 ............... 717 USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 ............... 717 USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 ............... 717 USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 .............. 721 USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 ............. 721 USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 ............. 721 USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 ........................... 725 USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 ........................... 725 USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 ........................... 725 USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 ............... 726 USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 ............... 726 USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 ............... 726 USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 .............. 731 USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 .............. 731 USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 .............. 731 USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 .............................. 735 USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 .............................. 735 USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 .............................. 735 USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ................... 736 USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ................... 736 USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ................... 736 USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B ....................... 737 USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B ....................... 737 USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B ....................... 737 USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................... 738 USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................... 738 USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ................... 738 USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D ............. 739 USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ............ 739 USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ............ 739 USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset 0x304 ........................................................................................................................... 740 USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset 0x308 ........................................................................................................................... 740 USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset 0x30C ........................................................................................................................... 740 USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ............. 741 USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 ............ 742 USB External Power Control (USBEPC), offset 0x400 ...................................................... 743 USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ................. 746 USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 ............................ 747 USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ......... 748 USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 ............................ 749 USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ....................................... 750 USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................... 751 USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................... 752 July 17, 2014 25 Texas Instruments-Production Data Revision History Revision History The revision history table notes changes made between the indicated revisions of the LM3S5732 data sheet. Table 1. Revision History Date July 2014 Revision Description 15852.2743 ■ In JTAG chapter, clarified procedure for recovering a locked device as well as sections on JTAG-to-SWD Switching and SWD-to-JTAG Switching. ■ In System Control chapter, clarified behavior of Reset Cause (RESC) register external reset bit. ■ In Internal Memory chapter: – Added sections on Execute-Only Protection, Read-Only Protection, and Permanently Disabling Debug. – Noted that the Boot Configuration (BOOTCFG) register requires a POR before committed changes to the Flash-resident registers take effect. ■ In UART chapter: – Clarified that the transmit interrupt is based on a transition through level. – Corrected reset for UART Raw Interrupt Status (UARTRIS) register. ■ In Electrical Characteristics chapter, updated Crystal Characteristics table. ■ In Ordering and Contact Information appendix, moved orderable part numbers table to addendum. ■ Additional minor data sheet clarifications and corrections. 26 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 1. Revision History (continued) Date Revision November 2011 11107 Description ■ Clarified that when the USB module is in operation, MOSC must be provided with a clock source, and the system clock must be at least 30 MHz. ■ Added module-specific pin tables to each chapter in the new Signal Description sections. ■ In Hibernation chapter: – Changed terminology from non-volatile memory to battery-backed memory. – Clarified Hibernation module register reset conditions. ■ In Internal Memory chapter, corrected note in USER_DBG and USER_REG0/1/2/3 registers, that once committed, the value of the register can never be restored to the factory default value. ■ In Timer chapter, clarified that in 16-Bit Input Edge Time Mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. ■ In UART chapter, clarified interrupt behavior. ■ In SSI chapter, corrected SSIClk in the figure "Synchronous Serial Frame Format (Single Transfer)". ■ In USB chapter: ■ – Removed MULTTRAN bit from USB Transmit Hub Address Endpoint n (USBTXHUBADDRn) and USB Receive Hub Address Endpoint n (USBRXHUBADDRn) registers. – Removed DISCON bit from Device Mode table for USB General Interrupt Status (USBIS) register. – Added WTID bit to USB Connect Timing (USBCONTIM) register. In Signal Tables chapter: – ■ ■ Corrected pin numbers in table "Connections for Unused Signals" (other pin tables were correct). In Electrical Characteristics chapter: – Corrected values in "Detailed Power Specifications" table. – Added "System Clock Characteristics with USB Operation" table. – Corrected Nom values for parameters "TCK clock Low time" and "TCK clock High time" in "JTAG Characteristics" table. – Corrected missing values for "Conversion time" and "Conversion rate" parameters in "ADC Characteristics" table. Additional minor data sheet clarifications and corrections. July 17, 2014 27 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision January 2011 9102 September 2010 7783 Description ■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ to SYSRESREQ. ■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register. ■ Added "Reset Sources" table to System Control chapter. ■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported. ■ Added note that specific module clocks must be enabled before that module's registers can be programmed. There must be a delay of 3 system clocks after the module clock is enabled before any of that module's registers are accessed. ■ Changed I2C slave register base addresses and offsets to be relative to the I2C module base address of 0x4002.0000 and 0x4002.1000, so register bases and offsets were changed for all I2C slave ® registers. Note that the hw_i2c.h file in the StellarisWare Driver Library uses a base address of 2 0x4002.0800 and 0x4002.1800 for the I C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare uses the old slave base address for these offsets. ■ Corrected nonlinearity and offset error parameters (EL, ED and EO) in ADC Characteristics table. ■ Added specification for maximum input voltage on a non-power pin when the microcontroller is unpowered (VNON parameter in Maximum Ratings table). ■ Additional minor data sheet clarifications and corrections. ■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was added, including all the Cortex-M3 registers. ■ Changed register names to be consistent with StellarisWare names: the Cortex-M3 Interrupt Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register. ■ In the Internal Memory chapter: – Added clarification of instruction execution during Flash operations. – Deleted ROM Version (RMVER) register as it is not used. ■ In the GPIO chapter: – Renamed the GPIO High-Speed Control (GPIOHSCTL) register to the GPIO High-Performance Bus Control (GPIOHBCTL) register. – Added clarification about the operation of the Advanced High-Performance Bus (AHB) and the legacy Advanced Peripheral Bus (APB). – Modified Figure 9-1 on page 354 and Figure 9-2 on page 355 to clarify operation of the GPIO inputs when used as an alternate function. ■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode. ■ Numerous improvements and clarifications to the USB chapter. Also corrected definitions for bits 2 and 5 in the USBIE register. ■ In Electrical Characteristics chapter: – Added "Input voltage for a GPIO configured as an analog input" value to Table 21-1 on page 766. – Added ILKG parameter (GPIO input leakage current) to Table 21-4 on page 767. – Corrected values for tCLKRF parameter (SSIClk rise/fall time) in Table 21-22 on page 777. ■ Added dimensions for Tray and Tape and Reel shipping mediums. 28 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 1. Revision History (continued) Date Revision June 2010 7403 April 2010 January 2010 7021 6707 Description ■ Corrected base address for SRAM in architectural overview chapter. ■ Clarified system clock operation, adding content to “Clock Control” on page 176. ■ Clarified CAN bit timing examples. ■ In Signal Tables chapter, added table "Connections for Unused Signals." ■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time. ■ Additional minor data sheet clarifications and corrections. ■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed field width to 7 bits. ■ Added note about RST signal routing. ■ Clarified the function of the TnSTALL bit in the GPTMCTL register. ■ Additional minor data sheet clarifications and corrections. ■ In "System Control" section, clarified Debug Access Port operation after Sleep modes. ■ Clarified wording on Flash memory access errors. ■ Added section on Flash interrupts. ■ Changed the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers to be indeterminate. ■ Clarified operation of SSI transmit FIFO. ■ Made these changes to the Operating Characteristics chapter: ■ – Added storage temperature ratings to "Temperature Characteristics" table – Added "ESD Absolute Maximum Ratings" table Made these changes to the Electrical Characteristics chapter: – In "Flash Memory Characteristics" table, corrected Mass erase time – Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) – In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time July 17, 2014 29 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision October 2009 6449 July 2009 5920 Description ■ Removed the MAXADCSPD bit field from the DCGC0 register as it has no function in deep-sleep mode. ■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers because the module resets in 32-bit mode. ■ Clarified CAN bit timing and corrected examples. ■ Corrected description for ADDR bit field in USBTXFIFOSZ and USBRXFIFOSZ registers. ■ Clarified PWM source for ADC triggering ■ Made these changes to the Electrical Characteristics chapter: – Removed VSIH and VSIL parameters from Operating Conditions table. – Changed SSI set up and hold times to be expressed in system clocks, not ns. – Revised ADC electrical specifications to clarify, including reorganizing and adding new data. – Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS. – Table added showing actual PLL frequency depending on input crystal. ■ Additional minor data sheet clarifications and corrections. ■ Clarified Power-on reset and RST pin operation; added new diagrams. ■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL) registers. ■ Clarified explanation of nonvolatile register programming in Internal Memory chapter. ■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1 registers. ■ Special bulk handling and packet splitting has never been supported as the µDMA module can support the same function. As a result, all references to these topics has been removed. Bit 7 in the USBTXCSRLn register only functions as NAKTO in Host mode and is reserved in Device mode. In addition, bit 0 in the USBRXCSRHn register is reserved. ■ The DISCON and CONN bits in the USBIS and USBIE registers are not available in Device mode. When the USB controller is acting as a self-powered Device, a GPIO input or analog comparator input must be connected to VBUS and configured to generate an interrupt when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal. ■ Changed buffer type for WAKE pin to TTL. ■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR(Internal voltage reference error) parameter. ■ Changed ordering numbers. ■ Additional minor data sheet clarifications and corrections. 30 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 1. Revision History (continued) Date Revision April 2009 5368 January 2009 November 2008 4724 4283 Description ■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 165). ■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor. ■ Corrected bits 2:1 in I2CSIMR, I2CSRIS, I2CSMIS, and I2CSICR registers to be reserved bits (cannot interrupt on start and stop conditions). ■ Corrected bits 15:11 in USBTXMAXP0/1/2 and USBRXMAXP0/1/2 registers to be reserved bits (cannot define multiplier). ■ Additional minor data sheet clarifications and corrections. ■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W. ■ Added clarification as to what happens when the SSI in slave mode is required to transmit but there is no data in the TX FIFO. ■ Added section called "Setting the Device Address" for special considerations when writing the USBFADDR register. ■ Corrected USBEPIDX to be an 8-bit register. ■ Added comparator operating mode tables. ■ Corrected pin types of signals RST to "in" and USB0RBIAS to "out". ■ Additional minor data sheet clarifications and corrections. ■ Revised High-Level Block Diagram. ■ Additional minor data sheet clarifications and corrections were made. July 17, 2014 31 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision October 2008 4149 Description ■ Added note on clearing interrupts to the Interrupts chapter: Note: ■ It may take several processor cycles after a write to clear an interrupt source in order for NVIC to see the interrupt source de-assert. This means if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer) Added clarification on JTAG reset to the JTAG chapter: In order to reset the JTAG module after the device has been powered on, the TMS input must be held HIGH for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. ■ The binary value was incorrect in the JTAG 16-bit switch sequence in the JTAG-to-SWD Switching section in the JTAG chapter. Sentence changed to: The 16-bit switch sequence for switching to JTAG mode is defined as b1110011100111100, transmitted LSB first. ■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the Internal Memory chapter. The correct value is 0x0000.0006. ■ Step 1 of the Initialization and Configuration procedure in the ADC chapter states the wrong register to use to enable the ADC clock. Sentence changed to: 1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC0 register. June 2008 2972 ■ In the CAN chapter, major improvements were made including a rewrite of the conceptual information and the addition of new figures to clarify how to use the Controller Area Network (CAN) module. ■ In the USB chapter, clarified endpoint terminology and added a new section on DMA Operation. ■ Additional minor data sheet clarifications and corrections were made. Started tracking revision history. 32 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller About This Document This data sheet provides reference information for the LM3S5732 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents ® The following related documents are available on the Stellaris web site at www.ti.com/stellaris: ■ Stellaris® Errata ■ ARM® Cortex™-M3 Errata ■ Cortex™-M3/M4 Instruction Set Technical User's Manual ■ Stellaris® Boot Loader User's Guide ■ Stellaris® Graphics Library User's Guide ■ Stellaris® Peripheral Driver Library User's Guide ■ Stellaris® ROM User’s Guide ■ Stellaris® USB Library User's Guide The following related documents are also referenced: ■ ARM® Debug Interface V5 Architecture Specification ■ ARM® Embedded Trace Macrocell Architecture Specification ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers. July 17, 2014 33 Texas Instruments-Production Data About This Document Documentation Conventions This document uses the conventions shown in Table 2 on page 34. Table 2. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. bit A single bit in a register. bit field Two or more consecutive and related bits. offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 2-4 on page 72. Register N Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. reserved Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. Register Bit/Field Types This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. R/WC Software can read or write this field. Writing to it with any value clears the register. R/W1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1S Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit value in the register. W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field Reset Value This value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. 34 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 2. Documentation Conventions (continued) Notation Meaning assert a signal Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). deassert a signal Change the value of the signal from the logically True state to the logically False state. SIGNAL Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. 0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. July 17, 2014 35 Texas Instruments-Production Data Architectural Overview 1 Architectural Overview ® The Stellaris family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The Stellaris family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris LM3S5000 series combines USB 2.0 Full-Speed On-The-Go/Host/Device combinations with Bosch CAN networking technology. The LM3S5732 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. For applications requiring extreme conservation of power, the LM3S5732 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S5732 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S5732 microcontroller perfectly for battery applications. In addition, the LM3S5732 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S5732 microcontroller is code-compatible to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise needs. Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact Information” on page 826 for ordering information for Stellaris family devices. 1.1 Product Features The LM3S5732 microcontroller includes the following product features: ■ 32-Bit RISC Performance – 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications – System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism – Thumb®-compatible Thumb-2-only instruction set processor core for high code density – 50-MHz operation – Hardware-division and single-cycle-multiplication 36 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller – Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling – 28 interrupts with eight priority levels – Memory protection unit (MPU), providing a privileged mode for protected operating system functionality – Unaligned data access, enabling data to be efficiently packed into memory – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ■ ARM® Cortex™-M3 Processor Core – Compact core. – Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. – Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. – Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. – Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining – External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler for safety critical applications. – Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. – Migration from the ARM7™ processor family for better performance and power efficiency. – Full-featured debug solution • Serial Wire JTAG Debug Port (SWJ-DP) • Flash Patch and Breakpoint (FPB) unit for implementing breakpoints • Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling • Instrumentation Trace Macrocell (ITM) for support of printf style debugging • Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer – Optimized for single-cycle flash usage – Three sleep modes with clock gating for low power – Single-cycle multiply instruction and hardware divide July 17, 2014 37 Texas Instruments-Production Data Architectural Overview – Atomic operations – ARM Thumb2 mixed 16-/32-bit instruction set – 1.25 DMIPS/MHz ■ JTAG – IEEE 1149.1-1990 compatible Test Access Port (TAP) controller – Four-bit Instruction Register (IR) chain for storing JTAG instructions – IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST – ARM additional instructions: APACC, DPACC and ABORT – Integrated ARM Serial Wire Debug (SWD) ■ Hibernation – System power control using discrete external regulator – Dedicated pin for waking from an external signal – Low-battery detection, signaling, and interrupt generation – 32-bit real-time clock (RTC) – Two 32-bit RTC match registers for timed wake-up and interrupt generation – Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal – RTC predivider trim for making fine adjustments to the clock rate – 64 32-bit words of non-volatile memory – Programmable interrupts for RTC match, external wake, and low battery events ■ Internal Memory – 128 KB single-cycle flash • User-managed flash block protection on a 2-KB block basis • User-managed flash data programming • User-defined and managed flash-protection block – 64 KB single-cycle SRAM – Pre-programmed ROM • Stellaris family peripheral driver library (DriverLib) • Stellaris boot loader ■ DMA Controller 38 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller – ARM PrimeCell® 32-channel configurable µDMA controller – Support for multiple transfer modes • Basic, for simple transfer scenarios • Ping-pong, for continuous data flow to/from peripherals • Scatter-gather, from a programmable list of up to 256 arbitrary transfers initiated from a single request – Dedicated channels for supported peripherals – One channel each for receive and transmit path for bidirectional peripherals – Dedicated channel for software-initiated transfers – Independently configured and operated channels – Per-channel configurable bus arbitration scheme – Two levels of priority – Design optimizations for improved bus access performance between µDMA controller and the processor core • µDMA controller access is subordinate to core access • RAM striping • Peripheral bus segmentation – Data sizes of 8, 16, and 32 bits – Source and destination address increment size of byte, half-word, word, or no increment – Maskable device requests – Optional software initiated requests for any channel – Interrupt on transfer completion, with a separate interrupt per channel ■ GPIOs – 1-33 GPIOs, depending on configuration – 5-V-tolerant in input configuration – Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with existing code – Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for ports on APB – Programmable control for GPIO interrupts July 17, 2014 39 Texas Instruments-Production Data Architectural Overview • Interrupt generation masking • Edge-triggered on rising, falling, or both • Level-sensitive on High or Low values – Bit masking in both read and write operations through address lines – Can initiate an ADC sample sequence – Pins configured as digital inputs are Schmitt-triggered. – Programmable control for GPIO pad configuration • Weak pull-up or pull-down resistors • 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications • Slew rate control for the 8-mA drive • Open drain enables • Digital input enables ■ General-Purpose Timers – Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently: • As a single 32-bit timer • As one 32-bit Real-Time Clock (RTC) to event capture • For Pulse Width Modulation (PWM) • To trigger analog-to-digital conversions – 32-bit Timer modes • Programmable one-shot timer • Programmable periodic timer • Real-Time Clock when using an external 32.768-KHz clock as the input • User-enabled stalling when the controller asserts CPU Halt flag during debug • ADC event trigger – 16-bit Timer modes • General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) • Programmable one-shot timer 40 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug • ADC event trigger – 16-bit Input Capture modes • Input edge count capture • Input edge time capture – 16-bit PWM mode • Simple PWM mode with software-programmable output inversion of the PWM signal ■ ARM FiRM-compliant Watchdog Timer – 32-bit down counter with a programmable load register – Separate watchdog clock with an enable – Programmable interrupt generation logic with interrupt masking – Lock register protection from runaway software – Reset generation logic with an enable/disable – User-enabled stalling when the controller asserts the CPU Halt flag during debug ■ ADC – Six analog input channels – Single-ended and differential-input configurations – On-chip internal temperature sensor – Sample rate of 500 thousand samples/second – Flexible, configurable analog-to-digital conversion – Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs – Flexible trigger control • Controller (software) • Timers • GPIO – Hardware averaging of up to 64 samples for improved accuracy – Converter uses an internal 3-V reference July 17, 2014 41 Texas Instruments-Production Data Architectural Overview – Power and ground for the analog circuitry is separate from the digital power and ground ■ UART – Two fully programmable 16C550-type UARTs with IrDA support – Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading – Programmable baud-rate generator allowing speeds up to 3.125 Mbps – Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface – FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 – Standard asynchronous communication bits for start, stop, and parity – Line-break generation and detection – Fully programmable serial interface characteristics • 5, 6, 7, or 8 data bits • Even, odd, stick, or no-parity bit generation/detection • 1 or 2 stop bit generation – IrDA serial-IR (SIR) encoder/decoder providing • Programmable use of IrDA Serial Infrared (SIR) or UART input/output • Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex • Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations • Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration – Dedicated Direct Memory Access (DMA) transmit and receive channels ■ Synchronous Serial Interface (SSI) – Master or slave operation – Support for Direct Memory Access (DMA) – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from 4 to 16 bits – Internal loopback test mode for diagnostic/debug testing 42 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ■ I2C – Two I2C modules, each with the following features: – Devices on the I2C bus can be designated as either a master or a slave • Supports both sending and receiving data as either a master or a slave • Supports simultaneous master and slave operation – Four I2C modes • Master transmit • Master receive • Slave transmit • Slave receive – Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) – Master and slave interrupt generation • Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) • Slave generates interrupts when data has been sent or requested by a master – Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode ■ Controller Area Network (CAN) – CAN protocol version 2.0 part A/B – Bit rates up to 1 Mbps – 32 message objects with individual identifier masks – Maskable interrupt – Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications – Programmable Loopback mode for self-test operation – Programmable FIFO mode enables storage of multiple message objects – Gluelessly attaches to an external CAN interface through the CANnTX and CANnRX signals ■ USB – Standards-based – USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation – USB Device or Host mode July 17, 2014 43 Texas Instruments-Production Data Architectural Overview – Integrated PHY – 4 transfer types: Control, Interrupt, Bulk, and Isochronous – 8 endpoints • 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint • 3 configurable IN endpoints and 3 configurable OUT endpoints – 2 KB dedicated endpoint memory • Direct memory access (DMA) • One endpoint may be defined for double-buffered 1023-byte isochronous packet size ■ Power – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V – Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits – Low-power options on controller: Sleep and Deep-sleep modes – Low-power options for peripherals: software controls shutdown of individual peripherals – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Flexible Reset Sources – Power-on reset (POR) – Reset pin assertion – Brown-out (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – Internal low drop-out (LDO) regulator output goes unregulated ■ Industrial-range 64-pin RoHS-compliant LQFP package 1.2 Target Applications ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances and switches 44 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 46 depicts the features on the Stellaris LM3S5732 microcontroller. July 17, 2014 45 Texas Instruments-Production Data Architectural Overview Figure 1-1. Stellaris LM3S5732 Microcontroller High-Level Block Diagram JTAG/SWD ARM® Cortex™-M3 ROM Boot Loader DriverLib (50MHz) System Control and Clocks (w/ Precis. Osc.) Flash (128KB) DCode bus NVIC MPU ICode bus System Bus LM3S5732 Bus Matrix SRAM (64KB) SYSTEM PERIPHERALS GeneralPurpose Timer (3) Hibernation Module USB Host (FS PHY) SSI (1) Advanced Peripheral Bus (APB) Watchdog Timer (1) Advanced High-Performance Bus (AHB) DMA GPIOs (1-33) SERIAL PERIPHERALS UART (2) I2C (2) CAN Controller (1) ANALOG PERIPHERALS 10- Bit ADC Channels (6) 46 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 1.4 Functional Overview The following sections provide an overview of the features of the LM3S5732 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 826. 1.4.1 ARM Cortex™-M3 1.4.1.1 Processor Core (see page 53) All members of the Stellaris product family, including the LM3S5732 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. 1.4.1.2 Memory Map (see page 72) A memory map lists the location of instructions and data in memory. The memory map for the LM3S5732 controller can be found in Table 2-4 on page 72. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. 1.4.1.3 System Timer (SysTick) (see page 95) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.4 Nested Vectored Interrupt Controller (NVIC) (see page 96) The LM3S5732 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 28 interrupts. July 17, 2014 47 Texas Instruments-Production Data Architectural Overview 1.4.1.5 System Control Block (SCB) (see page 98) The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 1.4.1.6 Memory Protection Unit (MPU) (see page 98) The MPU supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 1.4.1.7 Direct Memory Access (see page 290) The LM3S5732 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing for more efficient use of the processor and the expanded available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported peripheral and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller also supports sophisticated transfer modes such as ping-pong and scatter-gather, which allows the processor to set up a list of transfer tasks for the controller. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S5732 controller features Pulse Width Modulation (PWM) outputs. 1.4.2.1 PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. On the LM3S5732, PWM motion control functionality can be achieved through: ■ The motion control features of the general-purpose timers using the CCP pins CCP Pins (see page 405) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. 1.4.3 Analog Peripherals To handle analog signals, the LM3S5732 microcontroller offers an Analog-to-Digital Converter (ADC). 1.4.3.1 ADC (see page 457) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The LM3S5732 ADC module features 10-bit conversion resolution and supports six input channels, plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up to eight analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. 48 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 1.4.4 Serial Communications Peripherals The LM3S5732 controller supports both asynchronous and synchronous serial communications with: ■ Two fully programmable 16C550-type UARTs ■ One SSI module ■ Two I2C modules ■ One USB 2.0 full-speed controller ■ One CAN unit 1.4.4.1 UART (see page 492) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S5732 controller includes two fully programmable 16C550-type UARTs that support data transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA. Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (see page 536) Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications interface. The LM3S5732 controller includes one SSI module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 I2C (see page 576) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). July 17, 2014 49 Texas Instruments-Production Data Architectural Overview The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S5732 controller includes two I2C modules that provide the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. Each I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master. 1.4.4.4 USB (see page 659) Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface without rebooting the system. The LM3S5732 controller supports the USB 2.0 full-speed configuration with Device or USB Host mode. The specified throughput for a USB 2.0 full-speed controller is 12 Mbps. 1.4.4.5 Controller Area Network (see page 613) Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire. Originally created for automotive purposes, now it is used in many embedded control applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at 500m). A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information. The LM3S5732 includes one CAN unit. 1.4.5 System Peripherals 1.4.5.1 Programmable GPIOs (see page 351) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris GPIO module is comprised of five physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 1-33 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 754 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. Pins configured as digital inputs are Schmitt-triggered. 50 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 1.4.5.2 Three Programmable Timers (see page 399) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.5.3 Watchdog Timer (see page 433) A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 Memory Peripherals The LM3S5732 controller offers both single-cycle SRAM and single-cycle Flash memory. 1.4.6.1 SRAM (see page 260) The LM3S5732 static random access memory (SRAM) controller supports 64 KB SRAM. The internal SRAM of the Stellaris devices starts at base address 0x2000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 Flash (see page 261) The LM3S5732 Flash controller supports 128 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.4.6.3 ROM (see page 786) The LM3S5732 microcontroller ships with the Stellaris family Peripheral Driver Library conveniently preprogrammed in read-only memory (ROM). The Stellaris Peripheral Driver Library is a royalty-free software library for controlling on-chip peripherals, and includes a boot-loader capability. The library performs both peripheral initialization and peripheral control functions, with a choice of polled or interrupt-driven peripheral support, and takes full advantage of the stellar interrupt performance of July 17, 2014 51 Texas Instruments-Production Data Architectural Overview the ARM® Cortex™-M3 core. No special pragmas or custom assembly code prologue/epilogue functions are required. For applications that require in-field programmability, the royalty-free Stellaris boot loader included in the Stellaris Peripheral Driver Library can act as an application loader and support in-field firmware updates. 1.4.7 Additional Features 1.4.7.1 JTAG TAP Controller (see page 159) The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is composed of the standard four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM, Stellaris, and unimplemented JTAG instructions. 1.4.7.2 System Control and Clocks (see page 171) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.7.3 Hibernation Module (see page 238) The Hibernation module provides logic to switch power off to the main processor and peripherals, and to wake on external or time-based events. The Hibernation module includes power-sequencing logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used for saving state during hibernation. 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 753 ■ “Signal Tables” on page 754 ■ “Operating Characteristics” on page 765 ■ “Electrical Characteristics” on page 766 ■ “Package Information” on page 828 52 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 2 The Cortex-M3 Processor The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ Compact core. ■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ■ Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. ■ Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. ■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining ■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler for safety critical applications. ■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. ■ Migration from the ARM7™ processor family for better performance and power efficiency. ■ Full-featured debug solution – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer ■ Optimized for single-cycle flash usage ■ Three sleep modes with clock gating for low power ■ Single-cycle multiply instruction and hardware divide ■ Atomic operations ■ ARM Thumb2 mixed 16-/32-bit instruction set ■ 1.25 DMIPS/MHz July 17, 2014 53 Texas Instruments-Production Data The Cortex-M3 Processor ® The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. This chapter provides information on the Stellaris implementation of the Cortex-M3 processor, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the instruction set, see the Cortex™-M3/M4 Instruction Set Technical User's Manual. 2.1 Block Diagram The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. 54 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep ARM Cortex-M3 CM3 Core Debug Instructions Data Trace Port Interface Unit Memory Protection Unit Flash Patch and Breakpoint Instrumentation Data Watchpoint Trace Macrocell and Trace ROM Table Private Peripheral Bus (internal) Adv. Peripheral Bus Bus Matrix Serial Wire JTAG Debug Port Debug Access Port 2.2 Overview 2.2.1 System-Level Interface Serial Wire Output Trace Port (SWO) I-code bus D-code bus System bus The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis. 2.2.2 Integrated Configurable Debug The Cortex-M3 processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification for details on SWJ-DP. For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. July 17, 2014 55 Texas Instruments-Production Data The Cortex-M3 Processor The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored in a read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration. For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5 Architecture Specification. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer, as shown in Figure 2-2 on page 56. Figure 2-2. TPIU Block Diagram 2.2.4 Debug ATB Slave Port ATB Interface APB Slave Port APB Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) Cortex-M3 System Component Details The Cortex-M3 includes the following system components: ■ SysTick A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as a simple counter (see “System Timer (SysTick)” on page 95). ■ Nested Vectored Interrupt Controller (NVIC) An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 96). ■ System Control Block (SCB) 56 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see “System Control Block (SCB)” on page 98). ■ Memory Protection Unit (MPU) Improves system reliability by defining the memory attributes for different memory regions. The MPU provides up to eight different regions and an optional predefined background region (see “Memory Protection Unit (MPU)” on page 98). 2.3 Programming Model This section describes the Cortex-M3 programming model. In addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included. 2.3.1 Processor Mode and Privilege Levels for Software Execution The Cortex-M3 has two modes of operation: ■ Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. ■ Handler mode Used to handle exceptions. When the processor has finished exception processing, it returns to Thread mode. In addition, the Cortex-M3 has two privilege levels: ■ Unprivileged In this mode, software has the following restrictions: – Limited access to the MSR and MRS instructions and no use of the CPS instruction – No access to the system timer, NVIC, or system control block – Possibly restricted access to memory or peripherals ■ Privileged In this mode, software can use all the instructions and has access to all resources. In Thread mode, the CONTROL register (see page 71) controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 2.3.2 Stacks The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks: July 17, 2014 57 Texas Instruments-Production Data The Cortex-M3 Processor the main stack and the process stack, with a pointer for each held in independent registers (see the SP register on page 61). In Thread mode, the CONTROL register (see page 71) controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1 on page 58. Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use Processor Mode Use Privilege Level Thread Applications Privileged or unprivileged Stack Used Handler Exception handlers Always privileged a Main stack or process stack a Main stack a. See CONTROL (page 71). 2.3.3 Register Map Figure 2-3 on page 58 shows the Cortex-M3 register set. Table 2-2 on page 59 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. Figure 2-3. Cortex-M3 Register Set R0 R1 R2 Low registers R3 R4 R5 R6 General-purpose registers R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSR PSP‡ MSP‡ ‡ Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL CONTROL register 58 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 2-2. Processor Register Map Offset Type Reset - R0 R/W - Cortex General-Purpose Register 0 60 - R1 R/W - Cortex General-Purpose Register 1 60 - R2 R/W - Cortex General-Purpose Register 2 60 - R3 R/W - Cortex General-Purpose Register 3 60 - R4 R/W - Cortex General-Purpose Register 4 60 - R5 R/W - Cortex General-Purpose Register 5 60 - R6 R/W - Cortex General-Purpose Register 6 60 - R7 R/W - Cortex General-Purpose Register 7 60 - R8 R/W - Cortex General-Purpose Register 8 60 - R9 R/W - Cortex General-Purpose Register 9 60 - R10 R/W - Cortex General-Purpose Register 10 60 - R11 R/W - Cortex General-Purpose Register 11 60 - R12 R/W - Cortex General-Purpose Register 12 60 - SP R/W - Stack Pointer 61 - LR R/W 0xFFFF.FFFF Link Register 62 - PC R/W - Program Counter 63 - PSR R/W 0x0100.0000 Program Status Register 64 - PRIMASK R/W 0x0000.0000 Priority Mask Register 68 - FAULTMASK R/W 0x0000.0000 Fault Mask Register 69 - BASEPRI R/W 0x0000.0000 Base Priority Mask Register 70 - CONTROL R/W 0x0000.0000 Control Register 71 2.3.4 Description See page Name Register Descriptions This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 58. The core registers are not memory mapped and are accessed by register name rather than offset. Note: The register type shown in the register descriptions refers to type during program execution in Thread mode and Handler mode. Debug access can differ. July 17, 2014 59 Texas Instruments-Production Data The Cortex-M3 Processor Register 1: Cortex General-Purpose Register 0 (R0) Register 2: Cortex General-Purpose Register 1 (R1) Register 3: Cortex General-Purpose Register 2 (R2) Register 4: Cortex General-Purpose Register 3 (R3) Register 5: Cortex General-Purpose Register 4 (R4) Register 6: Cortex General-Purpose Register 5 (R5) Register 7: Cortex General-Purpose Register 6 (R6) Register 8: Cortex General-Purpose Register 7 (R7) Register 9: Cortex General-Purpose Register 8 (R8) Register 10: Cortex General-Purpose Register 9 (R9) Register 11: Cortex General-Purpose Register 10 (R10) Register 12: Cortex General-Purpose Register 11 (R11) Register 13: Cortex General-Purpose Register 12 (R12) The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Cortex General-Purpose Register 0 (R0) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - DATA Type Reset DATA Type Reset Bit/Field Name Type Reset 31:0 DATA R/W - Description Register data. 60 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 14: Stack Pointer (SP) The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode. Stack Pointer (SP) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - SP Type Reset SP Type Reset Bit/Field Name Type Reset 31:0 SP R/W - Description This field is the address of the stack pointer. July 17, 2014 61 Texas Instruments-Production Data The Cortex-M3 Processor Register 15: Link Register (LR) The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. LR can be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 88 for the values and description. Link Register (LR) Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 LINK Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 LINK Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 LINK R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF This field is the return address. 62 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 16: Program Counter (PC) The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode. Program Counter (PC) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - PC Type Reset PC Type Reset Bit/Field Name Type Reset 31:0 PC R/W - Description This field is the current program address. July 17, 2014 63 Texas Instruments-Production Data The Cortex-M3 Processor Register 17: Program Status Register (PSR) Note: This register is also referred to as xPSR. The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions: ■ Application Program Status Register (APSR), bits 31:27, ■ Execution Program Status Register (EPSR), bits 26:24, 15:10 ■ Interrupt Program Status Register (IPSR), bits 6:0 The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be accessed in either privileged or unprivileged mode. APSR contains the current state of the condition flags from previous instruction executions. EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see “Exception Entry and Return” on page 86). IPSR contains the exception type number of the current Interrupt Service Routine (ISR). These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. page 64 shows the possible register combinations for the PSR. See the MRS and MSR instruction descriptions in the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information about how to access the program status registers. Table 2-3. PSR Register Combinations Register Type PSR R/W Combination APSR, EPSR, and IPSR IEPSR RO EPSR and IPSR a, b a APSR and IPSR b APSR and EPSR IAPSR R/W EAPSR R/W a. The processor ignores writes to the IPSR bits. b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. Program Status Register (PSR) Type R/W, reset 0x0100.0000 Type Reset 31 30 29 28 27 N Z C V Q 26 25 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 15 14 13 12 11 10 9 ICI / IT ICI / IT Type Reset RO 0 RO 0 RO 0 24 23 22 21 20 THUMB RO 1 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 reserved RO 0 RO 0 RO 0 RO 0 RO 0 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 reserved ISRNUM RO 0 RO 0 64 RO 0 RO 0 RO 0 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 31 N R/W 0 Description APSR Negative or Less Flag Value Description 1 The previous operation result was negative or less than. 0 The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessing PSR or APSR. 30 Z R/W 0 APSR Zero Flag Value Description 1 The previous operation result was zero. 0 The previous operation result was non-zero. The value of this bit is only meaningful when accessing PSR or APSR. 29 C R/W 0 APSR Carry or Borrow Flag Value Description 1 The previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. 0 The previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. The value of this bit is only meaningful when accessing PSR or APSR. 28 V R/W 0 APSR Overflow Flag Value Description 1 The previous operation resulted in an overflow. 0 The previous operation did not result in an overflow. The value of this bit is only meaningful when accessing PSR or APSR. 27 Q R/W 0 APSR DSP Overflow and Saturation Flag Value Description 1 DSP Overflow or saturation has occurred. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. July 17, 2014 65 Texas Instruments-Production Data The Cortex-M3 Processor Bit/Field Name Type Reset 26:25 ICI / IT RO 0x0 Description EPSR ICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are zero. The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 24 THUMB RO 1 EPSR Thumb State This bit indicates the Thumb state and should always be set. The following can clear the THUMB bit: ■ The BLX, BX and POP{PC} instructions ■ Restoration from the stacked xPSR value on an exception return ■ Bit 0 of the vector value on an exception entry or reset Attempting to execute instructions when this bit is clear results in a fault or lockup. See “Lockup” on page 90 for more information. The value of this bit is only meaningful when accessing PSR or EPSR. 23:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:10 ICI / IT RO 0x0 EPSR ICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When an interrupt occurs during the execution of an LDM, STM, PUSH or POP instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. When EPSR holds the ICI execution state, bits 11:10 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 9:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 66 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 6:0 ISRNUM RO 0x00 IPSR ISR Number This field contains the exception type number of the current Interrupt Service Routine (ISR). Value Description 0x00 Thread mode 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x3F Interrupt Vector 47 0x40-0x7F Reserved See “Exception Types” on page 81 for more information. The value of this field is only meaningful when accessing PSR or IPSR. July 17, 2014 67 Texas Instruments-Production Data The Cortex-M3 Processor Register 18: Priority Mask Register (PRIMASK) The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 81. Priority Mask Register (PRIMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PRIMASK R/W 0 RO 0 PRIMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority. 0 No effect. 68 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 19: Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 81. Fault Mask Register (FAULTMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 FAULTMASK R/W 0 RO 0 FAULTMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI. 0 No effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. July 17, 2014 69 Texas Instruments-Production Data The Cortex-M3 Processor Register 20: Base Priority Mask Register (BASEPRI) The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. For more information on exception priority levels, see “Exception Types” on page 81. Base Priority Mask Register (BASEPRI) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset BASEPRI RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:5 BASEPRI R/W 0x0 R/W 0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Base Priority Any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. The PRIMASK register can be used to mask all exceptions with programmable priority levels. Higher priority exceptions have lower priority levels. Value Description 4:0 reserved RO 0x0 0x0 All exceptions are unmasked. 0x1 All exceptions with priority level 1-7 are masked. 0x2 All exceptions with priority level 2-7 are masked. 0x3 All exceptions with priority level 3-7 are masked. 0x4 All exceptions with priority level 4-7 are masked. 0x5 All exceptions with priority level 5-7 are masked. 0x6 All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 70 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 21: Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. This register is only accessible in privileged mode. Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 88). In an OS environment, threads running in Thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex™-M3/M4 Instruction Set Technical User's Manual, or perform an exception return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 88. Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the Cortex™-M3/M4 Instruction Set Technical User's Manual. Control Register (CONTROL) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 ASP TMPL RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 ASP R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Active Stack Pointer Value Description 1 PSP is the current stack pointer. 0 MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. 0 TMPL R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. July 17, 2014 71 Texas Instruments-Production Data The Cortex-M3 Processor 2.3.5 Exceptions and Interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See “Exception Entry and Return” on page 86 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” on page 96 for more information. 2.3.6 Data Types The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. See “Memory Regions, Types and Attributes” on page 74 for more information. 2.4 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map for the LM3S5732 controller is provided in Table 2-4 on page 72. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see “Bit-Banding” on page 76). The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers (see “Cortex-M3 Peripherals” on page 95). Note: Within the memory map, all reserved space returns a bus fault when read or written. Table 2-4. Memory Map Start End Description For details, see page ... 0x0000.0000 0x0001.FFFF On-chip Flash 267 0x0002.0000 0x00FF.FFFF Reserved - 0x0100.0000 0x1FFF.FFFF Reserved for ROM 261 0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAM 260 0x2001.0000 0x21FF.FFFF Reserved - 0x2200.0000 0x221F.FFFF Bit-band alias of bit-banded on-chip SRAM starting at 0x2000.0000 260 0x2220.0000 0x3FFF.FFFF Reserved - 0x4000.0000 0x4000.0FFF Watchdog timer 0 436 0x4000.1000 0x4000.3FFF Reserved - 0x4000.4000 0x4000.4FFF GPIO Port A 361 0x4000.5000 0x4000.5FFF GPIO Port B 361 0x4000.6000 0x4000.6FFF GPIO Port C 361 0x4000.7000 0x4000.7FFF GPIO Port D 361 Memory FiRM Peripherals 72 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x4000.8000 0x4000.8FFF SSI0 549 0x4000.9000 0x4000.BFFF Reserved - 0x4000.C000 0x4000.CFFF UART0 501 0x4000.D000 0x4000.DFFF UART1 501 0x4000.E000 0x4001.FFFF Reserved - 0x4002.0000 0x4002.0FFF I2C 0 591 0x4002.1000 0x4002.1FFF I2C 1 591 0x4002.2000 0x4002.3FFF Reserved - 0x4002.4000 0x4002.4FFF GPIO Port E 361 0x4002.5000 0x4002.FFFF Reserved - 0x4003.0000 0x4003.0FFF Timer 0 410 0x4003.1000 0x4003.1FFF Timer 1 410 0x4003.2000 0x4003.2FFF Timer 2 410 0x4003.3000 0x4003.7FFF Reserved - 0x4003.8000 0x4003.8FFF ADC0 466 0x4003.9000 0x4003.FFFF Reserved - 0x4004.0000 0x4004.0FFF CAN0 Controller 633 0x4004.1000 0x4004.FFFF Reserved - 0x4005.0000 0x4005.0FFF USB 675 0x4005.1000 0x4005.7FFF Reserved - 0x4005.8000 0x4005.8FFF GPIO Port A (AHB aperture) 361 0x4005.9000 0x4005.9FFF GPIO Port B (AHB aperture) 361 0x4005.A000 0x4005.AFFF GPIO Port C (AHB aperture) 361 0x4005.B000 0x4005.BFFF GPIO Port D (AHB aperture) 361 0x4005.C000 0x4005.CFFF GPIO Port E (AHB aperture) 361 0x4005.D000 0x400F.BFFF Reserved - 0x400F.C000 0x400F.CFFF Hibernation Module 246 0x400F.D000 0x400F.DFFF Flash memory control 267 0x400F.E000 0x400F.EFFF System control 185 0x400F.F000 0x400F.FFFF µDMA 310 0x4010.0000 0x41FF.FFFF Reserved - 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - 0x4400.0000 0xDFFF.FFFF Reserved - 0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 55 0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 55 0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 55 0xE000.3000 0xE000.DFFF Reserved - 0xE000.E000 0xE000.EFFF Cortex-M3 Peripherals (SysTick, NVIC, MPU and SCB) 103 0xE000.F000 0xE003.FFFF Reserved - Peripherals Private Peripheral Bus July 17, 2014 73 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 56 0xE004.1000 0xFFFF.FFFF Reserved - 2.4.1 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: ■ Normal: The processor can re-order transactions for efficiency and perform speculative reads. ■ Device: The processor preserves transaction order relative to other transactions to Device or Strongly Ordered memory. ■ Strongly Ordered: The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region. 2.4.2 Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions (see “Software Ordering of Memory Accesses” on page 75). However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always observed before A2. 2.4.3 Behavior of Memory Accesses Table 2-5 on page 74 shows the behavior of accesses to each region in the memory map. See “Memory Regions, Types and Attributes” on page 74 for more information on memory types and the XN attribute. Stellaris devices may have reserved memory areas within the address ranges shown below (refer to Table 2-4 on page 72 for more information). Table 2-5. Memory Access Behavior Address Range Memory Region 0x0000.0000 - 0x1FFF.FFFF Code Memory Type Execute Never (XN) Description Normal - This executable region is for program code. Data can also be stored here. 74 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 2-5. Memory Access Behavior (continued) Address Range Memory Region Memory Type Execute Never (XN) Description 0x2000.0000 - 0x3FFF.FFFF SRAM Normal - This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 77). 0x4000.0000 - 0x5FFF.FFFF Peripheral Device XN This region includes bit band and bit band alias areas (see Table 2-7 on page 77). 0x6000.0000 - 0x9FFF.FFFF External RAM Normal - This executable region is for data. 0xA000.0000 - 0xDFFF.FFFF External device Device XN This region is for external device memory. 0xE000.0000- 0xE00F.FFFF Private peripheral bus Strongly Ordered XN This region includes the NVIC, system timer, and system control block. 0xE010.0000- 0xFFFF.FFFF Reserved - - - The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region because the Cortex-M3 has separate buses that can perform instruction fetches and data accesses simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit (MPU)” on page 98. The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. 2.4.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: ■ The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. ■ The processor has multiple bus interfaces. ■ Memory or devices in the memory map have different wait states. ■ Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” on page 74 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The Cortex-M3 has the following memory barrier instructions: ■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. ■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. ■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. Memory barrier instructions can be used in the following situations: July 17, 2014 75 Texas Instruments-Production Data The Cortex-M3 Processor ■ MPU programming – If the MPU settings are changed and the change must be effective on the very next instruction, use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. – Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not required. ■ Vector table If the program changes an entry in the vector table and then enables the corresponding exception, use a DMB instruction between the operations. The DMB instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. ■ Self-modifying code If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. The change then takes effect on completion of the DSB instruction. Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use of DMB instructions. For more information on the memory barrier instructions, see the Cortex™-M3/M4 Instruction Set Technical User's Manual. 2.4.5 Bit-Banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-6 on page 77. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region, as shown in Table 2-7 on page 77. For the specific address range of the bit-band regions, see Table 2-4 on page 72. Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region. A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. 76 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 2-6. SRAM Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses Start End 0x2000.0000 0x2000.FFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. 0x2200.0000 0x221F.FFFF SRAM bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. Table 2-7. Peripheral Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses 0x400F.FFFF Peripheral bit-band region Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. 0x43FF.FFFF Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Start End 0x4000.0000 0x4200.0000 The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where: bit_word_offset The position of the target bit in the bit-band memory region. bit_word_addr The address of the word in the alias memory region that maps to the targeted bit. bit_band_base The starting address of the alias region. byte_offset The number of the byte in the bit-band region that contains the targeted bit. bit_number The bit position, 0-7, of the targeted bit. Figure 2-4 on page 78 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: ■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4) ■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4) July 17, 2014 77 Texas Instruments-Production Data The Cortex-M3 Processor ■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) Figure 2-4. Bit-Band Mapping 32-MB Alias Region 0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0 0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0004 0x2200.0000 7 3 1-MB SRAM Bit-Band Region 7 6 5 4 3 2 1 0 7 6 0x200F.FFFF 7 6 5 4 3 2 0x2000.0003 2.4.5.1 5 4 3 2 1 0 7 6 0x200F.FFFE 1 0 7 6 5 4 3 2 5 4 3 2 1 0 6 0x200F.FFFD 1 0 0x2000.0002 7 6 5 4 3 2 0x2000.0001 5 4 2 1 0 1 0 0x200F.FFFC 1 0 7 6 5 4 3 2 0x2000.0000 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set. 2.4.5.2 Directly Accessing a Bit-Band Region “Behavior of Memory Accesses” on page 74 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 2.4.6 Data Storage The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the 78 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-5 on page 79 illustrates how data is stored. Figure 2-5. Data Storage Memory 7 Register 0 31 2.4.7 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte Synchronization Primitives The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. A pair of synchronization primitives consists of: ■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. ■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write was performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: ■ The word instructions LDREX and STREX ■ The halfword instructions LDREXH and STREXH ■ The byte instructions LDREXB and STREXB Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform an exclusive read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Modify the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location. 4. Test the returned status bit. July 17, 2014 79 Texas Instruments-Production Data The Cortex-M3 Processor If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the entire read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1. The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has executed a Load-Exclusive instruction. The processor removes its exclusive access tag if: ■ It executes a CLREX instruction. ■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds. ■ An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see the Cortex™-M3/M4 Instruction Set Technical User's Manual. 2.5 Exception Model The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 2-8 on page 82 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 28 interrupts (listed in Table 2-9 on page 83). Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in “Nested Vectored Interrupt Controller (NVIC)” on page 96. Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the programmable priorities. Important: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be 80 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC)” on page 96 for more information on exceptions and interrupts. 2.5.1 Exception States Each exception is in one of the following states: ■ Inactive. The exception is not active and not pending. ■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. ■ Active. An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. ■ Active and Pending. The exception is being serviced by the processor, and there is a pending exception from the same source. 2.5.2 Exception Types The exception types are: ■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. ■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. ■ Hard Fault. A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. ■ Memory Management Fault. A memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. The MPU or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. ■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. July 17, 2014 81 Texas Instruments-Production Data The Cortex-M3 Processor ■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. ■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. ■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception is only active when enabled. This exception does not activate if it is a lower priority than the current activation. ■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using the Interrupt Control and State (INTCTRL) register. ■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor can use this exception as system tick. ■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 83 lists the interrupts on the LM3S5732 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 2-8 on page 82 shows as having configurable priority (see the SYSHNDCTRL register on page 137 and the DIS0 register on page 112). For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” on page 88. Table 2-8. Exception Types Exception Type a Vector Number Priority Vector Address or b Offset - 0 - 0x0000.0000 Stack top is loaded from the first entry of the vector table on reset. Reset 1 -3 (highest) 0x0000.0004 Asynchronous Non-Maskable Interrupt (NMI) 2 -2 0x0000.0008 Asynchronous Hard Fault 3 -1 0x0000.000C - 0x0000.0010 Synchronous Memory Management 4 c programmable 82 Activation July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 2-8. Exception Types (continued) Exception Type a Vector Number Priority Bus Fault 5 programmable Usage Fault 6 7-10 - Vector Address or b Offset Activation c 0x0000.0014 Synchronous when precise and asynchronous when imprecise programmable c 0x0000.0018 Synchronous - c c Reserved SVCall 11 programmable 0x0000.002C Synchronous Debug Monitor 12 programmable 0x0000.0030 Synchronous - 13 - 0x0000.0038 Asynchronous c 0x0000.003C Asynchronous PendSV 14 programmable SysTick 15 programmable Interrupts 16 and above Reserved c d programmable 0x0000.0040 and above Asynchronous a. 0 is the default priority for all the programmable priorities. b. See “Vector Table” on page 84. c. See SYSPRI1 on page 134. d. See PRIn registers on page 120. Table 2-9. Interrupts Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 0-15 - 0x0000.0000 0x0000.003C 16 0 0x0000.0040 GPIO Port A 17 1 0x0000.0044 GPIO Port B 18 2 0x0000.0048 GPIO Port C 19 3 0x0000.004C GPIO Port D 20 4 0x0000.0050 GPIO Port E 21 5 0x0000.0054 UART0 22 6 0x0000.0058 UART1 23 7 0x0000.005C SSI0 24 8 0x0000.0060 I2C0 25-29 9-13 - 30 14 0x0000.0078 ADC0 Sequence 0 31 15 0x0000.007C ADC0 Sequence 1 32 16 0x0000.0080 ADC0 Sequence 2 33 17 0x0000.0084 ADC0 Sequence 3 34 18 0x0000.0088 Watchdog Timer 0 35 19 0x0000.008C Timer 0A 36 20 0x0000.0090 Timer 0B 37 21 0x0000.0094 Timer 1A 38 22 0x0000.0098 Timer 1B 39 23 0x0000.009C Timer 2A 40 24 0x0000.00A0 Timer 2B 41-43 25-27 - Reserved Processor exceptions Reserved July 17, 2014 83 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-9. Interrupts (continued) 2.5.3 Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 44 28 0x0000.00B0 System Control Flash Memory Control 45 29 0x0000.00B4 46-52 30-36 - 53 37 0x0000.00D4 54 38 - 55 39 0x0000.00DC 56-58 40-42 - 59 43 0x0000.00EC Hibernation Module 60 44 0x0000.00F0 USB 61 45 - Reserved I2C1 Reserved CAN0 Reserved Reserved 62 46 0x0000.00F8 µDMA Software 63 47 0x0000.00FC µDMA Error Exception Handlers The processor handles exceptions using: ■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. ■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. ■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. 2.5.4 Vector Table The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in Table 2-8 on page 82. Figure 2-6 on page 85 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code 84 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 2-6. Vector Table Exception number IRQ number 63 47 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Offset 0x00FC . . . 0x004C 0x0048 0x0044 0x0040 0x003C 0x0038 12 11 Vector IRQ47 . . . IRQ2 IRQ1 IRQ0 Systick PendSV Reserved Reserved for Debug -5 10 0x002C 9 SVCall Reserved 8 7 6 -10 5 -11 4 -12 3 -13 2 -14 1 0x0018 0x0014 0x0010 0x000C 0x0008 0x0004 0x0000 Usage fault Bus fault Memory management fault Hard fault NMI Reset Initial SP value On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000.0100 to 0x3FFF.FF00 (see “Vector Table” on page 84). Note that when configuring the VTABLE register, the offset must be aligned on a 256-byte boundary. 2.5.5 Exception Priorities As Table 2-8 on page 82 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see page 134 and page 120. Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. July 17, 2014 85 Texas Instruments-Production Data The Cortex-M3 Processor If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 2.5.6 Interrupt Priority Grouping To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields: ■ An upper field that defines the group priority ■ A lower field that defines a subpriority within the group Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see page 128. 2.5.7 Exception Entry and Return Descriptions of exception handling use the following terms: ■ Preemption. When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” on page 86 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” on page 87 more information. ■ Return. Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” on page 88 for more information. ■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. ■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On 86 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.5.7.1 Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers (see PRIMASK on page 68, FAULTMASK on page 69, and BASEPRI on page 70). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to as stack frame. Figure 2-7. Exception Stack Frame ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack IRQ top of stack Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN bit of the Configuration Control (CCR) register is set, stack align adjustment is performed during stacking. The stack frame includes the return address, which is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. July 17, 2014 87 Texas Instruments-Production Data The Cortex-M3 Processor 2.5.7.2 Exception Return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: ■ An LDM or POP instruction that loads the PC ■ A BX instruction using any register ■ An LDR instruction with the PC as the destination EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest four bits of this value provide information on the return stack and processor mode. Table 2-10 on page 88 shows the EXC_RETURN values with a description of the exception return behavior. EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table 2-10. Exception Return Behavior EXC_RETURN[31:0] Description 0xFFFF.FFF0 Reserved 0xFFFF.FFF1 Return to Handler mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFF2 - 0xFFFF.FFF8 Reserved 0xFFFF.FFF9 Return to Thread mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFFA - 0xFFFF.FFFC Reserved 0xFFFF.FFFD Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. 0xFFFF.FFFE - 0xFFFF.FFFF 2.6 Reserved Fault Handling Faults are a subset of the exceptions (see “Exception Model” on page 80). The following conditions generate a fault: ■ A bus error on an instruction fetch or vector table load or a data access. ■ An internally detected error such as an undefined instruction or an attempt to change state with a BX instruction. ■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN). ■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region. 88 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 2.6.1 Fault Types Table 2-11 on page 89 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. See page 141 for more information about the fault status registers. Table 2-11. Faults Fault Handler Fault Status Register Bit Name Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) FORCED MPU or default memory mismatch on Memory management instruction access fault Memory Management Fault Status (MFAULTSTAT) IERR MPU or default memory mismatch on Memory management data access fault Memory Management Fault Status (MFAULTSTAT) DERR MPU or default memory mismatch on Memory management exception stacking fault Memory Management Fault Status (MFAULTSTAT) MSTKE MPU or default memory mismatch on Memory management exception unstacking fault Memory Management Fault Status (MFAULTSTAT) MUSTKE Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF Attempt to enter an invalid instruction Usage fault b set state Usage Fault Status (UFAULTSTAT) INVSTAT a Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0 a. Occurs on an access to an XN region even if the MPU is disabled. b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation. 2.6.2 Fault Escalation and Hard Faults All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on page 134). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on page 137). Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in “Exception Model” on page 80. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when: ■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. July 17, 2014 89 Texas Instruments-Production Data The Cortex-M3 Processor ■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. ■ An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. ■ A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: 2.6.3 Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-12 on page 90. Table 2-12. Fault Status and Fault Address Registers 2.6.4 Handler Status Register Name Address Register Name Register Description Hard fault Hard Fault Status (HFAULTSTAT) - page 147 Memory management Memory Management Fault Status fault (MFAULTSTAT) Memory Management Fault Address (MMADDR) page 141 Bus fault Bus Fault Status (BFAULTSTAT) Bus Fault Address (FAULTADDR) page 141 Usage fault Usage Fault Status (UFAULTSTAT) - page 141 page 148 page 149 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger. Note: 2.7 If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state. Power Management The Cortex-M3 processor sleep modes reduce power consumption: ■ Sleep mode stops the processor clock. ■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory. The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used (see page 130). For more information about the behavior of the sleep modes, see “System Control” on page 182. 90 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to Sleep mode and Deep-sleep mode. 2.7.1 Entering Sleep Modes This section describes the mechanisms software can use to put the processor into one of the sleep modes. The system can generate spurious wake-up events, for example a debug operation wakes up the processor. Therefore, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. 2.7.1.1 Wait for Interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 91). When the processor executes a WFI instruction, it stops executing instructions and enters sleep mode. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information. 2.7.1.2 Wait for Event The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes a WFE instruction, it checks the event register. If the register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction. Typically, this situation occurs if an SEV instruction has been executed. Software cannot access this register directly. See the Cortex™-M3/M4 Instruction Set Technical User's Manual for more information. 2.7.1.3 Sleep-on-Exit If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This mechanism can be used in applications that only require the processor to run when an exception occurs. 2.7.2 Wake Up from Sleep Mode The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode. 2.7.2.1 Wake Up from WFI or Sleep-on-Exit Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor clears PRIMASK. For more information about PRIMASK and FAULTMASK, see page 68 and page 69. 2.7.2.2 Wake Up from WFE The processor wakes up if it detects an exception with sufficient priority to cause exception entry. July 17, 2014 91 Texas Instruments-Production Data The Cortex-M3 Processor In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about SYSCTRL, see page 130. 2.8 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 92 lists the supported instructions. Note: In Table 2-13 on page 92: ■ ■ ■ ■ ■ Angle brackets, , enclose alternative forms of the operand Braces, {}, enclose optional operands The Operands column is not exhaustive Op2 is a flexible second operand that can be either a register or a constant Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions in the Cortex™-M3/M4 Instruction Set Technical User's Manual. Table 2-13. Cortex-M3 Instruction Summary Mnemonic Operands Brief Description Flags ADC, ADCS {Rd,} Rn, Op2 Add with carry N,Z,C,V ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V ADD, ADDW {Rd,} Rn , #imm12 Add N,Z,C,V ADR Rd, label Load PC-relative address - AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C ASR, ASRS Rd, Rm, Arithmetic shift right N,Z,C B label Branch - BFC Rd, #lsb, #width Bit field clear - BFI Rd, Rn, #lsb, #width Bit field insert - BIC, BICS {Rd,} Rn, Op2 Bit clear N,Z,C BKPT #imm Breakpoint - BL label Branch with link - BLX Rm Branch indirect with link - BX Rm Branch indirect - CBNZ Rn, label Compare and branch if non-zero - CBZ Rn, label Compare and branch if zero - CLREX - Clear exclusive - CLZ Rd, Rm Count leading zeros - CMN Rn, Op2 Compare negative N,Z,C,V CMP Rn, Op2 Compare N,Z,C,V CPSID i Change processor state, disable interrupts - CPSIE i Change processor state, enable interrupts - DMB - Data memory barrier - DSB - Data synchronization barrier - 92 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C ISB - Instruction synchronization barrier - IT - If-Then condition block - LDM Rn{!}, reglist Load multiple registers, increment after - LDMDB, LDMEA Rn{!}, reglist Load multiple registers, decrement before LDMFD, LDMIA Rn{!}, reglist Load multiple registers, increment after - LDR Rt, [Rn, #offset] Load register with word - LDRB, LDRBT Rt, [Rn, #offset] Load register with byte - LDRD Rt, Rt2, [Rn, #offset] Load register with two bytes - LDREX Rt, [Rn, #offset] Load register exclusive - LDREXB Rt, [Rn] Load register exclusive with byte - LDREXH Rt, [Rn] Load register exclusive with halfword - LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword - LDRSB, LDRSBT Rt, [Rn, #offset] Load register with signed byte - LDRSH, LDRSHT Rt, [Rn, #offset] Load register with signed halfword - LDRT Rt, [Rn, #offset] Load register with word - LSL, LSLS Rd, Rm, Logical shift left N,Z,C LSR, LSRS Rd, Rm, Logical shift right N,Z,C MLA Rd, Rn, Rm, Ra Multiply with accumulate, 32-bit result - MLS Rd, Rn, Rm, Ra Multiply and subtract, 32-bit result - MOV, MOVS Rd, Op2 Move N,Z,C MOV, MOVW Rd, #imm16 Move 16-bit constant N,Z,C MOVT Rd, #imm16 Move top - MRS Rd, spec_reg Move from special register to general register - MSR spec_reg, Rm Move from general register to special register N,Z,C,V MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z MVN, MVNS Rd, Op2 Move NOT N,Z,C NOP - No operation - ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C POP reglist Pop registers from stack - PUSH reglist Push registers onto stack - RBIT Rd, Rn Reverse bits - REV Rd, Rn Reverse byte order in a word - REV16 Rd, Rn Reverse byte order in each halfword - REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend - ROR, RORS Rd, Rm, Rotate right N,Z,C RRX, RRXS Rd, Rm Rotate right with extend N,Z,C July 17, 2014 - 93 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags RSB, RSBS {Rd,} Rn, Op2 Reverse subtract N,Z,C,V SBC, SBCS {Rd,} Rn, Op2 Subtract with carry N,Z,C,V SBFX Rd, Rn, #lsb, #width Signed bit field extract - SDIV {Rd,} Rn, Rm Signed divide - SEV - Send event - SMLAL RdLo, RdHi, Rn, Rm Signed multiply with accumulate (32x32+64), 64-bit result - SMULL RdLo, RdHi, Rn, Rm Signed multiply (32x32), 64-bit result - SSAT Rd, #n, Rm {,shift #s} Signed saturate Q STM Rn{!}, reglist Store multiple registers, increment after - STMDB, STMEA Rn{!}, reglist Store multiple registers, decrement before STMFD, STMIA Rn{!}, reglist Store multiple registers, increment after - STR Rt, [Rn {, #offset}] Store register word - STRB, STRBT Rt, [Rn {, #offset}] Store register byte - STRD Rt, Rt2, [Rn {, #offset}] Store register two words - STREX Rt, Rt, [Rn {, #offset}] Store register exclusive - STREXB Rd, Rt, [Rn] Store register exclusive byte - STREXH Rd, Rt, [Rn] Store register exclusive halfword - STRH, STRHT Rt, [Rn {, #offset}] Store register halfword - STRSB, STRSBT Rt, [Rn {, #offset}] Store register signed byte - STRSH, STRSHT Rt, [Rn {, #offset}] Store register signed halfword - STRT Rt, [Rn {, #offset}] Store register word - SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V SUB, SUBW {Rd,} Rn, #imm12 Subtract 12-bit constant N,Z,C,V SVC #imm Supervisor call - SXTB {Rd,} Rm {,ROR #n} Sign extend a byte - SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword - TBB [Rn, Rm] Table branch byte - TBH [Rn, Rm, LSL #1] Table branch halfword - TEQ Rn, Op2 Test equivalence N,Z,C TST Rn, Op2 Test N,Z,C UBFX Rd, Rn, #lsb, #width Unsigned bit field extract - UDIV {Rd,} Rn, Rm Unsigned divide - UMLAL RdLo, RdHi, Rn, Rm Unsigned multiply with accumulate (32x32+32+32), 64-bit result - UMULL RdLo, RdHi, Rn, Rm Unsigned multiply (32x 2), 64-bit result - USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q UXTB {Rd,} Rm, {,ROR #n} Zero extend a Byte - UXTH {Rd,} Rm, {,ROR #n} Zero extend a Halfword - WFE - Wait for event - WFI - Wait for interrupt - 94 - July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 3 Cortex-M3 Peripherals ® This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals, including: ■ SysTick (see page 95) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. ■ Nested Vectored Interrupt Controller (NVIC) (see page 96) – Facilitates low-latency exception and interrupt handling – Controls power management – Implements system control registers ■ System Control Block (SCB) (see page 98) Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. ■ Memory Protection Unit (MPU) (see page 98) Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. Table 3-1 on page 95 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed. Table 3-1. Core Peripheral Register Regions Address Core Peripheral Description (see page ...) 0xE000.E010-0xE000.E01F System Timer 95 0xE000.E100-0xE000.E4EF Nested Vectored Interrupt Controller 96 0xE000.ED00-0xE000.ED3F System Control Block 98 0xE000.ED90-0xE000.EDB8 Memory Protection Unit 98 0xE000.EF00-0xE000.EF03 3.1 Functional Description This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals: SysTick, NVIC, SCB and MPU. 3.1.1 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. July 17, 2014 95 Texas Instruments-Production Data Cortex-M3 Peripherals ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter used to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNT bit in the STCTRL control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. The timer consists of three registers: ■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the counter's wrap value. ■ SysTick Current Value (STCURRENT): The current value of the counter. When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter reaches zero, the COUNT status bit is set. The COUNT bit clears on reads. Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers. Note: 3.1.2 When the processor is halted for debugging, the counter does not decrement. Nested Vectored Interrupt Controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ■ 28 interrupts. ■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ■ Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). 96 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. 3.1.2.1 Level-Sensitive and Pulse Interrupts The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts” on page 97 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 3.1.2.2 Hardware and Software Control of Interrupts The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: ■ The NVIC detects that the interrupt signal is High and the interrupt is not active. ■ The NVIC detects a rising edge on the interrupt signal. ■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit in the PEND0 register on page 114 or SWTRIG on page 122. A pending interrupt remains pending until one of the following: ■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. ■ Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. July 17, 2014 97 Texas Instruments-Production Data Cortex-M3 Peripherals – For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. 3.1.3 System Control Block (SCB) The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. 3.1.4 Memory Protection Unit (MPU) This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines eight separate memory regions, 0-7, and a background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” on page 74 for more information). Table 3-2 on page 98 shows the possible MPU region attributes. See the section called “MPU Configuration for a Stellaris Microcontroller” on page 102 for guidelines for programming a microcontroller implementation. Table 3-2. Memory Attributes Summary Memory Type Description Strongly Ordered All accesses to Strongly Ordered memory occur in program order. Device Memory-mapped peripherals Normal Normal memory To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: ■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. 98 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. 3.1.4.1 Updating an MPU Region To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can be programmed separately or with a multiple-word write to program all of these registers. You can use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using an STM instruction. Updating an MPU Region Using Separate Words This example simple code configures one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER STR R1, [R0, #0x0] STR R4, [R0, #0x4] STRH R2, [R0, #0x8] STRH R3, [R0, #0xA] ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Region Base Address Region Size and Enable Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER STR R1, [R0, #0x0] BIC R2, R2, #1 STRH R2, [R0, #0x8] STR R4, [R0, #0x4] STRH R3, [R0, #0xA] ORR R2, #1 STRH R2, [R0, #0x8] ; ; ; ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Disable Region Size and Enable Region Base Address Region Attribute Enable Region Size and Enable Software must use memory barrier instructions: ■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings. ■ After MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region. July 17, 2014 99 Texas Instruments-Production Data Cortex-M3 Peripherals For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is required after changing MPU settings, such as at the end of context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISB is not required. Updating an MPU Region Using Multi-Word Writes The MPU can be programmed directly using multi-word writes, depending how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region number, address, attribute, size and enable This operation can be done in two words for pre-packed information, meaning that the MPU Region Base Address (MPUBASE) register (see page 154) contains the required region number and has the VALID bit set. This method can be used when the data is statically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and region number combined ; with VALID (bit 4) set STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 156) to disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the most-significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be configured to 0x00, otherwise the MPU behavior is unpredictable. 100 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Example of SRD Use Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 101 shows. Figure 3-1. SRD Use Example Region 2, with subregions Region 1 Base address of both regions 3.1.4.2 Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB Disabled subregion 64KB Disabled subregion 0 MPU Access Permission Attributes The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 3-3 on page 101 shows the encodings for the TEX, C, B, and S access permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M3 does not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration for a Stellaris Microcontroller” on page 102 for information on programming the MPU for Stellaris implementations. Table 3-3. TEX, S, C, and B Bit Field Encoding TEX S 000b x C B Memory Type Shareability Other Attributes a 0 0 Strongly Ordered Shareable - a - 000 x 0 1 Device Shareable 000 0 1 0 Normal Not shareable 000 1 1 0 Normal Shareable 000 0 1 1 Normal Not shareable 000 1 1 1 Normal Shareable 001 0 0 0 Normal Not shareable 001 1 0 0 Normal Shareable Outer and inner noncacheable. 001 x a 0 1 Reserved encoding - - a Outer and inner write-through. No write allocate. 001 x 1 0 Reserved encoding - - 001 0 1 1 Normal Not shareable 001 1 1 1 Normal Shareable Outer and inner write-back. Write and read allocate. 010 x a 0 0 Device Not shareable Nonshared Device. a 0 1 Reserved encoding - - a 1 x Reserved encoding - - 010 x 010 x a July 17, 2014 101 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-3. TEX, S, C, and B Bit Field Encoding (continued) TEX S C B Memory Type Shareability Other Attributes 1BB 0 A A Normal Not shareable 1BB 1 A A Normal Shareable Cached memory (BB = outer policy, AA = inner policy). See Table 3-4 for the encoding of the AA and BB bits. a. The MPU ignores the value of this bit. Table 3-4 on page 102 shows the cache policy for memory attribute encodings with a TEX value in the range of 0x4-0x7. Table 3-4. Cache Policy for Memory Attribute Encoding Encoding, AA or BB Corresponding Cache Policy 00 Non-cacheable 01 Write back, write and read allocate 10 Write through, no write allocate 11 Write back, no write allocate Table 3-5 on page 102 shows the AP encodings in the MPUATTR register that define the access permissions for privileged and unprivileged software. Table 3-5. AP Bit Field Encoding AP Bit Field Privileged Permissions Unprivileged Permissions Description 000 No access No access All accesses generate a permission fault. 001 R/W No access Access from privileged software only. 010 R/W RO Writes by unprivileged software generate a permission fault. 011 R/W R/W Full access. 100 Unpredictable Unpredictable Reserved. 101 RO No access Reads by privileged software only. 110 RO RO Read-only, by privileged or unprivileged software. 111 RO RO Read-only, by privileged or unprivileged software. MPU Configuration for a Stellaris Microcontroller Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 102. Table 3-6. Memory Region Attributes for Stellaris Microcontrollers Memory Region TEX S C B Memory Type and Attributes Flash memory 000b 0 1 0 Normal memory, non-shareable, write-through Internal SRAM 000b 1 1 0 Normal memory, shareable, write-through External SRAM 000b 1 1 1 Normal memory, shareable, write-back, write-allocate Peripherals 000b 1 0 1 Device memory, shareable 102 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller In current Stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. 3.1.4.3 MPU Mismatch When an access violates the MPU permissions, the processor generates a memory management fault (see “Exceptions and Interrupts” on page 72 for more information). The MFAULTSTAT register indicates the cause of the fault. See page 141 for more information. 3.2 Register Map Table 3-7 on page 103 lists the Cortex-M3 Peripheral SysTick, NVIC, MPU and SCB registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note: Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table 3-7. Peripherals Register Map Offset Name Type Reset Description See page System Timer (SysTick) Registers 0x010 STCTRL R/W 0x0000.0000 SysTick Control and Status Register 106 0x014 STRELOAD R/W 0x0000.0000 SysTick Reload Value Register 108 0x018 STCURRENT R/WC 0x0000.0000 SysTick Current Value Register 109 Nested Vectored Interrupt Controller (NVIC) Registers 0x100 EN0 R/W 0x0000.0000 Interrupt 0-31 Set Enable 110 0x104 EN1 R/W 0x0000.0000 Interrupt 32-47 Set Enable 111 0x180 DIS0 R/W 0x0000.0000 Interrupt 0-31 Clear Enable 112 0x184 DIS1 R/W 0x0000.0000 Interrupt 32-47 Clear Enable 113 0x200 PEND0 R/W 0x0000.0000 Interrupt 0-31 Set Pending 114 0x204 PEND1 R/W 0x0000.0000 Interrupt 32-47 Set Pending 115 0x280 UNPEND0 R/W 0x0000.0000 Interrupt 0-31 Clear Pending 116 0x284 UNPEND1 R/W 0x0000.0000 Interrupt 32-47 Clear Pending 117 0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0-31 Active Bit 118 0x304 ACTIVE1 RO 0x0000.0000 Interrupt 32-47 Active Bit 119 0x400 PRI0 R/W 0x0000.0000 Interrupt 0-3 Priority 120 0x404 PRI1 R/W 0x0000.0000 Interrupt 4-7 Priority 120 0x408 PRI2 R/W 0x0000.0000 Interrupt 8-11 Priority 120 0x40C PRI3 R/W 0x0000.0000 Interrupt 12-15 Priority 120 0x410 PRI4 R/W 0x0000.0000 Interrupt 16-19 Priority 120 July 17, 2014 103 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-7. Peripherals Register Map (continued) Description See page Offset Name Type Reset 0x414 PRI5 R/W 0x0000.0000 Interrupt 20-23 Priority 120 0x418 PRI6 R/W 0x0000.0000 Interrupt 24-27 Priority 120 0x41C PRI7 R/W 0x0000.0000 Interrupt 28-31 Priority 120 0x420 PRI8 R/W 0x0000.0000 Interrupt 32-35 Priority 120 0x424 PRI9 R/W 0x0000.0000 Interrupt 36-39 Priority 120 0x428 PRI10 R/W 0x0000.0000 Interrupt 40-43 Priority 120 0x42C PRI11 R/W 0x0000.0000 Interrupt 44-47 Priority 120 0xF00 SWTRIG WO 0x0000.0000 Software Trigger Interrupt 122 System Control Block (SCB) Registers 0xD00 CPUID RO 0x411F.C231 CPU ID Base 123 0xD04 INTCTRL R/W 0x0000.0000 Interrupt Control and State 124 0xD08 VTABLE R/W 0x0000.0000 Vector Table Offset 127 0xD0C APINT R/W 0xFA05.0000 Application Interrupt and Reset Control 128 0xD10 SYSCTRL R/W 0x0000.0000 System Control 130 0xD14 CFGCTRL R/W 0x0000.0000 Configuration and Control 132 0xD18 SYSPRI1 R/W 0x0000.0000 System Handler Priority 1 134 0xD1C SYSPRI2 R/W 0x0000.0000 System Handler Priority 2 135 0xD20 SYSPRI3 R/W 0x0000.0000 System Handler Priority 3 136 0xD24 SYSHNDCTRL R/W 0x0000.0000 System Handler Control and State 137 0xD28 FAULTSTAT R/W1C 0x0000.0000 Configurable Fault Status 141 0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 147 0xD34 MMADDR R/W - Memory Management Fault Address 148 0xD38 FAULTADDR R/W - Bus Fault Address 149 Memory Protection Unit (MPU) Registers 0xD90 MPUTYPE RO 0x0000.0800 MPU Type 150 0xD94 MPUCTRL R/W 0x0000.0000 MPU Control 151 0xD98 MPUNUMBER R/W 0x0000.0000 MPU Region Number 153 0xD9C MPUBASE R/W 0x0000.0000 MPU Region Base Address 154 0xDA0 MPUATTR R/W 0x0000.0000 MPU Region Attribute and Size 156 0xDA4 MPUBASE1 R/W 0x0000.0000 MPU Region Base Address Alias 1 154 0xDA8 MPUATTR1 R/W 0x0000.0000 MPU Region Attribute and Size Alias 1 156 0xDAC MPUBASE2 R/W 0x0000.0000 MPU Region Base Address Alias 2 154 104 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 3-7. Peripherals Register Map (continued) Name Type Reset 0xDB0 MPUATTR2 R/W 0x0000.0000 MPU Region Attribute and Size Alias 2 156 0xDB4 MPUBASE3 R/W 0x0000.0000 MPU Region Base Address Alias 3 154 0xDB8 MPUATTR3 R/W 0x0000.0000 MPU Region Attribute and Size Alias 3 156 3.3 Description See page Offset System Timer (SysTick) Register Descriptions This section lists and describes the System Timer registers, in numerical order by address offset. July 17, 2014 105 Texas Instruments-Production Data Cortex-M3 Peripherals Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 Note: This register can only be accessed from privileged mode. The SysTick STCTRL register enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 16 COUNT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 CLK_SRC INTEN ENABLE R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 COUNT RO 0 Count Flag Value Description 0 The SysTick timer has not counted to 0 since the last time this bit was read. 1 The SysTick timer has counted to 0 since the last time this bit was read. This bit is cleared by a read of the register or if the STCURRENT register is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in the AHB-AP Control Register is clear. Otherwise, the COUNT bit is not changed by the debugger read. See the ARM® Debug Interface V5 Architecture Specification for more information on MasterType. 15:3 reserved RO 0x000 2 CLK_SRC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Source Value Description 0 External reference clock. (Not implemented for most Stellaris microcontrollers.) 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. 106 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 1 INTEN R/W 0 0 ENABLE R/W 0 Description Interrupt Enable Value Description 0 Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. 1 An interrupt is generated to the NVIC when SysTick counts to 0. Enable Value Description 0 The counter is disabled. 1 Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. July 17, 2014 107 Texas Instruments-Production Data Cortex-M3 Peripherals Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 Note: This register can only be accessed from privileged mode. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD field. SysTick Reload Value Register (STRELOAD) Base 0xE000.E000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 RO 0 RO 0 RO 0 RO 0 15 14 13 R/W 0 R/W 0 R/W 0 27 26 25 24 23 22 21 20 18 17 16 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 19 RELOAD RELOAD Type Reset Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 RELOAD R/W 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. 108 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 Note: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000 Offset 0x018 Type R/WC, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 reserved Type Reset 20 19 18 17 16 CURRENT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 CURRENT Type Reset R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 CURRENT R/WC 0x00.0000 Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. 3.4 NVIC Register Descriptions This section lists and describes the NVIC registers, in numerical order by address offset. The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any other unprivileged mode access causes a bus fault. Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An interrupt can enter the pending state even if it is disabled. Before programming the VTABLE register to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For more information, see page 127. July 17, 2014 109 Texas Instruments-Production Data Cortex-M3 Peripherals Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 Note: This register can only be accessed from privileged mode. The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 83 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 0-31 Set Enable (EN0) Base 0xE000.E000 Offset 0x100 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 INT R/W R/W 0 Reset R/W 0 Description 0x0000.0000 Interrupt Enable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. 110 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 5: Interrupt 32-47 Set Enable (EN1), offset 0x104 Note: This register can only be accessed from privileged mode. The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 32; bit 15 corresponds to Interrupt 47. See Table 2-9 on page 83 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 32-47 Set Enable (EN1) Base 0xE000.E000 Offset 0x104 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset INT Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 INT R/W 0x0.0000 Interrupt Enable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. July 17, 2014 111 Texas Instruments-Production Data Cortex-M3 Peripherals Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 Note: This register can only be accessed from privileged mode. The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 83 for interrupt assignments. Interrupt 0-31 Clear Enable (DIS0) Base 0xE000.E000 Offset 0x180 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. 112 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 7: Interrupt 32-47 Clear Enable (DIS1), offset 0x184 Note: This register can only be accessed from privileged mode. The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 15 corresponds to Interrupt 47. See Table 2-9 on page 83 for interrupt assignments. Interrupt 32-47 Clear Enable (DIS1) Base 0xE000.E000 Offset 0x184 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 INT R/W 0x0.0000 Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. July 17, 2014 113 Texas Instruments-Production Data Cortex-M3 Peripherals Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 Note: This register can only be accessed from privileged mode. The PEND0 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 83 for interrupt assignments. Interrupt 0-31 Set Pending (PEND0) Base 0xE000.E000 Offset 0x200 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Set Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. 114 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 9: Interrupt 32-47 Set Pending (PEND1), offset 0x204 Note: This register can only be accessed from privileged mode. The PEND1 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 32; bit 15 corresponds to Interrupt 47. See Table 2-9 on page 83 for interrupt assignments. Interrupt 32-47 Set Pending (PEND1) Base 0xE000.E000 Offset 0x204 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 INT R/W 0x0.0000 Interrupt Set Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. July 17, 2014 115 Texas Instruments-Production Data Cortex-M3 Peripherals Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 Note: This register can only be accessed from privileged mode. The UNPEND0 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 83 for interrupt assignments. Interrupt 0-31 Clear Pending (UNPEND0) Base 0xE000.E000 Offset 0x280 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 116 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 11: Interrupt 32-47 Clear Pending (UNPEND1), offset 0x284 Note: This register can only be accessed from privileged mode. The UNPEND1 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 32; bit 15 corresponds to Interrupt 47. See Table 2-9 on page 83 for interrupt assignments. Interrupt 32-47 Clear Pending (UNPEND1) Base 0xE000.E000 Offset 0x284 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 INT R/W 0x0.0000 Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. July 17, 2014 117 Texas Instruments-Production Data Cortex-M3 Peripherals Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 Note: This register can only be accessed from privileged mode. The ACTIVE0 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 83 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 0-31 Active Bit (ACTIVE0) Base 0xE000.E000 Offset 0x300 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT RO Reset Description 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. 118 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 13: Interrupt 32-47 Active Bit (ACTIVE1), offset 0x304 Note: This register can only be accessed from privileged mode. The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit 15 corresponds to Interrupt 47. See Table 2-9 on page 83 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 32-47 Active Bit (ACTIVE1) Base 0xE000.E000 Offset 0x304 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 INT Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 INT RO 0x0.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. July 17, 2014 119 Texas Instruments-Production Data Cortex-M3 Peripherals Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 Register 25: Interrupt 44-47 Priority (PRI11), offset 0x42C Note: This register can only be accessed from privileged mode. The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: PRIn Register Bit Field Interrupt Bits 31:29 Interrupt [4n+3] Bits 23:21 Interrupt [4n+2] Bits 15:13 Interrupt [4n+1] Bits 7:5 Interrupt [4n] See Table 2-9 on page 83 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register (see page 128) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 INTD Type Reset R/W 0 15 R/W 0 R/W 0 RO 0 RO 0 14 13 12 11 INTB Type Reset R/W 0 R/W 0 26 25 24 23 reserved RO 0 RO 0 RO 0 R/W 0 10 9 8 7 reserved R/W 0 RO 0 RO 0 RO 0 22 21 20 19 INTC R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 INTA RO 0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 120 RO 0 RO 0 RO 0 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 31:29 INTD R/W 0x0 Description Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 INTC R/W 0x0 Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 INTB R/W 0x0 Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 INTA R/W 0x0 Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 121 Texas Instruments-Production Data Cortex-M3 Peripherals Register 26: Software Trigger Interrupt (SWTRIG), offset 0xF00 Note: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). See Table 2-9 on page 83 for interrupt assignments. When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 132) is set, unprivileged software can access the SWTRIG register. Software Trigger Interrupt (SWTRIG) Base 0xE000.E000 Offset 0xF00 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 INTID Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:0 INTID WO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. 3.5 System Control Block (SCB) Register Descriptions This section lists and describes the System Control Block (SCB) registers, in numerical order by address offset. The SCB registers can only be accessed from privileged mode. All registers must be accessed with aligned word accesses except for the FAULTSTAT and SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. 122 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 27: CPU ID Base (CPUID), offset 0xD00 Note: This register can only be accessed from privileged mode. The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x411F.C231 31 30 29 28 27 26 25 24 23 22 IMP Type Reset 21 20 19 18 VAR RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PARTNO Type Reset RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 17 16 RO 1 RO 1 1 0 RO 0 RO 1 CON REV RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 IMP RO 0x41 Implementer Code RO 1 RO 1 RO 0 RO 0 Value Description 0x41 ARM 23:20 VAR RO 0x1 Variant Number Value Description 0x1 19:16 CON RO 0xF The rn value in the rnpn product revision identifier, for example, the 1 in r1p1. Constant Value Description 0xF 15:4 PARTNO RO 0xC23 Always reads as 0xF. Part Number Value Description 0xC23 Cortex-M3 processor. 3:0 REV RO 0x1 Revision Number Value Description 0x1 The pn value in the rnpn product revision identifier, for example, the 1 in r1p1. July 17, 2014 123 Texas Instruments-Production Data Cortex-M3 Peripherals Register 28: Interrupt Control and State (INTCTRL), offset 0xD04 Note: This register can only be accessed from privileged mode. The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits. Interrupt Control and State (INTCTRL) Base 0xE000.E000 Offset 0xD04 Type R/W, reset 0x0000.0000 31 NMISET Type Reset 30 29 reserved 28 26 PENDSV UNPENDSV 25 PENDSTSET PENDSTCLR 24 reserved 23 22 21 ISRPRE ISRPEND 20 19 18 reserved 17 16 VECPEND R/W 0 RO 0 RO 0 R/W 0 WO 0 R/W 0 WO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 VECPEND Type Reset 27 RO 0 RETBASE RO 0 reserved RO 0 Bit/Field Name Type Reset 31 NMISET R/W 0 VECACT RO 0 Description NMI Set Pending Value Description 0 On a read, indicates an NMI exception is not pending. On a write, no effect. 1 On a read, indicates an NMI exception is pending. On a write, changes the NMI exception state to pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 30:29 reserved RO 0x0 28 PENDSV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PendSV Set Pending Value Description 0 On a read, indicates a PendSV exception is not pending. On a write, no effect. 1 On a read, indicates a PendSV exception is pending. On a write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to the UNPENDSV bit. 124 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 27 UNPENDSV WO 0 Description PendSV Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the PendSV exception. This bit is write only; on a register read, its value is unknown. 26 PENDSTSET R/W 0 SysTick Set Pending Value Description 0 On a read, indicates a SysTick exception is not pending. On a write, no effect. 1 On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception state to pending. This bit is cleared by writing a 1 to the PENDSTCLR bit. 25 PENDSTCLR WO 0 SysTick Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the SysTick exception. This bit is write only; on a register read, its value is unknown. 24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23 ISRPRE RO 0 Debug Interrupt Handling Value Description 0 The release from halt does not take an interrupt. 1 The release from halt takes an interrupt. This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. 22 ISRPEND RO 0 Interrupt Pending Value Description 0 No interrupt is pending. 1 An interrupt is pending. This bit provides status for all interrupts excluding NMI and Faults. 21:19 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 125 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description 18:12 VECPEND RO 0x00 Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. Value Description 0x00 No exceptions are pending 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x3F Interrupt Vector 47 0x40-0x7F Reserved 11 RETBASE RO 0 Return to Base Value Description 0 There are preempted active exceptions to execute. 1 There are no active exceptions, or the currently executing exception is the only active exception. This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero). 10:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:0 VECACT RO 0x00 Interrupt Pending Vector Number This field contains the active exception number. The exception numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 64). 126 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 29: Vector Table Offset (VTABLE), offset 0xD08 Note: This register can only be accessed from privileged mode. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type R/W, reset 0x0000.0000 31 30 reserved Type Reset 29 28 27 26 25 24 23 BASE 22 21 20 19 18 17 16 OFFSET RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 OFFSET Type Reset R/W 0 R/W 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:30 reserved RO 0x0 29 BASE R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Vector Table Base Value Description 28:8 OFFSET R/W 0x000.00 0 The vector table is in the code memory region. 1 The vector table is in the SRAM memory region. Vector Table Offset When configuring the OFFSET field, the offset must be aligned to the number of exception entries in the vector table. Because there are 47 interrupts, the offset must be aligned on a 256-byte boundary. 7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 127 Texas Instruments-Production Data Cortex-M3 Peripherals Register 30: Application Interrupt and Reset Control (APINT), offset 0xD0C Note: This register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored. The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table 3-8 on page 128 shows how the PRIGROUP value controls this split. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29. Note: Determining preemption of an exception uses only the group priority field. Table 3-8. Interrupt Priority Levels a PRIGROUP Bit Field Binary Point Group Priority Field Subpriority Field Group Priorities Subpriorities 0x0 - 0x4 bxxx. [7:5] None 8 1 0x5 bxx.y [7:6] [5] 4 2 0x6 bx.yy [7] [6:5] 2 4 0x7 b.yyy None [7:5] 1 8 a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. Application Interrupt and Reset Control (APINT) Base 0xE000.E000 Offset 0xD0C Type R/W, reset 0xFA05.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 5 4 3 2 1 0 VECTKEY Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 15 14 13 12 11 10 reserved ENDIANESS Type Reset RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 0 R/W 0 R/W 0 9 8 7 6 PRIGROUP RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 VECTKEY R/W 0xFA05 reserved R/W 0 RO 0 RO 0 RO 0 SYSRESREQ VECTCLRACT VECTRESET RO 0 RO 0 WO 0 WO 0 WO 0 Description Register Key This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. 15 ENDIANESS RO 0 Data Endianess The Stellaris implementation uses only little-endian mode so this is cleared to 0. 14:11 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 128 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 10:8 PRIGROUP R/W 0x0 Description Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-8 on page 128 for more information). 7:3 reserved RO 0x0 2 SYSRESREQ WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Reset Request Value Description 0 No effect. 1 Resets the core and all on-chip peripherals except the Debug interface. This bit is automatically cleared during the reset of the core and reads as 0. 1 VECTCLRACT WO 0 Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 0 VECTRESET WO 0 System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. July 17, 2014 129 Texas Instruments-Production Data Cortex-M3 Peripherals Register 31: System Control (SYSCTRL), offset 0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.00 4 SEVONPEND R/W 0 RO 0 RO 0 RO 0 RO 0 4 3 SEVONPEND reserved R/W 0 RO 0 SLEEPDEEP SLEEPEXIT R/W 0 R/W 0 0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Wake Up on Pending Value Description 0 Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor. When an event or interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of a SEV instruction or an external event. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 SLEEPDEEP R/W 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. 130 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 1 SLEEPEXIT R/W 0 Description Sleep on ISR Exit Value Description 0 When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. 1 When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 131 Texas Instruments-Production Data Cortex-M3 Peripherals Register 32: Configuration and Control (CFGCTRL), offset 0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 122). Configuration and Control (CFGCTRL) Base 0xE000.E000 Offset 0xD14 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 reserved STKALIGN BFHFNMIGN RO 0 RO 0 R/W 0 Bit/Field Name Type Reset 31:10 reserved RO 0x0000.00 9 STKALIGN R/W 0 R/W 0 RO 0 RO 0 RO 0 4 3 DIV0 UNALIGNED R/W 0 R/W 0 reserved MAINPEND BASETHR RO 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Stack Alignment on Exception Entry Value Description 0 The stack is 4-byte aligned. 1 The stack is 8-byte aligned. On exception entry, the processor uses bit 9 of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 8 BFHFNMIGN R/W 0 Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK escalated handlers. Value Description 0 Data bus faults caused by load and store instructions cause a lock-up. 1 Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 132 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 4 DIV0 R/W 0 Description Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. Value Description 3 UNALIGNED R/W 0 0 Do not trap on divide by 0. A divide by zero returns a quotient of 0. 1 Trap on divide by 0. Trap on Unaligned Access Value Description 0 Do not trap on unaligned halfword and word accesses. 1 Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 MAINPEND R/W 0 Allow Main Interrupt Trigger Value Description 0 BASETHR R/W 0 0 Disables unprivileged software access to the SWTRIG register. 1 Enables unprivileged software access to the SWTRIG register (see page 122). Thread State Control Value Description 0 The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 88 for more information). July 17, 2014 133 Texas Instruments-Production Data Cortex-M3 Peripherals Register 33: System Handler Priority 1 (SYSPRI1), offset 0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 reserved Type Reset RO 0 15 RO 0 RO 0 RO 0 RO 0 14 13 12 11 BUS Type Reset R/W 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 10 9 8 7 reserved R/W 0 RO 0 22 21 20 19 USAGE RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 MEM RO 0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 USAGE R/W 0x0 Usage Fault Priority This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 BUS R/W 0x0 Bus Fault Priority This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 MEM R/W 0x0 Memory Management Fault Priority This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 134 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 34: System Handler Priority 2 (SYSPRI2), offset 0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 SVC Type Reset 22 21 20 19 18 17 16 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:29 SVC R/W 0x0 RO 0 Description SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 28:0 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 135 Texas Instruments-Production Data Cortex-M3 Peripherals Register 35: System Handler Priority 3 (SYSPRI3), offset 0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type R/W, reset 0x0000.0000 31 30 29 28 27 TICK Type Reset 26 25 24 23 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 22 21 20 19 PENDSV R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 DEBUG RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:29 TICK R/W 0x0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 RO 0 RO 0 RO 0 Description SysTick Exception Priority This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority. 28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 PENDSV R/W 0x0 PendSV Priority This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority. 20:8 reserved RO 0x000 7:5 DEBUG R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. 4:0 reserved RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 136 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 36: System Handler Control and State (SYSHNDCTRL), offset 0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. Caution – Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified. System Handler Control and State (SYSHNDCTRL) Base 0xE000.E000 Offset 0xD24 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 SVC BUSP MEMP USAGEP R/W 0 R/W 0 R/W 0 R/W 0 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 USAGE BUS MEM R/W 0 R/W 0 R/W 0 10 9 8 7 6 5 4 3 2 1 0 TICK PNDSV reserved MON SVCA R/W 0 R/W 0 RO 0 R/W 0 R/W 0 USGA reserved BUSA MEMA R/W 0 RO 0 R/W 0 R/W 0 reserved Type Reset Type Reset reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 USAGE R/W 0 Usage Fault Enable Value Description 17 BUS R/W 0 0 Disables the usage fault exception. 1 Enables the usage fault exception. Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. July 17, 2014 137 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 16 MEM R/W 0 Description Memory Management Fault Enable Value Description 15 SVC R/W 0 0 Disables the memory management fault exception. 1 Enables the memory management fault exception. SVC Call Pending Value Description 0 An SVC call exception is not pending. 1 An SVC call exception is pending. This bit can be modified to change the pending status of the SVC call exception. 14 BUSP R/W 0 Bus Fault Pending Value Description 0 A bus fault exception is not pending. 1 A bus fault exception is pending. This bit can be modified to change the pending status of the bus fault exception. 13 MEMP R/W 0 Memory Management Fault Pending Value Description 0 A memory management fault exception is not pending. 1 A memory management fault exception is pending. This bit can be modified to change the pending status of the memory management fault exception. 12 USAGEP R/W 0 Usage Fault Pending Value Description 0 A usage fault exception is not pending. 1 A usage fault exception is pending. This bit can be modified to change the pending status of the usage fault exception. 11 TICK R/W 0 SysTick Exception Active Value Description 0 A SysTick exception is not active. 1 A SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. 138 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 10 PNDSV R/W 0 Description PendSV Exception Active Value Description 0 A PendSV exception is not active. 1 A PendSV exception is active. This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 MON R/W 0 Debug Monitor Active Value Description 7 SVCA R/W 0 0 The Debug monitor is not active. 1 The Debug monitor is active. SVC Call Active Value Description 0 SVC call is not active. 1 SVC call is active. This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit. 6:4 reserved RO 0x0 3 USGA R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Usage Fault Active Value Description 0 Usage fault is not active. 1 Usage fault is active. This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BUSA R/W 0 Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. July 17, 2014 139 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 0 MEMA R/W 0 Description Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. 140 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 37: Configurable Fault Status (FAULTSTAT), offset 0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: ■ Usage Fault Status (UFAULTSTAT), bits 31:16 ■ Bus Fault Status (BFAULTSTAT), bits 15:8 ■ Memory Management Fault Status (MFAULTSTAT), bits 7:0 FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows: ■ ■ ■ ■ ■ The complete FAULTSTAT register, with a word access to offset 0xD28 The MFAULTSTAT, with a byte access to offset 0xD28 The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28 The BFAULTSTAT, with a byte access to offset 0xD29 The UFAULTSTAT, with a halfword access to offset 0xD2A Bits are cleared by writing a 1 to them. In a fault handler, the true faulting address can be determined by: 1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address (FAULTADDR) value. 2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the MMADDR or FAULTADDR contents are valid. Software must follow this sequence because another higher priority exception might change the MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the MMADDR or FAULTADDR value. Configurable Fault Status (FAULTSTAT) Base 0xE000.E000 Offset 0xD28 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 reserved Type Reset RO 0 RO 0 RO 0 15 14 13 BFARV Type Reset R/W1C 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 25 24 DIV0 UNALIGN R/W1C 0 R/W1C 0 23 22 21 20 reserved RO 0 RO 0 RO 0 6 5 12 11 10 9 8 7 BSTKE BUSTKE IMPRE PRECISE IBUS MMARV R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved RO 0 RO 0 RO 0 4 MSTKE R/W1C 0 19 18 17 16 NOCP INVPC INVSTAT UNDEF R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 3 2 MUSTKE reserved R/W1C 0 RO 0 1 0 DERR IERR R/W1C 0 R/W1C 0 Bit/Field Name Type Reset Description 31:26 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 141 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 25 DIV0 R/W1C 0 Description Divide-by-Zero Usage Fault Value Description 0 No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 1 The processor has executed an SDIV or UDIV instruction with a divisor of 0. When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the Configuration and Control (CFGCTRL) register (see page 132). This bit is cleared by writing a 1 to it. 24 UNALIGN R/W1C 0 Unaligned Access Usage Fault Value Description 0 No unaligned access fault has occurred, or unaligned access trapping is not enabled. 1 The processor has made an unaligned memory access. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting the UNALIGNED bit in the CFGCTRL register (see page 132). This bit is cleared by writing a 1 to it. 23:20 reserved RO 0x00 19 NOCP R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. No Coprocessor Usage Fault Value Description 0 A usage fault has not been caused by attempting to access a coprocessor. 1 The processor has attempted to access a coprocessor. This bit is cleared by writing a 1 to it. 18 INVPC R/W1C 0 Invalid PC Load Usage Fault Value Description 0 A usage fault has not been caused by attempting to load an invalid PC value. 1 The processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing a 1 to it. 142 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 17 INVSTAT R/W1C 0 Description Invalid State Usage Fault Value Description 0 A usage fault has not been caused by an invalid state. 1 The processor has attempted to execute an instruction that makes illegal use of the EPSR register. When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register. This bit is not set if an undefined instruction uses the EPSR register. This bit is cleared by writing a 1 to it. 16 UNDEF R/W1C 0 Undefined Instruction Usage Fault Value Description 0 A usage fault has not been caused by an undefined instruction. 1 The processor has attempted to execute an undefined instruction. When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it. 15 BFARV R/W1C 0 Bus Fault Address Register Valid Value Description 0 The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address. 1 The FAULTADDR register is holding a valid fault address. This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 14:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 143 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 12 BSTKE R/W1C 0 Description Stack Bus Fault Value Description 0 No bus fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 11 BUSTKE R/W1C 0 Unstack Bus Fault Value Description 0 No bus fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more bus faults. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 10 IMPRE R/W1C 0 Imprecise Data Bus Error Value Description 0 An imprecise data bus error has not occurred. 1 A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When this bit is set, a fault address is not written to the FAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the IMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it. 9 PRECISE R/W1C 0 Precise Data Bus Error Value Description 0 A precise data bus error has not occurred. 1 A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When this bit is set, the fault address is written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 144 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 8 IBUS R/W1C 0 Description Instruction Bus Error Value Description 0 An instruction bus error has not occurred. 1 An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 7 MMARV R/W1C 0 Memory Management Fault Address Register Valid Value Description 0 The value in the Memory Management Fault Address (MMADDR) register is not a valid fault address. 1 The MMADDR register is holding a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 6:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 MSTKE R/W1C 0 Stack Access Violation Value Description 0 No memory management fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more access violations. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. July 17, 2014 145 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 3 MUSTKE R/W1C 0 Description Unstack Access Violation Value Description 0 No memory management fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more access violations. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 DERR R/W1C 0 Data Access Violation Value Description 0 A data access violation has not occurred. 1 The processor attempted a load or store at a location that does not permit the operation. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register. This bit is cleared by writing a 1 to it. 0 IERR R/W1C 0 Instruction Access Violation Value Description 0 An instruction access violation has not occurred. 1 The processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 146 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 38: Hard Fault Status (HFAULTSTAT), offset 0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type R/W1C, reset 0x0000.0000 Type Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBG FORCED R/W1C 0 R/W1C 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VECT reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 RO 0 reserved Type Reset Bit/Field Name Type Reset 31 DBG R/W1C 0 Description Debug Event This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable. 30 FORCED R/W1C 0 Forced Hard Fault Value Description 0 No forced hard fault has occurred. 1 A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it. 29:2 reserved RO 0x00 1 VECT R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Vector Table Read Fault Value Description 0 No bus fault has occurred on a vector table read. 1 A bus fault occurred on a vector table read. This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 147 Texas Instruments-Production Data Cortex-M3 Peripherals Register 39: Memory Management Fault Address (MMADDR), offset 0xD34 Note: This register can only be accessed from privileged mode. The MMADDR register contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in the MMADDR register is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Bits in the Memory Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether the value in the MMADDR register is valid (see page 141). Memory Management Fault Address (MMADDR) Base 0xE000.E000 Offset 0xD34 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. 148 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 40: Bus Fault Address (FAULTADDR), offset 0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDR register contains the address of the location that generated a bus fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT) register indicate the cause of the fault and whether the value in the FAULTADDR register is valid (see page 141). Bus Fault Address (FAULTADDR) Base 0xE000.E000 Offset 0xD38 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. 3.6 Memory Protection Unit (MPU) Register Descriptions This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset. The MPU registers can only be accessed from privileged mode. July 17, 2014 149 Texas Instruments-Production Data Cortex-M3 Peripherals Register 41: MPU Type (MPUTYPE), offset 0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.0800 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 DREGION Type Reset RO 0 RO 0 RO 0 RO 0 19 18 17 16 RO 0 IREGION RO 0 RO 0 RO 0 RO 0 4 3 2 1 reserved RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 0 SEPARATE RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 IREGION RO 0x00 Number of I Regions This field indicates the number of supported MPU instruction regions. This field always contains 0x00. The MPU memory map is unified and is described by the DREGION field. 15:8 DREGION RO 0x08 Number of D Regions Value Description 0x08 Indicates there are eight supported MPU data regions. 7:1 reserved RO 0x00 0 SEPARATE RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Separate or Unified MPU Value Description 0 Indicates the MPU is unified. 150 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 42: MPU Control (MPUCTRL), offset 0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRL register enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask Register (FAULTMASK) escalated handlers. When the ENABLE and PRIVDEFEN bits are both set: ■ For privileged accesses, the default memory map is as described in “Memory Model” on page 72. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. ■ Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled, then only privileged software can operate. When the ENABLE bit is clear, the system uses the default memory map, which has the same memory attributes as if the MPU is not implemented (see Table 2-5 on page 74 for more information). The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set. Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when operating with these two priorities. MPU Control (MPUCTRL) Base 0xE000.E000 Offset 0xD94 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 PRIVDEFEN HFNMIENA R/W 0 R/W 0 ENABLE R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 151 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 2 PRIVDEFEN R/W 0 Description MPU Default Region This bit enables privileged software access to the default memory map. Value Description 0 If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 If the MPU is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. When this bit is set, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. 1 HFNMIENA R/W 0 MPU Enabled During Faults This bit controls the operation of the MPU during hard fault, NMI, and FAULTMASK handlers. Value Description 0 The MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit. 1 The MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. 0 ENABLE R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. 152 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 43: MPU Region Number (MPUNUMBER), offset 0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBER register selects which memory region is referenced by the MPU Region Base Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the required region number should be written to this register before accessing the MPUBASE or the MPUATTR register. However, the region number can be changed by writing to the MPUBASE register with the VALID bit set (see page 154). This write updates the value of the REGION field. MPU Region Number (MPUNUMBER) Base 0xE000.E000 Offset 0xD98 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 NUMBER R/W 0x0 NUMBER RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. July 17, 2014 153 Texas Instruments-Production Data Cortex-M3 Peripherals Register 44: MPU Region Base Address (MPUBASE), offset 0xD9C Register 45: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 Register 46: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC Register 47: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 Note: This register can only be accessed from privileged mode. The MPUBASE register defines the base address of the MPU region selected by the MPU Region Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To change the current region number and update the MPUNUMBER register, write the MPUBASE register with the VALID bit set. The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size, as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines the value of N where: N = Log2(Region size in bytes) If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x0000.0000. The base address is aligned to the size of the region. For example, a 64-KB region must be aligned on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000. MPU Region Base Address (MPUBASE) Base 0xE000.E000 Offset 0xD9C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 VALID reserved R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 WO 0 RO 0 ADDR Type Reset ADDR Type Reset R/W 0 Bit/Field Name Type Reset 31:5 ADDR R/W 0x0000.000 REGION R/W 0 R/W 0 R/W 0 Description Base Address Mask Bits 31:N in this field contain the region base address. The value of N depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 154 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 4 VALID WO 0 Description Region Number Valid Value Description 0 The MPUNUMBER register is not changed and the processor updates the base address for the region specified in the MPUNUMBER register and ignores the value of the REGION field. 1 The MPUNUMBER register is updated with the value of the REGION field and the base address is updated for the region specified in the REGION field. This bit is always read as 0. 3 reserved RO 0 2:0 REGION R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Region Number On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the current region number in the MPUNUMBER register. July 17, 2014 155 Texas Instruments-Production Data Cortex-M3 Peripherals Register 48: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 Register 49: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 Register 50: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 Register 51: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 Note: This register can only be accessed from privileged mode. The MPUATTR register defines the region size and memory attributes of the MPU region specified by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions. The MPUATTR register is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table 3-9 on page 156 gives example SIZE values with the corresponding region size and value of N in the MPU Region Base Address (MPUBASE) register. Table 3-9. Example SIZE Field Values a SIZE Encoding Region Size Value of N Note 00100b (0x4) 32 B 5 Minimum permitted size 01001b (0x9) 1 KB 10 - 10011b (0x13) 1 MB 20 - 11101b (0x1D) 1 GB 30 - 11111b (0x1F) 4 GB No valid ADDR field in MPUBASE; the Maximum possible size region occupies the complete memory map. a. Refers to the N parameter in the MPUBASE register (see page 154). MPU Region Attribute and Size (MPUATTR) Base 0xE000.E000 Offset 0xDA0 Type R/W, reset 0x0000.0000 31 30 29 28 27 reserved Type Reset 26 25 24 23 AP 21 reserved 20 19 18 TEX 17 16 XN reserved S C B RO 0 RO 0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 SRD Type Reset 22 reserved SIZE 156 R/W 0 ENABLE R/W 0 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 31:29 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 XN R/W 0 Instruction Access Disable Value Description 0 Instruction fetches are enabled. 1 Instruction fetches are disabled. 27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 26:24 AP R/W 0 Access Privilege For information on using this bit field, see Table 3-5 on page 102. 23:22 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21:19 TEX R/W 0x0 Type Extension Mask For information on using this bit field, see Table 3-3 on page 101. 18 S R/W 0 Shareable For information on using this bit, see Table 3-3 on page 101. 17 C R/W 0 Cacheable For information on using this bit, see Table 3-3 on page 101. 16 B R/W 0 Bufferable For information on using this bit, see Table 3-3 on page 101. 15:8 SRD R/W 0x00 Subregion Disable Bits Value Description 0 The corresponding subregion is enabled. 1 The corresponding subregion is disabled. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, configure the SRD field as 0x00. See the section called “Subregions” on page 100 for more information. 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:1 SIZE R/W 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 156 for more information. July 17, 2014 157 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 0 ENABLE R/W 0 Description Region Enable Value Description 0 The region is disabled. 1 The region is enabled. 158 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 4 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. ® The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM, Stellaris, and unimplemented JTAG instructions. The Stellaris JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. July 17, 2014 159 Texas Instruments-Production Data JTAG Interface 4.1 Block Diagram Figure 4-1. JTAG Module Block Diagram TCK TMS TAP Controller TDI Instruction Register (IR) BYPASS Data Register TDO Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register Cortex-M3 Debug Port 4.2 Signal Description Table 4-1 on page 160 lists the external signals of the JTAG/SWD controller and describes the function of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals are under commit protection and require a special process to be configured as GPIOs, see “Commit Control” on page 357. The column in the table below titled "Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 371) is set to choose the JTAG/SWD function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 351. Table 4-1. JTAG_SWD_SWO Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type SWCLK 52 I TTL Description JTAG/SWD CLK. SWDIO 51 I/O TTL JTAG TMS and SWDIO. SWO 49 O TTL JTAG TDO and SWO. TCK 52 I TTL JTAG/SWD CLK. TDI 50 I TTL JTAG TDI. TDO 49 O TTL JTAG TDO and SWO. TMS 51 I/O TTL JTAG TMS and SWDIO. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 160 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 4.3 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 160. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 4-3 on page 167 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 772 for JTAG timing diagrams. 4.3.1 JTAG Interface Pins The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 4-2 on page 161. Detailed information on each pin follows. Table 4-2. JTAG Port Pins Reset State 4.3.1.1 Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value TCK Input Enabled Disabled N/A N/A TMS Input Enabled Disabled N/A N/A TDI Input Enabled Disabled N/A N/A TDO Output Enabled Disabled 2-mA driver High-Z Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 4.3.1.2 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. July 17, 2014 161 Texas Instruments-Production Data JTAG Interface Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG module and associated registers are reset to their default values. This procedure should be performed to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety in Figure 4-2 on page 163. By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 4.3.1.3 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 4.3.1.4 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 4.3.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 4-2 on page 163. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset the JTAG module after the device has been powered on, the TMS input must be held HIGH for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. 162 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 4-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 0 Select DR Scan 1 Select IR Scan 1 0 1 Capture DR 1 Capture IR 0 0 Shift DR Shift IR 0 1 Exit 1 DR Exit 1 IR 1 Pause IR 0 1 Exit 2 DR 0 1 0 Exit 2 IR 1 1 Update DR 4.3.3 1 0 Pause DR 1 0 1 0 0 1 0 0 Update IR 1 0 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 166. 4.3.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. July 17, 2014 163 Texas Instruments-Production Data JTAG Interface 4.3.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PC[3:0] JTAG/SWD pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides four more GPIOs for use in the design. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 371), GPIO Pull-Up Select (GPIOPUR) register (see page 377), and GPIO Digital Enable (GPIODEN) register (see page 381) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 383) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 384) have been set to 1. Recovering a "Locked" Device Note: Performing the sequence below causes the nonvolatile registers discussed in “Nonvolatile Register Programming” on page 264 to be restored to their factory default values. The mass erase of the flash memory caused by the below sequence occurs prior to the nonvolatile registers being restored. If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is: 1. Assert and hold the RST signal. 2. Apply power to the device. 3. Perform the JTAG-to-SWD switch sequence. 4. Perform the SWD-to-JTAG switch sequence. 5. Perform the JTAG-to-SWD switch sequence. 6. Perform the SWD-to-JTAG switch sequence. 7. Perform the JTAG-to-SWD switch sequence. 8. Perform the SWD-to-JTAG switch sequence. 9. Perform the JTAG-to-SWD switch sequence. 164 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 10. Perform the SWD-to-JTAG switch sequence. 11. Perform the JTAG-to-SWD switch sequence. 12. Perform the SWD-to-JTAG switch sequence. 13. Release the RST signal. 14. Wait 400 ms. 15. Power-cycle the device. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug (SWD)” on page 165. When performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence in the section called “JTAG-to-SWD Switching” on page 165 must be performed. 4.3.4.2 Communication with JTAG/SWD Because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software should check the ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. 4.3.4.3 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequences of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Debug Interface V5 Architecture Specification. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send the switching preamble to the microcontroller. The 16-bit TMS/SWDIO command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The July 17, 2014 165 Texas Instruments-Production Data JTAG Interface complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset states. 2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS/SWDIO. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already in SWD mode before sending the switch sequence, the SWD goes into the line reset state. To verify that the Debug Access Port (DAP) has switched to the Serial Wire Debug (SWD) operating mode, perform a SWD READID operation. The ID value can be compared against the device's known ID to verify the switch. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch command to the microcontroller. The 16-bit TMS/SWDIO command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first. This command can also be represented as 0xE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset states. 2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS/SWDIO. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already in JTAG mode before sending the switch sequence, the JTAG goes into the Test Logic Reset state. To verify that the Debug Access Port (DAP) has switched to the JTAG operating mode, set the JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The DR value can be compared against the device's known IDCODE to verify the switch. 4.4 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the four JTAG pins (PC[3:0]) should be reverted to their default settings. 4.5 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 166 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 4.5.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 4-3 on page 167. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 4-3. JTAG Instruction Register Commands 4.5.1.1 IR[3:0] Instruction Description 0000 EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0001 INTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. 0010 SAMPLE / PRELOAD Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. 1000 ABORT Shifts data into the ARM Debug Port Abort Register. 1010 DPACC Shifts data into and out of the ARM DP Access Register. 1011 APACC Shifts data into and out of the ARM AC Access Register. 1110 IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. 1111 BYPASS Connects TDI to TDO through a single Shift Register chain. All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. EXTEST Instruction The EXTEST instruction is not associated with its own Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows tests to be developed that drive known values out of the controller, which can be used to verify connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 4.5.1.2 INTEST Instruction The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing.While the INTEXT instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. July 17, 2014 167 Texas Instruments-Production Data JTAG Interface 4.5.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data Register” on page 169 for more information. 4.5.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 170 for more information. 4.5.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see “DPACC Data Register” on page 170 for more information. 4.5.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see “APACC Data Register” on page 170 for more information. 4.5.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 169 for more information. 4.5.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. 168 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 169 for more information. 4.5.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 4.5.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-3 on page 169. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x3BA0.0477. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 4-3. IDCODE Register Format 31 TDI 4.5.2.2 28 27 12 11 Version Part Number 1 0 Manufacturer ID 1 TDO BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-4 on page 169. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. Figure 4-4. BYPASS Register Format 0 TDI 4.5.2.3 0 TDO Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 4-5 on page 170. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. July 17, 2014 169 Texas Instruments-Production Data JTAG Interface When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 4-5. Boundary Scan Register Format TDI I N O U T O E ... GPIO PB6 4.5.2.4 I N O U T GPIO m O E I N O U T O E GPIO m +1 ... I N O U T O E TDO GPIO n APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 170 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 5 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 5.1 Signal Description Table 5-1 on page 171 lists the external signals of the System Control module and describes the function of each. The NMI signal is the alternate function for and functions as a GPIO after reset. under commit protection and require a special process to be configured as any alternate function or to subsequently return to the GPIO function, see “Commit Control” on page 357. The column in the table below titled "Pin Assignment" lists the GPIO pin placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 371) should be set to choose the NMI function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 351. The remaining signals (with the word "fixed" in the Pin Assignment column) have a fixed pin assignment and function. Table 5-1. System Control & Clocks Signals (64LQFP) Pin Name Pin Number Pin Type a Buffer Type Description NMI 55 I TTL OSC0 30 I Analog Non-maskable interrupt. Main oscillator crystal input or an external clock reference input. OSC1 31 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 40 I TTL System reset input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 5.2 Functional Description The System Control module provides the following capabilities: ■ Device identification (see “Device Identification” on page 171) ■ Local control, such as reset (see “Reset Control” on page 171), power (see “Power Control” on page 176) and clock control (see “Clock Control” on page 176) ■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 182 5.2.1 Device Identification Several read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC7 registers. 5.2.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 Reset Sources The controller has six sources of reset: July 17, 2014 171 Texas Instruments-Production Data System Control 1. External reset input pin (RST) assertion; see “External RST Pin” on page 173. 2. Power-on reset (POR); see “Power-On Reset (POR)” on page 172. 3. Internal brown-out (BOR) detector; see “Brown-Out Reset (BOR)” on page 174. 4. Software-initiated reset (with the software reset registers); see “Software Reset” on page 174. 5. A watchdog timer reset condition violation; see “Watchdog Timer Reset” on page 175. 6. MOSC failure; see “Main Oscillator Verification Failure” on page 176. Table 5-2 provides a summary of results of the various reset operations. Table 5-2. Reset Sources Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset? Power-On Reset Yes Yes Yes RST Yes Pin Config Only Yes Brown-Out Reset Yes No Yes Software System Request a Reset Yes No Yes Software Peripheral Reset No No Yes Watchdog Reset Yes No Yes MOSC Failure Reset Yes No Yes b a. By using the SYSRESREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control (APINT) register b. Programmable on a module-by-module basis using the Software Reset Control Registers. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR or an external reset is the cause, and then all the other bits in the RESC register are cleared except for the POR or EXT indicator. 5.2.2.2 Power-On Reset (POR) Note: The power-on reset also resets the JTAG controller. An external reset does not. The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VTH). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input may be used as discussed in “External RST Pin” on page 173. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. 172 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset timing is shown in Figure 21-5 on page 774. 5.2.2.3 External RST Pin Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be sure to place any components connected to the RST signal as close to the microcontroller as possible. If the application only uses the internal POR circuit, the RST input must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 173. Figure 5-1. Basic RST Configuration VDD Stellaris® RPU RST RPU = 0 to 100 kΩ The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals except the JTAG TAP controller (see “JTAG Interface” on page 159). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted (see “Reset” on page 773). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. To improve noise immunity and/or to delay reset at power up, the RST input may be connected to an RC network as shown in Figure 5-2 on page 173. Figure 5-2. External Circuitry to Extend Power-On Reset VDD Stellaris® RPU RST C1 RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 µF July 17, 2014 173 Texas Instruments-Production Data System Control If the application requires the use of an external reset switch, Figure 5-3 on page 174 shows the proper circuitry to use. Figure 5-3. Reset Circuit Controlled by Switch VDD Stellaris® RPU RST C1 RS Typical RPU = 10 kΩ Typical RS = 470 Ω C1 = 10 nF The RPU and C1 components define the power-on delay. The external reset timing is shown in Figure 21-4 on page 773. 5.2.2.4 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset. The brown-out reset is equivalent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 21-6 on page 774. 5.2.2.5 Software Reset Software can reset a specific peripheral or generate a reset to the entire system . Peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 182). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. 174 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 21-7 on page 774. 5.2.2.6 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The watchdog reset timing is shown in Figure 21-8 on page 774. 5.2.3 Non-Maskable Interrupt The controller has two sources of non-maskable interrupt (NMI): ■ The assertion of the NMI signal. ■ A main oscillator verification error. If both sources of NMI are enabled, software must check that the main oscillator verification is the cause of the interrupt in order to distinguish between the two sources. 5.2.3.1 NMI Pin The alternate function to GPIO port pin B7 is an NMI signal. The alternate function must be enabled in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs (GPIOs)” on page 351. Note that enabling the NMI alternate function requires the use of the GPIO lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality. The active sense of the NMI signal is High; asserting the enabled NMI signal above VIH initiates the NMI interrupt sequence. July 17, 2014 175 Texas Instruments-Production Data System Control 5.2.3.2 Main Oscillator Verification Failure The main oscillator verification circuit may generate a reset event, at which time a Power-on Reset is generated and control is transferred to the NMI handler. The NMI handler is used to address the main oscillator verification failure because the necessary code can be removed from the general reset handler, speeding up reset processing. The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator fail status bit (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit action is described in more detail in “Clock Control” on page 176. 5.2.4 Power Control ® The Stellaris microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the controller's internal logic. For power reduction, the LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Note: On the printed circuit board, use the LDO output as the source of VDD25 input. Do not use an external regulator to supply the voltage to VDD25. In addition, the LDO requires decoupling capacitors. See “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 767. VDDA must be supplied with 3.3 V, or the microcontroller does not function properly. VDDA is the supply for all of the analog circuitry on the device, including the clock circuitry. 5.2.5 Clock Control System control determines the control of clocks in this part. 5.2.5.1 Fundamental Clock Sources There are multiple clock sources for use in the device: ■ Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%. Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being used, the crystal value must be one of the supported frequencies between 3.579545 MHz through 16.384 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz and 16.384 MHz. The single-ended clock source range is from DC through the specified speed of the device. The supported crystals are listed in the XTAL bit field in the RCC register (see page 194). Note that the MOSC must have a clock source for the USB PLL. ■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator is similar to the internal oscillator, except that it provides an operational frequency of 30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. 176 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ■ External Real-Time Oscillator. The external real-time oscillator provides a low-frequency, accurate clock reference. It is intended to provide the system with a real-time clock source. The real-time oscillator is part of the Hibernation Module (see “Hibernation Module” on page 238) and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings. The internal system clock (SysClk), is derived from any of the above sources plus two others: the output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz (inclusive). Table 5-3 on page 177 shows how the various clock sources can be used in a system. Table 5-3. Clock Source Options 5.2.5.2 Clock Source Drive PLL? Internal Oscillator (12 MHz) No BYPASS = 1 Used as SysClk? Yes BYPASS = 1, OSCSRC = 0x1 Internal Oscillator divide by 4 (3 MHz) No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x2 Main Oscillator Yes BYPASS = 0, OSCSRC = Yes 0x0 BYPASS = 1, OSCSRC = 0x0 Internal 30-kHz Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x3 External Real-Time Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC2 = 0x7 Clock Configuration The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. These registers control the following clock functionality: ■ Source of clocks in sleep and deep-sleep modes ■ System clock derived from PLL or other clock source ■ Enabling/disabling of oscillators and PLL ■ Clock divisors ■ Crystal input selection Figure 5-4 on page 178 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. The ADC clock signal is automatically divided down to 16 MHz for proper ADC operation. Note: When the ADC module is in operation, the system clock must be at least 16 MHz. When the USB module is in operation, MOSC must be provided with a clock source, and the system clock must be at least 30 MHz. July 17, 2014 177 Texas Instruments-Production Data System Control Figure 5-4. Main Clock Tree XTALa USBPWRDN c USB PLL (240 MHz) USB Clock ÷4 USEPWMDIV a PWMDW a PWM Clock XTALa PWRDN b MOSCDIS a PLL (400 MHz) Main OSC USESYSDIV a,d ÷2 IOSCDIS a System Clock Internal OSC (12 MHz) SYSDIV b,d ÷4 BYPASS Internal OSC (30 kHz) Hibernation Module (32.768 kHz) b,d OSCSRC b,d PWRDN ADC Clock ÷ 25 a. Control provided by RCC register bit/field. b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2. c. Control provided by RCC2 register bit/field. d. Also may be controlled by DSLPCLKCFG when in deep sleep mode. Note: The figure above shows all features available on all Stellaris® DustDevil-class devices. Not all peripherals may be available on this device. In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. Table 5-4 shows how the SYSDIV encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1). The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see Table 5-3 on page 177. 178 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field SYSDIV Divisor a Frequency (BYPASS=0) Frequency (BYPASS=1) StellarisWare Parameter b 0x0 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1 0x1 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x2 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3 0x3 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x4 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 0x5 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x6 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 0x7 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x8 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9 0x9 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 0xA /11 18.18 MHz Clock source frequency/11 SYSCTL_SYSDIV_11 0xB /12 16.67 MHz Clock source frequency/12 SYSCTL_SYSDIV_12 0xC /13 15.38 MHz Clock source frequency/13 SYSCTL_SYSDIV_13 0xD /14 14.29 MHz Clock source frequency/14 SYSCTL_SYSDIV_14 0xE /15 13.33 MHz Clock source frequency/15 SYSCTL_SYSDIV_15 0xF /16 12.5 MHz (default) Clock source frequency/16 SYSCTL_SYSDIV_16 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding plus 1. Table 5-5 shows how the SYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list of possible clock sources, see Table 5-3 on page 177. Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field SYSDIV2 Divisor a Frequency (BYPASS2=0) Frequency (BYPASS2=1) StellarisWare Parameter b 0x00 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1 0x01 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x02 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3 0x03 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x04 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 0x05 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x06 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 0x07 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x08 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9 0x09 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 ... ... ... ... ... July 17, 2014 179 Texas Instruments-Production Data System Control Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field (continued) SYSDIV2 0x3F Divisor /64 a Frequency (BYPASS2=0) Frequency (BYPASS2=1) StellarisWare Parameter 3.125 MHz Clock source frequency/64 SYSCTL_SYSDIV_64 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. 5.2.5.3 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 16.384 MHz, otherwise, the range of supported crystals is 1 to 16.384 MHz. The XTAL bit in the RCC register (see page 194) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 5.2.5.4 Main PLL Frequency Configuration The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency, and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 198). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 21-10 on page 770 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 194) describes the available crystal choices and default programming of the PLLCFG register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. To configure the external 32-kHz real-time oscillator as the PLL input reference, program the OSCRC2 field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x7. 5.2.5.5 USB PLL Frequency Configuration The USB PLL is disabled by default during power-on reset and is enabled later by software. The USB PLL must be enabled and running for proper USB function. The main oscillator is the only clock reference for the USB PLL. The USB PLL is enabled by clearing the USBPWRDN bit of the RCC2 register. The XTAL bit field (Crystal Value) of the RCC register describes the available crystal choices. The main oscillator must be connected to one of the following crystal values in order to correctly generate the USB clock: 4, 5, 6, 8, 10, 12, or 16 MHz. Only these crystals provide the necessary USB PLL VCO frequency to conform with the USB timing specifications. 5.2.5.6 PLL Modes Both PLLs have two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. 180 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 194 and page 201). 5.2.5.7 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 21-9 on page 770). During the relock time, the affected PLL is not usable as a clock reference. Either PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). When the XTAL value is greater than 0x0f, the down counter is set to 0x2400 to maintain the required lock time on higher frequency crystal inputs. Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2 register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt. The USB PLL is not protected during the lock time (TREADY) and software should ensure that the USB PLL has locked before using the interface. Software can use many methods to ensure the TREADY period has passed, including periodically polling the USBPLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the USB PLL Lock interrupt. 5.2.5.8 Main Oscillator Verification Circuit A circuit is added to ensure that the main oscillator is running at the appropriate frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable band of attached crystals. The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL) register. If this circuit is enabled and detects an error, the following sequence is performed by the hardware: 1. The MOSCFAIL bit in the Reset Cause (RESC) register is set. 2. If the internal oscillator (IOSC) is disabled, it is enabled. 3. The system clock is switched from the main oscillator to the IOSC. 4. An internal power-on reset is initiated that lasts for 32 IOSC periods. 5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence. July 17, 2014 181 Texas Instruments-Production Data System Control 5.2.6 System Control For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. There are four levels of operation for the device defined as: ■ Run Mode. In Run mode, the controller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. ■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M3 core executing a WFI(Wait for Interrupt) instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See “Power Management” on page 90 for more details. Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. ■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See “Power Management” on page 90 for more details. The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. ■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device and only the Hibernation module's circuitry is active. An external wake event or RTC event is required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside of the Hibernation module see a normal "power on" sequence and the processor starts running code. It can determine that it has been restarted from Hibernate mode by inspecting the Hibernation module registers. 182 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock. A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface. 5.3 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a “raw” clock source and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 5.4 Register Map Table 5-6 on page 183 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Note: Additional Flash and ROM registers defined in the System Control register space are described in the “Internal Memory” on page 260. Table 5-6. System Control Register Map Description See page Offset Name Type Reset 0x000 DID0 RO - Device Identification 0 186 0x004 DID1 RO - Device Identification 1 205 0x008 DC0 RO 0x00FF.003F Device Capabilities 0 207 July 17, 2014 183 Texas Instruments-Production Data System Control Table 5-6. System Control Register Map (continued) Offset Name 0x010 Description See page Type Reset DC1 RO 0x0101.32FF Device Capabilities 1 208 0x014 DC2 RO 0x0007.5013 Device Capabilities 2 210 0x018 DC3 RO 0x9F3F.0000 Device Capabilities 3 211 0x01C DC4 RO 0x0000.301F Device Capabilities 4 212 0x020 DC5 RO 0x0000.0000 Device Capabilities 5 213 0x024 DC6 RO 0x0000.0002 Device Capabilities 6 214 0x028 DC7 RO 0x40C0.0F3F Device Capabilities 7 215 0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 188 0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 189 0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 235 0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 236 0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 237 0x050 RIS RO 0x0000.0000 Raw Interrupt Status 190 0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 191 0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 192 0x05C RESC R/W - Reset Cause 193 0x060 RCC R/W 0x0780.3AD1 Run-Mode Clock Configuration 194 0x064 PLLCFG RO - XTAL to PLL Translation 198 0x06C GPIOHBCTL R/W 0x0000.0000 GPIO High-Performance Bus Control 199 0x070 RCC2 R/W 0x0780.6810 Run-Mode Clock Configuration 2 201 0x07C MOSCCTL R/W 0x0000.0000 Main Oscillator Control 203 0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 217 0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 223 0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 229 0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 219 0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 225 0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 231 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 221 0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 227 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 233 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 204 184 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 5.5 Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. July 17, 2014 185 Texas Instruments-Production Data System Control Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset 31 30 reserved Type Reset 29 28 27 26 VER 25 24 23 22 21 20 reserved 18 17 16 CLASS RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - MAJOR Type Reset 19 MINOR Bit/Field Name Type Reset 31 reserved RO 0 30:28 VER RO 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows: Value Description 0x1 Second version of the DID0 register format. 27:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 CLASS RO 0x3 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x3 Stellaris® DustDevil-class devices 186 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 15:8 MAJOR RO - Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. 7:0 MINOR RO - Minor Revision This field specifies the minor revision number of the device. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. July 17, 2014 187 Texas Instruments-Production Data System Control Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 BORIOR R/W 0 BORIOR reserved R/W 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 188 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 VADJ Bit/Field Name Type Reset 31:6 reserved RO 0 5:0 VADJ R/W 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LDO Output Voltage This field sets the on-chip output voltage. The programming values for the VADJ field are provided below. Value VOUT (V) 0x00 2.50 0x01 2.45 0x02 2.40 0x03 2.35 0x04 2.30 0x05 2.25 0x06-0x3F Reserved 0x1B 2.75 0x1C 2.70 0x1D 2.65 0x1E 2.60 0x1F 2.55 July 17, 2014 189 Texas Instruments-Production Data System Control Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 BORRIS reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MOSCPUPRIS USBPLLLRIS RO 0 RO 0 PLLLRIS RO 0 reserved Bit/Field Name Type Reset Description 31:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 MOSCPUPRIS RO 0 MOSC Power Up Raw Interrupt Status This bit is set when the PLL TMOSCPUP Timer asserts. 7 USBPLLLRIS RO 0 USB PLL Lock Raw Interrupt Status This bit is set when the USB PLL TUSBREADY Timer asserts. 6 PLLLRIS RO 0 PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORRIS RO 0 Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 190 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 BORIM reserved RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MOSCPUPIM USBPLLLIM R/W 0 R/W 0 PLLLIM R/W 0 reserved Bit/Field Name Type Reset Description 31:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 MOSCPUPIM R/W 0 MOSC Power Up Interrupt Mask This bit specifies whether a MOSC power up intterupt is promoted to a controller interrupt. If set, an interrupt is generated if MOSCPUPRIS in RIS is set; otherwise, an interrupt is not generated. 7 USBPLLLIM R/W 0 USB PLL Lock Interrupt Mask This bit specifies whether a USB PLL Lock interrupt is promoted to a controller interrupt. If set, an interrupt is generated if USBPLLLRIS in RIS is set; otherwise, an interrupt is not generated. 6 PLLLIM R/W 0 PLL Lock Interrupt Mask This bit specifies whether a PLL Lock interrupt is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORIM R/W 0 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 191 Texas Instruments-Production Data System Control Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 190). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MOSCPUPMIS USBPLLLMIS R/W1C 0 R/W1C 0 PLLLMIS R/W1C 0 reserved BORMIS reserved R/W1C 0 RO 0 Bit/Field Name Type Reset Description 31:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 MOSCPUPMIS R/W1C 0 MOSC Power Up Masked Interrupt Status This bit is set when the TMOSCPUP timer asserts. The interrupt is cleared by writing a 1 to this bit. 7 USBPLLLMIS R/W1C 0 USB PLL Lock Masked Interrupt Status This bit is set when the USB PLL TUSBREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 6 PLLLMIS R/W1C 0 PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORMIS R/W1C 0 BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 192 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when a power- on reset or an external reset is the cause, in which case, all bits other than POR or EXT in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W - 9 8 7 6 5 4 3 2 1 0 SW WDT BOR POR EXT RO 0 RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - R/W - reserved Type Reset MOSCFAIL reserved Type Reset RO 0 16 Bit/Field Name Type Reset Description 31:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 MOSCFAIL R/W - MOSC Failure Reset When set, indicates the MOSC circuit was enable for clock validation and failed. This generated a reset event. 15:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SW R/W - Software Reset When set, indicates a software reset is the cause of the reset event. 3 WDT R/W - Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. 2 BOR R/W - Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. 1 POR R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. 0 EXT R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. July 17, 2014 193 Texas Instruments-Production Data System Control Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x0780.3AD1 31 30 29 28 RO 0 RO 0 RO 0 RO 0 15 14 13 12 reserved Type Reset reserved Type Reset RO 0 RO 0 27 26 25 24 23 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 11 10 9 8 R/W 0 R/W 1 ACG PWRDN reserved BYPASS R/W 1 RO 1 21 20 19 R/W 0 RO 0 RO 0 RO 0 7 6 5 4 3 R/W 1 R/W 1 R/W 0 R/W 1 RO 0 SYSDIV 22 Bit/Field Name Type Reset 31:28 reserved RO 0x0 27 ACG R/W 0 R/W 0 17 16 RO 0 RO 0 RO 0 2 1 0 reserved USESYSDIV XTAL R/W 1 18 OSCSRC reserved RO 0 IOSCDIS MOSCDIS R/W 0 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 26:23 SYSDIV R/W 0xF System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). See Table 5-4 on page 179 for bit encodings. If the SYSDIV value is less than MINSYSDIV (see page 208), and the PLL is being used, then the MINSYSDIV value is used as the divisor. If the PLL is not being used, the SYSDIV value can be less than MINSYSDIV. 22 USESYSDIV R/W 0 Enable System Clock Divider Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field in the RCC2 register is used as the system clock divider rather than the SYSDIV field in this register. 194 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 21:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 PWRDN R/W 1 PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. 12 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 BYPASS R/W 1 PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. See Table 5-4 on page 179 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly. While the ADC works in a 14-18 MHz range, to maintain a 1 M sample/second rate, the ADC must be provided a 16-MHz clock source. July 17, 2014 195 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 10:6 XTAL R/W 0xB Description Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Depending on the crystal used, the PLL frequency may not be exactly 400 MHz (see Table 21-10 on page 770 for more information). Frequencies that may be used with the USB interface are indicated in the table. To function within the clocking requirements of the USB specification, a crystal of 4, 5, 6, 8, 10, 12, or 16 MHz must be used. Value Crystal Frequency (MHz) Not Using the PLL Crystal Frequency (MHz) Using the PLL 0x00 1.000 reserved 0x01 1.8432 reserved 0x02 2.000 reserved 0x03 2.4576 0x04 reserved 3.579545 MHz 0x05 3.6864 MHz 0x06 4 MHz (USB) 0x07 4.096 MHz 0x08 4.9152 MHz 0x09 5 MHz (USB) 0x0A 5.12 MHz 0x0B 6 MHz (reset value)(USB) 0x0C 6.144 MHz 0x0D 7.3728 MHz 0x0E 8 MHz (USB) 0x0F 8.192 MHz 0x10 10.0 MHz (USB) 0x11 12.0 MHz (USB) 0x12 12.288 MHz 0x13 13.56 MHz 0x14 14.31818 MHz 0x15 16.0 MHz (USB) 0x16 16.384 MHz 196 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 5:4 OSCSRC R/W 0x1 Description Oscillator Source Selects the input source for the OSC. The values are: Value Input Source 0x0 MOSC Main oscillator 0x1 IOSC Internal oscillator (default) 0x2 IOSC/4 Internal oscillator / 4 0x3 30 kHz 30-KHz internal oscillator For additional oscillator sources, see the RCC2 register. 3:2 reserved RO 0x0 1 IOSCDIS R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. 0 MOSCDIS R/W 1 Main Oscillator Disable 0: Main oscillator is enabled . 1: Main oscillator is disabled (default). July 17, 2014 197 Texas Instruments-Production Data System Control Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 194). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO - RO - RO - RO - RO - 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - reserved Type Reset reserved Type Reset RO 0 RO 0 F Bit/Field Name Type Reset 31:14 reserved RO 0x0 13:5 F RO - R Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL F Value This field specifies the value supplied to the PLL’s F input. 4:0 R RO - PLL R Value This field specifies the value supplied to the PLL’s R input. 198 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C This register controls which internal bus is used to access each GPIO port. When a bit is clear, the corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and through the APB memory aperture. When a bit is set, the corresponding port is accessed across the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each GPIO port can be individually configured to use AHB or APB, but may be accessed only through one aperture. The AHB bus provides better back-to-back access performance than the APB bus. The address aperture in the memory map changes for the ports that are enabled for AHB access (see Table 9-6 on page 360). GPIO High-Performance Bus Control (GPIOHBCTL) Base 0x400F.E000 Offset 0x06C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PORTE PORTD PORTC PORTB PORTA RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.0 4 PORTE R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Port E Advanced High-Performance Bus This bit defines the memory aperture for Port E. Value Description 3 PORTD R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port D Advanced High-Performance Bus This bit defines the memory aperture for Port D. Value Description 2 PORTC R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port C Advanced High-Performance Bus This bit defines the memory aperture for Port C. Value Description 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. July 17, 2014 199 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 1 PORTB R/W 0 Description Port B Advanced High-Performance Bus This bit defines the memory aperture for Port B. Value Description 0 PORTA R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port A Advanced High-Performance Bus This bit defines the memory aperture for Port A. Value Description 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. 200 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 11: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields, as shown in Table 5-7, when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC field is located at the same LSB bit position; however, some RCC2 fields are larger than the corresponding RCC field. Table 5-7. RCC2 Fields that Override RCC fields RCC2 Field... Overrides RCC Field SYSDIV2, bits[28:23] SYSDIV, bits[26:23] PWRDN2, bit[13] PWRDN, bit[13] BYPASS2, bit[11] BYPASS, bit[11] OSCSRC2, bits[6:4] OSCSRC, bits[5:4] Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x0780.6810 31 30 USERCC2 Type Reset 29 28 27 26 reserved 25 23 22 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 15 14 13 12 11 10 9 8 7 6 RO 0 R/W 1 21 20 R/W 1 RO 0 reserved R/W 1 RO 0 19 18 17 16 reserved reserved USBPWRDN PWRDN2 reserved BYPASS2 Type Reset 24 SYSDIV2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 RO 0 RO 0 OSCSRC2 RO 0 RO 0 Bit/Field Name Type Reset Description 31 USERCC2 R/W 0 Use RCC2 R/W 0 R/W 0 reserved R/W 1 RO 0 RO 0 When set, overrides the RCC register fields. 30:29 reserved RO 0x0 28:23 SYSDIV2 R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS2 bit is configured). SYSDIV2 is used for the divisor when both the USESYSDIV bit in the RCC register and the USERCC2 bit in this register are set. See Table 5-5 on page 179 for programming guidelines. 22:15 reserved RO 0x0 14 USBPWRDN R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power-Down USB PLL When set, powers down the USB PLL. 13 PWRDN2 R/W 1 Power-Down PLL When set, powers down the PLL. July 17, 2014 201 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 BYPASS2 R/W 1 Bypass PLL When set, bypasses the PLL for the clock source. See Table 5-5 on page 179 for programming guidelines. 10:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:4 OSCSRC2 R/W 0x1 Oscillator Source Selects the input source for the OSC. The values are: Value Description 0x0 MOSC Main oscillator 0x1 IOSC Internal oscillator 0x2 IOSC/4 Internal oscillator / 4 0x3 30 kHz 30-kHz internal oscillator 0x4 Reserved 0x5 Reserved 0x6 Reserved 0x7 32 kHz 32.768-kHz external oscillator 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 202 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 12: Main Oscillator Control (MOSCCTL), offset 0x07C This register provides control over the features of the main oscillator, including the ability to enable the MOSC clock validation circuit. When enabled, this circuit monitors the energy on the MOSC pins to provide a Clock Valid signal. If the clock goes invalid after being enabled, the part does a hardware reset and reboots to the NMI handler. Main Oscillator Control (MOSCCTL) Base 0x400F.E000 Offset 0x07C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0 0 CVAL R/W 0 RO 0 CVAL R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Validation for MOSC When set, the monitor circuit is enabled. July 17, 2014 203 Texas Instruments-Production Data System Control Register 13: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 29 28 27 26 reserved Type Reset 25 24 23 22 21 20 DSDIVORIDE 18 17 16 reserved RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 19 DSOSCSRC RO 0 Bit/Field Name Type Reset 31:29 reserved RO 0x0 28:23 DSDIVORIDE R/W 0x0F R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Divider Field Override 6-bit system divider field to override when Deep-Sleep occurs with PLL running. 22:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:4 DSOSCSRC R/W 0x0 Clock Source Specifies the clock source during Deep-Sleep mode. Value Description 0x0 MOSC Use main oscillator as source. 0x1 IOSC Use internal 12-MHz oscillator as source. 0x2 Reserved 0x3 30 kHz Use 30-kHz internal oscillator as source. 0x4 Reserved 0x5 Reserved 0x6 Reserved 0x7 32 kHz Use 32.768-kHz external oscillator as source. 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 204 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 14: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 31 30 29 28 27 26 RO 0 15 25 24 23 22 21 20 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 1 14 13 12 11 10 9 8 7 6 5 4 RO 1 RO 0 RO 0 RO 0 RO 0 RO - RO - RO - VER Type Reset FAM PINCOUNT Type Reset RO 0 RO 1 18 17 16 RO 0 RO 1 RO 1 RO 0 3 2 1 0 PARTNO reserved RO 0 19 TEMP Bit/Field Name Type Reset 31:28 VER RO 0x1 RO - PKG ROHS RO - RO 1 QUAL RO - RO - Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 27:24 FAM RO 0x0 Second version of the DID1 register format. Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 23:16 PARTNO RO 0x96 Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0x96 LM3S5732 15:13 PINCOUNT RO 0x3 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x3 64-pin package July 17, 2014 205 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 12:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 TEMP RO - Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 4:3 PKG RO - 0x0 Commercial temperature range (0°C to 70°C) 0x1 Industrial temperature range (-40°C to 85°C) 0x2 Extended temperature range (-40°C to 105°C) Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 2 ROHS RO 1 0x0 SOIC package 0x1 LQFP package 0x2 BGA package RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 1:0 QUAL RO - Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified 206 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 15: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00FF.003F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 SRAMSZ Type Reset FLASHSZ Type Reset RO 0 Bit/Field Name Type Reset Description 31:16 SRAMSZ RO 0x00FF SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x00FF 64 KB of SRAM 15:0 FLASHSZ RO 0x003F Flash Size Indicates the size of the on-chip flash memory. Value Description 0x003F 128 KB of Flash July 17, 2014 207 Texas Instruments-Production Data System Control Register 16: Device Capabilities 1 (DC1), offset 0x010 This register is predefined by the part and can be used to verify features. The PWM, SARADC0, MAXADCSPD, WDT, SWO, SWD, and JTAG bits mask the RCGC0, SCGC0, and DCGC0 registers. Other bits are passed as 0. MAXADCSPD is clipped to the maximum value specified in DC1. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0101.32FF 31 30 29 RO 0 RO 0 RO 0 15 14 13 RO 0 RO 0 28 27 26 25 RO 0 RO 0 RO 0 RO 0 12 11 10 9 RO 1 RO 0 reserved Type Reset MINSYSDIV Type Reset RO 1 24 23 22 21 19 18 17 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 8 7 6 5 4 3 2 1 0 MPU RO 1 HIB TEMPSNS PLL WDT SWO SWD JTAG RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 CAN0 reserved RO 0 MAXADCSPD RO 1 RO 0 20 reserved 16 ADC Bit/Field Name Type Reset Description 31:25 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24 CAN0 RO 1 CAN Module 0 Present When set, indicates that CAN unit 0 is present. 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC RO 1 ADC Module Present. When set, indicates that the ADC module is present. 15:12 MINSYSDIV RO 0x3 System Clock Divider. Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x3 11:10 reserved RO 0 9:8 MAXADCSPD RO 0x2 Specifies a 50-MHz CPU clock with a PLL divider of 4. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Max ADC Speed. This field indicates the maximum rate at which the ADC samples data. Value Description 0x2 7 MPU RO 1 500K samples/second MPU Present. When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the "Cortex-M3 Peripherals" chapter in the Stellaris Data Sheet for details on the MPU. 208 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 6 HIB RO 1 Hibernation Module Present. When set, indicates that the Hibernation module is present. 5 TEMPSNS RO 1 Temp Sensor Present. When set, indicates that the on-chip temperature sensor is present. 4 PLL RO 1 PLL Present. When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 3 WDT RO 1 Watchdog Timer Present. When set, indicates that a watchdog timer is present. 2 SWO RO 1 SWO Trace Port Present. When set, indicates that the Serial Wire Output (SWO) trace port is present. 1 SWD RO 1 SWD Present. When set, indicates that the Serial Wire Debugger (SWD) is present. 0 JTAG RO 1 JTAG Present. When set, indicates that the JTAG debugger interface is present. July 17, 2014 209 Texas Instruments-Production Data System Control Register 17: Device Capabilities 2 (DC2), offset 0x014 This register is predefined by the part and can be used to verify features. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x0007.5013 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 reserved I2C1 reserved I2C0 RO 0 RO 1 RO 0 RO 1 RO 0 25 24 23 22 21 20 19 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 3 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset Type Reset reserved RO 0 SSI0 RO 1 18 17 16 TIMER2 TIMER1 TIMER0 RO 1 RO 1 RO 1 2 1 0 UART1 UART0 RO 1 RO 1 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 RO 1 Timer 2 Present. When set, indicates that General-Purpose Timer module 2 is present. 17 TIMER1 RO 1 Timer 1 Present. When set, indicates that General-Purpose Timer module 1 is present. 16 TIMER0 RO 1 Timer 0 Present. When set, indicates that General-Purpose Timer module 0 is present. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 RO 1 I2C Module 1 Present. When set, indicates that I2C module 1 is present. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 RO 1 I2C Module 0 Present. When set, indicates that I2C module 0 is present. 11:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 RO 1 SSI0 Present. When set, indicates that SSI module 0 is present. 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 UART1 RO 1 UART1 Present. When set, indicates that UART module 1 is present. 0 UART0 RO 1 UART0 Present. When set, indicates that UART module 0 is present. 210 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 18: Device Capabilities 3 (DC3), offset 0x018 This register is predefined by the part and can be used to verify features. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0x9F3F.0000 31 30 32KHZ Type Reset 29 reserved 28 27 26 25 24 23 22 reserved 21 20 19 18 17 16 CCP4 CCP3 CCP2 CCP1 CCP0 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 RO 1 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset Bit/Field Name Type Reset Description 31 32KHZ RO 1 32KHz Input Clock Available. When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock. 30:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 CCP4 RO 1 CCP4 Pin Present. When set, indicates that Capture/Compare/PWM pin 4 is present. 27 CCP3 RO 1 CCP3 Pin Present. When set, indicates that Capture/Compare/PWM pin 3 is present. 26 CCP2 RO 1 CCP2 Pin Present. When set, indicates that Capture/Compare/PWM pin 2 is present. 25 CCP1 RO 1 CCP1 Pin Present. When set, indicates that Capture/Compare/PWM pin 1 is present. 24 CCP0 RO 1 CCP0 Pin Present. When set, indicates that Capture/Compare/PWM pin 0 is present. 23:22 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21 ADC5 RO 1 ADC5 Pin Present. When set, indicates that ADC pin 5 is present. 20 ADC4 RO 1 ADC4 Pin Present. When set, indicates that ADC pin 4 is present. 19 ADC3 RO 1 ADC3 Pin Present. When set, indicates that ADC pin 3 is present. 18 ADC2 RO 1 ADC2 Pin Present. When set, indicates that ADC pin 2 is present. 17 ADC1 RO 1 ADC1 Pin Present. When set, indicates that ADC pin 1 is present. 16 ADC0 RO 1 ADC0 Pin Present. When set, indicates that ADC pin 0 is present. 15:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 211 Texas Instruments-Production Data System Control Register 19: Device Capabilities 4 (DC4), offset 0x01C This register is predefined by the part and can be used to verify features. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x0000.301F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 UDMA ROM RO 1 RO 1 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 GPIOE GPIOD GPIOC GPIOB GPIOA RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 reserved Type Reset reserved Type Reset RO 0 RO 0 reserved RO 0 Bit/Field Name Type Reset Description 31:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA RO 1 Micro-DMA is present 12 ROM RO 1 Internal Code ROM is present 11:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 GPIOE RO 1 GPIO Port E Present. When set, indicates that GPIO Port E is present. 3 GPIOD RO 1 GPIO Port D Present. When set, indicates that GPIO Port D is present. 2 GPIOC RO 1 GPIO Port C Present. When set, indicates that GPIO Port C is present. 1 GPIOB RO 1 GPIO Port B Present. When set, indicates that GPIO Port B is present. 0 GPIOA RO 1 GPIO Port A Present. When set, indicates that GPIO Port A is present. 212 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 20: Device Capabilities 5 (DC5), offset 0x020 This register is predefined by the part and can be used to verify features. Device Capabilities 5 (DC5) Base 0x400F.E000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 213 Texas Instruments-Production Data System Control Register 21: Device Capabilities 6 (DC6), offset 0x024 This register is predefined by the part and can be used to verify features. Device Capabilities 6 (DC6) Base 0x400F.E000 Offset 0x024 Type RO, reset 0x0000.0002 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0 1:0 USB0 RO 0x2 USB0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. This specifies that USB0 is present and its capability Value Description 0x2 USB is Device or Host. 214 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 22: Device Capabilities 7 (DC7), offset 0x028 This register is predefined by the part and can be used to verify uDMA channel features. Device Capabilities 7 (DC7) Base 0x400F.E000 Offset 0x028 Type RO, reset 0x40C0.0F3F Type Reset 31 30 29 28 27 reserved SW RO 0 RO 1 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 25 24 RO 0 RO 0 RO 0 RO 1 10 9 8 7 reserved reserved Type Reset 26 RO 0 RO 1 RO 1 22 21 20 19 RO 1 RO 0 RO 0 RO 0 6 5 4 3 RO 1 RO 1 reserved RO 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 reserved UART1_TX UART1_RX SSI0_TX SSI0_RX UART0_TX UART0_RX RO 0 23 USB_EP3_TX USB_EP3_RX USB_EP2_TX USB_EP2_RX USB_EP1_TX USB_EP1_RX RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset Description 31 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 SW RO 1 Software transfer on uDMA Ch30. When set, indicates uDMA channel 30 is available for software. 29:24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23 UART1_TX RO 1 UART1 TX on uDMA Ch23. When set, indicates uDMA channel 23 is available and connected to the transmit path of UART module 1. 22 UART1_RX RO 1 UART1 RX on uDMA Ch22. When set, indicates uDMA channel 22 is available and connected to the receive path of UART module 1. 21:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 SSI0_TX RO 1 SSI0 TX on uDMA Ch11. When set, indicates uDMA channel 11 is available and connected to the transmit path of SSI module 0. 10 SSI0_RX RO 1 SSI0 RX on uDMA Ch10. When set, indicates uDMA channel 10 is available and connected to the receive path of SSI module 0. 9 UART0_TX RO 1 UART0 TX on uDMA Ch9. When set, indicates uDMA channel 9 is available and connected to the transmit path of UART module 0. 8 UART0_RX RO 1 UART0 RX on uDMA Ch8. When set, indicates uDMA channel 8 is available and connected to the receive path of UART module 0. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 USB_EP3_TX RO 1 USB EP3 TX on uDMA Ch5. When set, indicates uDMA channel 5 is available and connected to the transmit path of USB endpoint 3. July 17, 2014 215 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 4 USB_EP3_RX RO 1 USB EP3 RX on uDMA Ch4. When set, indicates uDMA channel 4 is available and connected to the receive path of USB endpoint 2. 3 USB_EP2_TX RO 1 USB EP2 TX on uDMA Ch3. When set, indicates uDMA channel 3 is available and connected to the transmit path of USB endpoint 2. 2 USB_EP2_RX RO 1 USB EP2 RX on uDMA Ch2. When set, indicates uDMA channel 1 is available and connected to the receive path of USB endpoint 2. 1 USB_EP1_TX RO 1 USB EP1 TX on uDMA Ch1. When set, indicates uDMA channel 1 is available and connected to the transmit path of USB endpoint 1. 0 USB_EP1_RX RO 1 USB EP1 RX on uDMA Ch0. When set, indicates uDMA channel 0 is available and connected to the receive path of USB endpoint 1. 216 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 23: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 RO 0 RO 0 RO 0 15 14 13 RO 0 RO 0 RO 0 28 27 26 25 RO 0 RO 0 RO 0 RO 0 12 11 10 9 RO 0 RO 0 R/W 0 reserved Type Reset RO 0 23 22 21 R/W 0 RO 0 RO 0 RO 0 8 7 6 5 CAN0 reserved Type Reset 24 MAXADCSPD R/W 0 20 19 18 17 RO 0 RO 0 RO 0 RO 0 R/W 0 4 3 2 1 0 reserved reserved HIB RO 0 R/W 1 reserved RO 0 RO 0 16 ADC WDT R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:25 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24 CAN0 R/W 0 CAN0 Clock Gating Control. This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC R/W 0 ADC0 Clock Gating Control. This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 15:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 217 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 9:8 MAXADCSPD R/W 0 Description ADC Sample Speed. This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 1 HIB Clock Gating Control. This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Clock Gating Control. This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 218 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 24: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 24 23 22 21 CAN0 RO 0 R/W 0 9 8 MAXADCSPD RO 0 RO 0 R/W 0 R/W 0 20 19 18 17 reserved RO 0 RO 0 RO 0 RO 0 5 4 7 6 reserved HIB RO 0 R/W 1 reserved RO 0 RO 0 16 ADC RO 0 RO 0 3 2 WDT R/W 0 RO 0 R/W 0 1 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:25 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24 CAN0 R/W 0 CAN0 Clock Gating Control. This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC R/W 0 ADC0 Clock Gating Control. This bit controls the clock gating for general SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 15:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 219 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 9:8 MAXADCSPD R/W 0 Description ADC Sample Speed. This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate.You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 1 HIB Clock Gating Control. This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Clock Gating Control. This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 220 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 25: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 24 23 RO 0 RO 0 RO 0 RO 0 21 RO 0 RO 0 RO 0 R/W 0 RO 0 11 10 9 8 7 RO 0 RO 0 RO 0 6 5 4 HIB RO 0 RO 0 RO 0 RO 0 20 19 18 17 reserved reserved Type Reset 22 CAN0 RO 0 R/W 1 reserved RO 0 RO 0 16 ADC RO 0 RO 0 3 2 WDT R/W 0 RO 0 R/W 0 1 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:25 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24 CAN0 R/W 0 CAN0 Clock Gating Control. This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC R/W 0 ADC0 Clock Gating Control. This bit controls the clock gating for general SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 15:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 1 HIB Clock Gating Control. This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 221 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 3 WDT R/W 0 WDT Clock Gating Control. This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 222 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 26: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 RO 0 25 24 23 22 21 20 19 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 3 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset Type Reset reserved RO 0 SSI0 R/W 0 18 17 16 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 2 1 0 UART1 UART0 R/W 0 R/W 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control. This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control. This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control. This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Clock Gating Control. This bit controls the clock gating for I2C module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. July 17, 2014 223 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control. This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 11:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 R/W 0 SSI0 Clock Gating Control. This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 UART1 R/W 0 UART1 Clock Gating Control. This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control. This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 224 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 27: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 reserved Type Reset Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 15 14 13 12 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 17 16 TIMER1 TIMER0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 4 3 2 SSI0 RO 0 18 TIMER2 R/W 0 reserved RO 0 RO 0 1 0 UART1 UART0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control. This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control. This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control. This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Clock Gating Control. This bit controls the clock gating for I2C module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. July 17, 2014 225 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control. This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 11:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 R/W 0 SSI0 Clock Gating Control. This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 UART1 R/W 0 UART1 Clock Gating Control. This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control. This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 226 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 28: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 reserved Type Reset Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 15 14 13 12 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 17 16 TIMER1 TIMER0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 4 3 2 SSI0 RO 0 18 TIMER2 R/W 0 reserved RO 0 RO 0 1 0 UART1 UART0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control. This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control. This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control. This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Clock Gating Control. This bit controls the clock gating for I2C module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. July 17, 2014 227 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control. This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 11:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 R/W 0 SSI0 Clock Gating Control. This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 UART1 R/W 0 UART1 Clock Gating Control. This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control. This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 228 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 29: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 8 7 6 5 4 3 2 1 0 GPIOE GPIOD GPIOC GPIOB GPIOA RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 UDMA R/W 0 16 USB0 reserved Bit/Field Name Type Reset Description 31:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 USB0 R/W 0 USB0 Clock Gating Control. This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA R/W 0 UDMA Clock Gating Control. This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 GPIOE R/W 0 Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. July 17, 2014 229 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 3 GPIOD R/W 0 Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control. This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control. This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control. This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 230 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 30: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 reserved Type Reset RO 0 RO 0 15 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 13 12 11 10 9 8 7 6 5 UDMA R/W 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 16 USB0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 4 3 2 1 0 GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 USB0 R/W 0 USB0 Clock Gating Control. This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA R/W 0 UDMA Clock Gating Control. This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 GPIOE R/W 0 Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. July 17, 2014 231 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 3 GPIOD R/W 0 Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control. This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control. This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control. This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 232 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 31: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 reserved Type Reset RO 0 RO 0 15 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 13 12 11 10 9 8 7 6 5 UDMA R/W 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 16 USB0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 4 3 2 1 0 GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 USB0 R/W 0 USB0 Clock Gating Control. This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA R/W 0 UDMA Clock Gating Control. This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 GPIOE R/W 0 Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. July 17, 2014 233 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 3 GPIOD R/W 0 Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control. This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control. This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control. This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 234 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 32: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 15 14 RO 0 RO 0 23 22 21 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 13 12 11 10 9 8 7 6 5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset 24 CAN0 HIB RO 0 19 18 17 RO 0 RO 0 RO 0 RO 0 R/W 0 4 3 2 1 0 reserved reserved Type Reset 20 reserved RO 0 RO 0 16 ADC WDT R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:25 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24 CAN0 R/W 0 CAN0 Reset Control. Reset control for CAN unit 0. 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 ADC R/W 0 ADC0 Reset Control. Reset control for SAR ADC module 0. 15:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 0 HIB Reset Control. Reset control for the Hibernation module. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT R/W 0 WDT Reset Control. Reset control for Watchdog unit. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 235 Texas Instruments-Production Data System Control Register 33: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 RO 0 25 24 23 22 21 20 19 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 3 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset Type Reset reserved RO 0 SSI0 R/W 0 18 17 16 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 2 1 0 UART1 UART0 R/W 0 R/W 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 TIMER2 R/W 0 Timer 2 Reset Control. Reset control for General-Purpose Timer module 2. 17 TIMER1 R/W 0 Timer 1 Reset Control. Reset control for General-Purpose Timer module 1. 16 TIMER0 R/W 0 Timer 0 Reset Control. Reset control for General-Purpose Timer module 0. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Reset Control. Reset control for I2C unit 1. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Reset Control. Reset control for I2C unit 0. 11:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 R/W 0 SSI0 Reset Control. Reset control for SSI unit 0. 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 UART1 R/W 0 UART1 Reset Control. Reset control for UART unit 1. 0 UART0 R/W 0 UART0 Reset Control. Reset control for UART unit 0. 236 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 34: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 8 7 6 5 4 3 2 1 0 GPIOE GPIOD GPIOC GPIOB GPIOA RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 UDMA R/W 0 16 USB0 reserved Bit/Field Name Type Reset Description 31:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 USB0 R/W 0 USB0 Reset Control. Reset control for USB unit 0. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA R/W 0 UDMA Reset Control. Reset control for uDMA unit. 12:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 GPIOE R/W 0 Port E Reset Control. Reset control for GPIO Port E. 3 GPIOD R/W 0 Port D Reset Control. Reset control for GPIO Port D. 2 GPIOC R/W 0 Port C Reset Control. Reset control for GPIO Port C. 1 GPIOB R/W 0 Port B Reset Control. Reset control for GPIO Port B. 0 GPIOA R/W 0 Port A Reset Control. Reset control for GPIO Port A. July 17, 2014 237 Texas Instruments-Production Data Hibernation Module 6 Hibernation Module The Hibernation Module manages removal and restoration of power to provide a means for reducing power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation module remaining powered. Power can be restored based on an external signal, or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power supply. The Hibernation module has the following features: ■ System power control using discrete external regulator ■ Dedicated pin for waking from an external signal ■ Low-battery detection, signaling, and interrupt generation ■ 32-bit real-time clock (RTC) ■ Two 32-bit RTC match registers for timed wake-up and interrupt generation ■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal ■ RTC predivider trim for making fine adjustments to the clock rate ■ 64 32-bit words of non-volatile memory ■ Programmable interrupts for RTC match, external wake, and low battery events 238 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 6.1 Block Diagram Figure 6-1. Hibernation Module Block Diagram HIBCTL.CLK32EN 32.768 kHz XOSC0 Pre-Divider 4.194304 MHz XOSC1 Interrupts HIBIM HIBRIS HIBMIS HIBIC HIBRTCT /128 HIBCTL.CLKSEL Non-Volatile Memory 64 words HIBDATA RTC HIBRTCC HIBRTCLD HIBRTCM0 HIBRTCM1 MATCH0/1 WAKE LOWBAT VDD Low Battery Detect VBAT HIBCTL.LOWBATEN 6.2 Interrupts to CPU Power Sequence Logic HIB HIBCTL.PWRCUT HIBCTL.RTCWEN HIBCTL.PINWEN HIBCTL.VABORT Signal Description Table 6-1 on page 239 lists the external signals of the Hibernation module and describes the function of each. These signals have dedicated functions and are not alternate functions for any GPIO signals. Table 6-1. Hibernate Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type Description HIB 33 O OD An output that indicates the processor is in Hibernate mode. VBAT 37 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE 32 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 34 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 35 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 17, 2014 239 Texas Instruments-Production Data Hibernation Module 6.3 Functional Description The Hibernation module controls the power to the processor with an enable signal (HIB) that signals an external voltage regulator to turn off. The Hibernation module power source is determined dynamically. The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power switch selects the appropriate voltage source. The Hibernation module also has a separate clock source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is low, and optionally prevent hibernation when this occurs. When waking from hibernation, the HIB signal is deasserted. The return of VDD causes a POR to be executed. The time from when the WAKE signal is asserted to when code begins execution is equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TIRPOR). 6.3.1 Register Access Timing Because the Hibernation module has an independent clocking domain, certain registers must be written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain Hibernation registers, or between a write followed by a read to those same registers. There is no restriction on timing for back-to-back reads from the Hibernation module. Software may make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. Software should poll HIBCTL for WRC=1 prior to accessing any affected register. The following registers are subject to this timing restriction: ■ Hibernation RTC Counter (HIBRTCC) ■ Hibernation RTC Match 0 (HIBRTCM0) ■ Hibernation RTC Match 1 (HIBRTCM1) ■ Hibernation RTC Load (HIBRTCLD) ■ Hibernation RTC Trim (HIBRTCT) ■ Hibernation Data (HIBDATA) 6.3.2 Clock Source The Hibernation module must be clocked by an external source, even if the RTC feature is not used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to produce the 32.768-kHz clock reference. For an alternate clock source, a 32.768-kHz oscillator can be connected to the XOSC0 pin. See Figure 6-2 on page 241 and Figure 6-3 on page 241. Note that these diagrams only show the connection to the Hibernation pins and not to the full system. See “Hibernation Module” on page 775 for specific values. The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a 32.768-kHz clock source. If the bit is set to 0, the 4.194304-MHz input clock is divided by 128, 240 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller resulting in a 32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for the clock source, no delay is needed. Figure 6-2. Clock Source Using Crystal Stellaris Microcontroller Regulator or Switch Input Voltage IN OUT VDD EN XOSC0 X1 RL XOSC1 C1 C2 HIB WAKE RPU Open drain external wake up circuit Note: VBAT 3V Battery GND X1 = Crystal frequency is fXOSC_XTAL. C1,2 = Capacitor value derived from crystal vendor load capacitance specifications. RL = Load resistor is RXOSC_LOAD. RPU = Pull-up resistor (1 M½). See “Hibernation Module” on page 775 for specific parameter values. Figure 6-3. Clock Source Using Dedicated Oscillator Stellaris Microcontroller Regulator or Switch Input Voltage IN OUT EN VDD Clock Source XOSC0 (fEXT_OSC) N.C. XOSC1 HIB WAKE RPU Open drain external wake up circuit Note: VBAT GND 3V Battery RPU = Pull-up resistor (1 M½). July 17, 2014 241 Texas Instruments-Production Data Hibernation Module 6.3.3 Battery Management The Hibernation module can be independently powered by a battery or an auxiliary power source. The module can monitor the voltage level of the battery and detect when the voltage drops below VLOWBAT. When this happens, an interrupt can be generated. The module can also be configured so that it will not go into Hibernate mode if the battery voltage drops below this threshold. Battery voltage is not measured while in Hibernate mode. Important: System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under nominal conditions or else the Hibernation module draws power from the battery even when VDD is available. The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering Hibernation mode when a low battery is detected. The module can also be configured to generate an interrupt for the low-battery condition (see “Interrupts and Status” on page 243). 6.3.4 Real-Time Clock The Hibernation module includes a 32-bit counter that increments once per second with a proper clock source and configuration (see “Clock Source” on page 240). The 32.768-kHz clock signal is fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and is used for one second out of every 64 seconds to divide the input clock. This allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC rate, and down from 0x7FFF in order to speed up the RTC rate. The Hibernation module includes two 32-bit match registers that are compared to the value of the RTC counter. The match registers can be used to wake the processor from hibernation mode, or to generate an interrupt to the processor if it is not in hibernation. The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1 registers. The RTC can be configured to generate interrupts by using the interrupt registers (see “Interrupts and Status” on page 243). As long as the RTC is enabled and a valid VBAT is present, the RTC continues counting, regardless of whether VDD is present or if the part is in hibernation. 6.3.5 Battery-Backed Memory The Hibernation module contains 64 32-bit words of memory which are retained during hibernation. This memory is powered from the battery or auxiliary power supply during hibernation. The processor software can save state information in this memory prior to hibernation, and can then recover the state upon waking. The battery-backed memory can be accessed through the HIBDATA registers. 242 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 6.3.6 Power Control Important: The Hibernation Module requires special system implementation considerations when using HIB to control power, as it is intended to power-down all other sections of its host device. All system signals and power supplies that connect to the chip must be driven to 0 VDC or powered down with the same regulator controlled by HIB. See “Hibernation Module” on page 775 for more details. The Hibernation module controls power to the microcontroller through the use of the HIB pin. This pin is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V and/or 2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external regulator is turned off and no longer powers the system. The Hibernation module remains powered from the VBAT supply (which could be a battery or an auxiliary power source) until a Wake event. Power to the device is restored by deasserting the HIB signal, which causes the external regulator to turn power back on to the chip. 6.3.7 Initiating Hibernate Hibernation mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC match. The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power supply as the logic 1 reference. When the Hibernation module wakes, the microcontroller will see a normal power-on reset. Software can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see “Interrupts and Status” on page 243) and by looking for state data in the battery-backed memory (see “Battery-Backed Memory” on page 242). When the HIB signal deasserts, enabling the external regulator, the external regulator must reach the operating voltage within tHIB_TO_VDD. 6.3.8 Interrupts and Status The Hibernation module can generate interrupts when the following conditions occur: ■ Assertion of WAKE pin ■ RTC match ■ Low battery detected All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time. The software interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can also read the status of the Hibernation module at any time by reading the HIBRIS register which shows all of the pending events. This register can be used at power-on to see if a wake condition is pending, which indicates to the software that a hibernation wake occurred. The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register. July 17, 2014 243 Texas Instruments-Production Data Hibernation Module 6.4 Initialization and Configuration The Hibernation module can be set in several different configurations. The following sections show the recommended programming sequence for various scenarios. The examples below assume that a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the Hibernation module runs at 32.768 kHz and is asynchronous to the rest of the system, software must allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access Timing” on page 240). The registers that require a delay are listed in a note in “Register Map” on page 245 as well as in each register description. 6.4.1 Initialization The Hibernation module clock source must be enabled first, even if the RTC feature is not used. If a 4.194304-MHz crystal is used, perform the following steps: 1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128 input path. 2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any other operations with the Hibernation module. If a 32.678-kHz oscillator is used, then perform the following steps: 1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input. 2. No delay is necessary. The above is only necessary when the entire system is initialized for the first time. If the processor is powered due to a wake from hibernation, then the Hibernation module has already been powered up and the above steps are not necessary. The software can detect that the Hibernation module and clock are already powered by examining the CLK32EN bit of the HIBCTL register. 6.4.2 RTC Match Functionality (No Hibernation) Use the following steps to implement the RTC match functionality of the Hibernation module: 1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the HIBIM register at offset 0x014. 4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting. 6.4.3 RTC Match/Wake-Up from Hibernation Use the following steps to implement the RTC match and wake-up functionality of the Hibernation module: 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 244 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the HIBCTL register at offset 0x010. 6.4.4 External Wake-Up from Hibernation Use the following steps to implement the Hibernation module with the external WAKE pin as the wake-up source for the microcontroller: 1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the HIBCTL register at offset 0x010. 6.4.5 RTC/External Wake-Up from Hibernation 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F to the HIBCTL register at offset 0x010. 6.5 Register Map Table 6-2 on page 245 lists the Hibernation registers. All addresses given are relative to the Hibernation Module base address at 0x400F.C000. Note that the Hibernation module clock must be enabled before the registers can be programmed (see page 217). There must be a delay of 3 system clocks after the Hibernation module clock is enabled before any Hibernation module registers are accessed. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 240. Important: The Hibernation module registers are reset under two conditions: 1. A system reset when the RTCEN and the PINWEN bits in the HIBCTL register are both cleared. 2. A cold POR, when both the VDD and VBAT supplies are removed. Any other reset condition is ignored by the Hibernation module. Table 6-2. Hibernation Module Register Map Offset Name 0x000 Description See page Type Reset HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 247 0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 248 0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 249 0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 250 July 17, 2014 245 Texas Instruments-Production Data Hibernation Module Table 6-2. Hibernation Module Register Map (continued) Name Type Reset 0x010 HIBCTL R/W 0x8000.0000 Hibernation Control 251 0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 254 0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 255 0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 256 0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 257 0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 258 0x0300x12C HIBDATA R/W - Hibernation Data 259 6.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the Hibernation module registers, in numerical order by address offset. 246 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 This register is the current 32-bit value of the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 240. Hibernation RTC Counter (HIBRTCC) Base 0x400F.C000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RTCC Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RTCC Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type 31:0 RTCC RO RO 0 Reset RO 0 Description 0x0000.0000 RTC Counter A read returns the 32-bit counter value. This register is read-only. To change the value, use the HIBRTCLD register. July 17, 2014 247 Texas Instruments-Production Data Hibernation Module Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit match 0 register for the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 240. Hibernation RTC Match 0 (HIBRTCM0) Base 0x400F.C000 Offset 0x004 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM0 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RTCM0 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 RTCM0 R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF RTC Match 0 A write loads the value into the RTC match register. A read returns the current match value. 248 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 This register is the 32-bit match 1 register for the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 240. Hibernation RTC Match 1 (HIBRTCM1) Base 0x400F.C000 Offset 0x008 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM1 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RTCM1 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 RTCM1 R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF RTC Match 1 A write loads the value into the RTC match register. A read returns the current match value. July 17, 2014 249 Texas Instruments-Production Data Hibernation Module Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C This register is the 32-bit value loaded into the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 240. Hibernation RTC Load (HIBRTCLD) Base 0x400F.C000 Offset 0x00C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCLD Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RTCLD Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 RTCLD R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. 250 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 5: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. Hibernation Control (HIBCTL) Base 0x400F.C000 Offset 0x010 Type R/W, reset 0x8000.0000 31 30 29 28 27 26 25 24 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 WRC Type Reset 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 HIBREQ RTCEN R/W 0 R/W 0 reserved reserved Type Reset 22 VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL RO 0 Bit/Field Name Type Reset 31 WRC RO 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Write Complete/Capable This bit indicates whether the hibernation module can receive a write operation. Value Description 0 The interface is processing a prior write and is busy. Any write operation that is attempted while WRC is 0 results in undetermined behavior. 1 The interface is ready to accept a write. Software must poll this bit between write requests and defer writes until WRC=1 to ensure proper operation. This difference may be exploited by software at reset time to detect which method of programming is appropriate: 0 = software delay loops required; 1 = WRC paced available. The bit name WRC means "Write Complete," which is the normal use of the bit (between write accesses). However, because the bit is set out-of-reset, the name can also mean "Write Capable" which simply indicates that the interface may be written to by software. This meaning also has more meaning to the out-of-reset sense. 30:8 reserved RO 0x00 7 VABORT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power Cut Abort Enable Value Description 0 Power cut occurs during a low-battery alert. 1 Power cut is aborted. July 17, 2014 251 Texas Instruments-Production Data Hibernation Module Bit/Field Name Type Reset 6 CLK32EN R/W 0 Description Clocking Enable Value Description 0 Disabled 1 Enabled This bit must be enabled to use the Hibernation module. If a crystal is used, then software should wait 20 ms after setting this bit to allow the crystal to power up and stabilize. 5 LOWBATEN R/W 0 Low Battery Monitoring Enable Value Description 0 Disabled 1 Enabled When set, low battery voltage detection is enabled (VBAT < VLOWBAT). 4 PINWEN R/W 0 External WAKE Pin Enable Value Description 0 Disabled 1 Enabled When set, an external event on the WAKE pin will re-power the device. 3 RTCWEN R/W 0 RTC Wake-up Enable Value Description 0 Disabled 1 Enabled When set, an RTC match event (RTCM0 or RTCM1) will re-power the device based on the RTC counter value matching the corresponding match register 0 or 1. 2 CLKSEL R/W 0 Hibernation Module Clock Select Value 1 HIBREQ R/W 0 Description 0 Use Divide by 128 output. Use this value for a 4.194304-MHz crystal. 1 Use raw output. Use this value for a 32.768-kHz oscillator. Hibernation Request Value Description 0 Disabled 1 Hibernation initiated After a wake-up event, this bit is cleared by hardware. 252 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 0 RTCEN R/W 0 Description RTC Timer Enable Value Description 0 Disabled 1 Enabled July 17, 2014 253 Texas Instruments-Production Data Hibernation Module Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Hibernation Interrupt Mask (HIBIM) Base 0x400F.C000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset EXTW Bit/Field Name Type Reset 31:4 reserved RO 0x000.0000 3 EXTW R/W 0 LOWBAT R/W 0 RTCALT1 R/W 0 RTCALT0 R/W 0 R/W 0 R/W 0 External Wake-Up Interrupt Mask Description 0 Masked 1 Unmasked Low Battery Voltage Interrupt Mask Description 0 Masked 1 Unmasked RTC Alert1 Interrupt Mask Value 0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Value 1 LOWBAT RTCALT1 RTCALT0 Description Value 2 R/W 0 Description 0 Masked 1 Unmasked RTC Alert0 Interrupt Mask Value Description 0 Masked 1 Unmasked 254 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Hibernation Raw Interrupt Status (HIBRIS) Base 0x400F.C000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset EXTW RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Raw Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status LOWBAT RTCALT1 RTCALT0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 255 Texas Instruments-Production Data Hibernation Module Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset EXTW RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Masked Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status LOWBAT RTCALT1 RTCALT0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 256 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Hibernation Interrupt Clear (HIBIC) Base 0x400F.C000 Offset 0x020 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 reserved Type Reset reserved Type Reset EXTW Bit/Field Name Type Reset 31:4 reserved RO 0x000.0000 3 EXTW R/W1C 0 LOWBAT RTCALT1 RTCALT0 R/W1C 0 R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Masked Interrupt Clear Reads return an indeterminate value. 2 LOWBAT R/W1C 0 Low Battery Voltage Masked Interrupt Clear Reads return an indeterminate value. 1 RTCALT1 R/W1C 0 RTC Alert1 Masked Interrupt Clear Reads return an indeterminate value. 0 RTCALT0 R/W1C 0 RTC Alert0 Masked Interrupt Clear Reads return an indeterminate value. July 17, 2014 257 Texas Instruments-Production Data Hibernation Module Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 240. Hibernation RTC Trim (HIBRTCT) Base 0x400F.C000 Offset 0x024 Type R/W, reset 0x0000.7FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 TRIM Type Reset R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TRIM R/W 0x7FFF RTC Trim Value This value is loaded into the RTC predivider every 64 seconds. It is used to adjust the RTC rate to account for drift and inaccuracy in the clock source. The compensation is made by software by adjusting the default value of 0x7FFF up or down. 258 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the system processor in order to store state information and does not lose power during a power-cut operation as long as a battery is present. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 240. Hibernation Data (HIBDATA) Base 0x400F.C000 Offset 0x030-0x12C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - RTD Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 RTD Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 RTD R/W - R/W - Description Hibernation Module NV Registers[63:0] July 17, 2014 259 Texas Instruments-Production Data Internal Memory 7 Internal Memory The LM3S5732 microcontroller comes with 64 KB of bit-banded SRAM and 128 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1 on page 260 illustrates the Flash functions. The dashed boxes in the figure indicate registers residing in the System Control module rather than the Flash Control module. Figure 7-1. Flash Block Diagram ROM Control ROM Array RMCTL Icode Bus Cortex-M3 System Bus Dcode Bus Flash Control FMA FMD FMC FCRIS FCIM FCMISC Flash Array Flash Protection Bridge FMPREn FMPPEn Flash Timing USECRL User Registers USER_DBG USER_REG0 USER_REG1 USER_REG2 USER_REG3 SRAM Array 7.2 Functional Description This section describes the functionality of the SRAM, ROM, and Flash memories. 7.2.1 SRAM Memory Note: The SRAM memory is implemented using two 32-bit wide SRAM banks (separate SRAM arrays). The banks are partitioned so that one bank contains all even words (the even bank) and the other contains all odd words (the odd bank). A write access that is followed immediately by a read access to the same bank will incur a stall of a single clock cycle. However, a write to one bank followed by a read of the other bank can occur in successive clock cycles without incurring any delay. 260 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ® The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, see “Bit-Banding” on page 76. 7.2.2 ROM Memory The ROM of the Stellaris device is located at address 0x0100.0000 of the device memory map and contains the following components: ■ Stellaris Boot Loader and vector table (see “Boot Loader” on page 781) ■ Stellaris Peripheral Driver Library (DriverLib) release for product-specific peripherals and interfaces (see “ROM DriverLib Functions” on page 786) 7.2.3 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 7.2.3.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. July 17, 2014 261 Texas Instruments-Production Data Internal Memory 7.2.3.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in two pairs of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may be executed or read by software or debuggers. If a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. The policies may be combined as shown in Table 7-1 on page 262. Table 7-1. Flash Protection Policy Combinations FMPPEn FMPREn Protection 0 0 Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. 1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. 0 1 Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 1 1 No protection. The block may be written, erased, executed or read. A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited and generates a bus fault. A Flash memory access that attempts to program or erase a program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt (by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. These settings create a policy of open access and programmability. The register bits may be changed by clearing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The changes are committed using the Flash Memory Control (FMC) register. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 264. 7.2.3.3 Execute-Only Protection Execute-only protection prevents both modification and visibility to a protected flash block. This mode is intended to be used in situations where a device requires debug capability, yet portions of the application space must be protected from external access. An example of this is a company who wishes to sell Stellaris devices with their proprietary software pre-programmed, yet allow the end user to add custom code to an unprotected region of the flash (such as a motor control module with a customizable motor configuration section in flash). Literal data introduces a complication to the protection mechanism. When C code is compiled and linked, literal data (constants, and so on) is typically placed in the text section, between functions, by the compiler. The literal data is accessed at run time through the use of the LDR instruction, which loads the data from memory using a PC-relative memory address. The execution of the LDR instruction generates a read transaction across the Cortex-M3's DCode bus, which is subject to the 262 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller execute-only protection mechanism. If the accessed block is marked as execute only, the transaction is blocked, and the processor is prevented from loading the constant data and, therefore, inhibiting correct execution. Therefore, using execute-only protection requires that literal data be handled differently. There are three ways to address this: 1. Use a compiler that allows literal data to be collected into a separate section that is put into one or more read-enabled flash blocks. Note that the LDR instruction may use a PC-relative address–-in which case the literal pool cannot be located outside the span of the offset–-or the software may reserve a register to point to the base address of the literal pool and the LDR offset is relative to the beginning of the pool. 2. Use a compiler that generates literal data from arithmetic instruction immediate data and subsequent computation. 3. Use method 1 or 2, but in assembly language, if the compiler does not support either method. 7.2.3.4 Read-Only Protection Read-only protection prevents the contents of the flash block from being re-programmed, while still allowing the content to be read by processor or the debug interface. Note that if a FMPREn bit is cleared, all read accesses to the Flash memory block are disallowed, including any data accesses. Care must be taken not to store required data in a Flash memory block that has the associated FMPREn bit cleared. The read-only mode does not prevent read access to the stored program, but it does provide protection against accidental (or malicious) erasure or programming. Read-only is especially useful for utilities like the boot loader when the debug interface is permanently disabled. In such combinations, the boot loader, which provides access control to the Flash memory, is protected from being erased or modified. 7.2.3.5 Permanently Disabling Debug For extremely sensitive applications, the debug interface to the processor and peripherals can be permanently disabled, blocking all accesses to the device through the JTAG or SWD interfaces. With the debug interface disabled, it is still possible to perform standard IEEE instructions (such as boundary scan operations), but access to the processor and peripherals is blocked. The DBG0 and DBG1 bits of the User Debug (USER_DBG) register control whether the debug interface is turned on or off. The debug interface should not be permanently disabled without providing some mechanism–-such as the boot loader–-to provide customer-installable updates or bug fixes. Disabling the debug interface is permanent and cannot be reversed. 7.2.3.6 Interrupts The Flash memory controller can generate interrupts when the following conditions are observed: ■ Programming Interrupt - signals when a program or erase action is complete. ■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block of memory that is protected by its corresponding FMPPEn bit. The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller Masked Interrupt Status (FCMIS) register (see page 273) by setting the corresponding MASK bits. If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw Interrupt Status (FCRIS) register (see page 272). July 17, 2014 263 Texas Instruments-Production Data Internal Memory Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register (see page 274). 7.3 Flash Memory Initialization and Configuration 7.3.1 Flash Programming The Stellaris devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD, and FMC. During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation is complete. If instruction execution is required during a Flash memory operation, the code that is executing must be placed in SRAM and executed from there while the flash operation is in progress. 7.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 7.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. 7.3.1.3 To perform a mass erase of the flash 1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. 7.3.2 Nonvolatile Register Programming Note: The USER_DBG register requires a POR before the committed changes take effect. This section discusses how to update registers that are resident within the Flash memory itself. These registers exist in a separate space from the main Flash memory array and are not affected by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0 with a write operation. Prior to being committed, the register contents are unaffected by any reset condition except power-on reset, which returns the register contents to the original value. By committing the register values using the COMT bit in the FMC register, the register contents become nonvolatile and are therefore retained following power cycling. Once the register contents are committed, the only way to restore the factory default values is to perform the sequence described in the section called “Recovering a "Locked" Device” on page 164. With the exception of the USER_DBG register, the settings in these registers can be tested before committing them to Flash memory. For the USER_DBG register, the data to be written is loaded 264 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller into the FMD register before it is committed. The FMD register is read only and does not allow the USER_DBG operation to be tried before committing it to nonvolatile memory. Important: The Flash memory resident registers can only have bits changed from 1 to 0 by user programming and can only be committed once. After being committed, these registers can only be restored to their factory default values only by performing the sequence described in the section called “Recovering a "Locked" Device” on page 164. The mass erase of the main Flash memory array caused by the sequence is performed prior to restoring these registers. In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and USER_DBG registers each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be changed from 1 to 0. Table 7-2 on page 265 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 7-2. User-Programmable Flash Memory Resident Registers Register to be Committed 7.4 FMA Value Data Source FMPRE0 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.0001 USER_REG1 USER_REG2 0x8000.0002 USER_REG2 USER_REG3 0x8000.0003 USER_REG3 USER_DBG 0x7510.0000 FMD Register Map Table 7-3 on page 265 lists the ROM Controller register and the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC register offsets are relative to the Flash memory control base address of 0x400F.D000. The ROM and Flash memory protection register offsets are relative to the System Control base address of 0x400F.E000. Table 7-3. Flash Register Map Offset Name Type Reset Description See page - ROM Control 267 ROM Registers (System Control Offset) 0x0F0 RMCTL R/W1C Flash Memory Control Registers (Flash Control Offset) 0x000 FMA R/W 0x0000.0000 Flash Memory Address 268 0x004 FMD R/W 0x0000.0000 Flash Memory Data 269 0x008 FMC R/W 0x0000.0000 Flash Memory Control 270 July 17, 2014 265 Texas Instruments-Production Data Internal Memory Table 7-3. Flash Register Map (continued) See page Offset Name Type Reset Description 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 272 0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 273 0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 274 Flash Memory Protection Registers (System Control Offset) 0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 277 0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 277 0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 278 0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 278 0x140 USECRL R/W 0x31 USec Reload 276 0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 279 0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 280 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 281 0x1E8 USER_REG2 R/W 0xFFFF.FFFF User Register 2 282 0x1EC USER_REG3 R/W 0xFFFF.FFFF User Register 3 283 0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 284 0x208 FMPRE2 R/W 0x0000.0000 Flash Memory Protection Read Enable 2 285 0x20C FMPRE3 R/W 0x0000.0000 Flash Memory Protection Read Enable 3 286 0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 287 0x408 FMPPE2 R/W 0x0000.0000 Flash Memory Protection Program Enable 2 288 0x40C FMPPE3 R/W 0x0000.0000 Flash Memory Protection Program Enable 3 289 7.5 ROM Register Descriptions (System Control Offset) This section lists and describes the ROM Controller registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. 266 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 1: ROM Control (RMCTL), offset 0x0F0 This register provides control of the ROM controller state. ROM Control (RMCTL) Base 0x400F.E000 Offset 0x0F0 Type R/W1C, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C - reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0 0 BA R/W1C - RO 0 BA Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Boot Alias ■ The device has ROM. ■ The first two words of the Flash memory contain 0xFFFF.FFFF. This bit is cleared by writing a 1 to this bit position. When the BA bit is set, the boot alias is in effect and the ROM appears at address 0x0. When the BA bit is clear, the Flash appears at address 0x0. 7.6 Flash Register Descriptions (Flash Control Offset) This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. July 17, 2014 267 Texas Instruments-Production Data Internal Memory Register 2: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 16 OFFSET OFFSET Type Reset Bit/Field Name Type Reset Description 31:17 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16:0 OFFSET R/W 0x0 Address Offset Address offset in flash where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 264 for details on values for this field). 268 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 3: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DATA Type Reset DATA Type Reset Bit/Field Name Type Reset Description 31:0 DATA R/W 0x0 Data Value Data value for write operation. July 17, 2014 269 Texas Instruments-Production Data Internal Memory Register 4: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 268). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 269) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 COMT MERASE ERASE WRITE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 WRKEY Type Reset reserved Type Reset Bit/Field Name Type Reset 31:16 WRKEY WO 0x0 Description Flash Write Key This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 15:4 reserved RO 0x0 3 COMT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Commit Register Value Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 μs. 2 MERASE R/W 0 Mass Erase Flash Memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. 270 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 1 ERASE R/W 0 Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 0 WRITE R/W 0 Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 µs. July 17, 2014 271 Texas Instruments-Production Data Internal Memory Register 5: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PRIS ARIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 PRIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Raw Interrupt Status This bit provides status on programming cycles which are write or erase actions generated through the FMC register bits (see page 270). Value Description 1 The programming cycle has completed. 0 The programming cycle has not completed. This status is sent to the interrupt controller when the PMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register. 0 ARIS RO 0 Access Raw Interrupt Status Value Description 1 A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. 0 No access has tried to improperly program or erase the Flash memory. This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register. 272 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 6: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PMASK AMASK RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 PMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the interrupt controller. Value Description 0 AMASK R/W 0 1 An interrupt is sent to the interrupt controller when the PRIS bit is set. 0 The PRIS interrupt is suppressed and not sent to the interrupt controller. Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the interrupt controller. Value Description 1 An interrupt is sent to the interrupt controller when the ARIS bit is set. 0 The ARIS interrupt is suppressed and not sent to the interrupt controller. July 17, 2014 273 Texas Instruments-Production Data Internal Memory Register 7: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:2 reserved RO 0x0 1 PMISC R/W1C 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 1 0 PMISC AMISC R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. Writing a 1 to this bit clears PMISC and also the PRIS bit in the FCRIS register (see page 272). 0 When read, a 0 indicates that a programming cycle complete interrupt has not occurred. A write of 0 has no effect on the state of this bit. 0 AMISC R/W1C 0 Access Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. Writing a 1 to this bit clears AMISC and also the ARIS bit in the FCRIS register (see page 272). 0 When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit. 274 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 7.7 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. July 17, 2014 275 Texas Instruments-Production Data Internal Memory Register 8: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. USec Reload (USECRL) Base 0x400F.E000 Offset 0x140 Type R/W, reset 0x31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 USEC RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 USEC R/W 0x31 Microsecond Reload Value MHz -1 of the controller clock when the flash is being erased or programmed. If the maximum system frequency is being used, USEC should be set to 0x31 (50 MHz) whenever the flash is being erased or programmed. 276 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 9: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.E000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. July 17, 2014 277 Texas Instruments-Production Data Internal Memory Register 10: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.E000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 PROG_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. 278 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 11: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0 disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once commited, the value of this register can never be restored to the factory default value. User Debug (USER_DBG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset 31 NW R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 1 0 DBG1 DBG0 R/W 1 R/W 0 Description User Debug Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:2 DATA R/W 0x1FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 1 DBG1 R/W 1 Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. July 17, 2014 279 Texas Instruments-Production Data Internal Memory Register 12: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once commited, the value of this register can never be restored to the factory default value. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 280 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 13: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once commited, the value of this register can never be restored to the factory default value. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. July 17, 2014 281 Texas Instruments-Production Data Internal Memory Register 14: User Register 2 (USER_REG2), offset 0x1E8 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once commited, the value of this register can never be restored to the factory default value. User Register 2 (USER_REG2) Base 0x400F.E000 Offset 0x1E8 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 282 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 15: User Register 3 (USER_REG3), offset 0x1EC Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once commited, the value of this register can never be restored to the factory default value. User Register 3 (USER_REG3) Base 0x400F.E000 Offset 0x1EC Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. July 17, 2014 283 Texas Instruments-Production Data Internal Memory Register 16: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. 284 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 17: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 0 Reset R/W 0 R/W 0 Description 0x00000000 Flash Read Enable Configures 2-KB flash blocks to be read only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 129 to 192 KB. July 17, 2014 285 Texas Instruments-Production Data Internal Memory Register 18: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 0 Reset R/W 0 R/W 0 Description 0x00000000 Flash Read Enable Configures 2-KB flash blocks to be read only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 193 to 256 KB. 286 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 19: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. July 17, 2014 287 Texas Instruments-Production Data Internal Memory Register 20: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 0 R/W 0 Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 129 to 192 KB. 288 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 21: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 0 R/W 0 Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 193 to 256 KB. July 17, 2014 289 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 8 Micro Direct Memory Access (μDMA) The LM3S5732 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing for more efficient use of the processor and the expanded available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported peripheral and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller also supports sophisticated transfer modes such as ping-pong and scatter-gather, which allows the processor to set up a list of transfer tasks for the controller. The μDMA controller has the following features: ■ ARM PrimeCell® 32-channel configurable µDMA controller ■ Support for multiple transfer modes – Basic, for simple transfer scenarios – Ping-pong, for continuous data flow to/from peripherals – Scatter-gather, from a programmable list of up to 256 arbitrary transfers initiated from a single request ■ Dedicated channels for supported peripherals ■ One channel each for receive and transmit path for bidirectional peripherals ■ Dedicated channel for software-initiated transfers ■ Independently configured and operated channels ■ Per-channel configurable bus arbitration scheme ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping – Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Source and destination address increment size of byte, half-word, word, or no increment ■ Maskable device requests ■ Optional software initiated requests for any channel ■ Interrupt on transfer completion, with a separate interrupt per channel 290 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 8.1 Block Diagram Figure 8-1. μDMA Block Diagram μDMA Controller DMA error System Memory CH Control Table request Peripheral done DMA Channel 0 • • • request Peripheral DMA Channel N-1 done Nested Vectored Interrupt Controller (NVIC) IRQ General Peripheral N Registers request done DMASTAT DMACFG DMACTLBASE DMAALTBASE DMAWAITSTAT DMASWREQ DMAUSEBURSTSET DMAUSEBURSTCLR DMAREQMASKSET DMAREQMASKCLR DMAENASET DMAENACLR DMAALTSET DMAALTCLR DMAPRIOSET DMAPRIOCLR DMAERRCLR DMASRCENDP DMADSTENDP DMACHCTRL • • • DMASRCENDP DMADSTENDP DMACHCTRL Transfer Buffers Used by uDMA ARM Cortex-M3 8.2 Functional Description The μDMA controller is a flexible and highly configurable DMA controller designed to work effeciently with the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow for sophisticated programmed data transfers. The DMA controller's usage of the bus is always subordinate to the processor core, and so it will never hold up a bus transaction by the processor. Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth it provides is essentially free, with no impact on the rest of the system. The bus architecture has been optimized to greatly reduce contention between the processor core and the μDMA controller, thus improving performance. The optimizations include RAM striping and peripheral bus segmentation, which in many cases allows both the processor core and the μDMA controller to access the bus and perform simultaneous data transfers. Each peripheral function that is supported has a dedicated channel on the μDMA controller that can be configured independently. The μDMA controller makes use of a unique configuration method by using channel control structures that are maintained in system memory by the processor. While simple transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that allow the controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The controller also supports the use of ping-pong buffering to accomodate constant streaming of data to or from a peripheral. Each channel also has a configurable arbitration size. The arbitration size is the number of items that will be transferred in a burst before the controller rearbitrates for channel priority. Using the arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time it makes a DMA service request. July 17, 2014 291 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 8.2.1 Channel Assigments μDMA channels 0-31 are assigned to peripherals according to the following table. Note: Channels that are not listed in the table may be assigned to peripherals in the future. However, they are currently available for software use. Table 8-1. DMA Channel Assignments 8.2.2 DMA Channel Peripheral Assigned 0 USB Endpoint 1 Receive 1 USB Endpoint 1 Transmit 2 USB Endpoint 2 Receive 3 USB Endpoint 2 Transmit 4 USB Endpoint 3 Receive 5 USB Endpoint 3 Transmit 8 UART0 Receive 9 UART0 Transmit 10 SSI0 Receive 11 SSI0 Transmit 22 UART1 Receive 23 UART1 Transmit 30 Dedicated for software use Priority The μDMA controller assigns priority to each channel based on the channel number and the priority level bit for the channel. Channel number 0 has the highest priority and as the channel number increases, the priority of a channel decreases. Each channel has a priority level bit to provide two levels of priority: default priority and high priority. If the priority level bit is set, then that channel has higher priority than all other channels at default priority. If multiple channels are set for high priority, then the channel number is used to determine relative priority among all the high priority channels. The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET) register, and cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register. 8.2.3 Arbitration Size When a μDMA channel requests a transfer, the μDMA controller arbitrates between all the channels making a request and services the DMA channel with the highest priority. Once a transfer begins, it continues for a selectable number of transfers before rearbitrating among the requesting channels again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers. After the μDMA controller transfers the number of items specified by the arbitration size, it then checks among all the channels making a request and services the channel with the highest priority. If a lower priority DMA channel uses a large arbitration size, the latency for higher priority channels will be increased because the μDMA controller will complete the lower priority burst before checking for higher priority requests. Therefore, lower priority channels should not use a large arbitration size for best response on high priority channels. The arbitration size can also be thought of as a burst size. It is the maximum number of items that will be transferred at any one time in a burst. Here, the term arbitration refers to determination of DMA channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, 292 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller the processor always takes priority. Furthermore, the μDMA controller will be held off whenever the processor needs to perform a bus transaction on the same bus, even in the middle of a burst transfer. 8.2.4 Request Types The μDMA controller responds to two types of requests from a peripheral: single or burst. Each peripheral may support either or both types of requests. A single request means that the peripheral is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple items. The μDMA controller responds differently depending on whether the peripheral is making a single request or a burst request. If both are asserted and the μDMA channel has been set up for a burst transfer, then the burst request takes precedence. See Table 8-2 on page 293, which shows how each peripheral supports the two request types. Table 8-2. Request Type Support 8.2.4.1 Peripheral Single Request Signal Burst Request Signal USB TX None FIFO TXRDY USB RX None FIFO RXRDY UART TX TX FIFO Not Full TX FIFO Level (configurable) UART RX RX FIFO Not Empty RX FIFO Level (configurable) SSI TX TX FIFO Not Full TX FIFO Level (fixed at 4) SSI RX RX FIFO Not Empty RX FIFO Level (fixed at 4) Single Request When a single request is detected, and not a burst request, the μDMA controller will transfer one item, and then stop and wait for another request. 8.2.4.2 Burst Request When a burst request is detected, the μDMA controller will transfer the number of items that is the lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration size should be the same as the number of data items that the peripheral can accomodate when making a burst request. For example, the UART will generate a burst request based on the FIFO trigger level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer when the trigger level is reached. It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps the nature of the data is such that it only makes sense when transferred together as a single unit rather than one piece at a time. The single request can be disabled by using the DMA Channel Useburst Set (DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the μDMA controller will only respond to burst requests for that channel. 8.2.5 Channel Configuration The μDMA controller uses an area of system memory to store a set of channel control structures in a table. The control table may have one or two entries for each DMA channel. Each entry in the table structure contains source and destination pointers, transfer size, and transfer mode. The control table can be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary. Table 8-3 on page 294 shows the layout in memory of the channel control table. Each channel may have one or two control structures in the contol table: a primary control structure and an optional July 17, 2014 293 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) alternate control structure. The table is organized so that all of the primary entries are in the first half of the table and all the alternate structures are in the second half of the table. The primary entry is used for simple transfer modes where transfers can be reconfigured and restarted after each transfer is complete. In this case, the alternate control structures are not used and therefore only the first half of the table needs to be allocated in memory. The second half of the control table is not needed and that memory can be used for something else. If a more complex transfer mode is used such as ping-pong or scatter-gather, then the alternate control structure is also used and memory space should be allocated for the entire table. Any unused memory in the control table may be used by the application. This includes the control structures for any channels that are unused by the application as well as the unused control word for each channel. Table 8-3. Control Structure Memory Map Offset Channel 0x0 0, Primary 0x10 1, Primary ... ... 0x1F0 31, Primary 0x200 0, Alternate 0x210 1, Alternate ... ... 0x3F0 31, Alternate Table 8-4 on page 294 shows an individual control structure entry in the control table. Each entry has a source and destination end pointer. These pointers point to the ending address of the transfer and are inclusive. If the source or destination is non-incrementing (as for a peripheral register), then the pointer should point to the transfer address. Table 8-4. Channel Control Structure Offset Description 0x000 Source End Pointer 0x004 Destination End Pointer 0x008 Control Word 0x00C Unused The remaining part of the control structure is the control word. The control word contains the following fields: ■ Source and destination data sizes ■ Source and destination address increment size ■ Number of transfers before bus arbitration ■ Total number of items to transfer ■ Useburst flag ■ Transfer mode 294 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The control word and each field are described in detail in “μDMA Channel Control Structure” on page 311. The μDMA controller updates the transfer size and transfer mode fields as the transfer is performed. At the end of a transfer, the transfer size will indicate 0, and the transfer mode will indicate "stopped". Since the control word is modified by the μDMA controller, it must be reconfigured before each new transfer. The source and destination end pointers are not modified so they can be left unchanged if the source or destination addresses remain the same. Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the DMA Channel Enable Set ((DMAENASET) register. A channel can be disabled by setting the channel bit in the DMA Channel Enable Clear (DMAENACLR) register. At the end of a complete DMA transfer, the controller will automatically disable the channel. 8.2.6 Transfer Modes The μDMA controller supports several transfer modes. Two of the modes support simple one-time transfers. There are several complex modes that are meant to support a continuous flow of data. 8.2.6.1 Stop Mode While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word. When the mode field has this value, the μDMA controller will not perform a transfer and will disable the channel if it is enabled. At the end of a transfer, the μDMA controller will update the control word to set the mode to Stop. 8.2.6.2 Basic Mode In Basic mode, the μDMA controller will perform transfers as long as there are more items to transfer and a transfer request is present. This mode is used with peripherals that assert a DMA request signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any situation where the request is momentary but the entire transfer should be completed. For example, for a software initiated transfer, the request is momentary, and if Basic mode is used then only one item will be transferred on a software request. When all of the items have been transferred using Basic mode, the μDMA controller will set the mode for that channel to Stop. 8.2.6.3 Auto Mode Auto mode is similar to Basic mode, except that once a transfer request is received the transfer will run to completion, even if the DMA request is removed. This mode is suitable for software-triggered transfers. Generally, you would not use Auto mode with a peripheral. When all the items have been transferred using Auto mode, the μDMA controller will set the mode for that channel to Stop. 8.2.6.4 Ping-Pong Ping-Pong mode is used to support a continuous data flow to or from a peripheral. To use Ping-Pong mode, both the primary and alternate data structures are used. Both are set up by the processor for data transfer between memory and a peripheral. Then the transfer is started using the primary control structure. When the transfer using the primary control structure is complete, the μDMA controller will then read the alternate control structure for that channel to continue the transfer. Each time this happens, an interrupt is generated and the processor can reload the control structure for the just-completed transfer. Data flow can continue indefinitely this way, using the primary and alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. July 17, 2014 295 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Refer to Figure 8-2 on page 296 for an example showing operation in Ping-Pong mode. Figure 8-2. Example of Ping-Pong DMA Transaction μDMA Controller SOURCE DEST transfers using BUFFER A transfer continues using alternate Primary Structure Cortex-M3 Processor SOURCE DEST Pe rip Time transfers using BUFFER B SOURCE DEST Alternate Structure SOURCE DEST ral /uD MA Int up t BUFFER B · Process data in BUFFER A · Reload primary structure Pe rip he ral /uD MA Int err transfers using BUFFER A up t BUFFER A · Process data in BUFFER B · Reload alternate structure transfer continues using alternate Primary Structure he err transfer continues using primary Alternate Structure BUFFER A Pe rip he ral /uD MA I transfers using BUFFER B nte rru p t BUFFER B · Process data in BUFFER B · Reload alternate structure 8.2.6.5 Memory Scatter-Gather Memory Scatter-Gather mode is a complex mode used when data needs to be transferred to or from varied locations in memory instead of a set of contiguous locations in a memory buffer. For example, a gather DMA operation could be used to selectively read the payload of several stored packets of a communication protocol, and store them together in sequence in a memory buffer. 296 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller In Memory Scatter-Gather mode, the primary control structure is used to program the alternate control structure from a table in memory. The table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode. Each entry in the table is copied in turn to the alternate structure where it is then executed. The μDMA controller alternates between using the primary control structure to copy the next transfer instruction from the list, and then executing the new transfer instruction. The end of the list is marked by setting the control word for the last entry to use Basic transfer mode. Once the last transfer is performed using Basic mode, the μDMA controller will stop. A completion interrupt will only be generated after the last transfer. It is possible to loop the list by having the last entry copy the primary control structure to point back to the beginning of the list (or to a new list). It is also possible to trigger a set of other channels to perform a transfer, either directly by programming a write to the software trigger for another channel, or indirectly by causing a peripheral action that will result in a μDMA request. By programming the μDMA controller using this method, a set of up to 256 arbitrary transfers can be performed based on a single DMA request. Refer to Figure 8-3 on page 298 and Figure 8-4 on page 299, which show an example of operation in Memory Scatter-Gather mode. This example shows a gather operation, where data in three separate buffers in memory will be copied together into one buffer. Figure 8-3 on page 298 shows how the application sets up a μDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that will be used for the operation is configured to copy from the task list to the alternate control structure. Figure 8-4 on page 299 shows the sequence as the μDMA controller peforms the three sets of copy operations. First, using the primary control structure, the μDMA controller loads the alternate control structure with task A. It then peforms the copy operation specified by task A, copying the data from the source buffer A to the destination buffer. Next, the μDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. July 17, 2014 297 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Figure 8-3. Memory Scatter-Gather, Setup and Configuration 1 2 3 Source and Destination Buffer in Memory Task List in Memory Channel Control Table in Memory 4 WORDS (SRC A) SRC A DST “TASK” A ITEMS=4 SRC SRC DST DST “TASK” B ITEMS=12 Channel Primary Control Structure ITEMS=16 16 WORDS (SRC B) B SRC DST “TASK” C ITEMS=1 SRC DST Channel Alternate Control Structure ITEMS=n 1 WORD (SRC C) C 4 (DEST A) 16 (DEST B) 1 (DEST C) NOTES: 1. Application has a need to copy data items from three separate location in memory into one combined buffer. 2. Application sets up uDMA “task list” in memory, which contains the pointers and control configuration for three uDMA copy “tasks.” 3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it will be executed by the uDMA controller. 298 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence Task List in Memory μDMA Control Table in Memory Buffers in Memory SRC A SRC SRC B PRI COPIED DST TASK A TASK B SRC SRC C ALT COPIED DST TASK C DEST A DEST B DEST C Using the channel’s primary control structure, the μDMA controller copies task A configuration to the channel’s alternate control structure. Task List in Memory Then, using the channel’s alternate control structure, the μDMA controller copies data from the source buffer A to the destination buffer. μDMA Control Table in Memory Buffers in Memory SRC A SRC B SRC PRI DST TASK A SRC TASK B TASK C SRC C COPIED ALT COPIED DST DEST A DEST B DEST C Using the channel’s primary control structure, the μDMA controller copies task B configuration to the channel’s alternate control structure. Task List in Memory Then, using the channel’s alternate control structure, the μDMA controller copies data from the source buffer B to the destination buffer. μDMA Control Table in Memory Buffers in Memory SRC A SRC SRC B PRI DST TASK A SRC TASK B TASK C SRC C ALT DST DEST A COPIED COPIED DEST B DEST C Using the channel’s primary control structure, the μDMA controller copies task C configuration to the channel’s alternate control structure. Then, using the channel’s alternate control structure, the μDMA controller copies data from the source buffer C to the destination buffer. July 17, 2014 299 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 8.2.6.6 Peripheral Scatter-Gather Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers are controlled by a peripheral making a DMA request. Upon detecting a DMA request from the peripheral, the μDMA controller will use the primary control structure to copy one entry from the list to the alternate control structure, and then perform the transfer. At the end of this transfer, the next transfer will only be started if the peripheral again asserts a DMA request. The μDMA controller will continue to perform transfers from the list only when the peripheral is making a request, until the last transfer is complete. A completion interrupt will only be generated after the last transfer. By programming the μDMA controller using this method, data can be transferred to or from a peripheral from a set of arbitrary locations whenever the peripheral is ready to transfer data. Refer to Figure 8-5 on page 301 and Figure 8-6 on page 302, which show an example of operation in Peripheral Scatter-Gather mode. This example shows a gather operation, where data from three separate buffers in memory will be copied to a single peripheral data register. Figure 8-5 on page 301 shows how the application sets up a µDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that will be used for the operation is configured to copy from the task list to the alternate control structure. Figure 8-6 on page 302 shows the sequence as the µDMA controller peforms the three sets of copy operations. First, using the primary control structure, the µDMA controller loads the alternate control structure with task A. It then peforms the copy operation specified by task A, copying the data from the source buffer A to the peripheral data register. Next, the µDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. 300 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration 1 2 3 Source Buffer in Memory Task List in Memory Channel Control Table in Memory 4 WORDS (SRC A) SRC A DST “TASK” A ITEMS=4 SRC SRC DST DST “TASK” B ITEMS=12 Channel Primary Control Structure ITEMS=16 16 WORDS (SRC B) B SRC DST “TASK” C ITEMS=1 SRC DST Channel Alternate Control Structure ITEMS=n 1 WORD (SRC C) C Peripheral Data Register DEST NOTES: 1. Application has a need to copy data items from three separate location in memory into a peripheral data register. 2. Application sets up μDMA “task list” in memory, which contains the pointers and control configuration for three uDMA copy “tasks.” 3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it will be executed by the μDMA controller. July 17, 2014 301 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence μDMA Control Table in Memory Task List in Memory Buffers in Memory SRC A SRC SRC B PRI TASK A TASK B COPIED DST SRC C SRC ALT COPIED TASK C DST Then, using the channel’s alternate control structure, the μDMA controller copies data from the source buffer A to the peripheral data register. Using the channel’s primary control structure, the μDMA controller copies task A configuration to the channel’s alternate control structure. Task List in Memory Peripheral Data Register Buffers in Memory μDMA Control Table in Memory SRC A SRC SRC B PRI DST TASK A TASK B TASK C SRC C SRC ALT COPIED DST Peripheral Data Register Then, using the channel’s alternate control structure, the μDMA controller copies data from the source buffer B to the peripheral data register. Using the channel’s primary control structure, the μDMA controller copies task B configuration to the channel’s alternate control structure. Task List in Memory COPIED Buffers in Memory μDMA Control Table in Memory SRC A SRC SRC B PRI DST TASK A TASK B TASK C SRC C SRC ALT COPIED DST COPIED Peripheral Data Register Using the channel’s primary control structure, the μDMA controller copies task C configuration to the channel’s alternate control structure. Then, using the channel’s alternate control structure, the μDMA controller copies data from the source buffer C to the peripheral data register. 302 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 8.2.7 Transfer Size and Increment The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size must be the same for any given transfer. The source and destination address can be auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and destination address increment values can be set independently, and it is not necessary for the address increment to match the data size as long as the increment is the same or larger than the data size. For example, it is possible to perform a transfer using 8-bit data size, but using an address increment of full words (4 bytes). The data to be transferred must be aligned in memory according to the data size (8, 16, or 32 bits). Table 8-5 on page 303 shows the configuration to read from a peripheral that supplies 8-bit data. Table 8-5. μDMA Read Example: 8-Bit Peripheral 8.2.8 Field Configuration Source data size 8 bits Destination data size 8 bits Source address increment No increment Destination address increment Byte Source end pointer Peripheral read FIFO register Destination end pointer End of the data buffer in memory Peripheral Interface Each peripheral that supports μDMA has a DMA single request and/or burst request signal that is asserted when the device is ready to transfer data. The request signal can be disabled or enabled by using the DMA Channel Request Mask Set (DMAREQMASKSET) and DMA Channel Request Mask Clear (DMAREQMASKCLR) registers. The DMA request signal is disabled, or masked, when the channel request mask bit is set. When the request is not masked, the DMA channel is configured correctly and enabled, and the peripheral asserts the DMA request signal, the μDMA controller will begin the transfer. When a DMA transfer is complete, the μDMA controller asserts a DMA Done signal, which is routed through the interrupt vector of the peripheral. Therefore, if DMA is used to transfer data for a peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed to handle the μDMA transfer completion interrupt. When DMA is enabled for a peripheral, the μDMA controller will mask the normal interrupts for a peripheral. This means that when a large amount of data is transferred using DMA, instead of receiving multiple interrupts from the peripheral as data flows, the processor will only receive one interrupt when the transfer is complete. The interrupt request from the μDMA controller is automatically cleared when the interrupt handler is activated. 8.2.9 Software Request There is a dedicated μDMA channel for software-initiated transfers. This channel also has a dedicated interrupt to signal completion of a DMA transfer. A transfer is initiated by software by first configuring and enabling the transfer, and then issuing a software request using the DMA Channel Software Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should be used. It is possible to initiate a transfer on any channel using the DMASWREQ register. If a request is initiated by software using a peripheral DMA channel, then the completion interrupt will occur on the interrupt vector for the peripheral instead of the software interrupt vector. This means that any July 17, 2014 303 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) channel may be used for software requests as long as the corresponding peripheral is not using μDMA. 8.2.10 Interrupts and Errors When a DMA transfer is complete, the μDMA controller will generate a completion interrupt on the interrupt vector of the peripheral. If the transfer uses the software DMA channel, then the completion interrupt will occur on the dedicated software DMA interrupt vector. If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data transfer, it will disable the DMA channel that caused the error, and generate an interrupt on the μDMA Error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register to determine if an error is pending. The ERRCLR bit will be set if an error occurred. The error can be cleared by writing a 1 to the ERRCLR bit. If the peripheral generates an error that causes an interrupt, the interrupt will be generated on the interrupt vector for that peripheral. This is the same whether or not μDMA is being used with the peripheral. Table 8-6 on page 304 shows the dedicated interrupt assignments for the μDMA controller. Table 8-6. μDMA Interrupt Assignments Interrupt Assignment 46 μDMA Software Channel Transfer 47 μDMA Error 8.3 Initialization and Configuration 8.3.1 Module Initialization Before the μDMA controller can be used, it must be enabled in the System Control block and in the peripheral. The location of the channel control structure must also be programmed. The following steps should be performed one time during system initialization: 1. The μDMA peripheral must be enabled in the System Control block. To do this, set the UDMA bit of the System Control RCGC2 register. 2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG) register. 3. Program the location of the channel control table by writing the base address of the table to the DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be aligned on a 1024-byte boundary. 8.3.2 Configuring a Memory-to-Memory Transfer μDMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used for software-initiated, memory-to-memory transfer if the associated peripheral is not being used. 8.3.2.1 Configure the Channel Attributes First, configure the channel attributes: 1. Set bit 30 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. 304 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 2. Set bit 30 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 30 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 30 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 8.3.2.2 Configure the Channel Control Structure Now the channel control structure must be configured. This example will transfer 256 32-bit words from one memory buffer to another. Channel 30 is used for a software transfer, and the control structure for channel 30 is at offset 0x1E0 of the channel control table. The channel control structure for channel 30 is located at the offsets shown in Table 8-7 on page 305. Table 8-7. Channel Control Structure Offsets for Channel 30 Offset Description Control Table Base + 0x1E0 Channel 30 Source End Pointer Control Table Base + 0x1E4 Channel 30 Destination End Pointer Control Table Base + 0x1E8 Channel 30 Control Word Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). 1. Set the source end pointer at offset 0x1E0 to the address of the source buffer + 0x3FC. 2. Set the destination end pointer at offset 0x1E4 to the address of the destination buffer + 0x3FC. The control word at offset 0x1E8 must be programmed according to Table 8-8 on page 305. Table 8-8. Channel Control Word Configuration for Memory Transfer Example Field in DMACHCTL Bits Value DSTINC 31:30 2 32-bit destination address increment DSTSIZE 29:28 2 32-bit destination data size SRCINC 27:26 2 32-bit source address increment SRCSIZE 25:24 2 32-bit source data size reserved 23:18 0 Reserved ARBSIZE 17:14 3 Arbitrates after 8 transfers XFERSIZE 13:4 255 3 0 N/A for this transfer type 2:0 2 Use Auto-request transfer mode NXTUSEBURST XFERMODE 8.3.2.3 Description Transfer 256 items Start the Transfer Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 30 of the DMA Channel Enable Set (DMAENASET) register. July 17, 2014 305 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 2. Issue a transfer request by setting bit 30 of the DMA Channel Software Request (DMASWREQ) register. The DMA transfer will now take place. If the interrupt is enabled, then the processor will be notified by interrupt when the transfer is complete. If needed, the status can be checked by reading bit 30 of the DMAENASET register. This bit will be automatically cleared when the transfer is complete. The status can also be checked by reading the XFERMODE field of the channel control word at offset 0x1E8. This field will automatically be set to 0 at the end of the transfer. 8.3.3 Configuring a Peripheral for Simple Transmit This example will set up the μDMA controller to transmit a buffer of data to a peripheral. The peripheral has a transmit FIFO with a trigger level of 4. The example peripheral will use μDMA channel 7. 8.3.3.1 Configure the Channel Attributes First, configure the channel attributes: 1. Set bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 8.3.3.2 Configure the Channel Control Structure Now the channel control structure must be configured. This example will transfer 64 8-bit bytes from a memory buffer to the peripheral's transmit FIFO register. This example uses μDMA channel 7, and the control structure for channel 7 is at offset 0x070 of the channel control table. The channel control structure for channel 7 is located at the offsets shown in Table 8-9 on page 306. Table 8-9. Channel Control Structure Offsets for Channel 7 Offset Description Control Table Base + 0x070 Channel 7 Source End Pointer Control Table Base + 0x074 Channel 7 Destination End Pointer Control Table Base + 0x078 Channel 7 Control Word Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). Since the peripheral pointer does not change, it simply points to the peripheral's data register. 1. Set the source end pointer at offset 0x070 to the address of the source buffer + 0x3F. 2. Set the destination end pointer at offset 0x074 to the address of the peripheral's transmit FIFO register. The control word at offset 0x078 must be programmed according to Table 8-10 on page 307. 306 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example Field in DMACHCTL Bits Value DSTINC 31:30 3 Destination address does not increment DSTSIZE 29:28 0 8-bit destination data size SRCINC 27:26 0 8-bit source address increment SRCSIZE 25:24 0 8-bit source data size reserved 23:18 0 Reserved ARBSIZE 17:14 2 Arbitrates after 4 transfers XFERSIZE 13:4 63 Transfer 64 items 3 0 N/A for this transfer type 2:0 1 Use Basic transfer mode NXTUSEBURST XFERMODE Note: 8.3.3.3 Description In this example, it is not important if the peripheral makes a single request or a burst request. Since the peripheral has a FIFO that will trigger at a level of 4, the arbitration size is set to 4. If the peripheral does make a burst request, then 4 bytes will be transferred, which is what the FIFO can accomodate. If the peripheral makes a single request (if there is any space in the FIFO), then one byte will be transferred at a time. If it is important to the application that transfers only be made in bursts, then the channel useburst SET[n] bit should be set by writing a 1 to bit 7 of the DMA Channel Useburst Set (DMAUSEBURSTSET) register. Start the Transfer Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 7 of the DMA Channel Enable Set (DMAENASET) register. The μDMA controller is now configured for transfer on channel 7. The controller will make transfers to the peripheral whenever the peripheral asserts a DMA request. The transfers will continue until the entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller will disable the channel and set the XFERMODE field of the channel control word to 0 (Stopped). The status of the transfer can be checked by reading bit 7 of the DMA Channel Enable Set (DMAENASET) register. This bit will be automatically cleared when the transfer is complete. The status can also be checked by reading the XFERMODE field of the channel control word at offset 0x078. This field will automatically be set to 0 at the end of the transfer. If peripheral interrupts were enabled, then the peripheral interrupt handler would receive an interrupt when the entire transfer was complete. 8.3.4 Configuring a Peripheral for Ping-Pong Receive This example will set up the μDMA controller to continuously receive 8-bit data from a peripheral into a pair of 64 byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example peripheral will use μDMA channel 8. 8.3.4.1 Configure the Channel Attributes First, configure the channel attributes: 1. Set bit 8 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. July 17, 2014 307 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 2. Set bit 8 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 8 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 8 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 8.3.4.2 Configure the Channel Control Structure Now the channel control structure must be configured. This example will transfer 8-bit bytes from the peripheral's receive FIFO register into two memory buffers of 64 bytes each. As data is received, when one buffer is full, the μDMA controller switches to use the other. To use Ping-Pong buffering, both primary and alternate channel control structures must be used. The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the alternate channel control structure is at offset 0x280. The channel control structures for channel 8 are located at the offsets shown in Table 8-11 on page 308. Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 Offset Description Control Table Base + 0x080 Channel 8 Primary Source End Pointer Control Table Base + 0x084 Channel 8 Primary Destination End Pointer Control Table Base + 0x088 Channel 8 Primary Control Word Control Table Base + 0x280 Channel 8 Alternate Source End Pointer Control Table Base + 0x284 Channel 8 Alternate Destination End Pointer Control Table Base + 0x288 Channel 8 Alternate Control Word Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). Since the peripheral pointer does not change, it simply points to the peripheral's data register. Both the primary and alternate sets of pointers must be configured. 1. Set the primary source end pointer at offset 0x080 to the address of the peripheral's receive buffer. 2. Set the primary destination end pointer at offset 0x084 to the address of ping-pong buffer A + 0x3F. 3. Set the alternate source end pointer at offset 0x280 to the address of the peripheral's receive buffer. 4. Set the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer B + 0x3F. The primary control word at offset 0x088, and the alternate control word at offset 0x288 must be programmed according to Table 8-10 on page 307. Both control words are initially programmed the same way. 1. Program the primary channel control word at offset 0x088 according to Table 8-12 on page 309. 2. Program the alternate channel control word at offset 0x288 according to Table 8-12 on page 309. 308 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example Field in DMACHCTL Bits Value DSTINC 31:30 0 8-bit destination address increment DSTSIZE 29:28 0 8-bit destination data size SRCINC 27:26 3 Source address does not increment SRCSIZE 25:24 0 8-bit source data size reserved 23:18 0 Reserved ARBSIZE 17:14 3 Arbitrates after 8 transfers XFERSIZE 13:4 63 Transfer 64 items 3 0 N/A for this transfer type 2:0 3 Use Ping-Pong transfer mode NXTUSEBURST XFERMODE Note: 8.3.4.3 Description In this example, it is not important if the peripheral makes a single request or a burst request. Since the peripheral has a FIFO that will trigger at a level of 8, the arbitration size is set to 8. If the peripheral does make a burst request, then 8 bytes will be transferred, which is what the FIFO can accomodate. If the peripheral makes a single request (if there is any data in the FIFO), then one byte will be transferred at a time. If it is important to the application that transfers only be made in bursts, then the channel useburst SET[n] bit should be set by writing a 1 to bit 8 of the DMA Channel Useburst Set (DMAUSEBURSTSET) register. Configure the Peripheral Interrupt In order to use μDMA Ping-Pong mode, it is best to use an interrupt handler. (It is also possible to use ping-pong mode without interrupts by polling). The interrupt handler will be triggered after each buffer is complete. 1. Configure and enable an interrupt handler for the peripheral. 8.3.4.4 Enable the μDMA Channel Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 8 of the DMA Channel Enable Set (DMAENASET) register. 8.3.4.5 Process Interrupts The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral asserts the DMA request signal, the μDMA controller will make transfers into buffer A using the primary channel control structure. When the primary transfer to buffer A is complete, it will switch to the alternate channel control structure and make transfers into buffer B. At the same time, the primary channel control word mode field will be set to indicate Stopped, and an interrupt will be triggered. When an interrupt is triggered, the interrupt handler must determine which buffer is complete and process the data, or set a flag that the data needs to be processed by non-interrupt buffer processing code. Then the next buffer transfer must be set up. In the interrupt handler: 1. Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the field is 0, this means buffer A is complete. If buffer A is complete, then: July 17, 2014 309 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) a. Process the newly received data in buffer A, or signal the buffer processing code that buffer A has data available. b. Reprogram the primary channel control word at offset 0x88 according to Table 8-12 on page 309. 2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the field is 0, this means buffer B is complete. If buffer B is complete, then: a. Process the newly received data in buffer B, or signal the buffer processing code that buffer B has data available. b. Reprogram the alternate channel control word at offset 0x288 according to Table 8-12 on page 309. 8.4 Register Map Table 8-13 on page 310 lists the μDMA channel control structures and registers. The channel control structure shows the layout of one entry in the channel control table. The channel control table is located in system memory, and the location is determined by the application, that is, the base address is n/a (not applicable). In the table below, the offset for the channel control structures is the offset from the entry in the channel control table. See “Channel Configuration” on page 293 and Table 8-3 on page 294 for a description of how the entries in the channel control table are located in memory. The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers can be programmed (see page 229). There must be a delay of 3 system clocks after the μDMA module clock is enabled before any μDMA module registers are accessed. Table 8-13. μDMA Register Map Offset Name Type Reset Description See page μDMA Channel Control Structure 0x000 DMASRCENDP R/W - DMA Channel Source Address End Pointer 312 0x004 DMADSTENDP R/W - DMA Channel Destination Address End Pointer 313 0x008 DMACHCTL R/W - DMA Channel Control Word 314 DMA Status 318 DMA Configuration 320 μDMA Registers 0x000 DMASTAT RO 0x001F.0000 0x004 DMACFG WO - 0x008 DMACTLBASE R/W 0x0000.0000 DMA Channel Control Base Pointer 321 0x00C DMAALTBASE RO 0x0000.0200 DMA Alternate Channel Control Base Pointer 322 0x010 DMAWAITSTAT RO 0x0000.0000 DMA Channel Wait on Request Status 323 0x014 DMASWREQ WO - DMA Channel Software Request 324 0x018 DMAUSEBURSTSET R/W 0x0000.0000 DMA Channel Useburst Set 325 0x01C DMAUSEBURSTCLR WO - DMA Channel Useburst Clear 327 0x020 DMAREQMASKSET R/W 0x0000.0000 DMA Channel Request Mask Set 328 310 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 8-13. μDMA Register Map (continued) Offset Name Type Reset 0x024 DMAREQMASKCLR WO - 0x028 DMAENASET R/W 0x0000.0000 0x02C DMAENACLR WO - 0x030 DMAALTSET R/W 0x0000.0000 0x034 DMAALTCLR WO - 0x038 DMAPRIOSET R/W 0x0000.0000 0x03C DMAPRIOCLR WO - 0x04C DMAERRCLR R/W 0xFD0 DMAPeriphID4 0xFE0 Description See page DMA Channel Request Mask Clear 330 DMA Channel Enable Set 331 DMA Channel Enable Clear 333 DMA Channel Primary Alternate Set 334 DMA Channel Primary Alternate Clear 336 DMA Channel Priority Set 337 DMA Channel Priority Clear 339 0x0000.0000 DMA Bus Error Clear 340 RO 0x0000.0004 DMA Peripheral Identification 4 346 DMAPeriphID0 RO 0x0000.0030 DMA Peripheral Identification 0 342 0xFE4 DMAPeriphID1 RO 0x0000.00B2 DMA Peripheral Identification 1 343 0xFE8 DMAPeriphID2 RO 0x0000.000B DMA Peripheral Identification 2 344 0xFEC DMAPeriphID3 RO 0x0000.0000 DMA Peripheral Identification 3 345 0xFF0 DMAPCellID0 RO 0x0000.000D DMA PrimeCell Identification 0 347 0xFF4 DMAPCellID1 RO 0x0000.00F0 DMA PrimeCell Identification 1 348 0xFF8 DMAPCellID2 RO 0x0000.0005 DMA PrimeCell Identification 2 349 0xFFC DMAPCellID3 RO 0x0000.00B1 DMA PrimeCell Identification 3 350 8.5 μDMA Channel Control Structure The μDMA Channel Control Structure holds the DMA transfer settings for a DMA channel. Each channel has two control structures, which are located in a table in system memory. Refer to “Channel Configuration” on page 293 for an explanation of the Channel Control Table and the Channel Control Structure. The channel control structure is one entry in the channel control table. There is a primary and alternate structure for each channel. The primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. July 17, 2014 311 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 DMA Channel Source Address End Pointer (DMASRCENDP) is part of the Channel Control Structure, and is used to specify the source address for a DMA transfer. DMA Channel Source Address End Pointer (DMASRCENDP) Base n/a Offset 0x000 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Source Address End Pointer Points to the last address of the DMA transfer source (inclusive). If the source address is not incrementing, then this points at the source location itself (such as a peripheral data register). 312 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 DMA Channel Destination Address End Pointer (DMADSTENDP) is part of the Channel Control Structure, and is used to specify the destination address for a DMA transfer. DMA Channel Destination Address End Pointer (DMADSTENDP) Base n/a Offset 0x004 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Destination Address End Pointer Points to the last address of the DMA transfer destination (inclusive). If the destination address is not incrementing, then this points at the destination location itself (such as a peripheral data register). July 17, 2014 313 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure, and is used to specify parameters of a DMA transfer. DMA Channel Control Word (DMACHCTL) Base n/a Offset 0x008 Type R/W, reset 30 29 R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 DSTINC Type Reset 28 27 DSTSIZE 26 SRCINC ARBSIZE Type Reset R/W - R/W - 25 24 23 22 21 R/W - R/W - R/W - R/W - 8 7 6 5 SRCSIZE 20 19 18 17 R/W - R/W - R/W - R/W - R/W - 4 3 2 1 0 reserved XFERSIZE R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:30 DSTINC R/W - R/W - R/W - R/W - R/W - 16 ARBSIZE NXTUSEBURST 31 R/W - R/W - XFERMODE R/W - R/W - R/W - Description Destination Address Increment Sets the bits to control the destination address increment. The address increment value must be equal or greater than the value of the destination size (DSTSIZE). Value Description 0x0 Byte Increment by 8-bit locations. 0x1 Half-word Increment by 16-bit locations. 0x2 Word Increment by 32-bit locations. 0x3 No increment Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel. 29:28 DSTSIZE R/W - Destination Data Size Sets the destination item data size. Note: You must set DSTSIZE to be the same as SRCSIZE. Value Description 0x0 Byte 8-bit data size. 0x1 Half-word 16-bit data size. 0x2 Word 32-bit data size. 0x3 Reserved 314 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 27:26 SRCINC R/W - Description Source Address Increment Sets the bits to control the source address increment. The address increment value must be equal or greater than the value of the source size (SRCSIZE). Value Description 0x0 Byte Increment by 8-bit locations. 0x1 Half-word Increment by 16-bit locations. 0x2 Word Increment by 32-bit locations. 0x3 No increment Address remains set to the value of the Source Address End Pointer (DMASRCENDP) for the channel. 25:24 SRCSIZE R/W - Source Data Size Sets the source item data size. Note: You must set DSTSIZE to be the same as SRCSIZE. Value Description 0x0 Byte 8-bit data size. 0x1 Half-word 16-bit data size. 0x2 Word 32-bit data size. 0x3 23:18 reserved R/W - Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 315 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset 17:14 ARBSIZE R/W - Description Arbitration Size Sets the number of DMA transfers that can occur before the controller re-arbitrates. The possible arbitration rate settings represent powers of 2 and are shown below. Value Description 0x0 1 Transfer Arbitrates after each DMA transfer. 0x1 2 Transfers 0x2 4 Transfers 0x3 8 Transfers 0x4 16 Transfers 0x5 32 Transfers 0x6 64 Transfers 0x7 128 Transfers 0x8 256 Transfers 0x9 512 Transfers 0xA-0xF 1024 Transfers This means that no arbitration occurs during the DMA transfer because the maximum transfer size is 1024. 13:4 XFERSIZE R/W - Transfer Size (minus 1) Sets the total number of items to transfer. The value of this field is 1 less than the number to transfer (value 0 means transfer 1 item). The maximum value for this 10-bit field is 1023 which represents a transfer size of 1024 items. The transfer size is the number of items, not the number of bytes. If the data size is 32 bits, then this value is the number of 32-bit words to transfer. The controller updates this field immediately prior to it entering the arbitration process, so it contains the number of outstanding DMA items that are necessary to complete the DMA cycle. 3 NXTUSEBURST R/W - Next Useburst Controls whether the useburst SET[n] bit is automatically set for the last transfer of a peripheral scatter-gather operation. Normally, for the last transfer, if the number of remaining items to transfer is less than the arbitration size, the controller will use single transfers to complete the transaction. If this bit is set, then the controller will only use a burst transfer to complete the last transfer. 316 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 2:0 XFERMODE R/W - Description DMA Transfer Mode Since this register is in system RAM, it has no reset value. Therefore, this field should be initialized to 0 before the channel is enabled. The operating mode of the DMA cycle. Refer to “Transfer Modes” on page 295 for a detailed explanation of transfer modes. Value Description 0x0 Stop Channel is stopped, or configuration data is invalid. 0x1 Basic The controller must receive a new request, prior to it entering the arbitration process, to enable the DMA cycle to complete. 0x2 Auto-Request The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer of XFERSIZE items without any further requests. 0x3 Ping-Pong The controller performs a DMA cycle using one of the channel control structures. After the DMA cycle completes, it performs a DMA cycle using the other channel control structure. After the next DMA cycle completes (and provided that the host processor has updated the original channel control data structure), it performs a DMA cycle using the original channel control data structure. The controller continues to perform DMA cycles until it either reads an invalid data structure or the host processor changes this field to 0x1 or 0x2. See “Ping-Pong” on page 295. 0x4 Memory Scatter-Gather When the controller operates in Memory Scatter-Gather mode, you must only use this value in the primary channel control data structure. See “Memory Scatter-Gather” on page 296. 0x5 Alternate Memory Scatter-Gather When the controller operates in Memory Scatter-Gather mode, you must only use this value in the alternate channel control data structure. 0x6 Peripheral Scatter-Gather When the controller operates in Peripheral Scatter-Gather mode, you must only use this value in the primary channel control data structure. See “Peripheral Scatter-Gather” on page 300. 0x7 Alternate Peripheral Scatter-Gather When the controller operates in Peripheral Scatter-Gather mode, you must only use this value in the alternate channel control data structure. 8.6 μDMA Register Descriptions The register addresses given are relative to the μDMA base address of 0x400F.F000. July 17, 2014 317 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 4: DMA Status (DMASTAT), offset 0x000 The DMA Status (DMASTAT) register returns the status of the controller. You cannot read this register when the controller is in the reset state. DMA Status (DMASTAT) Base 0x400F.F000 Offset 0x000 Type RO, reset 0x001F.0000 31 30 29 28 27 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 26 25 24 23 22 21 20 19 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 10 9 8 7 6 5 4 3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset STATE RO 0 17 16 RO 1 RO 1 RO 1 2 1 0 DMACHANS reserved Type Reset 18 reserved RO 0 MASTEN RO 0 RO 0 Bit/Field Name Type Reset Description 31:21 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20:16 DMACHANS RO 0x1F Available DMA Channels Minus 1 This bit contains a value equal to the number of DMA channels the controller is configured to use, minus one. That is, 32 DMA channels. 15:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 318 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 7:4 STATE RO 0x00 Control State Machine State Current state of the control state machine. State can be one of the following. Value Description 0x0 Idle 0x1 Read Chan Control Data Reading channel controller data. 0x2 Read Source End Ptr Reading source end pointer. 0x3 Read Dest End Ptr Reading destination end pointer. 0x4 Read Source Data Reading source data. 0x5 Write Dest Data Writing destination data. 0x6 Wait for Req Clear Waiting for DMA request to clear. 0x7 Write Chan Control Data Writing channel controller data. 0x8 Stalled 0x9 Done 0xA-0xF Undefined 3:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 MASTEN RO 0x00 Master Enable Returns status of the controller. Value Description 0 Disabled 1 Enabled July 17, 2014 319 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 5: DMA Configuration (DMACFG), offset 0x004 The DMACFG register controls the configuration of the controller. DMA Configuration (DMACFG) Base 0x400F.F000 Offset 0x004 Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - reserved Type Reset reserved Type Reset WO - MASTEN WO - Bit/Field Name Type Reset Description 31:1 reserved WO - Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 MASTEN WO - Controller Master Enable Enables the controller. Value Description 0 Disables 1 Enables 320 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 The DMACTLBASE register must be configured so that the base pointer points to a location in system memory. The amount of system memory that you must assign to the controller depends on the number of DMA channels used and whether you configure it to use the alternate channel control data structure. See “Channel Configuration” on page 293 for details about the Channel Control Table. The base address must be aligned on a 1024-byte boundary. You cannot read this register when the controller is in the reset state. DMA Channel Control Base Pointer (DMACTLBASE) Base 0x400F.F000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR Type Reset R/W 0 R/W 0 R/W 0 15 14 13 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 ADDR Type Reset R/W 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:10 ADDR R/W 0x00 Channel Control Base Address Pointer to the base address of the channel control table. The base address must be 1024-byte aligned. 9:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 321 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C The DMAALTBASE register returns the base address of the alternate channel control data. This register removes the necessity for application software to calculate the base address of the alternate channel control structures. You cannot read this register when the controller is in the reset state. DMA Alternate Channel Control Base Pointer (DMAALTBASE) Base 0x400F.F000 Offset 0x00C Type RO, reset 0x0000.0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 ADDR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 ADDR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 Bit/Field Name Type Reset Description 31:0 ADDR RO 0x200 Alternate Channel Address Pointer Provides the base address of the alternate channel control structures. 322 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 8: DMA Channel Wait on Request Status (DMAWAITSTAT), offset 0x010 This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can pull this Low to hold off the μDMA from performing a single request until the peripheral is ready for a burst request. The use of this feature is dependent on the design of the peripheral and is used to enhance performance of the μDMA with that peripheral. You cannot read this register when the controller is in the reset state. DMA Channel Wait on Request Status (DMAWAITSTAT) Base 0x400F.F000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WAITREQ[n] Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WAITREQ[n] Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:0 WAITREQ[n] RO 0x00 Channel [n] Wait Status Channel wait on request status. For each channel 0 through 31, a 1 in the corresponding bit field indicates that the channel is waiting on a request. July 17, 2014 323 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 Each bit of the DMASWREQ register represents the corresponding DMA channel. When you set a bit, it generates a request for the specified DMA channel. DMA Channel Software Request (DMASWREQ) Base 0x400F.F000 Offset 0x014 Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - SWREQ[n] Type Reset SWREQ[n] Type Reset Bit/Field Name Type Reset 31:0 SWREQ[n] WO - WO - Description Channel [n] Software Request For each channel 0 through 31, write a 1 to the corresponding bit field to generate a software DMA request for that DMA channel. Writing a 0 does not create a DMA request for the corresponding channel. 324 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 Each bit of the DMAUSEBURSTSET register represents the corresponding DMA channel. Writing a 1 disables the peripheral's single request input from generating requests, and therefore only the peripheral's burst request generates requests. Reading the register returns the status of useburst. When there are fewer items remaining to transfer than the arbitration (burst) size, the controller automatically clears the useburst bit to 0. This enables the remaining items to transfer using single requests. This bit should not be set for a peripheral's channel that does not support the burst request model. Refer to “Request Types” on page 293 for more details about request types. Reads DMA Channel Useburst Set (DMAUSEBURSTSET) Base 0x400F.F000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 SET[n] Type Reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 SET[n] Type Reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit/Field Name Type Reset Description 31:0 SET[n] R 0x00 Channel [n] Useburst Status Returns the useburst status of channel [n]. Value Description 0 Single and Burst DMA channel [n] responds to single or burst requests. 1 Burst Only DMA channel [n] responds only to burst requests. Writes DMA Channel Useburst Set (DMAUSEBURSTSET) Base 0x400F.F000 Offset 0x018 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 SET[n] Type Reset SET[n] Type Reset July 17, 2014 325 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset Description 31:0 SET[n] W 0x00 Channel [n] Useburst Set Sets useburst bit on channel [n]. Value Description 0 No Effect Use the DMAUSEBURSTCLR register to clear bit [n] to 0. 1 Burst Only DMA channel [n] responds only to burst requests. 326 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C Each bit of the DMAUSEBURSTCLR register represents the corresponding DMA channel. Writing a 1 enables dma_sreq[n] to generate requests. DMA Channel Useburst Clear (DMAUSEBURSTCLR) Base 0x400F.F000 Offset 0x01C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset CLR[n] Type Reset Bit/Field Name Type Reset 31:0 CLR[n] WO - Description Channel [n] Useburst Clear Clears useburst bit on channel [n]. Value Description 0 No Effect Use the DMAUSEBURSTSET to set bit [n] to 1. 1 Single and Burst DMA channel [n] responds to single and burst requests. July 17, 2014 327 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 Each bit of the DMAREQMASKSET register represents the corresponding DMA channel. Writing a 1 disables DMA requests for the channel. Reading the register returns the request mask status. When a μDMA channel's request is masked, that means the peripheral can no longer request μDMA transfers. The channel can then be used for software-initiated transfers. Reads DMA Channel Request Mask Set (DMAREQMASKSET) Base 0x400F.F000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 SET[n] Type Reset SET[n] Type Reset Bit/Field Name Type Reset Description 31:0 SET[n] R 0x00 Channel [n] Request Mask Status Returns the channel request mask status. Value Description 0 Enabled External requests are not masked for channel [n]. 1 Masked External requests are masked for channel [n]. Writes DMA Channel Request Mask Set (DMAREQMASKSET) Base 0x400F.F000 Offset 0x020 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 7 6 5 4 3 2 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 SET[n] Type Reset W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 SET[n] Type Reset W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 328 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 31:0 SET[n] W 0x00 Channel [n] Request Mask Set Masks (disables) the corresponding channel [n] from generating DMA requests. Value Description 0 No Effect 1 Masked Use the DMAREQMASKCLR register to clear the request mask. Masks (disables) DMA requests on channel [n]. July 17, 2014 329 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 Each bit of the DMAREQMASKCLR register represents the corresponding DMA channel. Writing a 1 clears the request mask for the channel, and enables the channel to receive DMA requests. DMA Channel Request Mask Clear (DMAREQMASKCLR) Base 0x400F.F000 Offset 0x024 Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - Bit/Field Name Type Reset 31:0 CLR[n] WO - WO - Description Channel [n] Request Mask Clear Set the appropriate bit to clear the DMA request mask for channel [n]. This will enable DMA requests for the channel. Value Description 0 No Effect Use the DMAREQMASKSET register to set the request mask. 1 Clear Mask Clears the request mask for the DMA channel. This enables DMA requests for the channel. 330 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 Each bit of the DMAENASET register represents the corresponding DMA channel. Writing a 1 enables the DMA channel. Reading the register returns the enable status of the channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be used for software-initiated transfers. Reads DMA Channel Enable Set (DMAENASET) Base 0x400F.F000 Offset 0x028 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 SET[n] Type Reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 SET[n] Type Reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit/Field Name Type Reset Description 31:0 SET[n] R 0x00 Channel [n] Enable Status Returns the enable status of the channels. Value Description 0 Disabled 1 Enabled Writes DMA Channel Enable Set (DMAENASET) Base 0x400F.F000 Offset 0x028 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 7 6 5 4 3 2 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 SET[n] Type Reset W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 SET[n] Type Reset W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 July 17, 2014 331 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset Description 31:0 SET[n] W 0x00 Channel [n] Enable Set Enables the corresponding channels. Note: The controller disables a channel when it completes the DMA cycle. Value Description 0 No Effect 1 Enable Use the DMAENACLR register to disable a channel. Enables channel [n]. 332 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C Each bit of the DMAENACLR register represents the corresponding DMA channel. Writing a 1 disables the specified DMA channel. DMA Channel Enable Clear (DMAENACLR) Base 0x400F.F000 Offset 0x02C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset CLR[n] Type Reset Bit/Field Name Type Reset 31:0 CLR[n] WO - Description Clear Channel [n] Enable Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel when it completes the DMA cycle. Value Description 0 No Effect 1 Disable Use the DMAENASET register to enable DMA channels. Disables channel [n]. July 17, 2014 333 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 Each bit of the DMAALTSET register represents the corresponding DMA channel. Writing a 1 configures the DMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding DMA channel. Reads DMA Channel Primary Alternate Set (DMAALTSET) Base 0x400F.F000 Offset 0x030 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 SET[n] Type Reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 SET[n] Type Reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit/Field Name Type Reset Description 31:0 SET[n] R 0x00 Channel [n] Alternate Status Returns the channel control data structure status. Value Description 0 Primary DMA channel [n] is using the primary control structure. 1 Alternate DMA channel [n] is using the alternate control structure. Writes DMA Channel Primary Alternate Set (DMAALTSET) Base 0x400F.F000 Offset 0x030 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 SET[n] Type Reset SET[n] Type Reset 334 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 31:0 SET[n] W 0x00 Channel [n] Alternate Set Selects the alternate channel control data structure for the corresponding DMA channel. Note: For Ping-Pong and Scatter-Gather DMA cycle types, the controller automatically sets these bits to select the alternate channel control data structure. Value Description 0 No Effect Use the DMAALTCLR register to set bit [n] to 0. 1 Alternate Selects the alternate control data structure for channel [n]. July 17, 2014 335 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 Each bit of the DMAALTCLR register represents the corresponding DMA channel. Writing a 1 configures the DMA channel to use the primary control data structure. DMA Channel Primary Alternate Clear (DMAALTCLR) Base 0x400F.F000 Offset 0x034 Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - Bit/Field Name Type Reset 31:0 CLR[n] WO - WO - Description Channel [n] Alternate Clear Set the appropriate bit to select the primary control data structure for the corresponding DMA channel. Note: For Ping-Pong and Scatter-Gather DMA cycle types, the controller sets these bits to select the primary channel control data structure. Value Description 0 No Effect Use the DMAALTSET register to select the alternate control data structure. 1 Primary Selects the primary control data structure for channel [n]. 336 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 Each bit of the the DMAPRIOSET register represents the corresponding DMA channel. Writing a 1 configures the DMA channel to have a high priority level. Reading the register returns the status of the channel priority mask. Reads DMA Channel Priority Set (DMAPRIOSET) Base 0x400F.F000 Offset 0x038 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 SET[n] Type Reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 SET[n] Type Reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit/Field Name Type Reset Description 31:0 SET[n] R 0x00 Channel [n] Priority Status Returns the channel priority status. Value Description 0 Default Priority DMA channel [n] is using the default priority level. 1 High Priority DMA channel [n] is using a High Priority level. Writes DMA Channel Priority Set (DMAPRIOSET) Base 0x400F.F000 Offset 0x038 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 SET[n] Type Reset SET[n] Type Reset July 17, 2014 337 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset Description 31:0 SET[n] W 0x00 Channel [n] Priority Set Sets the channel priority to high. Value Description 0 No Effect Use the DMAPRIOCLR register to set channel [n] to the default priority level. 1 High Priority Sets DMA channel [n] to a High Priority level. 338 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C Each bit of the DMAPRIOCLR register represents the corresponding DMA channel. Writing a 1 configures the DMA channel to have the default priority level. DMA Channel Priority Clear (DMAPRIOCLR) Base 0x400F.F000 Offset 0x03C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset CLR[n] Type Reset Bit/Field Name Type Reset 31:0 CLR[n] WO - Description Channel [n] Priority Clear Set the appropriate bit to clear the high priority level for the specified DMA channel. Value Description 0 No Effect Use the DMAPRIOSET register to set channel [n] to the High priority level. 1 Default Priority Sets DMA channel [n] to a Default priority level. July 17, 2014 339 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C The DMAERRCLR register is used to read and clear the DMA bus error status. The error status will be set if the μDMA controller encountered a bus error while performing a DMA transfer. If a bus error occurs on a channel, that channel will be automatically disabled by the μDMA controller. The other channels are unaffected. Reads DMA Bus Error Clear (DMAERRCLR) Base 0x400F.F000 Offset 0x04C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 0 ERRCLR RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ERRCLR R 0 DMA Bus Error Status Value Description 0 Low No bus error is pending. 1 High Bus error is pending. Writes DMA Bus Error Clear (DMAERRCLR) Base 0x400F.F000 Offset 0x04C Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 ERRCLR 340 W 0 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ERRCLR W 0 DMA Bus Error Clear Clears the bus error. Value Description 0 No Effect Bus error status is unchanged. 1 Clear Clears a pending bus error. July 17, 2014 341 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 21: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. DMA Peripheral Identification 0 (DMAPeriphID0) Base 0x400F.F000 Offset 0xFE0 Type RO, reset 0x0000.0030 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x30 DMA Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 342 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 22: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. DMA Peripheral Identification 1 (DMAPeriphID1) Base 0x400F.F000 Offset 0xFE4 Type RO, reset 0x0000.00B2 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0xB2 DMA Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. July 17, 2014 343 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 23: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. DMA Peripheral Identification 2 (DMAPeriphID2) Base 0x400F.F000 Offset 0xFE8 Type RO, reset 0x0000.000B 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x0B DMA Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 344 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 24: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. DMA Peripheral Identification 3 (DMAPeriphID3) Base 0x400F.F000 Offset 0xFEC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x00 DMA Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. July 17, 2014 345 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 25: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. DMA Peripheral Identification 4 (DMAPeriphID4) Base 0x400F.F000 Offset 0xFD0 Type RO, reset 0x0000.0004 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x04 DMA Peripheral ID Register Can be used by software to identify the presence of this peripheral. 346 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 26: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 The DMAPCellIDn registers are hard-coded and the fields within the registers determine the reset values. DMA PrimeCell Identification 0 (DMAPCellID0) Base 0x400F.F000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D DMA PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. July 17, 2014 347 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 27: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 The DMAPCellIDn registers are hard-coded and the fields within the registers determine the reset values. DMA PrimeCell Identification 1 (DMAPCellID1) Base 0x400F.F000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 DMA PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 348 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 28: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 The DMAPCellIDn registers are hard-coded and the fields within the registers determine the reset values. DMA PrimeCell Identification 2 (DMAPCellID2) Base 0x400F.F000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 DMA PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. July 17, 2014 349 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 29: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC The DMAPCellIDn registers are hard-coded and the fields within the registers determine the reset values. DMA PrimeCell Identification 3 (DMAPCellID3) Base 0x400F.F000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 DMA PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 350 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 9 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of five physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E). The GPIO module supports 1-33 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ 1-33 GPIOs, depending on configuration ■ 5-V-tolerant in input configuration ■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with existing code ■ Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for ports on APB ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can initiate an ADC sample sequence ■ Pins configured as digital inputs are Schmitt-triggered. ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 9.1 Signal Description GPIO signals have alternate hardware functions. Table 9-3 on page 353 lists the GPIO pins and their analog and digital alternate functions. The AINx analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to their circuitry (). These signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. The digital alternate hardware functions July 17, 2014 351 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric enoding shown in the table below. Note that each pin must be programmed individually; no type of grouping is implied by the columns in the table. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 9-1. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 1 1 0 GPIOPCTL 0 0x1 PA[5:2] SSI0 1 1 0 0 0x1 PB[3:2] I2C0 1 1 0 0 0x1 PC[3:0] JTAG/SWD 1 1 0 1 0x3 Table 9-2. GPIO Pins and Alternate Functions (64LQFP) IO Pin Number Multiplexed Function PA0 17 U0Rx PA1 18 U0Tx PA2 19 SSI0Clk PA3 20 SSI0Fss PA4 21 SSI0Rx PA5 22 SSI0Tx PA6 25 I2C1SCL PA7 26 I2C1SDA PB0 41 U1Rx PB1 42 U1Tx PB2 47 I2C0SCL PB3 27 I2C0SDA PB4 58 PB5 57 CCP0 PB6 56 CCP1 PB7 55 NMI PC0 52 TCK SWCLK PC1 51 TMS SWDIO PC2 50 TDI PC3 49 TDO PC4 11 CCP2 PC5 14 USB0EPEN PC6 15 USB0PFLT PC7 16 CCP4 PD0 61 CAN0Rx 352 Multiplexed Function SWO July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 9-2. GPIO Pins and Alternate Functions (64LQFP) (continued) IO Pin Number Multiplexed Function PD1 62 CAN0Tx PD2 63 ADC5 PD3 64 ADC4 PE0 6 ADC3 PE1 5 ADC2 PE2 2 ADC1 PE3 1 ADC0 PE4 8 CCP3 Multiplexed Function Table 9-3. GPIO Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type Description PA0 17 I/O TTL GPIO port A bit 0. PA1 18 I/O TTL GPIO port A bit 1. PA2 19 I/O TTL GPIO port A bit 2. PA3 20 I/O TTL GPIO port A bit 3. PA4 21 I/O TTL GPIO port A bit 4. PA5 22 I/O TTL GPIO port A bit 5. PA6 25 I/O TTL GPIO port A bit 6. PA7 26 I/O TTL GPIO port A bit 7. PB0 41 I/O TTL GPIO port B bit 0. PB1 42 I/O TTL GPIO port B bit 1. PB2 47 I/O TTL GPIO port B bit 2. PB3 27 I/O TTL GPIO port B bit 3. PB4 58 I/O TTL GPIO port B bit 4. PB5 57 I/O TTL GPIO port B bit 5. PB6 56 I/O TTL GPIO port B bit 6. PB7 55 I/O TTL GPIO port B bit 7. PC0 52 I/O TTL GPIO port C bit 0. PC1 51 I/O TTL GPIO port C bit 1. PC2 50 I/O TTL GPIO port C bit 2. PC3 49 I/O TTL GPIO port C bit 3. PC4 11 I/O TTL GPIO port C bit 4. PC5 14 I/O TTL GPIO port C bit 5. PC6 15 I/O TTL GPIO port C bit 6. PC7 16 I/O TTL GPIO port C bit 7. PD0 61 I/O TTL GPIO port D bit 0. PD1 62 I/O TTL GPIO port D bit 1. PD2 63 I/O TTL GPIO port D bit 2. PD3 64 I/O TTL GPIO port D bit 3. PE0 6 I/O TTL GPIO port E bit 0. PE1 5 I/O TTL GPIO port E bit 1. July 17, 2014 353 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 9-3. GPIO Signals (64LQFP) (continued) a Pin Name Pin Number Pin Type Buffer Type Description PE2 2 I/O TTL GPIO port E bit 2. PE3 1 I/O TTL GPIO port E bit 3. PE4 8 I/O TTL GPIO port E bit 4. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 9.2 Functional Description Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the four JTAG/SWD pins (PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block(see Figure 9-1 on page 354 and Figure 9-2 on page 355). The LM3S5732 microcontroller contains five ports and thus five of these physical GPIO blocks. Figure 9-1. Digital I/O Pads Commit Control GPIOLOCK GPIOCR Mode Control GPIOAFSEL Alternate Input DEMUX Alternate Output Alternate output Enable GPIO Output GPIO Output Enable Interrupt Control Pad Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN MUX GPIODATA GPIODIR Interrupt MUX GPIO Input Data Control Pad Input Pad Output Digital I/O Pad Package I/O Pin Pad Output Enable Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 354 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 9-2. Analog/Digital I/O Pads Commit Control Mode Control GPIOLOCK GPIOCR GPIOAFSEL Interrupt Pad Output GPIO Output Enable Interrupt Control Pad Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN GPIOAMSEL Pad Output Enable Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 9.2.1 Package I/O Pin Analog/ Digital I/O Pad GPIO Output MUX GPIODATA GPIODIR GPIO Input Pad Input MUX Data Control DEMUX Alternate Input Alternate Output Alternate Output Enable GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Analog Circuitry ADC (for PortE0 – 3 and PortD0 – 3 pins that connect to the ADC input MUX) Isolation Circuit Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. 9.2.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 363) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and the corresponding data register bit will capture and store the value on the GPIO port. When the data direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port. 9.2.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 362) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting July 17, 2014 355 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 9-3 on page 356, where u is data unchanged by the write. Figure 9-3. GPIODATA Write Example ADDR[9:2] 0x098 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 0 0 0 0xEB 1 1 1 0 1 0 1 1 GPIODATA u u 1 u u 0 1 u 7 6 5 4 3 2 1 0 During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-4 on page 356. Figure 9-4. GPIODATA Read Example 9.2.2 ADDR[9:2] 0x0C4 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 1 0 0 GPIODATA 1 0 1 1 1 1 1 0 Returned Value 0 0 1 1 0 0 0 0 7 6 5 4 3 2 1 0 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 364) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 365) ■ GPIO Interrupt Event (GPIOIEV) register (see page 366) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 367). 356 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 368 and page 369). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0) register can disable the PortB interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on PB4, and wait for the ADC interrupt or the ADC interrupt must be disabled in the EN0 register and the PortB interrupt handler must poll the ADC registers until the conversion is completed. See page 110 for more information. Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR) register (see page 370). When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 9.2.3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 371), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. Note: 9.2.4 If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be written to 1 to disable the analog isolation circuit. Commit Control The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 371), GPIO Pull-Up Select (GPIOPUR) register (see page 377), and GPIO Digital Enable (GPIODEN) register (see page 381) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 383) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 384) have been set to 1. 9.2.5 Pad Control The pad control registers allow for GPIO pad configuration by software based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital enable. For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only July 17, 2014 357 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) a maximum of two per side of the physical package with the total number of high-current GPIO outputs not exceeding four for the entire package. 9.2.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 9.3 Initialization and Configuration The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the ® Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides better back-to-back access performance than the APB bus. These apertures are mutually exclusive. The aperture enabled for a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL register (see page 199). To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the four JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-4 on page 358 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 9-5 on page 359 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. Table 9-4. GPIO Pad Configuration Examples a Configuration Digital Input (GPIO) GPIO Register Bit Value AFSEL 0 DIR ODR 0 0 DEN 1 PUR ? PDR ? DR2R DR4R DR8R X X X SLR X Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ? Open Drain Output (GPIO) 0 1 1 1 X X ? ? ? ? Open Drain Input/Output (I2C) 1 X 1 1 X X ? ? ? ? Digital Input (Timer CCP) 1 X 0 1 ? ? X X X X Digital Output (Timer PWM) 1 X 0 1 ? ? ? ? ? ? Digital Input/Output (SSI) 1 X 0 1 ? ? ? ? ? ? Digital Input/Output (UART) 1 X 0 1 ? ? ? ? ? ? a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration 358 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 9-5. GPIO Interrupt Configuration Example Register a Desired Interrupt Event Trigger GPIOIS Pin 2 Bit Value 7 0=edge 6 5 4 3 2 1 0 X X X X X 0 X X X X X X X 0 X X X X X X X 1 X X 0 0 0 0 0 1 0 0 1=level GPIOIBE 0=single edge 1=both edges GPIOIEV 0=Low level, or negative edge 1=High level, or positive edge GPIOIM 0=masked 1=not masked a. X=Ignored (don’t care bit) 9.4 Register Map Table 9-6 on page 360 lists the GPIO registers. Each GPIO port can be accessed through one of two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides better back-to-back access performance than the APB bus. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ GPIO Port A (APB): 0x4000.4000 GPIO Port A (AHB): 0x4005.8000 GPIO Port B (APB): 0x4000.5000 GPIO Port B (AHB): 0x4005.9000 GPIO Port C (APB): 0x4000.6000 GPIO Port C (AHB): 0x4005.A000 GPIO Port D (APB): 0x4000.7000 GPIO Port D (AHB): 0x4005.B000 GPIO Port E (APB): 0x4002.4000 GPIO Port E (AHB): 0x4005.C000 Note that the GPIO module clock must be enabled before the registers can be programmed (see page 229). There must be a delay of 3 system clocks after the GPIO module clock is enabled before any GPIO module registers are accessed. Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect, and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the four JTAG/SWD pins (PC[3:0]). July 17, 2014 359 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) These four pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for Port C is 0x0000.000F. The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these four pins default to non-committable. To ensure that the NMI pin is not accidentally programmed as the non-maskable interrupt pin, it defaults to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 9-6. GPIO Register Map Description See page Offset Name Type Reset 0x000 GPIODATA R/W 0x0000.0000 GPIO Data 362 0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 363 0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 364 0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 365 0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 366 0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 367 0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 368 0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 369 0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 370 0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 371 0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 373 0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 374 0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 375 0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 376 0x510 GPIOPUR R/W - GPIO Pull-Up Select 377 0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 379 0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 380 0x51C GPIODEN R/W - GPIO Digital Enable 381 0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 383 0x524 GPIOCR - - GPIO Commit 384 0x528 GPIOAMSEL R/W 0x0000.0000 GPIO Analog Mode Select 386 0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 387 360 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 9-6. GPIO Register Map (continued) Offset Name 0xFD4 Reset GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 388 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 389 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 390 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 391 0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 392 0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 393 0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 394 0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 395 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 396 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 397 0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 398 9.5 Description See page Type Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. July 17, 2014 361 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 363). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DATA RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA R/W 0x00 GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See “Data Register Operation” on page 355 for examples of reads and writes. 362 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DIR RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DIR R/W 0x00 GPIO Data Direction The DIR values are defined as follows: Value Description 0 Pins are inputs. 1 Pins are outputs. July 17, 2014 363 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset IS RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IS R/W 0x00 GPIO Interrupt Sense The IS values are defined as follows: Value Description 0 Edge on corresponding pin is detected (edge-sensitive). 1 Level on corresponding pin is detected (level-sensitive). 364 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 364) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 366). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset IBE RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IBE R/W 0x00 GPIO Interrupt Both Edges The IBE values are defined as follows: Value Description 0 Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 366). 1 Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. July 17, 2014 365 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 364). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset IEV RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IEV R/W 0x00 GPIO Interrupt Event The IEV values are defined as follows: Value Description 0 Falling edge or Low levels on corresponding pins trigger interrupts. 1 Rising edge or High levels on corresponding pins trigger interrupts. 366 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset IME RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IME R/W 0x00 GPIO Interrupt Mask Enable The IME values are defined as follows: Value Description 0 Corresponding pin interrupt is masked. 1 Corresponding pin interrupt is not masked. July 17, 2014 367 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 367). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RIS RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 RIS RO 0x00 GPIO Interrupt Raw Status Reflects the status of interrupt trigger condition detection on pins (raw, prior to masking). The RIS values are defined as follows: Value Description 0 Corresponding pin interrupt requirements not met. 1 Corresponding pin interrupt has met requirements. 368 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0) register can disable the PortB interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on PB4, and wait for the ADC interrupt or the ADC interrupt must be disabled in the EN0 register and the PortB interrupt handler must poll the ADC registers until the conversion is completed. See page 110 for more information. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset MIS RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 MIS RO 0x00 GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. The MIS values are defined as follows: Value Description 0 Corresponding GPIO line interrupt not active. 1 Corresponding GPIO line asserting interrupt. July 17, 2014 369 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 reserved Type Reset reserved Type Reset IC RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 IC W1C 0x00 GPIO Interrupt Clear The IC values are defined as follows: Value Description 0 Corresponding interrupt is unaffected. 1 Corresponding interrupt is cleared. 370 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 371), GPIO Pull-Up Select (GPIOPUR) register (see page 377), and GPIO Digital Enable (GPIODEN) register (see page 381) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 383) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 384) have been set to 1. Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the four JTAG/SWD pins (PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x420 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 AFSEL RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 371 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 7:0 AFSEL R/W - Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 Software control of corresponding GPIO line (GPIO mode). 1 Hardware control of corresponding GPIO line (alternate hardware function). Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the four JTAG/SWD pins (PC[3:0]). These four pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for Port C is 0x0000.000F. 372 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV2 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DRV2 R/W 0xFF Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. July 17, 2014 373 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV4 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DRV4 R/W 0x00 Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. 374 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. The 8-mA setting is also used for high-current operation. Note: There is no configuration difference between 8-mA and high-current operation. The additional current capacity results from a shift in the VOH/VOL levels. See “Recommended DC Operating Conditions” on page 766 for further information. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DRV8 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DRV8 R/W 0x00 Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. July 17, 2014 375 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 381). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no effect until the GPIO is changed to an output. When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set to 1 (see examples in “Initialization and Configuration” on page 358). GPIO Open Drain Select (GPIOODR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset ODE RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 ODE R/W 0x00 Output Pad Open Drain Enable The ODE values are defined as follows: Value Description 0 Open drain configuration is disabled. 1 Open drain configuration is enabled. 376 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 379). Write access to this register is protected with the GPIOCR register. Bits in GPIOCR that are set to 0 will prevent writes to the equivalent bit in this register. Note: The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 371), GPIO Pull-Up Select (GPIOPUR) register (see page 377), and GPIO Digital Enable (GPIODEN) register (see page 381) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 383) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 384) have been set to 1. GPIO Pull-Up Select (GPIOPUR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x510 Type R/W, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - reserved Type Reset reserved Type Reset PUE RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 377 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 7:0 PUE R/W - Description Pad Weak Pull-Up Enable Value Description 0 The corresponding pin's weak pull-up resistor is disabled. 1 The corresponding pin's weak pull-up resistor is enabled. A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the four JTAG/SWD pins (PC[3:0]). These four pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for Port C is 0x0000.000F. 378 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 377). GPIO Pull-Down Select (GPIOPDR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset PDE RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PDE R/W 0x00 Pad Weak Pull-Down Enable Value Description 0 The corresponding pin's weak pull-down resistor is disabled. 1 The corresponding pin's weak pull-down resistor is enabled. A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. July 17, 2014 379 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 375). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset SRL RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 SRL R/W 0x00 Slew Rate Limit Enable (8-mA drive only) The SRL values are defined as follows: Value Description 0 Slew rate control disabled. 1 Slew rate control enabled. 380 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the corresponding GPIODEN bit must be set. Note: The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 371), GPIO Pull-Up Select (GPIOPUR) register (see page 377), and GPIO Digital Enable (GPIODEN) register (see page 381) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 383) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 384) have been set to 1. GPIO Digital Enable (GPIODEN) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x51C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DEN RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 381 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 7:0 DEN R/W - Description Digital Enable The DEN values are defined as follows: Value Description 0 Digital functions disabled. 1 Digital functions enabled. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the four JTAG/SWD pins (PC[3:0]). These four pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for Port C is 0x0000.000F. 382 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 384). Writing 0x0x4C4F.434B to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000. GPIO Lock (GPIOLOCK) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 LOCK Type Reset LOCK Type Reset Bit/Field Name Type 31:0 LOCK R/W Reset Description 0x0000.0001 GPIO Lock A write of the value 0x4C4F.434B unlocks the GPIO Commit (GPIOCR) register for write access. A write of any other value or a write to the GPIOCR register reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked July 17, 2014 383 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL, GPIOPUR, and GPIODEN registers are committed when a write to these registers is performed. If a bit in the GPIOCR register is zero, the data being written to the corresponding bit in the GPIOAFSEL, GPIOPUR, or GPIODEN registers cannot be committed and retains its previous value. If a bit in the GPIOCR register is set, the data being written to the corresponding bit of the GPIOAFSEL, GPIOPUR, or GPIODEN registers is committed to the register and reflects the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the registers that control connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the NMI and JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the corresponding registers. Because this protection is currently only implemented on the NMI and JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL, GPIOPUR, or GPIODEN register bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x524 Type -, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 - - - - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CR RO 0 RO 0 RO 0 RO 0 - - - - Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 384 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 7:0 CR - - Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL, GPIOPUR, or GPIODEN registers to be written. Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these four pins default to non-committable. To ensure that the NMI pin is not accidentally programmed as the non-maskable interrupt pin, it defaults to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. July 17, 2014 385 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 Important: This register is only valid for ports D and E. If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be written to 1 to disable the analog isolation circuit. The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because the GPIOs may be driven by a 5V source and affect analog operation, analog circuitry requires isolation from the pins when not used in their analog function. Each bit of this register controls the isolation circuitry for circuits that share the same pin as the GPIO bit lane. GPIO Analog Mode Select (GPIOAMSEL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0x528 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 GPIOAMSEL RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 GPIOAMSEL R/W 0x00 GPIO Analog Mode Select Value Description 0 Analog function of the pin is disabled, the isolation is enabled, and the pin is capable of digital functions as specified by the other GPIO configuration registers. 1 Analog function of the pin is enabled, the isolation is disabled, and the pin is capable of analog functions. Note: This register and bits are required only for GPIO bit lanes that share analog function through a unified I/O pad. The reset state of this register is 0 for all bit lanes. 386 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 22: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0] July 17, 2014 387 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 23: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8] 388 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 24: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16] July 17, 2014 389 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 25: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24] 390 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 26: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x61 GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. July 17, 2014 391 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 27: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x00 GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 392 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 28: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. July 17, 2014 393 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 29: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 394 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 30: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. July 17, 2014 395 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 31: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 396 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 32: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. July 17, 2014 397 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 33: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 398 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 10 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. ® The Stellaris General-Purpose Timer Module (GPTM) contains three GPTM blocks (Timer0, Timer1, and Timer 2). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events. The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer resources include the System Timer (SysTick) (see 95). The General-Purpose Timers provide the following features: ■ Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently: – As a single 32-bit timer – As one 32-bit Real-Time Clock (RTC) to event capture – For Pulse Width Modulation (PWM) – To trigger analog-to-digital conversions ■ 32-bit Timer modes – Programmable one-shot timer – Programmable periodic timer – Real-Time Clock when using an external 32.768-KHz clock as the input – User-enabled stalling when the controller asserts CPU Halt flag during debug – ADC event trigger ■ 16-bit Timer modes – General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) – Programmable one-shot timer – Programmable periodic timer – User-enabled stalling when the controller asserts CPU Halt flag during debug – ADC event trigger ■ 16-bit Input Capture modes – Input edge count capture July 17, 2014 399 Texas Instruments-Production Data General-Purpose Timers – Input edge time capture ■ 16-bit PWM mode – Simple PWM mode with software-programmable output inversion of the PWM signal 10.1 Block Diagram Note: In Figure 10-1 on page 400, the specific CCP pins available depend on the Stellaris device. See Table 10-1 on page 400 for the available CCPs. Figure 10-1. GPTM Module Block Diagram 0x0000 (Down Counter Modes) TimerA Control TA Comparator GPTMTAPR Clock / Edge Detect GPTMTAMATCHR Interrupt / Config TimerA Interrupt GPTMCFG GPTMTAILR GPTMAR En GPTMTAMR GPTMCTL GPTMIMR TimerB Interrupt 32 KHz or Even CCP Pin RTC Divider GPTMRIS GPTMMIS TimerB Control GPTMICR GPTMTBR En Clock / Edge Detect GPTMTBPR GPTMTBMATCHR GPTMTBILR Odd CCP Pin TB Comparator GPTMTBMR 0x0000 (Down Counter Modes) System Clock Table 10-1. Available CCP Pins Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin Timer 0 TimerA CCP0 - TimerB - CCP1 TimerA CCP2 - TimerB - CCP3 TimerA CCP4 - TimerB - - Timer 1 Timer 2 10.2 Signal Description Table 10-2 on page 401 lists the external signals of the GP Timer module and describes the function of each. The GP Timer signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the possible GPIO 400 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller pin placements for these GP Timer signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 371) should be set to choose the GP Timer function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 351. Table 10-2. General-Purpose Timers Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type Description CCP0 57 I/O TTL Capture/Compare/PWM 0. CCP1 56 I/O TTL Capture/Compare/PWM 1. CCP2 11 I/O TTL Capture/Compare/PWM 2. CCP3 8 I/O TTL Capture/Compare/PWM 3. CCP4 16 I/O TTL Capture/Compare/PWM 4. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 10.3 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 411), the GPTM TimerA Mode (GPTMTAMR) register (see page 412), and the GPTM TimerB Mode (GPTMTBMR) register (see page 414). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. 10.3.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register (see page 425) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 426). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 429) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 430). 10.3.2 32-Bit Timer Operating Modes This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 425 ■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 426 ■ GPTM TimerA (GPTMTAR) register [15:0], see page 431 ■ GPTM TimerB (GPTMTBR) register [15:0], see page 432 July 17, 2014 401 Texas Instruments-Production Data General-Purpose Timers In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 10.3.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 412), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 416), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 421), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 423). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register (see page 419), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 422). The ADC trigger is enabled by setting the TAOTE bit in GPTMCTL. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. 10.3.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 427) by the controller. The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter. When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 402 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 10.3.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 411). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both. 10.3.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTMIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The ADC trigger is enabled by setting the TnOTE bit in the GPTMCTL register. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period). Table 10-3. 16-Bit Timer With Prescaler Configurations a Prescale #Clock (T c) Max Time Units 00000000 1 1.3107 mS 00000001 2 2.6214 mS 00000010 3 3.9322 mS ------------ -- -- -- 11111101 254 332.9229 mS 11111110 255 334.2336 mS 11111111 256 335.5443 mS a. Tc is the clock period. 10.3.3.2 16-Bit Input Edge Count Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Count mode. July 17, 2014 403 Texas Instruments-Production Data General-Purpose Timers In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 10-2 on page 404 shows how input edge count mode works. In this case, the timer start value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMTnMATCHR register. Figure 10-2. 16-Bit Input Edge Count Mode Example Timer stops, flags asserted Count Timer reload on next cycle Ignored Ignored 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal 10.3.3.3 16-Bit Input Edge Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Time mode. 404 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). The timer is capable of capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMTnILR register. Figure 10-3 on page 405 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). Figure 10-3. 16-Bit Input Edge Time Mode Example Count 0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z Z X Y Time Input Signal 10.3.3.4 16-Bit PWM Mode Note: The prescaler is not available in 16-Bit PWM mode. The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from July 17, 2014 405 Texas Instruments-Production Data General-Purpose Timers GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMTnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 10-4 on page 406 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMTnIRL=0xC350 and the match value is GPTMTnMATCHR=0x411A. Figure 10-4. 16-Bit PWM Mode Example Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 10.4 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, and TIMER2 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 10.4.1 32-Bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 406 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 407. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 10.4.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register. 10.4.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). July 17, 2014 407 Texas Instruments-Production Data General-Purpose Timers 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 8 on page 408. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 10.4.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 408 through step 9 on page 408. 10.4.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 408 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 10.4.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 10.5 Register Map Table 10-4 on page 410 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s address, relative to that timer’s base address: ■ Timer0: 0x4003.0000 ■ Timer1: 0x4003.1000 ■ Timer2: 0x4003.2000 Note that the Timer module clock must be enabled before the registers can be programmed (see page 223). There must be a delay of 3 system clocks after the Timer module clock is enabled before any Timer module registers are accessed. July 17, 2014 409 Texas Instruments-Production Data General-Purpose Timers Table 10-4. Timers Register Map Name Type Reset 0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 411 0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 412 0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 414 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 416 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 419 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 421 0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 422 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 423 0x028 GPTMTAILR R/W 0xFFFF.FFFF GPTM TimerA Interval Load 425 0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 426 0x030 GPTMTAMATCHR R/W 0xFFFF.FFFF GPTM TimerA Match 427 0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 428 0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 429 0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 430 0x048 GPTMTAR RO 0xFFFF.FFFF GPTM TimerA 431 0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 432 10.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. 410 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 GPTMCFG R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 GPTMCFG R/W 0x0 GPTM Configuration The GPTMCFG values are defined as follows: Value Description 0x0 32-bit timer configuration. 0x1 32-bit real-time clock (RTC) counter configuration. 0x2 Reserved 0x3 Reserved 0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. July 17, 2014 411 Texas Instruments-Production Data General-Purpose Timers Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TAAMS TACMR RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TAMR R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TAAMS R/W 0 GPTM TimerA Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TACMR R/W 0 To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2. GPTM TimerA Capture Mode The TACMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode 412 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 1:0 TAMR R/W 0x0 Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. July 17, 2014 413 Texas Instruments-Production Data General-Purpose Timers Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TBAMS TBCMR RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TBMR R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TBAMS R/W 0 GPTM TimerB Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TBCMR R/W 0 To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2. GPTM TimerB Capture Mode The TBCMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode 414 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 1:0 TBMR R/W 0x0 Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register’s contents are ignored and GPTMTAMR is used. July 17, 2014 415 Texas Instruments-Production Data General-Purpose Timers Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 TBOTE reserved TBSTALL TBEN R/W 0 RO 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TAOTE RTCEN TASTALL TAEN R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved TBPWML Type Reset RO 0 R/W 0 TBEVENT R/W 0 R/W 0 reserved TAPWML RO 0 R/W 0 TAEVENT R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:15 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 TBPWML R/W 0 GPTM TimerB PWM Output Level The TBPWML values are defined as follows: Value Description 13 TBOTE R/W 0 0 Output is unaffected. 1 Output is inverted. GPTM TimerB Output Trigger Enable The TBOTE values are defined as follows: Value Description 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see page 472). 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 416 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 11:10 TBEVENT R/W 0x0 Description GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges 9 TBSTALL R/W 0 GPTM Timer B Stall Enable The TBSTALL values are defined as follows: Value Description 0 Timer B continues counting while the processor is halted by the debugger. 1 Timer B freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TBSTALL bit is ignored. 8 TBEN R/W 0 GPTM TimerB Enable The TBEN values are defined as follows: Value Description 0 TimerB is disabled. 1 TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 TAPWML R/W 0 GPTM TimerA PWM Output Level The TAPWML values are defined as follows: Value Description 5 TAOTE R/W 0 0 Output is unaffected. 1 Output is inverted. GPTM TimerA Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 The output TimerA ADC trigger is disabled. 1 The output TimerA ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see page 472). July 17, 2014 417 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 4 RTCEN R/W 0 Description GPTM RTC Enable The RTCEN values are defined as follows: Value Description 3:2 TAEVENT R/W 0x0 0 RTC counting is disabled. 1 RTC counting is enabled. GPTM TimerA Event Mode The TAEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges 1 TASTALL R/W 0 GPTM Timer A Stall Enable The TASTALL values are defined as follows: Value Description 0 Timer A continues counting while the processor is halted by the debugger. 1 Timer A freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TASTALL bit is ignored. 0 TAEN R/W 0 GPTM TimerA Enable The TAEN values are defined as follows: Value Description 0 TimerA is disabled. 1 TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 418 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 CBEIM CBMIM TBTOIM RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RTCIM CAEIM CAMIM TATOIM RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBEIM R/W 0 GPTM CaptureB Event Interrupt Mask The CBEIM values are defined as follows: Value Description 9 CBMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureB Match Interrupt Mask The CBMIM values are defined as follows: Value Description 8 TBTOIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM TimerB Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 7:4 reserved RO 0 0 Interrupt is disabled. 1 Interrupt is enabled. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 419 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 3 RTCIM R/W 0 Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 2 CAEIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 1 CAMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureA Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 TATOIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM TimerA Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 420 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RTCRIS CAERIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 CBERIS RO 0 CBMRIS TBTORIS RO 0 RO 0 reserved CAMRIS TATORIS RO 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBERIS RO 0 GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking. 9 CBMRIS RO 0 GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking. 8 TBTORIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 7:4 reserved RO 0x0 3 RTCRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 2 CAERIS RO 0 GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking. 1 CAMRIS RO 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 0 TATORIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. July 17, 2014 421 Texas Instruments-Production Data General-Purpose Timers Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 CBEMIS CBMMIS TBTOMIS RO 0 RO 0 RO 0 reserved RTCMIS RO 0 CAEMIS CAMMIS TATOMIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBEMIS RO 0 GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking. 9 CBMMIS RO 0 GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking. 8 TBTOMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 7:4 reserved RO 0x0 3 RTCMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking. 2 CAEMIS RO 0 GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking. 1 CAMMIS RO 0 GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking. 0 TATOMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. 422 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 reserved Type Reset reserved Type Reset RO 0 RO 0 RO 0 CBECINT CBMCINT RO 0 RO 0 W1C 0 W1C 0 reserved TBTOCINT W1C 0 RO 0 RO 0 RO 0 RTCCINT CAECINT CAMCINT RO 0 W1C 0 W1C 0 W1C 0 0 TATOCINT W1C 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 CBECINT W1C 0 GPTM CaptureB Event Interrupt Clear The CBECINT values are defined as follows: Value Description 9 CBMCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureB Match Interrupt Clear The CBMCINT values are defined as follows: Value Description 8 TBTOCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM TimerB Time-Out Interrupt Clear The TBTOCINT values are defined as follows: Value Description 7:4 reserved RO 0x0 0 The interrupt is unaffected. 1 The interrupt is cleared. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 423 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 3 RTCCINT W1C 0 Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 2 CAECINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 1 CAMCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureA Match Interrupt Clear The CAMCINT values are defined as follows: Value Description 0 TATOCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM TimerA Time-Out Interrupt Clear The TATOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 424 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x028 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAILRH Type Reset TAILRL Type Reset Bit/Field Name Type Reset 31:16 TAILRH R/W 0xFFFF Description GPTM TimerA Interval Load Register High When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. 15:0 TAILRL R/W 0xFFFF GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. July 17, 2014 425 Texas Instruments-Production Data General-Purpose Timers Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset TBILRL Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TBILRL R/W 0xFFFF GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 426 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x030 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAMRH Type Reset TAMRL Type Reset Bit/Field Name Type Reset 31:16 TAMRH R/W 0xFFFF Description GPTM TimerA Match Register High When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. 15:0 TAMRL R/W 0xFFFF GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. July 17, 2014 427 Texas Instruments-Production Data General-Purpose Timers Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset TBMRL Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TBMRL R/W 0xFFFF GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. 428 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TAPSR RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TAPSR R/W 0x00 GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 10-3 on page 403 for more details and an example. July 17, 2014 429 Texas Instruments-Production Data General-Purpose Timers Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset TBPSR RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 TBPSR R/W 0x00 GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 10-3 on page 403 for more details and an example. 430 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 15: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the number of edges that have occurred. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x048 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 TARH Type Reset TARL Type Reset Bit/Field Name Type Reset 31:16 TARH RO 0xFFFF Description GPTM TimerA Register High If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. 15:0 TARL RO 0xFFFF GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge-Count mode, when it returns the number of edges that have occurred. July 17, 2014 431 Texas Instruments-Production Data General-Purpose Timers Register 16: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the number of edges that have occurred. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 reserved Type Reset TBRL Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TBRL RO 0xFFFF GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge-Count mode, when it returns the number of edges that have occurred. 432 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 11 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. ® The Stellaris Watchdog Timer module has the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the controller asserts the CPU Halt flag during debug The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. July 17, 2014 433 Texas Instruments-Production Data Watchdog Timer 11.1 Block Diagram Figure 11-1. WDT Module Block Diagram WDTLOAD Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt WDTRIS 32-Bit Down Counter WDTMIS 0x00000000 WDTLOCK System Clock WDTTEST Comparator WDTVALUE Identification Registers 11.2 WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. 434 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 11.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 11.4 Register Map Table 11-1 on page 435 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000. Table 11-1. Watchdog Timer Register Map Description See page Offset Name Type Reset 0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 437 0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 438 0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 439 0x00C WDTICR WO - Watchdog Interrupt Clear 440 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 441 0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 442 0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 443 0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 444 0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 445 0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 446 0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 447 0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 448 0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 449 0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 450 0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 451 July 17, 2014 435 Texas Instruments-Production Data Watchdog Timer Table 11-1. Watchdog Timer Register Map (continued) Offset Name 0xFEC Reset WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 452 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 453 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 454 0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 455 0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 456 11.5 Description See page Type Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 436 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 WDTLoad Type Reset WDTLoad Type Reset Bit/Field Name Type 31:0 WDTLoad R/W Reset R/W 1 Description 0xFFFF.FFFF Watchdog Load Value July 17, 2014 437 Texas Instruments-Production Data Watchdog Timer Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 WDTValue Type Reset WDTValue Type Reset Bit/Field Name Type 31:0 WDTValue RO Reset RO 1 Description 0xFFFF.FFFF Watchdog Value Current value of the 32-bit down counter. 438 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 1 0 RESEN INTEN R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 RESEN R/W 0 Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 INTEN R/W 0 0 Disabled. 1 Enable the Watchdog module reset output. Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description 0 Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 1 Interrupt event enabled. Once enabled, all writes are ignored. July 17, 2014 439 Texas Instruments-Production Data Watchdog Timer Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.0000 Offset 0x00C Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WDTIntClr Type Reset WDTIntClr Type Reset Bit/Field Name Type Reset 31:0 WDTIntClr WO - WO - Description Watchdog Interrupt Clear 440 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 WDTRIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 WDTRIS RO 0 Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. July 17, 2014 441 Texas Instruments-Production Data Watchdog Timer Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 WDTMIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 WDTMIS RO 0 Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. 442 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STALL R/W 0 reserved Bit/Field Name Type Reset Description 31:9 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 STALL R/W 0 Watchdog Stall Enable When set to 1, if the Stellaris microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. 7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 443 Texas Instruments-Production Data Watchdog Timer Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) Base 0x4000.0000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 WDTLock Type Reset WDTLock Type Reset Bit/Field Name Type Reset 31:0 WDTLock R/W 0x0000 R/W 0 Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked 444 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0] July 17, 2014 445 Texas Instruments-Production Data Watchdog Timer Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8] 446 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16] July 17, 2014 447 Texas Instruments-Production Data Watchdog Timer Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24] 448 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0] July 17, 2014 449 Texas Instruments-Production Data Watchdog Timer Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8] 450 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16] July 17, 2014 451 Texas Instruments-Production Data Watchdog Timer Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24] 452 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0] July 17, 2014 453 Texas Instruments-Production Data Watchdog Timer Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8] 454 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16] July 17, 2014 455 Texas Instruments-Production Data Watchdog Timer Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24] 456 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 12 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. ® The Stellaris ADC module features 10-bit conversion resolution and supports six input channels, plus an internal temperature sensor. The ADC module contains four programmable sequencer which allows for the sampling of multiple analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. The Stellaris ADC module provides the following features: ■ Six analog input channels ■ Single-ended and differential-input configurations ■ On-chip internal temperature sensor ■ Sample rate of 500 thousand samples/second ■ Flexible, configurable analog-to-digital conversion ■ Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – GPIO ■ Hardware averaging of up to 64 samples for improved accuracy ■ Converter uses an internal 3-V reference ■ Power and ground for the analog circuitry is separate from the digital power and ground 12.1 Block Diagram Figure 12-1 on page 458 provides details on the internal configuration of the ADC controls and data registers. July 17, 2014 457 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 12-1. ADC Module Block Diagram Trigger Events Comparator GPIO (PB4) Timer PWM Analog Inputs SS3 Comparator GPIO (PB4) Timer PWM Control/Status Sample Sequencer 0 ADCACTSS ADCSSMUX0 ADCOSTAT ADCSSCTL0 ADCUSTAT ADCSSFSTAT0 Analog-to-Digital Converter ADCSSPRI SS2 Sample Sequencer 1 ADCSSMUX1 Comparator GPIO (PB4) Timer PWM ADCSSCTL1 SS1 Hardware Averager ADCSSFSTAT1 ADCSAC Sample Sequencer 2 Comparator GPIO (PB4) Timer PWM SS0 ADCSSMUX2 ADCSSCTL2 FIFO Block ADCSSFSTAT2 ADCSSFIFO0 ADCEMUX ADCPSSI ADCSSFIFO1 Interrupt Control Sample Sequencer 3 ADCIM ADCSSMUX3 SS0 Interrupt SS1 Interrupt SS2 Interrupt SS3 Interrupt 12.2 ADCSSFIFO2 ADCSSFIFO3 ADCRIS ADCSSCTL3 ADCISC ADCSSFSTAT3 Signal Description Table 12-1 on page 458 lists the external signals of the ADC module and describes the function of each. The signals are analog functions for some GPIO signals. The column in the table below titled "Pin Assignment" lists the GPIO pin placement for the ADC signals. The AINx analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 351. Table 12-1. ADC Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type ADC0 1 I Analog Description Analog-to-digital converter input 0. ADC1 2 I Analog Analog-to-digital converter input 1. ADC2 5 I Analog Analog-to-digital converter input 2. ADC3 6 I Analog Analog-to-digital converter input 3. ADC4 64 I Analog Analog-to-digital converter input 4. ADC5 63 I Analog Analog-to-digital converter input 5. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 12.3 Functional Description The Stellaris ADC collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approaches found on many ADC modules. Each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC to collect data from multiple input sources without having to be re-configured or serviced by the 458 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller controller. The programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. 12.3.1 Sample Sequencers The sampling control and data capture is handled by the sample sequencers. All of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the FIFO. Table 12-2 on page 459 shows the maximum number of samples that each sequencer can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit word, with the lower 10 bits containing the conversion result. Table 12-2. Samples and FIFO Depth of Sequencers Sequencer Number of Samples Depth of FIFO SS3 1 1 SS2 4 4 SS1 4 4 SS0 8 8 For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. Sample sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, and should be configured before being enabled. When configuring a sample sequence, multiple uses of the same input pin within the same sequence is allowed. In the ADCSSCTLn register, the IEn bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete execution of the sample sequence after the fifth sample. After a sample sequence completes execution, the result data can be retrieved from the ADC Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers that read a single address to "pop" result data. For software debug purposes, the positions of the FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn) registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored using the ADCOSTAT and ADCUSTAT registers. 12.3.2 Module Control Outside of the sample sequencers, the remainder of the control logic is responsible for tasks such as: ■ Interrupt generation ■ Sequence prioritization ■ Trigger configuration July 17, 2014 459 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is configured automatically by hardware when the system XTAL is selected. The automatic clock divider configuration targets 16.667 MHz operation for all Stellaris devices. 12.3.2.1 Interrupts The register configurations of the sample sequencers dictate which events generate raw interrupts, but do not have control over whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signals are controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of the various interrupt signals, and the ADC Interrupt Status and Clear (ADCISC) register, which shows active interrupts that are enabled by the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the corresponding IN bit in ADCISC. 12.3.2.2 Prioritization When sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample sequencer units with the same priority do not provide consistent results, so software must ensure that all active sample sequencer units have a unique priority value. 12.3.2.3 Sampling Events Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select (ADCEMUX) register. The external peripheral triggering sources vary by Stellaris family member, but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting the SSx bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. Care must be taken when using the "Always" trigger. If a sequence's priority is too high, it is possible to starve other lower priority sequences. 12.3.3 Hardware Sample Averaging Circuit Higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the number of samples in the averaging calculation. For example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. By default the averaging circuit is off and all data from the converter passes through to the sequencer FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC) register (see page 479). There is a single averaging circuit and all input channels receive the same amount of averaging whether they are single-ended or differential. 12.3.4 Analog-to-Digital Converter The converter itself generates a 10-bit output value for selected analog input. Special analog pads are used to minimize the distortion on the input. An internal 3 V reference is used by the converter resulting in sample values ranging from 0x000 at 0 V input to 0x3FF at 3 V input when in single-ended input mode. 460 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 12.3.5 Differential Sampling In addition to traditional single-ended sampling, the ADC module supports differential sampling of two analog input channels. To enable differential sampling, software must set the Dn bit in the ADCSSCTL0n register in a step's configuration nibble. When a sequence step is configured for differential sampling, its corresponding value in the ADCSSMUXn register must be set to one of the four differential pairs, numbered 0-3. Differential pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see Table 12-3 on page 461). The ADC does not support other differential pairings such as analog input 0 with analog input 3. The number of differential pairs supported is dependent on the number of analog inputs (see Table 12-3 on page 461). Table 12-3. Differential Sampling Pairs Differential Pair Analog Inputs 0 0 and 1 1 2 and 3 2 4 and 5 The voltage sampled in differential mode is the difference between the odd and even channels: ∆V (differential voltage) = VIN_EVEN (even channels) – VIN_ODD (odd channels), therefore: ■ If ∆V = 0, then the conversion result = 0x1FF ■ If ∆V > 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF) ■ If ∆V < 0, then the conversion result < 0x1FF (range is 0–0x1FF) The differential pairs assign polarities to the analog inputs: the even-numbered input is always positive, and the odd-numbered input is always negative. In order for a valid conversion result to appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped, meaning it appears as either 3 V or 0 V, respectively, to the ADC. Figure 12-2 on page 462 shows an example of the negative input centered at 1.5 V. In this configuration, the differential range spans from -1.5 V to 1.5 V. Figure 12-3 on page 462 shows an example where the negative input is centered at -0.75 V, meaning inputs on the positive input saturate past a differential voltage of -0.75 V since the input voltage is less than 0 V. Figure 12-4 on page 463 shows an example of the negative input centered at 2.25 V, where inputs on the positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater than 3 V. July 17, 2014 461 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 12-2. Differential Sampling Range, VIN_ODD = 1.5 V ADC Conversion Result 0x3FF 0x1FF 0V -1.5 V 1.5 V 0V 3.0 V VIN_EVEN 1.5 V DV VIN_ODD = 1.5 V - Input Saturation Figure 12-3. Differential Sampling Range, VIN_ODD = 0.75 V ADC Conversion Result 0x3FF 0x1FF 0x0FF -1.5 V 0V -0.75 V +0.75 V +2.25 V +1.5 V VIN_EVEN DV - Input Saturation 462 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 12-4. Differential Sampling Range, VIN_ODD = 2.25 V ADC Conversion Result 0x3FF 0x2FF 0x1FF 0.75 V -1.5 V 2.25 V 3.0 V 0.75 V 1.5 V VIN_EVEN DV - Input Saturation 12.3.6 Internal Temperature Sensor The temperature sensor serves two primary purposes: 1) to notify the system that internal temperature is too high or low for reliable operation, and 2) to provide temperature measurements for calibration of the Hibernate module RTC trim value. The temperature sensor does not have a separate enable, since it also contains the bandgap reference and must always be enabled. The reference is supplied to other analog modules; not just the ADC. The internal temperature sensor provides an analog temperature reading as well as a reference voltage. The voltage at the output terminal SENSO is given by the following equation: SENSO = 2.7 - ((T + 55) / 75) This relation is shown in Figure 12-5 on page 464. July 17, 2014 463 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 12-5. Internal Temperature Sensor Characteristic 12.4 Initialization and Configuration In order for the ADC module to be used, the PLL must be enabled and using a supported crystal frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the ADC module. 12.4.1 Module Initialization Initialization of the ADC module is a simple process with very few steps. The main steps include enabling the clock to the ADC, disabling the analog isolation circuit associated with all inputs that are to be used, and reconfiguring the sample sequencer priorities (if needed). The initialization sequence for the ADC is as follows: 1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC0 register (see page 217). 2. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to the appropriate bits of the GPIOAMSEL register (see page 386) in the associated GPIO block. 3. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample Sequencer 3 as the lowest priority. 12.4.2 Sample Sequencer Configuration Configuration of the sample sequencers is slightly more complex than the module initialization since each sample sequence is completely programmable. The configuration for each sample sequencer should be as follows: 1. Ensure that the sample sequencer is disabled by writing a 0 to the corresponding ASENn bit in the ADCACTSS register. Programming of the sample sequencers is allowed without having them enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. Configure the trigger event for the sample sequencer in the ADCEMUX register. 464 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 3. For each sample in the sample sequence, configure the corresponding input source in the ADCSSMUXn register. 4. For each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. 5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register. 6. Enable the sample sequencer logic by writing a 1 to the corresponding ASENn bit in the ADCACTSS register. 12.5 Register Map Table 12-4 on page 465 lists the ADC registers. The offset listed is a hexadecimal increment to the register’s address, relative to the ADC base address of 0x4003.8000. Note that the ADC module clock must be enabled before the registers can be programmed (see page 217). There must be a delay of 3 system clocks after the ADC module clock is enabled before any ADC module registers are accessed. Table 12-4. ADC Register Map Description See page Offset Name Type Reset 0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 467 0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 468 0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 469 0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 470 0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 471 0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 472 0x018 ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 475 0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 476 0x028 ADCPSSI WO - ADC Processor Sample Sequence Initiate 478 0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 479 0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 480 0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 482 0x048 ADCSSFIFO0 RO - ADC Sample Sequence Result FIFO 0 485 0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 486 0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 487 0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 488 0x068 ADCSSFIFO1 RO - ADC Sample Sequence Result FIFO 1 485 0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 486 0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 487 July 17, 2014 465 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Table 12-4. ADC Register Map (continued) Offset Name Type Reset 0x084 ADCSSCTL2 R/W 0x0000.0000 0x088 ADCSSFIFO2 RO 0x08C ADCSSFSTAT2 0x0A0 Description See page ADC Sample Sequence Control 2 488 - ADC Sample Sequence Result FIFO 2 485 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 486 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 490 0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 491 0x0A8 ADCSSFIFO3 RO - ADC Sample Sequence Result FIFO 3 485 0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 486 12.6 Register Descriptions The remainder of this section lists and describes the ADC registers, in numerical order by address offset. 466 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the sample sequencers. Each sample sequencer can be enabled or disabled independently. ADC Active Sample Sequencer (ADCACTSS) Base 0x4003.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 ASEN3 ASEN2 ASEN1 ASEN0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 ASEN3 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC SS3 Enable Specifies whether Sample Sequencer 3 is enabled. If set, the sample sequence logic for Sequencer 3 is active. Otherwise, the sequencer is inactive. 2 ASEN2 R/W 0 ADC SS2 Enable Specifies whether Sample Sequencer 2 is enabled. If set, the sample sequence logic for Sequencer 2 is active. Otherwise, the sequencer is inactive. 1 ASEN1 R/W 0 ADC SS1 Enable Specifies whether Sample Sequencer 1 is enabled. If set, the sample sequence logic for Sequencer 1 is active. Otherwise, the sequencer is inactive. 0 ASEN0 R/W 0 ADC SS0 Enable Specifies whether Sample Sequencer 0 is enabled. If set, the sample sequence logic for Sequencer 0 is active. Otherwise, the sequencer is inactive. July 17, 2014 467 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each sample sequencer. These bits may be polled by software to look for interrupt conditions without having to generate controller interrupts. ADC Raw Interrupt Status (ADCRIS) Base 0x4003.8000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 INR3 INR2 INR1 INR0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 INR3 RO 0 SS3 Raw Interrupt Status This bit is set by hardware when a sample with its respective ADCSSCTL3 IE bit has completed conversion. This bit is cleared by setting the IN3 bit in the ADCISC register. 2 INR2 RO 0 SS2 Raw Interrupt Status This bit is set by hardware when a sample with its respective ADCSSCTL2 IE bit has completed conversion. This bit is cleared by setting the IN2 bit in the ADCISC register. 1 INR1 RO 0 SS1 Raw Interrupt Status This bit is set by hardware when a sample with its respective ADCSSCTL1 IE bit has completed conversion. This bit is cleared by setting the IN1 bit in the ADCISC register. 0 INR0 RO 0 SS0 Raw Interrupt Status This bit is set by hardware when a sample with its respective ADCSSCTL0 IE bit has completed conversion. This bit is cleared by setting the IN30 bit in the ADCISC register. 468 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the sample sequencer raw interrupt signals are promoted to controller interrupts. Each raw interrupt signal can be masked independently. ADC Interrupt Mask (ADCIM) Base 0x4003.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 MASK3 MASK2 MASK1 MASK0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 MASK3 R/W 0 SS3 Interrupt Mask When set, this bit allows the raw interrupt signal from Sample Sequencer 3 (ADCRIS register INR3 bit) to be promoted to a controller interrupt. When clear, the status of Sample Sequencer 3 does not affect the SS3 interrupt status. 2 MASK2 R/W 0 SS2 Interrupt Mask When set, this bit allows the raw interrupt signal from Sample Sequencer 2 (ADCRIS register INR2 bit) to be promoted to a controller interrupt. When clear, the status of Sample Sequencer 2 does not affect the SS2 interrupt status. 1 MASK1 R/W 0 SS1 Interrupt Mask When set, this bit allows the raw interrupt signal from Sample Sequencer 1 (ADCRIS register INR1 bit) to be promoted to a controller interrupt. When clear, the status of Sample Sequencer 1 does not affect the SS1 interrupt status. 0 MASK0 R/W 0 SS0 Interrupt Mask When set, this bit allows the raw interrupt signal from Sample Sequencer 0 (ADCRIS register INR0 bit) to be promoted to a controller interrupt. When clear, the status of Sample Sequencer 0 does not affect the SS0 interrupt status. July 17, 2014 469 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing sample sequence interrupt conditions and shows the status of controller interrupts generated by the sample sequencers. When read, each bit field is the logical AND of the respective INR and MASK bits. Sample sequence nterrupts are cleared by setting the corresponding bit position. If software is polling the ADCRIS instead of generating interrupts, the sample sequence INR bits are still cleared via the ADCISC register, even if the IN bit is not set. ADC Interrupt Status and Clear (ADCISC) Base 0x4003.8000 Offset 0x00C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN3 IN2 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 IN3 R/W1C 0 SS3 Interrupt Status and Clear This bit is set when both the INR3 bit in the ADCRIS register and the MASK3 bit in the ADCIM register are set, providing a level-based interrupt to the controller. This bit is cleared by writing a 1. Clearing this bit also clears the INR3 bit. 2 IN2 R/W1C 0 SS2 Interrupt Status and Clear This bit is set when both the INR2 bit in the ADCRIS register and the MASK2 bit in the ADCIM register are set, providing a level-based interrupt to the controller. This bit is cleared by writing a 1. Clearing this bit also clears the INR2 bit. 1 IN1 R/W1C 0 SS1 Interrupt Status and Clear This bit is set when both the INR1 bit in the ADCRIS register and the MASK1 bit in the ADCIM register are set, providing a level-based interrupt to the controller. This bit is cleared by writing a 1. Clearing this bit also clears the INR1 bit. 0 IN0 R/W1C 0 SS0 Interrupt Status and Clear This bit is set when both the INR0 bit in the ADCRIS register and the MASK0 bit in the ADCIM register are set, providing a level-based interrupt to the controller. This bit is cleared by writing a 1. Clearing this bit also clears the INR0 bit. 470 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) Base 0x4003.8000 Offset 0x010 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 OV3 OV2 OV1 OV0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 OV3 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Overflow When set, this bit specifies that the FIFO for Sample Sequencer 3 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. This bit is cleared by writing a 1. 2 OV2 R/W1C 0 SS2 FIFO Overflow When set, this bit specifies that the FIFO for Sample Sequencer 2 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. This bit is cleared by writing a 1. 1 OV1 R/W1C 0 SS1 FIFO Overflow When set, this bit specifies that the FIFO for Sample Sequencer 1 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. This bit is cleared by writing a 1. 0 OV0 R/W1C 0 SS0 FIFO Overflow When set, this bit specifies that the FIFO for Sample Sequencer 0 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. This bit is cleared by writing a 1. July 17, 2014 471 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each sample sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) Base 0x4003.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset EM3 Type Reset EM2 EM1 EM0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:12 EM3 R/W 0x0 SS3 Trigger Select This field selects the trigger source for Sample Sequencer 3. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 External (GPIO PB4) 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 416). 0x6 reserved 0x7 reserved 0x8 reserved 0x9-0xE reserved 0xF Always (continuously sample) 472 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 11:8 EM2 R/W 0x0 Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 External (GPIO PB4) 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 416). 0x6 reserved 0x7 reserved 0x8 reserved 0x9-0xE reserved 0xF 7:4 EM1 R/W 0x0 Always (continuously sample) SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 External (GPIO PB4) 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 416). 0x6 reserved 0x7 reserved 0x8 reserved 0x9-0xE reserved 0xF Always (continuously sample) July 17, 2014 473 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 3:0 EM0 R/W 0x0 Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 External (GPIO PB4) 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 416). 0x6 reserved 0x7 reserved 0x8 reserved 0x9-0xE reserved 0xF Always (continuously sample) 474 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding underflow condition is cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) Base 0x4003.8000 Offset 0x018 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 UV3 UV2 UV1 UV0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 UV3 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Underflow When set, this bit specifies that the FIFO for Sample Sequencer 3 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 2 UV2 R/W1C 0 SS2 FIFO Underflow When set, this bit specifies that the FIFO for Sample Sequencer 2 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 1 UV1 R/W1C 0 SS1 FIFO Underflow When set, this bit specifies that the FIFO for Sample Sequencer 1 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 0 UV0 R/W1C 0 SS0 FIFO Underflow When set, this bit specifies that the FIFO for Sample Sequencer 0 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. July 17, 2014 475 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority for the ADC to operate properly. ADC Sample Sequencer Priority (ADCSSPRI) Base 0x4003.8000 Offset 0x020 Type R/W, reset 0x0000.3210 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 1 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 RO 0 RO 0 R/W 0 R/W 1 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 SS3 R/W 1 reserved RO 0 SS2 R/W 1 Bit/Field Name Type Reset 31:14 reserved RO 0x0000.0 13:12 SS3 R/W 0x3 reserved SS1 reserved SS0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 3. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 11:10 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9:8 SS2 R/W 0x2 SS2 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 2. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 SS1 R/W 0x1 SS1 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 1. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 476 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 1:0 SS0 R/W 0x0 SS0 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. July 17, 2014 477 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the sample sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. ADC Processor Sample Sequence Initiate (ADCPSSI) Base 0x4003.8000 Offset 0x028 Type WO, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SS3 SS2 SS1 SS0 RO 0 RO 0 RO 0 RO 0 RO 0 WO - WO - WO - WO - reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 SS3 WO - SS3 Initiate When set, this bit triggers sampling on Sample Sequencer 3 if the sequencer is enabled in the ADCACTSS register. Only a write by software is valid; a read of this register returns no meaningful data. 2 SS2 WO - SS2 Initiate When set, this bit triggers sampling on Sample Sequencer 2 if the sequencer is enabled in the ADCACTSS register. Only a write by software is valid; a read of this register returns no meaningful data. 1 SS1 WO - SS1 Initiate When set, this bit triggers sampling on Sample Sequencer 1 if the sequencer is enabled in the ADCACTSS register. Only a write by software is valid; a read of this register returns no meaningful data. 0 SS0 WO - SS0 Initiate When set, this bit triggers sampling on Sample Sequencer 0 if the sequencer is enabled in the ADCACTSS register. Only a write by software is valid; a read of this register returns no meaningful data. 478 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An AVG = 7 provides unpredictable results. ADC Sample Averaging Control (ADCSAC) Base 0x4003.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 AVG R/W 0x0 AVG R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hardware Averaging Control Specifies the amount of hardware averaging that will be applied to ADC samples. The AVG field can be any value between 0 and 6. Entering a value of 7 creates unpredictable results. Value Description 0x0 No hardware oversampling 0x1 2x hardware oversampling 0x2 4x hardware oversampling 0x3 8x hardware oversampling 0x4 16x hardware oversampling 0x5 32x hardware oversampling 0x6 64x hardware oversampling 0x7 Reserved July 17, 2014 479 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. This register is 32 bits wide and contains information for eight possible samples. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0) Base 0x4003.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 reserved Type Reset RO 0 RO 0 R/W 0 15 14 13 reserved Type Reset RO 0 RO 0 28 MUX7 26 25 reserved RO 0 RO 0 R/W 0 12 11 10 9 reserved R/W 0 RO 0 RO 0 24 23 MUX6 R/W 0 MUX3 R/W 0 27 Bit/Field Name Type Reset 31:30 reserved RO 0 29:28 MUX7 R/W 0x0 21 RO 0 RO 0 R/W 0 8 7 6 5 reserved R/W 0 RO 0 20 19 MUX5 R/W 0 MUX2 R/W 0 22 reserved RO 0 17 RO 0 RO 0 R/W 0 4 3 2 1 reserved R/W 0 RO 0 16 MUX4 R/W 0 MUX1 R/W 0 18 reserved RO 0 R/W 0 0 MUX0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. The value set here indicates the corresponding pin, for example, a value of 1 indicates the input is ADC1. 27:26 reserved RO 0 25:24 MUX6 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7th Sample Input Select The MUX6 field is used during the seventh sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 23:22 reserved RO 0 21:20 MUX5 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6th Sample Input Select The MUX5 field is used during the sixth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 19:18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 480 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 17:16 MUX4 R/W 0x0 Description 5th Sample Input Select The MUX4 field is used during the fifth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 15:14 reserved RO 0 13:12 MUX3 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Input Select The MUX3 field is used during the fourth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 11:10 reserved RO 0 9:8 MUX2 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3rd Sample Input Select The MUX72 field is used during the third sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 7:6 reserved RO 0 5:4 MUX1 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2nd Sample Input Select The MUX1 field is used during the second sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 3:2 reserved RO 0 1:0 MUX0 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select The MUX0 field is used during the first sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. July 17, 2014 481 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with a sample sequencer. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Control 0 (ADCSSCTL0) Base 0x4003.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 Type Reset Type Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31 TS7 R/W 0 Description 8th Sample Temp Sensor Select This bit is used during the eighth sample of the sample sequence and and specifies the input source of the sample. When set, the temperature sensor is read. When clear, the input pin specified by the ADCSSMUX register is read. 30 IE7 R/W 0 8th Sample Interrupt Enable This bit is used during the eighth sample of the sample sequence and specifies whether the raw interrupt signal (INR0 bit) is asserted at the end of the sample's conversion. If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to a controller-level interrupt. When this bit is set, the raw interrupt is asserted. When this bit is clear, the raw interrupt is not asserted. It is legal to have multiple samples within a sequence generate interrupts. 29 END7 R/W 0 8th Sample is End of Sequence The END7 bit indicates that this is the last sample of the sequence. It is possible to end the sequence on any sample position. Samples defined after the sample containing a set END are not requested for conversion even though the fields may be non-zero. It is required that software write the END bit somewhere within the sequence. (Sample Sequencer 3, which only has a single sample in the sequence, is hardwired to have the END0 bit set.) Setting this bit indicates that this sample is the last in the sequence. 28 D7 R/W 0 8th Sample Diff Input Select The D7 bit indicates that the analog input is to be differentially sampled. The corresponding ADCSSMUXx nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". The temperature sensor does not have a differential option. When set, the analog inputs are differentially sampled. 27 TS6 R/W 0 7th Sample Temp Sensor Select Same definition as TS7 but used during the seventh sample. 482 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 26 IE6 R/W 0 Description 7th Sample Interrupt Enable Same definition as IE7 but used during the seventh sample. 25 END6 R/W 0 7th Sample is End of Sequence Same definition as END7 but used during the seventh sample. 24 D6 R/W 0 7th Sample Diff Input Select Same definition as D7 but used during the seventh sample. 23 TS5 R/W 0 6th Sample Temp Sensor Select Same definition as TS7 but used during the sixth sample. 22 IE5 R/W 0 6th Sample Interrupt Enable Same definition as IE7 but used during the sixth sample. 21 END5 R/W 0 6th Sample is End of Sequence Same definition as END7 but used during the sixth sample. 20 D5 R/W 0 6th Sample Diff Input Select Same definition as D7 but used during the sixth sample. 19 TS4 R/W 0 5th Sample Temp Sensor Select Same definition as TS7 but used during the fifth sample. 18 IE4 R/W 0 5th Sample Interrupt Enable Same definition as IE7 but used during the fifth sample. 17 END4 R/W 0 5th Sample is End of Sequence Same definition as END7 but used during the fifth sample. 16 D4 R/W 0 5th Sample Diff Input Select Same definition as D7 but used during the fifth sample. 15 TS3 R/W 0 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 13 END3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 TS2 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 10 IE2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. July 17, 2014 483 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 8 D2 R/W 0 Description 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 7 TS1 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 6 IE1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 TS0 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 484 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 Important: This register is read-sensitive. See the register description for details. This register contains the conversion results for samples collected with the sample sequencer (the ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1, ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT registers. ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0) Base 0x4003.8000 Offset 0x048 Type RO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO - RO - RO - RO - RO - 4 3 2 1 0 RO - RO - RO - RO - RO - reserved Type Reset RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - 15 14 13 12 11 10 9 8 7 6 5 reserved Type Reset RO - RO - RO - RO - DATA RO - RO - RO - RO - RO - RO - RO - Bit/Field Name Type Reset Description 31:10 reserved RO - Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9:0 DATA RO - Conversion Result Data July 17, 2014 485 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC This register provides a window into the sample sequencer, providing full/empty status information as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty FIFO. The ADCSSFSTAT0 register provides status on FIFO0, ADCSSFSTAT1 on FIFO1, ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3. ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0) Base 0x4003.8000 Offset 0x04C Type RO, reset 0x0000.0100 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RO 0 FULL RO 0 RO 0 reserved RO 0 RO 0 EMPTY RO 0 Bit/Field Name Type Reset 31:13 reserved RO 0x0 12 FULL RO 0 RO 1 HPTR TPTR Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Full When set, this bit indicates that the FIFO is currently full. 11:9 reserved RO 0x0 8 EMPTY RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Empty When set, this bit indicates that the FIFO is currently empty. 7:4 HPTR RO 0x0 FIFO Head Pointer This field contains the current "head" pointer index for the FIFO, that is, the next entry to be written. 3:0 TPTR RO 0x0 FIFO Tail Pointer This field contains the current "tail" pointer index for the FIFO, that is, the next entry to be read. 486 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSMUX0 register on page 480 for detailed bit descriptions. The ADCSSMUX1 register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2. ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1) Base 0x4003.8000 Offset 0x060 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset reserved Type Reset RO 0 MUX3 R/W 0 R/W 0 reserved R/W 0 MUX2 RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:15 reserved RO 0x0000 14:12 MUX3 R/W 0x0 11 reserved RO 0 10:8 MUX2 R/W 0x0 7 reserved RO 0 6:4 MUX1 R/W 0x0 3 reserved RO 0 2:0 MUX0 R/W 0x0 reserved R/W 0 RO 0 MUX1 R/W 0 R/W 0 reserved R/W 0 RO 0 MUX0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3rd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2nd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select July 17, 2014 487 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0 register on page 482 for detailed bit descriptions. The ADCSSCTL1 register configures Sample Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2. ADC Sample Sequence Control 1 (ADCSSCTL1) Base 0x4003.8000 Offset 0x064 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 TS3 IE3 END3 D3 TS2 IE2 END2 D2 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TS1 IE1 END1 D1 TS0 IE0 END0 D0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 TS3 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 13 END3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 TS2 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 10 IE2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 8 D2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 7 TS1 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 488 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 6 IE1 R/W 0 Description 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 TS0 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. July 17, 2014 489 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register defines the analog input configuration for a sample executed with Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample. See the ADCSSMUX0 register on page 480 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) Base 0x4003.8000 Offset 0x0A0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 MUX0 R/W 0 MUX0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select 490 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for a sample executed with Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 482 for detailed bit descriptions. ADC Sample Sequence Control 3 (ADCSSCTL3) Base 0x4003.8000 Offset 0x0A4 Type R/W, reset 0x0000.0002 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TS0 IE0 END0 D0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 TS0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 1 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. July 17, 2014 491 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) 13 Universal Asynchronous Receivers/Transmitters (UARTs) ® Each Stellaris Universal Asynchronous Receiver/Transmitter (UART) has the following features: ■ Two fully programmable 16C550-type UARTs with IrDA support ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable baud-rate generator allowing speeds up to 3.125 Mbps ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Standard asynchronous communication bits for start, stop, and parity ■ Line-break generation and detection ■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Dedicated Direct Memory Access (DMA) transmit and receive channels 492 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 13.1 Block Diagram Figure 13-1. UART Module Block Diagram System Clock DMA Request DMA Control UARTDMACTL Interrupt Interrupt Control UARTIFLS UARTIM UARTMIS UARTRIS UARTICR Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 13.2 TxFIFO 16 x 8 . . . Baud Rate Generator Transmitter (with SIR Transmit Encoder) UnTx UARTIBRD UARTDR UARTFBRD RxFIFO 16 x 8 Control/Status UARTRSR/ECR UARTFR UARTLCRH UARTCTL UARTILPR Receiver (with SIR Receive Decoder) UnRx . . . Signal Description Table 13-1 on page 493 lists the external signals of the UART module and describes the function of each. The UART signals are alternate functions for some GPIO signals and default to be GPIO signals at reset, with the exception of the U0Rx and U0Tx pins which default to the UART function. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for these UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 371) should be set to choose the UART function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 351. Table 13-1. UART Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type Description U0Rx 17 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 18 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Rx 41 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. July 17, 2014 493 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Table 13-1. UART Signals (64LQFP) (continued) a Pin Name Pin Number Pin Type Buffer Type U1Tx 42 O TTL Description UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 13.3 Functional Description Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 513). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. 13.3.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 13-2 on page 494 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 13-2. UART Character Frame UnTX LSB 1 5-8 data bits 0 n Parity bit if enabled Start 13.3.2 1-2 stop bits MSB Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 509) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 510). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.) BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) where UARTSysClk is the system clock connected to the UART. 494 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 511), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write ■ UARTFBRD write and UARTLCRH write 13.3.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 506) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in “Transmit/Receive Logic” on page 494). The start bit is valid and recognized if UnRx is still low on the eighth cycle of Baud16, otherwise it is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 13.3.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output and decoded input to the UART. The UART signal pins can be July 17, 2014 495 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This drives the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. See page 508 for more information on IrDA low-power pulse-duration configuration. Figure 13-3 on page 496 shows the UART transmit and receive signals, with and without IrDA modulation. Figure 13-3. IrDA Data Modulation Data bits Start bit UnTx 1 0 0 0 1 Stop bit 0 0 1 1 1 UnTx with IrDA 3 16 Bit period Bit period UnRx with IrDA UnRx 0 1 0 Start 1 0 0 1 1 Data bits 0 1 Stop In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time. If the application does not require the use of the UnRx signal, the GPIO pin that has the UnRx signal as an alternate function must be configured as the UnRx signal and pulled High. 13.3.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 502). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. 496 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 511). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 506) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 515). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 13.3.6 Interrupts The UART can generate interrupts when the following conditions are observed: ■ Overrun Error ■ Break Error ■ Parity Error ■ Framing Error ■ Receive Timeout ■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) ■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 520). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM ) register (see page 517) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 519). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 521). The receive interrupt changes state when one of the following events occurs: ■ If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit. ■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit. The transmit interrupt changes state when one of the following events occurs: July 17, 2014 497 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) ■ If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger level, the TXRIS bit is set. The transmit interrupt is based on a transition through level, therefore the FIFO must be written past the programmed trigger level otherwise no further transmit interrupts will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit. ■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit. 13.3.7 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 513). In loopback mode, data transmitted on UnTx is received on the UnRx input. 13.3.8 DMA Operation The UART provides an interface connected to the μDMA controller. The DMA operation of the UART is enabled through the UART DMA Control (UARTDMACTL) register. When DMA operation is enabled, the UART will assert a DMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever there is any data in the receive FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger level. For the transmit channel, a single transfer request is asserted whenever there is at least one empty location in the transmit FIFO. The burst request is asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The single and burst DMA transfer requests are handled automatically by the μDMA controller depending how the DMA channel is configured. To enable DMA operation for the receive channel, the RXDMAE bit of the DMA Control (UARTDMACTL) register should be set. To enable DMA operation for the transmit channel, the TXDMAE bit of UARTDMACTL should be set. The UART can also be configured to stop using DMA for the receive channel if a receive error occurs. If the DMAERR bit of UARTDMACR is set, then when a receive error occurs, the DMA receive requests will be automatically disabled. This error condition can be cleared by clearing the UART error interrupt. If DMA is enabled, then the μDMA controller will trigger an interrupt when a transfer is complete. The interrupt will occur on the UART interrupt vector. Therefore, if interrupts are used for UART operation and DMA is enabled, the UART interrupt handler must be designed to handle the μDMA completion interrupt. See “Micro Direct Memory Access (μDMA)” on page 290 for more details about programming the μDMA controller. 13.3.9 IrDA SIR block The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR transceiver. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception. 498 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 13.4 Initialization and Configuration To use the UARTs, the peripheral clock must be enabled by setting the UART0 or UART1 bits in the RCGC1 register. This section discusses the steps that are required to use a UART module. For this example, the UART clock is assumed to be 20 MHz and the desired UART configuration is: ■ 115200 baud rate ■ Data length of 8 bits ■ One stop bit ■ No parity ■ FIFOs disabled ■ No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 494, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 509) should be set to 10. The value to be loaded into the UARTFBRD register (see page 510) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Optionally, configure the uDMA channel (see “Micro Direct Memory Access (μDMA)” on page 290) and enable the DMA option(s) in the UARTDMACTL register. 6. Enable the UART by setting the UARTEN bit in the UARTCTL register. 13.5 Register Map Table 13-2 on page 500 lists the UART registers. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address: ■ UART0: 0x4000.C000 ■ UART1: 0x4000.D000 July 17, 2014 499 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Note that the UART module clock must be enabled before the registers can be programmed (see page 223). There must be a delay of 3 system clocks after the UART module clock is enabled before any UART module registers are accessed. Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 513) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 13-2. UART Register Map Offset Name Type Reset Description See page 0x000 UARTDR R/W 0x0000.0000 UART Data 502 0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 504 0x018 UARTFR RO 0x0000.0090 UART Flag 506 0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 508 0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 509 0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 510 0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 511 0x030 UARTCTL R/W 0x0000.0300 UART Control 513 0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 515 0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 517 0x03C UARTRIS RO 0x0000.0000 UART Raw Interrupt Status 519 0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 520 0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 521 0x048 UARTDMACTL R/W 0x0000.0000 UART DMA Control 523 0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 524 0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 525 0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 526 0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 527 0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 528 0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 529 0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 530 0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 531 0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 532 0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 533 0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 534 0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 535 500 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 13.6 Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. July 17, 2014 501 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 1: UART Data (UARTDR), offset 0x000 Important: This register is read-sensitive. See the register description for details. This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 OE BE PE FE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 DATA Bit/Field Name Type Reset Description 31:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 OE RO 0 UART Overrun Error The OE values are defined as follows: Value Description 10 BE RO 0 0 There has been no data loss due to a FIFO overrun. 1 New data was received when the FIFO was full, resulting in data loss. UART Break Error This bit is set to 1 when a break condition is detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 502 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 9 PE RO 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO. 8 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 7:0 DATA R/W 0 Data Transmitted or Received When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART. July 17, 2014 503 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset. Reads UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 OE BE PE FE RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 OE RO 0 UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. 2 BE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 504 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 1 PE RO 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. 0 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. Writes UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset DATA WO 0 Bit/Field Name Type Reset Description 31:8 reserved WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA WO 0 Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. July 17, 2014 505 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TXFE RXFF TXFF RXFE BUSY RO 1 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 TXFE RO 1 UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO is empty. 6 RXFF RO 0 UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full. 5 TXFF RO 0 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full. 4 RXFE RO 1 UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty. 506 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 3 BUSY RO 0 UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 507 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared to 0 when reset. The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.4 μs are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset ILPDVSR RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 ILPDVSR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. IrDA Low-Power Divisor This is an 8-bit low-power divisor value. 508 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 494 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset DIVINT Type Reset Bit/Field Name Type Reset 31:16 reserved RO 0 15:0 DIVINT R/W 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Integer Baud-Rate Divisor July 17, 2014 509 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 494 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 DIVFRAC R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor 510 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 SPS RO 0 RO 0 RO 0 RO 0 R/W 0 5 WLEN R/W 0 R/W 0 4 3 2 1 0 FEN STP2 EPS PEN BRK R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 SPS R/W 0 UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 6:5 WLEN R/W 0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 0x3 8 bits 0x2 7 bits 0x1 6 bits 0x0 5 bits (default) 4 FEN R/W 0 UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 3 STP2 R/W 0 UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. July 17, 2014 511 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 2 EPS R/W 0 Description UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 1 PEN R/W 0 UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 BRK R/W 0 UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. 512 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. Note: The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register. 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH). 4. Reprogram the control register. 5. Enable the UART. UART Control (UARTCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE TXE LBE RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 0 SIRLP SIREN UARTEN RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 RXE R/W 1 UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: 8 TXE R/W 1 To enable reception, the UARTEN bit must also be set. UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: To enable transmission, the UARTEN bit must also be set. July 17, 2014 513 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 7 LBE R/W 0 Description UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 6:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 SIRLP R/W 0 UART SIR Low Power Mode This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. See page 508 for more information. 1 SIREN R/W 0 UART SIR Enable If this bit is set to 1, the IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 0 UARTEN R/W 0 UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 514 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x034 Type R/W, reset 0x0000.0012 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RXIFLSEL R/W 1 TXIFLSEL R/W 1 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:3 RXIFLSEL R/W 0x2 UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Value Description 0x0 RX FIFO ≥ ⅛ full 0x1 RX FIFO ≥ ¼ full 0x2 RX FIFO ≥ ½ full (default) 0x3 RX FIFO ≥ ¾ full 0x4 RX FIFO ≥ ⅞ full 0x5-0x7 Reserved July 17, 2014 515 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 2:0 TXIFLSEL R/W 0x2 Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value Description 0x0 TX FIFO ≤ ⅞ empty 0x1 TX FIFO ≤ ¾ empty 0x2 TX FIFO ≤ ½ empty (default) 0x3 TX FIFO ≤ ¼ empty 0x4 TX FIFO ≤ ⅛ empty 0x5-0x7 Reserved 516 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. UART Interrupt Mask (UARTIM) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 15 14 RO 0 RO 0 RO 0 13 12 11 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 OEIM BEIM PEIM FEIM RTIM TXIM RXIM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIM R/W 0 UART Overrun Error Interrupt Mask On a read, the current mask for the OEIM interrupt is returned. Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller. 9 BEIM R/W 0 UART Break Error Interrupt Mask On a read, the current mask for the BEIM interrupt is returned. Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller. 8 PEIM R/W 0 UART Parity Error Interrupt Mask On a read, the current mask for the PEIM interrupt is returned. Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller. 7 FEIM R/W 0 UART Framing Error Interrupt Mask On a read, the current mask for the FEIM interrupt is returned. Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller. 6 RTIM R/W 0 UART Receive Time-Out Interrupt Mask On a read, the current mask for the RTIM interrupt is returned. Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller. 5 TXIM R/W 0 UART Transmit Interrupt Mask On a read, the current mask for the TXIM interrupt is returned. Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller. 4 RXIM R/W 0 UART Receive Interrupt Mask On a read, the current mask for the RXIM interrupt is returned. Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller. July 17, 2014 517 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description 3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 518 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x03C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 OERIS RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BERIS PERIS FERIS RTRIS TXRIS RXRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OERIS RO 0 UART Overrun Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 9 BERIS RO 0 UART Break Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 8 PERIS RO 0 UART Parity Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 7 FERIS RO 0 UART Framing Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 5 TXRIS RO 0 UART Transmit Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 4 RXRIS RO 0 UART Receive Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 519 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x040 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 OEMIS RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEMIS RO 0 UART Overrun Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 9 BEMIS RO 0 UART Break Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 8 PEMIS RO 0 UART Parity Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 7 FEMIS RO 0 UART Framing Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status Gives the masked interrupt state of this interrupt. 5 TXMIS RO 0 UART Transmit Masked Interrupt Status Gives the masked interrupt state of this interrupt. 4 RXMIS RO 0 UART Receive Masked Interrupt Status Gives the masked interrupt state of this interrupt. 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 520 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x044 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 OEIC RO 0 RO 0 RO 0 RO 0 W1C 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BEIC PEIC FEIC RTIC TXIC RXIC W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 reserved Bit/Field Name Type Reset Description 31:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIC W1C 0 Overrun Error Interrupt Clear The OEIC values are defined as follows: Value Description 9 BEIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Break Error Interrupt Clear The BEIC values are defined as follows: Value Description 8 PEIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Parity Error Interrupt Clear The PEIC values are defined as follows: Value Description 7 FEIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Framing Error Interrupt Clear The FEIC values are defined as follows: Value Description 0 No effect on the interrupt. 1 Clears interrupt. July 17, 2014 521 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 6 RTIC W1C 0 Description Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 5 TXIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Transmit Interrupt Clear The TXIC values are defined as follows: Value Description 4 RXIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Receive Interrupt Clear The RXIC values are defined as follows: Value Description 3:0 reserved RO 0x00 0 No effect on the interrupt. 1 Clears interrupt. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 522 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 14: UART DMA Control (UARTDMACTL), offset 0x048 The UARTDMACTL register is the DMA control register. UART DMA Control (UARTDMACTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x048 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DMAERR TXDMAE RXDMAE R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 DMAERR R/W 0 DMA on Error If this bit is set to 1, DMA receive requests are automatically disabled when a receive error occurs. 1 TXDMAE R/W 0 Transmit DMA Enable If this bit is set to 1, DMA for the transmit FIFO is enabled. 0 RXDMAE R/W 0 Receive DMA Enable If this bit is set to 1, DMA for the receive FIFO is enabled. July 17, 2014 523 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 15: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x0000 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 524 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 16: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x0000 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. July 17, 2014 525 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 17: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x0000 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 526 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 18: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 PID7 RO 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. July 17, 2014 527 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 19: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFE0 Type RO, reset 0x0000.0011 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID0 RO 0x11 UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 528 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 20: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x00 UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. July 17, 2014 529 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 21: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 530 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 22: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. July 17, 2014 531 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 23: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D UART PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 532 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 24: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 UART PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. July 17, 2014 533 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 25: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 UART PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 534 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 26: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 UART PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. July 17, 2014 535 Texas Instruments-Production Data Synchronous Serial Interface (SSI) 14 Synchronous Serial Interface (SSI) ® The Stellaris Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. The Stellaris SSI module has the following features: ■ Master or slave operation ■ Support for Direct Memory Access (DMA) ■ Programmable clock bit rate and prescale ■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing 536 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 14.1 Block Diagram Figure 14-1. SSI Module Block Diagram DMA Request DMA Control SSIDMACTL Interrupt Interrupt Control TxFIFO 8 x 16 SSIIM SSIMIS SSIRIS SSIICR . . . Control/Status SSITx SSICR0 SSICR1 SSISR SSIRx Transmit/ Receive Logic SSIDR RxFIFO 8 x 16 Clock Prescaler System Clock SSIClk SSIFss . . . SSICPSR Identification Registers SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 14.2 SSIPeriphID0 SSIPeriphID1 SSIPeriphID2 SSIPeriphID3 SSIPeriphID4 SSIPeriphID5 SSIPeriphID6 SSIPeriphID7 Signal Description Table 14-1 on page 538 lists the external signals of the SSI module and describes the function of each. The SSI signals are alternate functions for some GPIO signals and default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function Select July 17, 2014 537 Texas Instruments-Production Data Synchronous Serial Interface (SSI) (GPIOAFSEL) register (page 371) should be set to choose the SSI function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 351. Table 14-1. SSI Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type Description SSI0Clk 19 I/O TTL SSI module 0 clock. SSI0Fss 20 I/O TTL SSI module 0 frame signal. SSI0Rx 21 I TTL SSI module 0 receive. SSI0Tx 22 O TTL SSI module 0 transmit. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 14.3 Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. The SSI also supports the DMA interface. The transmit and receive FIFOs can be programmed as destination/source addresses in the DMA module. DMA operation is enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 563). 14.3.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 557). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 550). The frequency of the output clock SSIClk is defined by: SSIClk = FSysClk / (CPSDVSR * (1 + SCR)) Note: For master mode, the system clock must be at least two times faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk. See “Synchronous Serial Interface (SSI)” on page 777 to view SSI timing parameters. 14.3.2 FIFO Operation 14.3.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 554), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to 538 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or a µDMA request when the FIFO is empty. 14.3.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 14.3.3 Interrupts The SSI can generate interrupts when the following conditions are observed: ■ Transmit FIFO service ■ Receive FIFO service ■ Receive FIFO time-out ■ Receive FIFO overrun All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI can only generate a single interrupt request to the controller at any given time. You can mask each of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask (SSIIM) register (see page 558). Setting the appropriate mask bit to 1 enables the interrupt. Provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 560 and page 561, respectively). 14.3.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: ■ Texas Instruments synchronous serial ■ Freescale SPI ■ MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, July 17, 2014 539 Texas Instruments-Production Data Synchronous Serial Interface (SSI) both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and latch data from the other device on the falling edge. Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique, which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 14.3.4.1 Texas Instruments Synchronous Serial Frame Format Figure 14-2 on page 540 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 14-3 on page 541 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. 540 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits 14.3.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is Low, data is captured on the first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition. 14.3.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 14-4 on page 541 and Figure 14-5 on page 542. Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB MSB Q 4 to 16 bits SSITx MSB Note: LSB Q is undefined. July 17, 2014 541 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB LSB MSB MSB 4 to16 bits SSITx LSB MSB LSB MSB In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the master and slave data have been set, the SSIClk master clock pin goes High after one further half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 14.3.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 14-6 on page 543, which covers both single and continuous transfers. 542 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 SSIClk SSIFss SSIRx Q MSB Q LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After a further one half SSIClk period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 14.3.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 14-7 on page 543 and Figure 14-8 on page 544. Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSIRx MSB LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. July 17, 2014 543 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRx MSB LSB LSB MSB 4 to 16 bits In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, which causes slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One half period later, valid master data is transferred to the SSITx line. Now that both the master and slave data have been set, the SSIClk master clock pin becomes Low after one further half SSIClk period. This means that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 14.3.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 14-9 on page 545, which covers both single and continuous transfers. 544 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 SSIClk SSIFss SSIRx Q MSB LSB Q 4 to 16 bits MSB SSITx Note: LSB Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After a further one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 14.3.4.7 MICROWIRE Frame Format Figure 14-10 on page 545 shows the MICROWIRE frame format, again for a single frame. Figure 14-11 on page 546 shows the same format when back-to-back frames are transmitted. Figure 14-10. MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSITx LSB MSB 8-bit control SSIRx 0 MSB LSB 4 to 16 bits output data July 17, 2014 545 Texas Instruments-Production Data Synchronous Serial Interface (SSI) MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) SSIClk SSIFss SSITx LSB MSB LSB 8-bit control SSIRx 0 MSB LSB MSB 4 to 16 bits output data In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. 546 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 14-12 on page 547 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements tSetup=(2*tSSIClk) tHold=tSSIClk SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave 14.3.5 DMA Operation The SSI peripheral provides an interface connected to the μDMA controller. The DMA operation of the SSI is enabled through the SSI DMA Control (SSIDMACTL) register. When DMA operation is enabled, the SSI will assert a DMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever there is any data in the receive FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is 4 or more items. For the transmit channel, a single transfer request is asserted whenever there is at least one empty location in the transmit FIFO. The burst request is asserted whenever the transmit FIFO has 4 or more empty slots. The single and burst DMA transfer requests are handled automatically by the μDMA controller depending how the DMA channel is configured. To enable DMA operation for the receive channel, the RXDMAE bit of the DMA Control (SSIDMACTL) register should be set. To enable DMA operation for the transmit channel, the TXDMAE bit of SSIDMACTL should be set. If DMA is enabled, then the μDMA controller will trigger an interrupt when a transfer is complete. The interrupt will occur on the SSI interrupt vector. Therefore, if interrupts are used for SSI operation and DMA is enabled, the SSI interrupt handler must be designed to handle the μDMA completion interrupt. See “Micro Direct Memory Access (μDMA)” on page 290 for more details about programming the μDMA controller. 14.4 Initialization and Configuration To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x0000.0000. b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004. July 17, 2014 547 Texas Instruments-Production Data Synchronous Serial Interface (SSI) c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. 4. Write the SSICR0 register with the following configuration: ■ Serial clock rate (SCR) ■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) ■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) ■ The data size (DSS) 5. Optionally, configure the μDMA channel (see “Micro Direct Memory Access (μDMA)” on page 290) and enable the DMA option(s) in the SSIDMACTL register. 6. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: ■ Master operation ■ Freescale SPI mode (SPO=1, SPH=1) ■ 1 Mbps bit rate ■ 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x0000.0000. 3. Write the SSICPSR register with a value of 0x0000.0002. 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1. 14.5 Register Map Table 14-2 on page 549 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s address, relative to that SSI module’s base address: ■ SSI0: 0x4000.8000 548 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Note that the SSI module clock must be enabled before the registers can be programmed (see page 223). There must be a delay of 3 system clocks after the SSI module clock is enabled before any SSI module registers are accessed. Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. Table 14-2. SSI Register Map Offset Name Type Reset Description See page 0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 550 0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 552 0x008 SSIDR R/W 0x0000.0000 SSI Data 554 0x00C SSISR RO 0x0000.0003 SSI Status 555 0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 557 0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 558 0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 560 0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 561 0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 562 0x024 SSIDMACTL R/W 0x0000.0000 SSI DMA Control 563 0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 564 0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 565 0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 566 0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 567 0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 568 0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 569 0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 570 0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 571 0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 572 0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 573 0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 574 0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 575 14.6 Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. July 17, 2014 549 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 SPH SPO R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset SCR Type Reset FRF R/W 0 DSS Bit/Field Name Type Reset Description 31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:8 SCR R/W 0x0000 SSI Serial Clock Rate The value SCR is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=FSSIClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 7 SPH R/W 0 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH bit is 0, data is captured on the first clock edge transition. If SPH is 1, data is captured on the second clock edge transition. 6 SPO R/W 0 SSI Serial Clock Polarity This bit is only applicable to the Freescale SPI Format. When the SPO bit is 0, it produces a steady state Low value on the SSIClk pin. If SPO is 1, a steady state High value is placed on the SSIClk pin when data is not being transferred. 5:4 FRF R/W 0x0 SSI Frame Format Select The FRF values are defined as follows: Value Frame Format 0x0 Freescale SPI Frame Format 0x1 Texas Instruments Synchronous Serial Frame Format 0x2 MICROWIRE Frame Format 0x3 Reserved 550 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 3:0 DSS R/W 0x00 SSI Data Size Select The DSS values are defined as follows: Value Data Size 0x0-0x2 Reserved 0x3 4-bit data 0x4 5-bit data 0x5 6-bit data 0x6 7-bit data 0x7 8-bit data 0x8 9-bit data 0x9 10-bit data 0xA 11-bit data 0xB 12-bit data 0xC 13-bit data 0xD 14-bit data 0xE 15-bit data 0xF 16-bit data July 17, 2014 551 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SOD MS SSE LBM RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 SOD R/W 0 SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. The SOD values are defined as follows: Value Description 2 MS R/W 0 0 SSI can drive SSITx output in Slave Output mode. 1 SSI must not drive the SSITx output in Slave mode. SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when SSI is disabled (SSE=0). The MS values are defined as follows: Value Description 0 Device configured as a master. 1 Device configured as a slave. 552 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 1 SSE R/W 0 Description SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. The SSE values are defined as follows: Value Description 0 SSI operation disabled. 1 SSI operation enabled. Note: 0 LBM R/W 0 This bit must be set to 0 before any control registers are reprogrammed. SSI Loopback Mode Setting this bit enables Loopback Test mode. The LBM values are defined as follows: Value Description 0 Normal serial port operation enabled. 1 Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. July 17, 2014 553 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 3: SSI Data (SSIDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer). When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) SSI0 base: 0x4000.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 DATA R/W 0x0000 SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. 554 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 Offset 0x00C Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BSY RFF RNE TNF TFE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 R0 1 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset Description 31:5 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 BSY RO 0 SSI Busy Bit The BSY values are defined as follows: Value Description 3 RFF RO 0 0 SSI is idle. 1 SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. SSI Receive FIFO Full The RFF values are defined as follows: Value Description 2 RNE RO 0 0 Receive FIFO is not full. 1 Receive FIFO is full. SSI Receive FIFO Not Empty The RNE values are defined as follows: Value Description 1 TNF RO 1 0 Receive FIFO is empty. 1 Receive FIFO is not empty. SSI Transmit FIFO Not Full The TNF values are defined as follows: Value Description 0 Transmit FIFO is full. 1 Transmit FIFO is not full. July 17, 2014 555 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 0 TFE R0 1 Description SSI Transmit FIFO Empty The TFE values are defined as follows: Value Description 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. 556 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) SSI0 base: 0x4000.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CPSDVSR RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CPSDVSR R/W 0x00 SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. July 17, 2014 557 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. SSI Interrupt Mask (SSIIM) SSI0 base: 0x4000.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 TXIM RXIM RTIM RORIM R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXIM R/W 0 SSI Transmit FIFO Interrupt Mask The TXIM values are defined as follows: Value Description 2 RXIM R/W 0 0 TX FIFO half-empty or less condition interrupt is masked. 1 TX FIFO half-empty or less condition interrupt is not masked. SSI Receive FIFO Interrupt Mask The RXIM values are defined as follows: Value Description 1 RTIM R/W 0 0 RX FIFO half-full or more condition interrupt is masked. 1 RX FIFO half-full or more condition interrupt is not masked. SSI Receive Time-Out Interrupt Mask The RTIM values are defined as follows: Value Description 0 RX FIFO time-out interrupt is masked. 1 RX FIFO time-out interrupt is not masked. 558 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 0 RORIM R/W 0 Description SSI Receive Overrun Interrupt Mask The RORIM values are defined as follows: Value Description 0 RX FIFO overrun interrupt is masked. 1 RX FIFO overrun interrupt is not masked. July 17, 2014 559 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 Offset 0x018 Type RO, reset 0x0000.0008 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXRIS RXRIS RTRIS RORRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXRIS RO 1 SSI Transmit FIFO Raw Interrupt Status Indicates that the transmit FIFO is half empty or less, when set. 2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORRIS RO 0 SSI Receive Overrun Raw Interrupt Status Indicates that the receive FIFO has overflowed, when set. 560 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXMIS RXMIS RTMIS RORMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXMIS RO 0 SSI Transmit FIFO Masked Interrupt Status Indicates that the transmit FIFO is half empty or less, when set. 2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORMIS RO 0 SSI Receive Overrun Masked Interrupt Status Indicates that the receive FIFO has overflowed, when set. July 17, 2014 561 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 Offset 0x020 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RTIC RORIC RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 W1C 0 W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 RTIC W1C 0 SSI Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 RORIC W1C 0 0 No effect on interrupt. 1 Clears interrupt. SSI Receive Overrun Interrupt Clear The RORIC values are defined as follows: Value Description 0 No effect on interrupt. 1 Clears interrupt. 562 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 The SSIDMACTL register is the DMA control register. SSI DMA Control (SSIDMACTL) SSI0 base: 0x4000.8000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset TXDMAE RXDMAE R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 TXDMAE R/W 0 Transmit DMA Enable If this bit is set to 1, DMA for the transmit FIFO is enabled. 0 RXDMAE R/W 0 Receive DMA Enable If this bit is set to 1, DMA for the receive FIFO is enabled. July 17, 2014 563 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID4 RO 0x00 SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 564 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID5 RO 0x00 SSI Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. July 17, 2014 565 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID6 RO 0x00 SSI Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 566 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID7 RO 0x00 SSI Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. July 17, 2014 567 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 Offset 0xFE0 Type RO, reset 0x0000.0022 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 PID0 RO 0x22 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 568 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID1 RO 0x00 SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 17, 2014 569 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID2 RO 0x18 SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 570 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 PID3 RO 0x01 SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 17, 2014 571 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID0 RO 0x0D SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 572 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID1 RO 0xF0 SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. July 17, 2014 573 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 574 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. July 17, 2014 575 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface 15 Inter-Integrated Circuit (I2C) Interface The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S5732 microcontroller includes two I2C modules, providing the ability to interact (both send and receive) with other I2C devices on the bus. ® The Stellaris I2C interface has the following features: ■ Two I2C modules, each with the following features: ■ Devices on the I2C bus can be designated as either a master or a slave – Supports both sending and receiving data as either a master or a slave – Supports simultaneous master and slave operation ■ Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive ■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) ■ Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been sent or requested by a master ■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 576 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 15.1 Block Diagram Figure 15-1. I2C Block Diagram I2CSCL I2C Control Interrupt I2CMSA I2CSOAR I2CMCS I2CSCSR I2CMDR I2CSDR I2CMTPR I2CSIM I2CMIMR I2CSRIS I2CMRIS I2CSMIS I2CMMIS I2CSICR I2C Master Core I2CSCL I2C I/O Select I2CSDA I2CSCL I2C Slave Core I2CMICR I2CSDA I2CMCR 15.2 I2CSDA Signal Description Table 15-1 on page 577 lists the external signals of the I2C interface and describes the function of each. The I2C interface signals are alternate functions for some GPIO signals and default to be GPIO signals at reset., with the exception of the I2C0SCL and I2CSDA pins which default to the I2C function. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 371) should be set to choose the I2C function. Note that the I2C pins should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 351. Table 15-1. I2C Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type Description I2C0SCL 47 I/O OD I2C module 0 clock. I2C0SDA 27 I/O OD I2C module 0 data. I2C1SCL 25 I/O OD I2C module 1 clock. I2C1SDA 26 I/O OD I2C module 1 data. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 15.3 Functional Description Each I2C module is comprised of both master and slave functions which are implemented as separate peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional open-drain pads. A typical I2C bus configuration is shown in Figure 15-2 on page 578. See “Inter-Integrated Circuit (I2C) Interface” on page 779 for I2C timing diagrams. July 17, 2014 577 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 15-2. I2C Bus Configuration RPUP SCL SDA I2C Bus I2CSCL I2CSDA Stellaris® 15.3.1 RPUP SCL SDA 3rd Party Device with I2C Interface SCL SDA 3rd Party Device with I2C Interface I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines are High. Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in “START and STOP Conditions” on page 578) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. 15.3.1.1 START and STOP Conditions The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition, and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition. See Figure 15-3 on page 578. Figure 15-3. START and STOP Conditions SDA SDA SCL SCL START condition 15.3.1.2 STOP condition Data Format with 7-Bit Address Data transfers follow the format shown in Figure 15-4 on page 579. After the START condition, a slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates a request for data (receive). A data transfer is always terminated by a STOP condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/send formats are then possible within a single transfer. 578 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 15-4. Complete Data Transfer with a 7-Bit Address SDA MSB SCL 1 2 LSB R/S ACK 7 8 9 MSB 1 2 Slave address 7 LSB ACK 8 9 Data The first seven bits of the first byte make up the slave address (see Figure 15-5 on page 579). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master will write (send) data to the selected slave, and a one in this position means that the master will receive data from the slave. Figure 15-5. R/S Bit in First Byte MSB LSB R/S Slave address 15.3.1.3 Data Validity The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is Low (see Figure 15-6 on page 579). Figure 15-6. Data Validity During Bit Transfer on the I2C Bus SDA SCL 15.3.1.4 Data line Change stable of data allowed Acknowledge All bus transactions have a required acknowledge clock cycle that is generated by the master. During the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line. To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data validity requirements described in “Data Validity” on page 579. When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave so that the master can generate a STOP condition and abort the current transfer. If the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Since the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to allow the master to generate the STOP or a repeated START condition. 15.3.1.5 Arbitration A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate a START condition within minimum hold time of the START condition. In these situations, an July 17, 2014 579 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of the competing master devices to place a '1' (High) on SDA while another master transmits a '0' (Low) will switch off its data output stage and retire until the bus is idle again. Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 15.3.2 Available Speed Modes The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP. where: CLK_PRD is the system clock period SCL_LP is the low phase of SCL (fixed at 6) SCL_HP is the high phase of SCL (fixed at 4) TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see page 598). The I2C clock period is calculated as follows: SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD For example: CLK_PRD = 50 ns TIMER_PRD = 2 SCL_LP=6 SCL_HP=4 yields a SCL frequency of: 1/T = 333 Khz Table 15-2 on page 580 gives examples of timer period, system clock, and speed mode (Standard or Fast). Table 15-2. Examples of I2C Master Timer Period versus Speed Mode System Clock Timer Period Standard Mode Timer Period Fast Mode 4 MHz 0x01 100 Kbps - - 6 MHz 0x02 100 Kbps - - 12.5 MHz 0x06 89 Kbps 0x01 312 Kbps 16.7 MHz 0x08 93 Kbps 0x02 278 Kbps 20 MHz 0x09 100 Kbps 0x02 333 Kbps 25 MHz 0x0C 96.2 Kbps 0x03 312 Kbps 33 MHz 0x10 97.1 Kbps 0x04 330 Kbps 40 MHz 0x13 100 Kbps 0x04 400 Kbps 50 MHz 0x18 100 Kbps 0x06 357 Kbps 580 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 15.3.3 Interrupts The I2C can generate interrupts when the following conditions are observed: ■ Master transaction completed ■ Master arbitration lost ■ Master transaction error ■ Slave transaction received ■ Slave transaction requested There is a separate interrupt signal for the I2C master and I2C slave modules. While both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller. 15.3.3.1 I2C Master Interrupts The I2C master module generates an interrupt when a transaction completes (either transmit or receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration, the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in the I2C Master Interrupt Clear (I2CMICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Master Raw Interrupt Status (I2CMRIS) register. 15.3.3.2 I2C Slave Interrupts The slave module can generate an interrupt when data has been received or requested. This interrupt is enabled by writing a 1 to the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register. Software determines whether the module should write (transmit) or read (receive) data from the I2C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a 1 to the DATAIC bit in the I2C Slave Interrupt Clear (I2CSICR) register. In addition, the slave module can generate an interrupt when a start and stop condition is detected. These interrupts are enabled by writing a 1 to the STARTIM and STOPIM bits of the I2C Slave Interrupt Mask (I2CSIMR) register and cleared by writing a 1 to the STOPIC and STARTIC bits of the I2C Slave Interrupt Clear (I2CSICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Slave Raw Interrupt Status (I2CSRIS) register. 15.3.4 Loopback Operation The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL signals from the master and slave modules are tied together. July 17, 2014 581 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface 15.3.5 Command Sequence Flow Charts This section details the steps required to perform the various I2C transfer types in both master and slave mode. 15.3.5.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master. 582 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 15-7. Master Single SEND Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Write data to I2CMDR Read I2CMCS NO BUSBSY bit=0? YES Write ---0-111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle July 17, 2014 583 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 15-8. Master Single RECEIVE Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS NO BUSBSY bit=0? YES Write ---00111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Read data from I2CMDR Idle 584 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 15-9. Master Burst SEND Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS Write data to I2CMDR BUSY bit=0? YES Read I2CMCS ERROR bit=0? NO NO NO BUSBSY bit=0? YES Write data to I2CMDR YES Write ---0-011 to I2CMCS NO ARBLST bit=1? YES Write ---0-001 to I2CMCS NO Index=n? YES Write ---0-101 to I2CMCS Write ---0-100 to I2CMCS Error Service Idle Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle July 17, 2014 585 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 15-10. Master Burst RECEIVE Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS BUSY bit=0? Read I2CMCS NO YES NO BUSBSY bit=0? ERROR bit=0? NO YES Write ---01011 to I2CMCS NO Read data from I2CMDR ARBLST bit=1? YES Write ---01001 to I2CMCS NO Write ---0-100 to I2CMCS Index=m-1? Error Service YES Write ---00101 to I2CMCS Idle Read I2CMCS BUSY bit=0? NO YES NO ERROR bit=0? YES Error Service Read data from I2CMDR Idle 586 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 15-11. Master Burst RECEIVE after Burst SEND Idle Master operates in Master Transmit mode STOP condition is not generated Write Slave Address to I2CMSA Write ---01011 to I2CMCS Master operates in Master Receive mode Repeated START condition is generated with changing data direction Idle July 17, 2014 587 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 15-12. Master Burst SEND after Burst RECEIVE Idle Master operates in Master Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write ---0-011 to I2CMCS Master operates in Master Transmit mode Repeated START condition is generated with changing data direction Idle 15.3.5.2 I2C Slave Command Sequences Figure 15-13 on page 589 presents the command sequence available for the I2C slave. 588 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 15-13. Slave Command Sequence Idle Write OWN Slave Address to I2CSOAR Write -------1 to I2CSCSR Read I2CSCSR NO TREQ bit=1? YES Write data to I2CSDR 15.4 NO RREQ bit=1? FBR is also valid YES Read data from I2CSDR Initialization and Configuration The following example shows how to configure the I2C module to send a single byte as a master. This assumes the system clock is 20 MHz. 1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation. 4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020. 5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by the following equation: July 17, 2014 589 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1; TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1; TPR = 9 Write the I2CMTPR register with the value of 0x0000.0009. 6. Specify the slave address of the master and that the next operation will be a Send by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B. 7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired data. 8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with a value of 0x0000.0007 (STOP, START, RUN). 9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has been cleared. 15.5 Register Map Table 15-3 on page 590 lists the I2C registers. All addresses given are relative to the I2C base addresses for the master and slave: ■ I2C 0: 0x4002.0000 ■ I2C 1: 0x4002.1000 Note that the I2C module clock must be enabled before the registers can be programmed (see page 223). There must be a delay of 3 system clocks after the I2C module clock is enabled before any I2C module registers are accessed. ® The hw_i2c.h file in the StellarisWare Driver Library uses a base address of 0x800 for the I2C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare uses an offset between 0x000 and 0x018 with the slave base address. Table 15-3. Inter-Integrated Circuit (I2C) Interface Register Map Offset Description See page Name Type Reset 0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 592 0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 593 0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 597 0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 598 0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 599 0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 600 0x018 I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 601 0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 602 0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 603 I2C Master 590 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 15-3. Inter-Integrated Circuit (I2C) Interface Register Map (continued) Offset Description See page Name Type Reset 0x800 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 605 0x804 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 606 0x808 I2CSDR R/W 0x0000.0000 I2C Slave Data 608 0x80C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 609 0x810 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 610 0x814 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 611 0x818 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 612 I2C Slave 15.6 Register Descriptions (I2C Master) The remainder of this section lists and describes the I2C master registers, in numerical order by address offset. See also “Register Descriptions (I2C Slave)” on page 604. July 17, 2014 591 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Send (Low). I2C Master Slave Address (I2CMSA) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset SA RO 0 R/S Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:1 SA R/W 0 I2C Slave Address This field specifies bits A6 through A0 of the slave address. 0 R/S R/W 0 Receive/Send The R/S bit specifies if the next operation is a Receive (High) or Send (Low). Value Description 0 Send. 1 Receive. 592 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses four control bits when written, and accesses seven status bits when read. The status register consists of seven bits, which when read determine the state of the I2C bus controller. The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes the generation of the START, or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst. To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after each byte. This bit must be reset when the I2C bus controller requires no further data to be sent from the slave transmitter. Reads I2C Master Control/Status (I2CMCS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BUSBSY IDLE ARBLST ERROR BUSY RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATACK ADRACK RO 0 RO 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 BUSBSY RO 0 Bus Busy This bit specifies the state of the I2C bus. If set, the bus is busy; otherwise, the bus is idle. The bit changes based on the START and STOP conditions. 5 IDLE RO 0 I2C Idle This bit specifies the I2C controller state. If set, the controller is idle; otherwise the controller is not idle. 4 ARBLST RO 0 Arbitration Lost This bit specifies the result of bus arbitration. If set, the controller lost arbitration; otherwise, the controller won arbitration. July 17, 2014 593 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 3 DATACK RO 0 Description Acknowledge Data This bit specifies the result of the last data operation. If set, the transmitted data was not acknowledged; otherwise, the data was acknowledged. 2 ADRACK RO 0 Acknowledge Address This bit specifies the result of the last address operation. If set, the transmitted address was not acknowledged; otherwise, the address was acknowledged. 1 ERROR RO 0 Error This bit specifies the result of the last bus operation. If set, an error occurred on the last operation; otherwise, no error was detected. The error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0 BUSY RO 0 I2C Busy This bit specifies the state of the controller. If set, the controller is busy; otherwise, the controller is idle. When the BUSY bit is set, the other status bits are not valid. Writes I2C Master Control/Status (I2CMCS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 0 ACK STOP START RUN WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved WO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 ACK WO 0 Data Acknowledge Enable When set, causes received data byte to be acknowledged automatically by the master. See field decoding in Table 15-4 on page 595. 2 STOP WO 0 Generate STOP When set, causes the generation of the STOP condition. See field decoding in Table 15-4 on page 595. 1 START WO 0 Generate START When set, causes the generation of a START or repeated START condition. See field decoding in Table 15-4 on page 595. 594 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 0 RUN WO 0 Description I2C Master Enable When set, allows the master to send or receive data. See field decoding in Table 15-4 on page 595. Table 15-4. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) Current I2CMSA[0] State R/S Idle I2CMCS[3:0] ACK STOP START RUN 1 0 X a 0 1 0 X 1 1 1 START condition followed by a SEND and STOP condition (master remains in Idle state). 1 0 0 1 1 START condition followed by RECEIVE operation with negative ACK (master goes to the Master Receive state). 1 0 1 1 1 START condition followed by RECEIVE and STOP condition (master remains in Idle state). 1 1 0 1 1 START condition followed by RECEIVE (master goes to the Master Receive state). 1 1 1 1 1 Illegal. All other combinations not listed are non-operations. Master Transmit Description START condition followed by SEND (master goes to the Master Transmit state). NOP. X X 0 0 1 SEND operation (master remains in Master Transmit state). X X 1 0 0 STOP condition (master goes to Idle state). X X 1 0 1 SEND followed by STOP condition (master goes to Idle state). 0 X 0 1 1 Repeated START condition followed by a SEND (master remains in Master Transmit state). 0 X 1 1 1 Repeated START condition followed by SEND and STOP condition (master goes to Idle state). 1 0 0 1 1 Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive state). 1 0 1 1 1 Repeated START condition followed by a SEND and STOP condition (master goes to Idle state). 1 1 0 1 1 Repeated START condition followed by RECEIVE (master goes to Master Receive state). 1 1 1 1 1 Illegal. All other combinations not listed are non-operations. NOP. July 17, 2014 595 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Table 15-4. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) (continued) Current I2CMSA[0] State R/S I2CMCS[3:0] Description ACK STOP START RUN X 0 0 0 1 RECEIVE operation with negative ACK (master remains in Master Receive state). X X 1 0 0 STOP condition (master goes to Idle state). X 0 1 0 1 RECEIVE followed by STOP condition (master goes to Idle state). X 1 0 0 1 RECEIVE operation (master remains in Master Receive state). X 1 1 0 1 Illegal. 1 0 0 1 1 Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receive state). 1 0 1 1 1 Repeated START condition followed by RECEIVE and STOP condition (master goes to Idle state). 1 1 0 1 1 Repeated START condition followed by RECEIVE (master remains in Master Receive state). 0 X 0 1 1 Repeated START condition followed by SEND (master goes to Master Transmit state). 0 X 1 1 1 Repeated START condition followed by SEND and STOP condition (master goes to Idle state). Master Receive All other combinations not listed are non-operations. b NOP. a. An X in a table cell indicates the bit can be 0 or 1. b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave. 596 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 3: I2C Master Data (I2CMDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Master Transmit state, and the data received when in the Master Receive state. I2C Master Data (I2CMDR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA R/W 0x00 Data Transferred Data transferred during transaction. July 17, 2014 597 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register specifies the period of the SCL clock. Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur. I2C Master Timer Period (I2CMTPR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x00C Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset reserved Type Reset TPR RO 0 R/W 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:0 TPR R/W 0x1 SCL Clock Period This field specifies the period of the SCL clock. SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). 598 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Master Interrupt Mask (I2CMIMR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 IM Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 IM R/W 0 Interrupt Mask This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. July 17, 2014 599 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending. I2C Master Raw Interrupt Status (I2CMRIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RIS RO 0 Raw Interrupt Status This bit specifies the raw interrupt state (prior to masking) of the I2C master block. If set, an interrupt is pending; otherwise, an interrupt is not pending. 600 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled. I2C Master Masked Interrupt Status (I2CMMIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 MIS RO 0 Masked Interrupt Status This bit specifies the raw interrupt state (after masking) of the I2C master block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. July 17, 2014 601 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw interrupt. I2C Master Interrupt Clear (I2CMICR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x01C Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 IC Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 IC WO 0 Interrupt Clear This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise, a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data. 602 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave) and sets the interface for test mode loopback. I2C Master Configuration (I2CMCR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SFE MFE RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 reserved RO 0 RO 0 LPBK RO 0 R/W 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SFE R/W 0 I2C Slave Function Enable This bit specifies whether the interface may operate in Slave mode. If set, Slave mode is enabled; otherwise, Slave mode is disabled. 4 MFE R/W 0 I2C Master Function Enable This bit specifies whether the interface may operate in Master mode. If set, Master mode is enabled; otherwise, Master mode is disabled and the interface clock is disabled. 3:1 reserved RO 0x00 0 LPBK R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Loopback This bit specifies whether the interface is operating normally or in Loopback mode. If set, the device is put in a test mode loopback configuration; otherwise, the device operates normally. July 17, 2014 603 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface 15.7 Register Descriptions (I2C Slave) The remainder of this section lists and describes the I2C slave registers, in numerical order by address offset. See also “Register Descriptions (I2C Master)” on page 591. 604 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus. I2C Slave Own Address (I2CSOAR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x800 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset OAR RO 0 R/W 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:0 OAR R/W 0x00 I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. July 17, 2014 605 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 This register accesses one control bit when written, and three status bits when read. The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates that the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte into the I2C Slave Data (I2CSDR) register to clear the TREQ bit. The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the Stellaris I2C slave operation. Reads I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x804 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 FBR TREQ RREQ RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 FBR RO 0 First Byte Received Indicates that the first byte following the slave’s own address is received. This bit is only valid when the RREQ bit is set, and is automatically cleared when data has been read from the I2CSDR register. Note: 1 TREQ RO 0 This bit is not used for slave transmit operations. Transmit Request This bit specifies the state of the I2C slave with regards to outstanding transmit requests. If set, the I2C unit has been addressed as a slave transmitter and uses clock stretching to delay the master until data has been written to the I2CSDR register. Otherwise, there is no outstanding transmit request. 0 RREQ RO 0 Receive Request This bit specifies the status of the I2C slave with regards to outstanding receive requests. If set, the I2C unit has outstanding receive data from the I2C master and uses clock stretching to delay the master until the data has been read from the I2CSDR register. Otherwise, no receive data is outstanding. 606 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Writes I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x804 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 DA Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DA WO 0 Device Active Value Description 0 Disables the I2C slave operation. 1 Enables the I2C slave operation. Once this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. July 17, 2014 607 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 12: I2C Slave Data (I2CSDR), offset 0x808 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. I2C Slave Data (I2CSDR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x808 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 DATA R/W 0x0 Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. 608 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Slave Interrupt Mask (I2CSIMR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x80C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATAIM R/W 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DATAIM R/W 0 Data Interrupt Mask This bit controls whether the raw interrupt for data received and data requested is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. July 17, 2014 609 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 This register specifies whether an interrupt is pending. I2C Slave Raw Interrupt Status (I2CSRIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x810 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATARIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DATARIS RO 0 Data Raw Interrupt Status This bit specifies the raw interrupt state for data received and data requested (prior to masking) of the I2C slave block. If set, an interrupt is pending; otherwise, an interrupt is not pending. 610 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 This register specifies whether an interrupt was signaled. I2C Slave Masked Interrupt Status (I2CSMIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x814 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATAMIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DATAMIS RO 0 Data Masked Interrupt Status This bit specifies the interrupt state for data received and data requested (after masking) of the I2C slave block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. July 17, 2014 611 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 This register clears the raw interrupt. A read of this register returns no meaningful data. I2C Slave Interrupt Clear (I2CSICR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x818 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 DATAIC WO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DATAIC WO 0 Data Interrupt Clear This bit controls the clearing of the raw interrupt for data received and data requested. When set, it clears the DATARIS interrupt bit; otherwise, it has no effect on the DATARIS bit value. 612 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 16 Controller Area Network (CAN) Module Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire. Originally created for automotive purposes, it is also used in many embedded control applications (such as industrial and medical). Bit rates up to 1Mbps are possible at network lengths less than 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at 500 meters). ® The Stellaris CAN controller supports the following features: ■ CAN protocol version 2.0 part A/B ■ Bit rates up to 1 Mbps ■ 32 message objects with individual identifier masks ■ Maskable interrupt ■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications ■ Programmable Loopback mode for self-test operation ■ Programmable FIFO mode enables storage of multiple message objects ■ Gluelessly attaches to an external CAN interface through the CANnTX and CANnRX signals July 17, 2014 613 Texas Instruments-Production Data Controller Area Network (CAN) Module 16.1 Block Diagram Figure 16-1. CAN Controller Block Diagram CAN Control CANCTL CANSTS CANERR CANBIT CANINT CANTST CANBRPE ABP Pins CAN Tx CAN Interface 1 CANIF1CRQ CANIF1CMSK CANIF1MSK1 CANIF1MSK2 CANIF1ARB1 CANIF1ARB2 CANIF1MCTL CANIF1DA1 CANIF1DA2 CANIF1DB1 CANIF1DB2 APB Interface CAN Interface 2 CANIF2CRQ CANIF2CMSK CANIF2MSK1 CANIF2MSK2 CANIF2ARB1 CANIF2ARB2 CANIF2MCTL CANIF2DA1 CANIF2DA2 CANIF2DB1 CANIF2DB2 CAN Core CAN Rx Message Object Registers CANTXRQ1 CANTXRQ2 CANNWDA1 CANNWDA2 CANMSG1INT CANMSG2INT CANMSG1VAL CANMSG2VAL Message RAM 32 Message Objects 16.2 Signal Description Table 16-1 on page 614 lists the external signals of the CAN controller and describes the function of each. The CAN controller signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for the CAN signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 371) should be set to choose the CAN controller function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 351. Table 16-1. Controller Area Network Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type CAN0Rx 61 I Analog Description CAN module 0 receive. 614 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 16-1. Controller Area Network Signals (64LQFP) (continued) a Pin Name Pin Number Pin Type Buffer Type CAN0Tx 62 O Analog Description CAN module 0 transmit. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 16.3 Functional Description The Stellaris CAN controller conforms to the CAN protocol version 2.0 (parts A and B). Message transfers that include data, remote, error, and overload frames with an 11-bit identifier (standard) or a 29-bit identifier (extended) are supported. Transfer rates can be programmed up to 1 Mbps. The CAN module consists of three major parts: ■ CAN protocol controller and message handler ■ Message memory ■ CAN register interface A data frame contains data for transmission, whereas a remote frame contains no data and is used to request the transmission of a specific message object. The CAN data/remote frame is constructed as shown in Figure 16-2 on page 615. Figure 16-2. CAN Data/Remote Frame Remote Transmission Request Start Of Frame Bus Idle R S Control O Message Delimiter T Field R F Number 1 Of Bits 11 or 29 1 6 Delimiter Bits Data Field CRC Sequence A C K EOP IFS 0 . . . 64 15 1 1 1 7 3 CRC Sequence CRC Field Arbitration Field Bit Stuffing End of Frame Field Bus Idle Interframe Field Acknowledgement Field CAN Data Frame The protocol controller transfers and receives the serial data from the CAN bus and passes the data on to the message handler. The message handler then loads this information into the appropriate message object based on the current filtering and identifiers in the message object memory. The message handler is also responsible for generating interrupts based on events on the CAN bus. The message object memory is a set of 32 identical memory blocks that hold the current configuration, status, and actual data for each message object. These are accessed via either of the CAN message object register interfaces. July 17, 2014 615 Texas Instruments-Production Data Controller Area Network (CAN) Module The message memory is not directly accessible in the Stellaris memory map, so the Stellaris CAN controller provides an interface to communicate with the message memory via two CAN interface register sets for communicating with the message objects. As there is no direct access to the message object memory, these two interfaces must be used to read or write to each message object. The two message object interfaces allow parallel access to the CAN controller message objects when multiple objects may have new information that must be processed. In general, one interface is used for transmit data and one for receive data. 16.3.1 Initialization Software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register (with software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus are stopped and the CANnTX signal is held High. Entering the initialization state does not change the configuration of the CAN controller, the message objects, or the error counters. However, some configuration registers are only accessible while in the initialization state. To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each message object. If a message object is not needed, label it as not valid by clearing the MSGVAL bit in the CAN IFn Arbitration 2 (CANIFnARB2) register. Otherwise, the whole message object must be initialized, as the fields of the message object may not have valid information, causing unexpected results. Both the INIT and CCE bits in the CANCTL register must be set in order to access the CANBIT register and the CAN Baud Rate Prescaler Extension (CANBRPE) register to configure the bit timing. To leave the initialization state, the INIT bit must be cleared. Afterwards, the internal Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (indicating a bus idle condition) before it takes part in bus activities and starts message transfers. Message object initialization does not require the CAN to be in the initialization state and can be done on the fly. However, message objects should all be configured to particular identifiers or set to not valid before message transfer starts. To change the configuration of a message object during normal operation, clear the MSGVAL bit in the CANIFnARB2 register to indicate that the message object is not valid during the change. When the configuration is completed, set the MSGVAL bit again to indicate that the message object is once again valid. 16.3.2 Operation There are two sets of CAN Interface Registers (CANIF1x and CANIF2x), which are used to access the message objects in the Message RAM. The CAN controller coordinates transfers to and from the Message RAM to and from the registers. The two sets are independent and identical and can be used to queue transactions. Generally, one interface is used to transmit data and one is used to receive data. Once the CAN module is initialized and the INIT bit in the CANCTL register is cleared, the CAN module synchronizes itself to the CAN bus and starts the message transfer. As each message is received, it goes through the message handler's filtering process, and if it passes through the filter, is stored in the message object specified by the MNUM bit in the CAN IFn Command Request (CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and eight data bytes) is stored in the message object. If the Identifier Mask (the MSK bits in the CAN IFn Mask 1 and CAN IFn Mask 2 (CANIFnMSKn) registers) is used, the arbitration bits that are masked to "don't care" may be overwritten in the message object. The CPU may read or write each message at any time via the CAN Interface Registers. The message handler guarantees data consistency in case of concurrent accesses. 616 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The transmission of message objects is under the control of the software that is managing the CAN hardware. These can be message objects used for one-time data transfers, or permanent message objects used to respond in a more periodic manner. Permanent message objects have all arbitration and control set up, and only the data bytes are updated. At the start of transmission, the appropriate TXRQST bit in the CAN Transmission Request n (CANTXRQn) register and the NEWDAT bit in the CAN New Data n (CANNWDAn) register are set. If several transmit messages are assigned to the same message object (when the number of message objects is not sufficient), the whole message object has to be configured before the transmission of this message is requested. The transmission of any number of message objects may be requested at the same time; they are transmitted according to their internal priority, which is based on the message identifier (MNUM) for the message object, with 1 being the highest priority and 32 being the lowest priority. Messages may be updated or set to not valid any time, even when their requested transmission is still pending. The old data is discarded when a message is updated before its pending transmission has started. Depending on the configuration of the message object, the transmission of a message may be requested autonomously by the reception of a remote frame with a matching identifier. Transmission can be automatically started by the reception of a matching remote frame. To enable this mode, set the RMTEN bit in the CAN IFn Message Control (CANIFnMCTL) register. A matching received remote frame causes the TXRQST bit to be set and the message object automatically transfers its data or generates an interrupt indicating a remote frame was requested. This can be strictly a single message identifier, or it can be a range of values specified in the message object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are identified as remote frame requests. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the CANIFnMSKn register to filter which frames are identified as a remote frame request. The MXTD bit in the CANIFnMSK2 register should be set if a remote frame request is expected to be triggered by 29-bit extended identifiers. 16.3.3 Transmitting Message Objects If the internal transmit shift register of the CAN module is ready for loading, and if there is no data transfer occurring between the CAN Interface Registers and message RAM, the valid message object with the highest priority that has a pending transmission request is loaded into the transmit shift register by the message handler and the transmission is started. The message object's NEWDAT bit in the CANNWDAn register is cleared. After a successful transmission, and if no new data was written to the message object since the start of the transmission, the TXRQST bit in the CANTXRQn register is cleared. If the CAN controller is set up to interrupt upon a successful transmission of a message object, (the TXIE bit in the CAN IFn Message Control (CANIFnMCTL) register is set), the INTPND bit in the CANIFnMCTL register is set after a successful transmission. If the CAN module has lost the arbitration or if an error occurred during the transmission, the message is re-transmitted as soon as the CAN bus is free again. If, meanwhile, the transmission of a message with higher priority has been requested, the messages are transmitted in the order of their priority. 16.3.4 Configuring a Transmit Message Object The following steps illustrate how to configure a transmit message object. 1. In the CAN IFn Command Mask (CANIFnCMASK) register: ■ Set the WRNRD bit to specify a write to the CANIFnCMASK register; specify whether to transfer the IDMASK, DIR, and MXTD of the message object into the CAN IFn registers using the MASK bit ■ Specify whether to transfer the ID, DIR, XTD, and MSGVAL of the message object into the interface registers using the ARB bit July 17, 2014 617 Texas Instruments-Production Data Controller Area Network (CAN) Module ■ Specify whether to transfer the control bits into the interface registers using the CONTROL bit ■ Specify whether to clear the INTPND bit in the CANIFnMCTL register using the CLRINTPND bit ■ Specify whether to clear the NEWDAT bit in the CANNWDAn register using the NEWDAT bit ■ Specify which bits to transfer using the DATAA and DATAB bits 2. In the CANIFnMSK1 register, use the MSK[15:0] bits to specify which of the bits in the 29-bit or 11-bit message identifier are used for acceptance filtering. Note that MSK[15:0] in this register are used for bits [15:0] of the 29-bit message identifier and are not used for an 11-bit identifier. A value of 0x00 enables all messages to pass through the acceptance filtering. Also note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the UMASK bit in the CANIFnMCTL register. 3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the acceptance filtering. Also note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the UMASK bit in the CANIFnMCTL register. 4. For a 29-bit identifier, configure ID[15:0] in the CANIFnARB1 register to are used for bits [15:0] of the message identifier and ID[12:0] in the CANIFnARB2 register to are used for bits [28:16] of the message identifier. Set the XTD bit to indicate an extended identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to indicate that the message object is valid. 5. For an 11-bit identifier, disregard the CANIFnARB1 register and configure ID[12:2] in the CANIFnARB2 register to are used for bits [10:0] of the message identifier. Clear the XTD bit to indicate a standard identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to indicate that the message object is valid. 6. In the CANIFnMCTL register: ■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering ■ Optionally set the TXIE bit to enable the INTPND bit to be set after a successful transmission ■ Optionally set the RMTEN bit to enable the TXRQST bit to be set upon the reception of a matching remote frame allowing automatic transmission ■ Set the EOB bit for a single message object; ■ Set the DLC[3:0] field to specify the size of the data frame. Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits. 7. Load the data to be transmitted into the CAN IFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1, CANIFnDB2) or (CANIFnDATAA and CANIFnDATAB) registers. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. 618 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 8. Program the number of the message object to be transmitted in the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. 9. When everything is properly configured, set the TXRQST bit in the CANIFnMCTL register. Once this bit is set, the message object is available to be transmitted, depending on priority and bus availability. Note that setting the RMTEN bit in the CANIFnMCTL register can also start message transmission if a matching remote frame has been received. 16.3.5 Updating a Transmit Message Object The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface Registers and neither the MSGVAL bit in the CANIFnARB2 register nor the TXRQST bits in the CANIFnMCTL register have to be cleared before the update. Even if only some of the data bytes are to be updated, all four bytes of the corresponding CANIFnDAn/CANIFnDBn register have to be valid before the content of that register is transferred to the message object. Either the CPU must write all four bytes into the CANIFnDAn/CANIFnDBn register or the message object is transferred to the CANIFnDAn/CANIFnDBn register before the CPU writes the new data bytes. In order to only update the data in a message object, the WRNRD, DATAA and DATAB bits in the CANIFnMSKn register are set, followed by writing the updated data into CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2 registers, and then the number of the message object is written to the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. To begin transmission of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register. To prevent the clearing of the TXRQST bit in the CANIFnMCTL register at the end of a transmission that may already be in progress while the data is updated, the NEWDAT and TXRQST bits have to be set at the same time in the CANIFnMCTL register. When these bits are set at the same time, NEWDAT is cleared as soon as the new transmission has started. 16.3.6 Accepting Received Message Objects When the arbitration and control field (the ID and XTD bits in the CANIFnARB2 and the RMTEN and DLC[3:0] bits of the CANIFnMCTL register) of an incoming message is completely shifted into the CAN controller, the message handling capability of the controller starts scanning the message RAM for a matching valid message object. To scan the message RAM for a matching message object, the controller uses the acceptance filtering programmed through the mask bits in the CANIFnMSKn register and enabled using the UMASK bit in the CANIFnMCTL register. Each valid message object, starting with object 1, is compared with the incoming message to locate a matching message object in the message RAM. If a match occurs, the scanning is stopped and the message handler proceeds depending on whether it is a data frame or remote frame that was received. 16.3.7 Receiving a Data Frame The message handler stores the message from the CAN controller receive shift register into the matching message object in the message RAM. The data bytes, all arbitration bits, and the DLC bits are all stored into the corresponding message object. In this manner, the data bytes are connected with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register is set to indicate that new data has been received. The CPU should clear this bit when it reads the message object to indicate to the controller that the message has been received, and the buffer is free to receive more messages. If the CAN controller receives a message and the NEWDAT bit is already set, the MSGLST bit in the CANIFnMCTL register is set to indicate that the previous data was lost. If the system requires an interrupt upon successful reception of a frame, the RXIE bit of the CANIFnMCTL register should be set. In this case, the INTPND bit of the same register is set, July 17, 2014 619 Texas Instruments-Production Data Controller Area Network (CAN) Module causing the CANINT register to point to the message object that just received a message. The TXRQST bit of this message object should be cleared to prevent the transmission of a remote frame. 16.3.8 Receiving a Remote Frame A remote frame contains no data, but instead specifies which object should be transmitted. When a remote frame is received, three different configurations of the matching message object have to be considered: Configuration in CANIFnMCTL ■ ■ ■ UMASK = 1 or 0 ■ DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this CANIFnARB2 register message object remains unchanged, and the remote frame is ignored. This remote frame is disabled, the data is not transferred RMTEN = 0 (do not change the TXRQST bit of the and there is no indication that the remote frame ever happened. CANIFnMCTL register at reception of the frame) ■ ■ UMASK = 0 (ignore mask in the CANIFnMSKn register) ■ DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this message object is cleared. The arbitration and control field (ID + CANIFnARB2 register XTD + RMTEN + DLC) from the shift register is stored into the RMTEN = 0 (do not change the TXRQST bit of the message object in the message RAM and the NEWDAT bit of this CANIFnMCTL register at reception of the frame) message object is set. The data field of the message object remains unchanged; the remote frame is treated similar to a received data UMASK = 1 (use mask (MSK, MXTD, and MDIR in frame. This is useful for a remote data request from another CAN the CANIFnMSKn register) for acceptance filtering) device for which the Stellaris controller does not have readily available data. The software must fill the data and answer the frame manually. ■ ■ 16.3.9 Description DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this CANIFnARB2 register message object is set. The rest of the message object remains unchanged, and the controller automatically transfers the data in RMTEN = 1 (set the TXRQST bit of the the message object as soon as possible. CANIFnMCTL register at reception of the frame to enable transmission) Receive/Transmit Priority The receive/transmit priority for the message objects is controlled by the message number. Message object 1 has the highest priority, while message object 32 has the lowest priority. If more than one transmission request is pending, the message objects are transmitted in order based on the message object with the lowest message number. This should not be confused with the message identifier as that priority is enforced by the CAN bus. This means that if message object 1 and message object 2 both have valid messages that need to be transmitted, message object 1 will always be transmitted first regardless of the message identifier in the message object itself. 16.3.10 Configuring a Receive Message Object The following steps illustrate how to configure a receive message object. 1. Program the CAN IFn Command Mask (CANIFnCMASK) register as described in the “Configuring a Transmit Message Object” on page 617 section, except that the WRNRD bit is set to specify a write to the message RAM. 2. Program the CANIFnMSK1and CANIFnMSK2 registers as described in the “Configuring a Transmit Message Object” on page 617 section to configure which bits are used for acceptance 620 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller filtering. Note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the UMASK bit in the CANIFnMCTL register. 3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the acceptance filtering. Also note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the UMASK bit in the CANIFnMCTL register. 4. Program the CANIFnARB1 and CANIFnARB2 registers as described in the “Configuring a Transmit Message Object” on page 617 section to program XTD and ID bits for the message identifier to be received; set the MSGVAL bit to indicate a valid message; and clear the DIR bit to specify receive. 5. In the CANIFnMCTL register: ■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering ■ Optionally set the RXIE bit to enable the INTPND bit to be set after a successful reception ■ Clear the RMTEN bit to leave the TXRQST bit unchanged ■ Set the EOB bit for a single message object ■ Set the DLC[3:0] field to specify the size of the data frame Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits. 6. Program the number of the message object to be received in the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. Reception of the message object begins as soon as a matching frame is available on the CAN bus. When the message handler stores a data frame in the message object, it stores the received Data Length Code and eight data bytes in the CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2 register. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. If the Data Length Code is less than 8, the remaining bytes of the message object are overwritten by unspecified values. The CAN mask registers can be used to allow groups of data frames to be received by a message object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register should be set if only 29-bit extended identifiers are expected by this message object. 16.3.11 Handling of Received Message Objects The CPU may read a received message any time via the CAN Interface registers because the data consistency is guaranteed by the message handler state machine. Typically, the CPU first writes 0x007F to the CANIFnCMSK register and then writes the number of the message object to the CANIFnCRQ register. That combination transfers the whole received message from the message RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn, and CANIFnMCTL). Additionally, the NEWDAT and INTPND bits are cleared in the message RAM, July 17, 2014 621 Texas Instruments-Production Data Controller Area Network (CAN) Module acknowledging that the message has been read and clearing the pending interrupt generated by this message object. If the message object uses masks for acceptance filtering, the CANIFnARBn registers show the full, unmasked ID for the received message. The NEWDAT bit in the CANIFnMCTL register shows whether a new message has been received since the last time this message object was read. The MSGLST bit in the CANIFnMCTL register shows whether more than one message has been received since the last time this message object was read. MSGLST is not automatically cleared, and should be cleared by software after reading its status. Using a remote frame, the CPU may request new data from another CAN node on the CAN bus. Setting the TXRQST bit of a receive object causes the transmission of a remote frame with the receive object's identifier. This remote frame triggers the other CAN node to start the transmission of the matching data frame. If the matching data frame is received before the remote frame could be transmitted, the TXRQST bit is automatically reset. This prevents the possible loss of data when the other device on the CAN bus has already transmitted the data slightly earlier than expected. 16.3.11.1 Configuration of a FIFO Buffer With the exception of the EOB bit in the CANIFnMCTL register, the configuration of receive message objects belonging to a FIFO buffer is the same as the configuration of a single receive message object (see “Configuring a Receive Message Object” on page 620). To concatenate two or more message objects into a FIFO buffer, the identifiers and masks (if used) of these message objects have to be programmed to matching values. Due to the implicit priority of the message objects, the message object with the lowest message object number is the first message object in a FIFO buffer. The EOB bit of all message objects of a FIFO buffer except the last one must be cleared. The EOB bit of the last message object of a FIFO buffer is set, indicating it is the last entry in the buffer. 16.3.11.2 Reception of Messages with FIFO Buffers Received messages with identifiers matching to a FIFO buffer are stored starting with the message object with the lowest message number. When a message is stored into a message object of a FIFO buffer, the NEWDAT of the CANIFnMCTL register bit of this message object is set. By setting NEWDAT while EOB is clear, the message object is locked and cannot be written to by the message handler until the CPU has cleared the NEWDAT bit. Messages are stored into a FIFO buffer until the last message object of this FIFO buffer is reached. If none of the preceding message objects has been released by clearing the NEWDAT bit, all further messages for this FIFO buffer will be written into the last message object of the FIFO buffer and therefore overwrite previous messages. 16.3.11.3 Reading from a FIFO Buffer When the CPU transfers the contents of a message object from a FIFO buffer by writing its number to the CANIFnCRQ, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should be set such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the read. The values of these bits in the CANIFnMCTL register always reflect the status of the message object before the bits are cleared. To assure the correct function of a FIFO buffer, the CPU should read out the message objects starting with the message object with the lowest message number. When reading from the FIFO buffer, the user should be aware that a new received message is placed in the message object with the lowest message number for which the NEWDAT bit of the CANIFnMCTL register. As a result, the order of the received messages in the FIFO is not guaranteed. Figure 16-3 on page 623 shows how a set of message objects which are concatenated to a FIFO Buffer can be handled by the CPU. 622 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 16-3. Message Objects in a FIFO Buffer START Message Interrupt Read Interrupt Pointer 0x0000 Case Interrupt Pointer else 0x8000 END Status Change Interrupt Handling MNUM = Interrupt Pointer Write MNUM to IFn Command Request (Read Message to IFn Registers, Reset NEWDAT = 0, Reset INTPND = 0 Read IFn Message Control Yes No NEWDAT = 1 Read Data from IFn Data A,B EOB = 1 Yes No MNUM = MNUM + 1 July 17, 2014 623 Texas Instruments-Production Data Controller Area Network (CAN) Module 16.3.12 Handling of Interrupts If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt with the highest priority, disregarding their chronological order. The status interrupt has the highest priority. Among the message interrupts, the message object's interrupt with the lowest message number has the highest priority. A message interrupt is cleared by clearing the message object's INTPND bit in the CANIFnMCTL register or by reading the CAN Status (CANSTS) register. The status Interrupt is cleared by reading the CANSTS register. The interrupt identifier INTID in the CANINT register indicates the cause of the interrupt. When no interrupt is pending, the register reads as 0x0000. If the value of the INTID field is different from 0, then there is an interrupt pending. If the IE bit is set in the CANCTL register, the interrupt line to the CPU is active. The interrupt line remains active until the INTID field is 0, meaning that all interrupt sources have been cleared (the cause of the interrupt is reset), or until IE is cleared, which disables interrupts from the CAN controller. The INTID field of the CANINT register points to the pending message interrupt with the highest interrupt priority. The SIE bit in the CANCTL register controls whether a change of the RXOK, TXOK, and LEC bits in the CANSTS register can cause an interrupt. The EIE bit in the CANCTLregister controls whether a change of the BOFF and EWARN bits in the CANSTS can cause an interrupt. The IE bit in the CANCTL controls whether any interrupt from the CAN controller actually generates an interrupt to the microcontroller's interrupt controller. The CANINT register is updated even when the IE bit in the CANCTL register is clear, but the interrupt will not be indicated to the CPU. A value of 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN module has updated, but not necessarily changed, the CANSTS , indicating that either an error or status interrupt has been generated. A write access to the CANSTS register can clear the RXOK, TXOK, and LEC bits in that same register; however, the only way to clear the source of a status interrupt is to read the CANSTS register. There are two ways to determine the source of an interrupt during interrupt handling. The first is to read the INTID bit in the CANINT register to determine the highest priority interrupt that is pending, and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see all of the message objects that have pending interrupts. An interrupt service routine reading the message that is the source of the interrupt may read the message and clear the message object's INTPND bit at the same time by setting the CLRINTPND bit in the CANIFnCMSK register. Once the INTPND bit has been cleared, the CANINT register contains the message number for the next message object with a pending interrupt. 16.3.13 Test Mode A Test Mode is provided, which allows various diagnostics to be performed. Test Mode is entered by setting the TEST bit CANCTL register. Once in Test Mode, the TX[1:0], LBACK, SILENT and BASIC bits in the CAN Test (CANTST) register can be used to put the CAN controller into the various diagnostic modes. The RX bit in the CANTST register allows monitoring of the CANnRX signal. All CANTST register functions are disabled when the TEST bit is cleared. 16.3.13.1 Silent Mode Silent Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames). The CAN Controller is put in Silent Mode setting the SILENT bit in the CANTST register. In Silent Mode, the CAN controller is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the CAN bus and it cannot start a transmission. If the CAN Controller is required to send a dominant bit (ACK bit, overload flag, 624 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller or active error flag), the bit is rerouted internally so that the CAN Controller monitors this dominant bit, although the CAN bus remains in recessive state. 16.3.13.2 Loopback Mode Loopback mode is useful for self-test functions. In Loopback Mode, the CAN Controller internally routes the CANnTX signal on to the CANnRX signal and treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into the message buffer. The CAN Controller is put in Loopback Mode by setting the LBACK bit in the CANTST register. To be independent from external stimulation, the CAN Controller ignores acknowledge errors (a recessive bit sampled in the acknowledge slot of a data/remote frame) in Loopback Mode. The actual value of the CANnRX signal is disregarded by the CAN Controller. The transmitted messages can be monitored on the CANnTX signal. 16.3.13.3 Loopback Combined with Silent Mode Loopback Mode and Silent Mode can be combined to allow the CAN Controller to be tested without affecting a running CAN system connected to the CANnTX and CANnRX signals. In this mode, the CANnRX signal is disconnected from the CAN Controller and the CANnTX signal is held recessive. This mode is enabled by setting both the LBACK and SILENT bits in the CANTST register. 16.3.13.4 Basic Mode Basic Mode allows the CAN Controller to be operated without the Message RAM. In Basic Mode, The CANIF1 registers are used as the transmit buffer. The transmission of the contents of the IF1 registers is requested by setting the BUSY bit of the CANIF1CRQ register. The CANIF1 registers are locked while the BUSY bit is set. The BUSY bit indicates that a transmission is pending. As soon the CAN bus is idle, the CANIF1 registers are loaded into the shift register of the CAN Controller and transmission is started. When the transmission has completed, the BUSY bit is cleared and the locked CANIF1 registers are released. A pending transmission can be aborted at any time by clearing the BUSY bit in the CANIF1CRQ register while the CANIF1 registers are locked. If the CPU has cleared the BUSY bit, a possible retransmission in case of lost arbitration or an error is disabled. The CANIF2 Registers are used as a receive buffer. After the reception of a message, the contents of the shift register is stored into the CANIF2 registers, without any acceptance filtering. Additionally, the actual contents of the shift register can be monitored during the message transfer. Each time a read message object is initiated by setting the BUSY bit of the CANIF2CRQ register, the contents of the shift register are stored into the CANIF2 registers. In Basic Mode, all message-object-related control and status bits and of the control bits of the CANIFnCMSK registers are not evaluated. The message number of the CANIFnCRQ registers is also not evaluated. In the CANIF2MCTL register, the NEWDAT and MSGLST bits retain their function, the DLC[3:0] field shows the received DLC, the other control bits are cleared. Basic Mode is enabled by setting the BASIC bit in the CANTST register. 16.3.13.5 Transmit Control Software can directly override control of the CANnTX signal in four different ways. ■ CANnTX is controlled by the CAN Controller ■ The sample point is driven on the CANnTX signal to monitor the bit timing ■ CANnTX drives a low value July 17, 2014 625 Texas Instruments-Production Data Controller Area Network (CAN) Module ■ CANnTX drives a high value The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check the physical layer of the CAN bus. The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register. The three test functions for the CANnTX signal interfere with all CAN protocol functions. TX[1:0] must be cleared when CAN message transfer or Loopback Mode, Silent Mode, or Basic Mode are selected. 16.3.14 Bit Timing Configuration Error Considerations Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the performance of a CAN network can be reduced significantly. In many cases, the CAN bit synchronization amends a faulty configuration of the CAN bit timing to such a degree that only occasionally an error frame is generated. In the case of arbitration, however, when two or more CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the transmitters to become error passive. The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on the CAN bus. 16.3.15 Bit Time and Bit Rate The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member of the CAN network has its own clock generator. The timing parameter of the bit time can be configured individually for each CAN node, creating a common bit rate even though the CAN nodes' oscillator periods may be different. Because of small variations in frequency caused by changes in temperature or voltage and by deteriorating components, these oscillators are not absolutely stable. As long as the variations remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the different bit rates by periodically resynchronizing to the bit stream. According to the CAN specification, the bit time is divided into four segments (see Figure 16-4 on page 627): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable number of time quanta (see Table 16-2 on page 627). The length of the time quantum (tq), which is the basic time unit of the bit time, is defined by the CAN controller's input clock (fsys) and the Baud Rate Prescaler (BRP): tq = BRP / fsys The fsys input clock is the system clock frequency as configured by the RCC or RCC2 registers (see page 194 or page 201). The Synchronization Segment Sync is that part of the bit time where edges of the CAN bus level are expected to occur; the distance between an edge that occurs outside of Sync and the Sync is called the phase error of that edge. The Propagation Time Segment Prop is intended to compensate for the physical delay times within the CAN network. The Phase Buffer Segments Phase1 and Phase2 surround the Sample Point. The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase errors. 626 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller A given bit rate may be met by different bit-time configurations, but for the proper function of the CAN network, the physical delay times and the oscillator's tolerance range have to be considered. Figure 16-4. CAN Bit Time Nominal CAN Bit Time a b TSEG1 Sync Prop TSEG2 Phase1 c 1 Time Quantum q) (tq Phase2 Sample Point a. TSEG1 = Prop + Phase1 b. TSEG2 = Phase2 c. Phase1 = Phase2 or Phase1 + 1 = Phase2 a Table 16-2. CAN Protocol Ranges Parameter Range Remark BRP [1 .. 64] Defines the length of the time quantum tq. The CANBRPE register can be used to extend the range to 1024. Sync 1 tq Fixed length, synchronization of bus input to system clock Prop [1 .. 8] tq Compensates for the physical delay times Phase1 [1 .. 8] tq May be lengthened temporarily by synchronization Phase2 [1 .. 8] tq May be shortened temporarily by synchronization SJW [1 .. 4] tq May not be longer than either Phase Buffer Segment a. This table describes the minimum programmable ranges required by the CAN protocol. The bit timing configuration is programmed in two register bytes in the CANBIT register. In the CANBIT register, the four components TSEG2, TSEG1, SJW, and BRP have to be programmed to a numerical value that is one less than its functional value; so instead of values in the range of [1..n], values in the range of [0..n-1] are programmed. That way, for example, SJW (functional range of [1..4]) is represented by only two bits in the SJW bit field. Table 16-3 shows the relationship between the CANBIT register values and the parameters. Table 16-3. CANBIT Register Values CANBIT Register Field Setting TSEG2 Phase2 - 1 TSEG1 Prop + Phase1 - 1 SJW SJW - 1 BRP BRP Therefore, the length of the bit time is (programmed values): [TSEG1 + TSEG2 + 3] × tq or (functional values): July 17, 2014 627 Texas Instruments-Production Data Controller Area Network (CAN) Module [Sync + Prop + Phase1 + Phase2] × tq The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number of time quanta in the bit time. The processing of the bit time, the calculation of the position of the sample point, and occasional synchronizations are controlled by the CAN controller and are evaluated once per time quantum. The CAN controller translates messages to and from frames. In addition, the controller generates and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC code, performs the error management, and decides which type of synchronization is to be used. The bit value is received or transmitted at the sample point. The information processing time (IPT) is the time after the sample point needed to calculate the next bit to be transmitted on the CAN bus. The IPT includes any of the following: retrieving the next data bit, handling a CRC bit, determining if bit stuffing is required, generating an error flag or simply going idle. The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is the lower limit of the programmed length of Phase2. In case of synchronization, Phase2 may be shortened to a value less than IPT, which does not affect bus timing. 16.3.16 Calculating the Bit Timing Parameters Usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. The resulting bit time (1/bit rate) must be an integer multiple of the system clock period. The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the required bit time, allowing iterations of the following steps. The first part of the bit time to be defined is Prop. Its length depends on the delay times measured in the system. A maximum bus length as well as a maximum node delay has to be defined for expandable CAN bus systems. The resulting time for Prop is converted into time quanta (rounded up to the nearest integer multiple of tq). Sync is 1 tq long (fixed), which leaves (bit time - Prop - 1) tq for the two Phase Buffer Segments. If the number of remaining tq is even, the Phase Buffer Segments have the same length, that is, Phase2 = Phase1, else Phase2 = Phase1 + 1. The minimum nominal length of Phase2 has to be regarded as well. Phase2 may not be shorter than the CAN controller's Information Processing Time, which is, depending on the actual implementation, in the range of [0..2] tq. The length of the synchronization jump width is set to the least of 4, Phase1 or Phase2. The oscillator tolerance range necessary for the resulting configuration is calculated by the formula given below: (1 − df ) × fnom ≤ fosc ≤ (1 + df ) × fnom where: df ≤ (Phase _ seg1, Phase _ seg2) min 2 × (13 × tbit − Phase _ Seg 2) ■ df = Maximum tolerance of oscillator frequency ■ fosc Actual=oscillator df =max 2 × dffrequency × fnom 628 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ■ fnom = Nominal oscillator frequency − )df × fnom ≤ fosc + account × the fnom frequency tolerance must following formulas: (Maximum )df 1 −(1df × )fnom ≤ fosc ≤ (take 1≤ +(1into df × )fnom (Phase _ seg 1, Phase _ seg 2) min (Phase _ seg 1, Phase _ seg 2) min df df ≤ ≤ 2 × (13 × tbit − Phase _ Seg 2) 2 × (13 × tbit − Phase _ Seg 2) × df × fnom df df maxmax = 2=× 2df × fnom where: ■ Phase1 and Phase2 are from Table 16-2 on page 627 ■ tbit = Bit Time ■ dfmax = Maximum difference between two oscillators If more than one configuration is possible, that configuration allowing the highest oscillator tolerance range should be chosen. CAN nodes with different system clocks require different configurations to come to the same bit rate. The calculation of the propagation time in the CAN network, based on the nodes with the longest delay times, is done once for the whole network. The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range. The calculation may show that bus length or bit rate have to be decreased or that the oscillator frequencies' stability has to be increased in order to find a protocol-compliant configuration of the CAN bit timing. 16.3.16.1 Example for Bit Timing at High Baud Rate In this example, the frequency of CAN clock is 25 MHz, and the bit rate is 1 Mbps. bit time = 1 µs = n * tq = 5 * tq = 200 ns tq = (Baud rate Prescaler)/CAN Baud rate Prescaler = tq * CAN Baud rate Prescaler = 200E-9 * tq Clock Clock 25E6 = 5 tSync = 1 * tq = 200 ns \\fixed at 1 time quanta delay delay delay tProp \\400 is next integer multiple of tq of bus driver 50 ns of receiver circuit 30 ns of bus line (40m) 220 ns 400 ns = 2 * tq bit time bit time tPhase 1 tPhase 1 tPhase 1 = = + + + tSync + tSync + tPhase2 tPhase2 tPhase2 tTSeg1 + tTSeg2 = 5 * tq tProp + tPhase 1 + tPhase2 = bit time - tSync - tProp = (5 * tq) - (1 * tq) - (2 * tq) = 2 * tq July 17, 2014 629 Texas Instruments-Production Data Controller Area Network (CAN) Module tPhase1 = 1 * tq tPhase2 = 1 * tq \\tPhase2 = tPhase1 tTSeg1 = tProp + tPhase1 tTSeg1 = (2 * tq) + (1 * tq) tTSeg1 = 3 * tq tTSeg2 = tPhase2 tTSeg2 = (Information Processing Time + 1) * tq tTSeg2 = 1 * tq \\Assumes IPT=0 tSJW = 1 * tq \\Least of 4, Phase1 and Phase2 In the above example, the bit field values for the CANBIT register are: = TSeg2 -1 TSEG2 = 1-1 =0 = TSeg1 -1 TSEG1 = 3-1 =2 = SJW -1 SJW = 1-1 =0 = Baud rate prescaler - 1 BRP = 5-1 =4 The final value programmed into the CANBIT register = 0x0204. 16.3.16.2 Example for Bit Timing at Low Baud Rate In this example, the frequency of the CAN clock is 50 MHz, and the bit rate is 100 Kbps. bit time = 10 µs = n * tq = 10 * tq tq = 1 µs tq = (Baud rate Prescaler)/CAN Clock Baud rate Prescaler = tq * CAN Clock Baud rate Prescaler = 1E-6 * 50E6 = 50 tSync = 1 * tq = 1 µs \\fixed at 1 time quanta delay delay delay tProp \\1 µs is next integer multiple of tq of bus driver 200 ns of receiver circuit 80 ns of bus line (40m) 220 ns 1 µs = 1 * tq bit time bit time tPhase 1 tPhase 1 tPhase 1 = = + + + tSync + tSync + tPhase2 tPhase2 tPhase2 tTSeg1 + tTSeg2 = 10 * tq tProp + tPhase 1 + tPhase2 = bit time - tSync - tProp = (10 * tq) - (1 * tq) - (1 * tq) = 8 * tq 630 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller tPhase1 = 4 * tq tPhase2 = 4 * tq tTSeg1 tTSeg1 tTSeg1 tTSeg2 tTSeg2 tTSeg2 = = = = = = \\tPhase1 = tPhase2 tProp + tPhase1 (1 * tq) + (4 * tq) 5 * tq tPhase2 (Information Processing Time + 4) × tq 4 * tq \\Assumes IPT=0 tSJW = 4 * tq \\Least of 4, Phase1, and Phase2 = TSeg2 -1 TSEG2 = 4-1 =3 = TSeg1 -1 TSEG1 = 5-1 =4 = SJW -1 SJW = 4-1 =3 = Baud rate prescaler - 1 BRP = 50-1 =49 The final value programmed into the CANBIT register = 0x34F1. 16.4 Register Map Table 16-4 on page 631 lists the registers. All addresses given are relative to the CAN base address of: ■ CAN0: 0x4004.0000 Note that the CAN module clock must be enabled before the registers can be programmed (see page 217). There must be a delay of 3 system clocks after the CAN module clock is enabled before any CAN module registers are accessed. Table 16-4. CAN Register Map Offset Name Type Reset Description See page 0x000 CANCTL R/W 0x0000.0001 CAN Control 634 0x004 CANSTS R/W 0x0000.0000 CAN Status 636 0x008 CANERR RO 0x0000.0000 CAN Error Counter 638 0x00C CANBIT R/W 0x0000.2301 CAN Bit Timing 639 0x010 CANINT RO 0x0000.0000 CAN Interrupt 640 0x014 CANTST R/W 0x0000.0000 CAN Test 641 0x018 CANBRPE R/W 0x0000.0000 CAN Baud Rate Prescaler Extension 643 July 17, 2014 631 Texas Instruments-Production Data Controller Area Network (CAN) Module Table 16-4. CAN Register Map (continued) Description See page Offset Name Type Reset 0x020 CANIF1CRQ R/W 0x0000.0001 CAN IF1 Command Request 644 0x024 CANIF1CMSK R/W 0x0000.0000 CAN IF1 Command Mask 645 0x028 CANIF1MSK1 R/W 0x0000.FFFF CAN IF1 Mask 1 647 0x02C CANIF1MSK2 R/W 0x0000.FFFF CAN IF1 Mask 2 648 0x030 CANIF1ARB1 R/W 0x0000.0000 CAN IF1 Arbitration 1 649 0x034 CANIF1ARB2 R/W 0x0000.0000 CAN IF1 Arbitration 2 650 0x038 CANIF1MCTL R/W 0x0000.0000 CAN IF1 Message Control 652 0x03C CANIF1DA1 R/W 0x0000.0000 CAN IF1 Data A1 654 0x040 CANIF1DA2 R/W 0x0000.0000 CAN IF1 Data A2 654 0x044 CANIF1DB1 R/W 0x0000.0000 CAN IF1 Data B1 654 0x048 CANIF1DB2 R/W 0x0000.0000 CAN IF1 Data B2 654 0x080 CANIF2CRQ R/W 0x0000.0001 CAN IF2 Command Request 644 0x084 CANIF2CMSK R/W 0x0000.0000 CAN IF2 Command Mask 645 0x088 CANIF2MSK1 R/W 0x0000.FFFF CAN IF2 Mask 1 647 0x08C CANIF2MSK2 R/W 0x0000.FFFF CAN IF2 Mask 2 648 0x090 CANIF2ARB1 R/W 0x0000.0000 CAN IF2 Arbitration 1 649 0x094 CANIF2ARB2 R/W 0x0000.0000 CAN IF2 Arbitration 2 650 0x098 CANIF2MCTL R/W 0x0000.0000 CAN IF2 Message Control 652 0x09C CANIF2DA1 R/W 0x0000.0000 CAN IF2 Data A1 654 0x0A0 CANIF2DA2 R/W 0x0000.0000 CAN IF2 Data A2 654 0x0A4 CANIF2DB1 R/W 0x0000.0000 CAN IF2 Data B1 654 0x0A8 CANIF2DB2 R/W 0x0000.0000 CAN IF2 Data B2 654 0x100 CANTXRQ1 RO 0x0000.0000 CAN Transmission Request 1 655 0x104 CANTXRQ2 RO 0x0000.0000 CAN Transmission Request 2 655 0x120 CANNWDA1 RO 0x0000.0000 CAN New Data 1 656 0x124 CANNWDA2 RO 0x0000.0000 CAN New Data 2 656 0x140 CANMSG1INT RO 0x0000.0000 CAN Message 1 Interrupt Pending 657 0x144 CANMSG2INT RO 0x0000.0000 CAN Message 2 Interrupt Pending 657 0x160 CANMSG1VAL RO 0x0000.0000 CAN Message 1 Valid 658 0x164 CANMSG2VAL RO 0x0000.0000 CAN Message 2 Valid 658 632 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 16.5 CAN Register Descriptions The remainder of this section lists and describes the CAN registers, in numerical order by address offset. There are two sets of Interface Registers that are used to access the Message Objects in the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used to queue transactions. July 17, 2014 633 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 1: CAN Control (CANCTL), offset 0x000 This control register initializes the module and enables test mode and interrupts. The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11 consecutive High bits) before resuming normal operations. At the end of the bus-off recovery sequence, the Error Management Counters are reset. During the waiting time after INIT is cleared, each time a sequence of 11 High bits has been monitored, a BITERROR0 code is written to the CANSTS register (the LEC field = 0x5), enabling the CPU to readily check whether the CAN bus is stuck Low or continuously disturbed, and to monitor the proceeding of the bus-off recovery sequence. CAN Control (CANCTL) CAN0 base: 0x4004.0000 Offset 0x000 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TEST CCE DAR reserved EIE SIE IE INIT R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 TEST R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Test Mode Enable 0: Normal operation 1: Test mode 6 CCE R/W 0 Configuration Change Enable 0: Do not allow write access to the CANBIT register. 1: Allow write access to the CANBIT register if the INIT bit is 1. 5 DAR R/W 0 Disable Automatic-Retransmission 0: Auto-retransmission of disturbed messages is enabled. 1: Auto-retransmission is disabled. 4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 EIE R/W 0 Error Interrupt Enable 0: Disabled. No error status interrupt is generated. 1: Enabled. A change in the BOFF or EWARN bits in the CANSTS register generates an interrupt. 634 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 2 SIE R/W 0 Description Status Interrupt Enable 0: Disabled. No status interrupt is generated. 1: Enabled. An interrupt is generated when a message has successfully been transmitted or received, or a CAN bus error has been detected. A change in the TXOK, RXOK or LEC bits in the CANSTS register generates an interrupt. 1 IE R/W 0 CAN Interrupt Enable 0: Interrupts disabled. 1: Interrupts enabled. 0 INIT R/W 1 Initialization 0: Normal operation. 1: Initialization started. July 17, 2014 635 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 2: CAN Status (CANSTS), offset 0x004 Important: This register is read-sensitive. See the register description for details. The status register contains information for interrupt servicing such as Bus-Off, error count threshold, and error types. The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This field is cleared when a message has been transferred (reception or transmission) without error. The unused error code 7 may be written by the CPU to manually set this field to an invalid error so that it can be checked for a change later. An error interrupt is generated by the BOFF and EWARN bits and a status interrupt is generated by the RXOK, TXOK, and LEC bits, if the corresponding enable bits in the CAN Control (CANCTL) register are set. A change of the EPASS bit or a write to the RXOK, TXOK, or LEC bits does not generate an interrupt. Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is pending. CAN Status (CANSTS) CAN0 base: 0x4004.0000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 BOFF EWARN EPASS RXOK TXOK RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 BOFF RO 0 LEC R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bus-Off Status 0: CAN controller is not in bus-off state. 1: CAN controller is in bus-off state. 6 EWARN RO 0 Warning Status 0: Both error counters are below the error warning limit of 96. 1: At least one of the error counters has reached the error warning limit of 96. 5 EPASS RO 0 Error Passive 0: The CAN module is in the Error Active state, that is, the receive or transmit error count is less than or equal to 127. 1: The CAN module is in the Error Passive state, that is, the receive or transmit error count is greater than 127. 636 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 4 RXOK R/W 0 Description Received a Message Successfully 0: Since this bit was last cleared, no message has been successfully received. 1: Since this bit was last cleared, a message has been successfully received, independent of the result of the acceptance filtering. This bit is never cleared by the CAN module. 3 TXOK R/W 0 Transmitted a Message Successfully 0: Since this bit was last cleared, no message has been successfully transmitted. 1: Since this bit was last cleared, a message has been successfully transmitted error-free and acknowledged by at least one other node. This bit is never cleared by the CAN module. 2:0 LEC R/W 0x0 Last Error Code This is the type of the last error to occur on the CAN bus. Value Definition 0x0 No Error 0x1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x2 Format Error A fixed format part of the received frame has the wrong format. 0x3 ACK Error The message transmitted was not acknowledged by another node. 0x4 Bit 1 Error When a message is transmitted, the CAN controller monitors the data lines to detect any conflicts. When the arbitration field is transmitted, data conflicts are a part of the arbitration protocol. When other frame fields are transmitted, data conflicts are considered errors. A Bit 1 Error indicates that the device wanted to send a High level (logical 1) but the monitored bus value was Low (logical 0). 0x5 Bit 0 Error A Bit 0 Error indicates that the device wanted to send a Low level (logical 0), but the monitored bus value was High (logical 1). During bus-off recovery, this status is set each time a sequence of 11 High bits has been monitored. This enables the CPU to monitor the proceeding of the bus-off recovery sequence without any disturbances to the bus. 0x6 CRC Error The CRC checksum was incorrect in the received message, indicating that the calculated value received did not match the calculated CRC of the data. 0x7 No Event When the LEC bit shows this value, no CAN bus event was detected since the CPU wrote this value to LEC. July 17, 2014 637 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 3: CAN Error Counter (CANERR), offset 0x008 This register contains the error counter values, which can be used to analyze the cause of an error. CAN Error Counter (CANERR) CAN0 base: 0x4004.0000 Offset 0x008 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RP Type Reset RO 0 REC TEC RO 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 RP RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Received Error Passive 0: The Receive Error counter is below the Error Passive level (127 or less). 1: The Receive Error counter has reached the Error Passive level (128 or greater). 14:8 REC RO 0x00 Receive Error Counter State of the receiver error counter (0 to 127). 7:0 TEC RO 0x00 Transmit Error Counter State of the transmit error counter (0 to 255). 638 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 4: CAN Bit Timing (CANBIT), offset 0x00C This register is used to program the bit width and bit quantum. Values are programmed to the system clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL register. See “Bit Time and Bit Rate” on page 626 for more information. CAN Bit Timing (CANBIT) CAN0 base: 0x4004.0000 Offset 0x00C Type R/W, reset 0x0000.2301 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 1 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset reserved Type Reset RO 0 TSEG2 R/W 0 R/W 1 TSEG1 Bit/Field Name Type Reset 31:15 reserved RO 0x0000 14:12 TSEG2 R/W 0x2 SJW BRP Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Time Segment after Sample Point 0x00-0x07: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. So, for example, a reset value of 0x2 defines that there is 3 (2+1) bit time quanta defined for Phase_Seg2 (see Figure 16-4 on page 627). The bit time quanta is defined by the BRP field. 11:8 TSEG1 R/W 0x3 Time Segment Before Sample Point 0x00-0x0F: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. So, for example, the reset value of 0x3 defines that there is 4 (3+1) bit time quanta defined for Phase_Seg1 (see Figure 16-4 on page 627). The bit time quanta is define by the BRP field. 7:6 SJW R/W 0x0 (Re)Synchronization Jump Width 0x00-0x03: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. During the start of frame (SOF), if the CAN controller detects a phase error (misalignment), it can adjust the length of TSEG2 or TSEG1 by the value in SJW. So the reset value of 0 adjusts the length by 1 bit time quanta. 5:0 BRP R/W 0x1 Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quantum. 0x00-0x03F: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. BRP defines the number of CAN clock periods that make up 1 bit time quanta, so the reset value is 2 bit time quanta (1+1). The CANBRPE register can be used to further divide the bit time. July 17, 2014 639 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 5: CAN Interrupt (CANINT), offset 0x010 This register indicates the source of the interrupt. If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in the CANCTL register is set, the interrupt is active. The interrupt line remains active until the INTID field is cleared by reading the CANSTS register, or until the IE bit in the CANCTL register is cleared. Note: Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is pending. CAN Interrupt (CANINT) CAN0 base: 0x4004.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset INTID Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 INTID RO 0x0000 Interrupt Identifier The number in this field indicates the source of the interrupt. Value Definition 0x0000 No interrupt pending 0x0001-0x0020 Number of the message object that caused the interrupt 0x0021-0x7FFF Reserved 0x8000 Status Interrupt 0x8001-0xFFFF Reserved 640 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 6: CAN Test (CANTST), offset 0x014 This is the test mode register for self-test and external pin access. It is write-enabled by setting the TEST bit in the CANCTL register. Different test functions may be combined, however, CAN transfers will be affected if the TX bits in this register are not zero. CAN Test (CANTST) CAN0 base: 0x4004.0000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 LBACK SILENT BASIC RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RX RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 RX RO 0 TX R/W 0 R/W 0 reserved RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Receive Observation Displays the value on the CANnRx pin. 6:5 TX R/W 0x0 Transmit Control Overrides control of the CANnTx pin. Value Description 0x0 CAN Module Control CANnTx is controlled by the CAN module; default operation 0x1 Sample Point The sample point is driven on the CANnTx signal. This mode is useful to monitor bit timing. 0x2 Driven Low CANnTx drives a low value. This mode is useful for checking the physical layer of the CAN bus. 0x3 Driven High CANnTx drives a high value. This mode is useful for checking the physical layer of the CAN bus. 4 LBACK R/W 0 Loopback Mode 0: Disabled. 1: Enabled. In loopback mode, the data from the transmitter is routed into the receiver. Any data on the receive input is ignored. July 17, 2014 641 Texas Instruments-Production Data Controller Area Network (CAN) Module Bit/Field Name Type Reset Description 3 SILENT R/W 0 Silent Mode Do not transmit data; monitor the bus. Also known as Bus Monitor mode. 0: Disabled. 1: Enabled. 2 BASIC R/W 0 Basic Mode 0: Disabled. 1: Use CANIF1 registers as transmit buffer, and use CANIF2 registers as receive buffer. 1:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 642 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is write-enabled by setting the CCE bit in the CANCTL register. CAN Baud Rate Prescaler Extension (CANBRPE) CAN0 base: 0x4004.0000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3:0 BRPE R/W 0x0 BRPE Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Baud Rate Prescaler Extension 0x00-0x0F: Extend the BRP bit in the CANBIT register to values up to 1023. The actual interpretation by the hardware is one more than the value programmed by BRPE (MSBs) and BRP (LSBs). July 17, 2014 643 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 A message transfer is started as soon as there is a write of the message object number to the MNUM field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY bit is automatically set to indicate that a transfer between the CAN Interface Registers and the internal message RAM is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the interface register and the message RAM completes, which then clears the BUSY bit. CAN IF1 Command Request (CANIF1CRQ) CAN0 base: 0x4004.0000 Offset 0x020 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset BUSY Type Reset RO 0 reserved RO 0 MNUM Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 BUSY RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Busy Flag 0: Cleared when read/write action has finished. 1: Set when a write occurs to the message number in this register. 14:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:0 MNUM R/W 0x01 Message Number Selects one of the 32 message objects in the message RAM for data transfer. The message objects are numbered from 1 to 32. Value Description 0x00 Reserved 0 is not a valid message number; it is interpreted as 0x20, or object 32. 0x01-0x20 Message Number Indicates specified message object 1 to 32. 0x21-0x3F Reserved Not a valid message number; values are shifted and it is interpreted as 0x01-0x1F. 644 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 Reading the Command Mask registers provides status for various functions. Writing to the Command Mask registers specifies the transfer direction and selects which buffer registers are the source or target of the data transfer. Note that when a read from the message object buffer occurs when the WRNRD bit is clear and the CLRINTPND and/or NEWDAT bits are set, the interrupt pending and/or new data flags in the message object buffer are cleared. CAN IF1 Command Mask (CANIF1CMSK) CAN0 base: 0x4004.0000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRNRD MASK ARB CONTROL CLRINTPND NEWDAT / TXRQST reserved DATAA DATAB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 WRNRD R/W 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Write, Not Read Transfer the message object address specified by the CAN Command Request (CANIFnCRQ) register to the CAN message buffer registers. Note: 6 MASK R/W 0 Interrupt pending and new data conditions in the message buffer can be cleared by reading from the buffer (WRNRD = 0) when the CLRINTPND and/or NEWDAT bits are set. Access Mask Bits 0: Mask bits unchanged. 1: Transfer IDMASK + DIR + MXTD of the message object into the Interface registers. 5 ARB R/W 0 Access Arbitration Bits 0: Arbitration bits unchanged. 1: Transfer ID + DIR + XTD + MSGVAL of the message object into the Interface registers. July 17, 2014 645 Texas Instruments-Production Data Controller Area Network (CAN) Module Bit/Field Name Type Reset 4 CONTROL R/W 0 Description Access Control Bits 0: Control bits unchanged. 1: Transfer control bits from the CANIFnMCTL register into the Interface registers. 3 CLRINTPND R/W 0 Clear Interrupt Pending Bit If WRNRD is set, this bit controls whether the INTPND bit in the CANIFnMCTL register is changed. 0: The INTPND bit in the message object remains unchanged. 1: The INTPND bit is cleared in the message object. If WRNRD is clear and this bit is clear, the interrupt pending status is transferred from the message buffer into the CANIFnMCTL register. If WRNRD is clear and this bit is set, the interrupt pending status is cleared in the message buffer. Note that the value of this bit that is transferred to the CANIFnMCTL register always reflects the status of the bits before clearing. 2 NEWDAT / TXRQST R/W 0 NEWDAT / TXRQST Bit If WRNRD is set, this bit can act as a TXRQST bit and request a transmission. Note that when this bit is set, the TXRQST bit in the CANIFnMCTL register is ignored. 0: Transmission is not requested 1: Begin a transmission If WRNRD is clear and this bit is clear, the value of the new data status is transferred from the message buffer into the CANIFnMCTL register. If WRNRD is clear and this bit is set, the new data status is cleared in the message buffer. Note that the value of this bit that is transferred to the CANIFnMCTL register always reflects the status of the bits before clearing. 1 DATAA R/W 0 Access Data Byte 0 to 3 When WRNRD = 1: 0: Data bytes 0-3 are unchanged. 1: Transfer data bytes 0-3 in message object to CANIFnDA1 and CANIFnDA2. When WRNRD = 0: 0: Data bytes 0-3 are unchanged. 1: Transfer data bytes 0-3 in CANIFnDA1 and CANIFnDA2 to the message object. 0 DATAB R/W 0 Access Data Byte 4 to 7 When WRNRD = 1: 0: Data bytes 4-7 are unchanged. 1: Transfer data bytes 4-7 in message object to CANIFnDB1 and CANIFnDB2. When WRNRD = 0: 0: Data bytes 4-7 are unchanged. 1: Transfer data bytes 4-7 in CANIFnDB1 and CANIFnDB2 to the message object. 646 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 The mask information provided in this register accompanies the data (CANIFnDAn), arbitration information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance filtering. Additional mask information is contained in the CANIFnMSK2 register. CAN IF1 Mask 1 (CANIF1MSK1) CAN0 base: 0x4004.0000 Offset 0x028 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset MSK Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MSK R/W 0xFFFF Identifier Mask When using a 29-bit identifier, these bits are used for bits [15:0] of the ID. The MSK field in the CANIFnMSK2 register are used for bits [28:16] of the ID. When using an 11-bit identifier, these bits are ignored. 0: The corresponding identifier field (ID) in the message object cannot inhibit the match in acceptance filtering. 1: The corresponding identifier field (ID) is used for acceptance filtering. July 17, 2014 647 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C This register holds extended mask information that accompanies the CANIFnMSK1 register. CAN IF1 Mask 2 (CANIF1MSK2) CAN0 base: 0x4004.0000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 MXTD MDIR reserved R/W 1 R/W 1 RO 1 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset Type Reset MSK Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 MXTD R/W 0x1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Mask Extended Identifier 0: The extended identifier bit (XTD in the CANIFnARB2 register) has no effect on the acceptance filtering. 1: The extended identifier bit XTD is used for acceptance filtering. 14 MDIR R/W 0x1 Mask Message Direction 0: The message direction bit (DIR in the CANIFnARB2 register) has no effect for acceptance filtering. 1: The message direction bit DIR is used for acceptance filtering. 13 reserved RO 0x1 12:0 MSK R/W 0xFF Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Identifier Mask When using a 29-bit identifier, these bits are used for bits [28:16] of the ID. The MSK field in the CANIFnMSK1 register are used for bits [15:0] of the ID. When using an 11-bit identifier, MSK[12:2] are used for bits [10:0] of the ID. 0: The corresponding identifier field (ID) in the message object cannot inhibit the match in acceptance filtering. 1: The corresponding identifier field (ID) is used for acceptance filtering. 648 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 These registers hold the identifiers for acceptance filtering. CAN IF1 Arbitration 1 (CANIF1ARB1) CAN0 base: 0x4004.0000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset ID Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 ID R/W 0x0000 Message Identifier This bit field is used with the ID field in the CANIFnARB2 register to create the message identifier. When using a 29-bit identifier, bits 15:0 of the CANIFnARB1 register are [15:0] of the ID, while bits 12:0 of the CANIFnARB2 register are [28:16] of the ID. When using an 11-bit identifier, these bits are not used. July 17, 2014 649 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 These registers hold information for acceptance filtering. CAN IF1 Arbitration 2 (CANIF1ARB2) CAN0 base: 0x4004.0000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 MSGVAL XTD DIR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset ID Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 MSGVAL R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Message Valid 0: The message object is ignored by the message handler. 1: The message object is configured and ready to be considered by the message handler within the CAN controller. All unused message objects should have this bit cleared during initialization and before clearing the INIT bit in the CANCTL register. The MSGVAL bit must also be cleared before any of the following bits are modified or if the message object is no longer required: the ID fields in the CANIFnARBn registers, the XTD and DIR bits in the CANIFnARB2 register, or the DLC field in the CANIFnMCTL register. 14 XTD R/W 0 Extended Identifier 0: An 11-bit Standard Identifier is used for this message object. 1: A 29-bit Extended Identifier is used for this message object. 13 DIR R/W 0 Message Direction 0: Receive. When the TXRQST bit in the CANIFnMCTL register is set, a remote frame with the identifier of this message object is received. On reception of a data frame with matching identifier, that message is stored in this message object. 1: Transmit. When the TXRQST bit in the CANIFnMCTL register is set, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TXRQST bit of this message object is set (if RMTEN=1). 650 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 12:0 ID R/W 0x000 Message Identifier This bit field is used with the ID field in the CANIFnARB2 register to create the message identifier. When using a 29-bit identifier, ID[15:0] of the CANIFnARB1 register are [15:0] of the ID, while these bits, ID[12:0], are [28:16] of the ID. When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of the ID. The ID field in the CANIFnARB1 register is ignored. July 17, 2014 651 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 This register holds the control information associated with the message object to be sent to the Message RAM. CAN IF1 Message Control (CANIF1MCTL) CAN0 base: 0x4004.0000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 UMASK TXIE RXIE R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RMTEN TXRQST EOB R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset NEWDAT MSGLST INTPND Type Reset R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 NEWDAT R/W 0 reserved RO 0 RO 0 DLC Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. New Data 0: No new data has been written into the data portion of this message object by the message handler since the last time this flag was cleared by the CPU. 1: The message handler or the CPU has written new data into the data portion of this message object. 14 MSGLST R/W 0 Message Lost 0 : No message was lost since the last time this bit was cleared by the CPU. 1: The message handler stored a new message into this object when NEWDAT was set; the CPU has lost a message. This bit is only valid for message objects when the DIR bit in the CANIFnARB2 register clear (receive). 13 INTPND R/W 0 Interrupt Pending 0: This message object is not the source of an interrupt. 1: This message object is the source of an interrupt. The interrupt identifier in the CANINT register points to this message object if there is not another interrupt source with a higher priority. 12 UMASK R/W 0 Use Acceptance Mask 0: Mask ignored. 1: Use mask (MSK, MXTD, and MDIR bits in the CANIFnMSKn registers) for acceptance filtering. 652 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 11 TXIE R/W 0 Description Transmit Interrupt Enable 0: The INTPND bit in the CANIFnMCTL register is unchanged after a successful transmission of a frame. 1: The INTPND bit in the CANIFnMCTL register is set after a successful transmission of a frame. 10 RXIE R/W 0 Receive Interrupt Enable 0: The INTPND bit in the CANIFnMCTL register is unchanged after a successful reception of a frame. 1: The INTPND bit in the CANIFnMCTL register is set after a successful reception of a frame. 9 RMTEN R/W 0 Remote Enable 0: At the reception of a remote frame, the TXRQST bit in the CANIFnMCTL register is left unchanged. 1: At the reception of a remote frame, the TXRQST bit in the CANIFnMCTL register is set. 8 TXRQST R/W 0 Transmit Request 0: This message object is not waiting for transmission. 1: The transmission of this message object is requested and is not yet done. 7 EOB R/W 0 End of Buffer 0: Message object belongs to a FIFO Buffer and is not the last message object of that FIFO Buffer. 1: Single message object or last message object of a FIFO Buffer. This bit is used to concatenate two or more message objects (up to 32) to build a FIFO buffer. For a single message object (thus not belonging to a FIFO buffer), this bit must be set. 6:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 DLC R/W 0x0 Data Length Code Value Description 0x0-0x8 Specifies the number of bytes in the data frame. 0x9-0xF Defaults to a data frame with 8 bytes. The DLC field in the CANIFnMCTL register of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it writes DLC to the value given by the received message. July 17, 2014 653 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 These registers contain the data to be sent or that has been received. In a CAN data frame, data byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte is transmitted first. CAN IF1 Data A1 (CANIF1DA1) CAN0 base: 0x4004.0000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset DATA Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 DATA R/W 0x0000 Data The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2 data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2 data bytes 7 and 6. 654 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By reading out these bits, the CPU can check which message object has a transmission request pending. The TXRQST bit of a specific message object can be changed by three sources: (1) the CPU via the CANIFnMCTL register, (2) the message handler state machine after the reception of a remote frame, or (3) the message handler state machine after a successful transmission. The CANTXRQ1 register contains the TXRQST bits of the first 16 message objects in the message RAM; the CANTXRQ2 register contains the TXRQST bits of the second 16 message objects. CAN Transmission Request 1 (CANTXRQ1) CAN0 base: 0x4004.0000 Offset 0x100 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 TXRQST Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TXRQST RO 0x0000 Transmission Request Bits 0: The corresponding message object is not waiting for transmission. 1: The transmission of the corresponding message object is requested and is not yet done. July 17, 2014 655 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By reading these bits, the CPU can check which message object has its data portion updated. The NEWDAT bit of a specific message object can be changed by three sources: (1) the CPU via the CANIFnMCTL register, (2) the message handler state machine after the reception of a data frame, or (3) the message handler state machine after a successful transmission. The CANNWDA1 register contains the NEWDAT bits of the first 16 message objects in the message RAM; the CANNWDA2 register contains the NEWDAT bits of the second 16 message objects. CAN New Data 1 (CANNWDA1) CAN0 base: 0x4004.0000 Offset 0x120 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 NEWDAT Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 NEWDAT RO 0x0000 New Data Bits 0: No new data has been written into the data portion of the corresponding message object by the message handler since the last time this flag was cleared by the CPU. 1: The message handler or the CPU has written new data into the data portion of the corresponding message object. 656 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects. By reading these bits, the CPU can check which message object has an interrupt pending. The INTPND bit of a specific message object can be changed through two sources: (1) the CPU via the CANIFnMCTL register, or (2) the message handler state machine after the reception or transmission of a frame. This field is also encoded in the CANINT register. The CANMSG1INT register contains the INTPND bits of the first 16 message objects in the message RAM; the CANMSG2INT register contains the INTPND bits of the second 16 message objects. CAN Message 1 Interrupt Pending (CANMSG1INT) CAN0 base: 0x4004.0000 Offset 0x140 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset INTPND Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 INTPND RO 0x0000 Interrupt Pending Bits 0: The corresponding message object is not the source of an interrupt. 1: The corresponding message object is the source of an interrupt. July 17, 2014 657 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects. By reading these bits, the CPU can check which message object is valid. The message value of a specific message object can be changed with the CANIFnMCTL register. The CANMSG1VAL register contains the MSGVAL bits of the first 16 message objects in the message RAM; the CANMSG2VAL register contains the MSGVAL bits of the second 16 message objects in the message RAM. CAN Message 1 Valid (CANMSG1VAL) CAN0 base: 0x4004.0000 Offset 0x160 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 MSGVAL Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MSGVAL RO 0x0000 Message Valid Bits 0: The corresponding message object is not configured and is ignored by the message handler. 1: The corresponding message object is configured and should be considered by the message handler. 658 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 17 Universal Serial Bus (USB) Controller ® The Stellaris USB controller operates as a full-speed or low-speed function controller during point-to-point or multipoint (hub) communications with USB functions. The controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. Eight endpoints including two hard-wired for control transfers (one endpoint for IN and one endpoint for OUT) plus six endpoints defined by firmware along with a dynamic sizable FIFO support multiple packet queueing. µDMA access to the FIFO allows minimal interference from system software. The controller has the capability to access an external power regulator through a power enable pad output (USB0EPEN) and power fault detect pad input (USB0PFLT). The Stellaris USB module has the following features: ■ Standards-based ■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation ■ USB Device or Host mode ■ Integrated PHY ■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous ■ 8 endpoints – 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint – 3 configurable IN endpoints and 3 configurable OUT endpoints ■ 2 KB dedicated endpoint memory – Direct memory access (DMA) – One endpoint may be defined for double-buffered 1023-byte isochronous packet size July 17, 2014 659 Texas Instruments-Production Data Universal Serial Bus (USB) Controller 17.1 Block Diagram Figure 17-1. USB Module Block Diagram DMA Requests Endpoint Control Transmit EP0 – 7 Control Receive CPU Interface Host Transaction Scheduler Combine Endpoints Interrupt Control EP Reg. Decoder Packet Encode/Decode UTM Synchronization USB PHY FIFO RAM Controller Rx Rx Buff Buff Packet Encode Data Sync Tx Buff Packet Decode USB FS/LS PHY Cycle Control USB Data Lines D+ and D- 17.2 Common Regs Cycle Control AHB bus – Slave mode Tx Buff Timers CRC Gen/Check Interrupts FIFO Decoder Signal Description Some USB controller signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for these USB signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 371) should be set to choose the USB function. The USB0VBUS and USB0ID signals are configured by clearing the appropriate DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 351. The remaining signals (with the word "fixed" in the Pin Assignment column) have a fixed pin assignment and function. Table 17-1. USB Signals (64LQFP) a Pin Name Pin Number Pin Type Buffer Type Description USB0DM 45 I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP 46 I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. USB0EPEN 14 O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0PFLT 15 I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. USB0RBIAS 48 O Analog 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 17.3 Functional Description Note: A 9.1-kΩ resistor should be connected between the USB0RBIAS and ground. The 9.1-kΩ resistor should have a 1% tolerance and should be located in close proximity to the 660 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller USB0RBIAS pin. Power dissipation in the resistor is low, so a chip resistor of any geometry may be used. The Stellaris USB controller provides the ability for the controller to choose between Host controller and Device controller functionality. The USB controller requires both A and B connectors in the system to provide Host or Device connectivity. If both connectors are present, the controller provides external signals to enable or disable power to the USB0VBUS pin on the USB connector when not in use. The controller can only be used in Host or Device mode and cannot be used in both modes simultaneously. However, the controller can be manually switched at run time if the system requires both Host and Device functionality. Note: 17.3.1 When USB is used in the system, the minimum system frequency is 30 MHz. Operation as a Device This section describes the Stellaris USB controller's actions when it is being used as a USB Device. Before the USB controller's operating mode is changed from Device to Host or Host to Device, software must reset the USB controller by setting the USB0 bit in the Software Reset Control 2 (SRCR2) register (see page 237). IN endpoints, OUT endpoints, entry into and exit from SUSPEND mode, and recognition of Start of Frame (SOF) are all described. When in Device mode, IN transactions are controlled by an endpoint’s transmit interface and use the transmit endpoint registers for the given endpoint. OUT transactions are handled with an endpoint's receive interface and use the receive endpoint registers for the given endpoint. When configuring the size of the FIFOs for endpoints, take into account the maximum packet size for an endpoint. ■ Bulk. Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used (described further in the following section). ■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used. ■ Isochronous. Isochronous endpoints are more flexible and can be up to 1023 bytes. ■ Control. It is also possible to specify a separate control endpoint for a USB Device. However, in most cases the USB Device should use the dedicated control endpoint on the USB controller’s endpoint 0. 17.3.1.1 Endpoints When operating as a Device, the USB controller provides two dedicated control endpoints (IN and OUT) and six configurable endpoints (3 IN and 3 OUT) that can be used for communications with a Host controller. The endpoint number and direction associated with an endpoint is directly related to its register designation. For example, when the Host is transmitting to endpoint 1, all configuration and data is in the endpoint 1 transmit register interface. Endpoint 0 is a dedicated control endpoint used for all control transactions to endpoint 0 during enumeration or when any other control requests are made to endpoint 0. Endpoint 0 uses the first 64 bytes of the USB controller's FIFO RAM as a shared memory for both IN and OUT transactions. The remaining six endpoints can be configured as control, bulk, interrupt, or isochronous endpoints. They should be treated as three configurable IN and three configurable OUT endpoints. The endpoint pairs are not required to have the same type for their IN and OUT endpoint configuration. For example, the OUT portion of an endpoint pair could be a bulk endpoint, while the IN portion of that July 17, 2014 661 Texas Instruments-Production Data Universal Serial Bus (USB) Controller endpoint pair could be an interrupt endpoint. The address and size of the FIFOs attached to each endpoint can be modified to fit the application's needs. 17.3.1.2 IN Transactions as a Device When operating as a USB Device, data for IN transactions is handled through the FIFOs attached to the transmit endpoints. The sizes of the FIFOs for the three configurable IN endpoints are determined by the USB Transmit FIFO Start Address (USBTXFIFOADD) register. The maximum size of a data packet that may be placed in a transmit endpoint’s FIFO for transmission is programmable and is determined by the value written to the USB Maximum Transmit Data Endpoint n (USBTXMAXPn) register for that endpoint. The endpoint’s FIFO can also be configured to use double-packet or single-packet buffering. When double-packet buffering is enabled, two data packets can be buffered in the FIFO, which also requires that the FIFO is at least two packets in size. When double-packet buffering is disabled, only one packet can be buffered, even if the packet size is less than half the FIFO size. Note: The maximum packet size set for any endpoint must not exceed the FIFO size. The USBTXMAXPn register should not be written to while data is in the FIFO as unexpected results may occur. Single-Packet Buffering If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint (as set in the USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) register), only one packet can be buffered in the FIFO and single-packet buffering is required. When each packet is completely loaded into the transmit FIFO, the TXRDY bit in the USB Transmit Control and Status Endpoint n Low (USBTXCSRLn) register must be set. If the AUTOSET bit in the USB Transmit Control and Status Endpoint n High (USBTXCSRHn) register is set, the TXRDY bit is automatically set when a maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, the TXRDY bit must be set manually. When the TXRDY bit is set, either manually or automatically, the packet is ready to be sent. When the packet has been successfully sent, both TXRDY and FIFONE are cleared, and the appropriate transmit endpoint interrupt signaled. At this point, the next packet can be loaded into the FIFO. Double-Packet Buffering If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint, two packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is loaded into the transmit FIFO, the TXRDY bit in the USBTXCSRLn register must be set. If the AUTOSET bit in the USBTXCSRHn register is set, the TXRDY bit is automatically set when a maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, TXRDY must be set manually. When the TXRDY bit is set, either manually or automatically, the packet is ready to be sent. After the first packet is loaded, TXRDY is immediately cleared and an interrupt is generated. A second packet can now be loaded into the transmit FIFO and TXRDY set again (either manually or automatically if the packet is the maximum size). At this point, both packets are ready to be sent. After each packet has been successfully sent, TXRDY is automatically cleared and the appropriate transmit endpoint interrupt signaled to indicate that another packet can now be loaded into the transmit FIFO. The state of the FIFONE bit in the USBTXCSRLn register at this point indicates how many packets may be loaded. If the FIFONE bit is set, then another packet is in the FIFO and only one more packet can be loaded. If the FIFONE bit is clear, then no packets are in the FIFO and two more packets can be loaded. Note: Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS) register. This bit is set by default, so it must be cleared to enable double-packet buffering. 662 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 17.3.1.3 OUT Transactions as a Device When in Device mode, OUT transactions are handled through the USB controller receive FIFOs. The sizes of the receive FIFOs for the three configurable OUT endpoints are determined by the USB Receive FIFO Start Address (USBRXFIFOADD) register. The maximum amount of data received by an endpoint in any packet is determined by the value written to the USB Maximum Receive Data Endpoint n (USBRXMAXPn) register for that endpoint. When double-packet buffering is enabled, two data packets can be buffered in the FIFO. When double-packet buffering is disabled, only one packet can be buffered even if the packet is less than half the FIFO size. Note: In all cases, the maximum packet size must not exceed the FIFO size. Single-Packet Buffering If the size of the receive endpoint FIFO is less than twice the maximum packet size for an endpoint, only one data packet can be buffered in the FIFO and single-packet buffering is required. When a packet is received and placed in the receive FIFO, the RXRDY and FULL bits in the USB Receive Control and Status Endpoint n Low (USBRXCSRLn) register are set and the appropriate receive endpoint is signaled, indicating that a packet can now be unloaded from the FIFO. After the packet has been unloaded, the RXRDY bit must be cleared in order to allow further packets to be received. This action also generates the acknowledge signaling to the Host controller. If the AUTOCL bit in the USB Receive Control and Status Endpoint n High (USBRXCSRHn) register is set and a maximum-sized packet is unloaded from the FIFO, the RXRDY and FULL bits are cleared automatically. For packet sizes less than the maximum, RXRDY must be cleared manually. Double-Packet Buffering If the size of the receive endpoint FIFO is at least twice the maximum packet size for the endpoint, two data packets can be buffered and double-packet buffering can be used. When the first packet is received and loaded into the receive FIFO, the RXRDY bit in the USBRXCSRLn register is set and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be unloaded from the FIFO. Note: The FULL bit in USBRXCSRLn is not set when the first packet is received. It is only set if a second packet is received and loaded into the receive FIFO. After each packet has been unloaded, the RXRDY bit must be cleared to allow further packets to be received. If the AUTOCL bit in the USBRXCSRHn register is set and a maximum-sized packet is unloaded from the FIFO, the RXRDY bit is cleared automatically. For packet sizes less than the maximum, RXRDY must be cleared manually. If the FULL bit is set when RXRDY is cleared, the USB controller first clears the FULL bit, then sets RXRDY again to indicate that there is another packet waiting in the FIFO to be unloaded. Note: 17.3.1.4 Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) register. This bit is set by default, so it must be cleared to enable double-packet buffering. Scheduling The Device has no control over the scheduling of transactions as scheduling is determined by the Host controller. The Stellaris USB controller can set up a transaction at any time. The USB controller waits for the request from the Host controller and generates an interrupt when the transaction is complete or if it was terminated due to some error. If the Host controller makes a request and the Device controller is not ready, the USB controller sends a busy response (NAK) to all requests until it is ready. July 17, 2014 663 Texas Instruments-Production Data Universal Serial Bus (USB) Controller 17.3.1.5 Additional Actions The USB controller responds automatically to certain conditions on the USB bus or actions by the Host controller such as when the USB controller automatically stalls a control transfer or unexpected zero length OUT data packets. Stalled Control Transfer The USB controller automatically issues a STALL handshake to a control transfer under the following conditions: 1. The Host sends more data during an OUT data phase of a control transfer than was specified in the Device request during the SETUP phase. This condition is detected by the USB controller when the Host sends an OUT token (instead of an IN token) after the last OUT packet has been unloaded and the DATAEND bit in the USB Control and Status Endpoint 0 Low (USBCSRL0) register has been set. 2. The Host requests more data during an IN data phase of a control transfer than was specified in the Device request during the SETUP phase. This condition is detected by the USB controller when the Host sends an IN token (instead of an OUT token) after the CPU has cleared TXRDY and set DATAEND in response to the ACK issued by the Host to what should have been the last packet. 3. The Host sends more than USBRXMAXPn bytes of data with an OUT data token. 4. The Host sends more than a zero length data packet for the OUT STATUS phase. Zero Length OUT Data Packets A zero-length OUT data packet is used to indicate the end of a control transfer. In normal operation, such packets should only be received after the entire length of the Device request has been transferred. However, if the Host sends a zero-length OUT data packet before the entire length of Device request has been transferred, it is signaling the premature end of the transfer. In this case, the USB controller automatically flushes any IN token ready for the data phase from the FIFO and sets the DATAEND bit in the USBCSRL0 register. Setting the Device Address When a Host is attempting to enumerate the USB Device, it requests that the Device change its address from zero to some other value. The address is changed by writing the value that the Host requested to the USB Device Functional Address (USBFADDR) register. However, care should be taken when writing to USBFADDR to avoid changing the address before the transaction is complete. This register should only be set after the SET_ADDRESS command is complete. Like all control transactions, the transaction is only complete after the Device has left the STATUS phase. In the case of a SET_ADDRESS command, the transaction is completed by responding to the IN request from the Host with a zero-byte packet. Once the Device has responded to the IN request, the USBFADDR register should be programmed to the new value as soon as possible to avoid missing any new commands sent to the new address. Note: If the USBFADDR register is set to the new value as soon as the Device receives the OUT transaction with the SET_ADDRESS command in the packet, it changes the address during the control transfer. In this case, the Device does not receive the IN request that allows the USB transaction to exit the STATUS phase of the control transfer because it is sent to the 664 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller old address. As a result, the Host does not get a response to the IN request, and the Host fails to enumerate the Device. 17.3.1.6 Device Mode SUSPEND When no activity has occurred on the USB bus for 3 ms, the USB controller automatically enters SUSPEND mode. If the SUSPEND interrupt has been enabled in the USB Interrupt Enable (USBIE) register, an interrupt is generated at this time. When in SUSPEND mode, the PHY also goes into SUSPEND mode. When RESUME signaling is detected, the USB controller exits SUSPEND mode and takes the PHY out of SUSPEND. If the RESUME interrupt is enabled, an interrupt is generated. The USB controller can also be forced to exit SUSPEND mode by setting the RESUME bit in the USB Power (USBPOWER) register. When this bit is set, the USB controller exits SUSPEND mode and drives RESUME signaling onto the bus. The RESUME bit must be cleared after 10 ms (a maximum of 15 ms) to end RESUME signaling. To meet USB power requirements, the controller can be put into Deep Sleep mode which keeps the controller in a static state. The USB controller is not able to Hibernate because all the internal states are lost as a result. 17.3.1.7 Start-of-Frame When the USB controller is operating in Device mode, it receives a Start-Of-Frame (SOF) packet from the Host once every millisecond. When the SOF packet is received, the 11-bit frame number contained in the packet is written into the USB Frame Value (USBFRAME) register, and an SOF interrupt is also signaled and can be handled by the application. Once the USB controller has started to receive SOF packets, it expects one every millisecond. If no SOF packet is received after 1.00358 ms, the packet is assumed to have been lost, and the USBFRAME register is not updated. The USB controller continues and resynchronizes these pulses to the received SOF packets when these packets are successfully received again. 17.3.1.8 USB RESET When the USB controller is in Device mode and a RESET condition is detected on the USB bus, the USB controller automatically performs the following actions: ■ Clears the USBFADDR register. ■ Clears the USB Endpoint Index (USBEPIDX) register. ■ Flushes all endpoint FIFOs. ■ Clears all control/status registers. ■ Enables all endpoint interrupts. ■ Generates a RESET interrupt. When the application software driving the USB controller receives a RESET interrupt, any open pipes are closed and the USB controller waits for bus enumeration to begin. 17.3.1.9 Connect/Disconnect The USB controller connection to the USB bus is handled by software. The USB PHY can be switched between normal mode and non-driving mode by setting or clearing the SOFTCONN bit of the USBPOWER register. When the SOFTCONN bit is set, the PHY is placed in its normal mode, July 17, 2014 665 Texas Instruments-Production Data Universal Serial Bus (USB) Controller and the USB0DP/USB0DM lines of the USB bus are enabled. At the same time, the USB controller is placed into a state, in which it does not respond to any USB signaling except a USB RESET. When the SOFTCONN bit is cleared, the PHY is put into non-driving mode, USB0DP and USB0DM are tristated, and the USB controller appears to other devices on the USB bus as if it has been disconnected. The non-driving mode is the default so the USB controller appears disconnected until the SOFTCONN bit has been set. The application software can then choose when to set the PHY into its normal mode. Systems with a lengthy initialization procedure may use this to ensure that initialization is complete, and the system is ready to perform enumeration before connecting to the USB bus. Once the SOFTCONN bit has been set, the USB controller can be disconnected by clearing this bit. When the USB controller is acting as a self-powered Device, a GPIO input or analog comparator input must be connected to VBUS and configured to generate an interrupt when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal. Note: 17.3.2 The USB controller does not generate an interrupt when the Device is connected to the Host. However, an interrupt is generated when the Host terminates a session. Operation as a Host When the Stellaris USB controller is operating in Host mode, it can either be used for point-to-point communications with another USB device or, when attached to a hub, for communication with multiple devices. Before the USB controller's operating mode is changed from Host to Device or Device to Host, software must reset the USB controller by setting the USB0 bit in the Software Reset Control 2 (SRCR2) register (see page 237). Full-speed and low-speed USB devices are supported, both for point-to-point communication and for operation through a hub. The USB controller automatically carries out the necessary transaction translation needed to allow a low-speed or full-speed device to be used with a USB 2.0 hub. Control, bulk, isochronous, and interrupt transactions are supported. This section describes the USB controller's actions when it is being used as a USB Host. Configuration of IN endpoints, OUT endpoints, entry into and exit from SUSPEND mode, and RESET are all described. When in Host mode, IN transactions are controlled by an endpoint’s receive interface. All IN transactions use the receive endpoint registers and all OUT endpoints use the transmit endpoint registers for a given endpoint. As in Device mode, the FIFOs for endpoints should take into account the maximum packet size for an endpoint. ■ Bulk. Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used (described further in the following section). ■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used. ■ Isochronous. Isochronous endpoints are more flexible and can be up to 1023 bytes. ■ Control. It is also possible to specify a separate control endpoint to communicate with a Device. However, in most cases the USB controller should use the dedicated control endpoint to communicate with a Device’s endpoint 0. 17.3.2.1 Endpoints The endpoint registers are used to control the USB endpoint interfaces which communicate with Device(s) that are connected. The endpoints consist of a dedicated control IN endpoint, a dedicated control OUT endpoint, three configurable OUT endpoints, and three configurable IN endpoints. 666 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller The dedicated control interface can only be used for control transactions to endpoint 0 of Devices. These control transactions are used during enumeration or other control functions that communicate using endpoint 0 of Devices. This control endpoint shares the first 64 bytes of the USB controller’s FIFO RAM for IN and OUT transactions. The remaining IN and OUT interfaces can be configured to communicate with control, bulk, interrupt, or isochronous Device endpoints. These USB interfaces can be used to simultaneously schedule as many as three independent OUT and three independent IN transactions to any endpoints on any Device. The IN and OUT controls are paired in three sets of registers. However, they can be configured to communicate with different types of endpoints and different endpoints on Devices. For example, the first pair of endpoint controls can be split so that the OUT portion is communicating with a Device’s bulk OUT endpoint 1, while the IN portion is communicating with a Device’s interrupt IN endpoint 2. Before accessing any Device, whether for point-to-point communications or for communications via a hub, the relevant USB Receive Functional Address Endpoint n (USBRXFUNCADDRn) or USB Transmit Functional Address Endpoint n (USBTXFUNCADDRn) registers must be set for each receive or transmit endpoint to record the address of the Device being accessed. The USB controller also supports connections to Devices through a USB hub by providing a register that specifies the hub address and port of each USB transfer. The FIFO address and size are customizable and can be specified for each USB IN and OUT transfer. Customization includes allowing one FIFO per transaction, sharing a FIFO across transactions, and allowing for double-buffered FIFOs. 17.3.2.2 IN Transactions as a Host IN transactions are handled in a similar manner to the way in which OUT transactions are handled when the USB controller is in Device mode except that the transaction first must be initiated by setting the REQPKT bit in the USBCSRL0 register, indicating to the transaction scheduler that there is an active transaction on this endpoint. The transaction scheduler then sends an IN token to the target Device. When the packet is received and placed in the receive FIFO, the RXRDY bit in the USBCSRL0 register is set, and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be unloaded from the FIFO. When the packet has been unloaded, RXRDY must be cleared. The AUTOCL bit in the USBRXCSRHn register can be used to have RXRDY automatically cleared when a maximum-sized packet has been unloaded from the FIFO. The AUTORQ bit in USBRXCSRHn causes the REQPKT bit to be automatically set when the RXRDY bit is cleared. The AUTOCL and AUTORQ bits can be used with µDMA accesses to perform complete bulk transfers without main processor intervention. When the RXRDY bit is cleared, the controller sends an acknowledge to the Device. When there is a known number of packets to be transferred, the USB Request Packet Count in Block Transfer Endpoint n (USBRQPKTCOUNTn) register associated with the endpoint should be configured to the number of packets to be transferred. The USB controller decrements the value in the USBRQPKTCOUNTn register following each request. When the USBRQPKTCOUNTn value decrements to 0, the AUTORQ bit is cleared to prevent any further transactions being attempted. For cases where the size of the transfer is unknown, USBRQPKTCOUNTn should be cleared. AUTORQ then remains set until cleared by the reception of a short packet (that is, less than the MAXLOAD value in the USBRXMAXPn register) such as may occur at the end of a bulk transfer. If the Device responds to a bulk or interrupt IN token with a NAK, the USB Host controller keeps retrying the transaction until any NAK Limit that has been set has been reached. If the target Device responds with a STALL, however, the USB Host controller does not retry the transaction but sets the STALLED bit in the USBCSRL0 register. If the target Device does not respond to the IN token within the required time, or the packet contained a CRC or bit-stuff error, the USB Host controller July 17, 2014 667 Texas Instruments-Production Data Universal Serial Bus (USB) Controller retries the transaction. If after three attempts the target Device has still not responded, the USB Host controller clears the REQPKT bit and sets the ERROR bit in the USBCSRL0 register. 17.3.2.3 OUT Transactions as a Host OUT transactions are handled in a similar manner to the way in which IN transactions are handled when the USB controller is in Device mode. The TXRDY bit in the USBTXCSRLn register must be set as each packet is loaded into the transmit FIFO. Again, setting the AUTOSET bit in the USBTXCSRHn register automatically sets TXRDY when a maximum-sized packet has been loaded into the FIFO. Furthermore, AUTOSET can be used with the µDMA controller to perform complete bulk transfers without software intervention. If the target Device responds to the OUT token with a NAK, the USB Host controller keeps retrying the transaction until the NAK Limit that has been set has been reached. However, if the target Device responds with a STALL, the USB controller does not retry the transaction but interrupts the main processor by setting the STALLED bit in the USBTXCSRLn register. If the target Device does not respond to the OUT token within the required time, or the packet contained a CRC or bit-stuff error, the USB Host controller retries the transaction. If after three attempts the target Device has still not responded, the USB controller flushes the FIFO and sets the ERROR bit in the USBTXCSRLn register. 17.3.2.4 Transaction Scheduling Scheduling of transactions is handled automatically by the USB Host controller. The Host controller allows configuration of the endpoint communication scheduling based on the type of endpoint transaction. Interrupt transactions can be scheduled to occur in the range of every frame to every 255 frames in 1 frame increments. Bulk endpoints do not allow scheduling parameters, but do allow for a NAK timeout in the event an endpoint on a Device is not responding. Isochronous endpoints can be scheduled from every frame to every 216 frames, in powers of 2. The USB controller maintains a frame counter. If the target Device is a full-speed device, the USB controller automatically sends an SOF packet at the start of each frame and increments the frame counter. If the target Device is a low-speed device, a K state is transmitted on the bus to act as a keep-alive to stop the low-speed device from going into SUSPEND mode. After the SOF packet has been transmitted, the USB Host controller cycles through all the configured endpoints looking for active transactions. An active transaction is defined as a receive endpoint for which the REQPKT bit is set or a transmit endpoint for which the TXRDY bit and/or the FIFONE bit is set. An isochronous or interrupt transaction is started if the transaction is found on the first scheduler cycle of a frame and if the interval counter for that endpoint has counted down to zero. As a result, only one interrupt or isochronous transaction occurs per endpoint every n frames, where n is the interval set via the USB Host Transmit Interval Endpoint n (USBTXINTERVALn) or USB Host Receive Interval Endpoint n (USBRXINTERVALn) register for that endpoint. An active bulk transaction starts immediately, provided sufficient time is left in the frame to complete the transaction before the next SOF packet is due. If the transaction must be retried (for example, because a NAK was received or the target Device did not respond), then the transaction is not retried until the transaction scheduler has first checked all the other endpoints for active transactions. This process ensures that an endpoint that is sending a lot of NAKs does not block other transactions on the bus. The controller also allows the user to specify a limit to the length of time for NAKs to be received from a target Device before the endpoint times out. 668 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 17.3.2.5 USB Hubs The following setup requirements apply to the USB Host controller only if it is used with a USB hub. When a full- or low-speed Device is connected to the USB controller via a USB 2.0 hub, details of the hub address and the hub port also must be recorded in the corresponding USB Receive Hub Address Endpoint n (USBRXHUBADDRn) and USB Receive Hub Port Endpoint n (USBRXHUBPORTn) or the USB Transmit Hub Address Endpoint n (USBTXHUBADDRn) and USB Transmit Hub Port Endpoint n (USBTXHUBPORTn) registers. In addition, the speed at which the Device operates (full or low) must be recorded in the USB Type Endpoint 0 (USBTYPE0) (endpoint 0), USB Host Configure Transmit Type Endpoint n (USBTXTYPEn), or USB Host Configure Receive Type Endpoint n (USBRXTYPEn) registers for each endpoint that is accessed by the Device. For hub communications, the settings in these registers record the current allocation of the endpoints to the attached USB Devices. To maximize the number of Devices supported, the USB Host controller allows this allocation to be changed dynamically by simply updating the address and speed information recorded in these registers. Any changes in the allocation of endpoints to Device functions must be made following the completion of any on-going transactions on the endpoints affected. 17.3.2.6 Babble The USB Host controller does not start a transaction until the bus has been inactive for at least the minimum inter-packet delay. The controller also does not start a transaction unless it can be finished before the end of the frame. If the bus is still active at the end of a frame, then the USB Host controller assumes that the target Device to which it is connected has malfunctioned, and the USB controller suspends all transactions and generates a babble interrupt. 17.3.2.7 Host SUSPEND If the SUSPEND bit in the USBPOWER register is set, the USB Host controller completes the current transaction then stops the transaction scheduler and frame counter. No further transactions are started and no SOF packets are generated. To exit SUSPEND mode, set the RESUME bit and clear the SUSPEND bit. While the RESUME bit is set, the USB Host controller generates RESUME signaling on the bus. After 20 ms, the RESUME bit must be cleared, at which point the frame counter and transaction scheduler start. The Host supports the detection of a remote wake-up. 17.3.2.8 USB RESET If the RESET bit in the USBPOWER register is set, the USB Host controller generates USB RESET signaling on the bus. The RESET bit must be set for at least 20 ms to ensure correct resetting of the target Device. After the CPU has cleared the bit, the USB Host controller starts its frame counter and transaction scheduler. 17.3.2.9 Connect/Disconnect A session is started by setting the SESSION bit in the USB Device Control (USBDEVCTL) register, enabling the USB controller to wait for a Device to be connected. When a Device is detected, a connect interrupt is generated. The speed of the Device that has been connected can be determined by reading the USBDEVCTL register where the FSDEV bit is set for a full-speed Device, and the LSDEV bit is set for a low-speed Device. The USB controller must generate a RESET to the Device, and then the USB Host controller can begin Device enumeration. If the Device is disconnected while a session is in progress, a disconnect interrupt is generated. July 17, 2014 669 Texas Instruments-Production Data Universal Serial Bus (USB) Controller 17.3.3 DMA Operation The USB peripheral provides an interface connected to the μDMA controller. The μDMA operation of the USB is enabled through the USBTXCSRHn and USBRXCSRHn registers, for the TX and RX channels respectively. When μDMA operation is enabled, the USB asserts a μDMA request on the enabled receive or transmit channel when the associated FIFO can transfer data. When either FIFO can transfer data, the burst request for that channel is asserted. The μDMA channel must be configured to operate in Basic mode, and the size of the μDMA transfer must be restricted to whole multiples of the size of the USB FIFO. Both read and write transfers of the USB FIFOs using μDMA must be configured in this manner. For example, if the USB endpoint is configured with a FIFO size of 64 bytes, the μDMA channel can be used to transfer 64 bytes to or from the endpoint FIFO. If the number of bytes to transfer is less than 64, then a programmed I/O method must be used to copy the data to or from the FIFO. If the DMAMOD bit in the USBTXCSRHn/USBRXCSRHn register is clear, an interrupt is generated after every packet is transferred, but the μDMA continues transferring data. If the DMAMOD bit is set, an interrupt is generated only when the entire μDMA transfer is complete. The interrupt occurs on the USB interrupt vector. Therefore, if interrupts are used for USB operation and the μDMA is enabled, the USB interrupt handler must be designed to handle the μDMA completion interrupt. Care must be taken when using the μDMA to unload the receive FIFO as data is read from the receive FIFO in 4 byte chunks regardless of the value off the MAXLOAD field in the USBRXCSRHn register. The RXRDY bit is cleared as follows. Table 17-2. Remainder (MAXLOAD/4) Value Description 0 MAXLOAD = 64 bytes 1 MAXLOAD = 61 bytes 2 MAXLOAD = 62 bytes 3 MAXLOAD = 63 bytes Table 17-3. Actual Bytes Read Value Description 0 MAXLOAD 1 MAXLOAD+3 2 MAXLOAD+2 3 MAXLOAD+1 Table 17-4. Packet Sizes That Clear RXRDY Value Description 0 MAXLOAD, MAXLOAD-1, MAXLOAD-2, MAXLOAD-3 1 MAXLOAD 2 MAXLOAD, MAXLOAD-1 3 MAXLOAD, MAXLOAD-1, MAXLOAD-2 To enable DMA operation for the endpoint receive channel, the DMAEN bit of the USBRXCSRHn register should be set. To enable DMA operation for the endpoint transmit channel, the DMAEN bit of the USBTXCSRHn register must be set. 670 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller See “Micro Direct Memory Access (μDMA)” on page 290 for more details about programming the μDMA controller. 17.4 Initialization and Configuration To use the USB Controller, the peripheral clock must be enabled via the RCGC2 register (see page 229). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2 register in the System Control module (see page 229). To find out which GPIO port to enable, refer to Table 19-3 on page 760. The initial configuration in all cases requires that the processor enable the USB controller and USB controller’s physical layer interface (PHY) before setting any registers. The next step is to enable the USB PLL so that the correct clocking is provided to the PHY. To ensure that voltage is not supplied to the bus incorrectly, the external power control signal, USB0EPEN, should be negated on start up by configuring the USB0EPEN and USB0PFLT pins to be controlled by the USB controller and not exhibit their default GPIO behavior. The USB controller provides a method to set the current operating mode of the USB controller. This register should be written with the desired default mode so that the controller can respond to external USB events. 17.4.1 Pin Configuration When using the Device controller portion of the USB controller in a system that also provides Host functionality, the power to VBUS must be disabled to allow the external Host controller to supply power. Usually, the USB0EPEN signal is used to control the external regulator and should be negated to avoid having two devices driving the USB0VBUS power pin on the USB connector. When the USB controller is acting as a Host, it is in control of two signals that are attached to an external voltage supply that provides power to VBUS. The Host controller uses the USB0EPEN signal to enable or disable power to the USB0VBUS pin on the USB connector. An input pin, USB0PFLT, provides feedback when there has been a power fault on VBUS. The USB0PFLT signal can be configured to either automatically negate the USB0EPEN signal to disable power, and/or it can generate an interrupt to the interrupt controller to allow software to handle the power fault condition. The polarity and actions related to both USB0EPEN and USB0PFLT are fully configurable in the USB controller. The controller also provides interrupts on Device insertion and removal to allow the Host controller code to respond to these external events. 17.4.2 Endpoint Configuration To start communication in Host or Device mode, the endpoint registers must first be configured. In Host mode, this configuration establishes a connection between an endpoint register and an endpoint on a Device. In Device mode, an endpoint must be configured before enumerating to the Host controller. In both cases, the endpoint 0 configuration is limited because it is a fixed-function, fixed-FIFO-size endpoint. In Device and Host modes, the endpoint requires little setup but does require a software-based state machine to progress through the setup, data, and status phases of a standard control transaction. In Device mode, the configuration of the remaining endpoints is done once before enumerating and then only changed if an alternate configuration is selected by the Host controller. In Host mode, the endpoints must be configured to operate as control, bulk, interrupt or isochronous mode. Once the type of endpoint is configured, a FIFO area must be assigned to each endpoint. In the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per transaction. Isochronous endpoints can have packets with up to 1023 bytes per packet. In either July 17, 2014 671 Texas Instruments-Production Data Universal Serial Bus (USB) Controller mode, the maximum packet size for the given endpoint must be set prior to sending or receiving data. Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to each endpoint. The total FIFO RAM available is 4 Kbytes with the first 64 bytes reserved for endpoint 0. The endpoint’s FIFO must be at least as large as the maximum packet size. The FIFO can also be configured as a double-buffered FIFO so that interrupts occur at the end of each packet and allow filling the other half of the FIFO. If operating as a Device, the USB Device controller's soft connect must be enabled when the Device is ready to start communications, indicating to the Host controller that the Device is ready to start the enumeration process. If operating as a Host controller, the Device soft connect must be disabled and power must be provided to VBUS via the USB0EPEN signal. 17.5 Register Map Table 17-5 on page 672 lists the registers. All addresses given are relative to the USB base address of 0x4005.0000. Note that the USB controller clock must be enabled before the registers can be programmed (see page 229). There must be a delay of 3 system clocks after the USB module clock is enabled before any USB module registers are accessed. Table 17-5. Universal Serial Bus (USB) Controller Register Map See page Offset Name Type Reset Description 0x000 USBFADDR R/W 0x00 USB Device Functional Address 676 0x001 USBPOWER R/W 0x20 USB Power 677 0x002 USBTXIS RO 0x0000 USB Transmit Interrupt Status 680 0x004 USBRXIS RO 0x0000 USB Receive Interrupt Status 681 0x006 USBTXIE R/W 0x000F USB Transmit Interrupt Enable 682 0x008 USBRXIE R/W 0x000E USB Receive Interrupt Enable 683 0x00A USBIS RO 0x00 USB General Interrupt Status 684 0x00B USBIE R/W 0x06 USB Interrupt Enable 687 0x00C USBFRAME RO 0x0000 USB Frame Value 690 0x00E USBEPIDX R/W 0x00 USB Endpoint Index 691 0x00F USBTEST R/W 0x00 USB Test Mode 692 0x020 USBFIFO0 R/W 0x0000.0000 USB FIFO Endpoint 0 694 0x024 USBFIFO1 R/W 0x0000.0000 USB FIFO Endpoint 1 694 0x028 USBFIFO2 R/W 0x0000.0000 USB FIFO Endpoint 2 694 0x02C USBFIFO3 R/W 0x0000.0000 USB FIFO Endpoint 3 694 0x060 USBDEVCTL RO 0x80 USB Device Control 695 0x062 USBTXFIFOSZ R/W 0x00 USB Transmit Dynamic FIFO Sizing 696 0x063 USBRXFIFOSZ R/W 0x00 USB Receive Dynamic FIFO Sizing 696 0x064 USBTXFIFOADD R/W 0x0000 USB Transmit FIFO Start Address 697 672 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 17-5. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x066 USBRXFIFOADD R/W 0x0000 USB Receive FIFO Start Address 697 0x07A USBCONTIM R/W 0x5C USB Connect Timing 698 0x07D USBFSEOF R/W 0x77 USB Full-Speed Last Transaction to End of Frame Timing 699 0x07E USBLSEOF R/W 0x72 USB Low-Speed Last Transaction to End of Frame Timing 700 0x080 USBTXFUNCADDR0 R/W 0x00 USB Transmit Functional Address Endpoint 0 701 0x082 USBTXHUBADDR0 R/W 0x00 USB Transmit Hub Address Endpoint 0 702 0x083 USBTXHUBPORT0 R/W 0x00 USB Transmit Hub Port Endpoint 0 703 0x088 USBTXFUNCADDR1 R/W 0x00 USB Transmit Functional Address Endpoint 1 701 0x08A USBTXHUBADDR1 R/W 0x00 USB Transmit Hub Address Endpoint 1 702 0x08B USBTXHUBPORT1 R/W 0x00 USB Transmit Hub Port Endpoint 1 703 0x08C USBRXFUNCADDR1 R/W 0x00 USB Receive Functional Address Endpoint 1 704 0x08E USBRXHUBADDR1 R/W 0x00 USB Receive Hub Address Endpoint 1 705 0x08F USBRXHUBPORT1 R/W 0x00 USB Receive Hub Port Endpoint 1 706 0x090 USBTXFUNCADDR2 R/W 0x00 USB Transmit Functional Address Endpoint 2 701 0x092 USBTXHUBADDR2 R/W 0x00 USB Transmit Hub Address Endpoint 2 702 0x093 USBTXHUBPORT2 R/W 0x00 USB Transmit Hub Port Endpoint 2 703 0x094 USBRXFUNCADDR2 R/W 0x00 USB Receive Functional Address Endpoint 2 704 0x096 USBRXHUBADDR2 R/W 0x00 USB Receive Hub Address Endpoint 2 705 0x097 USBRXHUBPORT2 R/W 0x00 USB Receive Hub Port Endpoint 2 706 0x098 USBTXFUNCADDR3 R/W 0x00 USB Transmit Functional Address Endpoint 3 701 0x09A USBTXHUBADDR3 R/W 0x00 USB Transmit Hub Address Endpoint 3 702 0x09B USBTXHUBPORT3 R/W 0x00 USB Transmit Hub Port Endpoint 3 703 0x09C USBRXFUNCADDR3 R/W 0x00 USB Receive Functional Address Endpoint 3 704 0x09E USBRXHUBADDR3 R/W 0x00 USB Receive Hub Address Endpoint 3 705 0x09F USBRXHUBPORT3 R/W 0x00 USB Receive Hub Port Endpoint 3 706 0x102 USBCSRL0 R/W 0x00 USB Control and Status Endpoint 0 Low 708 0x103 USBCSRH0 R/W 0x00 USB Control and Status Endpoint 0 High 712 0x108 USBCOUNT0 RO 0x00 USB Receive Byte Count Endpoint 0 714 0x10A USBTYPE0 R/W 0x00 USB Type Endpoint 0 715 0x10B USBNAKLMT R/W 0x00 USB NAK Limit 716 0x110 USBTXMAXP1 R/W 0x0000 USB Maximum Transmit Data Endpoint 1 707 July 17, 2014 673 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Table 17-5. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x112 USBTXCSRL1 R/W 0x00 USB Transmit Control and Status Endpoint 1 Low 717 0x113 USBTXCSRH1 R/W 0x00 USB Transmit Control and Status Endpoint 1 High 721 0x114 USBRXMAXP1 R/W 0x0000 USB Maximum Receive Data Endpoint 1 725 0x116 USBRXCSRL1 R/W 0x00 USB Receive Control and Status Endpoint 1 Low 726 0x117 USBRXCSRH1 R/W 0x00 USB Receive Control and Status Endpoint 1 High 731 0x118 USBRXCOUNT1 RO 0x0000 USB Receive Byte Count Endpoint 1 735 0x11A USBTXTYPE1 R/W 0x00 USB Host Transmit Configure Type Endpoint 1 736 0x11B USBTXINTERVAL1 R/W 0x00 USB Host Transmit Interval Endpoint 1 737 0x11C USBRXTYPE1 R/W 0x00 USB Host Configure Receive Type Endpoint 1 738 0x11D USBRXINTERVAL1 R/W 0x00 USB Host Receive Polling Interval Endpoint 1 739 0x120 USBTXMAXP2 R/W 0x0000 USB Maximum Transmit Data Endpoint 2 707 0x122 USBTXCSRL2 R/W 0x00 USB Transmit Control and Status Endpoint 2 Low 717 0x123 USBTXCSRH2 R/W 0x00 USB Transmit Control and Status Endpoint 2 High 721 0x124 USBRXMAXP2 R/W 0x0000 USB Maximum Receive Data Endpoint 2 725 0x126 USBRXCSRL2 R/W 0x00 USB Receive Control and Status Endpoint 2 Low 726 0x127 USBRXCSRH2 R/W 0x00 USB Receive Control and Status Endpoint 2 High 731 0x128 USBRXCOUNT2 RO 0x0000 USB Receive Byte Count Endpoint 2 735 0x12A USBTXTYPE2 R/W 0x00 USB Host Transmit Configure Type Endpoint 2 736 0x12B USBTXINTERVAL2 R/W 0x00 USB Host Transmit Interval Endpoint 2 737 0x12C USBRXTYPE2 R/W 0x00 USB Host Configure Receive Type Endpoint 2 738 0x12D USBRXINTERVAL2 R/W 0x00 USB Host Receive Polling Interval Endpoint 2 739 0x130 USBTXMAXP3 R/W 0x0000 USB Maximum Transmit Data Endpoint 3 707 0x132 USBTXCSRL3 R/W 0x00 USB Transmit Control and Status Endpoint 3 Low 717 0x133 USBTXCSRH3 R/W 0x00 USB Transmit Control and Status Endpoint 3 High 721 0x134 USBRXMAXP3 R/W 0x0000 USB Maximum Receive Data Endpoint 3 725 0x136 USBRXCSRL3 R/W 0x00 USB Receive Control and Status Endpoint 3 Low 726 0x137 USBRXCSRH3 R/W 0x00 USB Receive Control and Status Endpoint 3 High 731 0x138 USBRXCOUNT3 RO 0x0000 USB Receive Byte Count Endpoint 3 735 0x13A USBTXTYPE3 R/W 0x00 USB Host Transmit Configure Type Endpoint 3 736 0x13B USBTXINTERVAL3 R/W 0x00 USB Host Transmit Interval Endpoint 3 737 0x13C USBRXTYPE3 R/W 0x00 USB Host Configure Receive Type Endpoint 3 738 0x13D USBRXINTERVAL3 R/W 0x00 USB Host Receive Polling Interval Endpoint 3 739 674 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 17-5. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x304 USBRQPKTCOUNT1 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 1 740 0x308 USBRQPKTCOUNT2 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 2 740 0x30C USBRQPKTCOUNT3 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 3 740 0x340 USBRXDPKTBUFDIS R/W 0x0000 USB Receive Double Packet Buffer Disable 741 0x342 USBTXDPKTBUFDIS R/W 0x0000 USB Transmit Double Packet Buffer Disable 742 0x400 USBEPC R/W 0x0000.0000 USB External Power Control 743 0x404 USBEPCRIS RO 0x0000.0000 USB External Power Control Raw Interrupt Status 746 0x408 USBEPCIM R/W 0x0000.0000 USB External Power Control Interrupt Mask 747 0x40C USBEPCISC R/W1C 0x0000.0000 USB External Power Control Interrupt Status and Clear 748 0x410 USBDRRIS RO 0x0000.0000 USB Device RESUME Raw Interrupt Status 749 0x414 USBDRIM R/W 0x0000.0000 USB Device RESUME Interrupt Mask 750 0x418 USBDRISC R/W1C 0x0000.0000 USB Device RESUME Interrupt Status and Clear 751 0x41C USBGPCS R/W 0x0000.0000 USB General-Purpose Control and Status 752 17.6 Register Descriptions The LM3S5732 USB controller has Host-or-Device capabilities as specified in the USB0 bit field in the DC6 register (see page 214). Device Host This icon indicates that the register is used in Device mode. Some registers are used for both Host and Device mode and may have different bit definitions depending on the mode. This icon indicates that the register is used in Host mode. Some registers are used for both Host and Device mode and may have different bit definitions depending on the mode. The USB controller is in Device mode upon reset, so the reset values shown for these registers apply to the Device mode definition. July 17, 2014 675 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 1: USB Device Functional Address (USBFADDR), offset 0x000 Device USBFADDR is an 8-bit register that contains the 7-bit address of the Device part of the transaction. When the USB controller is being used in Device mode (the HOST bit in the USBDEVCTL register is clear), this register must be written with the address received through a SET_ADDRESS command, which is then used for decoding the function address in subsequent token packets. Important: See the section called “Setting the Device Address” on page 664 for special considerations when writing this register. USB Device Functional Address (USBFADDR) Base 0x4005.0000 Offset 0x000 Type R/W, reset 0x00 7 6 5 4 reserved Type Reset RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 FUNCADDR R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 FUNCADDR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Function Address Function Address of Device as received through SET_ADDRESS. 676 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 2: USB Power (USBPOWER), offset 0x001 USBPOWER is an 8-bit register used for controlling SUSPEND and RESUME signaling and some basic operational aspects of the USB controller. Host Device Host Mode USB Power (USBPOWER) Base 0x4005.0000 Offset 0x001 Type R/W, reset 0x20 7 6 5 4 reserved Type Reset RO 0 RO 0 3 2 RESET RO 1 RO 0 1 0 RESUME SUSPEND PWRDNPHY R/W 0 R/W 0 R/W1S 0 Bit/Field Name Type Reset 7:4 reserved RO 0x2 3 RESET R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RESET Signaling Value Description 2 RESUME R/W 0 1 Enables RESET signaling on the bus. 0 Ends RESET signaling on the bus. RESUME Signaling Value Description 1 Enables RESUME signaling when the Device is in SUSPEND mode. 0 Ends RESUME signaling on the bus. This bit must be cleared by software 20 ms after being set. 1 SUSPEND R/W1S 0 SUSPEND Mode Value Description 0 PWRDNPHY R/W 0 1 Enables SUSPEND mode. 0 No effect. Power Down PHY Value Description 1 Powers down the internal USB PHY. 0 No effect. July 17, 2014 677 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Device Mode USB Power (USBPOWER) Base 0x4005.0000 Offset 0x001 Type R/W, reset 0x20 Type Reset 7 6 ISOUP SOFTCONN R/W 0 R/W 0 5 4 reserved RO 1 RO 0 3 2 RESET 1 0 RESUME SUSPEND PWRDNPHY RO 0 R/W 0 RO 0 Bit/Field Name Type Reset 7 ISOUP R/W 0 R/W 0 Description Isochronous Update Value Description 1 The USB controller waits for an SOF token from the time the TXRDY bit is set in the USBTXCSRLn register before sending the packet. If an IN token is received before an SOF token, then a zero-length data packet is sent. 0 No effect. Note: 6 SOFTCONN R/W 0 This bit is only valid for isochronous transfers. Soft Connect/Disconnect Value Description 5:4 reserved RO 0x2 3 RESET RO 0 1 The USB D+/D- lines are enabled. 0 The USB D+/D- lines are tri-stated. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RESET Signaling Value Description 2 RESUME R/W 0 1 RESET signaling is present on the bus. 0 RESET signaling is not present on the bus. RESUME Signaling Value Description 1 Enables RESUME signaling when the Device is in SUSPEND mode. 0 Ends RESUME signaling on the bus. This bit must be cleared by software 10 ms (a maximum of 15 ms) after being set. 678 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 1 SUSPEND RO 0 Description SUSPEND Mode Value Description 0 PWRDNPHY R/W 0 1 The USB controller is in SUSPEND mode. 0 This bit is cleared when software reads the interrupt register or sets the RESUME bit above. Power Down PHY Value Description 1 Powers down the internal USB PHY. 0 No effect. July 17, 2014 679 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 3: USB Transmit Interrupt Status (USBTXIS), offset 0x002 Important: This register is read-sensitive. See the register description for details. Host Device USBTXIS is a 16-bit read-only register that indicates which interrupts are currently active for endpoint 0 and the transmit endpoints 1–3. The meaning of the EPn bits in this register are based on the mode of the device. The EP1, EP2 and EP3 bits always indicate that the USB controller is sending data; however, in Host mode, the bits refer to OUT endpoints; while in Device mode, the bits refer to IN endpoints. The EP0 bit is special in Host and Device modes and indicates that either a control IN or control OUT endpoint has generated an interrupt. Note: Bits relating to endpoints that have not been configured always return 0. Note also that all active interrupts are cleared when this register is read. USB Transmit Interrupt Status (USBTXIS) Base 0x4005.0000 Offset 0x002 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 EP3 EP2 EP1 EP0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 15:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 EP3 RO 0 TX Endpoint 3 Interrupt Value Description 2 EP2 RO 0 0 No interrupt. 1 The Endpoint 3 transmit interrupt is asserted. TX Endpoint 2 Interrupt Same description as EP15. 1 EP1 RO 0 TX Endpoint 1 Interrupt Same description as EP15. 0 EP0 RO 0 TX and RX Endpoint 0 Interrupt Value Description 0 No interrupt. 1 The Endpoint 0 transmit and receive interrupt is asserted. 680 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 4: USB Receive Interrupt Status (USBRXIS), offset 0x004 Important: This register is read-sensitive. See the register description for details. USBRXIS is a 16-bit read-only register that indicates which of the interrupts for receive endpoints 1–3 are currently active. Host Note: Device Bits relating to endpoints that have not been configured always return 0. Note also that all active interrupts are cleared when this register is read. USB Receive Interrupt Status (USBRXIS) Base 0x4005.0000 Offset 0x004 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 EP3 EP2 EP1 reserved RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 15:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 EP3 RO 0 RX Endpoint 3 Interrupt Value Description 2 EP2 RO 0 0 No interrupt. 1 The Endpoint 3 receive interrupt is asserted. RX Endpoint 2 Interrupt Same description as EP3. 1 EP1 RO 0 RX Endpoint 1 Interrupt Same description as EP3. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 681 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 5: USB Transmit Interrupt Enable (USBTXIE), offset 0x006 Host Device USBTXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBTXIS register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the corresponding interrupt bit in the USBTXIS register is set. When a bit is cleared, the interrupt in the USBTXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset, the bits corresponding to endpoint 0 and transmit endpoints 1-3 are set to 1, while the remaining bits are set to 0. USB Transmit Interrupt Enable (USBTXIE) Base 0x4005.0000 Offset 0x006 Type R/W, reset 0x000F 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 EP3 EP2 EP1 EP0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset 2 1 0 Bit/Field Name Type Reset Description 15:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 EP3 R/W 1 TX Endpoint 3 Interrupt Enable Value Description 2 EP2 R/W 1 1 An interrupt is sent to the interrupt controller when the EP3 bit in the USBTXIS register is set. 0 The EP3 transmit interrupt is suppressed and not sent to the interrupt controller. TX Endpoint 2 Interrupt Enable Same description as EP3. 1 EP1 R/W 1 TX Endpoint 1 Interrupt Enable Same description as EP3. 0 EP0 R/W 1 TX and RX Endpoint 0 Interrupt Enable Value Description 1 An interrupt is sent to the interrupt controller when the EP0 bit in the USBTXIS register is set. 0 The EP0 transmit interrupt is suppressed and not sent to the interrupt controller. 682 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 6: USB Receive Interrupt Enable (USBRXIE), offset 0x008 Host Device USBRXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBRXIS register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the corresponding interrupt bit in the USBRXIS register is set. When a bit is cleared, the interrupt in the USBRXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset, the bits corresponding to receive endpoints 1-3 are set to 1, while the remaining bits are set to 0. USB Receive Interrupt Enable (USBRXIE) Base 0x4005.0000 Offset 0x008 Type R/W, reset 0x000E 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 EP3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 reserved Type Reset 2 1 0 EP2 EP1 reserved R/W 1 R/W 1 RO 0 Bit/Field Name Type Reset Description 15:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 EP3 R/W 1 RX Endpoint 3 Interrupt Enable 2 EP2 R/W 1 RX Endpoint 2 Interrupt Enable 1 EP1 R/W 1 RX Endpoint 1 Interrupt Enable 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 683 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 7: USB General Interrupt Status (USBIS), offset 0x00A Important: This register is read-sensitive. See the register description for details. USBIS is an 8-bit read-only register that indicates which USB interrupts are currently active. All active interrupts are cleared when this register is read. Host Device Host Mode USB General Interrupt Status (USBIS) Base 0x4005.0000 Offset 0x00A Type RO, reset 0x00 7 6 reserved Type Reset RO 0 RO 0 5 4 3 DISCON CONN SOF 2 RO 0 RO 0 RO 0 1 0 BABBLE RESUME reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 DISCON RO 0 Session Disconnect Value Description 4 CONN RO 0 1 A Device disconnect has been detected. 0 No interrupt. Session Connect Value Description 3 SOF RO 0 1 A Device connection has been detected. 0 No interrupt. Start of Frame Value Description 2 BABBLE RO 0 1 A new frame has started. 0 No interrupt. Babble Detected Value Description 1 Babble has been detected. This interrupt is active only after the first SOF has been sent. 0 No interrupt. 684 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 1 RESUME RO 0 Description RESUME Signaling Detected Value Description 1 RESUME signaling has been detected on the bus while the USB controller is in SUSPEND mode. 0 No interrupt. This interrupt can only be used if the USB controller's system clock is enabled. If the user disables the clock programming, the USBDRRIS, USBDRIM, and USBDRISC registers should be used. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 0 Device Mode USB General Interrupt Status (USBIS) Base 0x4005.0000 Offset 0x00A Type RO, reset 0x00 7 6 RO 0 RO 0 5 4 RO 0 RO 0 reserved Type Reset 3 2 SOF RESET RO 0 RO 0 RESUME SUSPEND RO 0 Bit/Field Name Type Reset 7:4 reserved RO 0x0 3 SOF RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Start of Frame Value Description 2 RESET RO 0 1 A new frame has started. 0 No interrupt. RESET Signaling Detected Value Description 1 RESET signaling has been detected on the bus. 0 No interrupt. July 17, 2014 685 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 1 RESUME RO 0 Description RESUME Signaling Detected Value Description 1 RESUME signaling has been detected on the bus while the USB controller is in SUSPEND mode. 0 No interrupt. This interrupt can only be used if the USB controller's system clock is enabled. If the user disables the clock programming, the USBDRRIS, USBDRIM, and USBDRISC registers should be used. 0 SUSPEND RO 0 SUSPEND Signaling Detected Value Description 1 SUSPEND signaling has been detected on the bus. 0 No interrupt. 686 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 8: USB Interrupt Enable (USBIE), offset 0x00B USBIE is an 8-bit register that provides interrupt enable bits for each of the interrupts in USBIS. At reset interrupts 1 and 2 are enabled in Device mode. Host Device Host Mode USB Interrupt Enable (USBIE) Base 0x4005.0000 Offset 0x00B Type R/W, reset 0x06 7 6 reserved Type Reset RO 0 RO 0 5 4 3 DISCON CONN SOF 2 R/W 0 R/W 0 R/W 0 1 0 BABBLE RESUME reserved R/W 1 R/W 1 RO 0 Bit/Field Name Type Reset Description 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 DISCON R/W 0 Enable Disconnect Interrupt Value Description 4 CONN R/W 0 1 An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set. 0 The DISCON interrupt is suppressed and not sent to the interrupt controller. Enable Connect Interrupt Value Description 3 SOF R/W 0 1 An interrupt is sent to the interrupt controller when the CONN bit in the USBIS register is set. 0 The CONN interrupt is suppressed and not sent to the interrupt controller. Enable Start-of-Frame Interrupt Value Description 1 An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set. 0 The SOF interrupt is suppressed and not sent to the interrupt controller. July 17, 2014 687 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 2 BABBLE R/W 1 Description Enable Babble Interrupt Value Description 1 RESUME R/W 1 1 An interrupt is sent to the interrupt controller when the BABBLE bit in the USBIS register is set. 0 The BABBLE interrupt is suppressed and not sent to the interrupt controller. Enable RESUME Interrupt Value Description 0 reserved RO 1 An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set. 0 The RESUME interrupt is suppressed and not sent to the interrupt controller. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 0 Device Mode USB Interrupt Enable (USBIE) Base 0x4005.0000 Offset 0x00B Type R/W, reset 0x06 7 6 reserved Type Reset RO 0 RO 0 5 4 3 2 DISCON reserved SOF RESET R/W 0 RO 0 R/W 0 R/W 1 RESUME SUSPEND R/W 1 Bit/Field Name Type Reset 7:6 reserved RO 0x0 5 DISCON R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable Disconnect Interrupt Value Description 4 reserved RO 0 1 An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set. 0 The DISCON interrupt is suppressed and not sent to the interrupt controller. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 688 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 3 SOF R/W 0 Description Enable Start-of-Frame Interrupt Value Description 2 RESET R/W 1 1 An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set. 0 The SOF interrupt is suppressed and not sent to the interrupt controller. Enable RESET Interrupt Value Description 1 RESUME R/W 1 1 An interrupt is sent to the interrupt controller when the RESET bit in the USBIS register is set. 0 The RESET interrupt is suppressed and not sent to the interrupt controller. Enable RESUME Interrupt Value Description 0 SUSPEND R/W 0 1 An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set. 0 The RESUME interrupt is suppressed and not sent to the interrupt controller. Enable SUSPEND Interrupt Value Description 1 An interrupt is sent to the interrupt controller when the SUSPEND bit in the USBIS register is set. 0 The SUSPEND interrupt is suppressed and not sent to the interrupt controller. July 17, 2014 689 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 9: USB Frame Value (USBFRAME), offset 0x00C USBFRAME is a 16-bit read-only register that holds the last received frame number. Host USB Frame Value (USBFRAME) Device Base 0x4005.0000 Offset 0x00C Type RO, reset 0x0000 15 14 RO 0 RO 0 13 12 11 10 9 8 7 6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 FRAME RO 0 Bit/Field Name Type Reset Description 15:11 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:0 FRAME RO 0x00 Frame Number 690 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 10: USB Endpoint Index (USBEPIDX), offset 0x00E Each endpoint's buffer can be accessed by configuring a FIFO size and starting address. The USBEPIDX 16-bit register is used with the USBTXFIFOSZ, USBRXFIFOSZ, USBTXFIFOADD, and USBRXFIFOADD registers. Host Device USB Endpoint Index (USBEPIDX) Base 0x4005.0000 Offset 0x00E Type R/W, reset 0x00 7 6 RO 0 RO 0 5 4 3 2 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset 1 0 R/W 0 R/W 0 EPIDX Bit/Field Name Type Reset Description 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 EPIDX R/W 0x0 Endpoint Index This bit field configures which endpoint is accessed when reading or writing to one of the USB controller's indexed registers. A value of 0x0 corresponds to Endpoint 0 and a value of 0x3 corresponds to Endpoint 3. July 17, 2014 691 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 11: USB Test Mode (USBTEST), offset 0x00F Host USBTEST is an 8-bit register that is primarily used to put the USB controller into one of the four test modes for operation described in the USB 2.0 Specification, in response to a SET FEATURE: USBTESTMODE command. This register is not used in normal operation. Device Note: Only one of these bits should be set at any time. Host Mode USB Test Mode (USBTEST) Base 0x4005.0000 Offset 0x00F Type R/W, reset 0x00 7 6 5 4 3 FORCEH FIFOACC FORCEFS Type Reset R/W 0 R/W1S 0 R/W 0 2 1 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset 7 FORCEH R/W 0 Description Force Host Mode Value Description 1 Forces the USB controller to enter Host mode when the SESSION bit is set, regardless of whether the USB controller is connected to any peripheral. The state of the USB0DP and USB0DM signals is ignored. The USB controller then remains in Host mode until the SESSION bit is cleared, even if a Device is disconnected. If the FORCEH bit remains set, the USB controller re-enters Host mode the next time the SESSION bit is set. 0 No effect. While in this mode, status of the bus connection may be read using the DEV bit of the USBDEVCTL register. The operating speed is determined from the FORCEFS bit. 6 FIFOACC R/W1S 0 FIFO Access Value Description 1 Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO. 0 No effect. This bit is cleared automatically. 5 FORCEFS R/W 0 Force Full-Speed Mode Value Description 1 Forces the USB controller into Full-Speed mode upon receiving a USB RESET. 0 The USB controller operates at Low Speed. 692 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 4:0 reserved RO 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Mode USB Test Mode (USBTEST) Base 0x4005.0000 Offset 0x00F Type R/W, reset 0x00 7 6 5 4 3 reserved FIFOACC FORCEFS Type Reset RO 0 R/W1S 0 R/W 0 2 1 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 FIFOACC R/W1S 0 FIFO Access Value Description 1 Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO. 0 No effect. This bit is cleared automatically. 5 FORCEFS R/W 0 Force Full-Speed Mode Value Description 4:0 reserved RO 0x0 1 Forces the USB controller into Full-Speed mode upon receiving a USB RESET. 0 The USB controller operates at Low Speed. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 693 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 12: USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 Register 13: USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 Register 14: USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 Register 15: USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C Important: This register is read-sensitive. See the register description for details. These 32-bit registers provide an address for CPU access to the FIFOs for each endpoint. Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint. Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint. Host Device Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of accesses is allowed provided the data accessed is contiguous. All transfers associated with one packet must be of the same width so that the data is consistently byte-, halfword- or word-aligned. However, the last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer. Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support either single-packet or double-packet buffering (see the section called “Single-Packet Buffering” on page 663). Burst writing of multiple packets is not supported as flags must be set after each packet is written. Following a STALL response or a transmit error on endpoint 1–3, the associated FIFO is completely flushed. USB FIFO Endpoint 0 (USBFIFO0) Base 0x4005.0000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EPDATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 EPDATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 EPDATA R/W R/W 0 Reset R/W 0 Description 0x0000.0000 Endpoint Data Writing to this register loads the data into the Transmit FIFO and reading unloads data from the Receive FIFO. 694 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 16: USB Device Control (USBDEVCTL), offset 0x060 USBDEVCTL provides the status information for the current operating mode (Host or Device) of the USB controller. If the USB controller is in Host mode, this register also indicates if a full- or low-speed Device has been connected. Host USB Device Control (USBDEVCTL) Base 0x4005.0000 Offset 0x060 Type RO, reset 0x80 Type Reset 7 6 5 reserved FSDEV LSDEV RO 0 RO 0 RO 0 4 3 2 reserved RO 0 1 HOST RO 0 RO 0 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 FSDEV RO 0 Full-Speed Device Detected Value Description 5 LSDEV RO 0 0 A full-speed Device has not been detected on the port. 1 A full-speed Device has been detected on the port. Low-Speed Device Detected Value Description 0 A low-speed Device has not been detected on the port. 1 A low-speed Device has been detected on the port. 4:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 HOST RO 0 Host Mode Value Description 0 The USB controller is acting as a Device. 1 The USB controller is acting as a Host. Note: 1:0 reserved RO 0 This value is only valid while a session is in progress. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 695 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 17: USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 Register 18: USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 These 8-bit registers allow the selected TX/RX endpoint FIFOs to be dynamically sized. USBEPIDX is used to configure each transmit endpoint's FIFO size. Host Device USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) Base 0x4005.0000 Offset 0x062 Type R/W, reset 0x00 7 6 5 4 reserved Type Reset RO 0 RO 0 3 2 R/W 0 R/W 0 DPB RO 0 R/W 0 1 0 R/W 0 R/W 0 SIZE Bit/Field Name Type Reset 7:5 reserved RO 0x0 4 DPB R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Double Packet Buffer Support Value Description 3:0 SIZE R/W 0x0 0 Only single-packet buffering is supported. 1 Double-packet buffering is supported. Max Packet Size Maximum packet size to be allowed. If DPB = 0, the FIFO also is this size; if DPB = 1, the FIFO is twice this size. Value Packet Size (Bytes) 0x0 8 0x1 16 0x2 32 0x3 64 0x4 128 0x5 256 0x6 512 0x7 1024 0x8 2048 0x9-0xF Reserved 696 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 19: USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 Register 20: USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 USBTXFIFOADD and USBRXFIFOADD are 16-bit registers that control the start address of the selected transmit and receive endpoint FIFOs. Host Device USB Transmit FIFO Start Address (USBTXFIFOADD) Base 0x4005.0000 Offset 0x064 Type R/W, reset 0x0000 15 14 13 RO 0 RO 0 RO 0 12 11 10 9 8 7 6 5 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 ADDR R/W 0 Bit/Field Name Type Reset Description 15:9 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8:0 ADDR R/W 0x00 Transmit/Receive Start Address Start address of the endpoint FIFO. Value Start Address 0x0 0 0x1 8 0x2 16 0x3 24 0x4 32 0x5 40 0x6 48 0x7 56 0x8 64 ... ... 0x1FF 4095 July 17, 2014 697 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 21: USB Connect Timing (USBCONTIM), offset 0x07A This 8-bit configuration register specifies connection delay. Host USB Connect Timing (USBCONTIM) Device Base 0x4005.0000 Offset 0x07A Type R/W, reset 0x5C 7 6 R/W 0 R/W 1 5 4 3 2 R/W 0 R/W 1 R/W 1 R/W 1 WTCON Type Reset 1 0 R/W 0 R/W 0 WTID Bit/Field Name Type Reset 7:4 WTCON R/W 0x5 Description Connect Wait This field configures the wait required to allow for the user’s connect/disconnect filter, in units of 533.3 ns. The default corresponds to 2.667 µs. 3:0 WTID R/W 0xC Wait ID This field configures the delay required from the enable of the ID detection to when the ID value is valid, in units of 4.369 ms. The default corresponds to 52.43 ms. 698 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 22: USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D This 8-bit configuration register specifies the minimum time gap allowed between the start of the last transaction and the EOF for full-speed transactions. Host Device USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF) Base 0x4005.0000 Offset 0x07D Type R/W, reset 0x77 7 6 5 4 3 2 1 0 R/W 0 R/W 1 R/W 1 R/W 1 FSEOFG Type Reset R/W 0 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 7:0 FSEOFG R/W 0x77 Full-Speed End-of-Frame Gap This field is used during full-speed transactions to configure the gap between the last transaction and the End-of-Frame (EOF), in units of 533.3 ns. The default corresponds to 63.46 µs. July 17, 2014 699 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 23: USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E This 8-bit configuration register specifies the minimum time gap that is to be allowed between the start of the last transaction and the EOF for low-speed transactions. Host Device USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF) Base 0x4005.0000 Offset 0x07E Type R/W, reset 0x72 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 1 R/W 0 LSEOFG Type Reset R/W 0 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 7:0 LSEOFG R/W 0x72 Low-Speed End-of-Frame Gap This field is used during low-speed transactions to set the gap between the last transaction and the End-of-Frame (EOF), in units of 1.067 µs. The default corresponds to 121.6 µs. 700 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 24: USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 Register 25: USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 Register 26: USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 Register 27: USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 USBTXFUNCADDRn is an 8-bit read/write register that records the address of the target function to be accessed through the associated endpoint (EPn). USBTXFUNCADDRn must be defined for each transmit endpoint that is used. Host Note: USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0. USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0) Base 0x4005.0000 Offset 0x080 Type R/W, reset 0x00 7 6 5 4 reserved Type Reset RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 ADDR R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 ADDR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Address Specifies the USB bus address for the target Device. July 17, 2014 701 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 28: USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 Register 29: USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A Register 30: USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 Register 31: USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A USBTXHUBADDRn is an 8-bit read/write register that, like USBTXHUBPORTn, only must be written when a USB Device is connected to transmit endpoint EPn via a USB 2.0 hub. This register records the address of the USB 2.0 hub through which the target associated with the endpoint is accessed. Host Note: USBTXHUBADDR0 is used for both receive and transmit for endpoint 0. USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0) Base 0x4005.0000 Offset 0x082 Type R/W, reset 0x00 7 6 5 4 reserved Type Reset RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 ADDR R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 ADDR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hub Address This field specifies the USB bus address for the USB 2.0 hub. 702 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 32: USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 Register 33: USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B Register 34: USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 Register 35: USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B USBTXHUBPORTn is an 8-bit read/write register that, like USBTXHUBADDRn, only must be written when a full- or low-speed Device is connected to transmit endpoint EPn via a USB 2.0 hub. This register records the port of the USB 2.0 hub through which the target associated with the endpoint is accessed. Host Note: USBTXHUBPORT0 is used for both receive and transmit for endpoint 0. USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0) Base 0x4005.0000 Offset 0x083 Type R/W, reset 0x00 7 6 5 4 reserved Type Reset RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 PORT R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 PORT R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hub Port This field specifies the USB hub port number. July 17, 2014 703 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 36: USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C Register 37: USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 Register 38: USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C USBRXFUNCADDRn is an 8-bit read/write register that records the address of the target function accessed through the associated endpoint (EPn). USBRXFUNCADDRn must be defined for each receive endpoint that is used. Host Note: USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0. USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1) Base 0x4005.0000 Offset 0x08C Type R/W, reset 0x00 7 6 5 4 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 ADDR R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 ADDR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Address This field specifies the USB bus address for the target Device. 704 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 39: USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E Register 40: USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 Register 41: USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E USBRXHUBADDRn is an 8-bit read/write register that, like USBRXHUBPORTn, only must be written when a full- or low-speed Device is connected to receive endpoint EPn via a USB 2.0 hub. This register records the address of the USB 2.0 hub through which the target associated with the endpoint is accessed. Host Note: USBTXHUBADDR0 is used for both receive and transmit for endpoint 0. USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1) Base 0x4005.0000 Offset 0x08E Type R/W, reset 0x00 7 6 5 4 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 ADDR R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 ADDR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hub Address This field specifies the USB bus address for the USB 2.0 hub. July 17, 2014 705 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 42: USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F Register 43: USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 Register 44: USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F USBRXHUBPORTn is an 8-bit read/write register that, like USBRXHUBADDRn, only must be written when a full- or low-speed Device is connected to receive endpoint EPn via a USB 2.0 hub. This register records the port of the USB 2.0 hub through which the target associated with the endpoint is accessed. Host Note: USBTXHUBPORT0 is used for both receive and transmit for endpoint 0. USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1) Base 0x4005.0000 Offset 0x08F Type R/W, reset 0x00 7 6 5 4 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 PORT R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 PORT R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hub Port This field specifies the USB hub port number. 706 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 45: USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 Register 46: USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 Register 47: USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 Host The USBTXMAXPn 16-bit register defines the maximum amount of data that can be transferred through the transmit endpoint in a single operation. Device Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed operation. The total amount of data represented by the value written to this register must not exceed the FIFO size for the transmit endpoint, and must not exceed half the FIFO size if double-buffering is required. If this register is changed after packets have been sent from the endpoint, the transmit endpoint FIFO must be completely flushed (using the FLUSH bit in USBTXCSRLn) after writing the new value to this register. Note: USBTXMAXPn must be set to an even number of bytes for proper interrupt generation in µDMA Basic Mode. USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1) Base 0x4005.0000 Offset 0x110 Type R/W, reset 0x0000 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MAXLOAD RO 0 RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 15:11 reserved RO 0 10:0 MAXLOAD R/W 0x000 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Maximum Payload This field specifies the maximum payload in bytes per transaction. July 17, 2014 707 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 48: USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 USBCSRL0 is an 8-bit register that provides control and status bits for endpoint 0. Host Device Host Mode USB Control and Status Endpoint 0 Low (USBCSRL0) Base 0x4005.0000 Offset 0x102 Type R/W, reset 0x00 7 NAKTO Type Reset R/W 0 6 5 STATUS REQPKT R/W 0 4 3 2 1 0 ERROR SETUP STALLED TXRDY RXRDY R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 NAKTO R/W 0 Description NAK Timeout Value Description 0 No timeout. 1 Indicates that endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the USBNAKLMT register. Software must clear this bit to allow the endpoint to continue. 6 STATUS R/W 0 STATUS Packet Value Description 0 No transaction. 1 Initiates a STATUS stage transaction. This bit must be set at the same time as the TXRDY or REQPKT bit is set. Setting this bit ensures that the DT bit is set in the USBCSRH0 register so that a DATA1 packet is used for the STATUS stage transaction. This bit is automatically cleared when the STATUS stage is over. 5 REQPKT R/W 0 Request Packet Value Description 0 No request. 1 Requests an IN transaction. This bit is cleared when the RXRDY bit is set. 708 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 4 ERROR R/W 0 Description Error Value Description 0 No error. 1 Three attempts have been made to perform a transaction with no response from the peripheral. The EP0 bit in the USBTXIS register is also set in this situation. Software must clear this bit. 3 SETUP R/W 0 Setup Packet Value Description 0 Sends an OUT token. 1 Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set. Setting this bit always clears the DT bit in the USBCSRH0 register to send a DATA0 packet. 2 STALLED R/W 0 Endpoint Stalled Value Description 0 No handshake has been received. 1 A STALL handshake has been received. Software must clear this bit. 1 TXRDY R/W 0 Transmit Packet Ready Value Description 0 No transmit packet is ready. 1 Software sets this bit after loading a data packet into the TX FIFO. The EP0 bit in the USBTXIS register is also set in this situation. If both the TXRDY and SETUP bits are set, a setup packet is sent. If just TXRDY is set, an OUT packet is sent. This bit is cleared automatically when the data packet has been transmitted. 0 RXRDY R/W 0 Receive Packet Ready Value Description 0 No received packet has been received. 1 Indicates that a data packet has been received in the RX FIFO. The EP0 bit in the USBTXIS register is also set in this situation. Software must clear this bit after the packet has been read from the FIFO to acknowledge that the data has been read from the FIFO. July 17, 2014 709 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Device Mode USB Control and Status Endpoint 0 Low (USBCSRL0) Base 0x4005.0000 Offset 0x102 Type R/W, reset 0x00 7 6 SETENDC RXRDYC Type Reset W1C 0 W1C 0 5 STALL 4 3 2 SETEND DATAEND STALLED W1C 0 RO 0 W1C 0 R/W 0 1 0 TXRDY RXRDY R/W 0 RO 0 Bit/Field Name Type Reset 7 SETENDC W1C 0 Description Setup End Clear Writing a 1 to this bit clears the SETEND bit. 6 RXRDYC W1C 0 RXRDY Clear Writing a 1 to this bit clears the RXRDY bit. 5 STALL W1C 0 Send Stall Value Description 0 No effect. 1 Terminates the current transaction and transmits the STALL handshake. This bit is cleared automatically after the STALL handshake is transmitted. 4 SETEND RO 0 Setup End Value Description 0 A control transaction has not ended or ended after the DATAEND bit was set. 1 A control transaction has ended before the DATAEND bit has been set. The EP0 bit in the USBTXIS register is also set in this situation. This bit is cleared by writing a 1 to the SETENDC bit. 3 DATAEND W1C 0 Data End Value Description 0 No effect. 1 Set this bit in the following situations: ■ When setting TXRDY for the last data packet ■ When clearing RXRDY after unloading the last data packet ■ When setting TXRDY for a zero-length data packet This bit is cleared automatically. 710 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 2 STALLED R/W 0 Description Endpoint Stalled Value Description 0 A STALL handshake has not been transmitted. 1 A STALL handshake has been transmitted. Software must clear this bit. 1 TXRDY R/W 0 Transmit Packet Ready Value Description 0 No transmit packet is ready. 1 Software sets this bit after loading an IN data packet into the TX FIFO. The EP0 bit in the USBTXIS register is also set in this situation. This bit is cleared automatically when the data packet has been transmitted. 0 RXRDY RO 0 Receive Packet Ready Value Description 0 No data packet has been received. 1 A data packet has been received. The EP0 bit in the USBTXIS register is also set in this situation. This bit is cleared by writing a 1 to the RXRDYC bit. July 17, 2014 711 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 49: USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 USBSR0H is an 8-bit register that provides control and status bits for endpoint 0. Host Device Host Mode USB Control and Status Endpoint 0 High (USBCSRH0) Base 0x4005.0000 Offset 0x103 Type R/W, reset 0x00 7 6 RO 0 RO 0 5 4 3 RO 0 RO 0 2 reserved Type Reset RO 0 1 0 DTWE DT FLUSH W1S 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7:3 reserved RO 0x0 2 DTWE W1S 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data Toggle Write Enable Value Description 0 The DT bit cannot be written. 1 Enables the current state of the endpoint 0 data toggle to be written (see DT bit). This bit is automatically cleared once the new value is written. 1 DT R/W 0 Data Toggle When read, this bit indicates the current state of the endpoint 0 data toggle. If DTWE is set, this bit may be written with the required setting of the data toggle. If DTWE is Low, this bit cannot be written. Care should be taken when writing to this bit as it should only be changed to RESET USB endpoint 0. 0 FLUSH R/W 0 Flush FIFO Value Description 0 No effect. 1 Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is cleared. This bit is automatically cleared after the flush is performed. Important: This bit should only be set when TXRDY is clear and RXRDY is set. At other times, it may cause data to be corrupted. 712 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Device Mode USB Control and Status Endpoint 0 High (USBCSRH0) Base 0x4005.0000 Offset 0x103 Type R/W, reset 0x00 7 6 5 RO 0 RO 0 RO 0 4 3 2 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 0 FLUSH W1S 0 Bit/Field Name Type Reset Description 7:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 FLUSH W1S 0 Flush FIFO Value Description 0 No effect. 1 Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is cleared. This bit is automatically cleared after the flush is performed. Important: This bit should only be set when TXRDY is clear and RXRDY is set. At other times, it may cause data to be corrupted. July 17, 2014 713 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 50: USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 USBCOUNT0 is an 8-bit read-only register that indicates the number of received data bytes in the endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while the RXRDY bit is set. Host Device USB Receive Byte Count Endpoint 0 (USBCOUNT0) Base 0x4005.0000 Offset 0x108 Type RO, reset 0x00 7 6 5 4 RO 0 RO 0 RO 0 reserved Type Reset RO 0 3 2 1 0 RO 0 RO 0 RO 0 COUNT RO 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 COUNT RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Count COUNT is a read-only value that indicates the number of received data bytes in the endpoint 0 FIFO. 714 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 51: USB Type Endpoint 0 (USBTYPE0), offset 0x10A This is an 8-bit register that must be written with the operating speed of the targeted Device being communicated with using endpoint 0. Host USB Type Endpoint 0 (USBTYPE0) Base 0x4005.0000 Offset 0x10A Type R/W, reset 0x00 7 6 5 4 3 R/W 0 RO 0 RO 0 RO 0 SPEED Type Reset R/W 0 2 1 0 RO 0 RO 0 RO 0 reserved Bit/Field Name Type Reset 7:6 SPEED R/W 0x0 Description Operating Speed This field specifies the operating speed of the target Device. If selected, the target is assumed to have the same connection speed as the USB controller. Value Description 0x0 - 0x1 Reserved 5:0 reserved RO 0x0 0x2 Full 0x3 Low Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 715 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 52: USB NAK Limit (USBNAKLMT), offset 0x10B USBNAKLMT is an 8-bit register that sets the number of frames after which endpoint 0 should time out on receiving a stream of NAK responses. (Equivalent settings for other endpoints can be made through their USBTXINTERVALn and USBRXINTERVALn registers.) Host (m-1) The number of frames selected is 2 (where m is the value set in the register, with valid values of 2–16). If the Host receives NAK responses from the target for more frames than the number represented by the limit set in this register, the endpoint is halted. Note: A value of 0 or 1 disables the NAK timeout function. USB NAK Limit (USBNAKLMT) Base 0x4005.0000 Offset 0x10B Type R/W, reset 0x00 7 6 5 4 3 2 RO 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 1 0 R/W 0 R/W 0 NAKLMT R/W 0 Bit/Field Name Type Reset Description 7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4:0 NAKLMT R/W 0x0 EP0 NAK Limit This field specifies the number of frames after receiving a stream of NAK responses. 716 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 53: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 Register 54: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 Register 55: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the currently selected transmit endpoint. Host Device Host Mode USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1) Base 0x4005.0000 Offset 0x112 Type R/W, reset 0x00 Type Reset 7 6 5 4 3 2 1 0 NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 NAKTO R/W 0 Description NAK Timeout Value Description 6 CLRDT R/W 0 0 No timeout. 1 Bulk endpoints only: Indicates that the transmit endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBTXINTERVALn register. Software must clear this bit to allow the endpoint to continue. Clear Data Toggle Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register. 5 STALLED R/W 0 Endpoint Stalled Value Description 0 A STALL handshake has not been received. 1 Indicates that a STALL handshake has been received. When this bit is set, any µDMA request that is in progress is stopped, the FIFO is completely flushed, and the TXRDY bit is cleared. Software must clear this bit. July 17, 2014 717 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 4 SETUP R/W 0 Description Setup Packet Value Description 0 No SETUP token is sent. 1 Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set. Note: 3 FLUSH R/W 0 Setting this bit also clears the DT bit in the USBTXCSRHn register. Flush FIFO Value Description 0 No effect. 1 Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation. This bit may be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Important: 2 ERROR R/W 0 This bit should only be set when the TXRDY bit is clear. At other times, it may cause data to be corrupted. Error Value Description 0 No error. 1 Three attempts have been made to send a packet and no handshake packet has been received. The TXRDY bit is cleared, the EPn bit in the USBTXIS register is set, and the FIFO is completely flushed in this situation. Software must clear this bit. Note: 1 FIFONE R/W 0 This is valid only when the endpoint is operating in Bulk or Interrupt mode. FIFO Not Empty Value Description 0 The FIFO is empty. 1 At least one packet is in the transmit FIFO. 718 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 0 TXRDY R/W 0 Description Transmit Packet Ready Value Description 0 No transmit packet is ready. 1 Software sets this bit after loading a data packet into the TX FIFO. This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO. Device Mode USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1) Base 0x4005.0000 Offset 0x112 Type R/W, reset 0x00 Type Reset 7 6 5 4 3 2 1 0 reserved CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 CLRDT R/W 0 Clear Data Toggle Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register. 5 STALLED R/W 0 Endpoint Stalled Value Description 0 A STALL handshake has not been transmitted. 1 A STALL handshake has been transmitted. The FIFO is flushed and the TXRDY bit is cleared. Software must clear this bit. 4 STALL R/W 0 Send STALL Value Description 0 No effect. 1 Issues a STALL handshake to an IN token. Software clears this bit to terminate the STALL condition. Note: This bit has no effect in isochronous transfers. July 17, 2014 719 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset Description 3 FLUSH R/W 0 Flush FIFO Value Description 0 No effect. 1 Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation. This bit may be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Important: 2 UNDRN R/W 0 This bit should only be set when the TXRDY bit is clear. At other times, it may cause data to be corrupted. Underrun Value Description 0 No underrun. 1 An IN token has been received when TXRDY is not set. Software must clear this bit. 1 FIFONE R/W 0 FIFO Not Empty Value Description 0 TXRDY R/W 0 0 The FIFO is empty. 1 At least one packet is in the transmit FIFO. Transmit Packet Ready Value Description 0 No transmit packet is ready. 1 Software sets this bit after loading a data packet into the TX FIFO. This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO. 720 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 56: USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 Register 57: USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 Register 58: USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 USBTXCSRHn is an 8-bit register that provides additional control for transfers through the currently selected transmit endpoint. Host Device Host Mode USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1) Base 0x4005.0000 Offset 0x113 Type R/W, reset 0x00 7 6 AUTOSET reserved Type Reset R/W 0 RO 0 5 4 3 2 1 MODE DMAEN FDT DMAMOD DTWE DT R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 AUTOSET R/W 0 0 Description Auto Set Value Description 0 The TXRDY bit must be set manually. 1 Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in USBTXMAXPn) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then the TXRDY bit must be set manually. 6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 MODE R/W 0 Mode Value Description 0 Enables the endpoint direction as RX. 1 Enables the endpoint direction as TX. Note: This bit only has an effect when the same endpoint FIFO is used for both transmit and receive transactions. July 17, 2014 721 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 4 DMAEN R/W 0 Description DMA Request Enable Value Description 0 Disables the µDMA request for the transmit endpoint. 1 Enables the µDMA request for the transmit endpoint. Note: 3 FDT R/W 0 3 TX and 3 /RX endpoints can be connected to the µDMA module. If this bit is set for a particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. Force Data Toggle Value Description 2 DMAMOD R/W 0 0 No effect. 1 Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints. DMA Request Mode Value Description 0 An interrupt is generated after every µDMA packet transfer. 1 An interrupt is generated only after the entire μDMA transfer is complete. Note: 1 DTWE R/W 0 This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Data Toggle Write Enable Value Description 0 The DT bit cannot be written. 1 Enables the current state of the transmit endpoint data to be written (see DT bit). This bit is automatically cleared once the new value is written. 0 DT R/W 0 Data Toggle When read, this bit indicates the current state of the transmit endpoint data toggle. If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the transmit endpoint. 722 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Device Mode USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1) Base 0x4005.0000 Offset 0x113 Type R/W, reset 0x00 7 Type Reset 6 5 4 3 2 AUTOSET ISO MODE DMAEN FDT DMAMOD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 1 0 reserved RO 0 Bit/Field Name Type Reset 7 AUTOSET R/W 0 RO 0 Description Auto Set Value Description 6 ISO R/W 0 0 The TXRDY bit must be set manually. 1 Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in USBTXMAXPn) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then the TXRDY bit must be set manually. Isochronous Transfers Value Description 5 MODE R/W 0 0 Enables the transmit endpoint for bulk or interrupt transfers. 1 Enables the transmit endpoint for isochronous transfers. Mode Value Description 0 Enables the endpoint direction as RX. 1 Enables the endpoint direction as TX. Note: 4 DMAEN R/W 0 This bit only has an effect where the same endpoint FIFO is used for both transmit and receive transactions. DMA Request Enable Value Description 0 Disables the µDMA request for the transmit endpoint. 1 Enables the µDMA request for the transmit endpoint. Note: 3 TX and 3 RX endpoints can be connected to the µDMA module. If this bit is set for a particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. July 17, 2014 723 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 3 FDT R/W 0 Description Force Data Toggle Value Description 2 DMAMOD R/W 0 0 No effect. 1 Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints. DMA Request Mode Value Description 0 An interrupt is generated after every µDMA packet transfer. 1 An interrupt is generated only after the entire μDMA transfer is complete. Note: 1:0 reserved RO 0x0 This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 724 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 59: USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 Register 60: USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 Register 61: USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 Host The USBRXMAXPn is a 16-bit register which defines the maximum amount of data that can be transferred through the selected receive endpoint in a single operation. Device Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed operations. The total amount of data represented by the value written to this register must not exceed the FIFO size for the receive endpoint, and must not exceed half the FIFO size if double-buffering is required. Note: USBRXMAXPn must be set to an even number of bytes for proper interrupt generation in µDMA Basic mode. USB Maximum Receive Data Endpoint 1 (USBRXMAXP1) Base 0x4005.0000 Offset 0x114 Type R/W, reset 0x0000 15 14 RO 0 RO 0 13 12 11 10 9 8 7 6 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MAXLOAD Bit/Field Name Type Reset 15:11 reserved RO 0 10:0 MAXLOAD R/W 0x000 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Maximum Payload The maximum payload in bytes per transaction. July 17, 2014 725 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 62: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 Register 63: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 Register 64: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 USBRXCSRLn is an 8-bit register that provides control and status bits for transfers through the currently selected receive endpoint. Host Device Host Mode USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1) 7 CLRDT Type Reset W1C 0 6 5 STALLED REQPKT R/WC 0 4 3 2 1 0 FLUSH DATAERR / NAKTO Base 0x4005.0000 Offset 0x116 Type R/W, reset 0x00 ERROR FULL RXRDY R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 CLRDT W1C 0 Description Clear Data Toggle Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register. 6 STALLED R/WC 0 Endpoint Stalled Value Description 0 A STALL handshake has not been received. 1 A STALL handshake has been received. The EPn bit in the USBRXIS register is also set. Software must clear this bit. 5 REQPKT R/W 0 Request Packet Value Description 0 No request. 1 Requests an IN transaction. This bit is cleared when RXRDY is set. 726 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 4 FLUSH R/W 0 Flush FIFO Value Description 0 No effect. 1 Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Important: 3 DATAERR / NAKTO R/W 0 This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted. Data Error / NAK Timeout Value Description 0 Normal operation. 1 Isochronous endpoints only: Indicates that RXRDY is set and the data packet has a CRC or bit-stuff error. This bit is cleared when RXRDY is cleared. Bulk endpoints only: Indicates that the receive endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBRXINTERVALn register. Software must clear this bit to allow the endpoint to continue. 2 ERROR R/W 0 Error Value Description 0 No error. 1 Three attempts have been made to receive a packet and no data packet has been received. The EPn bit in the USBRXIS register is set in this situation. Software must clear this bit. Note: 1 FULL RO 0 This bit is only valid when the receive endpoint is operating in Bulk or Interrupt mode. In Isochronous mode, it always returns zero. FIFO Full Value Description 0 The receive FIFO is not full. 1 No more packets can be loaded into the receive FIFO. July 17, 2014 727 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 0 RXRDY R/W 0 Description Receive Packet Ready Value Description 0 No data packet has been received. 1 A data packet has been received. The EPn bit in the USBRXIS register is also set in this situation. If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit is automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO. Device Mode USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1) Base 0x4005.0000 Offset 0x116 Type R/W, reset 0x00 Type Reset 7 6 5 CLRDT STALLED STALL W1C 0 R/W 0 R/W 0 4 3 FLUSH DATAERR W1S 0 2 1 0 OVER FULL RXRDY R/W 0 RO 0 R/W 0 RO 0 Bit/Field Name Type Reset 7 CLRDT W1C 0 Description Clear Data Toggle Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register. 6 STALLED R/W 0 Endpoint Stalled Value Description 0 A STALL handshake has not been transmitted. 1 A STALL handshake has been transmitted. Software must clear this bit. 5 STALL R/W 0 Send STALL Value Description 0 No effect. 1 Issues a STALL handshake. Software must clear this bit to terminate the STALL condition. Note: This bit has no effect where the endpoint is being used for isochronous transfers. 728 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset Description 4 FLUSH W1S 0 Flush FIFO Value Description 0 No effect. 1 Flushes the next packet from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Important: 3 DATAERR RO 0 This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted. Data Error Value Description 0 Normal operation. 1 Indicates that RXRDY is set and the data packet has a CRC or bit-stuff error. This bit is cleared when RXRDY is cleared. Note: 2 OVER R/W 0 This bit is only valid when the endpoint is operating in Isochronous mode. In Bulk mode, it always returns zero. Overrun Value Description 0 No overrun error. 1 Indicates that an OUT packet cannot be loaded into the receive FIFO. Software must clear this bit. Note: 1 FULL RO 0 This bit is only valid when the endpoint is operating in Isochronous mode. In Bulk mode, it always returns zero. FIFO Full Value Description 0 The receive FIFO is not full. 1 No more packets can be loaded into the receive FIFO. July 17, 2014 729 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 0 RXRDY R/W 0 Description Receive Packet Ready Value Description 0 No data packet has been received. 1 A data packet has been received. The EPn bit in the USBRXIS register is also set in this situation. If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit is automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO. 730 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 65: USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 Register 66: USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 Register 67: USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 USBRXCSRHn is an 8-bit register that provides additional control and status bits for transfers through the currently selected receive endpoint. Host Device Host Mode USB Receive Control and Status Endpoint 1 High (USBRXCSRH1) Base 0x4005.0000 Offset 0x117 Type R/W, reset 0x00 7 6 5 AUTOCL AUTORQ DMAEN Type Reset R/W 0 R/W 0 4 3 2 PIDERR DMAMOD R/W 0 RO 0 1 0 DTWE DT reserved RO 0 RO 0 RO 0 R/W 0 Bit/Field Name Type Reset Description 7 AUTOCL R/W 0 Auto Clear Value Description 6 AUTORQ R/W 0 0 No effect. 1 Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using µDMA to unload the receive FIFO as data is read from the receive FIFO in 4 byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXPn register, see “DMA Operation” on page 670. Auto Request Value Description 0 No effect. 1 Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared. Note: This bit is automatically cleared when a short packet is received. July 17, 2014 731 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 5 DMAEN R/W 0 Description DMA Request Enable Value Description 0 Disables the µDMA request for the receive endpoint. 1 Enables the µDMA request for the receive endpoint. Note: 4 PIDERR RO 0 3 TX and 3 RX endpoints can be connected to the µDMA module. If this bit is set for a particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. PID Error Value Description 0 No error. 1 Indicates a PID error in the received packet of an isochronous transaction. This bit is ignored in bulk or interrupt transactions. 3 DMAMOD R/W 0 DMA Request Mode Value Description 0 An interrupt is generated after every µDMA packet transfer. 1 An interrupt is generated only after the entire μDMA transfer is complete. Note: 2 DTWE RO 0 This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Data Toggle Write Enable Value Description 0 The DT bit cannot be written. 1 Enables the current state of the receive endpoint data to be written (see DT bit). This bit is automatically cleared once the new value is written. 1 DT RO 0 Data Toggle When read, this bit indicates the current state of the receive data toggle. If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the receive endpoint. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 732 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Device Mode USB Receive Control and Status Endpoint 1 High (USBRXCSRH1) Type Reset 7 6 5 4 3 AUTOCL ISO DMAEN DISNYET / PIDERR Base 0x4005.0000 Offset 0x117 Type R/W, reset 0x00 2 DMAMOD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 1 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 7 AUTOCL R/W 0 Auto Clear Value Description 6 ISO R/W 0 0 No effect. 1 Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using µDMA to unload the receive FIFO as data is read from the receive FIFO in 4 byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXPn register, see “DMA Operation” on page 670. Isochronous Transfers Value Description 5 DMAEN R/W 0 0 Enables the receive endpoint for isochronous transfers. 1 Enables the receive endpoint for bulk/interrupt transfers. DMA Request Enable Value Description 0 Disables the µDMA request for the receive endpoint. 1 Enables the µDMA request for the receive endpoint. Note: 3 TX and 3 RX endpoints can be connected to the µDMA module. If this bit is set for a particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. July 17, 2014 733 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 4 DISNYET / PIDERR R/W 0 Description Disable NYET / PID Error Value Description 0 No effect. 1 For bulk or interrupt transactions: Disables the sending of NYET handshakes. When this bit is set, all successfully received packets are acknowledged, including at the point at which the FIFO becomes full. For isochronous transactions: Indicates a PID error in the received packet. 3 DMAMOD R/W 0 DMA Request Mode Value Description 0 An interrupt is generated after every µDMA packet transfer. 1 An interrupt is generated only after the entire μDMA transfer is complete. Note: 2:0 reserved RO 0x0 This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 734 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 68: USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 Register 69: USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 Register 70: USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 Note: Host Device The value returned changes as the FIFO is unloaded and is only valid while the RXRDY bit in the USBRXCSRLn register is set. USBRXCOUNTn is a 16-bit read-only register that holds the number of data bytes in the packet currently in line to be read from the receive FIFO. If the packet is transmitted as multiple bulk packets, the number given is for the combined packet. USB Receive Byte Count Endpoint 1 (USBRXCOUNT1) Base 0x4005.0000 Offset 0x118 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 COUNT Bit/Field Name Type Reset 15:13 reserved RO 0x0 12:0 COUNT RO 0x000 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Receive Packet Count Indicates the number of bytes in the receive packet. July 17, 2014 735 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 71: USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A Register 72: USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A Register 73: USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A USBTXTYPEn is an 8-bit register that must be written with the endpoint number to be targeted by the endpoint, the transaction protocol to use for the currently selected transmit endpoint, and its operating speed. Host USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1) Base 0x4005.0000 Offset 0x11A Type R/W, reset 0x00 7 6 SPEED Type Reset R/W 0 R/W 0 5 4 3 2 PROTO R/W 0 R/W 0 1 0 R/W 0 R/W 0 TEP R/W 0 R/W 0 Bit/Field Name Type Reset 7:6 SPEED R/W 0x0 Description Operating Speed This bit field specifies the operating speed of the target Device: Value Description 0x0 Default The target is assumed to be using the same connection speed as the USB controller. 5:4 PROTO R/W 0x0 0x1 Reserved 0x2 Full 0x3 Low Protocol Software must configure this bit field to select the required protocol for the transmit endpoint: Value Description 3:0 TEP R/W 0x0 0x0 Control 0x1 Isochronous 0x2 Bulk 0x3 Interrupt Target Endpoint Number Software must configure this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during Device enumeration. 736 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 74: USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B Register 75: USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B Register 76: USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B USBTXINTERVALn is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently selected transmit endpoint. For bulk endpoints, this register defines the number of frames after which the endpoint should time out on receiving a stream of NAK responses. Host The USBTXINTERVALn register value defines a number of frames, as follows: Transfer Type Interrupt Speed Valid values (m) Interpretation Low-Speed or Full-Speed 0x01 – 0xFF The polling interval is m frames. Isochronous Full-Speed 0x01 – 0x10 The polling interval is 2(m-1) frames. Bulk Full-Speed 0x02 – 0x10 The NAK Limit is 2(m-1) frames. A value of 0 or 1 disables the NAK timeout function. USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1) Base 0x4005.0000 Offset 0x11B Type R/W, reset 0x00 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 TXPOLL / NAKLMT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 7:0 TXPOLL / NAKLMT R/W 0x00 TX Polling / NAK Limit The polling interval for interrupt/isochronous transfers; the NAK limit for bulk transfers. See table above for valid entries; other values are reserved. July 17, 2014 737 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 77: USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C Register 78: USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C Register 79: USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C USBRXTYPEn is an 8-bit register that must be written with the endpoint number to be targeted by the endpoint, the transaction protocol to use for the currently selected receive endpoint, and its operating speed. Host USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1) Base 0x4005.0000 Offset 0x11C Type R/W, reset 0x00 7 6 SPEED Type Reset R/W 0 R/W 0 5 4 3 2 PROTO R/W 0 R/W 0 1 0 R/W 0 R/W 0 TEP R/W 0 R/W 0 Bit/Field Name Type Reset 7:6 SPEED R/W 0x0 Description Operating Speed This bit field specifies the operating speed of the target Device: Value Description 0x0 Default The target is assumed to be using the same connection speed as the USB controller. 5:4 PROTO R/W 0x0 0x1 Reserved 0x2 Full 0x3 Low Protocol Software must configure this bit field to select the required protocol for the receive endpoint: Value Description 3:0 TEP R/W 0x0 0x0 Control 0x1 Isochronous 0x2 Bulk 0x3 Interrupt Target Endpoint Number Software must set this value to the endpoint number contained in the receive endpoint descriptor returned to the USB controller during Device enumeration. 738 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 80: USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D Register 81: USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D Register 82: USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D USBRXINTERVALn is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently selected receive endpoint. For bulk endpoints, this register defines the number of frames after which the endpoint should time out on receiving a stream of NAK responses. Host The USBTXINTERVALn register value defines a number of frames, as follows: Transfer Type Interrupt Speed Valid values (m) Interpretation Low-Speed or Full-Speed 0x01 – 0xFF The polling interval is m frames. Isochronous Full-Speed 0x01 – 0x10 The polling interval is 2(m-1) frames. Bulk Full-Speed 0x02 – 0x10 The NAK Limit is 2(m-1) frames. A value of 0 or 1 disables the NAK timeout function. USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1) Base 0x4005.0000 Offset 0x11D Type R/W, reset 0x00 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 TXPOLL / NAKLMT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 7:0 TXPOLL / NAKLMT R/W 0x00 RX Polling / NAK Limit The polling interval for interrupt/isochronous transfers; the NAK limit for bulk transfers. See table above for valid entries; other values are reserved. July 17, 2014 739 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 83: USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset 0x304 Register 84: USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset 0x308 Register 85: USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset 0x30C This 16-bit read/write register is used in Host mode to specify the number of packets that are to be transferred in a block transfer of one or more bulk packets to receive endpoint n. The USB controller uses the value recorded in this register to determine the number of requests to issue where the AUTORQ bit in the USBRXCSRHn register has been set. See “IN Transactions as a Host” on page 667. Host Note: Multiple packets combined into a single bulk packet within the FIFO count as one packet. USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1) Base 0x4005.0000 Offset 0x304 Type R/W, reset 0x0000 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 COUNT Type Reset Bit/Field Name Type Reset 15:0 COUNT R/W 0x0000 Description Block Transfer Packet Count Sets the number of packets of the size defined by the MAXLOAD bit field that are to be transferred in a block transfer. Note: This is only used in Host mode when AUTORQ is set. The bit has no effect in Device mode or when AUTORQ is not set. 740 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 86: USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 USBRXDPKTBUFDIS is a 16-bit register that indicates which of the receive endpoints have disabled the double-packet buffer functionality (see the section called “Double-Packet Buffering” on page 663). Host Device USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) Base 0x4005.0000 Offset 0x340 Type R/W, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 EP3 EP2 EP1 reserved R/W 0 R/W 0 R/W 0 RO 0 Bit/Field Name Type Reset Description 15:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 EP3 R/W 0 EP3 RX Double-Packet Buffer Disable 2 EP2 R/W 0 EP2 RX Double-Packet Buffer Disable 1 EP1 R/W 0 EP1 RX Double-Packet Buffer Disable 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 741 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 87: USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 USBTXDPKTBUFDIS is a 16-bit register that indicates which of the transmit endpoints have disabled the double-packet buffer functionality (see the section called “Double-Packet Buffering” on page 662). Host Device USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS) Base 0x4005.0000 Offset 0x342 Type R/W, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 EP3 EP2 EP1 reserved R/W 0 R/W 0 R/W 0 RO 0 Bit/Field Name Type Reset Description 15:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 EP3 R/W 0 EP3 TX Double-Packet Buffer Disable 2 EP2 R/W 0 EP2 TX Double-Packet Buffer Disable 1 EP1 R/W 0 EP1 TX Double-Packet Buffer Disable 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 742 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 88: USB External Power Control (USBEPC), offset 0x400 Host Device This 32-bit register specifies the function of the two-pin external power interface (USB0EPEN and USB0PFLT). The assertion of the power fault input may generate an automatic action, as controlled by the hardware configuration registers. The automatic action is necessary because the fault condition may require a response faster than one provided by firmware. USB External Power Control (USBEPC) Base 0x4005.0000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset reserved Type Reset RO 0 PFLTACT Bit/Field Name Type Reset 31:10 reserved RO 0x0000.0 9:8 PFLTACT R/W 0x0 reserved PFLTAEN PFLTSEN PFLTEN R/W 0 RO 0 R/W 0 R/W 0 reserved EPENDE R/W 0 RO 0 R/W 0 EPEN R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power Fault Action This bit field specifies how the USB0EPEN signal is changed when detecting a USB power fault. Value Description 0x0 Unchanged USB0EPEN is controlled by the combination of the EPEN and EPENDE bits. 0x1 Tristate USB0EPEN is undriven (tristate). 0x2 Low USB0EPEN is driven Low. 0x3 High USB0EPEN is driven High. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 17, 2014 743 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 6 PFLTAEN R/W 0 Description Power Fault Action Enable This bit specifies whether a USB power fault triggers any automatic corrective action regarding the driven state of the USB0EPEN signal. Value Description 0 Disabled USB0EPEN is controlled by the combination of the EPEN and EPENDE bits. 1 Enabled The USB0EPEN output is automatically changed to the state specified by the PFLTACT field. 5 PFLTSEN R/W 0 Power Fault Sense This bit specifies the logical sense of the USB0PFLT input signal that indicates an error condition. The complementary state is the inactive state. Value Description 0 Low Fault If USB0PFLT is driven Low, the power fault is signaled internally (if enabled by the PFLTEN bit). 1 High Fault If USB0PFLT is driven High, the power fault is signaled internally (if enabled by the PFLTEN bit). 4 PFLTEN R/W 0 Power Fault Input Enable This bit specifies whether the USB0PFLT input signal is used in internal logic. Value Description 0 Not Used The USB0PFLT signal is ignored. 1 Used The USB0PFLT signal is used internally. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 744 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Bit/Field Name Type Reset 2 EPENDE R/W 0 Description EPEN Drive Enable This bit specifies whether the USB0EPEN signal is driven or undriven (tristate). When driven, the signal value is specified by the EPEN field. When not driven, the EPEN field is ignored and the USB0EPEN signal is placed in a high-impedance state. Value Description 0 Not Driven The USB0EPEN signal is high impedance. 1 Driven The USB0EPEN signal is driven to the logical value specified by the value of the EPEN field. The USB0EPEN signal is undriven at reset because the sense of the external power supply enable is unknown. By adding the high-impedance state, system designers may bias the power supply enable to the disabled state using a large resistor (100 kΩ) and later configure and drive the output signal to enable the power supply. 1:0 EPEN R/W 0x0 External Power Supply Enable Configuration This bit field specifies and controls the logical value driven on the USB0EPEN signal. Value Description 0x0 Power Enable Active Low The USB0EPEN signal is driven Low if the EPENDE bit is set. 0x1 Power Enable Active High The USB0EPEN signal is driven High if the EPENDE bit is set. 0x2-0x3 Reserved July 17, 2014 745 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 89: USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 This 32-bit register specifies the unmasked interrupt status of the two-pin external power interface. Host USB External Power Control Raw Interrupt Status (USBEPCRIS) Device 31 Base 0x4005.0000 Offset 0x404 Type RO, reset 0x0000.0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PF RO 0 RO 0 0 PF RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Power Fault Interrupt Status Value Description 1 A Power Fault status has been detected. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the PF bit in the USBEPCISC register. 746 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 90: USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 This 32-bit register specifies the interrupt mask of the two-pin external power interface. Host USB External Power Control Interrupt Mask (USBEPCIM) Device Base 0x4005.0000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PF R/W 0 RO 0 PF RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Power Fault Interrupt Mask Value Description 1 The raw interrupt signal from a detected power fault is sent to the interrupt controller. 0 A detected power fault does not affect the interrupt status. July 17, 2014 747 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 91: USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C This 32-bit register specifies the masked interrupt status of the two-pin external power interface. It also provides a method to clear the interrupt state. Host Device USB External Power Control Interrupt Status and Clear (USBEPCISC) Base 0x4005.0000 Offset 0x40C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PF R/W1C 0 RO 0 0 PF RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Power Fault Interrupt Status and Clear Value Description 1 The PF bits in the USBEPCRIS and USBEPCIM registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the PF bit in the USBEPCRIS register. 748 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 92: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 The USBDRRIS 32-bit register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. Host Device USB Device RESUME Raw Interrupt Status (USBDRRIS) Base 0x4005.0000 Offset 0x410 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 RESUME RO 0 RO 0 0 RESUME RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RESUME Interrupt Status Value Description 1 A RESUME status has been detected. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the RESUME bit in the USBDRISC register. July 17, 2014 749 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 93: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 Host Device The USBDRIM 32-bit register is the masked interrupt status register. On a read, this register gives the current value of the mask on the corresponding interrupt. Setting a bit sets the mask, preventing the interrupt from being signaled to the interrupt controller. Clearing a bit clears the corresponding mask, enabling the interrupt to be sent to the interrupt controller. USB Device RESUME Interrupt Mask (USBDRIM) Base 0x4005.0000 Offset 0x414 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RESUME R/W 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RESUME R/W 0 RESUME Interrupt Mask Value Description 1 The raw interrupt signal from a detected RESUME is sent to the interrupt controller. This bit should only be set when a SUSPEND has been detected (the SUSPEND bit in the USBIS register is set). 0 A detected RESUME does not affect the interrupt status. 750 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Register 94: USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 The USBDRISC 32-bit register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. Host Device USB Device RESUME Interrupt Status and Clear (USBDRISC) Base 0x4005.0000 Offset 0x418 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 RESUME R/W1C 0 RO 0 0 RESUME RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RESUME Interrupt Status and Clear Value Description 1 The RESUME bits in the USBDRRIS and USBDRCIM registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the RESUME bit in the USBDRCRIS register. July 17, 2014 751 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 95: USB General-Purpose Control and Status (USBGPCS), offset 0x41C USBGPCS provides the state of the internal ID signal. Host USB General-Purpose Control and Status (USBGPCS) Device 31 Base 0x4005.0000 Offset 0x41C Type R/W, reset 0x0000.0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 DEVMOD R/W 0 RO 0 0 DEVMOD RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Mode This bit is used to control the state of the internal ID signal. In Device mode this bit is ignored (assumed set). Value Description 0 Host mode 1 Device mode 752 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 18 Pin Diagram The LM3S5732 microcontroller pin diagram is shown below. Figure 18-1. 64-Pin LQFP Package Pin Diagram July 17, 2014 753 Texas Instruments-Production Data Signal Tables 19 Signal Tables Important: All multiplexed pins are GPIOs by default, with the exception of the four JTAG pins (PC[3:0]) which default to the JTAG functionality. The following tables list the signals available for each pin. Functionality is enabled by software with the GPIOAFSEL register. All digital inputs are Schmitt triggered. ■ ■ ■ ■ ■ 19.1 Signals by Pin Number Signals by Signal Name Signals by Function, Except for GPIO GPIO Pins and Alternate Functions Connections for Unused Signals Signals by Pin Number Table 19-1. Signals by Pin Number Pin Number Pin Name Pin Type a Buffer Type PE3 I/O TTL ADC0 I Analog PE2 I/O TTL 1 2 Description GPIO port E bit 3. Analog-to-digital converter input 0. GPIO port E bit 2. ADC1 I Analog Analog-to-digital converter input 1. VDDA - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in “Recommended DC Operating Conditions” on page 766, regardless of system implementation. GNDA - Power The ground reference for the analog circuits (ADC, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. 3 4 PE1 I/O TTL ADC2 I Analog PE0 I/O TTL ADC3 I Analog Analog-to-digital converter input 3. LDO - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. The LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). PE4 I/O TTL GPIO port E bit 4. CCP3 I/O TTL Capture/Compare/PWM 3. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. GND - Power Ground reference for logic and I/O pins. PC4 I/O TTL GPIO port C bit 4. CCP2 I/O TTL Capture/Compare/PWM 2. 12 VDD - Power Positive supply for I/O and some logic. 13 GND - Power Ground reference for logic and I/O pins. 5 6 7 8 9 10 11 GPIO port E bit 1. Analog-to-digital converter input 2. GPIO port E bit 0. 754 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 19-1. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type PC5 I/O TTL GPIO port C bit 5. 14 USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. PC6 I/O TTL GPIO port C bit 6. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PC7 I/O TTL GPIO port C bit 7. CCP4 I/O TTL Capture/Compare/PWM 4. PA0 I/O TTL GPIO port A bit 0. U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. PA1 I/O TTL GPIO port A bit 1. U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. 15 16 17 18 PA2 I/O TTL GPIO port A bit 2. SSI0Clk I/O TTL SSI module 0 clock. 19 PA3 I/O TTL GPIO port A bit 3. SSI0Fss I/O TTL SSI module 0 frame signal. PA4 I/O TTL GPIO port A bit 4. SSI0Rx I TTL SSI module 0 receive. PA5 I/O TTL GPIO port A bit 5. SSI0Tx O TTL SSI module 0 transmit. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. GND - Power Ground reference for logic and I/O pins. PA6 I/O TTL GPIO port A bit 6. I2C1SCL I/O OD I2C module 1 clock. 20 21 22 23 24 Description 25 PA7 I/O TTL GPIO port A bit 7. I2C1SDA I/O OD I2C module 1 data. 26 PB3 I/O TTL GPIO port B bit 3. I2C0SDA I/O OD I2C module 0 data. VDD - Power Positive supply for I/O and some logic. 29 GND - Power Ground reference for logic and I/O pins. 30 OSC0 I Analog Main oscillator crystal input or an external clock reference input. OSC1 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. WAKE I TTL An external input that brings the processor out of Hibernate mode when asserted. HIB O OD An output that indicates the processor is in Hibernate mode. XOSC0 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. 27 28 31 32 33 34 35 July 17, 2014 755 Texas Instruments-Production Data Signal Tables Table 19-1. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type Description GND - Power Ground reference for logic and I/O pins. VBAT - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. 39 GND - Power Ground reference for logic and I/O pins. 40 RST I TTL System reset input. PB0 I/O TTL GPIO port B bit 0. 41 U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. PB1 I/O TTL GPIO port B bit 1. 42 U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. 43 VDD - Power Positive supply for I/O and some logic. 44 GND - Power Ground reference for logic and I/O pins. USB0DM I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. PB2 I/O TTL GPIO port B bit 2. I2C0SCL I/O OD I2C module 0 clock. USB0RBIAS O Analog PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI. PC1 I/O TTL GPIO port C bit 1. SWDIO I/O TTL JTAG TMS and SWDIO. TMS I/O TTL JTAG TMS and SWDIO. PC0 I/O TTL GPIO port C bit 0. SWCLK I TTL JTAG/SWD CLK. TCK I TTL JTAG/SWD CLK. GND - Power Ground reference for logic and I/O pins. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. PB7 I/O TTL GPIO port B bit 7. NMI I TTL Non-maskable interrupt. 36 37 38 45 46 47 48 49 50 51 52 53 54 55 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. PB6 I/O TTL GPIO port B bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. PB5 I/O TTL GPIO port B bit 5. CCP0 I/O TTL Capture/Compare/PWM 0. 56 57 756 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 19-1. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type 58 PB4 I/O TTL 59 VDD - Power Positive supply for I/O and some logic. 60 GND - Power Ground reference for logic and I/O pins. GPIO port B bit 4. PD0 I/O TTL CAN0Rx I Analog 61 GPIO port D bit 0. PD1 I/O TTL CAN0Tx O Analog PD2 I/O TTL ADC5 I Analog PD3 I/O TTL ADC4 I Analog 62 63 64 Description CAN module 0 receive. GPIO port D bit 1. CAN module 0 transmit. GPIO port D bit 2. Analog-to-digital converter input 5. GPIO port D bit 3. Analog-to-digital converter input 4. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 19.2 Signals by Signal Name Table 19-2. Signals by Signal Name a Pin Name Pin Number Pin Type Buffer Type ADC0 1 I Analog Description Analog-to-digital converter input 0. ADC1 2 I Analog Analog-to-digital converter input 1. ADC2 5 I Analog Analog-to-digital converter input 2. ADC3 6 I Analog Analog-to-digital converter input 3. ADC4 64 I Analog Analog-to-digital converter input 4. ADC5 63 I Analog Analog-to-digital converter input 5. CAN0Rx 61 I Analog CAN module 0 receive. CAN0Tx 62 O Analog CAN module 0 transmit. CCP0 57 I/O TTL Capture/Compare/PWM 0. CCP1 56 I/O TTL Capture/Compare/PWM 1. CCP2 11 I/O TTL Capture/Compare/PWM 2. CCP3 8 I/O TTL Capture/Compare/PWM 3. CCP4 16 I/O TTL Capture/Compare/PWM 4. GND 10 13 24 29 36 39 44 53 60 - Power Ground reference for logic and I/O pins. GNDA 4 - Power The ground reference for the analog circuits (ADC, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. HIB 33 O OD An output that indicates the processor is in Hibernate mode. I2C0SCL 47 I/O OD I2C module 0 clock. July 17, 2014 757 Texas Instruments-Production Data Signal Tables Table 19-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description I2C0SDA 27 I/O OD I2C module 0 data. I2C1SCL 25 I/O OD I2C module 1 clock. I2C1SDA 26 I/O OD I2C module 1 data. LDO 7 - Power NMI 55 I TTL OSC0 30 I Analog Main oscillator crystal input or an external clock reference input. OSC1 31 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. PA0 17 I/O TTL GPIO port A bit 0. PA1 18 I/O TTL GPIO port A bit 1. PA2 19 I/O TTL GPIO port A bit 2. PA3 20 I/O TTL GPIO port A bit 3. PA4 21 I/O TTL GPIO port A bit 4. PA5 22 I/O TTL GPIO port A bit 5. PA6 25 I/O TTL GPIO port A bit 6. PA7 26 I/O TTL GPIO port A bit 7. PB0 41 I/O TTL GPIO port B bit 0. PB1 42 I/O TTL GPIO port B bit 1. PB2 47 I/O TTL GPIO port B bit 2. PB3 27 I/O TTL GPIO port B bit 3. PB4 58 I/O TTL GPIO port B bit 4. PB5 57 I/O TTL GPIO port B bit 5. PB6 56 I/O TTL GPIO port B bit 6. PB7 55 I/O TTL GPIO port B bit 7. PC0 52 I/O TTL GPIO port C bit 0. PC1 51 I/O TTL GPIO port C bit 1. PC2 50 I/O TTL GPIO port C bit 2. PC3 49 I/O TTL GPIO port C bit 3. PC4 11 I/O TTL GPIO port C bit 4. PC5 14 I/O TTL GPIO port C bit 5. PC6 15 I/O TTL GPIO port C bit 6. PC7 16 I/O TTL GPIO port C bit 7. PD0 61 I/O TTL GPIO port D bit 0. PD1 62 I/O TTL GPIO port D bit 1. PD2 63 I/O TTL GPIO port D bit 2. PD3 64 I/O TTL GPIO port D bit 3. PE0 6 I/O TTL GPIO port E bit 0. PE1 5 I/O TTL GPIO port E bit 1. Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. The LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). Non-maskable interrupt. 758 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 19-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description PE2 2 I/O TTL GPIO port E bit 2. PE3 1 I/O TTL GPIO port E bit 3. PE4 8 I/O TTL GPIO port E bit 4. RST 40 I TTL System reset input. SSI0Clk 19 I/O TTL SSI module 0 clock. SSI0Fss 20 I/O TTL SSI module 0 frame signal. SSI0Rx 21 I TTL SSI module 0 receive. SSI0Tx 22 O TTL SSI module 0 transmit. SWCLK 52 I TTL JTAG/SWD CLK. SWDIO 51 I/O TTL JTAG TMS and SWDIO. SWO 49 O TTL JTAG TDO and SWO. TCK 52 I TTL JTAG/SWD CLK. TDI 50 I TTL JTAG TDI. TDO 49 O TTL JTAG TDO and SWO. TMS 51 I/O TTL JTAG TMS and SWDIO. U0Rx 17 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 18 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Rx 41 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 42 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. USB0DM 45 I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP 46 I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. USB0EPEN 14 O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0PFLT 15 I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. USB0RBIAS 48 O Analog 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. VBAT 37 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. VDD 12 28 43 59 - Power Positive supply for I/O and some logic. VDD25 9 23 38 54 - Power Positive supply for most of the logic function, including the processor core and most peripherals. July 17, 2014 759 Texas Instruments-Production Data Signal Tables Table 19-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description VDDA 3 - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in “Recommended DC Operating Conditions” on page 766, regardless of system implementation. WAKE 32 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 34 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 35 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 19.3 Signals by Function, Except for GPIO Table 19-3. Signals by Function, Except for GPIO Function Pin Name Pin Type Buffer Type ADC0 1 I Analog Analog-to-digital converter input 0. ADC1 2 I Analog Analog-to-digital converter input 1. ADC2 5 I Analog Analog-to-digital converter input 2. ADC3 6 I Analog Analog-to-digital converter input 3. ADC4 64 I Analog Analog-to-digital converter input 4. ADC5 63 I Analog Analog-to-digital converter input 5. CAN0Rx 61 I Analog CAN module 0 receive. CAN0Tx 62 O Analog CAN module 0 transmit. CCP0 57 I/O TTL Capture/Compare/PWM 0. CCP1 56 I/O TTL Capture/Compare/PWM 1. CCP2 11 I/O TTL Capture/Compare/PWM 2. CCP3 8 I/O TTL Capture/Compare/PWM 3. CCP4 16 I/O TTL Capture/Compare/PWM 4. HIB 33 O OD An output that indicates the processor is in Hibernate mode. VBAT 37 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. WAKE 32 I TTL An external input that brings the processor out of Hibernate mode when asserted. XOSC0 34 I Analog Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a crystal or a 32.768-kHz oscillator for the Hibernation module RTC. XOSC1 35 O Analog Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. ADC Controller Area Network General-Purpose Timers a Pin Number Hibernate Description 760 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 19-3. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Type a Buffer Type Description I2C0SCL 47 I/O OD I2C I2C0SDA 27 I/O OD I2C module 0 data. I2C1SCL 25 I/O OD I2C module 1 clock. I2C1SDA 26 I/O OD I2C module 1 data. SWCLK 52 I TTL JTAG/SWD CLK. SWDIO 51 I/O TTL JTAG TMS and SWDIO. SWO 49 O TTL JTAG TDO and SWO. TCK 52 I TTL JTAG/SWD CLK. TDI 50 I TTL JTAG TDI. TDO 49 O TTL JTAG TDO and SWO. TMS 51 I/O TTL JTAG TMS and SWDIO. GND 10 13 24 29 36 39 44 53 60 - Power Ground reference for logic and I/O pins. GNDA 4 - Power The ground reference for the analog circuits (ADC, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. LDO 7 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. The LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). VDD 12 28 43 59 - Power Positive supply for I/O and some logic. VDD25 9 23 38 54 - Power Positive supply for most of the logic function, including the processor core and most peripherals. VDDA 3 - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in “Recommended DC Operating Conditions” on page 766, regardless of system implementation. SSI0Clk 19 I/O TTL SSI module 0 clock. SSI0Fss 20 I/O TTL SSI module 0 frame signal. SSI0Rx 21 I TTL SSI module 0 receive. SSI0Tx 22 O TTL SSI module 0 transmit. I2C JTAG/SWD/SWO Pin Number Power SSI July 17, 2014 module 0 clock. 761 Texas Instruments-Production Data Signal Tables Table 19-3. Signals by Function, Except for GPIO (continued) Function System Control & Clocks Pin Name a Pin Number Pin Type NMI 55 I TTL OSC0 30 I Analog Main oscillator crystal input or an external clock reference input. OSC1 31 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 40 I TTL System reset input. U0Rx 17 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 18 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Rx 41 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 42 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. USB0DM 45 I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP 46 I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. USB0EPEN 14 O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0PFLT 15 I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. USB0RBIAS 48 O Analog UART Buffer Type Description Non-maskable interrupt. USB 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 19.4 GPIO Pins and Alternate Functions Table 19-4. GPIO Pins and Alternate Functions IO Pin Number Multiplexed Function PA0 17 U0Rx PA1 18 U0Tx PA2 19 SSI0Clk PA3 20 SSI0Fss PA4 21 SSI0Rx PA5 22 SSI0Tx PA6 25 I2C1SCL PA7 26 I2C1SDA PB0 41 U1Rx PB1 42 U1Tx PB2 47 I2C0SCL PB3 27 I2C0SDA PB4 58 PB5 57 Multiplexed Function CCP0 762 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 19-4. GPIO Pins and Alternate Functions (continued) 19.5 IO Pin Number Multiplexed Function Multiplexed Function PB6 56 CCP1 PB7 55 NMI PC0 52 TCK SWCLK PC1 51 TMS SWDIO PC2 50 TDI PC3 49 TDO PC4 11 CCP2 PC5 14 USB0EPEN PC6 15 USB0PFLT PC7 16 CCP4 PD0 61 CAN0Rx PD1 62 CAN0Tx PD2 63 ADC5 PD3 64 ADC4 PE0 6 ADC3 PE1 5 ADC2 PE2 2 ADC1 PE3 1 ADC0 PE4 8 CCP3 SWO Connections for Unused Signals Table 19-5 on page 763 shows how to handle signals for functions that are not used in a particular system implementation for devices that are in a 64-pin LQFP package. Two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx register. Table 19-5. Connections for Unused Signals (64-pin LQFP) Function GPIO Hibernate No Connects System Control Signal Name Pin Number Acceptable Practice Preferred Practice All unused GPIOs - NC GND HIB 33 NC NC VBAT 37 NC GND WAKE 32 NC GND XOSC0 34 NC GND XOSC1 35 NC NC NC - NC NC OSC0 30 NC GND OSC1 31 NC NC RST 40 Pull up as shown in Figure 5-1 on page 173 Connect through a capacitor to GND as close to pin as possible July 17, 2014 763 Texas Instruments-Production Data Signal Tables Table 19-5. Connections for Unused Signals (64-pin LQFP) (continued) Function USB Signal Name Pin Number Acceptable Practice Preferred Practice USB0RBIAS 48 Connect to GND through 10-kΩ resistor. Connect to GND through 10-kΩ resistor. USB0DM 45 NC GND USB0DP 46 NC GND 764 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 20 Operating Characteristics Table 20-1. Temperature Characteristics Characteristic Symbol Value Industrial operating temperature range TA -40 to +85 Unit °C Unpowered storage temperature range TS -65 to +150 °C Table 20-2. Thermal Characteristics Characteristic a Thermal resistance (junction to ambient) b Junction temperature Symbol Value ΘJA 37 Unit TJ TA + (P • ΘJA) °C/W °C a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator. b. Power dissipation is a function of temperature. a Table 20-3. ESD Absolute Maximum Ratings Parameter Name VESDHBM Min Nom Max Unit - - 2.0 kV VESDCDM - - 1.0 kV VESDMM - - 100 V a. All Stellaris parts are ESD tested following the JEDEC standard. July 17, 2014 765 Texas Instruments-Production Data Electrical Characteristics 21 Electrical Characteristics 21.1 DC Characteristics 21.1.1 Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings. Table 21-1. Maximum Ratings a Characteristic Symbol Value Unit Min Max VDD 0 4 V Core supply voltage (VDD25) VDD25 0 3 V Analog supply voltage (VDDA) VDDA 0 4 V Battery supply voltage (VBAT) VBAT 0 4 V I/O supply voltage (VDD) Input voltage Input voltage for a GPIO configured as an analog input Maximum current per output pins Maximum input voltage on a non-power pin when the microcontroller is unpowered -0.3 5.5 V -0.3 VDD + 0.3 V I - 25 mA VNON - 300 mV VIN a. Voltages are measured with respect to GND. Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either GND or VDD). 21.1.2 Recommended DC Operating Conditions For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package with the total number of high-current GPIO outputs not exceeding four for the entire package. Table 21-2. Recommended DC Operating Conditions Parameter Parameter Name Min Nom Max Unit VDD I/O supply voltage 3.0 3.3 3.6 V VDD25 Core supply voltage 2.25 2.5 2.75 V VDDA Analog supply voltage 3.0 3.3 3.6 V VBAT Battery supply voltage 2.3 3.0 3.6 V VIH High-level input voltage 2.0 - 5.0 V VIL Low-level input voltage -0.3 - 1.3 V 766 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 21-2. Recommended DC Operating Conditions (continued) Parameter Parameter Name Min Nom a VOH Max Unit High-level output voltage 2.4 VOLa Low-level output voltage - - - V - 0.4 V 2-mA Drive 4-mA Drive 2.0 - - mA 4.0 - - mA 8-mA Drive 8.0 - - mA 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA High-level source current, VOH=2.4 V IOH Low-level sink current, VOL=0.4 V IOL a. VOL and VOH shift to 1.2 V when using high-current GPIOs. 21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics Table 21-3. LDO Regulator Characteristics Parameter VLDOOUT Min Nom Max Unit Programmable internal (logic) power supply output value 2.25 2.5 2.75 V Output voltage accuracy - 2% - % tPON Power-on time - - 100 µs tON Time on - - 200 µs tOFF 21.1.4 Parameter Name Time off - - 100 µs VSTEP Step programming incremental voltage - 50 - mV CLDO External filter capacitor size for internal power supply 1.0 - 3.0 µF GPIO Module Characteristics Table 21-4. GPIO Module DC Characteristics Parameter Min Nom Max Unit RGPIOPU GPIO internal pull-up resistor 50 - 110 kΩ RGPIOPD GPIO internal pull-down resistor 55 - 180 kΩ - - 2 µA ILKG Parameter Name a GPIO input leakage current a. The leakage current is measured with GND or VDD applied to the corresponding pin(s). The leakage of digital port pins is measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled. 21.1.5 Power Specifications The power measurements specified in the tables that follow are run on the core processor using SRAM with the following specifications (except as noted): ■ VDD = 3.3 V ■ VDD25 = 2.50 V July 17, 2014 767 Texas Instruments-Production Data Electrical Characteristics ■ VBAT = 3.0 V ■ VDDA = 3.3 V ■ Temperature = 25°C ■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator ■ Main oscillator (MOSC) = enabled ■ Internal oscillator (IOSC) = disabled Table 21-5. Detailed Power Specifications Parameter Parameter Name Run mode 1 (Flash loop) Conditions VDD25 = 2.50 V 3.3 V VDD, VDDA 2.5 V VDD25 Nom Max Nom 5.8 pending 3.0 pendinga 56 Unit Nom Max 129 pendinga 0 pendinga mA pendinga 0 pendinga mA 5.8 pendinga 127 pendinga 0 pendinga mA 3.0 pendinga 49 pendinga 0 pendinga mA 3.0 pendinga 22 pendinga 0 pendinga mA 0.19 pendinga 0.10 pendinga 0 pendinga mA a Max 3.0 V VBAT Code= while(1){} executed out of Flash Peripherals = All ON System Clock = 50 MHz (with PLL) Run mode 2 (Flash loop) VDD25 = 2.50 V Code= while(1){} executed out of Flash Peripherals = All OFF IDD_RUN System Clock = 50 MHz (with PLL) Run mode 1 (SRAM loop) VDD25 = 2.50 V Code= while(1){} executed in SRAM Peripherals = All ON System Clock = 50 MHz (with PLL) Run mode 2 (SRAM loop) VDD25 = 2.50 V Code= while(1){} executed in SRAM Peripherals = All OFF System Clock = 50 MHz (with PLL) IDD_SLEEP Sleep mode VDD25 = 2.50 V Peripherals = All OFF System Clock = 50 MHz (with PLL) IDD_DEEPSLEEP Deep-Sleep mode LDO = 2.25 V Peripherals = All OFF System Clock = IOSC30KHZ/64 768 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 21-5. Detailed Power Specifications (continued) Parameter Parameter Name IDD_HIBERNATE Hibernate mode Conditions 3.3 V VDD, VDDA VBAT = 3.0 V 2.5 V VDD25 3.0 V VBAT Unit Nom Max Nom Max Nom Max 0 0 0 0 16 pendinga µA VDD = 0 V VDD25 = 0 V VDDA = 0 V Peripherals = All OFF System Clock = OFF Hibernate Module = 32 kHz a. Pending characterization completion. 21.1.6 Flash Memory Characteristics Table 21-6. Flash Memory Characteristics Parameter Parameter Name Min Nom Max Unit 10,000 100,000 - cycles Data retention at average operating temperature of 85˚C 10 - - years TPROG Word program time 20 - - µs TERASE Page erase time 20 - - ms TME Mass erase time - - 250 ms PECYC Number of guaranteed program/erase cycles a before failure TRET a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 21.1.7 Hibernation Table 21-7. Hibernation Module DC Characteristics Parameter 21.1.8 Parameter Name Value Unit VLOWBAT Low battery detect voltage 2.35 V RWAKEPU WAKE internal pull-up resistor 200 kΩ USB ® The Stellaris USB controller DC electrical specifications are compliant with the “Universal Serial Bus Specification Rev. 2.0” (full-speed and low-speed support). Some components of the USB system are integrated within the LM3S5732 microcontroller and specific to the Stellaris microcontroller design. These components are specified in Table 21-8 on page 769. Table 21-8. USB Controller DC Characteristics Parameter RBIAS Parameter Name Value of the pull-down resistor on the USB0RBIAS pin July 17, 2014 Value Unit 9.1K ± 1 % Ω 769 Texas Instruments-Production Data Electrical Characteristics 21.2 AC Characteristics 21.2.1 Load Conditions Unless otherwise specified, the following conditions are true for all timing measurements. Timing measurements are for 4-mA drive strength. Figure 21-1. Load Conditions CL = 50 pF pin GND 21.2.2 Clocks Table 21-9. Phase Locked Loop (PLL) Characteristics Parameter Parameter Name a fref_crystal Crystal reference referencea Min Nom Max Unit 3.579545 - 16.384 MHz fref_ext External clock 3.579545 - 16.384 MHz fpll PLL frequency - 400 - MHz TREADY PLL lock time - - 0.5 ms b a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration (RCC) register. b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. Table 21-10 on page 770 shows the actual frequency of the PLL based on the crystal frequency used (defined by the XTAL field in the RCC register). Table 21-10. Actual PLL Frequency XTAL Crystal Frequency (MHz) PLL Frequency (MHz) Error 0x04 0x05 3.5795 400.904 0.0023% 3.6864 398.1312 0.0047% 0x06 4.0 400 - 0x07 4.096 401.408 0.0035% 0x08 4.9152 398.1312 0.0047% 0x09 5.0 400 - 0x0A 5.12 399.36 0.0016% 0x0B 6.0 400 - 0x0C 6.144 399.36 0.0016% 0x0D 7.3728 398.1312 0.0047% 0x0E 8.0 400 0.0047% 0x0F 8.192 398.6773333 0.0033% 0x10 10.0 400 - 0x11 12.0 400 - 770 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Table 21-10. Actual PLL Frequency (continued) XTAL Crystal Frequency (MHz) PLL Frequency (MHz) Error 0x12 12.288 401.408 0.0035% 0x13 13.56 397.76 0.0056% 0x14 14.318 400.90904 0.0023% 0x15 16.0 400 - 0x16 16.384 404.1386667 0.010% Table 21-11. Clock Characteristics Parameter Name Min Nom Max Unit fIOSC Parameter Internal 12 MHz oscillator frequency 8.4 12 15.6 MHz fIOSC30KHZ Internal 30 KHz oscillator frequency 15 30 45 KHz fXOSC Hibernation module oscillator frequency - 4.194304 - MHz fXOSC_XTAL Crystal reference for hibernation oscillator - 4.194304 - MHz fXOSC_EXT External clock reference for hibernation module - 32.768 - KHz fMOSC Main oscillator frequency 1 - 16.384 MHz tMOSC_per Main oscillator period 61 - 1000 ns fref_crystal_bypass Crystal reference using the main oscillator a (PLL in BYPASS mode) 1 - 16.384 MHz fref_ext_bypass External clock reference (PLL in BYPASS a mode) 0 - 50 MHz fsystem_clock System clock 0 - 50 MHz a. The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. Table 21-12. Crystal Characteristics Parameter Name Value Frequency a Frequency tolerance Oscillation mode Units 16 12 8 6 4 3.5 MHz ±50 ±50 ±50 ±50 ±50 ±50 ppm Parallel Parallel Parallel Parallel Parallel Parallel - Motional capacitance (typ) 13.9 18.5 27.8 37.0 55.6 63.5 pF Motional inductance (typ) 7.15 9.5 14.3 19.1 28.6 32.7 mH Equivalent series resistance (max) 80 100 120 160 200 220 Ω Shunt capacitance (max) 10 10 10 10 10 10 pF Load capacitance (typ) 16 16 16 16 16 16 pF Drive level (typ) 100 100 100 100 100 100 µW a. This tolerance provides a guard band for temperature stability and aging drift. 21.2.2.1 System Clock Specifications with ADC Operation Table 21-13. System Clock Characteristics with ADC Operation Parameter fsysadc Parameter Name System clock frequency when the ADC module is operating (when PLL is bypassed) July 17, 2014 Min Nom Max Unit 16 - - MHz 771 Texas Instruments-Production Data Electrical Characteristics 21.2.2.2 System Clock Specification with USB Operation Table 21-14. System Clock Characteristics with USB Operation Parameter Fsysusb 21.2.3 Parameter Name Min Nom Max Unit 30 - - MHz System clock frequency when the USB module is operating (note that MOSC must be supplied with a clock source) JTAG and Boundary Scan Table 21-15. JTAG Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit J1 fTCK TCK operational clock frequency 0 - 10 MHz J2 tTCK TCK operational clock period J3 tTCK_LOW TCK clock Low time 100 - - ns - tTCK/2 - ns J4 tTCK_HIGH TCK clock High time - tTCK/2 - ns J5 J6 tTCK_R TCK rise time 0 - 10 ns tTCK_F TCK fall time 0 - 10 ns J7 tTMS_SU TMS setup time to TCK rise 20 - - ns J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns J9 tTDI_SU TDI setup time to TCK rise 25 - - ns J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns 2-mA drive 23 35 ns 4-mA drive 15 26 ns J11 t TDO_ZDV J12 t TDO_DV J13 t TDO_DVZ TCK fall to Data Valid from High-Z TCK fall to Data Valid from Data Valid TCK fall to High-Z from Data Valid - 14 25 ns 8-mA drive with slew rate control 8-mA drive 18 29 ns 2-mA drive 21 35 ns 14 25 ns 13 24 ns 8-mA drive with slew rate control 18 28 ns 2-mA drive 9 11 ns 7 9 ns 6 8 ns 7 9 ns 4-mA drive - 8-mA drive 4-mA drive - 8-mA drive 8-mA drive with slew rate control Figure 21-2. JTAG Test Clock Input Timing J2 J3 J4 TCK J6 J5 772 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 21-3. JTAG Test Access Port (TAP) Timing TCK J7 TMS TDI J8 J8 TMS Input Valid TMS Input Valid J9 J9 J10 TDI Input Valid J11 J10 TDI Input Valid J12 TDO 21.2.4 J7 TDO Output Valid J13 TDO Output Valid Reset Table 21-16. Reset Characteristics Parameter No. Parameter Parameter Name R1 VTH Reset threshold R2 VBTH Brown-Out threshold Min Nom Max Unit - 2.0 - V 2.85 2.9 2.95 V R3 TPOR Power-On Reset timeout - 10 - ms R4 TBOR Brown-Out timeout - 500 - µs R5 TIRPOR 6 - 11 ms Internal reset timeout after POR a R6 TIRBOR Internal reset timeout after BOR 0 - 1 µs R7 TIRHWR Internal reset timeout after hardware reset (RST pin) 0 - 1 ms R8 TIRSWR Internal reset timeout after software-initiated system reset a 2.5 - 20 µs R9 TIRWDR Internal reset timeout after watchdog reseta R10 TVDDRISE R11 TMIN 2.5 - 20 µs Supply voltage (VDD) rise time (0V-3.3V), power on reset - - 100 ms Supply voltage (VDD) rise time (0V-3.3V), waking from hibernation - - 250 µs Minimum RST pulse width 2 - - µs a. 20 * t MOSC_per Figure 21-4. External Reset Timing (RST) RST R11 R7 /Reset (Internal) July 17, 2014 773 Texas Instruments-Production Data Electrical Characteristics Figure 21-5. Power-On Reset Timing R1 VDD R3 /POR (Internal) R5 /Reset (Internal) Figure 21-6. Brown-Out Reset Timing R2 VDD R4 /BOR (Internal) R6 /Reset (Internal) Figure 21-7. Software Reset Timing SW Reset R8 /Reset (Internal) Figure 21-8. Watchdog Reset Timing WDOG Reset (Internal) R9 /Reset (Internal) 774 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 21.2.5 Sleep Modes a Table 21-17. Sleep Modes AC Characteristics Parameter No Parameter Min Nom Max Unit D1 tWAKE_S Time to wake from interrupt in sleep or deep-sleep mode, not using the PLL Parameter Name - - 7 system clocks D2 tWAKE_PLL_S Time to wake from interrupt in sleep or deep-sleep mode when using the PLL - - TREADY ms a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode. 21.2.6 Hibernation Module The Hibernation Module requires special system implementation considerations since it is intended to power-down all other sections of its host device. The system power-supply distribution and interfaces to the device must be driven to 0 VDC or powered down with the same external voltage regulator controlled by HIB. The external voltage regulators controlled by HIB must have a settling time of 250 μs or less. Table 21-18. Hibernation Module AC Characteristics Parameter No Parameter H1 tHIB_LOW H2 tHIB_HIGH H3 tWAKE_ASSERT H4 tWAKETOHIB Parameter Name Min Nom Max Unit Internal 32.768 KHz clock reference rising edge to /HIB asserted - 200 - μs Internal 32.768 KHz clock reference rising edge to /HIB deasserted - 30 - μs /WAKE assertion time 62 - - μs /WAKE assert to /HIB desassert 62 - 124 μs a H5 tXOSC_SETTLE XOSC settling time 20 - - ms H6 tHIB_REG_ACCESS Access time to or from a non-volatile register in HIB module to complete 92 - - μs H7 tHIB_TO_VDD HIB deassert to VDD and VDD25 at minimum operational level - - 250 μs a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance). Figure 21-9. Hibernation Module Timing 32.768 KHz (internal) H1 H2 HIB H4 WAKE H3 21.2.7 General-Purpose I/O (GPIO) Note: All GPIOs are 5 V-tolerant. July 17, 2014 775 Texas Instruments-Production Data Electrical Characteristics Table 21-19. GPIO Characteristics Parameter Parameter Name Condition tGPIOR tGPIOF Min GPIO Rise Time (from 20% to 80% of VDD) Nom Max Unit 2-mA drive 17 26 ns 4-mA drive 9 13 ns 8-mA drive - 6 9 ns 8-mA drive with slew rate control 10 12 ns 2-mA drive 17 25 ns 4-mA drive 8 12 ns 6 10 ns 11 13 ns GPIO Fall Time (from 80% to 20% of VDD) 8-mA drive - 8-mA drive with slew rate control 21.2.8 Analog-to-Digital Converter a Table 21-20. ADC Characteristics Parameter VADCIN N fADC Min Nom Max Unit Maximum single-ended, full-scale analog input voltage Parameter Name - - 3.0 V Minimum single-ended, full-scale analog input voltage 0.0 - - V Maximum differential, full-scale analog input voltage - - 1.5 V Minimum differential, full-scale analog input voltage 0.0 - - Resolution b ADC internal clock frequency 16 18 MHz 2 µs c 500 k samples/s tADCCONV Conversion time Conversion rate IL 14 bits c f ADCCONV tLT V 10 Latency from trigger to start of conversion - 2 - system clocks ADC input leakage - - ±3.0 µA RADC ADC equivalent resistance - - 10 kΩ CADC ADC equivalent capacitance 0.9 1.0 1.1 pF ±3 LSB LSB EL Integral nonlinearity error - - ED Differential nonlinearity error - - ±2 EO Offset error - - +6 LSB EG Full-scale gain error - - ±3 LSB ETS Temperature sensor accuracy - - ±5 °C d a. The ADC reference voltage is 3.0 V. This reference voltage is internally generated from the 3.3 VDDA supply by a band gap circuit. b. The ADC must be clocked from the PLL or directly from an external clock source to operate properly. c. The conversion time and rate scale from the specified number if the ADC internal clock frequency is any value other than 16 MHz. d. The offset error listed above is the conversion result with 0 V applied to the ADC input. 776 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 21-10. ADC Input Equivalency Diagram Stellaris® Microcontroller VDD ESD Clamp RADC ESD Clamp VIN 10-bit converter IL CADC Sample and hold ADC converter Table 21-21. ADC Module Internal Reference Characteristics Parameter VREFI EIR 21.2.9 Parameter Name Min Nom Max Unit Internal voltage reference for ADC - 3.0 - V Internal voltage reference error - - ±2.5 % Synchronous Serial Interface (SSI) Table 21-22. SSI Characteristics Parameter No. Parameter Parameter Name Min S1 tclk_per SSIClk cycle time S2 tclk_high SSIClk high time S3 tclk_low SSIClk low time a Nom Max Unit 2 - 65024 system clocks - 0.5 - t clk_per - 0.5 - t clk_per - 6 10 ns S4 tclkrf SSIClk rise/fall time S5 tDMd Data from master valid delay time 0 - 1 system clocks S6 tDMs Data from master setup time 1 - - system clocks S7 tDMh Data from master hold time 2 - - system clocks S8 tDSs Data from slave setup time 1 - - system clocks S9 tDSh Data from slave hold time 2 - - system clocks a. Note that the delays shown are using 8-mA drive strength. July 17, 2014 777 Texas Instruments-Production Data Electrical Characteristics Figure 21-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement S1 S4 S2 SSIClk S3 SSIFss SSITx SSIRx MSB LSB 4 to 16 bits Figure 21-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer S2 S1 SSIClk S3 SSIFss SSITx MSB LSB 8-bit control SSIRx 0 MSB LSB 4 to 16 bits output data 778 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Figure 21-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 S1 S2 S4 SSIClk (SPO=0) S3 SSIClk (SPO=1) S6 SSITx (master) S7 MSB S5 SSIRx (slave) S8 LSB S9 MSB LSB SSIFss 21.2.10 Inter-Integrated Circuit (I2C) Interface Table 21-23. I2C Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit a tSCH Start condition hold time 36 - - system clocks a tLP Clock Low period 36 - - system clocks b tSRT I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.4 V) - - (see note b) ns a tDH Data hold time 2 - - system clocks c tSFT I2CSCL/I2CSDA fall time (VIH =2.4 V to V IL =0.5 V) - 9 10 ns I1 I2 I3 I4 I5 a tHT Clock High time 24 - - system clocks a tDS Data setup time 18 - - system clocks a tSCSR Start condition setup time (for repeated start condition only) 36 - - system clocks a tSCS Stop condition setup time 24 - - system clocks I6 I7 I8 I9 I2C a. Values depend on the value programmed into the TPR bit in the Master Timer Period (I2CMTPR) register; a TPR programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above values are minimum values. b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. c. Specified at a nominal 50 pF load. July 17, 2014 779 Texas Instruments-Production Data Electrical Characteristics Figure 21-14. I2C Timing I2 I6 I5 I2CSCL I1 I4 I7 I8 I3 I9 I2CSDA 21.2.11 Universal Serial Bus (USB) Controller The Stellaris USB controller AC electrical specifications are compliant with the “Universal Serial Bus Specification Rev. 2.0” (full-speed and low-speed support). 780 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller A Boot Loader A.1 Boot Loader ® The Stellaris Boot Loader is executed from the ROM when flash is empty and is used to download code to the flash memory of a device without the use of a debug interface. The boot loader uses a simple packet interface to provide synchronous communication with the device. The boot loader runs off the internal oscillator and does not enable the PLL, so its speed is determined by the speed of the internal oscillator. The following serial interfaces can be used: ■ UART0 ■ SSI0 ■ I2C0 For simplicity, both the data format and communication protocol are identical for all serial interfaces. See the Stellaris Boot Loader User's Guide for information on the boot loader software. A.2 Interfaces Once communication with the boot loader is established via one of the serial interfaces, that interface is used until the boot loader is reset or new code takes over. For example, once you start communicating using the SSI port, communications with the boot loader via the UART are disabled until the device is reset. A.2.1 UART The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is automatically detected by the boot loader and can be any valid baud rate supported by the host and the device. The auto detection sequence requires that the baud rate should be no more than 1/32 the internal oscillator frequency of the board that is running the boot loader (which is at least 8.4 MHz, providing support for up to 262,500 baud). This is actually the same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device which is calculated as follows: Max Baud Rate = System Clock Frequency / 16 In order to determine the baud rate, the boot loader needs to determine the relationship between the internal oscillator and the baud rate. This is enough information for the boot loader to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows the host to use any valid baud rate that it wants to communicate with the device. The method used to perform this automatic synchronization relies on the host sending the boot loader two bytes that are both 0x55. This generates a series of pulses to the boot loader that it can use to calculate the ratios needed to program the UART to match the host’s baud rate. After the host sends the pattern, it attempts to read back one byte of data from the UART. The boot loader returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received after at least twice the time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait for the 0xCC byte again until the boot loader acknowledges that it has received a synchronization pattern correctly. For example, the time to wait for data back from the boot loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate of 115200, this time is 2*(20/115200) or 0.35 ms. July 17, 2014 781 Texas Instruments-Production Data Boot Loader A.2.2 SSI The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications, with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame Formats” on page 539 in the SSI chapter for more information on formats for this transfer protocol. Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI clock can run. This allows the SSI clock to be at most 1/12 the the internal oscillator frequency of the board running the boot loader (which is at least 8.4 MHz, providing support for up to 700 KHz).. Since the host device is the master, the SSI on the boot loader device does not need to determine the clock as it is provided directly by the host. A.2.3 I2C The Inter-Integrated Circuit (I2C) port operates in slave mode with a slave address of 0x42. The I2C port will work at both 100 Khz and 400 KHz I2C clock frequency. Since the host device is the master, the I2C on the boot loader device does not need to determine the clock as it is provided directly by the host. A.3 Packet Handling All communications, with the exception of the UART auto-baud, are done via defined packets that are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same format for receiving and sending packets, including the method used to acknowledge successful or unsuccessful reception of a packet. A.3.1 Packet Format All packets sent and received from the device use the following byte-packed format. struct { unsigned char ucSize; unsigned char ucCheckSum; unsigned char Data[]; }; A.3.2 ucSize The first byte received holds the total size of the transfer including the size and checksum bytes. ucChecksum This holds a simple checksum of the bytes in the data buffer only. The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3]. Data This is the raw data intended for the device, which is formatted in some form of command interface. There should be ucSize–2 bytes of data provided in this buffer to or from the device. Sending Packets The actual bytes of the packet can be sent individually or all at once; the only limitation is that commands that cause flash memory access should limit the download sizes to prevent losing bytes during flash programming. This limitation is discussed further in the section that describes the boot loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA (0x24)” on page 784). Once the packet has been formatted correctly by the host, it should be sent out over the UART or SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from 782 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This does not indicate that the actual contents of the command issued in the data portion of the packet were valid, just that the packet was received correctly. A.3.3 Receiving Packets The boot loader sends a packet of data in the same format that it receives a packet. The boot loader may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the data itself. There is no break in the data after the first non-zero byte is sent from the boot loader. Once the device communicating with the boot loader receives all the bytes, it must either ACK or NAK the packet to indicate that the transmission was successful. The appropriate response after sending a NAK to the boot loader is to resend the command that failed and request the data again. If needed, the host may send leading zeros before sending down the ACK/NAK signal to the boot loader, as the boot loader only accepts the first non-zero data as a valid response. This zero padding is needed by the SSI interface in order to receive data to or from the boot loader. A.4 Commands The next section defines the list of commands that can be sent to the boot loader. The first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent. A.4.1 COMMAND_PING (0X20) This command simply accepts the command and sets the global status to success. The format of the packet is as follows: Byte[0] = 0x03; Byte[1] = checksum(Byte[2]); Byte[2] = COMMAND_PING; The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status, the receipt of an ACK can be interpreted as a successful ping to the boot loader. A.4.2 COMMAND_DOWNLOAD (0x21) This command is sent to the boot loader to indicate where to store data and how many bytes will be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit values that are both transferred MSB first. The first 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent. This command also triggers an erase of the full area to be programmed so this command takes longer than other commands. This results in a longer time to receive the ACK/NAK back from the board. This command should be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size are valid for the device running the boot loader. The format of the packet to send this command is a follows: Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] = = = = = = 11 checksum(Bytes[2:10]) COMMAND_DOWNLOAD Program Address [31:24] Program Address [23:16] Program Address [15:8] July 17, 2014 783 Texas Instruments-Production Data Boot Loader Byte[6] = Program Address [7:0] Byte[7] = Program Size [31:24] Byte[8] = Program Size [23:16] Byte[9] = Program Size [15:8] Byte[10] = Program Size [7:0] A.4.3 COMMAND_RUN (0x22) This command is used to tell the boot loader to execute from the address passed as the parameter in this command. This command consists of a single 32-bit value that is interpreted as the address to execute. The 32-bit value is transmitted MSB first and the boot loader responds with an ACK signal back to the host device before actually executing the code at the given address. This allows the host to know that the command was received successfully and the code is now running. Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] A.4.4 = = = = = = = 7 checksum(Bytes[2:6]) COMMAND_RUN Execute Address[31:24] Execute Address[23:16] Execute Address[15:8] Execute Address[7:0] COMMAND_GET_STATUS (0x23) This command returns the status of the last command that was issued. Typically, this command should be sent after every command to ensure that the previous command was successful or to properly respond to a failure. The command requires one byte in the data of the packet and should be followed by reading a packet with one byte of data that contains a status code. The last step is to ACK or NAK the received data so the boot loader knows that the data has been read. Byte[0] = 0x03 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_GET_STATUS A.4.5 COMMAND_SEND_DATA (0x24) This command should only follow a COMMAND_DOWNLOAD command or another COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands automatically increment address and continue programming from the previous location. For packets which do not contain the final portion of the downloaded data, a multiple of four bytes should always be transferred. The command terminates programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to ensure that the data was successfully programmed into the flash. If the boot loader sends a NAK to this command, the boot loader does not increment the current address to allow retransmission of the previous data. The following example shows a COMMAND_SEND_DATA packet with 8 bytes of packet data: Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] = = = = = = = 11 checksum(Bytes[2:10]) COMMAND_SEND_DATA Data[0] Data[1] Data[2] Data[3] 784 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller Byte[7] = Data[4] Byte[8] = Data[5] Byte[9] = Data[6] Byte[10] = Data[7] A.4.6 COMMAND_RESET (0x25) This command is used to tell the boot loader device to reset. Unlike the COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set up for the new code. It can also be used to reset the boot loader if a critical error occurs and the host device wants to restart communication with the boot loader. Byte[0] = 3 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_RESET The boot loader responds with an ACK signal back to the host device before actually executing the software reset to the device running the boot loader. This allows the host to know that the command was received successfully and the part will be reset. July 17, 2014 785 Texas Instruments-Production Data ROM DriverLib Functions B ROM DriverLib Functions B.1 DriverLib Functions Included in the Integrated ROM ® The Stellaris Peripheral Driver Library (DriverLib) APIs that are available in the integrated ROM of the Stellaris family of devices are listed below. The detailed description of each function is available in the Stellaris® ROM User’s Guide. ROM_ADCHardwareOversampleConfigure // Configures the hardware oversampling factor of the ADC. ROM_ADCIntClear // Clears sample sequence interrupt source. ROM_ADCIntDisable // Disables a sample sequence interrupt. ROM_ADCIntEnable // Enables a sample sequence interrupt. ROM_ADCIntStatus // Gets the current interrupt status. ROM_ADCProcessorTrigger // Causes a processor trigger for a sample sequence. ROM_ADCSequenceConfigure // Configures the trigger source and priority of a sample sequence. ROM_ADCSequenceDataGet // Gets the captured data for a sample sequence. ROM_ADCSequenceDisable // Disables a sample sequence. ROM_ADCSequenceEnable // Enables a sample sequence. ROM_ADCSequenceOverflow // Determines if a sample sequence overflow occurred. ROM_ADCSequenceOverflowClear // Clears the overflow condition on a sample sequence. ROM_ADCSequenceStepConfigure // Configure a step of the sample sequencer. ROM_ADCSequenceUnderflow // Determines if a sample sequence underflow occurred. ROM_ADCSequenceUnderflowClear // Clears the underflow condition on a sample sequence. 786 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ROM_FlashErase // Erases a block of flash. ROM_FlashIntClear // Clears flash controller interrupt sources. ROM_FlashIntDisable // Disables individual flash controller interrupt sources. ROM_FlashIntEnable // Enables individual flash controller interrupt sources. ROM_FlashIntGetStatus // Gets the current interrupt status. ROM_FlashProgram // Programs flash. ROM_FlashProtectGet // Gets the protection setting for a block of flash. ROM_FlashProtectSave // Saves the flash protection settings. ROM_FlashProtectSet // Sets the protection setting for a block of flash. ROM_FlashUsecGet // Gets the number of processor clocks per micro-second. ROM_FlashUsecSet // Sets the number of processor clocks per micro-second. ROM_FlashUserGet // Gets the user registers. ROM_FlashUserSave // Saves the user registers. ROM_FlashUserSet // Sets the user registers. ROM_GPIODirModeGet // Gets the direction and mode of a pin. ROM_GPIODirModeSet // Sets the direction and mode of the specified pin(s). ROM_GPIOIntTypeGet // Gets the interrupt type for a pin. ROM_GPIOIntTypeSet // Sets the interrupt type for the specified pin(s). July 17, 2014 787 Texas Instruments-Production Data ROM DriverLib Functions ROM_GPIOPadConfigGet // Gets the pad configuration for a pin. ROM_GPIOPadConfigSet // Sets the pad configuration for the specified pin(s). ROM_GPIOPinIntClear // Clears the interrupt for the specified pin(s). ROM_GPIOPinIntDisable // Disables interrupts for the specified pin(s). ROM_GPIOPinIntEnable // Enables interrupts for the specified pin(s). ROM_GPIOPinIntStatus // Gets interrupt status for the specified GPIO port. ROM_GPIOPinRead // Reads the values present of the specified pin(s). ROM_GPIOPinTypeCAN // Configures pin(s) for use as a CAN device. ROM_GPIOPinTypeGPIOInput // Configures pin(s) for use as GPIO inputs. ROM_GPIOPinTypeGPIOOutput // Configures pin(s) for use as GPIO outputs. ROM_GPIOPinTypeGPIOOutputOD // Configures pin(s) for use as GPIO open drain outputs. ROM_GPIOPinTypeI2C // Configures pin(s) for use by the I2C peripheral. ROM_GPIOPinTypeSSI // Configures pin(s) for use by the SSI peripheral. ROM_GPIOPinTypeTimer // Configures pin(s) for use by the Timer peripheral. ROM_GPIOPinTypeUART // Configures pin(s) for use by the UART peripheral. ROM_GPIOPinWrite // Writes a value to the specified pin(s). ROM_I2CMasterBusBusy // Indicates whether or not the I2C bus is busy. ROM_I2CMasterBusy // Indicates whether or not the I2C Master is busy. 788 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ROM_I2CMasterControl // Controls the state of the I2C Master module. ROM_I2CMasterDataGet // Receives a byte that has been sent to the I2C Master. ROM_I2CMasterDataPut // Transmits a byte from the I2C Master. ROM_I2CMasterDisable // Disables the I2C master block. ROM_I2CMasterEnable // Enables the I2C Master block. ROM_I2CMasterErr // Gets the error status of the I2C Master module. ROM_I2CMasterInitExpClk // Initializes the I2C Master block. ROM_I2CMasterIntClear // Clears I2C Master interrupt sources. ROM_I2CMasterIntDisable // Disables the I2C Master interrupt. ROM_I2CMasterIntEnable // Enables the I2C Master interrupt. ROM_I2CMasterIntStatus // Gets the current I2C Master interrupt status. ROM_I2CMasterSlaveAddrSet // Sets the address that the I2C Master will place on the bus. ROM_I2CSlaveDataGet // Receives a byte that has been sent to the I2C Slave. ROM_I2CSlaveDataPut // Transmits a byte from the I2C Slave. ROM_I2CSlaveDisable // Disables the I2C slave block. ROM_I2CSlaveEnable // Enables the I2C Slave block. ROM_I2CSlaveInit // Initializes the I2C Slave block. ROM_I2CSlaveIntClear // Clears I2C Slave interrupt sources. July 17, 2014 789 Texas Instruments-Production Data ROM DriverLib Functions ROM_I2CSlaveIntDisable // Disables the I2C Slave interrupt. ROM_I2CSlaveIntEnable // Enables the I2C Slave interrupt. ROM_I2CSlaveIntStatus // Gets the current I2C Slave interrupt status. ROM_I2CSlaveStatus // Gets the I2C Slave module status. ROM_IntDisable // Disables an interrupt. ROM_IntEnable // Enables an interrupt. ROM_IntPriorityGet // Gets the priority of an interrupt. ROM_IntPriorityGroupingGet // Gets the priority grouping of the interrupt controller. ROM_IntPriorityGroupingSet // Sets the priority grouping of the interrupt controller. ROM_IntPrioritySet // Sets the priority of an interrupt. ROM_SSIConfigSetExpClk // Configures the synchronous serial interface. ROM_SSIDataGet // Gets a data element from the SSI receive FIFO. ROM_SSIDataGetNonBlocking // Gets a data element from the SSI receive FIFO. ROM_SSIDataPut // Puts a data element into the SSI transmit FIFO. ROM_SSIDataPutNonBlocking // Puts a data element into the SSI transmit FIFO. ROM_SSIDisable // Disables the synchronous serial interface. ROM_SSIEnable // Enables the synchronous serial interface. ROM_SSIIntClear // Clears SSI interrupt sources. 790 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ROM_SSIIntDisable // Disables individual SSI interrupt sources. ROM_SSIIntEnable // Enables individual SSI interrupt sources. ROM_SSIIntStatus // Gets the current interrupt status. ROM_SysCtlADCSpeedGet // Gets the sample rate of the ADC. ROM_SysCtlADCSpeedSet // Sets the sample rate of the ADC. ROM_SysCtlClockGet // Gets the processor clock rate. ROM_SysCtlClockSet // Sets the clocking of the device. ROM_SysCtlDeepSleep // Puts the processor into deep-sleep mode. ROM_SysCtlFlashSizeGet // Gets the size of the flash. ROM_SysCtlGPIOAHBDisable // Disables a GPIO peripheral for access from the AHB. ROM_SysCtlGPIOAHBEnable // Enables a GPIO peripheral for access from the AHB. ROM_SysCtlIntClear // Clears system control interrupt sources. ROM_SysCtlIntDisable // Disables individual system control interrupt sources. ROM_SysCtlIntEnable // Enables individual system control interrupt sources. ROM_SysCtlIntStatus // Gets the current interrupt status. ROM_SysCtlLDOGet // Gets the output voltage of the LDO. ROM_SysCtlLDOSet // Sets the output voltage of the LDO. ROM_SysCtlPeripheralClockGating // Controls peripheral clock gating in sleep and deep-sleep mode. July 17, 2014 791 Texas Instruments-Production Data ROM DriverLib Functions ROM_SysCtlPeripheralDeepSleepDisable // Disables a peripheral in deep-sleep mode. ROM_SysCtlPeripheralDeepSleepEnable // Enables a peripheral in deep-sleep mode. ROM_SysCtlPeripheralDisable // Disables a peripheral. ROM_SysCtlPeripheralEnable // Enables a peripheral. ROM_SysCtlPeripheralPresent // Determines if a peripheral is present. ROM_SysCtlPeripheralReset // Performs a software reset of a peripheral. ROM_SysCtlPeripheralSleepDisable // Disables a peripheral in sleep mode. ROM_SysCtlPeripheralSleepEnable // Enables a peripheral in sleep mode. ROM_SysCtlPinPresent // Determines if a pin is present. ROM_SysCtlReset // Resets the device. ROM_SysCtlResetCauseClear // Clears reset reasons. ROM_SysCtlResetCauseGet // Gets the reason for a reset. ROM_SysCtlSleep // Puts the processor into sleep mode. ROM_SysCtlSRAMSizeGet // Gets the size of the SRAM. ROM_SysTickDisable // Disables the SysTick counter. ROM_SysTickEnable // Enables the SysTick counter. ROM_SysTickIntDisable // Disables the SysTick interrupt. ROM_SysTickIntEnable // Enables the SysTick interrupt. 792 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ROM_SysTickPeriodGet // Gets the period of the SysTick counter. ROM_SysTickPeriodSet // Sets the period of the SysTick counter. ROM_SysTickValueGet // Gets the current value of the SysTick counter. ROM_TimerConfigure // Configures the timer(s). ROM_TimerControlEvent // Controls the event type. ROM_TimerControlLevel // Controls the output level. ROM_TimerControlStall // Controls the stall handling. ROM_TimerControlTrigger // Enables or disables the trigger output. ROM_TimerDisable // Disables the timer(s). ROM_TimerEnable // Enables the timer(s). ROM_TimerIntClear // Clears timer interrupt sources. ROM_TimerIntDisable // Disables individual timer interrupt sources. ROM_TimerIntEnable // Enables individual timer interrupt sources. ROM_TimerIntStatus // Gets the current interrupt status. ROM_TimerLoadGet // Gets the timer load value. ROM_TimerLoadSet // Sets the timer load value. ROM_TimerMatchGet // Gets the timer match value. ROM_TimerMatchSet // Sets the timer match value. July 17, 2014 793 Texas Instruments-Production Data ROM DriverLib Functions ROM_TimerPrescaleGet // Get the timer prescale value. ROM_TimerPrescaleSet // Set the timer prescale value. ROM_TimerRTCDisable // Disable RTC counting. ROM_TimerRTCEnable // Enable RTC counting. ROM_TimerValueGet // Gets the current timer value. ROM_UARTBreakCtl // Causes a BREAK to be sent. ROM_UARTCharGet // Waits for a character from the specified port. ROM_UARTCharGetNonBlocking // Receives a character from the specified port. ROM_UARTCharPut // Waits to send a character from the specified port. ROM_UARTCharPutNonBlocking // Sends a character to the specified port. ROM_UARTCharsAvail // Determines if there are any characters in the receive FIFO. ROM_UARTConfigGetExpClk // Gets the current configuration of a UART. ROM_UARTConfigSetExpClk // Sets the configuration of a UART. ROM_UARTDisable // Disables transmitting and receiving. ROM_UARTDisableSIR // Disables SIR (IrDA) mode on the specified UART. ROM_UARTEnable // Enables transmitting and receiving. ROM_UARTEnableSIR // Enables SIR (IrDA) mode on specified UART. ROM_UARTFIFOLevelGet // Gets the FIFO level at which interrupts are generated. 794 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ROM_UARTFIFOLevelSet // Sets the FIFO level at which interrupts are generated. ROM_UARTIntClear // Clears UART interrupt sources. ROM_UARTIntDisable // Disables individual UART interrupt sources. ROM_UARTIntEnable // Enables individual UART interrupt sources. ROM_UARTIntStatus // Gets the current interrupt status. ROM_UARTParityModeGet // Gets the type of parity currently being used. ROM_UARTParityModeSet // Sets the type of parity. ROM_UARTSpaceAvail // Determines if there is any space in the transmit FIFO. ROM_UpdateI2C // Starts an update over the I2C0 interface. ROM_UpdateSSI // Starts an update over the SSI0 interface. ROM_UpdateUART // Starts an update over the UART0 interface. ROM_WatchdogEnable // Enables the watchdog timer. ROM_WatchdogIntClear // Clears the watchdog timer interrupt. ROM_WatchdogIntEnable // Enables the watchdog timer interrupt. ROM_WatchdogIntStatus // Gets the current watchdog timer interrupt status. ROM_WatchdogLock // Enables the watchdog timer lock mechanism. ROM_WatchdogLockState // Gets the state of the watchdog timer lock mechanism. ROM_WatchdogReloadGet // Gets the watchdog timer reload value. July 17, 2014 795 Texas Instruments-Production Data ROM DriverLib Functions ROM_WatchdogReloadSet // Sets the watchdog timer reload value. ROM_WatchdogResetDisable // Disables the watchdog timer reset. ROM_WatchdogResetEnable // Enables the watchdog timer reset. ROM_WatchdogRunning // Determines if the watchdog timer is enabled. ROM_WatchdogStallDisable // Disables stalling of the watchdog timer during debug events. ROM_WatchdogStallEnable // Enables stalling of the watchdog timer during debug events. ROM_WatchdogUnlock // Disables the watchdog timer lock mechanism. ROM_WatchdogValueGet // Gets the current watchdog timer value. 796 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller C Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The Cortex-M3 Processor R0, type R/W, , reset - (see page 60) DATA DATA R1, type R/W, , reset - (see page 60) DATA DATA R2, type R/W, , reset - (see page 60) DATA DATA R3, type R/W, , reset - (see page 60) DATA DATA R4, type R/W, , reset - (see page 60) DATA DATA R5, type R/W, , reset - (see page 60) DATA DATA R6, type R/W, , reset - (see page 60) DATA DATA R7, type R/W, , reset - (see page 60) DATA DATA R8, type R/W, , reset - (see page 60) DATA DATA R9, type R/W, , reset - (see page 60) DATA DATA R10, type R/W, , reset - (see page 60) DATA DATA R11, type R/W, , reset - (see page 60) DATA DATA R12, type R/W, , reset - (see page 60) DATA DATA SP, type R/W, , reset - (see page 61) SP SP LR, type R/W, , reset 0xFFFF.FFFF (see page 62) LINK LINK PC, type R/W, , reset - (see page 63) PC PC July 17, 2014 797 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR, type R/W, , reset 0x0100.0000 (see page 64) N Z C V Q ICI / IT THUMB ICI / IT ISRNUM PRIMASK, type R/W, , reset 0x0000.0000 (see page 68) PRIMASK FAULTMASK, type R/W, , reset 0x0000.0000 (see page 69) FAULTMASK BASEPRI, type R/W, , reset 0x0000.0000 (see page 70) BASEPRI CONTROL, type R/W, , reset 0x0000.0000 (see page 71) ASP TMPL INTEN ENABLE Cortex-M3 Peripherals System Timer (SysTick) Registers Base 0xE000.E000 STCTRL, type R/W, offset 0x010, reset 0x0000.0000 COUNT CLK_SRC STRELOAD, type R/W, offset 0x014, reset 0x0000.0000 RELOAD RELOAD STCURRENT, type R/WC, offset 0x018, reset 0x0000.0000 CURRENT CURRENT Cortex-M3 Peripherals Nested Vectored Interrupt Controller (NVIC) Registers Base 0xE000.E000 EN0, type R/W, offset 0x100, reset 0x0000.0000 INT INT EN1, type R/W, offset 0x104, reset 0x0000.0000 INT DIS0, type R/W, offset 0x180, reset 0x0000.0000 INT INT DIS1, type R/W, offset 0x184, reset 0x0000.0000 INT PEND0, type R/W, offset 0x200, reset 0x0000.0000 INT INT PEND1, type R/W, offset 0x204, reset 0x0000.0000 INT UNPEND0, type R/W, offset 0x280, reset 0x0000.0000 INT INT 798 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNPEND1, type R/W, offset 0x284, reset 0x0000.0000 INT ACTIVE0, type RO, offset 0x300, reset 0x0000.0000 INT INT ACTIVE1, type RO, offset 0x304, reset 0x0000.0000 INT PRI0, type R/W, offset 0x400, reset 0x0000.0000 INTD INTC INTB INTA PRI1, type R/W, offset 0x404, reset 0x0000.0000 INTD INTC INTB INTA PRI2, type R/W, offset 0x408, reset 0x0000.0000 INTD INTC INTB INTA PRI3, type R/W, offset 0x40C, reset 0x0000.0000 INTD INTC INTB INTA PRI4, type R/W, offset 0x410, reset 0x0000.0000 INTD INTC INTB INTA PRI5, type R/W, offset 0x414, reset 0x0000.0000 INTD INTC INTB INTA PRI6, type R/W, offset 0x418, reset 0x0000.0000 INTD INTC INTB INTA PRI7, type R/W, offset 0x41C, reset 0x0000.0000 INTD INTC INTB INTA PRI8, type R/W, offset 0x420, reset 0x0000.0000 INTD INTC INTB INTA PRI9, type R/W, offset 0x424, reset 0x0000.0000 INTD INTC INTB INTA PRI10, type R/W, offset 0x428, reset 0x0000.0000 INTD INTC INTB INTA PRI11, type R/W, offset 0x42C, reset 0x0000.0000 INTD INTC INTB INTA SWTRIG, type WO, offset 0xF00, reset 0x0000.0000 INTID July 17, 2014 799 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cortex-M3 Peripherals System Control Block (SCB) Registers Base 0xE000.E000 CPUID, type RO, offset 0xD00, reset 0x411F.C231 IMP VAR CON PARTNO REV INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000 NMISET PENDSV UNPENDSV VECPEND ISRPRE PENDSTSET PENDSTCLR ISRPEND VECPEND RETBASE VECACT VTABLE, type R/W, offset 0xD08, reset 0x0000.0000 BASE OFFSET OFFSET APINT, type R/W, offset 0xD0C, reset 0xFA05.0000 VECTKEY PRIGROUP ENDIANESS SYSRESREQ VECTCLRACT VECTRESET SYSCTRL, type R/W, offset 0xD10, reset 0x0000.0000 SEVONPEND SLEEPDEEP SLEEPEXIT CFGCTRL, type R/W, offset 0xD14, reset 0x0000.0000 DIV0 STKALIGN BFHFNMIGN MAINPEND UNALIGNED BASETHR SYSPRI1, type R/W, offset 0xD18, reset 0x0000.0000 USAGE BUS MEM SYSPRI2, type R/W, offset 0xD1C, reset 0x0000.0000 SVC SYSPRI3, type R/W, offset 0xD20, reset 0x0000.0000 TICK PENDSV DEBUG SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000 USAGE SVC BUSP MEMP USAGEP TICK PNDSV MON SVCA USGA BUS MEM BUSA MEMA INVSTAT UNDEF DERR IERR FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000 BFARV BSTKE BUSTKE IMPRE DIV0 UNALIGN PRECISE IBUS NOCP MMARV MSTKE MUSTKE INVPC HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000 DBG FORCED VECT MMADDR, type R/W, offset 0xD34, reset ADDR ADDR FAULTADDR, type R/W, offset 0xD38, reset ADDR ADDR Cortex-M3 Peripherals Memory Protection Unit (MPU) Registers Base 0xE000.E000 MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800 IREGION DREGION SEPARATE 800 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRIVDEFEN HFNMIENA ENABLE MPUCTRL, type R/W, offset 0xD94, reset 0x0000.0000 MPUNUMBER, type R/W, offset 0xD98, reset 0x0000.0000 NUMBER MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000 ADDR ADDR VALID REGION VALID REGION VALID REGION VALID REGION MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000 ADDR ADDR MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000 ADDR ADDR MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.0000 ADDR ADDR MPUATTR, type R/W, offset 0xDA0, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR1, type R/W, offset 0xDA8, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR2, type R/W, offset 0xDB0, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR3, type R/W, offset 0xDB8, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE System Control Base 0x400F.E000 DID0, type RO, offset 0x000, reset - (see page 186) VER CLASS MAJOR MINOR PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD (see page 188) BORIOR LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000 (see page 189) VADJ RIS, type RO, offset 0x050, reset 0x0000.0000 (see page 190) MOSCPUPRIS USBPLLLRIS PLLLRIS BORRIS PLLLIM BORIM PLLLMIS BORMIS IMC, type R/W, offset 0x054, reset 0x0000.0000 (see page 191) MOSCPUPIM USBPLLLIM MISC, type R/W1C, offset 0x058, reset 0x0000.0000 (see page 192) MOSCPUPMIS USBPLLLMIS RESC, type R/W, offset 0x05C, reset - (see page 193) MOSCFAIL SW July 17, 2014 WDT BOR POR EXT 801 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCC, type R/W, offset 0x060, reset 0x0780.3AD1 (see page 194) ACG PWRDN SYSDIV BYPASS USESYSDIV XTAL OSCSRC IOSCDIS MOSCDIS PLLCFG, type RO, offset 0x064, reset - (see page 198) F R GPIOHBCTL, type R/W, offset 0x06C, reset 0x0000.0000 (see page 199) PORTE PORTD PORTC PORTB PORTA RCC2, type R/W, offset 0x070, reset 0x0780.6810 (see page 201) USERCC2 SYSDIV2 USBPWRDN PWRDN2 BYPASS2 OSCSRC2 MOSCCTL, type R/W, offset 0x07C, reset 0x0000.0000 (see page 203) CVAL DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 (see page 204) DSDIVORIDE DSOSCSRC DID1, type RO, offset 0x004, reset - (see page 205) VER FAM PARTNO PINCOUNT TEMP PKG ROHS QUAL DC0, type RO, offset 0x008, reset 0x00FF.003F (see page 207) SRAMSZ FLASHSZ DC1, type RO, offset 0x010, reset 0x0101.32FF (see page 208) CAN0 MINSYSDIV MAXADCSPD ADC MPU HIB TEMPSNS PLL WDT SWO SWD JTAG TIMER2 TIMER1 TIMER0 UART1 UART0 DC2, type RO, offset 0x014, reset 0x0007.5013 (see page 210) I2C1 I2C0 SSI0 DC3, type RO, offset 0x018, reset 0x9F3F.0000 (see page 211) 32KHZ CCP4 CCP3 CCP2 CCP1 CCP0 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 GPIOE GPIOD GPIOC GPIOB GPIOA DC4, type RO, offset 0x01C, reset 0x0000.301F (see page 212) UDMA ROM DC5, type RO, offset 0x020, reset 0x0000.0000 (see page 213) DC6, type RO, offset 0x024, reset 0x0000.0002 (see page 214) USB0 DC7, type RO, offset 0x028, reset 0x40C0.0F3F (see page 215) SW UART1_TX UART1_RX SSI0_TX SSI0_RX UART0_TX UART0_RX USB_EP3_TX USB_EP3_RX USB_EP2_TX USB_EP2_RX USB_EP1_TX USB_EP1_RX RCGC0, type R/W, offset 0x100, reset 0x00000040 (see page 217) CAN0 MAXADCSPD ADC HIB WDT HIB WDT SCGC0, type R/W, offset 0x110, reset 0x00000040 (see page 219) CAN0 MAXADCSPD ADC 802 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DCGC0, type R/W, offset 0x120, reset 0x00000040 (see page 221) CAN0 ADC HIB WDT RCGC1, type R/W, offset 0x104, reset 0x00000000 (see page 223) TIMER2 I2C1 I2C0 SSI0 TIMER1 TIMER0 UART1 UART0 TIMER1 TIMER0 UART1 UART0 TIMER1 TIMER0 UART1 UART0 SCGC1, type R/W, offset 0x114, reset 0x00000000 (see page 225) TIMER2 I2C1 I2C0 SSI0 DCGC1, type R/W, offset 0x124, reset 0x00000000 (see page 227) TIMER2 I2C1 I2C0 SSI0 RCGC2, type R/W, offset 0x108, reset 0x00000000 (see page 229) USB0 UDMA GPIOE GPIOD GPIOC GPIOB GPIOA GPIOE GPIOD GPIOC GPIOB GPIOA GPIOE GPIOD GPIOC GPIOB GPIOA SCGC2, type R/W, offset 0x118, reset 0x00000000 (see page 231) USB0 UDMA DCGC2, type R/W, offset 0x128, reset 0x00000000 (see page 233) USB0 UDMA SRCR0, type R/W, offset 0x040, reset 0x00000000 (see page 235) CAN0 ADC HIB WDT SRCR1, type R/W, offset 0x044, reset 0x00000000 (see page 236) TIMER2 I2C1 I2C0 SSI0 TIMER1 TIMER0 UART1 UART0 GPIOB GPIOA HIBREQ RTCEN SRCR2, type R/W, offset 0x048, reset 0x00000000 (see page 237) USB0 UDMA GPIOE GPIOD GPIOC Hibernation Module Base 0x400F.C000 HIBRTCC, type RO, offset 0x000, reset 0x0000.0000 (see page 247) RTCC RTCC HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF (see page 248) RTCM0 RTCM0 HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF (see page 249) RTCM1 RTCM1 HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF (see page 250) RTCLD RTCLD HIBCTL, type R/W, offset 0x010, reset 0x8000.0000 (see page 251) WRC VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 254) EXTW LOWBAT RTCALT1 RTCALT0 EXTW LOWBAT RTCALT1 RTCALT0 HIBRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 255) July 17, 2014 803 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HIBMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 256) EXTW LOWBAT RTCALT1 RTCALT0 EXTW LOWBAT RTCALT1 RTCALT0 HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000 (see page 257) HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF (see page 258) TRIM HIBDATA, type R/W, offset 0x030-0x12C, reset - (see page 259) RTD RTD Internal Memory ROM Registers (System Control Offset) Base 0x400F.E000 RMCTL, type R/W1C, offset 0x0F0, reset - BA Internal Memory Flash Memory Control Registers (Flash Control Offset) Base 0x400F.D000 FMA, type R/W, offset 0x000, reset 0x0000.0000 OFFSET OFFSET FMD, type R/W, offset 0x004, reset 0x0000.0000 DATA DATA FMC, type R/W, offset 0x008, reset 0x0000.0000 WRKEY COMT MERASE ERASE WRITE PRIS ARIS PMASK AMASK PMISC AMISC FCRIS, type RO, offset 0x00C, reset 0x0000.0000 FCIM, type R/W, offset 0x010, reset 0x0000.0000 FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000 Internal Memory Flash Memory Protection Registers (System Control Offset) Base 0x400F.E000 USECRL, type R/W, offset 0x140, reset 0x31 USEC FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE 804 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBG1 DBG0 USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE NW DATA DATA USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF NW DATA DATA USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF NW DATA DATA USER_REG2, type R/W, offset 0x1E8, reset 0xFFFF.FFFF NW DATA DATA USER_REG3, type R/W, offset 0x1EC, reset 0xFFFF.FFFF NW DATA DATA FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE2, type R/W, offset 0x208, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPRE3, type R/W, offset 0x20C, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE2, type R/W, offset 0x408, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE FMPPE3, type R/W, offset 0x40C, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE Micro Direct Memory Access (μDMA) μDMA Channel Control Structure Base n/a DMASRCENDP, type R/W, offset 0x000, reset ADDR ADDR DMADSTENDP, type R/W, offset 0x004, reset ADDR ADDR DMACHCTL, type R/W, offset 0x008, reset - ARBSIZE DSTSIZE SRCINC SRCSIZE XFERSIZE July 17, 2014 ARBSIZE NXTUSEBURST DSTINC XFERMODE 805 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Micro Direct Memory Access (μDMA) μDMA Registers Base 0x400F.F000 DMASTAT, type RO, offset 0x000, reset 0x001F.0000 DMACHANS STATE MASTEN DMACFG, type WO, offset 0x004, reset - MASTEN DMACTLBASE, type R/W, offset 0x008, reset 0x0000.0000 ADDR ADDR DMAALTBASE, type RO, offset 0x00C, reset 0x0000.0200 ADDR ADDR DMAWAITSTAT, type RO, offset 0x010, reset 0x0000.0000 WAITREQ[n] WAITREQ[n] DMASWREQ, type WO, offset 0x014, reset SWREQ[n] SWREQ[n] DMAUSEBURSTSET, type RO, offset 0x018, reset 0x0000.0000 (Reads) SET[n] SET[n] DMAUSEBURSTSET, type WO, offset 0x018, reset 0x0000.0000 (Writes) SET[n] SET[n] DMAUSEBURSTCLR, type WO, offset 0x01C, reset CLR[n] CLR[n] DMAREQMASKSET, type RO, offset 0x020, reset 0x0000.0000 (Reads) SET[n] SET[n] DMAREQMASKSET, type WO, offset 0x020, reset 0x0000.0000 (Writes) SET[n] SET[n] DMAREQMASKCLR, type WO, offset 0x024, reset CLR[n] CLR[n] DMAENASET, type RO, offset 0x028, reset 0x0000.0000 (Reads) SET[n] SET[n] DMAENASET, type WO, offset 0x028, reset 0x0000.0000 (Writes) SET[n] SET[n] DMAENACLR, type WO, offset 0x02C, reset CLR[n] CLR[n] DMAALTSET, type RO, offset 0x030, reset 0x0000.0000 (Reads) SET[n] SET[n] 806 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAALTSET, type WO, offset 0x030, reset 0x0000.0000 (Writes) SET[n] SET[n] DMAALTCLR, type WO, offset 0x034, reset CLR[n] CLR[n] DMAPRIOSET, type RO, offset 0x038, reset 0x0000.0000 (Reads) SET[n] SET[n] DMAPRIOSET, type WO, offset 0x038, reset 0x0000.0000 (Writes) SET[n] SET[n] DMAPRIOCLR, type WO, offset 0x03C, reset CLR[n] CLR[n] DMAERRCLR, type RO, offset 0x04C, reset 0x0000.0000 (Reads) ERRCLR DMAERRCLR, type WO, offset 0x04C, reset 0x0000.0000 (Writes) ERRCLR DMAPeriphID0, type RO, offset 0xFE0, reset 0x0000.0030 PID0 DMAPeriphID1, type RO, offset 0xFE4, reset 0x0000.00B2 PID1 DMAPeriphID2, type RO, offset 0xFE8, reset 0x0000.000B PID2 DMAPeriphID3, type RO, offset 0xFEC, reset 0x0000.0000 PID3 DMAPeriphID4, type RO, offset 0xFD0, reset 0x0000.0004 PID4 DMAPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 DMAPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 DMAPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 DMAPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 July 17, 2014 807 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 General-Purpose Input/Outputs (GPIOs) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 (see page 362) DATA GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 (see page 363) DIR GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 (see page 364) IS GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 (see page 365) IBE GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 (see page 366) IEV GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 (see page 367) IME GPIORIS, type RO, offset 0x414, reset 0x0000.0000 (see page 368) RIS GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 (see page 369) MIS GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 (see page 370) IC GPIOAFSEL, type R/W, offset 0x420, reset - (see page 371) AFSEL GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF (see page 373) DRV2 GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 (see page 374) DRV4 GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 (see page 375) DRV8 GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 (see page 376) ODE GPIOPUR, type R/W, offset 0x510, reset - (see page 377) PUE 808 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 379) PDE GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 380) SRL GPIODEN, type R/W, offset 0x51C, reset - (see page 381) DEN GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 (see page 383) LOCK LOCK GPIOCR, type -, offset 0x524, reset - (see page 384) CR GPIOAMSEL, type R/W, offset 0x528, reset 0x0000.0000 (see page 386) GPIOAMSEL GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 387) PID4 GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 388) PID5 GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 389) PID6 GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 390) PID7 GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 (see page 391) PID0 GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 392) PID1 GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 393) PID2 GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 394) PID3 GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 395) CID0 GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 396) CID1 GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 397) CID2 July 17, 2014 809 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 398) CID3 General-Purpose Timers Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 (see page 411) GPTMCFG GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 (see page 412) TAAMS TACMR TAMR TBAMS TBCMR TBMR GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 (see page 414) GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 (see page 416) TBPWML TBOTE TBEVENT TBSTALL TBEN TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 (see page 419) CBEIM CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS RTCMIS CAEMIS CAMMIS TATOMIS GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 421) CBERIS GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 (see page 422) CBEMIS CBMMIS TBTOMIS GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 (see page 423) CBECINT CBMCINT TBTOCINT RTCCINT CAECINT CAMCINT TATOCINT GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF (see page 425) TAILRH TAILRL GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 426) TBILRL GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF (see page 427) TAMRH TAMRL GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF (see page 428) TBMRL GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 (see page 429) TAPSR GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 (see page 430) TBPSR GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF (see page 431) TARH TARL 810 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESEN INTEN GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (see page 432) TBRL Watchdog Timer Base 0x4000.0000 WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF (see page 437) WDTLoad WDTLoad WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF (see page 438) WDTValue WDTValue WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 (see page 439) WDTICR, type WO, offset 0x00C, reset - (see page 440) WDTIntClr WDTIntClr WDTRIS, type RO, offset 0x010, reset 0x0000.0000 (see page 441) WDTRIS WDTMIS, type RO, offset 0x014, reset 0x0000.0000 (see page 442) WDTMIS WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 (see page 443) STALL WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 (see page 444) WDTLock WDTLock WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 445) PID4 WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 446) PID5 WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 447) PID6 WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 448) PID7 WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 (see page 449) PID0 WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 (see page 450) PID1 WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 451) PID2 WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 452) PID3 July 17, 2014 811 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASEN3 ASEN2 ASEN1 ASEN0 INR3 INR2 INR1 INR0 MASK3 MASK2 MASK1 MASK0 IN3 IN2 IN1 IN0 OV3 OV2 OV1 OV0 UV1 UV0 WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 453) CID0 WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 454) CID1 WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 455) CID2 WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 456) CID3 Analog-to-Digital Converter (ADC) Base 0x4003.8000 ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000 (see page 467) ADCRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 468) ADCIM, type R/W, offset 0x008, reset 0x0000.0000 (see page 469) ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000 (see page 470) ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000 (see page 471) ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000 (see page 472) EM3 EM2 EM1 EM0 ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000 (see page 475) UV3 UV2 ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210 (see page 476) SS3 SS2 SS1 SS0 ADCPSSI, type WO, offset 0x028, reset - (see page 478) SS3 SS2 SS1 SS0 ADCSAC, type R/W, offset 0x030, reset 0x0000.0000 (see page 479) AVG ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000 (see page 480) MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000 (see page 482) TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 ADCSSFIFO0, type RO, offset 0x048, reset - (see page 485) DATA 812 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCSSFIFO1, type RO, offset 0x068, reset - (see page 485) DATA ADCSSFIFO2, type RO, offset 0x088, reset - (see page 485) DATA ADCSSFIFO3, type RO, offset 0x0A8, reset - (see page 485) DATA ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100 (see page 486) FULL EMPTY HPTR TPTR EMPTY HPTR TPTR EMPTY HPTR TPTR EMPTY HPTR TPTR ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100 (see page 486) FULL ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100 (see page 486) FULL ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100 (see page 486) FULL ADCSSMUX1, type R/W, offset 0x060, reset 0x0000.0000 (see page 487) MUX3 MUX2 MUX1 MUX0 MUX1 MUX0 ADCSSMUX2, type R/W, offset 0x080, reset 0x0000.0000 (see page 487) MUX3 MUX2 ADCSSCTL1, type R/W, offset 0x064, reset 0x0000.0000 (see page 488) TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 ADCSSCTL2, type R/W, offset 0x084, reset 0x0000.0000 (see page 488) TS3 IE3 END3 D3 TS2 IE2 END2 ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 490) MUX0 ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002 (see page 491) TS0 IE0 END0 D0 OE BE PE FE Universal Asynchronous Receivers/Transmitters (UARTs) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UARTDR, type R/W, offset 0x000, reset 0x0000.0000 (see page 502) OE BE PE FE DATA UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Reads) (see page 504) UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Writes) (see page 504) DATA July 17, 2014 813 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXFE RXFF TXFF RXFE BUSY EPS PEN BRK SIRLP SIREN UARTEN UARTFR, type RO, offset 0x018, reset 0x0000.0090 (see page 506) UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 (see page 508) ILPDVSR UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 (see page 509) DIVINT UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 (see page 510) DIVFRAC UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 (see page 511) SPS WLEN FEN STP2 UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 (see page 513) RXE TXE LBE UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 (see page 515) RXIFLSEL TXIFLSEL UARTIM, type R/W, offset 0x038, reset 0x0000.0000 (see page 517) OEIM BEIM PEIM FEIM RTIM TXIM RXIM PERIS FERIS RTRIS TXRIS RXRIS PEMIS FEMIS RTMIS TXMIS RXMIS PEIC FEIC RTIC TXIC RXIC UARTRIS, type RO, offset 0x03C, reset 0x0000.0000 (see page 519) OERIS BERIS UARTMIS, type RO, offset 0x040, reset 0x0000.0000 (see page 520) OEMIS BEMIS UARTICR, type W1C, offset 0x044, reset 0x0000.0000 (see page 521) OEIC BEIC UARTDMACTL, type R/W, offset 0x048, reset 0x0000.0000 (see page 523) DMAERR TXDMAE RXDMAE UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 524) PID4 UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 525) PID5 UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 526) PID6 UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 527) PID7 UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 (see page 528) PID0 814 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 529) PID1 UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 530) PID2 UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 531) PID3 UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 532) CID0 UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 533) CID1 UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 534) CID2 UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 535) CID3 Synchronous Serial Interface (SSI) SSI0 base: 0x4000.8000 SSICR0, type R/W, offset 0x000, reset 0x0000.0000 (see page 550) SCR SPH SPO FRF DSS SSICR1, type R/W, offset 0x004, reset 0x0000.0000 (see page 552) SOD MS SSE LBM RFF RNE TNF TFE TXIM RXIM RTIM RORIM TXRIS RXRIS RTRIS RORRIS TXMIS RXMIS RTMIS RORMIS RTIC RORIC SSIDR, type R/W, offset 0x008, reset 0x0000.0000 (see page 554) DATA SSISR, type RO, offset 0x00C, reset 0x0000.0003 (see page 555) BSY SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 (see page 557) CPSDVSR SSIIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 558) SSIRIS, type RO, offset 0x018, reset 0x0000.0008 (see page 560) SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 561) SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 562) SSIDMACTL, type R/W, offset 0x024, reset 0x0000.0000 (see page 563) TXDMAE RXDMAE July 17, 2014 815 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 564) PID4 SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 565) PID5 SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 566) PID6 SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 567) PID7 SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 (see page 568) PID0 SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 569) PID1 SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 570) PID2 SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 571) PID3 SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 572) CID0 SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 573) CID1 SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 574) CID2 SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 575) CID3 Inter-Integrated Circuit (I2C) Interface I2C Master I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2CMSA, type R/W, offset 0x000, reset 0x0000.0000 SA R/S I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Reads) BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY ACK STOP START RUN I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Writes) I2CMDR, type R/W, offset 0x008, reset 0x0000.0000 DATA 816 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001 TPR I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000 IM I2CMRIS, type RO, offset 0x014, reset 0x0000.0000 RIS I2CMMIS, type RO, offset 0x018, reset 0x0000.0000 MIS I2CMICR, type WO, offset 0x01C, reset 0x0000.0000 IC I2CMCR, type R/W, offset 0x020, reset 0x0000.0000 SFE MFE LPBK Inter-Integrated Circuit (I2C) Interface I2C Slave I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2CSOAR, type R/W, offset 0x800, reset 0x0000.0000 OAR I2CSCSR, type RO, offset 0x804, reset 0x0000.0000 (Reads) FBR TREQ RREQ I2CSCSR, type WO, offset 0x804, reset 0x0000.0000 (Writes) DA I2CSDR, type R/W, offset 0x808, reset 0x0000.0000 DATA I2CSIMR, type R/W, offset 0x80C, reset 0x0000.0000 DATAIM I2CSRIS, type RO, offset 0x810, reset 0x0000.0000 DATARIS I2CSMIS, type RO, offset 0x814, reset 0x0000.0000 DATAMIS I2CSICR, type WO, offset 0x818, reset 0x0000.0000 DATAIC Controller Area Network (CAN) Module CAN0 base: 0x4004.0000 CANCTL, type R/W, offset 0x000, reset 0x0000.0001 (see page 634) TEST CCE DAR July 17, 2014 EIE SIE IE INIT 817 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BOFF EWARN EPASS RXOK TXOK CANSTS, type R/W, offset 0x004, reset 0x0000.0000 (see page 636) LEC CANERR, type RO, offset 0x008, reset 0x0000.0000 (see page 638) RP REC TEC CANBIT, type R/W, offset 0x00C, reset 0x0000.2301 (see page 639) TSEG2 TSEG1 SJW BRP CANINT, type RO, offset 0x010, reset 0x0000.0000 (see page 640) INTID CANTST, type R/W, offset 0x014, reset 0x0000.0000 (see page 641) RX TX LBACK SILENT BASIC CANBRPE, type R/W, offset 0x018, reset 0x0000.0000 (see page 643) BRPE CANIF1CRQ, type R/W, offset 0x020, reset 0x0000.0001 (see page 644) BUSY MNUM CANIF2CRQ, type R/W, offset 0x080, reset 0x0000.0001 (see page 644) BUSY MNUM MASK ARB CONTROL CLRINTPND WRNRD MASK ARB CONTROL CLRINTPND NEWDAT / TXRQST WRNRD DATAA DATAB NEWDAT / TXRQST CANIF1CMSK, type R/W, offset 0x024, reset 0x0000.0000 (see page 645) DATAA DATAB CANIF2CMSK, type R/W, offset 0x084, reset 0x0000.0000 (see page 645) CANIF1MSK1, type R/W, offset 0x028, reset 0x0000.FFFF (see page 647) MSK CANIF2MSK1, type R/W, offset 0x088, reset 0x0000.FFFF (see page 647) MSK CANIF1MSK2, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 648) MXTD MDIR MSK CANIF2MSK2, type R/W, offset 0x08C, reset 0x0000.FFFF (see page 648) MXTD MDIR MSK CANIF1ARB1, type R/W, offset 0x030, reset 0x0000.0000 (see page 649) ID 818 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CANIF2ARB1, type R/W, offset 0x090, reset 0x0000.0000 (see page 649) ID CANIF1ARB2, type R/W, offset 0x034, reset 0x0000.0000 (see page 650) MSGVAL XTD DIR ID CANIF2ARB2, type R/W, offset 0x094, reset 0x0000.0000 (see page 650) MSGVAL XTD DIR ID CANIF1MCTL, type R/W, offset 0x038, reset 0x0000.0000 (see page 652) NEWDAT MSGLST INTPND UMASK TXIE RXIE RMTEN TXRQST EOB DLC TXRQST EOB DLC CANIF2MCTL, type R/W, offset 0x098, reset 0x0000.0000 (see page 652) NEWDAT MSGLST INTPND UMASK TXIE RXIE RMTEN CANIF1DA1, type R/W, offset 0x03C, reset 0x0000.0000 (see page 654) DATA CANIF1DA2, type R/W, offset 0x040, reset 0x0000.0000 (see page 654) DATA CANIF1DB1, type R/W, offset 0x044, reset 0x0000.0000 (see page 654) DATA CANIF1DB2, type R/W, offset 0x048, reset 0x0000.0000 (see page 654) DATA CANIF2DA1, type R/W, offset 0x09C, reset 0x0000.0000 (see page 654) DATA CANIF2DA2, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 654) DATA CANIF2DB1, type R/W, offset 0x0A4, reset 0x0000.0000 (see page 654) DATA CANIF2DB2, type R/W, offset 0x0A8, reset 0x0000.0000 (see page 654) DATA CANTXRQ1, type RO, offset 0x100, reset 0x0000.0000 (see page 655) TXRQST CANTXRQ2, type RO, offset 0x104, reset 0x0000.0000 (see page 655) TXRQST CANNWDA1, type RO, offset 0x120, reset 0x0000.0000 (see page 656) NEWDAT CANNWDA2, type RO, offset 0x124, reset 0x0000.0000 (see page 656) NEWDAT July 17, 2014 819 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CANMSG1INT, type RO, offset 0x140, reset 0x0000.0000 (see page 657) INTPND CANMSG2INT, type RO, offset 0x144, reset 0x0000.0000 (see page 657) INTPND CANMSG1VAL, type RO, offset 0x160, reset 0x0000.0000 (see page 658) MSGVAL CANMSG2VAL, type RO, offset 0x164, reset 0x0000.0000 (see page 658) MSGVAL Universal Serial Bus (USB) Controller Base 0x4005.0000 USBFADDR, type R/W, offset 0x000, reset 0x00 (see page 676) FUNCADDR USBPOWER, type R/W, offset 0x001, reset 0x20 (Host Mode) (see page 677) RESET RESUME SUSPEND PWRDNPHY RESET RESUME SUSPEND PWRDNPHY USBPOWER, type R/W, offset 0x001, reset 0x20 (Device Mode) (see page 677) ISOUP SOFTCONN USBTXIS, type RO, offset 0x002, reset 0x0000 (see page 680) EP3 EP2 EP1 EP3 EP2 EP1 EP3 EP2 EP1 EP3 EP2 EP1 EP0 USBRXIS, type RO, offset 0x004, reset 0x0000 (see page 681) USBTXIE, type R/W, offset 0x006, reset 0x000F (see page 682) EP0 USBRXIE, type R/W, offset 0x008, reset 0x000E (see page 683) USBIS, type RO, offset 0x00A, reset 0x00 ( Host Mode) (see page 684) DISCON CONN SOF BABBLE RESUME SOF RESET SOF BABBLE RESUME SOF RESET USBIS, type RO, offset 0x00A, reset 0x00 (Device Mode) (see page 684) RESUME SUSPEND USBIE, type R/W, offset 0x00B, reset 0x06 (Host Mode) (see page 687) DISCON CONN USBIE, type R/W, offset 0x00B, reset 0x06 (Device Mode) (see page 687) DISCON RESUME SUSPEND USBFRAME, type RO, offset 0x00C, reset 0x0000 (see page 690) FRAME USBEPIDX, type R/W, offset 0x00E, reset 0x00 (see page 691) EPIDX USBTEST, type R/W, offset 0x00F, reset 0x00 (Host Mode) (see page 692) FORCEH FIFOACC FORCEFS USBTEST, type R/W, offset 0x00F, reset 0x00 (Device Mode) (see page 692) FIFOACC FORCEFS USBFIFO0, type R/W, offset 0x020, reset 0x0000.0000 (see page 694) EPDATA EPDATA USBFIFO1, type R/W, offset 0x024, reset 0x0000.0000 (see page 694) EPDATA EPDATA 820 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSDEV LSDEV USBFIFO2, type R/W, offset 0x028, reset 0x0000.0000 (see page 694) EPDATA EPDATA USBFIFO3, type R/W, offset 0x02C, reset 0x0000.0000 (see page 694) EPDATA EPDATA USBDEVCTL, type RO, offset 0x060, reset 0x80 (see page 695) HOST USBTXFIFOSZ, type R/W, offset 0x062, reset 0x00 (see page 696) DPB SIZE DPB SIZE USBRXFIFOSZ, type R/W, offset 0x063, reset 0x00 (see page 696) USBTXFIFOADD, type R/W, offset 0x064, reset 0x0000 (see page 697) ADDR USBRXFIFOADD, type R/W, offset 0x066, reset 0x0000 (see page 697) ADDR USBCONTIM, type R/W, offset 0x07A, reset 0x5C (see page 698) WTCON WTID USBFSEOF, type R/W, offset 0x07D, reset 0x77 (see page 699) FSEOFG USBLSEOF, type R/W, offset 0x07E, reset 0x72 (see page 700) LSEOFG USBTXFUNCADDR0, type R/W, offset 0x080, reset 0x00 (see page 701) ADDR USBTXFUNCADDR1, type R/W, offset 0x088, reset 0x00 (see page 701) ADDR USBTXFUNCADDR2, type R/W, offset 0x090, reset 0x00 (see page 701) ADDR USBTXFUNCADDR3, type R/W, offset 0x098, reset 0x00 (see page 701) ADDR USBTXHUBADDR0, type R/W, offset 0x082, reset 0x00 (see page 702) ADDR USBTXHUBADDR1, type R/W, offset 0x08A, reset 0x00 (see page 702) ADDR USBTXHUBADDR2, type R/W, offset 0x092, reset 0x00 (see page 702) ADDR USBTXHUBADDR3, type R/W, offset 0x09A, reset 0x00 (see page 702) ADDR USBTXHUBPORT0, type R/W, offset 0x083, reset 0x00 (see page 703) PORT USBTXHUBPORT1, type R/W, offset 0x08B, reset 0x00 (see page 703) PORT USBTXHUBPORT2, type R/W, offset 0x093, reset 0x00 (see page 703) PORT USBTXHUBPORT3, type R/W, offset 0x09B, reset 0x00 (see page 703) PORT USBRXFUNCADDR1, type R/W, offset 0x08C, reset 0x00 (see page 704) ADDR USBRXFUNCADDR2, type R/W, offset 0x094, reset 0x00 (see page 704) ADDR USBRXFUNCADDR3, type R/W, offset 0x09C, reset 0x00 (see page 704) ADDR July 17, 2014 821 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STALLED TXRDY RXRDY SETEND DATAEND STALLED TXRDY RXRDY DT FLUSH USBRXHUBADDR1, type R/W, offset 0x08E, reset 0x00 (see page 705) ADDR USBRXHUBADDR2, type R/W, offset 0x096, reset 0x00 (see page 705) ADDR USBRXHUBADDR3, type R/W, offset 0x09E, reset 0x00 (see page 705) ADDR USBRXHUBPORT1, type R/W, offset 0x08F, reset 0x00 (see page 706) PORT USBRXHUBPORT2, type R/W, offset 0x097, reset 0x00 (see page 706) PORT USBRXHUBPORT3, type R/W, offset 0x09F, reset 0x00 (see page 706) PORT USBTXMAXP1, type R/W, offset 0x110, reset 0x0000 (see page 707) MAXLOAD USBTXMAXP2, type R/W, offset 0x120, reset 0x0000 (see page 707) MAXLOAD USBTXMAXP3, type R/W, offset 0x130, reset 0x0000 (see page 707) MAXLOAD USBCSRL0, type R/W, offset 0x102, reset 0x00 (Host Mode) (see page 708) NAKTO STATUS REQPKT ERROR SETUP USBCSRL0, type R/W, offset 0x102, reset 0x00 (Device Mode) (see page 708) SETENDC RXRDYC STALL USBCSRH0, type R/W, offset 0x103, reset 0x00 (Host Mode) (see page 712) DTWE USBCSRH0, type R/W, offset 0x103, reset 0x00 (Device Mode) (see page 712) FLUSH USBCOUNT0, type RO, offset 0x108, reset 0x00 (see page 714) COUNT USBTYPE0, type R/W, offset 0x10A, reset 0x00 (see page 715) SPEED USBNAKLMT, type R/W, offset 0x10B, reset 0x00 (see page 716) NAKLMT USBTXCSRL1, type R/W, offset 0x112, reset 0x00 (Host Mode) (see page 717) NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT MODE DMAEN FDT DMAMOD USBTXCSRL2, type R/W, offset 0x122, reset 0x00 (Host Mode) (see page 717) USBTXCSRL3, type R/W, offset 0x132, reset 0x00 (Host Mode) (see page 717) USBTXCSRL1, type R/W, offset 0x112, reset 0x00 (Device Mode) (see page 717) USBTXCSRL2, type R/W, offset 0x122, reset 0x00 (Device Mode) (see page 717) USBTXCSRL3, type R/W, offset 0x132, reset 0x00 (Device Mode) (see page 717) USBTXCSRH1, type R/W, offset 0x113, reset 0x00 (Host Mode) (see page 721) USBTXCSRH2, type R/W, offset 0x123, reset 0x00 (Host Mode) (see page 721) USBTXCSRH3, type R/W, offset 0x133, reset 0x00 (Host Mode) (see page 721) USBTXCSRH1, type R/W, offset 0x113, reset 0x00 (Device Mode) (see page 721) AUTOSET ISO 822 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AUTOSET ISO MODE DMAEN FDT DMAMOD AUTOSET ISO MODE DMAEN FDT DMAMOD FULL RXRDY FULL RXRDY FULL RXRDY USBTXCSRH2, type R/W, offset 0x123, reset 0x00 (Device Mode) (see page 721) USBTXCSRH3, type R/W, offset 0x133, reset 0x00 (Device Mode) (see page 721) USBRXMAXP1, type R/W, offset 0x114, reset 0x0000 (see page 725) MAXLOAD USBRXMAXP2, type R/W, offset 0x124, reset 0x0000 (see page 725) MAXLOAD USBRXMAXP3, type R/W, offset 0x134, reset 0x0000 (see page 725) MAXLOAD CLRDT STALLED REQPKT FLUSH DATAERR / NAKTO ERROR CLRDT STALLED REQPKT FLUSH DATAERR / NAKTO ERROR CLRDT STALLED REQPKT FLUSH DATAERR / NAKTO USBRXCSRL1, type R/W, offset 0x116, reset 0x00 (Host Mode) (see page 726) ERROR CLRDT STALLED STALL FLUSH DATAERR OVER FULL RXRDY CLRDT STALLED STALL FLUSH DATAERR OVER FULL RXRDY CLRDT STALLED STALL FLUSH DATAERR OVER FULL RXRDY USBRXCSRL2, type R/W, offset 0x126, reset 0x00 (Host Mode) (see page 726) USBRXCSRL3, type R/W, offset 0x136, reset 0x00 (Host Mode) (see page 726) USBRXCSRL1, type R/W, offset 0x116, reset 0x00 (Device Mode) (see page 726) USBRXCSRL2, type R/W, offset 0x126, reset 0x00 (Device Mode) (see page 726) USBRXCSRL3, type R/W, offset 0x136, reset 0x00 (Device Mode) (see page 726) AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL ISO DMAEN DISNYET / PIDERR DMAMOD AUTOCL ISO DMAEN DISNYET / PIDERR USBRXCSRH1, type R/W, offset 0x117, reset 0x00 (Host Mode) (see page 731) DMAMOD USBRXCSRH2, type R/W, offset 0x127, reset 0x00 (Host Mode) (see page 731) USBRXCSRH3, type R/W, offset 0x137, reset 0x00 (Host Mode) (see page 731) USBRXCSRH1, type R/W, offset 0x117, reset 0x00 (Device Mode) (see page 731) USBRXCSRH2, type R/W, offset 0x127, reset 0x00 (Device Mode) (see page 731) July 17, 2014 823 Texas Instruments-Production Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AUTOCL ISO DMAEN DISNYET / PIDERR Register Quick Reference DMAMOD USBRXCSRH3, type R/W, offset 0x137, reset 0x00 (Device Mode) (see page 731) USBRXCOUNT1, type RO, offset 0x118, reset 0x0000 (see page 735) COUNT USBRXCOUNT2, type RO, offset 0x128, reset 0x0000 (see page 735) COUNT USBRXCOUNT3, type RO, offset 0x138, reset 0x0000 (see page 735) COUNT USBTXTYPE1, type R/W, offset 0x11A, reset 0x00 (see page 736) SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP USBTXTYPE2, type R/W, offset 0x12A, reset 0x00 (see page 736) USBTXTYPE3, type R/W, offset 0x13A, reset 0x00 (see page 736) USBTXINTERVAL1, type R/W, offset 0x11B, reset 0x00 (see page 737) TXPOLL / NAKLMT USBTXINTERVAL2, type R/W, offset 0x12B, reset 0x00 (see page 737) TXPOLL / NAKLMT USBTXINTERVAL3, type R/W, offset 0x13B, reset 0x00 (see page 737) TXPOLL / NAKLMT USBRXTYPE1, type R/W, offset 0x11C, reset 0x00 (see page 738) SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP USBRXTYPE2, type R/W, offset 0x12C, reset 0x00 (see page 738) USBRXTYPE3, type R/W, offset 0x13C, reset 0x00 (see page 738) USBRXINTERVAL1, type R/W, offset 0x11D, reset 0x00 (see page 739) TXPOLL / NAKLMT USBRXINTERVAL2, type R/W, offset 0x12D, reset 0x00 (see page 739) TXPOLL / NAKLMT USBRXINTERVAL3, type R/W, offset 0x13D, reset 0x00 (see page 739) TXPOLL / NAKLMT USBRQPKTCOUNT1, type R/W, offset 0x304, reset 0x0000 (see page 740) COUNT USBRQPKTCOUNT2, type R/W, offset 0x308, reset 0x0000 (see page 740) COUNT USBRQPKTCOUNT3, type R/W, offset 0x30C, reset 0x0000 (see page 740) COUNT USBRXDPKTBUFDIS, type R/W, offset 0x340, reset 0x0000 (see page 741) EP3 EP2 EP1 EP3 EP2 EP1 USBTXDPKTBUFDIS, type R/W, offset 0x342, reset 0x0000 (see page 742) USBEPC, type R/W, offset 0x400, reset 0x0000.0000 (see page 743) PFLTACT PFLTAEN PFLTSEN PFLTEN EPENDE EPEN USBEPCRIS, type RO, offset 0x404, reset 0x0000.0000 (see page 746) PF 824 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBEPCIM, type R/W, offset 0x408, reset 0x0000.0000 (see page 747) PF USBEPCISC, type R/W1C, offset 0x40C, reset 0x0000.0000 (see page 748) PF USBDRRIS, type RO, offset 0x410, reset 0x0000.0000 (see page 749) RESUME USBDRIM, type R/W, offset 0x414, reset 0x0000.0000 (see page 750) RESUME USBDRISC, type R/W1C, offset 0x418, reset 0x0000.0000 (see page 751) RESUME USBGPCS, type R/W, offset 0x41C, reset 0x0000.0000 (see page 752) DEVMOD July 17, 2014 825 Texas Instruments-Production Data Ordering and Contact Information D Ordering and Contact Information D.1 Ordering Information ® The figure below defines the full set of potential orderable part numbers for all the Stellaris LM3S microcontrollers. See the Package Option Addendum for the valid orderable part numbers for the LM3S5732 microcontroller. LM3Snnnn–gppss–rrm Part Number nnn = Sandstorm-class parts nnnn = All other Stellaris® parts Temperature E = –40°C to +105°C I = –40°C to +85°C Revision Speed 20 = 20 MHz 25 = 25 MHz 50 = 50 MHz 80 = 80 MHz Package BZ = 108-ball BGA QC = 100-pin LQFP QN = 48-pin LQFP QR = 64-pin LQFP D.2 Shipping Medium T = Tape-and-reel Omitted = Default shipping (tray or tube) Part Markings The Stellaris microcontrollers are marked with an identifying number. This code contains the following information: ■ The first line indicates the part number, for example, LM3S9B90. ■ In the second line, the first eight characters indicate the temperature, package, speed, revision, and product status. For example in the figure below, IQC80C0X indicates an Industrial temperature (I), 100-pin LQFP package (QC), 80-MHz (80), revision C0 (C0) device. The letter immediately following the revision indicates product status. An X indicates experimental and requires a waiver; an S indicates the part is fully qualified and released to production. ■ The remaining characters contain internal tracking numbers. D.3 Kits The Stellaris Family provides the hardware and software tools that engineers need to begin development quickly. 826 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller ■ Reference Design Kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files ■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers before purchase ■ Development Kits provide you with all the tools you need to develop and prototype embedded applications right out of the box See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor. D.4 Support Information For support on Stellaris products, contact the TI Worldwide Product Information Center nearest you: http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm. July 17, 2014 827 Texas Instruments-Production Data Package Information E Package Information E.1 64-Pin LQFP Package E.1.1 Package Dimensions ASAT R Figure E-1. Stellaris LM3S5732 64-Pin LQFP Package D D 1 N 1 FOOT PRINT E B A 1 PACKAGE THICKNESS E DIMS. LEADS TOL. A A ±.05 D ±.20 D1 ±.10 E ±.20 E 12° TYP. A2 ±.10 1 L +.15/-.10 e BASIC .80 b ±.05 .35 MAX. .20 A O ddd ccc e A1 MAX. 1 A2 D 44L 12° TYP. MAX. MS-02 JEDEC REFERENCE DRAWING AC VARIATION DESIGNATOR ANOTHER VARIATION OF PIN 1 VISUAL AID 0.20 RAD. TYP. N NOTE 1 1. 2. 3. 4. 0.20 RAD. TYP. All dimensions in mm. Dimension shown are nominal with tolerance Foot length 'L' is measured at gage plane 0.2 L/F: Eftec 64T Cu or equivalent, 0.127mm (0. 6°±4° STANDOFF A A1 .25 SEATING PLANE O b 0.17 MAX. ddd L M C A-B DO NOT SCALE DRAWING C DEPT. THIS DOCUMENT CONTAINS INFORMATION S D S LEAD COPLANARITY ccc C 828 NAME DRAWN S. PEDRON CHECK J.GUICO SIGN July 17, 2014 Texas Instruments-Production Data DATE Dec. 2002 P.E. P.D.E Q.A. ® Stellaris LM3S5732 Microcontroller Note: The following notes apply to the package drawing. 1. All dimensions shown in mm. 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane. 4. L/F: Eftec 64T Cu or equivalent, 0.127mm (0.005") thick. Body +2.00 mm Footprint, 1.4 mm package thickness Symbols Leads 64L A Max. 1.60 A1 - 0.05 Min./0.15 Max. A2 ±0.05 1.40 D ±0.20 12.00 D1 ±0.10 10.00 E ±0.20 12.00 E1 ±0.10 10.00 L +0.15/-0.10 0.60 e Basic 0.50 b ±0.05 0.22 θ - 0˚-7˚ ddd Max. 0.08 ccc Max. 0.08 JEDEC Reference Drawing MS-026 Variation Designator BCD July 17, 2014 829 Texas Instruments-Production Data Package Information E.1.2 Tray Dimensions Figure E-2. 64-Pin LQFP Tray Dimensions 830 July 17, 2014 Texas Instruments-Production Data ® Stellaris LM3S5732 Microcontroller E.1.3 Tape and Reel Dimensions Figure E-3. 64-Pin LQFP Tape and Reel Dimensions July 17, 2014 831 Texas Instruments-Production Data PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM3S5732-IQR50-A0 NRND LQFP PM 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 LM3S5732 IQR50 PM LM3S5732-IQR50-A0T NRND LQFP PM 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 LM3S5732 IQR50 PM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of