TE X A S I NS TRUM E NTS - A DVA NCE I NFO RMAT ION
Stellaris® LM3S5B91 Microcontroller
D ATA SHE E T
D S -LM 3S 5B 91 - 7 1 6 4
C opyri ght © 2007-2010 Texas Instruments
Incorporated
Copyright
Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications
are subject to change without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
2
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 36
About This Document .................................................................................................................... 41
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
41
41
41
42
1
Architectural Overview .......................................................................................... 44
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.1.9
1.2
1.3
1.4
1.4.1
1.4.2
Functional Overview ......................................................................................................
ARM Cortex™-M3 .........................................................................................................
On-Chip Memory ...........................................................................................................
External Peripheral Interface .........................................................................................
Serial Communications Peripherals ................................................................................
System Integration ........................................................................................................
Advanced Motion Control ...............................................................................................
Analog ..........................................................................................................................
JTAG and ARM Serial Wire Debug ................................................................................
Packaging and Temperature ..........................................................................................
Target Applications ........................................................................................................
High-Level Block Diagram .............................................................................................
Additional Features .......................................................................................................
Memory Map ................................................................................................................
Hardware Details ..........................................................................................................
2
ARM Cortex-M3 Processor Core ........................................................................... 68
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
Block Diagram ..............................................................................................................
Functional Description ...................................................................................................
Programming Model ......................................................................................................
Serial Wire and JTAG Debug .........................................................................................
Embedded Trace Macrocell (ETM) .................................................................................
Trace Port Interface Unit (TPIU) .....................................................................................
ROM Table ...................................................................................................................
Memory Protection Unit (MPU) .......................................................................................
Nested Vectored Interrupt Controller (NVIC) ....................................................................
System Timer (SysTick) .................................................................................................
3
Memory Map ........................................................................................................... 81
4
Interrupts ................................................................................................................. 84
5
JTAG Interface ........................................................................................................ 87
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
Block Diagram ..............................................................................................................
Signal Description .........................................................................................................
Functional Description ...................................................................................................
JTAG Interface Pins ......................................................................................................
JTAG TAP Controller .....................................................................................................
Shift Registers ..............................................................................................................
Operational Considerations ............................................................................................
Initialization and Configuration .......................................................................................
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46
46
48
49
51
56
60
62
64
65
65
65
67
67
67
69
69
69
76
76
76
77
77
77
78
88
88
89
89
91
91
92
94
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5.5
5.5.1
5.5.2
Register Descriptions .................................................................................................... 95
Instruction Register (IR) ................................................................................................. 95
Data Registers .............................................................................................................. 97
6
System Control ....................................................................................................... 99
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.3
6.4
6.5
Signal Description ......................................................................................................... 99
Functional Description ................................................................................................... 99
Device Identification .................................................................................................... 100
Reset Control .............................................................................................................. 100
Non-Maskable Interrupt ............................................................................................... 104
Power Control ............................................................................................................. 105
Clock Control .............................................................................................................. 105
System Control ........................................................................................................... 112
Initialization and Configuration ..................................................................................... 113
Register Map .............................................................................................................. 114
Register Descriptions .................................................................................................. 115
7
Internal Memory ................................................................................................... 204
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3
7.4
7.5
7.6
Block Diagram ............................................................................................................
Functional Description .................................................................................................
SRAM ........................................................................................................................
ROM ..........................................................................................................................
Flash Memory .............................................................................................................
Flash Memory Initialization and Configuration ...............................................................
Flash Memory Programming ........................................................................................
32-Word Flash Memory Write Buffer .............................................................................
Nonvolatile Register Programming ...............................................................................
Register Map ..............................................................................................................
Flash Memory Register Descriptions (Flash Control Offset) ............................................
Memory Register Descriptions (System Control Offset) ..................................................
8
Micro Direct Memory Access (μDMA) ................................................................ 240
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
Block Diagram ............................................................................................................ 241
Functional Description ................................................................................................. 241
Channel Assignments .................................................................................................. 242
Priority ........................................................................................................................ 243
Arbitration Size ............................................................................................................ 243
Request Types ............................................................................................................ 243
Channel Configuration ................................................................................................. 244
Transfer Modes ........................................................................................................... 246
Transfer Size and Increment ........................................................................................ 254
Peripheral Interface ..................................................................................................... 254
Software Request ........................................................................................................ 254
Interrupts and Errors .................................................................................................... 255
Initialization and Configuration ..................................................................................... 255
Module Initialization ..................................................................................................... 255
Configuring a Memory-to-Memory Transfer ................................................................... 255
Configuring a Peripheral for Simple Transmit ................................................................ 257
Configuring a Peripheral for Ping-Pong Receive ............................................................ 258
Configuring Alternate Channels .................................................................................... 261
Register Map .............................................................................................................. 261
4
204
204
205
205
205
207
207
209
209
210
211
222
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8.5
8.6
μDMA Channel Control Structure ................................................................................. 262
μDMA Register Descriptions ........................................................................................ 269
9
General-Purpose Input/Outputs (GPIOs) ........................................................... 298
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.3
9.4
9.5
Signal Description ....................................................................................................... 298
Functional Description ................................................................................................. 303
Data Control ............................................................................................................... 305
Interrupt Control .......................................................................................................... 306
Mode Control .............................................................................................................. 307
Commit Control ........................................................................................................... 307
Pad Control ................................................................................................................. 308
Identification ............................................................................................................... 308
Initialization and Configuration ..................................................................................... 308
Register Map .............................................................................................................. 309
Register Descriptions .................................................................................................. 312
10
External Peripheral Interface (EPI) ..................................................................... 355
10.1
10.2
10.3
10.3.1
10.3.2
10.4
10.4.1
10.4.2
10.4.3
10.5
10.6
EPI Block Diagram ......................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Non-Blocking Reads ....................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
SDRAM Mode .............................................................................................................
Host Bus Mode ...........................................................................................................
General-Purpose Mode ...............................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
11
General-Purpose Timers ...................................................................................... 428
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.5
11.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
GPTM Reset Conditions ..............................................................................................
32-Bit Timer Operating Modes ......................................................................................
16-Bit Timer Operating Modes ......................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
32-Bit One-Shot/Periodic Timer Mode ...........................................................................
32-Bit Real-Time Clock (RTC) Mode .............................................................................
16-Bit One-Shot/Periodic Timer Mode ...........................................................................
Input Edge-Count Mode ...............................................................................................
16-Bit Input Edge Timing Mode ....................................................................................
16-Bit PWM Mode .......................................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
12
Watchdog Timers ................................................................................................. 476
356
357
359
360
361
361
362
366
375
383
384
429
429
432
432
433
434
440
440
440
441
441
442
442
443
443
444
12.1
Block Diagram ............................................................................................................ 477
12.2
Functional Description ................................................................................................. 477
12.2.1 Register Access Timing ............................................................................................... 478
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12.3
12.4
12.5
Initialization and Configuration ..................................................................................... 478
Register Map .............................................................................................................. 478
Register Descriptions .................................................................................................. 479
13
Analog-to-Digital Converter (ADC) ..................................................................... 501
13.1
13.2
13.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.4
13.4.1
13.4.2
13.5
13.6
Block Diagram ............................................................................................................ 502
Signal Description ....................................................................................................... 503
Functional Description ................................................................................................. 504
Sample Sequencers .................................................................................................... 504
Module Control ............................................................................................................ 505
Hardware Sample Averaging Circuit ............................................................................. 508
Analog-to-Digital Converter .......................................................................................... 508
Differential Sampling ................................................................................................... 510
Internal Temperature Sensor ........................................................................................ 513
Digital Comparator Unit ............................................................................................... 513
Initialization and Configuration ..................................................................................... 518
Module Initialization ..................................................................................................... 518
Sample Sequencer Configuration ................................................................................. 519
Register Map .............................................................................................................. 519
Register Descriptions .................................................................................................. 521
14
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 579
14.1
Block Diagram ............................................................................................................
14.2
Signal Description .......................................................................................................
14.3
Functional Description .................................................................................................
14.3.1 Transmit/Receive Logic ...............................................................................................
14.3.2 Baud-Rate Generation .................................................................................................
14.3.3 Data Transmission ......................................................................................................
14.3.4 Serial IR (SIR) .............................................................................................................
14.3.5 ISO 7816 Support .......................................................................................................
14.3.6 Modem Handshake Support .........................................................................................
14.3.7 LIN Support ................................................................................................................
14.3.8 FIFO Operation ...........................................................................................................
14.3.9 Interrupts ....................................................................................................................
14.3.10 Loopback Operation ....................................................................................................
14.3.11 DMA Operation ...........................................................................................................
14.4
Initialization and Configuration .....................................................................................
14.5
Register Map ..............................................................................................................
14.6
Register Descriptions ..................................................................................................
580
580
582
583
583
584
584
585
586
587
588
589
589
589
590
591
592
15
Synchronous Serial Interface (SSI) .................................................................... 640
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.4
15.5
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Bit Rate Generation .....................................................................................................
FIFO Operation ...........................................................................................................
Interrupts ....................................................................................................................
Frame Formats ...........................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
6
641
641
642
643
643
643
644
651
652
653
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Stellaris® LM3S5B91 Microcontroller
15.6
Register Descriptions .................................................................................................. 654
16
Inter-Integrated Circuit (I2C) Interface ................................................................ 682
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.4
16.5
16.6
16.7
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
I2C Bus Functional Overview ........................................................................................
Available Speed Modes ...............................................................................................
Interrupts ....................................................................................................................
Loopback Operation ....................................................................................................
Command Sequence Flow Charts ................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions (I2C Master) ...............................................................................
Register Descriptions (I2C Slave) .................................................................................
17
Inter-Integrated Circuit Sound (I2S) Interface .................................................... 719
17.1
17.2
17.3
17.3.1
17.3.2
17.4
17.5
17.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Transmit .....................................................................................................................
Receive ......................................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
18
Controller Area Network (CAN) Module ............................................................. 756
18.1
Block Diagram ............................................................................................................
18.2
Signal Description .......................................................................................................
18.3
Functional Description .................................................................................................
18.3.1 Initialization .................................................................................................................
18.3.2 Operation ...................................................................................................................
18.3.3 Transmitting Message Objects .....................................................................................
18.3.4 Configuring a Transmit Message Object ........................................................................
18.3.5 Updating a Transmit Message Object ...........................................................................
18.3.6 Accepting Received Message Objects ..........................................................................
18.3.7 Receiving a Data Frame ..............................................................................................
18.3.8 Receiving a Remote Frame ..........................................................................................
18.3.9 Receive/Transmit Priority .............................................................................................
18.3.10 Configuring a Receive Message Object ........................................................................
18.3.11 Handling of Received Message Objects ........................................................................
18.3.12 Handling of Interrupts ..................................................................................................
18.3.13 Test Mode ...................................................................................................................
18.3.14 Bit Timing Configuration Error Considerations ...............................................................
18.3.15 Bit Time and Bit Rate ...................................................................................................
18.3.16 Calculating the Bit Timing Parameters ..........................................................................
18.4
Register Map ..............................................................................................................
18.5
CAN Register Descriptions ..........................................................................................
683
683
684
684
686
687
688
688
695
696
697
710
720
720
722
723
727
729
730
731
757
757
758
759
760
761
761
762
763
763
763
764
764
765
767
768
770
770
772
775
776
19
Universal Serial Bus (USB) Controller ............................................................... 808
19.1
Block Diagram ............................................................................................................ 809
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19.2
19.3
19.3.1
19.3.2
19.3.3
19.3.4
19.4
19.4.1
19.4.2
19.5
19.6
Signal Description .......................................................................................................
Functional Description .................................................................................................
Operation as a Device .................................................................................................
Operation as a Host ....................................................................................................
OTG Mode ..................................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
Pin Configuration .........................................................................................................
Endpoint Configuration ................................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
20
Analog Comparators ............................................................................................ 947
20.1
20.2
20.3
20.3.1
20.4
20.5
20.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Internal Reference Programming ..................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
21
Pulse Width Modulator (PWM) ............................................................................ 961
21.1
21.2
21.3
21.3.1
21.3.2
21.3.3
21.3.4
21.3.5
21.3.6
21.3.7
21.3.8
21.4
21.5
21.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
PWM Timer .................................................................................................................
PWM Comparators ......................................................................................................
PWM Signal Generator ................................................................................................
Dead-Band Generator .................................................................................................
Interrupt/ADC-Trigger Selector .....................................................................................
Synchronization Methods ............................................................................................
Fault Conditions ..........................................................................................................
Output Control Block ...................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
22
Quadrature Encoder Interface (QEI) ................................................................. 1039
22.1
22.2
22.3
22.4
22.5
22.6
Block Diagram ...........................................................................................................
Signal Description .....................................................................................................
Functional Description ...............................................................................................
Initialization and Configuration ....................................................................................
Register Map ............................................................................................................
Register Descriptions .................................................................................................
23
Pin Diagram ........................................................................................................ 1062
24
Signal Tables ...................................................................................................... 1064
24.1
24.2
100-Pin LQFP Package Pin Tables ............................................................................. 1065
108-Pin BGA Package Pin Tables ............................................................................... 1102
8
809
811
811
816
820
822
823
823
824
824
835
948
948
949
950
952
952
953
962
963
966
966
967
968
969
969
970
971
971
972
973
976
1039
1040
1041
1044
1044
1045
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Stellaris® LM3S5B91 Microcontroller
25
Operating Characteristics ................................................................................. 1141
26
Electrical Characteristics .................................................................................. 1142
26.1
DC Characteristics ....................................................................................................
26.1.1 Maximum Ratings ......................................................................................................
26.1.2 Recommended DC Operating Conditions ....................................................................
26.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ..............................................
26.1.4 Flash Memory Characteristics ....................................................................................
26.1.5 GPIO Module Characteristics .....................................................................................
26.1.6 USB Module Characteristics .......................................................................................
26.1.7 Current Specifications ................................................................................................
26.2
AC Characteristics .....................................................................................................
26.2.1 Load Conditions ........................................................................................................
26.2.2 Clocks ......................................................................................................................
26.2.3 JTAG and Boundary Scan ..........................................................................................
26.2.4 Reset ........................................................................................................................
26.2.5 Sleep Modes .............................................................................................................
26.2.6 General-Purpose I/O (GPIO) ......................................................................................
26.2.7 External Peripheral Interface (EPI) ..............................................................................
26.2.8 Analog-to-Digital Converter ........................................................................................
26.2.9 Synchronous Serial Interface (SSI) .............................................................................
26.2.10 Inter-Integrated Circuit (I2C) Interface .........................................................................
26.2.11 Inter-Integrated Circuit Sound (I2S) Interface ...............................................................
26.2.12 Universal Serial Bus (USB) Controller .........................................................................
26.2.13 Analog Comparator ...................................................................................................
1142
1142
1142
1143
1143
1143
1144
1144
1144
1144
1145
1147
1148
1150
1150
1150
1156
1157
1159
1159
1161
1161
A
Boot Loader ........................................................................................................ 1162
A.1
A.2
A.2.1
A.2.2
A.2.3
Boot Loader Overview ...............................................................................................
Serial Interfaces ........................................................................................................
Serial Configuration ...................................................................................................
Serial Packet Handling ...............................................................................................
Serial Commands ......................................................................................................
B
ROM DriverLib Functions .................................................................................. 1167
B.1
DriverLib Functions Included in the Integrated ROM .................................................... 1167
C
Advance Encryption Standard and Cyclic Redundancy Check Software in
ROM ..................................................................................................................... 1215
C.1
C.2
Advanced Encryption Standard Software .................................................................... 1215
Cyclic Redundancy Check Software ........................................................................... 1215
D
Register Quick Reference ................................................................................. 1216
E
Ordering and Contact Information ................................................................... 1263
E.1
E.2
E.3
E.4
Ordering Information ..................................................................................................
Part Markings ............................................................................................................
Kits ...........................................................................................................................
Support Information ...................................................................................................
F
Package Information .......................................................................................... 1265
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1162
1162
1162
1163
1164
1263
1263
1264
1264
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Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.
Figure 6-5.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 10-6.
Figure 10-7.
Figure 10-8.
Figure 10-9.
Figure 10-10.
Figure 10-11.
Figure 10-12.
Figure 10-13.
Figure 10-14.
Figure 10-15.
Figure 10-16.
Figure 10-17.
Figure 10-18.
Figure 10-19.
Figure 10-20.
®
Stellaris LM3S5B91 Microcontroller High-Level Block Diagram ............................ 66
CPU Block Diagram ............................................................................................. 69
TPIU Block Diagram ............................................................................................ 77
JTAG Module Block Diagram ................................................................................ 88
Test Access Port State Machine ........................................................................... 91
IDCODE Register Format ..................................................................................... 97
BYPASS Register Format .................................................................................... 97
Boundary Scan Register Format ........................................................................... 98
Basic RST Configuration .................................................................................... 101
External Circuitry to Extend Power-On Reset ....................................................... 102
Reset Circuit Controlled by Switch ...................................................................... 102
Power Architecture ............................................................................................ 105
Main Clock Tree ................................................................................................ 108
Internal Memory Block Diagram .......................................................................... 204
μDMA Block Diagram ......................................................................................... 241
Example of Ping-Pong μDMA Transaction ........................................................... 247
Memory Scatter-Gather, Setup and Configuration ................................................ 249
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 250
Peripheral Scatter-Gather, Setup and Configuration ............................................. 252
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 253
Digital I/O Pads ................................................................................................. 304
Analog/Digital I/O Pads ...................................................................................... 305
GPIODATA Write Example ................................................................................. 306
GPIODATA Read Example ................................................................................. 306
EPI Block Diagram ............................................................................................. 357
SDRAM Non-Blocking Read Cycle ...................................................................... 364
SDRAM Normal Read Cycle ............................................................................... 365
SDRAM Write Cycle ........................................................................................... 366
Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 373
Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 373
Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 1, RDHIGH = 1 ............................................................................................... 374
Continuous Read Mode Accesses ...................................................................... 374
Write Followed by Read to External FIFO ............................................................ 375
Two-Entry FIFO ................................................................................................. 375
Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 379
Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
WRCYC=1 ........................................................................................................ 379
Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 380
FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 380
FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 380
FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 381
FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 381
FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 381
FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 381
iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 382
10
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Figure 10-21.
Figure 10-22.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 12-1.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10.
Figure 13-11.
Figure 13-12.
Figure 13-13.
Figure 13-14.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10.
Figure 15-11.
Figure 15-12.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 382
EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 383
GPTM Module Block Diagram ............................................................................ 429
16-Bit Input Edge-Count Mode Example .............................................................. 437
16-Bit Input Edge-Time Mode Example ............................................................... 438
16-Bit PWM Mode Example ................................................................................ 439
Timer Daisy Chain ............................................................................................. 439
WDT Module Block Diagram .............................................................................. 477
Implementation of Two ADC Blocks .................................................................... 502
ADC Module Block Diagram ............................................................................... 502
ADC Sample Phases ......................................................................................... 507
Doubling the ADC Sample Rate .......................................................................... 507
Skewed Sampling .............................................................................................. 508
Internal Voltage Conversion Result ..................................................................... 509
External Voltage Conversion Result .................................................................... 510
Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 511
Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 512
Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 512
Internal Temperature Sensor Characteristic ......................................................... 513
Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 516
Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 517
High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 518
UART Module Block Diagram ............................................................................. 580
UART Character Frame ..................................................................................... 583
IrDA Data Modulation ......................................................................................... 585
LIN Message ..................................................................................................... 587
LIN Synchronization Field ................................................................................... 588
SSI Module Block Diagram ................................................................................. 641
TI Synchronous Serial Frame Format (Single Transfer) ........................................ 645
TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 645
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 646
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 646
Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 647
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 648
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 648
Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 649
MICROWIRE Frame Format (Single Frame) ........................................................ 650
MICROWIRE Frame Format (Continuous Transfer) ............................................. 651
MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 651
I2C Block Diagram ............................................................................................. 683
I2C Bus Configuration ........................................................................................ 684
START and STOP Conditions ............................................................................. 685
Complete Data Transfer with a 7-Bit Address ....................................................... 685
R/S Bit in First Byte ............................................................................................ 685
Data Validity During Bit Transfer on the I2C Bus ................................................... 686
Master Single TRANSMIT .................................................................................. 689
Master Single RECEIVE ..................................................................................... 690
Master TRANSMIT with Repeated START ........................................................... 691
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Texas Instruments-Advance Information
Table of Contents
Figure 16-10. Master RECEIVE with Repeated START ............................................................. 692
Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 693
Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 694
Figure 16-13. Slave Command Sequence ................................................................................ 695
Figure 17-1. I2S Block Diagram ............................................................................................. 720
Figure 17-2. I2S Data Transfer ............................................................................................... 723
Figure 17-3. Left-Justified Data Transfer ................................................................................ 723
Figure 17-4. Right-Justified Data Transfer .............................................................................. 723
Figure 18-1. CAN Controller Block Diagram ............................................................................ 757
Figure 18-2. CAN Data/Remote Frame .................................................................................. 759
Figure 18-3. Message Objects in a FIFO Buffer ...................................................................... 767
Figure 18-4. CAN Bit Time .................................................................................................... 771
Figure 19-1. USB Module Block Diagram ............................................................................... 809
Figure 20-1. Analog Comparator Module Block Diagram ......................................................... 948
Figure 20-2. Structure of Comparator Unit .............................................................................. 950
Figure 20-3. Comparator Internal Reference Structure ............................................................ 951
Figure 21-1. PWM Unit Diagram ............................................................................................ 963
Figure 21-2. PWM Module Block Diagram .............................................................................. 963
Figure 21-3. PWM Count-Down Mode .................................................................................... 968
Figure 21-4. PWM Count-Up/Down Mode .............................................................................. 968
Figure 21-5. PWM Generation Example In Count-Up/Down Mode ........................................... 969
Figure 21-6. PWM Dead-Band Generator ............................................................................... 969
Figure 22-1. QEI Block Diagram .......................................................................................... 1040
Figure 22-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1043
Figure 23-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1062
Figure 23-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1063
Figure 26-1. Load Conditions ............................................................................................... 1145
Figure 26-2. JTAG Test Clock Input Timing ........................................................................... 1147
Figure 26-3. JTAG Test Access Port (TAP) Timing ................................................................ 1148
Figure 26-4. External Reset Timing (RST) ............................................................................ 1148
Figure 26-5. Power-On Reset Timing ................................................................................... 1149
Figure 26-6. Brown-Out Reset Timing .................................................................................. 1149
Figure 26-7. Software Reset Timing ..................................................................................... 1149
Figure 26-8. Watchdog Reset Timing ................................................................................... 1149
Figure 26-9. MOSC Failure Reset Timing ............................................................................. 1150
Figure 26-10. SDRAM Initialization and Load Mode Register Timing ........................................ 1152
Figure 26-11. SDRAM Read Timing ....................................................................................... 1152
Figure 26-12. SDRAM Write Timing ....................................................................................... 1153
Figure 26-13. Host-Bus 8/16 Mode Read Timing ..................................................................... 1154
Figure 26-14. Host-Bus 8/16 Mode Write Timing ..................................................................... 1154
Figure 26-15. General-Purpose Mode Read and Write Timing ................................................. 1155
Figure 26-16. General-Purpose Mode iRDY Timing ................................................................. 1155
Figure 26-17. ADC Input Equivalency Diagram ....................................................................... 1157
Figure 26-18. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1158
Figure 26-19. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1158
12
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Figure 26-20.
Figure 26-21.
Figure 26-22.
Figure 26-23.
Figure 26-24.
Figure 26-25.
Figure F-1.
Figure F-2.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ...................................
I2C Timing .......................................................................................................
I2S Master Mode Transmit Timing .....................................................................
I2S Master Mode Receive Timing ......................................................................
I2S Slave Mode Transmit Timing .......................................................................
I2S Slave Mode Receive Timing ........................................................................
100-Pin LQFP Package ....................................................................................
108-Ball BGA Package .....................................................................................
May 24, 2010
1159
1159
1160
1160
1161
1161
1265
1267
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Texas Instruments-Advance Information
Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 3-1.
Table 4-1.
Table 4-2.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 6-5.
Table 6-6.
Table 6-7.
Table 6-8.
Table 6-9.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 8-6.
Table 8-7.
Table 8-8.
Table 8-9.
Table 8-10.
Table 8-11.
Table 8-12.
Table 8-13.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Revision History .................................................................................................. 36
Documentation Conventions ................................................................................ 42
16-Bit Cortex-M3 Instruction Set Summary ............................................................ 70
32-Bit Cortex-M3 Instruction Set Summary ............................................................ 72
Memory Map ....................................................................................................... 81
Exception Types .................................................................................................. 84
Interrupts ............................................................................................................ 85
Signals for JTAG_SWD_SWO (100LQFP) ............................................................. 88
Signals for JTAG_SWD_SWO (108BGA) .............................................................. 89
JTAG Port Pins State after Power-On Reset or RST assertion ................................ 90
JTAG Instruction Register Commands ................................................................... 95
Signals for System Control & Clocks (100LQFP) ................................................... 99
Signals for System Control & Clocks (108BGA) ..................................................... 99
Reset Sources ................................................................................................... 100
Clock Source Options ........................................................................................ 106
Possible System Clock Frequencies Using the SYSDIV Field ............................... 109
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 109
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 110
System Control Register Map ............................................................................. 114
RCC2 Fields that Override RCC fields ................................................................. 135
Flash Memory Protection Policy Combinations .................................................... 206
User-Programmable Flash Memory Resident Registers ....................................... 210
Flash Register Map ............................................................................................ 210
μDMA Channel Assignments .............................................................................. 242
Request Type Support ....................................................................................... 244
Control Structure Memory Map ........................................................................... 245
Channel Control Structure .................................................................................. 245
μDMA Read Example: 8-Bit Peripheral ................................................................ 254
μDMA Interrupt Assignments .............................................................................. 255
Channel Control Structure Offsets for Channel 30 ................................................ 256
Channel Control Word Configuration for Memory Transfer Example ...................... 256
Channel Control Structure Offsets for Channel 7 .................................................. 257
Channel Control Word Configuration for Peripheral Transmit Example .................. 258
Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 259
Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 260
μDMA Register Map .......................................................................................... 261
GPIO Pins With Non-Zero Reset Values .............................................................. 299
GPIO Pins and Alternate Functions (100LQFP) ................................................... 299
GPIO Pins and Alternate Functions (108BGA) ..................................................... 301
GPIO Pad Configuration Examples ..................................................................... 308
GPIO Interrupt Configuration Example ................................................................ 309
GPIO Pins With Non-Zero Reset Values .............................................................. 310
GPIO Register Map ........................................................................................... 311
GPIO Pins With Non-Zero Reset Values .............................................................. 323
GPIO Pins With Non-Zero Reset Values .............................................................. 329
14
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 9-10.
Table 9-11.
Table 9-12.
Table 10-1.
Table 10-2.
Table 10-3.
Table 10-4.
Table 10-5.
Table 10-6.
Table 10-7.
Table 10-8.
Table 11-1.
Table 11-2.
Table 11-3.
Table 11-4.
Table 11-5.
Table 12-1.
Table 13-1.
Table 13-2.
Table 13-3.
Table 13-4.
Table 13-5.
Table 14-1.
Table 14-2.
Table 14-3.
Table 14-4.
Table 15-1.
Table 15-2.
Table 15-3.
Table 16-1.
Table 16-2.
Table 16-3.
Table 16-4.
Table 16-5.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table 17-6.
Table 17-7.
Table 17-8.
Table 17-9.
Table 17-10.
Table 18-1.
Table 18-2.
Table 18-3.
Table 18-4.
GPIO Pins With Non-Zero Reset Values .............................................................. 331
GPIO Pins With Non-Zero Reset Values .............................................................. 334
GPIO Pins With Non-Zero Reset Values .............................................................. 341
Signals for External Peripheral Interface (100LQFP) ............................................ 357
Signals for External Peripheral Interface (108BGA) .............................................. 358
EPI SDRAM Signal Connections ......................................................................... 363
Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 367
EPI Host-Bus 8 Signal Connections .................................................................... 368
EPI Host-Bus 16 Signal Connections .................................................................. 369
EPI General Purpose Signal Connections ........................................................... 377
External Peripheral Interface (EPI) Register Map ................................................. 383
Available CCP Pins ............................................................................................ 429
Signals for General-Purpose Timers (100LQFP) .................................................. 430
Signals for General-Purpose Timers (108BGA) .................................................... 431
16-Bit Timer With Prescaler Configurations ......................................................... 435
Timers Register Map .......................................................................................... 444
Watchdog Timers Register Map .......................................................................... 479
Signals for ADC (100LQFP) ............................................................................... 503
Signals for ADC (108BGA) ................................................................................. 503
Samples and FIFO Depth of Sequencers ............................................................ 504
Differential Sampling Pairs ................................................................................. 510
ADC Register Map ............................................................................................. 519
Signals for UART (100LQFP) ............................................................................. 581
Signals for UART (108BGA) ............................................................................... 582
Flow Control Mode ............................................................................................. 587
UART Register Map ........................................................................................... 591
Signals for SSI (100LQFP) ................................................................................. 642
Signals for SSI (108BGA) ................................................................................... 642
SSI Register Map .............................................................................................. 653
Signals for I2C (100LQFP) ................................................................................. 683
Signals for I2C (108BGA) ................................................................................... 683
Examples of I2C Master Timer Period versus Speed Mode ................................... 687
Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 696
Write Field Decoding for I2CMCS[3:0] Field ......................................................... 702
Signals for I2S (100LQFP) ................................................................................. 721
Signals for I2S (108BGA) ................................................................................... 721
I2S Transmit FIFO Interface ................................................................................ 724
Crystal Frequency (Values from 3.5795 MHz to 5 MHz) ........................................ 725
Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) ..................................... 725
Crystal Frequency (Values from 10 MHz to 14.3181 MHz) .................................... 726
Crystal Frequency (Values from 16 MHz to 16.384 MHz) ...................................... 726
I2S Receive FIFO Interface ................................................................................. 728
Audio Formats Configuration .............................................................................. 730
Inter-Integrated Circuit Sound (I2S) Interface Register Map ................................... 731
Signals for Controller Area Network (100LQFP) ................................................... 758
Signals for Controller Area Network (108BGA) ..................................................... 758
Message Object Configurations .......................................................................... 764
CAN Protocol Ranges ........................................................................................ 771
May 24, 2010
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Texas Instruments-Advance Information
Table of Contents
Table 18-5.
Table 18-6.
Table 19-1.
Table 19-2.
Table 19-3.
Table 19-4.
Table 19-5.
Table 19-6.
Table 20-1.
Table 20-2.
Table 20-3.
Table 20-4.
Table 21-1.
Table 21-2.
Table 21-3.
Table 22-1.
Table 22-2.
Table 22-3.
Table 24-1.
Table 24-2.
Table 24-3.
Table 24-4.
Table 24-5.
Table 24-6.
Table 24-7.
Table 24-8.
Table 24-9.
Table 24-10.
Table 24-11.
Table 25-1.
Table 25-2.
Table 25-3.
Table 26-1.
Table 26-2.
Table 26-3.
Table 26-4.
Table 26-5.
Table 26-6.
Table 26-7.
Table 26-8.
Table 26-9.
Table 26-10.
Table 26-11.
Table 26-12.
Table 26-13.
Table 26-14.
Table 26-15.
Table 26-16.
CANBIT Register Values .................................................................................... 771
CAN Register Map ............................................................................................. 775
Signals for USB (100LQFP) ................................................................................ 810
Signals for USB (108BGA) ................................................................................. 810
Remainder (RxMaxP/4) ...................................................................................... 822
Actual Bytes Read ............................................................................................. 822
Packet Sizes That Clear RXRDY ........................................................................ 823
Universal Serial Bus (USB) Controller Register Map ............................................ 824
Signals for Analog Comparators (100LQFP) ........................................................ 948
Signals for Analog Comparators (108BGA) .......................................................... 949
Internal Reference Voltage and ACREFCTL Field Values ..................................... 951
Analog Comparators Register Map ..................................................................... 952
Signals for PWM (100LQFP) .............................................................................. 964
Signals for PWM (108BGA) ................................................................................ 965
PWM Register Map ............................................................................................ 973
Signals for QEI (100LQFP) ............................................................................... 1040
Signals for QEI (108BGA) ................................................................................. 1041
QEI Register Map ............................................................................................ 1045
GPIO Pins With Default Alternate Functions ...................................................... 1064
Signals by Pin Number ..................................................................................... 1065
Signals by Signal Name ................................................................................... 1077
Signals by Function, Except for GPIO ............................................................... 1088
GPIO Pins and Alternate Functions ................................................................... 1097
Possible Pin Assignments for Alternate Functions .............................................. 1100
Signals by Pin Number ..................................................................................... 1102
Signals by Signal Name ................................................................................... 1115
Signals by Function, Except for GPIO ............................................................... 1126
GPIO Pins and Alternate Functions ................................................................... 1135
Possible Pin Assignments for Alternate Functions .............................................. 1138
Temperature Characteristics ............................................................................. 1141
Thermal Characteristics ................................................................................... 1141
ESD Absolute Maximum Ratings ...................................................................... 1141
Maximum Ratings ............................................................................................ 1142
Recommended DC Operating Conditions .......................................................... 1142
LDO Regulator Characteristics ......................................................................... 1143
Flash Memory Characteristics ........................................................................... 1143
GPIO Module DC Characteristics ...................................................................... 1143
USB Controller DC Characteristics .................................................................... 1144
Preliminary Current Consumption ..................................................................... 1144
Phase Locked Loop (PLL) Characteristics ......................................................... 1145
Actual PLL Frequency ...................................................................................... 1145
PIOSC Clock Characteristics ............................................................................ 1146
30-kHz Clock Characteristics ............................................................................ 1146
Main Oscillator Clock Characteristics ................................................................ 1146
MOSC Oscillator Input Characteristics ............................................................... 1146
System Clock Characteristics with ADC Operation ............................................. 1147
JTAG Characteristics ....................................................................................... 1147
Reset Characteristics ....................................................................................... 1148
16
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 26-17.
Table 26-18.
Table 26-19.
Table 26-20.
Table 26-21.
Table 26-22.
Table 26-23.
Table 26-24.
Table 26-25.
Table 26-26.
Table 26-27.
Table 26-28.
Table 26-29.
Table 26-30.
Table 26-31.
Table 26-32.
Table E-1.
Sleep Modes AC Characteristics .......................................................................
GPIO Characteristics .......................................................................................
EPI SDRAM Characteristics .............................................................................
EPI SDRAM Interface Characteristics ...............................................................
EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics .................................
EPI General-Purpose Interface Characteristics ..................................................
ADC Characteristics .........................................................................................
ADC Module External Reference Characteristics ...............................................
ADC Module Internal Reference Characteristics ................................................
SSI Characteristics ..........................................................................................
I2S Master Clock (Receive and Transmit) ..........................................................
I2S Slave Clock (Receive and Transmit) ............................................................
I2S Master Mode ..............................................................................................
I2S Slave Mode ................................................................................................
Analog Comparator Characteristics ...................................................................
Analog Comparator Voltage Reference Characteristics ......................................
Part Ordering Information .................................................................................
May 24, 2010
1150
1150
1150
1151
1153
1154
1156
1157
1157
1157
1159
1159
1160
1160
1161
1161
1263
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Texas Instruments-Advance Information
Table of Contents
List of Registers
System Control .............................................................................................................................. 99
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Device Identification 0 (DID0), offset 0x000 ..................................................................... 116
Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 118
Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 119
Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 121
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 123
Reset Cause (RESC), offset 0x05C ................................................................................ 125
Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 127
XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 132
GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 133
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 135
Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 138
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 139
Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 141
I2S MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 142
Device Identification 1 (DID1), offset 0x004 ..................................................................... 144
Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 146
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 147
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 150
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 153
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 156
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 158
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 160
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 161
Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 165
Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 168
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 170
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 171
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 174
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 177
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 179
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 183
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 187
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 191
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 193
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 195
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 197
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 199
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 202
Internal Memory ........................................................................................................................... 204
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Flash Memory Address (FMA), offset 0x000 ....................................................................
Flash Memory Data (FMD), offset 0x004 .........................................................................
Flash Memory Control (FMC), offset 0x008 .....................................................................
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................
18
212
213
214
216
217
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 .....................
Flash Memory Control 2 (FMC2), offset 0x020 .................................................................
Flash Write Buffer Valid (FWBVAL), offset 0x030 .............................................................
Flash Write Buffer n (FWBn), offset 0x100 - 0x17C ..........................................................
Flash Control (FCTL), offset 0x0F8 .................................................................................
ROM Control (RMCTL), offset 0x0F0 ..............................................................................
ROM Version Register (RMVER), offset 0x0F4 ................................................................
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ...................
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ...............
Boot Configuration (BOOTCFG), offset 0x1D0 .................................................................
User Register 0 (USER_REG0), offset 0x1E0 ..................................................................
User Register 1 (USER_REG1), offset 0x1E4 ..................................................................
User Register 2 (USER_REG2), offset 0x1E8 ..................................................................
User Register 3 (USER_REG3), offset 0x1EC .................................................................
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 ....................................
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 ....................................
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ...................................
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ...............................
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ...............................
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ...............................
218
219
220
221
222
223
224
225
226
227
230
231
232
233
234
235
236
237
238
239
Micro Direct Memory Access (μDMA) ........................................................................................ 240
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ......................
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................
DMA Channel Control Word (DMACHCTL), offset 0x008 ..................................................
DMA Status (DMASTAT), offset 0x000 ............................................................................
DMA Configuration (DMACFG), offset 0x004 ...................................................................
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 ..................................
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C ....................
DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 .............................
DMA Channel Software Request (DMASWREQ), offset 0x014 .........................................
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 ....................................
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C .................................
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 ..............................
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ...........................
DMA Channel Enable Set (DMAENASET), offset 0x028 ...................................................
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ...............................................
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 ....................................
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 .................................
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 .................................................
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C ..............................................
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................
DMA Channel Alternate Select (DMACHALT), offset 0x500 ..............................................
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 .........................................
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 .........................................
DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 .........................................
DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................
DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 .........................................
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ...........................................
May 24, 2010
263
264
265
270
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
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Texas Instruments-Advance Information
Table of Contents
Register 28:
Register 29:
Register 30:
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 295
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 296
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 297
General-Purpose Input/Outputs (GPIOs) ................................................................................... 298
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 313
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 314
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 315
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 316
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 317
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 318
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 319
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 320
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 322
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 323
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 325
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 326
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 327
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 328
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 329
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 331
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 333
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 334
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 336
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 337
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 339
GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 341
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 343
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 344
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 345
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 346
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 347
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 348
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 349
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 350
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 351
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 352
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 353
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 354
External Peripheral Interface (EPI) ............................................................................................. 355
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
EPI Configuration (EPICFG), offset 0x000 .......................................................................
EPI Main Baud Rate (EPIBAUD), offset 0x004 .................................................................
EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 ..............................................
EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ...............................................
EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ...........................................
EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ........................................
EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 ..........................................
EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 .......................................
EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 ...................................
20
385
387
389
391
395
399
404
406
408
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
EPI Address Map (EPIADDRMAP), offset 0x01C .............................................................
EPI Read Size 0 (EPIRSIZE0), offset 0x020 ....................................................................
EPI Read Size 1 (EPIRSIZE1), offset 0x030 ....................................................................
EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................
EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................
EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 .............................................
EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 .............................................
EPI Status (EPISTAT), offset 0x060 ................................................................................
EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ......................................................
EPI Read FIFO (EPIREADFIFO), offset 0x070 ................................................................
EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 ....................................................
EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 ....................................................
EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ...................................................
EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 ....................................................
EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 ....................................................
EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 ....................................................
EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ...................................................
EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................
EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ......................................................
EPI Interrupt Mask (EPIIM), offset 0x210 .........................................................................
EPI Raw Interrupt Status (EPIRIS), offset 0x214 ..............................................................
EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................
EPI Error Interrupt Status and Clear (EPIEISC), offset 0x21C ...........................................
409
411
411
412
412
413
413
415
417
418
418
418
418
418
418
418
418
419
421
422
423
425
426
General-Purpose Timers ............................................................................................................. 428
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 445
GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 446
GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 448
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 450
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 453
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 455
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 458
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 461
GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 463
GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 464
GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 465
GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 466
GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 467
GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 468
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 469
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 470
GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 471
GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 472
GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 474
GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 475
Watchdog Timers ......................................................................................................................... 476
Register 1:
Register 2:
Register 3:
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 480
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 481
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 482
May 24, 2010
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Texas Instruments-Advance Information
Table of Contents
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Interrupt Clear (WDTICR), offset 0x00C ..........................................................
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ..................................................
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 .............................................
Watchdog Test (WDTTEST), offset 0x418 .......................................................................
Watchdog Lock (WDTLOCK), offset 0xC00 .....................................................................
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 .................................
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 .................................
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 .................................
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 .................................
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 .................................
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 .................................
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 ....................................
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 ....................................
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 ....................................
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ..................................
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
Analog-to-Digital Converter (ADC) ............................................................................................. 501
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 522
ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 523
ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 525
ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 527
ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 530
ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 532
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 537
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 538
ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 540
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 541
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 543
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 544
ADC Control (ADCCTL), offset 0x038 ............................................................................. 546
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 547
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 549
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 552
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 552
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 552
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 552
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 553
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 553
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 553
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 553
ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 555
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 557
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 559
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 559
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 560
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 560
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 562
22
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 562
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 563
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 563
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 565
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 566
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 567
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 568
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 569
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 574
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 574
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 574
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 574
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 574
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 574
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 574
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 574
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 578
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 578
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 578
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 578
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 578
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 578
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 578
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 578
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 579
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
UART Data (UARTDR), offset 0x000 ............................................................................... 593
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 595
UART Flag (UARTFR), offset 0x018 ................................................................................ 598
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 601
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 602
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 603
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 604
UART Control (UARTCTL), offset 0x030 ......................................................................... 606
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 610
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 612
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 615
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 619
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 622
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 624
UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 625
UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 626
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 627
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 628
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 629
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 630
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 631
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 632
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 633
May 24, 2010
23
Texas Instruments-Advance Information
Table of Contents
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ......................................
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC .....................................
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................
634
635
636
637
638
639
Synchronous Serial Interface (SSI) ............................................................................................ 640
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
SSI Control 0 (SSICR0), offset 0x000 ..............................................................................
SSI Control 1 (SSICR1), offset 0x004 ..............................................................................
SSI Data (SSIDR), offset 0x008 ......................................................................................
SSI Status (SSISR), offset 0x00C ...................................................................................
SSI Clock Prescale (SSICPSR), offset 0x010 ..................................................................
SSI Interrupt Mask (SSIIM), offset 0x014 .........................................................................
SSI Raw Interrupt Status (SSIRIS), offset 0x018 ..............................................................
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................
SSI Interrupt Clear (SSIICR), offset 0x020 .......................................................................
SSI DMA Control (SSIDMACTL), offset 0x024 .................................................................
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 .............................................
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 .............................................
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 .............................................
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 .............................................
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 .............................................
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 .............................................
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ...............................................
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ...............................................
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ...............................................
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ...............................................
655
657
659
660
662
663
664
666
668
669
670
671
672
673
674
675
676
677
678
679
680
681
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 682
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I2C Master Slave Address (I2CMSA), offset 0x000 ...........................................................
I2C Master Control/Status (I2CMCS), offset 0x004 ...........................................................
I2C Master Data (I2CMDR), offset 0x008 .........................................................................
I2C Master Timer Period (I2CMTPR), offset 0x00C ...........................................................
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 .........................................................
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 .................................................
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ...........................................
I2C Master Interrupt Clear (I2CMICR), offset 0x01C .........................................................
I2C Master Configuration (I2CMCR), offset 0x020 ............................................................
I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................
I2C Slave Control/Status (I2CSCSR), offset 0x004 ...........................................................
I2C Slave Data (I2CSDR), offset 0x008 ...........................................................................
I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ...........................................................
I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ...................................................
I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 ..............................................
I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................
24
698
699
704
705
706
707
708
709
710
711
712
714
715
716
717
718
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Inter-Integrated Circuit Sound (I2S) Interface ............................................................................ 719
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
I2S Transmit FIFO Data (I2STXFIFO), offset 0x000 .......................................................... 732
I2S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ...................................... 733
I2S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... 734
I2S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ 736
I2S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 737
I2S Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 738
I2S Receive FIFO Data (I2SRXFIFO), offset 0x800 .......................................................... 739
I2S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ...................................... 740
I2S Receive Module Configuration (I2SRXCFG), offset 0x808 ........................................... 741
I2S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ......................................................... 744
I2S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 ..................................... 745
I2S Receive FIFO Level (I2SRXLEV), offset 0x818 ........................................................... 746
I2S Module Configuration (I2SCFG), offset 0xC00 ............................................................ 747
I2S Interrupt Mask (I2SIM), offset 0xC10 ......................................................................... 749
I2S Raw Interrupt Status (I2SRIS), offset 0xC14 ............................................................... 751
I2S Masked Interrupt Status (I2SMIS), offset 0xC18 ......................................................... 753
I2S Interrupt Clear (I2SIC), offset 0xC1C ......................................................................... 755
Controller Area Network (CAN) Module ..................................................................................... 756
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
CAN Control (CANCTL), offset 0x000 ............................................................................. 777
CAN Status (CANSTS), offset 0x004 ............................................................................... 779
CAN Error Counter (CANERR), offset 0x008 ................................................................... 782
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 783
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 785
CAN Test (CANTST), offset 0x014 .................................................................................. 786
CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 788
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 789
CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 789
CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 791
CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 791
CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 794
CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 794
CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 795
CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 795
CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 797
CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 797
CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 798
CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 798
CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 800
CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 800
CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 803
CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 803
CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 803
CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 803
CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 803
CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 803
CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 803
May 24, 2010
25
Texas Instruments-Advance Information
Table of Contents
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 803
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 804
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 804
CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 805
CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 805
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 806
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 806
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 807
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 807
Universal Serial Bus (USB) Controller ....................................................................................... 808
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
USB Device Functional Address (USBFADDR), offset 0x000 ............................................
USB Power (USBPOWER), offset 0x001 .........................................................................
USB Transmit Interrupt Status (USBTXIS), offset 0x002 ...................................................
USB Receive Interrupt Status (USBRXIS), offset 0x004 ...................................................
USB Transmit Interrupt Enable (USBTXIE), offset 0x006 ..................................................
USB Receive Interrupt Enable (USBRXIE), offset 0x008 ..................................................
USB General Interrupt Status (USBIS), offset 0x00A ........................................................
USB Interrupt Enable (USBIE), offset 0x00B ....................................................................
USB Frame Value (USBFRAME), offset 0x00C ................................................................
USB Endpoint Index (USBEPIDX), offset 0x00E ..............................................................
USB Test Mode (USBTEST), offset 0x00F .......................................................................
USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 .............................................................
USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 .............................................................
USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 .............................................................
USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C ............................................................
USB FIFO Endpoint 4 (USBFIFO4), offset 0x030 .............................................................
USB FIFO Endpoint 5 (USBFIFO5), offset 0x034 .............................................................
USB FIFO Endpoint 6 (USBFIFO6), offset 0x038 .............................................................
USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C ............................................................
USB FIFO Endpoint 8 (USBFIFO8), offset 0x040 .............................................................
USB FIFO Endpoint 9 (USBFIFO9), offset 0x044 .............................................................
USB FIFO Endpoint 10 (USBFIFO10), offset 0x048 .........................................................
USB FIFO Endpoint 11 (USBFIFO11), offset 0x04C .........................................................
USB FIFO Endpoint 12 (USBFIFO12), offset 0x050 .........................................................
USB FIFO Endpoint 13 (USBFIFO13), offset 0x054 .........................................................
USB FIFO Endpoint 14 (USBFIFO14), offset 0x058 .........................................................
USB FIFO Endpoint 15 (USBFIFO15), offset 0x05C .........................................................
USB Device Control (USBDEVCTL), offset 0x060 ............................................................
USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 .................................
USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 ..................................
USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 .................................
USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 ..................................
USB Connect Timing (USBCONTIM), offset 0x07A ..........................................................
USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B ..............................................
USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D ......
USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E ......
USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 ...........
USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 ...........
26
836
837
840
842
844
846
848
851
854
855
856
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
858
860
862
862
863
863
864
865
866
867
868
868
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 ........... 868
USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 ........... 868
USB Transmit Functional Address Endpoint 4 (USBTXFUNCADDR4), offset 0x0A0 ........... 868
USB Transmit Functional Address Endpoint 5 (USBTXFUNCADDR5), offset 0x0A8 ........... 868
USB Transmit Functional Address Endpoint 6 (USBTXFUNCADDR6), offset 0x0B0 ........... 868
USB Transmit Functional Address Endpoint 7 (USBTXFUNCADDR7), offset 0x0B8 ........... 868
USB Transmit Functional Address Endpoint 8 (USBTXFUNCADDR8), offset 0x0C0 .......... 868
USB Transmit Functional Address Endpoint 9 (USBTXFUNCADDR9), offset 0x0C8 .......... 868
USB Transmit Functional Address Endpoint 10 (USBTXFUNCADDR10), offset 0x0D0 ....... 868
USB Transmit Functional Address Endpoint 11 (USBTXFUNCADDR11), offset 0x0D8 ....... 868
USB Transmit Functional Address Endpoint 12 (USBTXFUNCADDR12), offset 0x0E0 ....... 868
USB Transmit Functional Address Endpoint 13 (USBTXFUNCADDR13), offset 0x0E8 ....... 868
USB Transmit Functional Address Endpoint 14 (USBTXFUNCADDR14), offset 0x0F0 ....... 868
USB Transmit Functional Address Endpoint 15 (USBTXFUNCADDR15), offset 0x0F8 ....... 868
USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 ...................... 870
USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A ...................... 870
USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 ...................... 870
USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A ...................... 870
USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4), offset 0x0A2 ...................... 870
USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5), offset 0x0AA ...................... 870
USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6), offset 0x0B2 ...................... 870
USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7), offset 0x0BA ...................... 870
USB Transmit Hub Address Endpoint 8 (USBTXHUBADDR8), offset 0x0C2 ...................... 870
USB Transmit Hub Address Endpoint 9 (USBTXHUBADDR9), offset 0x0CA ..................... 870
USB Transmit Hub Address Endpoint 10 (USBTXHUBADDR10), offset 0x0D2 .................. 870
USB Transmit Hub Address Endpoint 11 (USBTXHUBADDR11), offset 0x0DA .................. 870
USB Transmit Hub Address Endpoint 12 (USBTXHUBADDR12), offset 0x0E2 .................. 870
USB Transmit Hub Address Endpoint 13 (USBTXHUBADDR13), offset 0x0EA .................. 870
USB Transmit Hub Address Endpoint 14 (USBTXHUBADDR14), offset 0x0F2 .................. 870
USB Transmit Hub Address Endpoint 15 (USBTXHUBADDR15), offset 0x0FA .................. 870
USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 ............................. 872
USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B ............................ 872
USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 ............................. 872
USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B ............................ 872
USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset 0x0A3 ............................ 872
USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset 0x0AB ............................ 872
USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset 0x0B3 ............................ 872
USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset 0x0BB ............................ 872
USB Transmit Hub Port Endpoint 8 (USBTXHUBPORT8), offset 0x0C3 ............................ 872
USB Transmit Hub Port Endpoint 9 (USBTXHUBPORT9), offset 0x0CB ............................ 872
USB Transmit Hub Port Endpoint 10 (USBTXHUBPORT10), offset 0x0D3 ........................ 872
USB Transmit Hub Port Endpoint 11 (USBTXHUBPORT11), offset 0x0DB ......................... 872
USB Transmit Hub Port Endpoint 12 (USBTXHUBPORT12), offset 0x0E3 ......................... 872
USB Transmit Hub Port Endpoint 13 (USBTXHUBPORT13), offset 0x0EB ........................ 872
USB Transmit Hub Port Endpoint 14 (USBTXHUBPORT14), offset 0x0F3 ......................... 872
USB Transmit Hub Port Endpoint 15 (USBTXHUBPORT15), offset 0x0FB ........................ 872
USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C ........... 874
USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 ........... 874
May 24, 2010
27
Texas Instruments-Advance Information
Table of Contents
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
Register 95:
Register 96:
Register 97:
Register 98:
Register 99:
Register 100:
Register 101:
Register 102:
Register 103:
Register 104:
Register 105:
Register 106:
Register 107:
Register 108:
Register 109:
Register 110:
Register 111:
Register 112:
Register 113:
Register 114:
Register 115:
Register 116:
Register 117:
Register 118:
Register 119:
Register 120:
Register 121:
Register 122:
Register 123:
Register 124:
Register 125:
Register 126:
Register 127:
Register 128:
Register 129:
Register 130:
Register 131:
Register 132:
Register 133:
Register 134:
USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C ........... 874
USB Receive Functional Address Endpoint 4 (USBRXFUNCADDR4), offset 0x0A4 ........... 874
USB Receive Functional Address Endpoint 5 (USBRXFUNCADDR5), offset 0x0AC .......... 874
USB Receive Functional Address Endpoint 6 (USBRXFUNCADDR6), offset 0x0B4 ........... 874
USB Receive Functional Address Endpoint 7 (USBRXFUNCADDR7), offset 0x0BC .......... 874
USB Receive Functional Address Endpoint 8 (USBRXFUNCADDR8), offset 0x0C4 ........... 874
USB Receive Functional Address Endpoint 9 (USBRXFUNCADDR9), offset 0x0CC .......... 874
USB Receive Functional Address Endpoint 10 (USBRXFUNCADDR10), offset 0x0D4 ....... 874
USB Receive Functional Address Endpoint 11 (USBRXFUNCADDR11), offset 0x0DC ....... 874
USB Receive Functional Address Endpoint 12 (USBRXFUNCADDR12), offset 0x0E4 ....... 874
USB Receive Functional Address Endpoint 13 (USBRXFUNCADDR13), offset 0x0EC ....... 874
USB Receive Functional Address Endpoint 14 (USBRXFUNCADDR14), offset 0x0F4 ....... 874
USB Receive Functional Address Endpoint 15 (USBRXFUNCADDR15), offset 0x0FC ....... 874
USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E ...................... 876
USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 ....................... 876
USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E ...................... 876
USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4), offset 0x0A6 ...................... 876
USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5), offset 0x0AE ...................... 876
USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6), offset 0x0B6 ...................... 876
USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7), offset 0x0BE ...................... 876
USB Receive Hub Address Endpoint 8 (USBRXHUBADDR8), offset 0x0C6 ...................... 876
USB Receive Hub Address Endpoint 9 (USBRXHUBADDR9), offset 0x0CE ...................... 876
USB Receive Hub Address Endpoint 10 (USBRXHUBADDR10), offset 0x0D6 ................... 876
USB Receive Hub Address Endpoint 11 (USBRXHUBADDR11), offset 0x0DE ................... 876
USB Receive Hub Address Endpoint 12 (USBRXHUBADDR12), offset 0x0E6 ................... 876
USB Receive Hub Address Endpoint 13 (USBRXHUBADDR13), offset 0x0EE .................. 876
USB Receive Hub Address Endpoint 14 (USBRXHUBADDR14), offset 0x0F6 ................... 876
USB Receive Hub Address Endpoint 15 (USBRXHUBADDR15), offset 0x0FE ................... 876
USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F ............................. 878
USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 ............................. 878
USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F ............................. 878
USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset 0x0A7 ............................. 878
USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset 0x0AF ............................. 878
USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset 0x0B7 ............................. 878
USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset 0x0BF ............................. 878
USB Receive Hub Port Endpoint 8 (USBRXHUBPORT8), offset 0x0C7 ............................. 878
USB Receive Hub Port Endpoint 9 (USBRXHUBPORT9), offset 0x0CF ............................ 878
USB Receive Hub Port Endpoint 10 (USBRXHUBPORT10), offset 0x0D7 ......................... 878
USB Receive Hub Port Endpoint 11 (USBRXHUBPORT11), offset 0x0DF ......................... 878
USB Receive Hub Port Endpoint 12 (USBRXHUBPORT12), offset 0x0E7 ......................... 878
USB Receive Hub Port Endpoint 13 (USBRXHUBPORT13), offset 0x0EF ......................... 878
USB Receive Hub Port Endpoint 14 (USBRXHUBPORT14), offset 0x0F7 ......................... 878
USB Receive Hub Port Endpoint 15 (USBRXHUBPORT15), offset 0x0FF ......................... 878
USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 .......................... 880
USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 .......................... 880
USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 .......................... 880
USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset 0x140 .......................... 880
USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset 0x150 .......................... 880
28
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 135:
Register 136:
Register 137:
Register 138:
Register 139:
Register 140:
Register 141:
Register 142:
Register 143:
Register 144:
Register 145:
Register 146:
Register 147:
Register 148:
Register 149:
Register 150:
Register 151:
Register 152:
Register 153:
Register 154:
Register 155:
Register 156:
Register 157:
Register 158:
Register 159:
Register 160:
Register 161:
Register 162:
Register 163:
Register 164:
Register 165:
Register 166:
Register 167:
Register 168:
Register 169:
Register 170:
Register 171:
Register 172:
Register 173:
Register 174:
Register 175:
Register 176:
Register 177:
Register 178:
Register 179:
Register 180:
Register 181:
Register 182:
USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset 0x160 .......................... 880
USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset 0x170 .......................... 880
USB Maximum Transmit Data Endpoint 8 (USBTXMAXP8), offset 0x180 .......................... 880
USB Maximum Transmit Data Endpoint 9 (USBTXMAXP9), offset 0x190 .......................... 880
USB Maximum Transmit Data Endpoint 10 (USBTXMAXP10), offset 0x1A0 ...................... 880
USB Maximum Transmit Data Endpoint 11 (USBTXMAXP11), offset 0x1B0 ....................... 880
USB Maximum Transmit Data Endpoint 12 (USBTXMAXP12), offset 0x1C0 ...................... 880
USB Maximum Transmit Data Endpoint 13 (USBTXMAXP13), offset 0x1D0 ...................... 880
USB Maximum Transmit Data Endpoint 14 (USBTXMAXP14), offset 0x1E0 ...................... 880
USB Maximum Transmit Data Endpoint 15 (USBTXMAXP15), offset 0x1F0 ...................... 880
USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 ................................. 882
USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 ............................... 886
USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 ................................... 888
USB Type Endpoint 0 (USBTYPE0), offset 0x10A ............................................................ 889
USB NAK Limit (USBNAKLMT), offset 0x10B .................................................................. 890
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 ............... 891
USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 ............... 891
USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 ............... 891
USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142 ............... 891
USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152 ............... 891
USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162 ............... 891
USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172 ............... 891
USB Transmit Control and Status Endpoint 8 Low (USBTXCSRL8), offset 0x182 ............... 891
USB Transmit Control and Status Endpoint 9 Low (USBTXCSRL9), offset 0x192 ............... 891
USB Transmit Control and Status Endpoint 10 Low (USBTXCSRL10), offset 0x1A2 ........... 891
USB Transmit Control and Status Endpoint 11 Low (USBTXCSRL11), offset 0x1B2 ........... 891
USB Transmit Control and Status Endpoint 12 Low (USBTXCSRL12), offset 0x1C2 .......... 891
USB Transmit Control and Status Endpoint 13 Low (USBTXCSRL13), offset 0x1D2 .......... 891
USB Transmit Control and Status Endpoint 14 Low (USBTXCSRL14), offset 0x1E2 ........... 891
USB Transmit Control and Status Endpoint 15 Low (USBTXCSRL15), offset 0x1F2 ........... 891
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 .............. 896
USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 ............. 896
USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 ............. 896
USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143 ............. 896
USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153 ............. 896
USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163 ............. 896
USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173 ............. 896
USB Transmit Control and Status Endpoint 8 High (USBTXCSRH8), offset 0x183 ............. 896
USB Transmit Control and Status Endpoint 9 High (USBTXCSRH9), offset 0x193 ............. 896
USB Transmit Control and Status Endpoint 10 High (USBTXCSRH10), offset 0x1A3 ......... 896
USB Transmit Control and Status Endpoint 11 High (USBTXCSRH11), offset 0x1B3 .......... 896
USB Transmit Control and Status Endpoint 12 High (USBTXCSRH12), offset 0x1C3 ......... 896
USB Transmit Control and Status Endpoint 13 High (USBTXCSRH13), offset 0x1D3 ......... 896
USB Transmit Control and Status Endpoint 14 High (USBTXCSRH14), offset 0x1E3 ......... 896
USB Transmit Control and Status Endpoint 15 High (USBTXCSRH15), offset 0x1F3 ......... 896
USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 ........................... 900
USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 ........................... 900
USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 ........................... 900
May 24, 2010
29
Texas Instruments-Advance Information
Table of Contents
Register 183:
Register 184:
Register 185:
Register 186:
Register 187:
Register 188:
Register 189:
Register 190:
Register 191:
Register 192:
Register 193:
Register 194:
Register 195:
Register 196:
Register 197:
Register 198:
Register 199:
Register 200:
Register 201:
Register 202:
Register 203:
Register 204:
Register 205:
Register 206:
Register 207:
Register 208:
Register 209:
Register 210:
Register 211:
Register 212:
Register 213:
Register 214:
Register 215:
Register 216:
Register 217:
Register 218:
Register 219:
Register 220:
Register 221:
Register 222:
Register 223:
Register 224:
Register 225:
Register 226:
Register 227:
Register 228:
Register 229:
Register 230:
USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144 ...........................
USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154 ...........................
USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164 ...........................
USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174 ...........................
USB Maximum Receive Data Endpoint 8 (USBRXMAXP8), offset 0x184 ...........................
USB Maximum Receive Data Endpoint 9 (USBRXMAXP9), offset 0x194 ...........................
USB Maximum Receive Data Endpoint 10 (USBRXMAXP10), offset 0x1A4 .......................
USB Maximum Receive Data Endpoint 11 (USBRXMAXP11), offset 0x1B4 .......................
USB Maximum Receive Data Endpoint 12 (USBRXMAXP12), offset 0x1C4 ......................
USB Maximum Receive Data Endpoint 13 (USBRXMAXP13), offset 0x1D4 ......................
USB Maximum Receive Data Endpoint 14 (USBRXMAXP14), offset 0x1E4 .......................
USB Maximum Receive Data Endpoint 15 (USBRXMAXP15), offset 0x1F4 .......................
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 ...............
USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 ...............
USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 ...............
USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146 ...............
USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156 ...............
USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166 ...............
USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 ...............
USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8), offset 0x186 ...............
USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9), offset 0x196 ...............
USB Receive Control and Status Endpoint 10 Low (USBRXCSRL10), offset 0x1A6 ...........
USB Receive Control and Status Endpoint 11 Low (USBRXCSRL11), offset 0x1B6 ...........
USB Receive Control and Status Endpoint 12 Low (USBRXCSRL12), offset 0x1C6 ...........
USB Receive Control and Status Endpoint 13 Low (USBRXCSRL13), offset 0x1D6 ...........
USB Receive Control and Status Endpoint 14 Low (USBRXCSRL14), offset 0x1E6 ...........
USB Receive Control and Status Endpoint 15 Low (USBRXCSRL15), offset 0x1F6 ...........
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 ..............
USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 ..............
USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 ..............
USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147 ..............
USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157 ..............
USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167 ..............
USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177 ..............
USB Receive Control and Status Endpoint 8 High (USBRXCSRH8), offset 0x187 ..............
USB Receive Control and Status Endpoint 9 High (USBRXCSRH9), offset 0x197 ..............
USB Receive Control and Status Endpoint 10 High (USBRXCSRH10), offset 0x1A7 ..........
USB Receive Control and Status Endpoint 11 High (USBRXCSRH11), offset 0x1B7 ..........
USB Receive Control and Status Endpoint 12 High (USBRXCSRH12), offset 0x1C7 .........
USB Receive Control and Status Endpoint 13 High (USBRXCSRH13), offset 0x1D7 .........
USB Receive Control and Status Endpoint 14 High (USBRXCSRH14), offset 0x1E7 ..........
USB Receive Control and Status Endpoint 15 High (USBRXCSRH15), offset 0x1F7 ..........
USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 ..............................
USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 ..............................
USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 ..............................
USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148 ..............................
USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158 ..............................
USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168 ..............................
30
900
900
900
900
900
900
900
900
900
900
900
900
902
902
902
902
902
902
902
902
902
902
902
902
902
902
902
907
907
907
907
907
907
907
907
907
907
907
907
907
907
907
912
912
912
912
912
912
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 231:
Register 232:
Register 233:
Register 234:
Register 235:
Register 236:
Register 237:
Register 238:
Register 239:
Register 240:
Register 241:
Register 242:
Register 243:
Register 244:
Register 245:
Register 246:
Register 247:
Register 248:
Register 249:
Register 250:
Register 251:
Register 252:
Register 253:
Register 254:
Register 255:
Register 256:
Register 257:
Register 258:
Register 259:
Register 260:
Register 261:
Register 262:
Register 263:
Register 264:
Register 265:
Register 266:
Register 267:
Register 268:
Register 269:
Register 270:
Register 271:
Register 272:
Register 273:
Register 274:
Register 275:
Register 276:
Register 277:
Register 278:
USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178 ..............................
USB Receive Byte Count Endpoint 8 (USBRXCOUNT8), offset 0x188 ..............................
USB Receive Byte Count Endpoint 9 (USBRXCOUNT9), offset 0x198 ..............................
USB Receive Byte Count Endpoint 10 (USBRXCOUNT10), offset 0x1A8 ..........................
USB Receive Byte Count Endpoint 11 (USBRXCOUNT11), offset 0x1B8 ...........................
USB Receive Byte Count Endpoint 12 (USBRXCOUNT12), offset 0x1C8 ..........................
USB Receive Byte Count Endpoint 13 (USBRXCOUNT13), offset 0x1D8 ..........................
USB Receive Byte Count Endpoint 14 (USBRXCOUNT14), offset 0x1E8 ..........................
USB Receive Byte Count Endpoint 15 (USBRXCOUNT15), offset 0x1F8 ..........................
USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ...................
USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ...................
USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ...................
USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4), offset 0x14A ...................
USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5), offset 0x15A ...................
USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6), offset 0x16A ...................
USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7), offset 0x17A ...................
USB Host Transmit Configure Type Endpoint 8 (USBTXTYPE8), offset 0x18A ...................
USB Host Transmit Configure Type Endpoint 9 (USBTXTYPE9), offset 0x19A ...................
USB Host Transmit Configure Type Endpoint 10 (USBTXTYPE10), offset 0x1AA ...............
USB Host Transmit Configure Type Endpoint 11 (USBTXTYPE11), offset 0x1BA ...............
USB Host Transmit Configure Type Endpoint 12 (USBTXTYPE12), offset 0x1CA ..............
USB Host Transmit Configure Type Endpoint 13 (USBTXTYPE13), offset 0x1DA ..............
USB Host Transmit Configure Type Endpoint 14 (USBTXTYPE14), offset 0x1EA ...............
USB Host Transmit Configure Type Endpoint 15 (USBTXTYPE15), offset 0x1FA ...............
USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B .......................
USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B .......................
USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B .......................
USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4), offset 0x14B .......................
USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5), offset 0x15B .......................
USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6), offset 0x16B .......................
USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7), offset 0x17B .......................
USB Host Transmit Interval Endpoint 8 (USBTXINTERVAL8), offset 0x18B .......................
USB Host Transmit Interval Endpoint 9 (USBTXINTERVAL9), offset 0x19B .......................
USB Host Transmit Interval Endpoint 10 (USBTXINTERVAL10), offset 0x1AB ...................
USB Host Transmit Interval Endpoint 11 (USBTXINTERVAL11), offset 0x1BB ...................
USB Host Transmit Interval Endpoint 12 (USBTXINTERVAL12), offset 0x1CB ...................
USB Host Transmit Interval Endpoint 13 (USBTXINTERVAL13), offset 0x1DB ...................
USB Host Transmit Interval Endpoint 14 (USBTXINTERVAL14), offset 0x1EB ...................
USB Host Transmit Interval Endpoint 15 (USBTXINTERVAL15), offset 0x1FB ...................
USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ...................
USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ...................
USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ...................
USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4), offset 0x14C ...................
USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5), offset 0x15C ...................
USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6), offset 0x16C ...................
USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7), offset 0x17C ...................
USB Host Configure Receive Type Endpoint 8 (USBRXTYPE8), offset 0x18C ...................
USB Host Configure Receive Type Endpoint 9 (USBRXTYPE9), offset 0x19C ...................
May 24, 2010
912
912
912
912
912
912
912
912
912
914
914
914
914
914
914
914
914
914
914
914
914
914
914
914
916
916
916
916
916
916
916
916
916
916
916
916
916
916
916
918
918
918
918
918
918
918
918
918
31
Texas Instruments-Advance Information
Table of Contents
Register 279:
Register 280:
Register 281:
Register 282:
Register 283:
Register 284:
Register 285:
Register 286:
Register 287:
Register 288:
Register 289:
Register 290:
Register 291:
Register 292:
Register 293:
Register 294:
Register 295:
Register 296:
Register 297:
Register 298:
Register 299:
Register 300:
Register 301:
Register 302:
Register 303:
Register 304:
Register 305:
Register 306:
Register 307:
Register 308:
Register 309:
Register 310:
Register 311:
Register 312:
Register 313:
USB Host Configure Receive Type Endpoint 10 (USBRXTYPE10), offset 0x1AC ...............
USB Host Configure Receive Type Endpoint 11 (USBRXTYPE11), offset 0x1BC ...............
USB Host Configure Receive Type Endpoint 12 (USBRXTYPE12), offset 0x1CC ...............
USB Host Configure Receive Type Endpoint 13 (USBRXTYPE13), offset 0x1DC ...............
USB Host Configure Receive Type Endpoint 14 (USBRXTYPE14), offset 0x1EC ...............
USB Host Configure Receive Type Endpoint 15 (USBRXTYPE15), offset 0x1FC ...............
USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D .............
USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ............
USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ............
USB Host Receive Polling Interval Endpoint 4 (USBRXINTERVAL4), offset 0x14D ............
USB Host Receive Polling Interval Endpoint 5 (USBRXINTERVAL5), offset 0x15D ............
USB Host Receive Polling Interval Endpoint 6 (USBRXINTERVAL6), offset 0x16D ............
USB Host Receive Polling Interval Endpoint 7 (USBRXINTERVAL7), offset 0x17D ............
USB Host Receive Polling Interval Endpoint 8 (USBRXINTERVAL8), offset 0x18D ............
USB Host Receive Polling Interval Endpoint 9 (USBRXINTERVAL9), offset 0x19D ............
USB Host Receive Polling Interval Endpoint 10 (USBRXINTERVAL10), offset 0x1AD ........
USB Host Receive Polling Interval Endpoint 11 (USBRXINTERVAL11), offset 0x1BD .........
USB Host Receive Polling Interval Endpoint 12 (USBRXINTERVAL12), offset 0x1CD ........
USB Host Receive Polling Interval Endpoint 13 (USBRXINTERVAL13), offset 0x1DD ........
USB Host Receive Polling Interval Endpoint 14 (USBRXINTERVAL14), offset 0x1ED ........
USB Host Receive Polling Interval Endpoint 15 (USBRXINTERVAL15), offset 0x1FD ........
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset
0x304 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset
0x308 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset
0x30C ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 4 (USBRQPKTCOUNT4), offset
0x310 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 5 (USBRQPKTCOUNT5), offset
0x314 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 6 (USBRQPKTCOUNT6), offset
0x318 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 7 (USBRQPKTCOUNT7), offset
0x31C ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 8 (USBRQPKTCOUNT8), offset
0x320 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 9 (USBRQPKTCOUNT9), offset
0x324 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 10 (USBRQPKTCOUNT10), offset
0x328 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 11 (USBRQPKTCOUNT11), offset
0x32C ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 12 (USBRQPKTCOUNT12), offset
0x330 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 13 (USBRQPKTCOUNT13), offset
0x334 ...........................................................................................................................
USB Request Packet Count in Block Transfer Endpoint 14 (USBRQPKTCOUNT14), offset
0x338 ...........................................................................................................................
32
918
918
918
918
918
918
920
920
920
920
920
920
920
920
920
920
920
920
920
920
920
922
922
922
922
922
922
922
922
922
922
922
922
922
922
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 314: USB Request Packet Count in Block Transfer Endpoint 15 (USBRQPKTCOUNT15), offset
0x33C ........................................................................................................................... 922
Register 315: USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ............. 924
Register 316: USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 ............ 926
Register 317: USB External Power Control (USBEPC), offset 0x400 ...................................................... 928
Register 318: USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ................. 931
Register 319: USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 ............................ 932
Register 320: USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ......... 933
Register 321: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 ............................ 934
Register 322: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ....................................... 935
Register 323: USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................... 936
Register 324: USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................... 937
Register 325: USB VBUS Droop Control (USBVDC), offset 0x430 ......................................................... 938
Register 326: USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS), offset 0x434 .................... 939
Register 327: USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset 0x438 ............................... 940
Register 328: USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC), offset 0x43C ............ 941
Register 329: USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset 0x444 .............................. 942
Register 330: USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448 ......................................... 943
Register 331: USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C ...................... 944
Register 332: USB DMA Select (USBDMASEL), offset 0x450 ................................................................ 945
Analog Comparators ................................................................................................................... 947
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ..................................
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 .......................................
Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 .........................................
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 .......................
Analog Comparator Status 0 (ACSTAT0), offset 0x020 .....................................................
Analog Comparator Status 1 (ACSTAT1), offset 0x040 .....................................................
Analog Comparator Status 2 (ACSTAT2), offset 0x060 .....................................................
Analog Comparator Control 0 (ACCTL0), offset 0x024 .....................................................
Analog Comparator Control 1 (ACCTL1), offset 0x044 .....................................................
Analog Comparator Control 2 (ACCTL2), offset 0x064 ....................................................
954
955
956
957
958
958
958
959
959
959
Pulse Width Modulator (PWM) .................................................................................................... 961
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
PWM Master Control (PWMCTL), offset 0x000 ................................................................ 977
PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 979
PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 980
PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 982
PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 984
PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 986
PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 988
PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 991
PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 994
PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ............................................ 996
PWM Enable Update (PWMENUPD), offset 0x028 ........................................................... 998
PWM0 Control (PWM0CTL), offset 0x040 ..................................................................... 1002
PWM1 Control (PWM1CTL), offset 0x080 ..................................................................... 1002
PWM2 Control (PWM2CTL), offset 0x0C0 .................................................................... 1002
PWM3 Control (PWM3CTL), offset 0x100 ...................................................................... 1002
PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................. 1007
May 24, 2010
33
Texas Instruments-Advance Information
Table of Contents
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................. 1007
PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................. 1007
PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104 ................................... 1007
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................. 1010
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................. 1010
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................. 1010
PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108 ................................................... 1010
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ......................................... 1012
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ......................................... 1012
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ......................................... 1012
PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C .......................................... 1012
PWM0 Load (PWM0LOAD), offset 0x050 ..................................................................... 1014
PWM1 Load (PWM1LOAD), offset 0x090 ..................................................................... 1014
PWM2 Load (PWM2LOAD), offset 0x0D0 ..................................................................... 1014
PWM3 Load (PWM3LOAD), offset 0x110 ...................................................................... 1014
PWM0 Counter (PWM0COUNT), offset 0x054 .............................................................. 1015
PWM1 Counter (PWM1COUNT), offset 0x094 .............................................................. 1015
PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................. 1015
PWM3 Counter (PWM3COUNT), offset 0x114 ............................................................... 1015
PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................ 1016
PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................ 1016
PWM2 Compare A (PWM2CMPA), offset 0x0D8 ........................................................... 1016
PWM3 Compare A (PWM3CMPA), offset 0x118 ............................................................. 1016
PWM0 Compare B (PWM0CMPB), offset 0x05C ........................................................... 1017
PWM1 Compare B (PWM1CMPB), offset 0x09C ........................................................... 1017
PWM2 Compare B (PWM2CMPB), offset 0x0DC .......................................................... 1017
PWM3 Compare B (PWM3CMPB), offset 0x11C ............................................................ 1017
PWM0 Generator A Control (PWM0GENA), offset 0x060 .............................................. 1018
PWM1 Generator A Control (PWM1GENA), offset 0x0A0 .............................................. 1018
PWM2 Generator A Control (PWM2GENA), offset 0x0E0 .............................................. 1018
PWM3 Generator A Control (PWM3GENA), offset 0x120 ............................................... 1018
PWM0 Generator B Control (PWM0GENB), offset 0x064 .............................................. 1021
PWM1 Generator B Control (PWM1GENB), offset 0x0A4 .............................................. 1021
PWM2 Generator B Control (PWM2GENB), offset 0x0E4 .............................................. 1021
PWM3 Generator B Control (PWM3GENB), offset 0x124 ............................................... 1021
PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 .............................................. 1024
PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ............................................... 1024
PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 .............................................. 1024
PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128 ............................................... 1024
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ........................... 1025
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ........................... 1025
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ........................... 1025
PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C ............................ 1025
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ........................... 1026
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ........................... 1026
PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ........................... 1026
PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130 ............................ 1026
PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 .................................................. 1027
34
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 .................................................. 1027
PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 .................................................. 1027
PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134 .................................................. 1027
PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078 .................................................. 1029
PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 .................................................. 1029
PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 .................................................. 1029
PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138 .................................................. 1029
PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C ................................... 1032
PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC ................................... 1032
PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC ................................... 1032
PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C ................................... 1032
PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 .......................................... 1033
PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880 .......................................... 1033
PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900 .......................................... 1033
PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980 .......................................... 1033
PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 ................................................... 1034
PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 ................................................... 1034
PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 ................................................... 1034
PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984 ................................................... 1034
PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808 ................................................... 1036
PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888 ................................................... 1036
PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908 ................................................... 1036
PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988 ................................................... 1036
Quadrature Encoder Interface (QEI) ........................................................................................ 1039
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
QEI Control (QEICTL), offset 0x000 ..............................................................................
QEI Status (QEISTAT), offset 0x004 ..............................................................................
QEI Position (QEIPOS), offset 0x008 ............................................................................
QEI Maximum Position (QEIMAXPOS), offset 0x00C .....................................................
QEI Timer Load (QEILOAD), offset 0x010 .....................................................................
QEI Timer (QEITIME), offset 0x014 ...............................................................................
QEI Velocity Counter (QEICOUNT), offset 0x018 ...........................................................
QEI Velocity (QEISPEED), offset 0x01C ........................................................................
QEI Interrupt Enable (QEIINTEN), offset 0x020 .............................................................
QEI Raw Interrupt Status (QEIRIS), offset 0x024 ...........................................................
QEI Interrupt Status and Clear (QEIISC), offset 0x028 ...................................................
May 24, 2010
1046
1049
1050
1051
1052
1053
1054
1055
1056
1058
1060
35
Texas Instruments-Advance Information
Revision History
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S5B91
data sheet.
Table 1. Revision History
Date
Revision
May 2009
5285
Description
Started tracking revision history.
June 2009
5779
■
In System Control chapter, clarified power-on reset and external reset pin descriptions in "Reset
Sources" section.
■
Added missing comparator output pin bits to DC3 register; reset value changed as well.
■
Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■
Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0
registers.
■
In Request Type Support table in DMA chapter, corrected general-purpose timer row.
■
In General-Purpose Timers chapter, clarified DMA operation.
■
Added table "Preliminary Current Consumption" to Characteristics chapter.
■
Corrected Nom and Max values in "Hibernation Detailed Current Specifications" table.
■
Corrected Nom and Max values in EPI Characteristics table.
■
Added "CSn to output invalid" parameter to EPI table "EPI Host-Bus 8 and Host-Bus 16 Interface
Characteristics" and figure "Host-Bus 8/16 Mode Read Timing".
■
Corrected INL, DNL, OFF and GAIN values in ADC Characteristics table.
■
Updated ROM DriverLib appendix with RevC0 functions.
■
Updated part ordering numbers.
■
Additional minor data sheet clarifications and corrections.
36
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Stellaris® LM3S5B91 Microcontroller
Table 1. Revision History (continued)
Date
Revision
July 2009
5930
Description
■
Added "Non-Blocking Read Cycle", "Normal Read Cycle", and "Write Cycle" sections to EPI chapter.
■
Corrected values for MAXADC0SPD and MAXADC1SPD bits in DC1, RCGC0, SCGC0, and DCGC0
registers.
■
Corrected figure "TI Synchronous Serial Frame Format (Single Transfer)".
■
Made a number of corrections to the Electrical Characteristics chapter:
–
Deleted VBAT and VREFA parameters from and added footnotes to Recommended DC Operating
Conditions table.
–
Deleted Nominal and Maximum Current Specifications section.
–
Modified EPI SDRAM Characteristics table:
•
Changed tEPIR to tSDRAMR and deleted values for 2-mA and 4-mA drive.
•
Changed tEPIF to tSDRAMF and deleted values for 2-mA and 4-mA drive.
–
Changed values for tCOV, tCOI, and tCOT parameters in EPI SDRAM Interface Characteristics
table.
–
Deleted SDRAM Read Command Timing, SDRAM Write Command Timing, SDRAM Write Burst
Timing, SDRAM Precharge Command Timing and SDRAM CAS Latency Timing figures and
replaced with SDRAM Read Timing and SDRAM Write Timing figures.
–
Modified Host-Bus 8/16 Mode Write Timing figure.
–
Modified General-Purpose Mode Read and Write Timing figure.
–
Modified values for tDV and tDI parameters, and deleted tOD parameter from EPI General-Purpose
Interface Characteristics figure.
–
Major changes to ADC Characteristics tables, including adding additonal tables and diagram.
■
Added missing ROM_I2SIntStatus function to ROM DriverLib Functions appendix.
■
Corrected ordering part numbers.
■
Additional minor data sheet clarifications and corrections.
May 24, 2010
37
Texas Instruments-Advance Information
Revision History
Table 1. Revision History (continued)
Date
Revision
October 2009
6458
Description
®
■
Released new 1000, 3000, 5000 and 9000 series Stellaris devices.
■
The IDCODE value was corrected to be 0x4BA0.0477.
■
Clarified that the NMISET bit in the ICSR register in the NVIC is also a source for NMI.
■
Clarified the use of the LDO.
■
To clarify clock operation, reorganized clocking section, changed the USEFRACT bit to the DIV400
bit and the FRACT bit to the SYSDIV2LSB bit in the RCC2 register, added tables, and rewrote
descriptions.
■
Corrected bit description of the DSDIVORIDE field in the DSLPCLKCFG register.
■
Removed the DSFLASHCFG register at System Control offset 0x14C as it does not function correctly.
■
Removed the MAXADC1SPD and MAXADC0SPD fields from the DCGC0 as they have no function in
deep-sleep mode.
■
Corrected address offsets for the Flash Write Buffer (FWBn) registers.
■
Added Flash Control (FCTL) register at Internal memory offset 0x0F8 to help control frequent
power cycling when hibernation is not used.
■
Changed the name of the EPI channels for clarification: EPI0_TX became EPI0_WFIFO and EPI0_RX
became EPI0_NBRFIFO. This change was also made in the DC7 bit descriptions.
■
Removed the DMACHIS register at DMA module offset 0x504 as it does not function correctly.
■
Corrected alternate channel assignments for the µDMA controller.
■
Major improvements to the EPI chapter.
■
EPISDRAMCFG2 register was deleted as its function is not needed.
■
Clarified CAN bit timing and corrected examples.
■
Clarified PWM source for ADC triggering
■
Corrected ADDR field in the USBTXFIFOADD register to be 9 bits instead of 13 bits.
■
Changed SSI set up and hold times to be expressed in system clocks, not ns.
■
Updated Electrical Characteristics chapter with latest data. Changes were made to ADC and EPI
content.
■
Additional minor data sheet clarifications and corrections.
38
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Stellaris® LM3S5B91 Microcontroller
Table 1. Revision History (continued)
Date
Revision
February 2010
6790
March 2010
March 2010
6912
6983
Description
■
Added 108-ball BGA package.
■
In "System Control" chapter:
– Clarified functional description for external reset and brown-out reset.
– Clarified Debug Access Port operation after Sleep modes.
– Corrected the reset value of the Run-Mode Clock Configuration 2 (RCC2) register.
■
In "Internal Memory" chapter, clarified wording on Flash memory access errors and added a section
on interrupts to the Flash memory description.
■
In "External Peripheral Interface" chapter:
– Added clarification about byte selects and dual chip selects.
– Added timing diagrams for continuous-read mode (formerly SRAM mode).
– Corrected reset values of EPI Write FIFO Count (EPIWFIFOCNT) and EPI Raw Interrupt
Status (EPIRIS) registers.
■
Added clarification about timer operating modes and added register descriptions for the GPTM
Timer n Prescale Match (GPTMTnPMR) registers.
■
Clarified register descriptions for GPTM Timer A Value (GPTMTAV) and GPTM Timer B Value
(GPTMTBV) registers.
■
Corrected the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers.
■
Added ADC Sample Phase Control (ADCSPC) register at offset 0x24.
■
Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■
In the "Controller Area Network" chapter, added clarification about reading from the CAN FIFO
buffer and clarified packet timestamps functional description.
■
Added Session Disconnect (DISCON) bit to the USB General Interrupt Status (USBIS) and
USB Interrupt Enable (USBIE) registers.
■
Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■
Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
– Added table entry for VDD3ON power consumption to Table 26-7 on page 1144.
■
Added additional DriverLib functions to appendix.
■
Renamed the USER_DBG register to the BOOTCFG register in the Internal Memory chapter. Added
information on how to use a GPIO pin to force the ROM Boot Loader to execute on reset.
■
Added three figures to the ADC chapter on sample phase control.
■
Clarified configuration of USB0VBUS and USB0ID in OTG mode.
■
Corrected reset for EPIHB8CFG, EPI_HB16CFG and EPIGPCFG registers.
■
Extended TBRL bit field in GPTMTBR register.
■
Additional minor data sheet clarifications and corrections.
May 24, 2010
39
Texas Instruments-Advance Information
Revision History
Table 1. Revision History (continued)
Date
Revision
May 2010
7101
May 2010
7164
Description
■
Added pin table "Possible Pin Assignments for Alternate Functions", which lists the signals based
on number of possible pin assignments. This table can be used to plan how to configure the pins
for a particular functionality.
■
Additional minor data sheet clarifications and corrections.
■
Added data sheets for five new Stellaris® Tempest-class parts: LM3S1R26, LM3S1621, LM3S1B21,
LM3S9781, and LM3S9B81.
■
Additional minor data sheet clarifications and corrections.
40
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
About This Document
This data sheet provides reference information for the LM3S5B91 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
®
The following related documents are available on the documentation CD or from the Stellaris web
site at www.ti.com/stellaris:
■ Stellaris® Errata
■ ARM® Cortex™-M3 Errata
■ ARM® CoreSight Technical Reference Manual
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
■ Stellaris® Boot Loader User's Guide
■ Stellaris® Graphics Library User's Guide
■ Stellaris® Peripheral Driver Library User's Guide
■ Stellaris® ROM User’s Guide
■ Stellaris® USB Library User's Guide
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
May 24, 2010
41
Texas Instruments-Advance Information
About This Document
Documentation Conventions
This document uses the conventions shown in Table 2 on page 42.
Table 2. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
Two or more consecutive and related bits.
offset 0xnnn
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 81.
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field
Types
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
RC
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO
Software can read this field. Always write the chip reset value.
R/W
Software can read or write this field.
R/W1C
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1S
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO
Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field
Reset Value
This value in the register bit diagram shows the bit/field value after any reset, unless noted.
0
Bit cleared to 0 on chip reset.
1
Bit set to 1 on chip reset.
-
Nondeterministic.
Pin/Signal Notation
[]
Pin alternate function; a pin defaults to the signal without the brackets.
pin
Refers to the physical connection on the package.
signal
Refers to the electrical signal encoding of a pin.
42
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 2. Documentation Conventions (continued)
Notation
Meaning
assert a signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal
Change the value of the signal from the logically True state to the logically False state.
SIGNAL
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
May 24, 2010
43
Texas Instruments-Advance Information
Architectural Overview
1
Architectural Overview
Texas Instruments is the industry leader in bringing 32-bit capabilities and the full benefits of ARM®
Cortex-M3™-based microcontrollers to the broadest reach of the microcontroller market. For current
®
users of 8- and 16-bit MCUs, Stellaris with Cortex-M3 offers a direct path to the strongest ecosystem
®
of development tools, software and knowledge in the industry. Designers who migrate to Stellaris
benefit from great tools, small code footprint and outstanding performance. Even more important,
designers can enter the ARM ecosystem with full confidence in a compatible roadmap from $1 to
®
1 GHz. For users of current 32-bit MCUs, the Stellaris family offers the industry’s first implementation
of Cortex-M3 and the Thumb-2 instruction set. With blazingly-fast responsiveness, Thumb-2
technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density
and performance. Thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system
®
cost while delivering 25 percent better performance. The Texas Instruments Stellaris family of
microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit
computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver
customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package
with a small footprint.
The LM3S5B91 microcontroller has the following features:
■ ARM® Cortex™-M3 Processor Core
– 80-MHz operation; 100 DMIPS performance
– ARM Cortex SysTick Timer
– Nested Vectored Interrupt Controller (NVIC)
■ On-Chip Memory
– 256 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance
above 50 MHz
– 96 KB single-cycle SRAM
®
– Internal ROM loaded with StellarisWare software:
®
•
Stellaris Peripheral Driver Library
•
Stellaris Boot Loader
•
Advanced Encryption Standard (AES) cryptography tables
•
Cyclic Redundancy Check (CRC) error detection functionality
®
■ External Peripheral Interface (EPI)
– 8/16/32-bit dedicated parallel bus for external peripherals
– Supports SDRAM, SRAM/Flash memory, FPGAs, CPLDs
■ Advanced Serial Integration
– Two CAN 2.0 A/B controllers
44
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
– USB 2.0 OTG/Host/Device
– Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls)
– Two I2C modules
– Two Synchronous Serial Interface modules (SSI)
– Integrated Interchip Sound (I2S) module
■ System Integration
– Direct Memory Access Controller (DMA)
– System control and clocks including on-chip precision 16-MHz oscillator
– Four 32-bit timers (up to eight 16-bit)
– Eight Capture Compare PWM pins (CCP)
– Real-Time Clock
– Two Watchdog Timers
•
One timer runs off the main oscillator
•
One timer runs off the precision internal oscillator
– Up to 72 GPIOs, depending on configuration
•
Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
•
Independently configurable to 2, 4 or 8 mA drive capability
•
Up to 4 GPIOs can have 18 mA drive capability
■ Advanced Motion Control
– Eight advanced PWM outputs for motion and energy applications
– Four fault inputs to promote low-latency shutdown
– Two Quadrature Encoder Inputs (QEI)
■ Analog
– Two 10-bit Analog-to-Digital Converters (ADC) with sixteen analog input channels and sample
rate of one million samples/second
– Three analog comparators
– 16 digital comparators
– On-chip voltage regulator
■ JTAG and ARM Serial Wire Debug (SWD)
May 24, 2010
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Texas Instruments-Advance Information
Architectural Overview
■ 100-pin LQFP and 108-ball BGA package
■ Industrial (-40°C to 85°C) Temperature Range
®
The Stellaris LM3S5000 series, designed for Controller Area Network (CAN) applications, extends
®
the Stellaris family with Bosch CAN networking technology combined with USB 2.0 Full or Low
Speed On-The-Go (OTG) or Host/Device capabilities. The LM3S5000 microcontrollers are perfect
for cost-effective embedded control applications requiring industrial connectivity. The motion control
features are suitable for fault conditioning and sophisticated motion control.
The LM3S5B91 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
In addition, the LM3S5B91 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S5B91 microcontroller is code-compatible
®
to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact Information” on page
®
1263 for ordering information for Stellaris family devices.
1.1
Functional Overview
The following sections provide an overview of the features of the LM3S5B91 microcontroller. The
page number in parentheses indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 1263.
1.1.1
ARM Cortex™-M3
The following sections provide an overview of the ARM Cortex™-M3 processor core and instruction
set, the integrated System Timer (SysTick) and the Nested Vectored Interrupt Controller.
1.1.1.1
Processor Core (see page 68)
®
All members of the Stellaris product family, including the LM3S5B91 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
■ 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set, delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices; typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
46
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast multiplier
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage
■ Ultra-low power consumption with integrated sleep modes
■ 80-MHz operation
■ 1.25 DMIPS/MHz
“ARM Cortex-M3 Processor Core” on page 68 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.1.1.2
System Timer (SysTick) (see page 78)
ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter
■ A simple counter used to measure time to completion and time used
■ An internal clock-source control based on missing/meeting durations. The COUNTFLAG field in
the SysTick Control and Status register can be used to determine if an action completed within
a set duration, as part of a dynamic clock management control loop
May 24, 2010
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Texas Instruments-Advance Information
Architectural Overview
1.1.1.3
Nested Vectored Interrupt Controller (NVIC) (see page 84)
The LM3S5B91 controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC
and Cortex-M3 prioritize and handle all exceptions in Handler Mode. The processor state is
automatically stored to the stack on an exception and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state
saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 52 interrupts.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
“Interrupts” on page 84 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.1.2
On-Chip Memory
The following sections describe the on-chip memory modules.
1.1.2.1
SRAM (see page 205)
The LM3S5B91 microcontroller provides 96 KB of single-cycle on-chip SRAM. The internal SRAM
®
of the Stellaris devices is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller
(µDMA).
1.1.2.2
Flash Memory (see page 205)
The LM3S5B91 microcontroller provides 256 KB of single-cycle on-chip Flash memory (above 50
MHz, the Flash memory can be accessed in a single cycle as long as the code is linear; branches
incur a one-cycle stall). The Flash memory is organized as a set of 2-KB blocks that can be
individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s.
These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can
be marked as read-only or execute-only, providing different levels of code protection. Read-only
blocks cannot be erased or programmed, protecting the contents of those blocks from being modified.
Execute-only blocks cannot be erased or programmed, and can only be read by the controller
instruction fetch mechanism, protecting the contents of those blocks from being read by either the
controller or by a debugger.
1.1.2.3
ROM (see page 1167)
The LM3S5B91 ROM is preprogrammed with the following software and programs:
®
■ Stellaris Peripheral Driver Library
48
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
®
■ Stellaris Boot Loader
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error-detection functionality
®
The Stellaris Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM® Cortex™-M3
core. No special pragmas or custom assembly code prologue/epilogue functions are required. For
®
applications that require in-field programmability, the royalty-free Stellaris Boot Loader can act as
an application loader and support in-field firmware updates.
The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government. AES is a strong encryption method with reasonable performance and size. In
addition, it is fast in both hardware and software, is fairly easy to implement, and requires little
memory. The Texas Instruments encryption package is available with full source code, and is based
on lesser general public license (LGPL) source. An LGPL means that the code can be used within
an application without any copyleft implications for the application (the code does not automatically
become open source). Modifications to the package source, however, must be open source.
CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents
as when previously checked. This technique can be used to validate correct receipt of messages
(nothing lost or modified in transit), to validate data after decompression, to validate that Flash
memory contents have not been changed, and for other cases where the data needs to be validated.
A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more
readily.
1.1.3
External Peripheral Interface (see page 355)
The External Peripheral Interface (EPI) provides access to external devices using a parallel path.
Unlike communications peripherals such as SSI, UART, and I2C, the EPI is designed to act like a
bus to external peripherals and memory.
The EPI has the following features:
■ 8/16/32-bit dedicated parallel bus for external peripherals and memory
■ Memory interface supports contiguous memory access independent of data bus width, thus
enabling code execution directly from SDRAM, SRAM and Flash memory
■ Blocking and non-blocking reads
■ Separates processor from timing details through use of an internal write FIFO
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for read and write
– Read channel request asserted by programmable levels on the internal non-blocking read
FIFO (NBRFIFO)
– Write channel request asserted by empty on the internal write FIFO (WFIFO)
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The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory
(SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also
provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same
way as a communication mechanism and is speed-controlled using clocking.
■ Synchronous Dynamic Random Access Memory (SDRAM)
– Supports x16 (single data rate) SDRAM at up to 50 MHz
– Supports low-cost SDRAMs up to 64 MB (512 megabits)
– Includes automatic refresh and access to all banks/rows
– Includes a Sleep/Standby mode to keep contents active with minimal power draw
– Multiplexed address/data interface for reduced pin count
■ Host-bus
– Traditional x8 and x16 MCU bus interface capabilities
– Similar device compatibility options as PIC, ATmega, 8051, and others
– Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in
unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with
no byte selects)
– Support of both muxed and de-muxed address and data
– Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
with support for external FIFO (XFIFO) EMPTY and FULL signals
– Speed controlled, with read and write data wait-state counters
– Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn
– Manual chip-enable (or use extra address pins)
■ General Purpose
– Wide parallel interfaces for fast communications with CPLDs and FPGAs
– Data widths up to 32-bits
– Data rates up to 150 MB/second
– Optional “address” sizes from 4 bits to 20 bits
– Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable
input
■ General parallel GPIO
– 1 to 32 bits, FIFOed with speed control
– Useful for custom peripherals or for digital data acquisition and actuator controls
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1.1.4
Serial Communications Peripherals
The LM3S5B91 controller supports both asynchronous and synchronous serial communications
with:
■ Two CAN 2.0 A/B Controllers
■ USB 2.0 (full speed and low speed) OTG/Host/Device
■ Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls)
■ Two I2C modules
■ Two Synchronous Serial Interface modules (SSI)
■ Integrated Interchip Sound (I2S) Module
The following sections provide more detail on each of these communications functions.
1.1.4.1
Controller Area Network (see page 756)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally
created for automotive purposes, it is now used in many embedded control applications (for example,
industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters.
Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information.
The LM3S5B91 microcontroller includes two CAN units with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable Loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
1.1.4.2
USB (see page 808)
Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected
and disconnected using a standardized interface without rebooting the system.
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The LM3S5B91 controller supports three configurations in USB 2.0 full and low speed: USB Device,
USB Host, and USB On-The-Go (negotiated on-the-go as host or device when connected to other
USB-enabled systems).
The USB module has the following features:
■ Complies with USB-IF certification standards
■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation
■ Integrated PHY
■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous
■ 32 endpoints
– 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
■ VBUS droop and valid ID detection and interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive for up to three IN endpoints and three OUT
endpoints
– Channel requests asserted when FIFO contains required amount of data
1.1.4.3
UART (see page 579)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S5B91 controller includes three fully programmable 16C550-type UARTs. Although the
functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART
can generate individually masked interrupts from the Rx, Tx, modem status, and error conditions.
The module generates a single combined interrupt when any of the interrupts are asserted and are
unmasked.
The three UARTs have the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
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■ False-start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Full modem handshake support (on UART1)
■ LIN protocol support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
1.1.4.4
I2C (see page 682)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I2C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I2C bus can be designated as either a master or a slave. Each I2C module
supports both sending and receiving data as either a master or a slave and can operate
simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts.
The LM3S5B91 controller includes two I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
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– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
1.1.4.5
SSI (see page 640)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts
data between parallel and serial. The SSI module performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The SSI module can be configured as either a master or slave device. As a slave device,
the SSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
The LM3S5B91 controller includes two SSI modules with the following features:
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
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■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when FIFO contains 4 entries
1.1.4.6
Inter-Integrated Circuit Sound (I2S) Interface (see page 719)
The I2S interface is a configurable serial audio core that contains a transmit module and a receive
module. The module is configurable for the I2S as well as Left-Justified and Right-Justified serial
audio formats. Data can be in one of four modes: Stereo, Mono, Compact 16-bit Stereo and Compact
8-Bit Stereo.
The transmit and receive modules each have an 8-entry audio-sample FIFO. An audio sample can
consist of a Left and Right Stereo sample, a Mono sample, or a Left and Right Compact Stereo
sample. In Compact 16-Bit Stereo, each FIFO entry contains both the 16-bit left and 16-bit right
samples, allowing efficient data transfers and requiring less memory space. In Compact 8-bit Stereo,
each FIFO entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements
further.
Both the transmitter and receiver are capable of being a master or a slave.
®
The Stellaris I2S interface has the following features:
■ Configurable audio format supporting I2S, Left-justification, and Right-justification
■ Configurable sample size from 8 to 32 bits
■ Mono and Stereo support
■ 8-, 16-, and 32-bit FIFO interface for packing memory
■ Independent transmit and receive 8-entry FIFOs
■ Configurable FIFO-level interrupt and µDMA requests
■ Independent transmit and receive MCLK direction control
■ Transmit and receive internal MCLK sources
■ Independent transmit and receive control for serial clock and word select
■ MCLK and SCLK can be independently set to master or slave
■ Configurable transmit zero or last sample when FIFO empty
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Burst requests
– Channel requests asserted when FIFO contains required amount of data
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1.1.5
System Integration
The LM3S5B91 controller provides a variety of standard system functions integrated into the device,
including:
■ Micro Direct Memory Access Controller (µDMA)
■ System control and clocks including on-chip precision 16-MHz oscillator
■ ARM Cortex SysTick Timer
■ Four 32-bit timers (up to eight 16-bit)
■ Eight Capture Compare PWM pins (CCP)
■ Real-Time Clock
■ Two Watchdog Timers
■ Up to 72 GPIOs, depending on configuration
– Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
– Independently configurable to 2, 4 or 8 mA drive capability
– Up to 4 GPIOs can have 18 mA drive capability
The following sections provide more detail on each of these functions.
1.1.5.1
Direct Memory Access (see page 240)
The LM3S5B91 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M3 processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
■ ARM PrimeCell® 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules: GP Timer, USB, UART, ADC, EPI, SSI,
I2S
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– Alternate channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable bus arbitration scheme
– Optional software-initiated requests for any channel
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Transfer size is programmable in binary steps from 1 to 1024
■ Source and destination address increment size of byte, half-word, word, or no increment
■ Maskable peripheral requests
■ Interrupt on transfer completion, with a separate interrupt per channel
1.1.5.2
System Control and Clocks (see page 99)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
■ Device identification information: version, part number, SRAM size, Flash memory size, and so
on
■ Power control
– On-chip fixed Low Drop-Out (LDO) voltage regulator
– Low-power options for microcontroller: Sleep and Deep-sleep modes with clock gating
– Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Multiple clock sources for microcontroller system clock
– Precision Oscillator (PIOSC): on-chip resource providing a 16 MHz ±1% frequency at room
temperature
•
16 MHz ±3% across temperature
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•
Software power down control for low power modes
– Main Oscillator (MOSC): a frequency-accurate clock source by one of two means: an external
single-ended clock source is connected to the OSC0 input pin, or an external crystal is
connected across the OSC0 input and OSC1 output pins.
•
External oscillator used with or without on-chip PLL: select supported frequencies from 1
MHz to 16.384 MHz.
•
External crystal: from DC to maximum device speed
– Internal 30-kHz Oscillator: on chip resource providing a 30 kHz ± 50% frequency, used during
power-saving modes
■ Flexible reset sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out reset (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– MOSC failure
1.1.5.3
Four Programmable Timers (see page 428)
Programmable timers can be used to count or time external events that drive the Timer input pins.
Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently
as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time
Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions.
The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional
options:
■ Count up or down
■ 16- or 32-bit programmable one-shot timer
■ 16- or 32-bit programmable periodic timer
■ 16-bit general-purpose timer with an 8-bit prescaler
■ 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
■ Eight Capture Compare PWM pins (CCP)
■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
■ ADC event trigger
■ User-enabled stalling when the controller asserts CPU Halt flag during debug (excluding RTC
mode)
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■ 16-bit input-edge count- or time-capture modes
■ 16-bit PWM mode with software-programmable output inversion of the PWM signal
■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine.
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each timer
– Burst request generated on timer interrupt
1.1.5.4
CCP Pins (see page 436)
Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM
output on the CCP pin.
The LM3S5B91 microcontroller includes eight Capture Compare PWM pins (CCP) that can be
programmed to operate in the following modes:
■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
1.1.5.5
Watchdog Timers (see page 476)
A watchdog timer is used to regain control when a system has failed due to a software error or to
®
the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer
can generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog
Timer is ARM FiRM-compliant and can be configured to generate an interrupt to the controller on
its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer
has been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
The LM3S5B91 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the
®
system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
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■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
1.1.5.6
Programmable GPIOs (see page 298)
®
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris
GPIO module is comprised of nine physical GPIO blocks, each corresponding to an individual GPIO
port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time
Microcontrollers specification) and supports 0-72 programmable input/output pins. The number of
GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1064 for the
signals available to each GPIO pin).
■ Up to 72 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant input/outputs
■ Fast toggle capable of a change every two clock cycles
■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back
access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility
with existing code
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
1.1.6
Advanced Motion Control
The LM3S5B91 controller provides motion control functions integrated into the device, including:
■ Eight advanced PWM outputs for motion and energy applications
■ Four fault input to promote low-latency shutdown
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■ Two Quadrature Encoder Inputs (QEI)
The following provides more detail on these motion control functions.
1.1.6.1
PWM (see page 961)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control. The LM3S5B91 PWM module consists of four PWM generator blocks and a
control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two
comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. PWM generator block has
the following features:
■ Four fault-condition handling input to quickly provide low-latency shutdown and prevent damage
to the motor being controlled
■ One 16-bit counter
– Runs in Down or Up/Down mode
– Output frequency controlled by a 16-bit load value
– Load value updates can be synchronized
– Produces output signals at zero and load value
■ Two PWM comparators
– Comparator value updates can be synchronized
– Produces output signals on match
■ PWM signal generator
– Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
– Produces two independent PWM signals
■ Dead-band generator
– Produces two PWM signals with programmable dead-band delays suitable for driving a half-H
bridge
– Can be bypassed, leaving input PWM signals unmodified
■ Can initiate an ADC sample sequence
The control block determines the polarity of the PWM signals and which signals are passed through
to the pins. The output of the PWM generation blocks are managed by the output control block
before being passed to the device pins. The PWM control block has the following options:
■ PWM output enable of each PWM signal
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■ Optional output inversion of each PWM signal (polarity control)
■ Optional fault handling for each PWM signal
■ Synchronization of timers in the PWM generator blocks
■ Synchronization of timer/comparator updates across the PWM generator blocks
■ Synchronization of PWM output enables across the PWM generator blocks
■ Interrupt status summary of the PWM generator blocks
■ Extended fault capabilities with multiple fault signals, programmable polarities, and filtering
■ PWM generators can be operated independently or synchronized with other generators
1.1.6.2
QEI (see page 1039)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index
®
signal, can be used to reset the position counter. The Stellaris quadrature encoder with index (QEI)
module interprets the code produced by a quadrature encoder wheel to integrate position over time
and determine direction of rotation. In addition, it can capture a running estimate of the velocity of
the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the processor
frequency (for example, 20 MHz for a 80-MHz system).
The LM3S5B91 microcontroller includes two QEI modules providing control of two motors at the
same time with the following features:
■ Position integrator that tracks the encoder position
■ Programmable noise filter on the inputs
■ Velocity capture using built-in timer
■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
■ Interrupt generation on:
– Index pulse
– Velocity-timer expiration
– Direction change
– Quadrature error detection
1.1.7
Analog
The LM3S5B91 controller provides analog functions integrated into the device, including:
■ Two 10-bit Analog-to-Digital Converters (ADC) with sixteen analog input channels and sample
rate of one million samples/second
■ Three analog comparators
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■ 16 digital comparators
■ On-chip voltage regulator
The following provides more detail on these analog functions.
1.1.7.1
ADC (see page 501)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
®
discrete digital number. The Stellaris ADC module features 10-bit conversion resolution and supports
sixteen input channels plus an internal temperature sensor. Four buffered sample sequencers allow
rapid sampling of up to eight analog input sources without controller intervention. Each sample
sequencer provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequencer priority. A digital comparator function is included that allows the conversion
value to be diverted to a comparison unit that provides 16 digital comparators.
The LM3S5B91 microcontroller provides two ADC modules with the following features:
■ Sixteen analog input channels
■ Single-ended and differential-input configurations
■ On-chip internal temperature sensor
■ Maximum sample rate of one million samples/second
■ Optional phase shift in sample time programmable from 22.5º to 337.5º
■ Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– PWM
– GPIO
■ Hardware averaging of up to 64 samples for improved accuracy
■ Digital comparison unit providing sixteen digital comparators
■ Converter uses an internal 3-V reference or an external reference
■ Power and ground for the analog circuitry is separate from the digital power and ground
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each sample sequencer
– ADC module uses burst requests for DMA
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1.1.7.2
Analog Comparators (see page 947)
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result. The LM3S5B91 microcontroller provides three independent
integrated analog comparators that can be configured to drive an output or generate an interrupt or
ADC event.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The LM3S5B91 microcontroller provides three independent integrated analog comparators with the
following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
1.1.8
JTAG and ARM Serial Wire Debug (see page 87)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial
Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG
debug ports into one module providing all the normal JTAG debug and test functionality plus real-time
access to system memory without halting the core or requiring any target resident code. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP. The SWJ-DP interface
has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
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– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
1.1.9
Packaging and Temperature
■ Industrial-range 100-pin RoHS-compliant LQFP package
■ Industrial-range 108-ball RoHS-compliant BGA package
1.2
Target Applications
®
The Stellaris family is positioned for cost-conscious applications requiring significant control
processing and connectivity capabilities such as:
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3
High-Level Block Diagram
®
Figure 1-1 depicts the features on the Stellaris LM3S5B91 microcontroller. Note that there are two
on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is
the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back
access performance than the APB bus.
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Architectural Overview
®
Figure 1-1. Stellaris LM3S5B91 Microcontroller High-Level Block Diagram
JTAG/SWD
ROM
ARM®
Cortex™-M3
System
Control and
Clocks
(w/ Precis. Osc.)
Boot Loader
DriverLib
AES & CRC
Flash
(256 KB)
DCode bus
(80 MHz)
ICode bus
NVIC
MPU
System Bus
LM3S5B91
Bus Matrix
SRAM
(96 KB)
SYSTEM PERIPHERALS
DMA
Watchdog
Timers
(2)
GPIOs
(72)
GeneralPurpose
Timers (4)
SSI
(2)
I2S
Advanced Peripheral Bus (APB)
USB
(OTG)
Advanced High-Performance Bus (AHB)
External
Peripheral
Interface
SERIAL PERIPHERALS
UARTs
(3)
I2C
(2)
CAN
Controllers
(2)
ANALOG PERIPHERALS
Analog
Comparators
(3)
ADC
Channels
(16)
MOTION CONTROL PERIPHERALS
PWM
(8)
QEI
(2)
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1.4
Additional Features
1.4.1
Memory Map (see page 81)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S5B91 controller can be found in “Memory Map” on page 81. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map. The
ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map.
1.4.2
Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 1062
■ “Signal Tables” on page 1064
■ “Operating Characteristics” on page 1141
■ “Electrical Characteristics” on page 1142
■ “Package Information” on page 1265
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2
ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
■ 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set, delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices; typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast multiplier
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage
■ Ultra-low power consumption with integrated sleep modes
■ 80-MHz operation
■ 1.25 DMIPS/MHz
®
The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
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For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
2.1
Block Diagram
Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
Interrupts
Sleep
ARM
Cortex-M3
CM3 Core
Debug
Instructions
Data
Trace
Port
Interface
Unit
Memory
Protection
Unit
Flash
Patch and
Breakpoint
Instrumentation
Data
Watchpoint Trace Macrocell
and Trace
ROM
Table
Private Peripheral
Bus
(internal)
Adv. Peripheral
Bus
Bus
Matrix
Debug
Access Port
Serial Wire JTAG
Debug Port
2.2
Serial
Wire
Output
Trace
Port
(SWO)
I-code bus
D-code bus
System bus
Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
®
This section describes the Stellaris implementation.
Texas Instruments implements the ARM Cortex-M3 core as shown in Figure 2-1 on page 69. The
Cortex-M3 uses the entire 16-bit Thumb instruction set and the base Thumb-2 32-bit instruction set.
In addition, as noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3
components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the
MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the
sections that follow.
2.2.1
Programming Model
This section provides a brief overview of the programming model for the Cortex-M3 core. More
detailed information can be found in the ARM® Cortex™-M3 Technical Reference Manual.
■ Privileged access and user access - Code can execute as privileged or unprivileged. Unprivileged
execution limits or excludes access to some resources. Privileged execution has access to all
resources. Handler mode is always privileged. Thread mode can be privileged or unprivileged.
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Thread mode is privileged out of reset, but you can change it to user or unprivileged by setting
the CONTROL[0] bit using the MSR instruction. User access prevents:
– Use of some instructions such as CPS to set FAULTMASK and PRIMASK
– Access to most registers in System Control Space (SCS)
When Thread mode has been changed from privileged to user, it cannot change itself back to
privileged. Only a Handler can change the privilege of Thread mode. Handler mode is always
privileged.
■ Register set - The processor has the following 32-bit registers:
– 13 general-purpose registers, r0-r12
– Stack point alias of banked registers, SP_process and SP_main
– Link register, r14
– Program counter, r15
– One program status register, xPSR.
■ Data types - The processor supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
■ Memory formats - The processor views memory as a linear collection of bytes numbered in
ascending order from 0. For example, bytes 0-3 hold the first stored word and bytes 4-7 hold the
second stored word. The processor accesses code and data in little-endian format, which means
that the byte with the lowest address in a word is the least-significant byte of the word. The byte
with the highest address in a word is the most significant. The byte at address 0 of the memory
system connects to data lines 7-0.
■ Instruction set - The Cortex-M3 instruction set contains both 16 and 32-bit instructions. These
instructions are summarized in Table 2-1 on page 70 and Table 2-2 on page 72, respectively.
Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary
Operation
Assembler
Add register value and C flag to register value
ADC ,
Add immediate 3-bit value to register
ADD , , #
Add immediate 8-bit value to register
ADD , #
Add low register value to low register value
ADD , ,
Add high register value to low or high register value
ADD ,
Add 4* (immediate 8-bit value) with PC to register
ADD , PC, # * 4
Add 4* (immediate 8-bit value) with SP to register
ADD , SP, # * 4
Add 4* (immediate 7-bit value) to SP
ADD SP, # * 4
Bitwise AND register values
AND ,
Arithmetic shift right by immediate number
ASR , , #
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Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Arithmetic shift right by number in register
ASR ,
Branch conditional
B
Branch unconditional
B
Bit clear
BIC ,
Software breakpoint
BKPT
Branch with link
BL
Branch with link and exchange
BLX
Branch and exchange
BX
Compare not zero and branch
CBNZ ,
Compare zero and branch
CBZ ,
Compare negation of register value with another register value
CMN ,
Compare immediate 8-bit value
CMP , #
Compare registers
CMP ,
Compare high register to low or high register
CMP ,
Change processor state
CPS ,
Copy high or low register value to another high or low register
CPY
Bitwise exclusive OR register values
EOR ,
Condition the following instruction
IT
Condition the following two instructions
IT
Condition the following three instructions
IT
Condition the following four instructions
IT
Multiple sequential memory word loads
LDMIA !,
Load memory word from base register address + 5-bit immediate offset
LDR , [, # * 4]
Load memory word from base register address + register offset
LDR , [, ]
Load memory word from PC address + 8-bit immediate offset
LDR , [PC, # * 4]
Load memory word from SP address + 8-bit immediate offset
LDR, , [SP, # * 4]
Load memory byte [7:0] from register address + 5-bit immediate offset
LDRB , [, #]
Load memory byte [7:0] from register address + register offset
LDRB , [, ]
Load memory halfword [15:0] from register address + 5-bit immediate offset
LDRH , [, # * 2]
Load halfword [15:0] from register address + register offset
LDRH , [, ]
Load signed byte [7:0] from register address + register offset
LDRSB , [, ]
Load signed halfword [15:0] from register address + register offset
LDRSH , [, ]
Logical shift left by immediate number
LSL , , #
Logical shift left by number in register
LSL ,
Logical shift right by immediate number
LSR , , #
Logical shift right by number in register
LSR ,
Move immediate 8-bit value to register
MOV , #
Move low register value to low register
MOV ,
Move high or low register value to high or low register
MOV ,
Multiply register values
MUL ,
Move complement of register value to register
MVN ,
Negate register value and store in register
NEG ,
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Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
No operation
NOP
Bitwise logical OR register values
ORR ,
Pop registers from stack
POP
Pop registers and PC from stack
POP
Push registers onto stack
PUSH
Push LR and registers onto stack
PUSH
Reverse bytes in word and copy to register
REV ,
Reverse bytes in two halfwords and copy to register
REV16 ,
Reverse bytes in low halfword [15:0], sign-extend, and copy to register
REVSH ,
Rotate right by amount in register
ROR ,
Subtract register value and C flag from register value
SBC ,
Send event
SEV
Store multiple register words to sequential memory locations
STMIA !,
Store register word to register address + 5-bit immediate offset
STR , [, # * 4]
Store register word to register address
STR , [, ]
Store register word to SP address + 8-bit immediate offset
STR , [SP, # * 4]
Store register byte [7:0] to register address + 5-bit immediate offset
STRB , [, #]
Store register byte [7:0] to register address
STRB , [, ]
Store register halfword [15:0] to register address + 5-bit immediate offset
STRH , [, # * 2]
Store register halfword [15:0] to register address + register offset
STRH , [, ]
Subtract immediate 3-bit value from register
SUB , , #
Subtract immediate 8-bit value from register value
SUB , #
Subtract register values
SUB , ,
Subtract 4 (immediate 7-bit value) from SP
SUB SP, # * 4
Operating system service call with 8-bit immediate call code
SVC
Extract byte [7:0] from register, move to register, and sign-extend to 32 bits
SXTB ,
Extract halfword [15:0] from register, move to register, and sign-extend to 32 bits SXTH ,
Test register value for set bits by ANDing it with another register value
TST ,
Extract byte [7:0] from register, move to register, and zero-extend to 32 bits
UXTB , 10
Extract halfword [15:0] from register, move to register, and zero-extend to 32
bits
UXTH ,
Wait for event
WFE
Wait for interrupt
WFI
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary
Operation
Assembler
Add register value, immediate 12-bit value, and C bit
ADC{S}.W , , #
Add register value, shifted register value, and C bit
ADC{S}.W , , {, }
Add register value and immediate 12-bit value
ADD{S}.W , , #
Add register value and shifted register value
ADD{S}.W , {, }
Add register value and immediate 12-bit value
ADDW.W , , #
Bitwise AND register value with immediate 12-bit value
AND{S}.W , , #
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Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Bitwise AND register value with shifted register value
AND{S}.W , , Rm>{, }
Arithmetic shift right by number in register
ASR{S}.W , ,
Conditional branch
B{cond}.W
Clear bit field
BFC.W , #, #
Insert bit field from one register value into another
BFI.W , , #, #
Bitwise AND register value with complement of immediate 12-bit value
BIC{S}.W , , #
Bitwise AND register value with complement of shifted register value
BIC{S}.W , , {, }
Branch with link
BL
Branch with link (immediate)
BL
Unconditional branch
B.W
Clear exclusive clears the local record of the executing processor that an
address has had a request for an exclusive access.
CLREX
Return number of leading zeros in register value
CLZ.W ,
Compare register value with two’s complement of immediate 12-bit value
CMN.W , #
Compare register value with two’s complement of shifted register value
CMN.W , {, }
Compare register value with immediate 12-bit value
CMP.W , #
Compare register value with shifted register value
CMP.W , {, }
Data memory barrier
DMB
Data synchronization barrier
DSB
Exclusive OR register value with immediate 12-bit value
EOR{S}.W , , #
Exclusive OR register value with shifted register value
EOR{S}.W , , {, }
Instruction synchronization barrier
ISB
Load multiple memory registers, increment after or decrement before
LDM{IA|DB}.W {!},
Memory word from base register address + immediate 12-bit offset
LDR.W , [, #]
Memory word to PC from register address + immediate 12-bit offset
LDR.W PC, [, #]
Memory word to PC from base register address immediate 8-bit offset,
postindexed
LDR.W PC, [Rn], # 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF)
■ If ∆V < 0, then the conversion result < 0x1FF (range is 0–0x1FF)
The differential pairs assign polarities to the analog inputs: the even-numbered input is always
positive, and the odd-numbered input is always negative. In order for a valid conversion result to
appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input
is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped,
meaning it appears as either 3 V or 0 V, respectively, to the ADC.
Figure 13-8 on page 511 shows an example of the negative input centered at 1.5 V. In this
configuration, the differential range spans from -1.5 V to 1.5 V. Figure 13-9 on page 512 shows an
example where the negative input is centered at -0.75 V, meaning inputs on the positive input
saturate past a differential voltage of -0.75 V since the input voltage is less than 0 V. Figure
13-10 on page 512 shows an example of the negative input centered at 2.25 V, where inputs on the
positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater
than 3 V.
Figure 13-8. Differential Sampling Range, VIN_ODD = 1.5 V
0x3FF
0x1FF
0V
-1.5 V
1.5 V
0V
3.0 V VIN_EVEN
1.5 V DV
VIN_ODD = 1.5 V
- Input Saturation
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Figure 13-9. Differential Sampling Range, VIN_ODD = 0.75 V
ADC Conversion Result
0x3FF
0x1FF
0x0FF
-1.5 V
0V
-0.75 V
+0.75 V
+2.25 V
+1.5 V
VIN_EVEN
DV
- Input Saturation
Figure 13-10. Differential Sampling Range, VIN_ODD = 2.25 V
0x3FF
0x2FF
0x1FF
0.75 V
-1.5 V
2.25 V
3.0 V
0.75 V
1.5 V
VIN_EVEN
DV
- Input Saturation
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13.3.6
Internal Temperature Sensor
The temperature sensor's primary purpose is to notify the system that the internal temperature is
too high or low for reliable operation.
The temperature sensor does not have a separate enable, because it also contains the bandgap
reference and must always be enabled. The reference is supplied to other analog modules; not just
the ADC.
The internal temperature sensor provides an analog temperature reading as well as a reference
voltage. The voltage at the output terminal SENSO is given by the following equation:
SENSO = 2.7 - ((T + 55) / 75)
This relation is shown in Figure 13-11 on page 513.
Figure 13-11. Internal Temperature Sensor Characteristic
Sensor = 2.7 V – (T+55)
75
Sensor
2.7 V
1.633 V
0.3 V
-55° C
25° C
125° C Temp
The temperature reading from the temperature sensor can also be given as a function of the ADC
value. The following formula calculates temperature (in ℃) based on the ADC reading:
Temperature = 147.5 - ((225 × ADC) / 1023)
13.3.7
Digital Comparator Unit
An ADC is commonly used to sample an external signal and to monitor its value to ensure that it
remains in a given range. To automate this monitoring procedure and reduce the amount of processor
overhead that is required, digital comparator are provided. Conversions from the ADC that are sent
to the digital comparators are compared against the user programmable limits in the ADC Digital
Comparator Range (ADCDCCMPn) registers. If the observed signal moves out of the acceptable
range, a processor interrupt can be generated and/or a trigger can be sent to the PWM module.
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The digital comparators four operational modes (Once, Always, Hysteresis Once, Hysteresis Always)
can be applied to three separate regions (low band, mid band, high band) as defined by the user.
13.3.7.1
Output Functions
ADC conversions can either be stored in the ADC Sample Sequence FIFOs or compared using the
digital comparator resources as defined by the SnDCOP bits in the ADC Sample Sequence n
Operation (ADCSSOPn) register. These selected ADC conversions are used by their respective
digital comparator to monitor the external signal. Each comparator has two possible output functions:
processor interrupts and triggers.
Each function has its own state machine to track the monitored signal. Even though the interrupt
and trigger functions can be enabled individually or both at the same time, the same conversion
data is used by each function to determine if the right conditions have been met to assert the
associated output.
Interrupts
The digital comparator interrupt function is enabled by setting the CIE bit in the ADC Digital
Comparator Control (ADCDCCTLn) register. This bit enables the interrupt function state machine
to start monitoring the incoming ADC conversions. When the appropriate set of conditions is met,
and the DCONSSx bit is set in the ADCIM register, an interrupt is sent to the interrupt controller.
Triggers
The digital comparator trigger function is enabled by setting the CTE bit in the ADCDCCTLn register.
This bit enables the trigger function state machine to start monitoring the incoming ADC conversions.
When the appropriate set of conditions is met, the corresponding digital comparator trigger to the
PWM module is asserted
13.3.7.2
Operational Modes
Four operational modes are provided to support a broad range of applications and multiple possible
signaling requirements: Always, Once, Hysteresis Always, and Hysteresis Once. The operational
mode is selected using the CIM or CTM field in the ADCDCCTLn register.
Always Mode
In the Always operational mode, the associated interrupt or trigger is asserted whenever the ADC
conversion value meets its comparison criteria. The result is a string of assertions on the interrupt
or trigger while the conversions are within the appropriate range.
Once Mode
In the Once operational mode, the associated interrupt or trigger is asserted whenever the ADC
conversion value meets its comparison criteria, and the previous ADC conversion value did not.
The result is a single assertion of the interrupt or trigger when the conversions are within the
appropriate range.
Hysteresis-Always Mode
The Hysteresis-Always operational mode can only be used in conjunction with the low-band or
high-band regions because the mid-band region must be crossed and the opposite region entered
to clear the hysteresis condition. In the Hysteresis-Always mode, the associated interrupt or trigger
is asserted in the following cases: 1) the ADC conversion value meets its comparison criteria or 2)
a previous ADC conversion value has met the comparison criteria, and the hysteresis condition has
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not been cleared by entering the opposite region. The result is a string of assertions on the interrupt
or trigger that continue until the opposite region is entered.
Hysteresis-Once Mode
The Hysteresis-Once operational mode can only be used in conjunction with the low-band or
high-band regions because the mid-band region must be crossed and the opposite region entered
to clear the hysteresis condition. In the Hysteresis-Once mode, the associated interrupt or trigger
is asserted only when the ADC conversion value meets its comparison criteria, the hysteresis
condition is clear, and the previous ADC conversion did not meet the comparison criteria. The result
is a single assertion on the interrupt or trigger.
13.3.7.3
Function Ranges
The two comparison values, COMP0 and COMP1, in the ADC Digital Comparator Range
(ADCDCCMPn) register effectively break the conversion area into three distinct regions. These
regions are referred to as the low-band (less than or equal to COMP0), mid-band (greater than COMP0
but less than or equal to COMP1), and high-band (greater than COMP1) regions. COMP0 and COMP1
may be programmed to the same value, effectively creating two regions, but COMP1 must always
be greater than or equal to the value of COMP0. A COMP1 value that is less than COMP0 generates
unpredictable results.
Low-Band Operation
To operate in the low-band region, either the CIC field or the CTC field in the ADCDCCTLn register
must be programmed to 0x0. This setting causes interrupts or triggers to be generated in the low-band
region as defined by the programmed operational mode. An example of the state of the
interrupt/trigger signal in the low-band region for each of the operational modes is shown in Figure
13-12 on page 516. Note that a "0" in a column following the operational mode name (Always, Once,
Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is de-asserted
and a "1" indicates that the signal is asserted.
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Figure 13-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0)
COMP1
COMP0
Always –
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
Once –
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
Hysteresis Always –
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
Hysteresis Once –
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
Mid-Band Operation
To operate in the mid-band region, either the CIC field or the CTC field in the ADCDCCTLn register
must be programmed to 0x1. This setting causes interrupts or triggers to be generated in the mid-band
region according the operation mode. Only the Always and Once operational modes are available
in the mid-band region. An example of the state of the interrupt/trigger signal in the mid-band region
for each of the allowed operational modes is shown in Figure 13-13 on page 517. Note that a "0" in
a column following the operational mode name (Always or Once) indicates that the interrupt or
trigger signal is de-asserted and a "1" indicates that the signal is asserted.
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Figure 13-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1)
COMP1
COMP0
Always –
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
Once –
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
Hysteresis Always –
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Hysteresis Once –
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High-Band Operation
To operate in the high-band region, either the CIC field or the CTC field in the ADCDCCTLn register
must be programmed to 0x3. This setting causes interrupts or triggers to be generated in the
high-band region according the operation mode. An example of the state of the interrupt/trigger
signal in the high-band region for each of the allowed operational modes is shown in Figure
13-14 on page 518. Note that a "0" in a column following the operational mode name (Always, Once,
Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is de-asserted
and a "1" indicates that the signal is asserted.
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Figure 13-14. High-Band Operation (CIC=0x3 and/or CTC=0x3)
COMP1
COMP0
13.4
Always –
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
1
Once –
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
Hysteresis Always –
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
Hysteresis Once –
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and programmed to a supported
crystal frequency in the RCC register (see page 127). Using unsupported frequencies can cause
faulty operation in the ADC module.
13.4.1
Module Initialization
Initialization of the ADC module is a simple process with very few steps: enabling the clock to the
ADC, disabling the analog isolation circuit associated with all inputs that are to be used, and
reconfiguring the sample sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC0 register (see page 171).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register (see page 191). To
find out which GPIO port to enable, refer to Table 24-5 on page 1097.
3. Set the GPIO AFSEL bits for the ADC input pins (see page 323). To determine which GPIOs to
configure, see Table 24-4 on page 1088.
4. Configure the PMCn fields in the GPIOPCTL register to assign the AINx and VREFA signals to
the appropriate pins (see page 341 and Table 24-5 on page 1097).
5. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to
the appropriate bits of the GPIOAMSEL register (see page 339) in the associated GPIO block.
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6. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority and Sample
Sequencer 3 as the lowest priority.
13.4.2
Sample Sequencer Configuration
Configuration of the sample sequencers is slightly more complex than the module initialization
because each sample sequencer is completely programmable.
The configuration for each sample sequencer should be as follows:
1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the
ADCACTSS register. Programming of the sample sequencers is allowed without having them
enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger
event were to occur during the configuration process.
2. Configure the trigger event for the sample sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register.
6. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS
register.
13.5
Register Map
Table 13-5 on page 519 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that ADC module's base address of:
■ ADC0: 0x4003.8000
■ ADC1: 0x4003.9000
Note that the ADC module clock must be enabled before the registers can be programmed (see
page 171).
Table 13-5. ADC Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
ADCACTSS
R/W
0x0000.0000
ADC Active Sample Sequencer
522
0x004
ADCRIS
RO
0x0000.0000
ADC Raw Interrupt Status
523
0x008
ADCIM
R/W
0x0000.0000
ADC Interrupt Mask
525
0x00C
ADCISC
R/W1C
0x0000.0000
ADC Interrupt Status and Clear
527
0x010
ADCOSTAT
R/W1C
0x0000.0000
ADC Overflow Status
530
0x014
ADCEMUX
R/W
0x0000.0000
ADC Event Multiplexer Select
532
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Table 13-5. ADC Register Map (continued)
Offset
Name
0x018
See
page
Type
Reset
Description
ADCUSTAT
R/W1C
0x0000.0000
ADC Underflow Status
537
0x020
ADCSSPRI
R/W
0x0000.3210
ADC Sample Sequencer Priority
538
0x024
ADCSPC
R/W
0x0000.0000
ADC Sample Phase Control
540
0x028
ADCPSSI
R/W
-
ADC Processor Sample Sequence Initiate
541
0x030
ADCSAC
R/W
0x0000.0000
ADC Sample Averaging Control
543
0x034
ADCDCISC
R/W1C
0x0000.0000
ADC Digital Comparator Interrupt Status and Clear
544
0x038
ADCCTL
R/W
0x0000.0000
ADC Control
546
0x040
ADCSSMUX0
R/W
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 0
547
0x044
ADCSSCTL0
R/W
0x0000.0000
ADC Sample Sequence Control 0
549
0x048
ADCSSFIFO0
RO
-
ADC Sample Sequence Result FIFO 0
552
0x04C
ADCSSFSTAT0
RO
0x0000.0100
ADC Sample Sequence FIFO 0 Status
553
0x050
ADCSSOP0
R/W
0x0000.0000
ADC Sample Sequence 0 Operation
555
0x054
ADCSSDC0
R/W
0x0000.0000
ADC Sample Sequence 0 Digital Comparator Select
557
0x060
ADCSSMUX1
R/W
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 1
559
0x064
ADCSSCTL1
R/W
0x0000.0000
ADC Sample Sequence Control 1
560
0x068
ADCSSFIFO1
RO
-
ADC Sample Sequence Result FIFO 1
552
0x06C
ADCSSFSTAT1
RO
0x0000.0100
ADC Sample Sequence FIFO 1 Status
553
0x070
ADCSSOP1
R/W
0x0000.0000
ADC Sample Sequence 1 Operation
562
0x074
ADCSSDC1
R/W
0x0000.0000
ADC Sample Sequence 1 Digital Comparator Select
563
0x080
ADCSSMUX2
R/W
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 2
559
0x084
ADCSSCTL2
R/W
0x0000.0000
ADC Sample Sequence Control 2
560
0x088
ADCSSFIFO2
RO
-
ADC Sample Sequence Result FIFO 2
552
0x08C
ADCSSFSTAT2
RO
0x0000.0100
ADC Sample Sequence FIFO 2 Status
553
0x090
ADCSSOP2
R/W
0x0000.0000
ADC Sample Sequence 2 Operation
562
0x094
ADCSSDC2
R/W
0x0000.0000
ADC Sample Sequence 2 Digital Comparator Select
563
0x0A0
ADCSSMUX3
R/W
0x0000.0000
ADC Sample Sequence Input Multiplexer Select 3
565
0x0A4
ADCSSCTL3
R/W
0x0000.0002
ADC Sample Sequence Control 3
566
0x0A8
ADCSSFIFO3
RO
-
ADC Sample Sequence Result FIFO 3
552
0x0AC
ADCSSFSTAT3
RO
0x0000.0100
ADC Sample Sequence FIFO 3 Status
553
0x0B0
ADCSSOP3
R/W
0x0000.0000
ADC Sample Sequence 3 Operation
567
0x0B4
ADCSSDC3
R/W
0x0000.0000
ADC Sample Sequence 3 Digital Comparator Select
568
0xD00
ADCDCRIC
R/W
0x0000.0000
ADC Digital Comparator Reset Initial Conditions
569
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Table 13-5. ADC Register Map (continued)
Name
Type
Reset
0xE00
ADCDCCTL0
R/W
0x0000.0000
ADC Digital Comparator Control 0
574
0xE04
ADCDCCTL1
R/W
0x0000.0000
ADC Digital Comparator Control 1
574
0xE08
ADCDCCTL2
R/W
0x0000.0000
ADC Digital Comparator Control 2
574
0xE0C
ADCDCCTL3
R/W
0x0000.0000
ADC Digital Comparator Control 3
574
0xE10
ADCDCCTL4
R/W
0x0000.0000
ADC Digital Comparator Control 4
574
0xE14
ADCDCCTL5
R/W
0x0000.0000
ADC Digital Comparator Control 5
574
0xE18
ADCDCCTL6
R/W
0x0000.0000
ADC Digital Comparator Control 6
574
0xE1C
ADCDCCTL7
R/W
0x0000.0000
ADC Digital Comparator Control 7
574
0xE40
ADCDCCMP0
R/W
0x0000.0000
ADC Digital Comparator Range 0
578
0xE44
ADCDCCMP1
R/W
0x0000.0000
ADC Digital Comparator Range 1
578
0xE48
ADCDCCMP2
R/W
0x0000.0000
ADC Digital Comparator Range 2
578
0xE4C
ADCDCCMP3
R/W
0x0000.0000
ADC Digital Comparator Range 3
578
0xE50
ADCDCCMP4
R/W
0x0000.0000
ADC Digital Comparator Range 4
578
0xE54
ADCDCCMP5
R/W
0x0000.0000
ADC Digital Comparator Range 5
578
0xE58
ADCDCCMP6
R/W
0x0000.0000
ADC Digital Comparator Range 6
578
0xE5C
ADCDCCMP7
R/W
0x0000.0000
ADC Digital Comparator Range 7
578
13.6
Description
See
page
Offset
Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
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Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the sample sequencers. Each sample sequencer can be
enabled or disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
ASEN3
ASEN2
ASEN1
ASEN0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
ASEN3
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC SS3 Enable
Value Description
2
ASEN2
R/W
0
1
Sample Sequencer 3 is enabled.
0
Sample Sequencer 3 is disabled.
ADC SS2 Enable
Value Description
1
ASEN1
R/W
0
1
Sample Sequencer 2 is enabled.
0
Sample Sequencer 2 is disabled.
ADC SS1 Enable
Value Description
0
ASEN0
R/W
0
1
Sample Sequencer 1 is enabled.
0
Sample Sequencer 1 is disabled.
ADC SS0 Enable
Value Description
1
Sample Sequencer 0 is enabled.
0
Sample Sequencer 0 is disabled.
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Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each sample sequencer. These bits may
be polled by software to look for interrupt conditions without sending the interrupts to the interrupt
controller.
ADC Raw Interrupt Status (ADCRIS)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
1
0
INR3
INR2
INR1
INR0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INRDC
reserved
Type
Reset
16
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
INRDC
RO
0
Digital Comparator Raw Interrupt Status
Value Description
15:4
reserved
RO
0x000
3
INR3
RO
0
1
At least one bit in the ADCDCISC register is set, meaning that
a digital comparator interrupt has occurred.
0
All bits in the ADCDCISC register are clear.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 Raw Interrupt Status
Value Description
1
A sample has completed conversion and the respective
ADCSSCTL3 IEn bit is set, enabling a raw interrupt.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the IN3 bit in the ADCISC register.
2
INR2
RO
0
SS2 Raw Interrupt Status
Value Description
1
A sample has completed conversion and the respective
ADCSSCTL2 IEn bit is set, enabling a raw interrupt.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the IN2 bit in the ADCISC register.
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Bit/Field
Name
Type
Reset
1
INR1
RO
0
Description
SS1 Raw Interrupt Status
Value Description
1
A sample has completed conversion and the respective
ADCSSCTL1 IEn bit is set, enabling a raw interrupt.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the IN1 bit in the ADCISC register.
0
INR0
RO
0
SS0 Raw Interrupt Status
Value Description
1
A sample has completed conversion and the respective
ADCSSCTL0 IEn bit is set, enabling a raw interrupt.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the IN0 bit in the ADCISC register.
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Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the sample sequencer and digital comparator raw interrupt signals
are sent to the interrupt controller. Each raw interrupt signal can be masked independently. Only a
single DCONSSn bit should be set at any given time. Setting more than one of these bits results in
the INRDC bit from the ADCRIS register being masked, and no interrupt is generated on any of the
sample sequencer interrupt lines.
ADC Interrupt Mask (ADCIM)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
7
6
5
4
3
2
1
0
MASK3
MASK2
MASK1
MASK0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
18
17
16
DCONSS3 DCONSS2 DCONSS1 DCONSS0
reserved
Type
Reset
19
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
DCONSS3
R/W
0
Digital Comparator Interrupt on SS3
Value Description
18
DCONSS2
R/W
0
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS3 interrupt line.
0
The status of the digital comparators does not affect the SS3
interrupt status.
Digital Comparator Interrupt on SS2
Value Description
17
DCONSS1
R/W
0
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS2 interrupt line.
0
The status of the digital comparators does not affect the SS2
interrupt status.
Digital Comparator Interrupt on SS1
Value Description
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS1 interrupt line.
0
The status of the digital comparators does not affect the SS1
interrupt status.
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Bit/Field
Name
Type
Reset
16
DCONSS0
R/W
0
Description
Digital Comparator Interrupt on SS0
Value Description
15:4
reserved
RO
0x000
3
MASK3
R/W
0
1
The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS0 interrupt line.
0
The status of the digital comparators does not affect the SS0
interrupt status.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 Interrupt Mask
Value Description
2
MASK2
R/W
0
1
The raw interrupt signal from Sample Sequencer 3 (ADCRIS
register INR3 bit) is sent to the interrupt controller.
0
The status of Sample Sequencer 3 does not affect the SS3
interrupt status.
SS2 Interrupt Mask
Value Description
1
MASK1
R/W
0
1
The raw interrupt signal from Sample Sequencer 2 (ADCRIS
register INR2 bit) is sent to the interrupt controller.
0
The status of Sample Sequencer 2 does not affect the SS2
interrupt status.
SS1 Interrupt Mask
Value Description
0
MASK0
R/W
0
1
The raw interrupt signal from Sample Sequencer 1 (ADCRIS
register INR1 bit) is sent to the interrupt controller.
0
The status of Sample Sequencer 1 does not affect the SS1
interrupt status.
SS0 Interrupt Mask
Value Description
1
The raw interrupt signal from Sample Sequencer 0 (ADCRIS
register INR0 bit) is sent to the interrupt controller.
0
The status of Sample Sequencer 0 does not affect the SS0
interrupt status.
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Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing sample sequencer interrupt conditions and shows
the status of interrupts generated by the sample sequencers and the digital comparators which have
been sent to the interrupt controller. When read, each bit field is the logical AND of the respective
INR and MASK bits. Sample sequencer interrupts are cleared by writing a 1 to the corresponding
bit position. Digital comparator interrupts are cleared by writing a 1 to the appropriate bits in the
ADCDCISC register. If software is polling the ADCRIS instead of generating interrupts, the sample
sequence INRn bits are still cleared via the ADCISC register, even if the INn bit is not set.
ADC Interrupt Status and Clear (ADCISC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x00C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
1
0
IN3
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
Type
Reset
18
17
16
DCINSS3 DCINSS2 DCINSS1 DCINSS0
reserved
Type
Reset
19
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
DCINSS3
RO
0
Digital Comparator Interrupt Status on SS3
Value Description
1
Both the INRDC bit in the ADCRIS register and the DCONSS3
bit in the ADCIM register are set, providing a level-base interrupt
to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
18
DCINSS2
RO
0
Digital Comparator Interrupt Status on SS2
Value Description
1
Both the INRDC bit in the ADCRIS register and the DCONSS2
bit in the ADCIM register are set, providing a level-base interrupt
to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
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Bit/Field
Name
Type
Reset
17
DCINSS1
RO
0
Description
Digital Comparator Interrupt Status on SS1
Value Description
1
Both the INRDC bit in the ADCRIS register and the DCONSS1
bit in the ADCIM register are set, providing a level-base interrupt
to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
16
DCINSS0
RO
0
Digital Comparator Interrupt Status on SS0
Value Description
1
Both the INRDC bit in the ADCRIS register and the DCONSS0
bit in the ADCIM register are set, providing a level-base interrupt
to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1 to it. Clearing this bit also clears the
INRDC bit in the ADCRIS register.
15:4
reserved
RO
0x000
3
IN3
R/W1C
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 Interrupt Status and Clear
Value Description
1
Both the INR3 bit in the ADCRIS register and the MASK3 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the INR3
bit in the ADCRIS register.
2
IN2
R/W1C
0
SS2 Interrupt Status and Clear
Value Description
1
Both the INR2 bit in the ADCRIS register and the MASK2 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the INR2
bit in the ADCRIS register.
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Bit/Field
Name
Type
Reset
1
IN1
R/W1C
0
Description
SS1 Interrupt Status and Clear
Value Description
1
Both the INR1 bit in the ADCRIS register and the MASK1 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the INR1
bit in the ADCRIS register.
0
IN0
R/W1C
0
SS0 Interrupt Status and Clear
Value Description
1
Both the INR0 bit in the ADCRIS register and the MASK0 bit in
the ADCIM register are set, providing a level-based interrupt to
the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the INR0
bit in the ADCRIS register.
May 24, 2010
529
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x010
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OV3
OV2
OV1
OV0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
OV3
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 FIFO Overflow
Value Description
1
The FIFO for Sample Sequencer 3 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
0
The FIFO has not overflowed.
This bit is cleared by writing a 1.
2
OV2
R/W1C
0
SS2 FIFO Overflow
Value Description
1
The FIFO for Sample Sequencer 2 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
0
The FIFO has not overflowed.
This bit is cleared by writing a 1.
1
OV1
R/W1C
0
SS1 FIFO Overflow
Value Description
1
The FIFO for Sample Sequencer 1 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
0
The FIFO has not overflowed.
This bit is cleared by writing a 1.
530
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
0
OV0
R/W1C
0
Description
SS0 FIFO Overflow
Value Description
1
The FIFO for Sample Sequencer 0 has hit an overflow condition,
meaning that the FIFO is full and a write was requested. When
an overflow is detected, the most recent write is dropped.
0
The FIFO has not overflowed.
This bit is cleared by writing a 1.
May 24, 2010
531
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each
sample sequencer can be configured with a unique trigger source.
ADC Event Multiplexer Select (ADCEMUX)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
EM3
Type
Reset
EM2
EM1
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
EM0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
532
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
15:12
EM3
R/W
0x0
Description
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
0x1
Analog Comparator 0
0x2
Analog Comparator 1
0x3
Analog Comparator 2
0x4
External (GPIO PB4)
Note:
0x5
PB4 can be used to trigger the ADC. However, the
PB4/AIN10 pin cannot be used as both a GPIO
and an analog input.
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (see page 450).
0x6
PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 1007.
0x7
PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 1007.
0x8
PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 1007.
0x9
PWM3
The PWM module 3 trigger can be configured with the
PWM3INTEN register, see page 1007.
0xA-0xE reserved
0xF
Always (continuously sample)
May 24, 2010
533
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
11:8
EM2
R/W
0x0
Description
SS2 Trigger Select
This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
0x1
Analog Comparator 0
0x2
Analog Comparator 1
0x3
Analog Comparator 2
0x4
External (GPIO PB4)
Note:
0x5
PB4 can be used to trigger the ADC. However, the
PB4/AIN10 pin cannot be used as both a GPIO
and an analog input.
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (see page 450).
0x6
PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 1007.
0x7
PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 1007.
0x8
PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 1007.
0x9
PWM3
The PWM module 3 trigger can be configured with the
PWM3INTEN register, see page 1007.
0xA-0xE reserved
0xF
Always (continuously sample)
534
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
7:4
EM1
R/W
0x0
Description
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
0x1
Analog Comparator 0
0x2
Analog Comparator 1
0x3
Analog Comparator 2
0x4
External (GPIO PB4)
Note:
0x5
PB4 can be used to trigger the ADC. However, the
PB4/AIN10 pin cannot be used as both a GPIO
and an analog input.
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (see page 450).
0x6
PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 1007.
0x7
PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 1007.
0x8
PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 1007.
0x9
PWM3
The PWM module 3 trigger can be configured with the
PWM3INTEN register, see page 1007.
0xA-0xE reserved
0xF
Always (continuously sample)
May 24, 2010
535
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
3:0
EM0
R/W
0x0
Description
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0
The valid configurations for this field are:
Value
Event
0x0
Processor (default)
0x1
Analog Comparator 0
0x2
Analog Comparator 1
0x3
Analog Comparator 2
0x4
External (GPIO PB4)
Note:
0x5
PB4 can be used to trigger the ADC. However, the
PB4/AIN10 pin cannot be used as both a GPIO
and an analog input.
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (see page 450).
0x6
PWM0
The PWM module 0 trigger can be configured with the PWM0
Interrupt and Trigger Enable (PWM0INTEN) register, see
page 1007.
0x7
PWM1
The PWM module 1 trigger can be configured with the
PWM1INTEN register, see page 1007.
0x8
PWM2
The PWM module 2 trigger can be configured with the
PWM2INTEN register, see page 1007.
0x9
PWM3
The PWM module 3 trigger can be configured with the
PWM3INTEN register, see page 1007.
0xA-0xE reserved
0xF
Always (continuously sample)
536
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding
underflow condition is cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x018
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
UV3
UV2
UV1
UV0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
UV3
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 FIFO Underflow
The valid configurations for this field are shown below. This bit is cleared
by writing a 1.
Value Description
2
UV2
R/W1C
0
1
The FIFO for the Sample Sequencer has hit an underflow
condition, meaning that the FIFO is empty and a read was
requested. The problematic read does not move the FIFO
pointers, and 0s are returned.
0
The FIFO has not underflowed.
SS2 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
1
UV1
R/W1C
0
SS1 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
0
UV0
R/W1C
0
SS0 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
May 24, 2010
537
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the
highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities,
each sequence must have a unique priority for the ADC to operate properly.
ADC Sample Sequencer Priority (ADCSSPRI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x020
Type R/W, reset 0x0000.3210
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
1
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
RO
0
RO
0
R/W
0
R/W
1
RO
0
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
SS3
R/W
1
reserved
RO
0
SS2
R/W
1
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0x0000.0
13:12
SS3
R/W
0x3
reserved
SS1
reserved
SS0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
11:10
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:8
SS2
R/W
0x2
SS2 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
7:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
SS1
R/W
0x1
SS1 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
3:2
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
538
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
Description
1:0
SS0
R/W
0x0
SS0 Priority
This field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0. A priority encoding of 0x0 is highest
and 0x3 is lowest. The priorities assigned to the sequencers must be
uniquely mapped. The ADC may not operate properly if two or more
fields are equal.
May 24, 2010
539
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024
This register allows the ADC module to sample at one of 16 different discrete phases from 0.0°
through 337.5°. For example, the sample rate could be effectively doubled by sampling a signal
using one ADC module configured with the standard sample time and the second ADC module
configured with a 180.0° phase lag.
Note:
Care should be taken when the PHASE field is non-zero, as the resulting delay in sampling
the AINx input may result in undesirable system consequences. Designers should carefully
consider the impact of this delay.
ADC Sample Phase Control (ADCSPC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
PHASE
R/W
0x0
PHASE
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Difference
This field selects the sample phase difference from the standard sample
time.
Value Description
0x0
ADC sample lags by 0.0°
0x1
ADC sample lags by 22.5°
0x2
ADC sample lags by 45.0°
0x3
ADC sample lags by 67.5°
0x4
ADC sample lags by 90.0°
0x5
ADC sample lags by 112.5°
0x6
ADC sample lags by 135.0°
0x7
ADC sample lags by 157.5°
0x8
ADC sample lags by 180.0°
0x9
ADC sample lags by 202.5°
0xA
ADC sample lags by 225.0°
0xB
ADC sample lags by 247.5°
0xC
ADC sample lags by 270.0°
0xD
ADC sample lags by 292.5°
0xE
ADC sample lags by 315.0°
0xF
ADC sample lags by 337.5°
540
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the sample
sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
This register also provides a means to configure and then initiate concurrent sampling on all ADC
modules. To do this, the first ADC module should be configured. The ADCPSSI register for that
module should then be written. The appropriate SS bits should be set along with the SYNCWAIT bit.
Additional ADC modules should then be configured following the same procedure. Once the final
ADC module is configured, its ADCPSSI register should be written with the appropriate SS bits set
along with the GSYNC bit. All of the ADC modules then begin concurrent sampling according to their
configuration.
ADC Processor Sample Sequence Initiate (ADCPSSI)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x028
Type R/W, reset 31
30
GSYNC
Type
Reset
29
28
reserved
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
SYNCWAIT
R/W
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31
GSYNC
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
SS3
SS2
SS1
SS0
WO
-
WO
-
WO
-
WO
-
Description
Global Synchronize
Value Description
30:28
reserved
RO
0x0
27
SYNCWAIT
R/W
0
1
This bit initiates sampling in multiple ADC modules at the same
time. Any ADC module that has been initialized by setting an
SSn bit and the SYNCWAIT bit starts sampling once this bit is
written.
0
This bit is cleared once sampling has been initiated.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Synchronize Wait
Value Description
26:4
reserved
RO
0x0000.0
1
This bit allows the sample sequences to be initiated, but delays
sampling until the GSYNC bit is set.
0
Sampling begins when a sample sequence has been initiated.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
541
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
Description
3
SS3
WO
-
SS3 Initiate
Value Description
1
Begin sampling on Sample Sequencer 3, if the sequencer is
enabled in the ADCACTSS register.
0
No effect.
Only a write by software is valid; a read of this register returns no
meaningful data.
2
SS2
WO
-
SS2 Initiate
Value Description
1
Begin sampling on Sample Sequencer 2, if the sequencer is
enabled in the ADCACTSS register.
0
No effect.
Only a write by software is valid; a read of this register returns no
meaningful data.
1
SS1
WO
-
SS1 Initiate
Value Description
1
Begin sampling on Sample Sequencer 1, if the sequencer is
enabled in the ADCACTSS register.
0
No effect.
Only a write by software is valid; a read of this register returns no
meaningful data.
0
SS0
WO
-
SS0 Initiate
Value Description
1
Begin sampling on Sample Sequencer 0, if the sequencer is
enabled in the ADCACTSS register.
0
No effect.
Only a write by software is valid; a read of this register returns no
meaningful data.
542
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG = 7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x030
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2:0
AVG
R/W
0x0
AVG
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
Value Description
0x0
No hardware oversampling
0x1
2x hardware oversampling
0x2
4x hardware oversampling
0x3
8x hardware oversampling
0x4
16x hardware oversampling
0x5
32x hardware oversampling
0x6
64x hardware oversampling
0x7
reserved
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Analog-to-Digital Converter (ADC)
Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC),
offset 0x034
This register provides status and acknowledgement of digital comparator interrupts. One bit is
provided for each comparator.
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x034
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
DCINT7
R/W1C
0
RO
0
RO
0
7
6
5
4
3
2
1
0
DCINT7
DCINT6
DCINT5
DCINT4
DCINT3
DCINT2
DCINT1
DCINT0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator 7 Interrupt Status and Clear
Value Description
1
Digital Comparator 7 has generated an interrupt.
0
No interrupt.
This bit is cleared by writing a 1.
6
DCINT6
R/W1C
0
Digital Comparator 6 Interrupt Status and Clear
Value Description
1
Digital Comparator 6 has generated an interrupt.
0
No interrupt.
This bit is cleared by writing a 1.
5
DCINT5
R/W1C
0
Digital Comparator 5 Interrupt Status and Clear
Value Description
1
Digital Comparator 5 has generated an interrupt.
0
No interrupt.
This bit is cleared by writing a 1.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4
DCINT4
R/W1C
0
Description
Digital Comparator 4 Interrupt Status and Clear
Value Description
1
Digital Comparator 4 has generated an interrupt.
0
No interrupt.
This bit is cleared by writing a 1.
3
DCINT3
R/W1C
0
Digital Comparator 3 Interrupt Status and Clear
Value Description
1
Digital Comparator 3 has generated an interrupt.
0
No interrupt.
This bit is cleared by writing a 1.
2
DCINT2
R/W1C
0
Digital Comparator 2 Interrupt Status and Clear
Value Description
1
Digital Comparator 2 has generated an interrupt.
0
No interrupt.
This bit is cleared by writing a 1.
1
DCINT1
R/W1C
0
Digital Comparator 1 Interrupt Status and Clear
Value Description
1
Digital Comparator 1 has generated an interrupt.
0
No interrupt.
This bit is cleared by writing a 1.
0
DCINT0
R/W1C
0
Digital Comparator 0 Interrupt Status and Clear
Value Description
1
Digital Comparator 0 has generated an interrupt.
0
No interrupt.
This bit is cleared by writing a 1.
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Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 13: ADC Control (ADCCTL), offset 0x038
This register selects the voltage reference.
ADC Control (ADCCTL)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
VREF
R/W
0
RO
0
VREF
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Voltage Reference Select
Value Description
1
The external VREFA input is the voltage reference.
0
The internal reference as the voltage reference.
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 14: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 0. This register is 32 bits wide and contains information for eight possible
samples.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x040
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
MUX7
Type
Reset
R/W
0
R/W
0
15
14
R/W
0
R/W
0
R/W
0
R/W
0
13
12
11
10
MUX3
Type
Reset
R/W
0
R/W
0
25
24
23
22
MUX6
R/W
0
R/W
0
R/W
0
R/W
0
9
8
7
6
MUX2
R/W
0
R/W
0
R/W
0
R/W
0
21
20
19
18
MUX5
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
MUX1
R/W
0
Bit/Field
Name
Type
Reset
31:28
MUX7
R/W
0x0
R/W
0
R/W
0
R/W
0
17
16
R/W
0
R/W
0
1
0
R/W
0
R/W
0
MUX4
MUX0
R/W
0
R/W
0
R/W
0
R/W
0
Description
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 0x1 indicates the input
is AIN1.
27:24
MUX6
R/W
0x0
7th Sample Input Select
The MUX6 field is used during the seventh sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
23:20
MUX5
R/W
0x0
6th Sample Input Select
The MUX5 field is used during the sixth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
19:16
MUX4
R/W
0x0
5th Sample Input Select
The MUX4 field is used during the fifth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
15:12
MUX3
R/W
0x0
4th Sample Input Select
The MUX3 field is used during the fourth sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
11:8
MUX2
R/W
0x0
3rd Sample Input Select
The MUX2 field is used during the third sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
7:4
MUX1
R/W
0x0
Description
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the sample sequencer. It specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
3:0
MUX0
R/W
0x0
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
with the sample sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 15: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
a sample sequencer. When configuring a sample sequence, the END bit must be set for the final
sample, whether it be after the first sample, eighth sample, or any sample in between. This register
is 32 bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x044
Type R/W, reset 0x0000.0000
31
Type
Reset
Type
Reset
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TS7
IE7
END7
D7
TS6
IE6
END6
D6
TS5
IE5
END5
D5
TS4
IE4
END4
D4
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TS3
IE3
END3
D3
TS2
IE2
END2
D2
TS1
IE1
END1
D1
TS0
IE0
END0
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31
TS7
R/W
0
Description
8th Sample Temp Sensor Select
Value Description
30
IE7
R/W
0
1
The temperature sensor is read during the eighth sample of the
sample sequence.
0
The input pin specified by the ADCSSMUXn register is read
during the eighth sample of the sample sequence.
8th Sample Interrupt Enable
Value Description
1
The raw interrupt signal (INR0 bit) is asserted at the end of the
eighth sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
0
The raw interrupt is not asserted to the interrupt controller.
It is legal to have multiple samples within a sequence generate interrupts.
29
END7
R/W
0
8th Sample is End of Sequence
Value Description
1
The eighth sample is the last sample of the sequence.
0
Another sample is the sequence is the final sample.
It is possible to end the sequence on any sample position. Software
must set an ENDn bit somewhere within the sequence. Samples defined
after the sample containing a set ENDn bit are not requested for
conversion even though the fields may be non-zero.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
28
D7
R/W
0
Description
8th Sample Diff Input Select
Value Description
1
The analog input is differentially sampled. The corresponding
ADCSSMUXn nibble must be set to the pair number "i", where
the paired inputs are "2i and 2i+1".
0
The analog inputs are not differentially sampled.
Because the temperature sensor does not have a differential option,
this bit must not be set when the TS7 bit is set.
27
TS6
R/W
0
7th Sample Temp Sensor Select
Same definition as TS7 but used during the seventh sample.
26
IE6
R/W
0
7th Sample Interrupt Enable
Same definition as IE7 but used during the seventh sample.
25
END6
R/W
0
7th Sample is End of Sequence
Same definition as END7 but used during the seventh sample.
24
D6
R/W
0
7th Sample Diff Input Select
Same definition as D7 but used during the seventh sample.
23
TS5
R/W
0
6th Sample Temp Sensor Select
Same definition as TS7 but used during the sixth sample.
22
IE5
R/W
0
6th Sample Interrupt Enable
Same definition as IE7 but used during the sixth sample.
21
END5
R/W
0
6th Sample is End of Sequence
Same definition as END7 but used during the sixth sample.
20
D5
R/W
0
6th Sample Diff Input Select
Same definition as D7 but used during the sixth sample.
19
TS4
R/W
0
5th Sample Temp Sensor Select
Same definition as TS7 but used during the fifth sample.
18
IE4
R/W
0
5th Sample Interrupt Enable
Same definition as IE7 but used during the fifth sample.
17
END4
R/W
0
5th Sample is End of Sequence
Same definition as END7 but used during the fifth sample.
16
D4
R/W
0
5th Sample Diff Input Select
Same definition as D7 but used during the fifth sample.
15
TS3
R/W
0
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
14
IE3
R/W
0
Description
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
13
END3
R/W
0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
12
D3
R/W
0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
11
TS2
R/W
0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
10
IE2
R/W
0
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
9
END2
R/W
0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
8
D2
R/W
0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
7
TS1
R/W
0
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
6
IE1
R/W
0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
5
END1
R/W
0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
4
D1
R/W
0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
3
TS0
R/W
0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
2
IE0
R/W
0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
1
END0
R/W
0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
0
D0
R/W
0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
May 24, 2010
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Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 16: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 18: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 19: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
Important: Use caution when reading this register. Performing a read may change bit status.
This register contains the conversion results for samples collected with the sample sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x048
Type RO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DATA
RO
0
RO
0
RO
-
Bit/Field
Name
Type
Reset
31:10
reserved
RO
0x0000.00
9:0
DATA
RO
-
RO
-
RO
-
RO
-
RO
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Conversion Result Data
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 23: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the sample sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO. The ADCSSFSTAT0 register provides status on FIFO0, which has 8 entries; ADCSSFSTAT1
on FIFO1, which has 4 entries; ADCSSFSTAT2 on FIFO2, which has 4 entries; and ADCSSFSTAT3
on FIFO3 which has a single entry.
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x04C
Type RO, reset 0x0000.0100
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
FULL
RO
0
RO
0
reserved
RO
0
RO
0
EMPTY
RO
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
12
FULL
RO
0
RO
1
HPTR
TPTR
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Full
Value Description
11:9
reserved
RO
0x0
8
EMPTY
RO
1
1
The FIFO is currently full.
0
The FIFO is not currently full.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Empty
Value Description
1
The FIFO is currently empty.
0
The FIFO is not currently empty.
May 24, 2010
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
7:4
HPTR
RO
0x0
Description
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
3:0
TPTR
RO
0x0
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 24: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050
This register determines whether the sample from the given conversion on Sample Sequence 0 is
saved in the Sample Sequence FIFO0 or sent to the digital comparator unit.
ADC Sample Sequence 0 Operation (ADCSSOP0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x050
Type R/W, reset 0x0000.0000
31
30
29
reserved
Type
Reset
27
S7DCOP
26
25
reserved
24
23
S6DCOP
22
21
reserved
20
19
S5DCOP
18
17
reserved
16
S4DCOP
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
28
RO
0
RO
0
S3DCOP
RO
0
R/W
0
reserved
RO
0
RO
0
S2DCOP
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0x0
28
S7DCOP
R/W
0
R/W
0
reserved
RO
0
RO
0
S1DCOP
RO
0
R/W
0
reserved
RO
0
RO
0
S0DCOP
RO
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 7 Digital Comparator Operation
Value Description
27:25
reserved
RO
0x0
24
S6DCOP
R/W
0
1
The eighth sample is sent to the digital comparator unit specified
by the S7DCSEL bit in the ADCSSDC0 register, and the value
is not written to the FIFO.
0
The eighth sample is saved in Sample Sequence FIFO0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 6 Digital Comparator Operation
Same definition as S7DCOP but used during the seventh sample.
23:21
reserved
RO
0x0
20
S5DCOP
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 5 Digital Comparator Operation
Same definition as S7DCOP but used during the sixth sample.
19:17
reserved
RO
0x0
16
S4DCOP
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 4 Digital Comparator Operation
Same definition as S7DCOP but used during the fifth sample.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
15:13
reserved
RO
0x0
12
S3DCOP
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 3 Digital Comparator Operation
Same definition as S7DCOP but used during the fourth sample.
11:9
reserved
RO
0x0
8
S2DCOP
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 2 Digital Comparator Operation
Same definition as S7DCOP but used during the third sample.
7:5
reserved
RO
0x0
4
S1DCOP
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 1 Digital Comparator Operation
Same definition as S7DCOP but used during the second sample.
3:1
reserved
RO
0x0
0
S0DCOP
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Operation
Same definition as S7DCOP but used during the first sample.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 25: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0),
offset 0x054
This register determines which digital comparator receives the sample from the given conversion
on Sample Sequence 0, if the corresponding SnDCOP bit in the ADCSSOP0 register is set.
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x054
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
S7DCSEL
Type
Reset
24
23
22
21
20
19
S5DCSEL
18
17
16
S4DCSEL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S3DCSEL
Type
Reset
25
S6DCSEL
R/W
0
R/W
0
S2DCSEL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:28
S7DCSEL
R/W
0x0
S1DCSEL
R/W
0
R/W
0
R/W
0
R/W
0
S0DCSEL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Sample 7 Digital Comparator Select
When the S7DCOP bit in the ADCSSOP0 register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the eighth sample from Sample Sequencer 0.
Note:
Values not listed are reserved.
Value Description
27:24
S6DCSEL
R/W
0x0
0x0
Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0)
0x1
Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1)
0x2
Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2)
0x3
Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3)
0x4
Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4)
0x5
Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5)
0x6
Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6)
0x7
Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7)
Sample 6 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
seventh sample.
23:20
S5DCSEL
R/W
0x0
Sample 5 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
sixth sample.
19:16
S4DCSEL
R/W
0x0
Sample 4 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
fifth sample.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
15:12
S3DCSEL
R/W
0x0
Description
Sample 3 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
fourth sample.
11:8
S2DCSEL
R/W
0x0
Sample 2 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
third sample.
7:4
S1DCSEL
R/W
0x0
Sample 1 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
second sample.
3:0
S0DCSEL
R/W
0x0
Sample 0 Digital Comparator Select
This field has the same encodings as S7DCSEL but is used during the
first sample.
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Stellaris® LM3S5B91 Microcontroller
Register 26: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 27: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16 bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 547 for detailed bit descriptions. The ADCSSMUX1
register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2.
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x060
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
MUX3
Type
Reset
MUX2
MUX1
MUX0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
15:12
MUX3
R/W
0x0
4th Sample Input Select
11:8
MUX2
R/W
0x0
3rd Sample Input Select
7:4
MUX1
R/W
0x0
2nd Sample Input Select
3:0
MUX0
R/W
0x0
1st Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Analog-to-Digital Converter (ADC)
Register 28: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 29: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set for the
final sample, whether it be after the first sample, fourth sample, or any sample in between. These
registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0
register on page 549 for detailed bit descriptions. The ADCSSCTL1 register configures Sample
Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2.
ADC Sample Sequence Control 1 (ADCSSCTL1)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x064
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
TS3
IE3
END3
D3
TS2
IE2
END2
D2
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TS1
IE1
END1
D1
TS0
IE0
END0
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
Type
Reset
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
TS3
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4th Sample Temp Sensor Select
Same definition as TS7 but used during the fourth sample.
14
IE3
R/W
0
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
13
END3
R/W
0
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
12
D3
R/W
0
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
11
TS2
R/W
0
3rd Sample Temp Sensor Select
Same definition as TS7 but used during the third sample.
10
IE2
R/W
0
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
9
END2
R/W
0
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
8
D2
R/W
0
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
7
TS1
R/W
0
Description
2nd Sample Temp Sensor Select
Same definition as TS7 but used during the second sample.
6
IE1
R/W
0
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
5
END1
R/W
0
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
4
D1
R/W
0
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
3
TS0
R/W
0
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
2
IE0
R/W
0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
1
END0
R/W
0
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
0
D0
R/W
0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
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Analog-to-Digital Converter (ADC)
Register 30: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070
Register 31: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090
This register determines whether the sample from the given conversion on Sample Sequence n is
saved in the Sample Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1
register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2.
ADC Sample Sequence 1 Operation (ADCSSOP1)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x070
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
S3DCOP
RO
0
R/W
0
reserved
RO
0
RO
0
S2DCOP
RO
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
12
S3DCOP
R/W
0
R/W
0
reserved
RO
0
RO
0
S1DCOP
RO
0
R/W
0
reserved
RO
0
RO
0
S0DCOP
RO
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 3 Digital Comparator Operation
Value Description
11:9
reserved
RO
0x0
8
S2DCOP
R/W
0
1
The fourth sample is sent to the digital comparator unit specified
by the S3DCSEL bit in the ADCSSDC0n register, and the value
is not written to the FIFO.
0
The fourth sample is saved in Sample Sequence FIFOn.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 2 Digital Comparator Operation
Same definition as S3DCOP but used during the third sample.
7:5
reserved
RO
0x0
4
S1DCOP
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 1 Digital Comparator Operation
Same definition as S3DCOP but used during the second sample.
3:1
reserved
RO
0x0
0
S0DCOP
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Operation
Same definition as S3DCOP but used during the first sample.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 32: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1),
offset 0x074
Register 33: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2),
offset 0x094
These registers determine which digital comparator receives the sample from the given conversion
on Sample Sequence n if the corresponding SnDCOP bit in the ADCSSOPn register is set. The
ADCSSDC1 register controls the selection for Sample Sequencer 1 and the ADCSSDC2 register
controls the selection for Sample Sequencer 2.
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x074
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
S3DCSEL
Type
Reset
S2DCSEL
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:12
S3DCSEL
R/W
0x0
S1DCSEL
R/W
0
S0DCSEL
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 3 Digital Comparator Select
When the S3DCOP bit in the ADCSSOPn register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the eighth sample from Sample Sequencer n.
Note:
Values not listed are reserved.
Value Description
11:8
S2DCSEL
R/W
0x0
0x0
Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0)
0x1
Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1)
0x2
Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2)
0x3
Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3)
0x4
Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4)
0x5
Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5)
0x6
Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6)
0x7
Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7)
Sample 2 Digital Comparator Select
This field has the same encodings as S3DCSEL but is used during the
third sample.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
7:4
S1DCSEL
R/W
0x0
Description
Sample 1 Digital Comparator Select
This field has the same encodings as S3DCSEL but is used during the
second sample.
3:0
S0DCSEL
R/W
0x0
Sample 0 Digital Comparator Select
This field has the same encodings as S3DCSEL but is used during the
first sample.
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Stellaris® LM3S5B91 Microcontroller
Register 34: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register defines the analog input configuration for the sample executed with Sample Sequencer
3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSMUX0
register on page 547 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A0
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
MUX0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
MUX0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample Input Select
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Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 35: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for a sample executed with Sample Sequencer
3. The END0 bit is always set as this sequencer can execute only one sample. This register is 4 bits
wide and contains information for one possible sample. See the ADCSSCTL0 register on page 549
for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A4
Type R/W, reset 0x0000.0002
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TS0
IE0
END0
D0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
1
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
TS0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
2
IE0
R/W
0
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
1
END0
R/W
1
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Because this sequencer has only one entry, this bit must be set.
0
D0
R/W
0
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
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Stellaris® LM3S5B91 Microcontroller
Register 36: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0
This register determines whether the sample from the given conversion on Sample Sequence 3 is
saved in the Sample Sequence 3 FIFO or sent to the digital comparator unit.
ADC Sample Sequence 3 Operation (ADCSSOP3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B0
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
S0DCOP
R/W
0
RO
0
S0DCOP
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Operation
Value Description
1
The sample is sent to the digital comparator unit specified by
the S0DCSEL bit in the ADCSSDC03 register, and the value is
not written to the FIFO.
0
The sample is saved in Sample Sequence FIFO3.
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Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 37: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3),
offset 0x0B4
This register determines which digital comparator receives the sample from the given conversion
on Sample Sequence 3 if the corresponding SnDCOP bit in the ADCSSOP3 register is set.
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0B4
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
S0DCSEL
R/W
0x0
S0DCSEL
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample 0 Digital Comparator Select
When the S0DCOP bit in the ADCSSOP3 register is set, this field
indicates which digital comparator unit (and its associated set of control
registers) receives the sample from Sample Sequencer 3.
Note:
Values not listed are reserved.
Value Description
0x0
Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0)
0x1
Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1)
0x2
Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2)
0x3
Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3)
0x4
Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4)
0x5
Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5)
0x6
Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6)
0x7
Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7)
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 38: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC),
offset 0xD00
This register provides the ability to reset any of the digital comparator interrupt or trigger functions
back to their initial conditions. Resetting these functions ensures that the data that is being used by
the interrupt and trigger functions in the digital comparator unit is not stale.
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xD00
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
DCTRIG7 DCTRIG6 DCTRIG5 DCTRIG4 DCTRIG3 DCTRIG2 DCTRIG1 DCTRIG0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
DCINT7
DCINT6
DCINT5
DCINT4
DCINT3
DCINT2
DCINT1
DCINT0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23
DCTRIG7
R/W
0
Digital Comparator Trigger 7
Value Description
1
Resets the Digital Comparator 7 trigger unit to its initial
conditions.
0
No effect.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
22
DCTRIG6
R/W
0
Digital Comparator Trigger 6
Value Description
1
Resets the Digital Comparator 6 trigger unit to its initial
conditions.
0
No effect.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
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Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
21
DCTRIG5
R/W
0
Description
Digital Comparator Trigger 5
Value Description
1
Resets the Digital Comparator 5 trigger unit to its initial
conditions.
0
No effect.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
20
DCTRIG4
R/W
0
Digital Comparator Trigger 4
Value Description
1
Resets the Digital Comparator 4 trigger unit to its initial
conditions.
0
No effect.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
19
DCTRIG3
R/W
0
Digital Comparator Trigger 3
Value Description
1
Resets the Digital Comparator 3 trigger unit to its initial
conditions.
0
No effect.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
18
DCTRIG2
R/W
0
Digital Comparator Trigger 2
Value Description
1
Resets the Digital Comparator 2 trigger unit to its initial
conditions.
0
No effect.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
17
DCTRIG1
R/W
0
Description
Digital Comparator Trigger 1
Value Description
1
Resets the Digital Comparator 1 trigger unit to its initial
conditions.
0
No effect.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
16
DCTRIG0
R/W
0
Digital Comparator Trigger 0
Value Description
1
Resets the Digital Comparator 0 trigger unit to its initial
conditions.
0
No effect.
When the trigger has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the trigger, it is important
to reset the digital comparator to initial conditions when starting a new
sequence so that stale data is not used.
15:8
reserved
RO
0x00
7
DCINT7
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator Interrupt 7
Value Description
1
Resets the Digital Comparator 7 interrupt unit to its initial
conditions.
0
No effect.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
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Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
6
DCINT6
R/W
0
Description
Digital Comparator Interrupt 6
Value Description
1
Resets the Digital Comparator 6 interrupt unit to its initial
conditions.
0
No effect.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
5
DCINT5
R/W
0
Digital Comparator Interrupt 5
Value Description
1
Resets the Digital Comparator 5 interrupt unit to its initial
conditions.
0
No effect.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
4
DCINT4
R/W
0
Digital Comparator Interrupt 4
Value Description
1
Resets the Digital Comparator 4 interrupt unit to its initial
conditions.
0
No effect.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
3
DCINT3
R/W
0
Digital Comparator Interrupt 3
Value Description
1
Resets the Digital Comparator 3 interrupt unit to its initial
conditions.
0
No effect.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
2
DCINT2
R/W
0
Description
Digital Comparator Interrupt 2
Value Description
1
Resets the Digital Comparator 2 interrupt unit to its initial
conditions.
0
No effect.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
1
DCINT1
R/W
0
Digital Comparator Interrupt 1
Value Description
1
Resets the Digital Comparator 1 interrupt unit to its initial
conditions.
0
No effect.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
0
DCINT0
R/W
0
Digital Comparator Interrupt 0
Value Description
1
Resets the Digital Comparator 0 interrupt unit to its initial
conditions.
0
No effect.
When the interrupt has been cleared, this bit is automatically cleared.
Because the digital comparators use the current and previous ADC
conversion values to determine when to assert the interrupt, it is
important to reset the digital comparator to initial conditions when starting
a new sequence so that stale data is not used.
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Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 39: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00
Register 40: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04
Register 41: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08
Register 42: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C
Register 43: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10
Register 44: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14
Register 45: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18
Register 46: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C
This register provides the comparison encodings that generate an interrupt or PWM trigger.
ADC Digital Comparator Control 0 (ADCDCCTL0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xE00
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
CTE
RO
0
R/W
0
CTC
R/W
0
CTM
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
12
CTE
R/W
0
reserved
RO
0
CIE
CIC
R/W
0
CIM
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparison Trigger Enable
Value Description
1
Enables the trigger function state machine. The ADC conversion
data is used to determine if a trigger should be generated
according to the programming of the CTC and CTM fields.
0
Disables the trigger function state machine. ADC conversion
data is ignored by the trigger function.
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
11:10
CTC
R/W
0x0
Description
Comparison Trigger Condition
This field specifies the operational region in which a trigger is generated
when the ADC conversion data is compared against the values of COMP0
and COMP1. The COMP0 and COMP1 fields are defined in the
ADCDCCMPx registers.
Value Description
0x0
Low Band
ADC Data < COMP0 and < COMP1
0x1
Mid Band
COMP0 ≤ ADC Data < COMP1
0x2
reserved
0x3
High Band
COMP0 ≤ COMP1 ≤ ADC Data
9:8
CTM
R/W
0x0
Comparison Trigger Mode
This field specifies the mode by which the trigger comparison is made.
Value Description
0x0
Always
This mode generates a trigger every time the ADC conversion
data falls within the selected operational region.
0x1
Once
This mode generates a trigger the first time that the ADC
conversion data enters the selected operational region.
0x2
Hysteresis Always
This mode generates a trigger when the ADC conversion data
falls within the selected operational region and continues to
generate the trigger until the hysteresis condition is cleared by
entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3.
0x3
Hysteresis Once
This mode generates a trigger the first time that the ADC
conversion data falls within the selected operational region. No
additional triggers are generated until the hysteresis condition
is cleared by entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Bit/Field
Name
Type
Reset
4
CIE
R/W
0
Description
Comparison Interrupt Enable
Value Description
3:2
CIC
R/W
0x0
1
Enables the comparison interrupt. The ADC conversion data is
used to determine if an interrupt should be generated according
to the programming of the CIC and CIM fields.
0
Disables the comparison interrupt. ADC conversion data has
no effect on interrupt generation.
Comparison Interrupt Condition
This field specifies the operational region in which an interrupt is
generated when the ADC conversion data is compared against the
values of COMP0 and COMP1. The COMP0 and COMP1 fields are defined
in the ADCDCCMPx registers.
Value Description
0x0
Low Band
ADC Data < COMP0 and < COMP1
0x1
Mid Band
COMP0 ≤ ADC Data < COMP1
0x2
reserved
0x3
High Band
COMP0 < COMP1 ≤ ADC Data
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
1:0
CIM
R/W
0x0
Description
Comparison Interrupt Mode
This field specifies the mode by which the interrupt comparison is made.
Value Description
0x0
Always
This mode generates an interrupt every time the ADC conversion
data falls within the selected operational region.
0x1
Once
This mode generates an interrupt the first time that the ADC
conversion data enters the selected operational region.
0x2
Hysteresis Always
This mode generates an interrupt when the ADC conversion
data falls within the selected operational region and continues
to generate the interrupt until the hysteresis condition is cleared
by entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3.
0x3
Hysteresis Once
This mode generates an interrupt the first time that the ADC
conversion data falls within the selected operational region. No
additional interrupts are generated until the hysteresis condition
is cleared by entering the opposite operational region.
Note that the hysteresis modes are only defined for CTC
encodings of 0x0 and 0x3.
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Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)
Register 47: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40
Register 48: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44
Register 49: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48
Register 50: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C
Register 51: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50
Register 52: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54
Register 53: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58
Register 54: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C
This register defines the comparison values that are used to determine if the ADC conversion data
falls in the appropriate operating region.
Note:
The value in the COMP1 field must be greater than or equal to the value in the COMP0 field
or unexpected results can occur.
ADC Digital Comparator Range 0 (ADCDCCMP0)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0xE40
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
reserved
Type
Reset
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
20
COMP1
RO
0
RO
0
RO
0
RO
0
COMP0
RO
0
RO
0
R/W
0
Bit/Field
Name
Type
Reset
31:26
reserved
RO
0x0
25:16
COMP1
R/W
0x000
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Compare 1
The value in this field is compared against the ADC conversion data.
The result of the comparison is used to determine if the data lies within
the high-band region.
Note that the value of COMP1 must be greater than or equal to the value
of COMP0.
15:10
reserved
RO
0x0
9:0
COMP0
R/W
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Compare 0
The value in this field is compared against the ADC conversion data.
The result of the comparison is used to determine if the data lies within
the low-band region.
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Stellaris® LM3S5B91 Microcontroller
14
Universal Asynchronous Receivers/Transmitters
(UARTs)
®
The Stellaris LM3S5B91 controller includes three Universal Asynchronous Receiver/Transmitter
(UART) with the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ False-start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Full modem handshake support (on UART1)
■ LIN protocol support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
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Universal Asynchronous Receivers/Transmitters (UARTs)
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
14.1
Block Diagram
Figure 14-1. UART Module Block Diagram
System Clock
DMA Request
DMA Control
UARTDMACTL
Interrupt
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
14.2
TxFIFO
16 x 8
.
.
.
Baud Rate
Generator
UARTDR
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
UARTLCTL
UARTLSS
UARTLTIM
UnTx
UARTIBRD
UARTFBRD
Control/Status
Transmitter
(with SIR
Transmit
Encoder)
RxFIFO
16 x 8
Receiver
(with SIR
Receive
Decoder)
UnRx
.
.
.
Signal Description
Table 14-1 on page 581 and Table 14-2 on page 582 list the external signals of the UART module
and describe the function of each. The UART signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset, with the exception of the U0Rx and U0Tx pins which default
to the UART function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible
GPIO pin placements for these UART signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 323) should be set to choose the UART function. The number
in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port
Control (GPIOPCTL) register (page 341) to assign the UART signal to the specified GPIO port pin.
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Stellaris® LM3S5B91 Microcontroller
For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 298.
Table 14-1. Signals for UART (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
U0Rx
26
PA0 (1)
I
TTL
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx
27
PA1 (1)
O
TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1CTS
2
10
34
50
PE6 (9)
PD0 (9)
PA6 (9)
PJ3 (9)
I
TTL
UART module 1 Clear To Send modem status input
signal.
U1DCD
1
11
35
52
PE7 (9)
PD1 (9)
PA7 (9)
PJ4 (9)
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
47
53
PF0 (9)
PJ5 (9)
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
40
55
100
PG5 (10)
PJ7 (9)
PD7 (9)
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
37
41
97
PG6 (10)
PG4 (10)
PD4 (9)
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
43
54
61
PF6 (10)
PJ6 (9)
PF1 (9)
O
TTL
UART module 1 Request to Send modem output
control line.
U1Rx
10
12
23
26
66
92
PD0 (5)
PD2 (1)
PC6 (5)
PA0 (9)
PB0 (5)
PB4 (7)
I
TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Tx
11
13
22
27
67
91
PD1 (5)
PD3 (1)
PC7 (5)
PA1 (9)
PB1 (5)
PB5 (7)
O
TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx
10
19
92
98
PD0 (4)
PG0 (1)
PB4 (4)
PD5 (9)
I
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx
6
11
18
99
PE4 (5)
PD1 (4)
PG1 (1)
PD6 (9)
O
TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
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Table 14-2. Signals for UART (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
U0Rx
L3
PA0 (1)
I
TTL
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx
M3
PA1 (1)
O
TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1CTS
A1
G1
L6
M10
PE6 (9)
PD0 (9)
PA6 (9)
PJ3 (9)
I
TTL
UART module 1 Clear To Send modem status input
signal.
U1DCD
B1
G2
M6
K11
PE7 (9)
PD1 (9)
PA7 (9)
PJ4 (9)
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
M9
K12
PF0 (9)
PJ5 (9)
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
M7
L12
A2
PG5 (10)
PJ7 (9)
PD7 (9)
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
L7
K3
B5
PG6 (10)
PG4 (10)
PD4 (9)
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
M8
L10
H12
PF6 (10)
PJ6 (9)
PF1 (9)
O
TTL
UART module 1 Request to Send modem output
control line.
U1Rx
G1
H2
M2
L3
E12
A6
PD0 (5)
PD2 (1)
PC6 (5)
PA0 (9)
PB0 (5)
PB4 (7)
I
TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Tx
G2
H1
L2
M3
D12
B7
PD1 (5)
PD3 (1)
PC7 (5)
PA1 (9)
PB1 (5)
PB5 (7)
O
TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx
G1
K1
A6
C6
PD0 (4)
PG0 (1)
PB4 (4)
PD5 (9)
I
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx
B2
G2
K2
A3
PE4 (5)
PD1 (4)
PG1 (1)
PD6 (9)
O
TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
14.3
Functional Description
®
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 606). Transmit and receive are both enabled out of reset. Before any
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control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to
an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
14.3.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits
(LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 14-2 on page 583 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 14-2. UART Character Frame
UnTX
LSB
1
5-8 data bits
0
n
Parity bit
if enabled
Start
14.3.2
1-2
stop bits
MSB
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 602) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 603). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE
in UARTCTL is clear) or 8 (if HSE is set).
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to
as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5) in UARTCTL). This reference
clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during
receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 604), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
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when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
14.3.3
Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 598) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start
bit has been received), the receive counter begins running and data is sampled on the eighth cycle
of Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL
(described in “Transmit/Receive Logic” on page 583).
The start bit is valid if the UnRx signal is still low on the eighth cycle of Baud16 (HSE clear) or the
fourth cycle of Baud 8 (HSE set), otherwise a false start bit is detected and is ignored. Start bit errors
can be viewed in the UART Receive Status (UARTRSR) register (see page 595). If the start bit was
valid, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that
is, one bit period later) according to the programmed length of the data characters and value of the
HSE bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity
are defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO along with any error bits
associated with that word.
14.3.4
Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream and a half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output and decoded input to the UART. When enabled, the SIR block
uses the UnTx and UnRx pins for the SIR protocol. These signals should be connected to an infrared
transceiver to implement an IrDA SIR physical layer link. The SIR block can receive and transmit,
but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before
data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between
transmission and reception.The SIR block has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as a high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
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LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW and driving the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register. See page 601 for more
information on IrDA low-power pulse-duration configuration.
Figure 14-3 on page 585 shows the UART transmit and receive signals, with and without IrDA
modulation.
Figure 14-3. IrDA Data Modulation
Data bits
Start
bit
UnTx
1
0
0
0
1
Stop
bit
0
0
1
1
1
UnTx with IrDA
3
16 Bit period
Bit period
UnRx with IrDA
UnRx
0
1
0
Start
1
0
0
1
1
Data bits
0
1
Stop
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10-ms
delay between transmission and reception. This delay must be generated by software because it
is not automatically supported by the UART. The delay is required because the infrared receiver
electronics might become biased or even saturated from the optical power coupled from the adjacent
transmitter LED. This delay is known as latency or receiver setup time.
14.3.5
ISO 7816 Support
The UART offers basic support to allow communication with an ISO 7816 smartcard. When bit 3
(SMART) of the UARTCTL register is set, the UnTx signal is used as a bit clock, and the UnRx signal
is used as the half-duplex communication line connected to the smartcard. A GPIO signal can be
used to generate the reset signal to the smartcard. The remaining smartcard signals should be
provided by the system design.
When using ISO 7816 mode, the UARTLCRH register must be set to transmit 8-bit words (WLEN
bits 6:5 configured to 0x3) with EVEN parity (PEN set and EPS set). In this mode, the UART
automatically uses 2 stop bits, and the STP2 bit of the UARTLCRH register is ignored.
If a parity error is detected during transmission, UnRx is pulled Low during the second stop bit. In
this case, the UART aborts the transmission, flushes the transmit FIFO and discards any data it
contains, and raises a parity error interrupt, allowing software to detect the problem and initiate
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retransmission of the affected data. Note that the UART does not support automatic retransmission
in this case.
14.3.6
Modem Handshake Support
This section describes how to configure and use the modem status signals for UART1 when
connected as a DTE (data terminal equipment) or as a DCE (data communications equipment). In
general, a modem is a DCE and a computing device that connects to a modem is the DTE.
14.3.6.1
Signaling
The status signals provided by UART1differ based on whether the UART is used as a DTE or DCE.
When used as a DTE, the modem status signals are defined as:
■ U1CTS is Clear To Send
■ U1DSR is Data Set Ready
■ U1DCD is Data Carrier Detect
■ U1RI is Ring Indicator
■ U1RTS is Request To Send
■ U1DTR is Data Terminal Ready
When used as a DCE, the the modem status signals are defined as:
■ U1CTS is Request To Send
■ U1DSR is Data Terminal Ready
■ U1RTS is Clear To Send
■ U1DTR is Data Set Ready
Note that the support for DCE functions Data Carrier Detect and Ring Indicator are not provided. If
these signals are required, their function can be emulated by using a general-purpose I/O signal
and providing software support.
14.3.6.2
Flow Control Methods
Flow control can be accomplished by either hardware or software. The following sections describe
the different methods.
Hardware Flow Control (RTS/CTS)
Hardware flow control between two devices is accomplished by connecting the U1RTS output to the
Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the
receiving device to the U1CTS input.
The U1CTS input controls the transmitter. The transmitter may only transmit data when the U1CTS
input is asserted. The U1RTS output signal indicates the state of the receive FIFO. U1CTS remains
asserted until the preprogrammed watermark level is reached, indicating that the Receive FIFO has
no space to store additional characters.
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The UARTCTL register bits 15 (CTSEN) and 14 (RTSEN) specify the flow control mode as shown in
Table 14-3 on page 587.
Table 14-3. Flow Control Mode
Description
CTSEN
RTSEN
1
1
RTS and CTS flow control enabled
1
0
Only CTS flow control enabled
0
1
Only RTS flow control enabled
0
0
Both RTS and CTS flow control disabled
Note that when RTSEN is 1, software cannot modify the U1RTS output value through the UARTCTL
register Request to Send (RTS) bit, and the status of the RTS bit should be ignored.
Software Flow Control (Modem Status Interrupts)
Software flow control between two devices is accomplished by using interrupts to indicate the status
of the UART. Interrupts may be generated for U1DSR, U1DCD, U1CTS, and U1RI using the UARTIM
bits 3 through 0 respectively. The raw and masked interrupt status may be checked using the
UARTRIS and UARTMIS register. These interrupts may be cleared using the UARTICR register.
14.3.7
LIN Support
The UART module offers hardware support for the LIN protocol as either a master or a slave. The
LIN mode is enabled by setting the LIN bit in the UARTCTL register. A LIN message is identified
by the use of a Sync Break at the beginning of the message. The Sync Break is a transmission of
a series of 0s. The Sync Break is followed by the Sync data field (0x55). Figure 14-4 on page 587
illustrates the structure of a LIN message.
Figure 14-4. LIN Message
Message Frame
Header
Synch
Break
Synch Field
Response
Ident Field
Data
Field(s)
In-Frame
Response
Data Field
Checksum
Field
Interbyte
Space
The UART should be configured as followed to operate in LIN mode:
1. Configure the UART for 1 start bit, 8 data bits, no parity, and 1 stop bit. Enable the Transmit
FIFO.
2. Set the LIN bit in the UARTCTL register.
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When preparing to send a LIN message, the TXFIFO should contain the Sync data (0x55) at FIFO
location 0 and the Identifier data at location 1, followed by the data to be transmitted, and with the
checksum in the final FIFO entry.
14.3.7.1
LIN Master
The UART is enabled to be the LIN master by setting the MASTER bit in the UARTLCTL register.
The length of the Sync Break is programmable using the BLEN field in the UARTLCTL register and
can be 13-16 bits (baud clock cycles).
14.3.7.2
LIN Slave
The LIN UART slave is required to adjust its baud rate to that of the LIN master. In slave mode, the
LIN UART recognizes the Sync Break, which must be at least 13 bits in duration. A timer is provided
to capture timing data on the 1st and 5th falling edges of the Sync field so that the baud rate can
be adjusted to match the master.
After detecting a Sync Break, the UART waits for the synchronization field. The first falling edge
generates an interrupt using the LME1RIS bit in the UARTRIS register, and the timer value is
captured and stored in the UARTLSS register (T1). On the fifth falling edge, a second interrupt is
generated using the LME5RIS bit in the UARTRIS register, and the timer value is captured again
(T2). The actual baud rate can be calculated using (T2-T1)/8, and the local baud rate should be
adjusted as needed. Figure 14-5 on page 588 illustrates the synchronization field.
Figure 14-5. LIN Synchronization Field
Sync Break
0
1
2
3
4
5
6
7
8
Synch Field
9
10
11
12
13
0
1
2
Edge 1
3
4
5
6
Edge 5
7
8
8 Tbit
Sync Break Detect
14.3.8
FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 593). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 604).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 598) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 610). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include ⅛, ¼, ½, ¾, and ⅞. For example,
if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data
bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark.
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14.3.9
Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the
EOT bit in UARTCTRL is set, when the last bit of all transmitted data leaves the serializer)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 619).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM) register (see page 612) by setting the corresponding IM bits. If interrupts are not
used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 615).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a 1 to the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 622).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
14.3.10
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work by setting
the LBE bit in the UARTCTL register (see page 606). In loopback mode, data transmitted on the
UnTx output is received on the UnRx input.
14.3.11
DMA Operation
The UART provides an interface to the μDMA controller with separate channels for transmit and
receive. The DMA operation of the UART is enabled through the UART DMA Control
(UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on
the receive or transmit channel when the associated FIFO can transfer data. For the receive channel,
a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer
request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger
level configured in the UARTIFLS register. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The
single and burst DMA transfer requests are handled automatically by the μDMA controller depending
on how the DMA channel is configured.
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To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control
(UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit
of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive
channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive
error occurs, the DMA receive requests are automatically disabled. This error condition can be
cleared by clearing the appropriate UART error interrupt.
If DMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The
interrupt occurs on the UART interrupt vector. Therefore, if interrupts are used for UART operation
and DMA is enabled, the UART interrupt handler must be designed to handle the μDMA completion
interrupt.
See “Micro Direct Memory Access (μDMA)” on page 240 for more details about programming the
μDMA controller.
14.4
Initialization and Configuration
To enable and initialize the UART, the following steps are necessary:
1. The peripheral clock must be enabled by setting the UART0, UART1, or UART2 bits in the RCGC1
register (see page 179).
2. The clock to the appropriate GPIO module must be enabled via the RCGC2 register in the
System Control module (see page 191).
3. Set the GPIO AFSEL bits for the appropriate pins (see page 323). To determine which GPIOs to
configure, see Table 24-4 on page 1088.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected (see page
325 and page 333).
5. Configure the PMCn fields in the GPIOPCTL register to assign the UART signals to the appropriate
pins (see page 341 and Table 24-5 on page 1097).
To use the UARTs, the peripheral clock must be enabled by setting the UART0, UART1, or UART2
bits in the RCGC1 register (see page 179). In addition, the clock to the appropriate GPIO module
must be enabled via the RCGC2 register in the System Control module (see page 191). To find out
which GPIO port to enable, refer to Table 24-5 on page 1097.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz, and the desired UART configuration is:
■ 115200 baud rate
■ Data length of 8 bits
■ One stop bit
■ No parity
■ FIFOs disabled
■ No interrupts
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The first thing to consider when programming the UART is the baud-rate divisor (BRD), because
the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using
the equation described in “Baud-Rate Generation” on page 583, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 602) should be set to 10
decimal or 0xA. The value to be loaded into the UARTFBRD register (see page 603) is calculated
by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 240)
and enable the DMA option(s) in the UARTDMACTL register.
6. Enable the UART by setting the UARTEN bit in the UARTCTL register.
14.5
Register Map
Table 14-4 on page 591 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000
Note that the UART module clock must be enabled before the registers can be programmed (see
page 179).
Note:
The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 606)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 14-4. UART Register Map
Offset
Name
Type
Reset
Description
See
page
0x000
UARTDR
R/W
0x0000.0000
UART Data
593
0x004
UARTRSR/UARTECR
R/W
0x0000.0000
UART Receive Status/Error Clear
595
0x018
UARTFR
RO
0x0000.0090
UART Flag
598
0x020
UARTILPR
R/W
0x0000.0000
UART IrDA Low-Power Register
601
0x024
UARTIBRD
R/W
0x0000.0000
UART Integer Baud-Rate Divisor
602
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Universal Asynchronous Receivers/Transmitters (UARTs)
Table 14-4. UART Register Map (continued)
Name
Type
Reset
0x028
UARTFBRD
R/W
0x0000.0000
UART Fractional Baud-Rate Divisor
603
0x02C
UARTLCRH
R/W
0x0000.0000
UART Line Control
604
0x030
UARTCTL
R/W
0x0000.0300
UART Control
606
0x034
UARTIFLS
R/W
0x0000.0012
UART Interrupt FIFO Level Select
610
0x038
UARTIM
R/W
0x0000.0000
UART Interrupt Mask
612
0x03C
UARTRIS
RO
0x0000.000F
UART Raw Interrupt Status
615
0x040
UARTMIS
RO
0x0000.0000
UART Masked Interrupt Status
619
0x044
UARTICR
W1C
0x0000.0000
UART Interrupt Clear
622
0x048
UARTDMACTL
R/W
0x0000.0000
UART DMA Control
624
0x090
UARTLCTL
R/W
0x0000.0000
UART LIN Control
625
0x094
UARTLSS
RO
0x0000.0000
UART LIN Snap Shot
626
0x098
UARTLTIM
RO
0x0000.0000
UART LIN Timer
627
0xFD0
UARTPeriphID4
RO
0x0000.0000
UART Peripheral Identification 4
628
0xFD4
UARTPeriphID5
RO
0x0000.0000
UART Peripheral Identification 5
629
0xFD8
UARTPeriphID6
RO
0x0000.0000
UART Peripheral Identification 6
630
0xFDC
UARTPeriphID7
RO
0x0000.0000
UART Peripheral Identification 7
631
0xFE0
UARTPeriphID0
RO
0x0000.0060
UART Peripheral Identification 0
632
0xFE4
UARTPeriphID1
RO
0x0000.0000
UART Peripheral Identification 1
633
0xFE8
UARTPeriphID2
RO
0x0000.0018
UART Peripheral Identification 2
634
0xFEC
UARTPeriphID3
RO
0x0000.0001
UART Peripheral Identification 3
635
0xFF0
UARTPCellID0
RO
0x0000.000D
UART PrimeCell Identification 0
636
0xFF4
UARTPCellID1
RO
0x0000.00F0
UART PrimeCell Identification 1
637
0xFF8
UARTPCellID2
RO
0x0000.0005
UART PrimeCell Identification 2
638
0xFFC
UARTPCellID3
RO
0x0000.00B1
UART PrimeCell Identification 3
639
14.6
Description
See
page
Offset
Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
592
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 1: UART Data (UARTDR), offset 0x000
Important: Use caution when reading this register. Performing a read may change bit status.
This register is the data register (the interface to the FIFOs).
For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit
FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of
the transmit FIFO). A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11
OE
RO
0
DATA
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error
Value Description
10
BE
RO
0
1
New data was received when the FIFO was full, resulting in
data loss.
0
No data has been lost due to a FIFO overrun.
UART Break Error
Value Description
1
A break condition has been detected, indicating that the receive
data input was held Low for longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
0
No break condition has occurred
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state), and the next valid start bit is received.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
9
PE
RO
0
Description
UART Parity Error
Value Description
1
The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
0
No parity error has occurred
In FIFO mode, this error is associated with the character at the top of
the FIFO.
8
FE
RO
0
UART Framing Error
Value Description
7:0
DATA
R/W
0x00
1
The received character does not have a valid stop bit (a valid
stop bit is 1).
0
No framing error has occurred
Data Transmitted or Received
Data that is to be transmitted via the UART is written to this field.
When read, this field contains the data that was received by the UART.
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Stellaris® LM3S5B91 Microcontroller
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared on reset.
Read-Only Status Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
OE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error
Value Description
1
New data was received when the FIFO was full, resulting in
data loss.
0
No data has been lost due to a FIFO overrun.
This bit is cleared by a write to UARTECR.
The FIFO contents remain valid because no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must read the data in order to empty the FIFO.
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Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
2
BE
RO
0
Description
UART Break Error
Value Description
1
A break condition has been detected, indicating that the receive
data input was held Low for longer than a full-word transmission
time (defined as start, data, parity, and stop bits).
0
No break condition has occurred
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
1
PE
RO
0
UART Parity Error
Value Description
1
The parity of the received data character does not match the
parity defined by bits 2 and 7 of the UARTLCRH register.
0
No parity error has occurred
This bit is cleared to 0 by a write to UARTECR.
0
FE
RO
0
UART Framing Error
Value Description
1
The received character does not have a valid stop bit (a valid
stop bit is 1).
0
No framing error has occurred
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
Write-Only Error Clear Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
3
2
1
0
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
DATA
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
596
WO
0
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
31:8
reserved
WO
0x0000.00
7:0
DATA
WO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1. The RI, DCD, DSR and CTS bits indicate the modem status.
Note that bits [8,2:0] are only implemented on UART1. These bits are reserved on UART0 and
UART2.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x018
Type RO, reset 0x0000.0090
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
15
14
13
RO
0
RO
0
RO
0
RO
0
12
11
10
9
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
RI
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RI
TXFE
RXFF
TXFF
RXFE
BUSY
DCD
DSR
CTS
RO
0
RO
1
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Ring Indicator
Value Description
1
The U1RI signal is asserted.
0
The U1RI signal is not asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
7
TXFE
RO
1
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1
If the FIFO is disabled (FEN is 0), the transmit holding register
is empty.
If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
0
The transmitter has data to transmit.
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
6
RXFF
RO
0
Description
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1
If the FIFO is disabled (FEN is 0), the receive holding register
is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.
0
5
TXFF
RO
0
The receiver can receive data.
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1
If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
0
4
RXFE
RO
1
The transmitter is not full.
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1
If the FIFO is disabled (FEN is 0), the receive holding register
is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
0
3
BUSY
RO
0
The receiver is not empty.
UART Busy
Value Description
1
The UART is busy transmitting data. This bit remains set until
the complete byte, including all stop bits, has been sent from
the shift register.
0
The UART is not busy.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
2
DCD
RO
0
Data Carrier Detect
Value Description
1
The U1DCD signal is asserted.
0
The U1DCD signal is not asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
1
DSR
RO
0
Description
Data Set Ready
Value Description
1
The U1DSR signal is asserted.
0
The U1DSR signal is not asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0
CTS
RO
0
Clear To Send
Value Description
1
The U1CTS signal is asserted.
0
The U1CTS signal is not asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
600
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power
SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when
reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
The divisor must be programmed such that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, resulting in a
low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum
frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected,
but pulses greater than 1.4 μs are accepted as valid pulses.
Note:
Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
ILPDVSR
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
ILPDVSR
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
IrDA Low-Power Divisor
This field contains the 8-bit low-power divisor value.
May 24, 2010
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 583
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
DIVINT
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DIVINT
R/W
0x0000
Integer Baud-Rate Divisor
602
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 583
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DIVFRAC
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.000
5:0
DIVFRAC
R/W
0x0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fractional Baud-Rate Divisor
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Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x02C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
SPS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
SPS
R/W
0
RO
0
R/W
0
5
WLEN
R/W
0
R/W
0
4
3
2
1
0
FEN
STP2
EPS
PEN
BRK
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
6:5
WLEN
R/W
0x0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
4
FEN
R/W
0
0x0
5 bits (default)
0x1
6 bits
0x2
7 bits
0x3
8 bits
UART Enable FIFOs
Value Description
1
The transmit and receive FIFO buffers are enabled (FIFO mode).
0
The FIFOs are disabled (Character mode). The FIFOs become
1-byte-deep holding registers.
604
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
3
STP2
R/W
0
Description
UART Two Stop Bits Select
Value Description
1
Two stop bits are transmitted at the end of a frame. The receive
logic does not check for two stop bits being received.
When in 7816 smartcard mode (the SMART bit is set in the
UARTCTL register), the number of stop bits is forced to 2.
0
2
EPS
R/W
0
One stop bit is transmitted at the end of a frame.
UART Even Parity Select
Value Description
1
Even parity generation and checking is performed during
transmission and reception, which checks for an even number
of 1s in data and parity bits.
0
Odd parity is performed, which checks for an odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
1
PEN
R/W
0
UART Parity Enable
Value Description
0
BRK
R/W
0
1
Parity checking and generation is enabled.
0
Parity is disabled and no parity bit is added to the data frame.
UART Send Break
Value Description
1
A Low level is continually output on the UnTx signal, after
completing transmission of the current character. For the proper
execution of the break command, software must set this bit for
at least two frames (character periods).
0
Normal use.
May 24, 2010
605
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit
Enable (TXE) and Receive Enable (RXE) bits, which are set.
To enable the UART module, the UARTEN bit must be set. If software requires a configuration change
in the module, the UARTEN bit must be cleared before the configuration changes are written. If the
UART is disabled during a transmit or receive operation, the current transaction is completed prior
to the UART stopping.
Note that bits [15:14,11:10] are only implemented on UART1. These bits are reserved on UART0
and UART2.
Note:
The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by clearing bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x030
Type R/W, reset 0x0000.0300
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
Type
Reset
RO
0
RO
0
RO
0
13
12
15
14
CTSEN
RTSEN
R/W
0
R/W
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
5
4
3
2
1
0
RTS
DTR
RXE
TXE
LBE
LIN
HSE
EOT
SMART
SIRLP
SIREN
UARTEN
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
606
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
15
CTSEN
R/W
0
Description
Enable Clear To Send
Value Description
1
CTS hardware flow control is enabled. Data is only transmitted
when the U1CTS signal is asserted.
0
CTS hardware flow control is disabled.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
14
RTSEN
R/W
0
Enable Request to Send
Value Description
1
RTS hardware flow control is enabled. Data is only requested
(by asserting U1RTS) when the receive FIFO has available
entries.
0
RTS hardware flow control is disabled.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
13:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
RTS
R/W
0
Request to Send
When RTSEN is clear, the status of this bit is reflected on the U1RTS
signal. If RTSEN is set, this bit is ignored on a write and should be ignored
on read.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
10
DTR
R/W
0
Data Terminal Ready
This bit sets the state of the U1DTR output.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
9
RXE
R/W
1
UART Receive Enable
Value Description
1
The receive section of the UART is enabled.
0
The receive section of the UART is disabled.
If the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note:
To enable reception, the UARTEN bit must also be set.
May 24, 2010
607
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
8
TXE
R/W
1
Description
UART Transmit Enable
Value Description
1
The transmit section of the UART is enabled.
0
The transmit section of the UART is disabled.
If the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note:
7
LBE
R/W
0
To enable transmission, the UARTEN bit must also be set.
UART Loop Back Enable
Value Description
6
LIN
R/W
0
1
The UnTx path is fed through the UnRx path.
0
Normal operation.
LIN Mode Enable
Value Description
5
HSE
R/W
0
1
The UART operates in LIN mode.
0
Normal operation.
High-Speed Enable
Value Description
1
The UART is clocked using the system clock divided by 8.
0
The UART is clocked using the system clock divided by 16.
Note:
4
EOT
R/W
0
System clock used is also dependent on the baud-rate divisor
configuration (see page 602) and page 603).
End of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS
register.
Value Description
1
The TXRIS bit is set only after all transmitted data, including
stop bits, have cleared the serializer.
0
The TXRIS bit is set when the transmit FIFO condition specified
in UARTIFLS is met.
608
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
3
SMART
R/W
0
Description
ISO 7816 Smart Card Support
Value Description
1
The UART operates in Smart Card mode.
0
Normal operation.
The application must ensure that it sets 8-bit word length (WLEN set to
0x3) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in
UARTLCRH when using ISO 7816 mode.
In this mode, the value of the STP2 bit in UARTLCRH is ignored and
the number of stop bits is forced to 2. Note that the UART does not
support automatic retransmission on parity errors. If a parity error is
detected on transmission, all further transmit operations are aborted
and software must handle retransmission of the affected byte or
message.
2
SIRLP
R/W
0
UART SIR Low-Power Mode
This bit selects the IrDA encoding mode.
Value Description
1
The UART operates in SIR Low-Power mode. Low-level bits
are transmitted with a pulse width which is 3 times the period
of the IrLPBaud16 input signal, regardless of the selected bit
rate.
0
Low-level bits are transmitted as an active High pulse with a
width of 3/16th of the bit period.
Setting this bit uses less power, but might reduce transmission distances.
See page 601 for more information.
1
SIREN
R/W
0
UART SIR Enable
Value Description
0
UARTEN
R/W
0
1
The IrDA SIR block is enabled, and the UART will transmit and
receive data using SIR protocol.
0
Normal operation.
UART Enable
Value Description
1
The UART is enabled.
0
The UART is disabled.
If the UART is disabled in the middle of transmission or reception, it
completes the current character before stopping.
May 24, 2010
609
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x034
Type R/W, reset 0x0000.0012
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RXIFLSEL
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5:3
RXIFLSEL
R/W
0x2
R/W
1
TXIFLSEL
R/W
1
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value
Description
0x0
RX FIFO ≥ ⅛ full
0x1
RX FIFO ≥ ¼ full
0x2
RX FIFO ≥ ½ full (default)
0x3
RX FIFO ≥ ¾ full
0x4
RX FIFO ≥ ⅞ full
0x5-0x7 Reserved
610
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
2:0
TXIFLSEL
R/W
0x2
Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value
Description
0x0
TX FIFO ≤ ⅛ full
0x1
TX FIFO ≤ ¼ full
0x2
TX FIFO ≤ ½ full (default)
0x3
TX FIFO ≤ ¾ full
0x4
TX FIFO ≤ ⅞ full
0x5-0x7 Reserved
Note:
If the EOT bit in UARTCTL is set (see page 606), the transmit
interrupt is generated once the FIFO is completely empty and
all data including stop bits have left the transmit serializer. In
this case, the setting of TXIFLSEL is ignored.
May 24, 2010
611
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
LME5IM
LME1IM
LMSBIM
OEIM
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BEIM
PEIM
FEIM
RTIM
TXIM
RXIM
DSRIM
DCDIM
CTSIM
RIIM
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
Type
Reset
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
LME5IM
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LIN Mode Edge 5 Interrupt Mask
Value Description
14
LME1IM
R/W
0
1
An interrupt is sent to the interrupt controller when the LME5RIS
bit in the UARTRIS register is set.
0
The LME5RIS interrupt is suppressed and not sent to the
interrupt controller.
LIN Mode Edge 1 Interrupt Mask
Value Description
13
LMSBIM
R/W
0
1
An interrupt is sent to the interrupt controller when the LME1RIS
bit in the UARTRIS register is set.
0
The LME1RIS interrupt is suppressed and not sent to the
interrupt controller.
LIN Mode Sync Break Interrupt Mask
Value Description
1
An interrupt is sent to the interrupt controller when the LMSBRIS
bit in the UARTRIS register is set.
0
The LMSBRIS interrupt is suppressed and not sent to the
interrupt controller.
612
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
12:11
reserved
RO
0x0
10
OEIM
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error Interrupt Mask
Value Description
9
BEIM
R/W
0
1
An interrupt is sent to the interrupt controller when the OERIS
bit in the UARTRIS register is set.
0
The OERIS interrupt is suppressed and not sent to the interrupt
controller.
UART Break Error Interrupt Mask
Value Description
8
PEIM
R/W
0
1
An interrupt is sent to the interrupt controller when the BERIS
bit in the UARTRIS register is set.
0
The BERIS interrupt is suppressed and not sent to the interrupt
controller.
UART Parity Error Interrupt Mask
Value Description
7
FEIM
R/W
0
1
An interrupt is sent to the interrupt controller when the PERIS
bit in the UARTRIS register is set.
0
The PERIS interrupt is suppressed and not sent to the interrupt
controller.
UART Framing Error Interrupt Mask
Value Description
6
RTIM
R/W
0
1
An interrupt is sent to the interrupt controller when the FERIS
bit in the UARTRIS register is set.
0
The FERIS interrupt is suppressed and not sent to the interrupt
controller.
UART Receive Time-Out Interrupt Mask
Value Description
1
An interrupt is sent to the interrupt controller when the RTRIS
bit in the UARTRIS register is set.
0
The RTRIS interrupt is suppressed and not sent to the interrupt
controller.
May 24, 2010
613
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
5
TXIM
R/W
0
Description
UART Transmit Interrupt Mask
Value Description
4
RXIM
R/W
0
1
An interrupt is sent to the interrupt controller when the TXRIS
bit in the UARTRIS register is set.
0
The TXRIS interrupt is suppressed and not sent to the interrupt
controller.
UART Receive Interrupt Mask
Value Description
3
DSRIM
R/W
0
1
An interrupt is sent to the interrupt controller when the RXRIS
bit in the UARTRIS register is set.
0
The RXRIS interrupt is suppressed and not sent to the interrupt
controller.
UART Data Set Ready Modem Interrupt Mask
Value Description
2
DCDIM
R/W
0
1
An interrupt is sent to the interrupt controller when the DSRRIS
bit in the UARTRIS register is set.
0
The DSRRIS interrupt is suppressed and not sent to the interrupt
controller.
UART Data Carrier Detect Modem Interrupt Mask
Value Description
1
CTSIM
R/W
0
1
An interrupt is sent to the interrupt controller when the DCDRIS
bit in the UARTRIS register is set.
0
The DCDRIS interrupt is suppressed and not sent to the interrupt
controller.
UART Clear to Send Modem Interrupt Mask
Value Description
0
RIIM
R/W
0
1
An interrupt is sent to the interrupt controller when the CTSRIS
bit in the UARTRIS register is set.
0
The CTSRIS interrupt is suppressed and not sent to the interrupt
controller.
UART Ring Indicator Modem Interrupt Mask
Value Description
1
An interrupt is sent to the interrupt controller when the RIRIS
bit in the UARTRIS register is set.
0
The RIRIS interrupt is suppressed and not sent to the interrupt
controller.
614
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x03C
Type RO, reset 0x0000.000F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
LME5RIS LME1RIS LMSBRIS
Type
Reset
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
3
2
1
0
OERIS
BERIS
PERIS
FERIS
RTRIS
TXRIS
RXRIS
DSRRIS
DCDRIS
CTSRIS
RIRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
LME5RIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LIN Mode Edge 5 Raw Interrupt Status
Value Description
1
The timer value at the 5th falling edge of the LIN Sync Field has
been captured.
0
No interrupt
This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR
register.
14
LME1RIS
RO
0
LIN Mode Edge 1 Raw Interrupt Status
Value Description
1
The timer value at the 1st falling edge of the LIN Sync Field has
been captured.
0
No interrupt
This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR
register.
13
LMSBRIS
RO
0
LIN Mode Sync Break Raw Interrupt Status
Value Description
1
A LIN Sync Break has been detected.
0
No interrupt
This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR
register.
May 24, 2010
615
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
12:11
reserved
RO
0x0
10
OERIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error Raw Interrupt Status
Value Description
1
An overrun error has occurred.
0
No interrupt
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
9
BERIS
RO
0
UART Break Error Raw Interrupt Status
Value Description
1
A break error has occurred.
0
No interrupt
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
8
PERIS
RO
0
UART Parity Error Raw Interrupt Status
Value Description
1
A parity error has occurred.
0
No interrupt
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
7
FERIS
RO
0
UART Framing Error Raw Interrupt Status
Value Description
1
A framing error has occurred.
0
No interrupt
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
6
RTRIS
RO
0
UART Receive Time-Out Raw Interrupt Status
Value Description
1
A receive time out has occurred.
0
No interrupt
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
616
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
5
TXRIS
RO
0
Description
UART Transmit Raw Interrupt Status
Value Description
1
If the EOT bit in the UARTCTRL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
If the EOT bit is set, the last bit of all transmitted data and flags
has left the serializer.
0
No interrupt
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register.
4
RXRIS
RO
0
UART Receive Raw Interrupt Status
Value Description
1
The receive FIFO level has passed through the condition defined
in the UARTIFLS register.
0
No interrupt
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register.
3
DSRRIS
RO
0
UART Data Set Ready Modem Raw Interrupt Status
Value Description
1
Data Set Ready used for software flow control.
0
No interrupt
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
2
DCDRIS
RO
0
UART Data Carrier Detect Modem Raw Interrupt Status
Value Description
1
Data Carrier Detect used for software flow control.
0
No interrupt
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
1
CTSRIS
RO
0
UART Clear to Send Modem Raw Interrupt Status
Value Description
1
Clear to Send used for software flow control.
0
No interrupt
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
May 24, 2010
617
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
0
RIRIS
RO
0
Description
UART Ring Indicator Modem Raw Interrupt Status
Value Description
1
Ring Indicator used for software flow control.
0
No interrupt
This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register.
618
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
LME5MIS LME1MIS LMSBMIS
Type
Reset
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
OEMIS
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
LME5MIS
RO
0
DSRMIS DCDMIS
RO
0
RO
0
1
0
CTSMIS
RIMIS
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LIN Mode Edge 5 Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to the 5th falling edge
of the LIN Sync Field.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR
register.
14
LME1MIS
RO
0
LIN Mode Edge 1 Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to the 1st falling edge
of the LIN Sync Field.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR
register.
13
LMSBMIS
RO
0
LIN Mode Sync Break Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due the receipt of a LIN
Sync Break.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR
register.
May 24, 2010
619
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
Name
Type
Reset
12:11
reserved
RO
0x0
10
OEMIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to an overrun error.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
9
BEMIS
RO
0
UART Break Error Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to a break error.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
8
PEMIS
RO
0
UART Parity Error Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to a parity error.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
7
FEMIS
RO
0
UART Framing Error Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to a framing error.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
6
RTMIS
RO
0
UART Receive Time-Out Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to a receive time out.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
5
TXMIS
RO
0
UART Transmit Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to passing through
the specified transmit FIFO level (if the EOT bit is clear) or due
to the transmission of the last data bit (if the EOT bit is set).
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register.
620
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4
RXMIS
RO
0
Description
UART Receive Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register.
3
DSRMIS
RO
0
UART Data Set Ready Modem Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to Data Set Ready.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
2
DCDMIS
RO
0
UART Data Carrier Detect Modem Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to Data Carrier Detect.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
1
CTSMIS
RO
0
UART Clear to Send Modem Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to Clear to Send.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
0
RIMIS
RO
0
UART Ring Indicator Modem Masked Interrupt Status
Value Description
1
An unmasked interrupt was signaled due to Ring Indicator.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register.
May 24, 2010
621
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
LME5MIC LME1MIC LMSBMIC
Type
Reset
W1C
0
W1C
0
W1C
0
RO
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
OEIC
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
LME5MIC
W1C
0
DSRMIC DCDMIC CTSMIC
W1C
0
W1C
0
W1C
0
0
RIMIC
W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LIN Mode Edge 5 Interrupt Clear
Writing a 1 to this bit clears the LME5RIS bit in the UARTRIS register
and the LME5MIS bit in the UARTMIS register.
14
LME1MIC
W1C
0
LIN Mode Edge 1 Interrupt Clear
Writing a 1 to this bit clears the LME1RIS bit in the UARTRIS register
and the LME1MIS bit in the UARTMIS register.
13
LMSBMIC
W1C
0
LIN Mode Sync Break Interrupt Clear
Writing a 1 to this bit clears the LMSBRIS bit in the UARTRIS register
and the LMSBMIS bit in the UARTMIS register.
12:11
reserved
RO
0x0
10
OEIC
W1C
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and
the OEMIS bit in the UARTMIS register.
9
BEIC
W1C
0
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and
the BEMIS bit in the UARTMIS register.
8
PEIC
W1C
0
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and
the PEMIS bit in the UARTMIS register.
622
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
7
FEIC
W1C
0
Description
Framing Error Interrupt Clear
Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and
the FEMIS bit in the UARTMIS register.
6
RTIC
W1C
0
Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and
the RTMIS bit in the UARTMIS register.
5
TXIC
W1C
0
Transmit Interrupt Clear
Writing a 1 to this bit clears the TXRIS bit in the UARTRIS register and
the TXMIS bit in the UARTMIS register.
4
RXIC
W1C
0
Receive Interrupt Clear
Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and
the RXMIS bit in the UARTMIS register.
3
DSRMIC
W1C
0
UART Data Set Ready Modem Interrupt Clear
Writing a 1 to this bit clears the DSRRIS bit in the UARTRIS register
and the DSRMIS bit in the UARTMIS register.
2
DCDMIC
W1C
0
UART Data Carrier Detect Modem Interrupt Clear
Writing a 1 to this bit clears the DCDRIS bit in the UARTRIS register
and the DCDMIS bit in the UARTMIS register.
1
CTSMIC
W1C
0
UART Clear to Send Modem Interrupt Clear
Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register
and the CTSMIS bit in the UARTMIS register.
0
RIMIC
W1C
0
UART Ring Indicator Modem Interrupt Clear
Writing a 1 to this bit clears the RIRIS bit in the UARTRIS register and
the RIMIS bit in the UARTMIS register.
May 24, 2010
623
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 14: UART DMA Control (UARTDMACTL), offset 0x048
The UARTDMACTL register is the DMA control register.
UART DMA Control (UARTDMACTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x048
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
31:3
reserved
RO
2
DMAERR
R/W
RO
0
Reset
DMAERR TXDMAE RXDMAE
R/W
0
R/W
0
R/W
0
Description
0x00000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DMA on Error
Value Description
1
TXDMAE
R/W
0
1
µDMA receive requests are automatically disabled when a
receive error occurs.
0
µDMA receive requests are unaffected when a receive error
occurs.
Transmit DMA Enable
Value Description
0
RXDMAE
R/W
0
1
µDMA for the transmit FIFO is enabled.
0
µDMA for the transmit FIFO is disabled.
Receive DMA Enable
Value Description
1
µDMA for the receive FIFO is enabled.
0
µDMA for the receive FIFO is disabled.
624
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 15: UART LIN Control (UARTLCTL), offset 0x090
The UARTLCTL register is the configures the operation of the UART when in LIN mode.
UART LIN Control (UARTLCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x090
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
BLEN
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5:4
BLEN
R/W
0x0
reserved
RO
0
MASTER
RO
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sync Break Length
Value Description
3:1
reserved
RO
0x0
0
MASTER
R/W
0
0x3
Sync break length is 16T bits
0x2
Sync break length is 15T bits
0x1
Sync break length is 14T bits
0x0
Sync break length is 13T bits (default)
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LIN Master Enable
Value Description
1
The UART operates as a LIN master.
0
The UART operates as a LIN slave.
May 24, 2010
625
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094
The UARTLSS register captures the free-running timer value when either the Sync Edge 1 or the
Sync Edge 5 is detected in LIN mode.
UART LIN Snap Shot (UARTLSS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x094
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
TSS
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TSS
RO
0x0000
Timer Snap Shot
This field contains the value of the free-running timer when either the
Sync Edge 5 or the Sync Edge 1 was detected.
626
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 17: UART LIN Timer (UARTLTIM), offset 0x098
The UARTLTIM register contains the current timer value for the free-running timer that is used to
calculate the baud rate when in LIN slave mode. The value in this register is used along with the
value in the UART LIN Snap Shot (UARTLSS) register to adjust the baud rate to match that of the
master.
UART LIN Timer (UARTLTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x098
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
TIMER
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TIMER
RO
0x0000
Timer Value
This field contains the value of the free-running timer.
May 24, 2010
627
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 18: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID4
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
628
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 19: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID5
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID5
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
May 24, 2010
629
Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 20: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID6
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID6
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 21: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID7
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID7
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
May 24, 2010
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Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 22: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE0
Type RO, reset 0x0000.0060
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x60
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 23: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID1
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 24: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID2
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x18
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 25: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
PID3
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x01
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
May 24, 2010
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Texas Instruments-Advance Information
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 26: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 27: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
CID1
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 28: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID2
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID2
RO
0x05
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 29: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID3
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID3
RO
0xB1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
May 24, 2010
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Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
15
Synchronous Serial Interface (SSI)
®
The Stellaris microcontroller includes two Synchronous Serial Interface (SSI) modules. Each SSI
is a master or slave interface for synchronous serial communication with peripheral devices that
have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces.
®
The Stellaris LM3S5B91 controller includes two SSI modules with the following features:
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when FIFO contains 4 entries
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Stellaris® LM3S5B91 Microcontroller
15.1
Block Diagram
Figure 15-1. SSI Module Block Diagram
DMA Request
DMA Control
SSIDMACTL
Interrupt
Interrupt Control
TxFIFO
8 x 16
SSIIM
SSIMIS
SSIRIS
SSIICR
.
.
.
Control/Status
SSITx
SSICR0
SSICR1
SSISR
SSIRx
Transmit/
Receive
Logic
SSIDR
RxFIFO
8 x 16
Clock Prescaler
System Clock
SSIClk
SSIFss
.
.
.
SSICPSR
Identification Registers
SSIPCellID0
SSIPCellID1
SSIPCellID2
SSIPCellID3
15.2
SSIPeriphID0
SSIPeriphID1
SSIPeriphID2
SSIPeriphID3
SSIPeriphID4
SSIPeriphID5
SSIPeriphID6
SSIPeriphID7
Signal Description
Table 15-1 on page 642 and Table 15-2 on page 642 list the external signals of the SSI module and
describe the function of each. The SSI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and
SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Mux/Pin
Assignment" lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO
Alternate Function Select (GPIOAFSEL) register (page 323) should be set to choose the SSI
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Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
function. The number in parentheses is the encoding that must be programmed into the PMCn field
in the GPIO Port Control (GPIOPCTL) register (page 341) to assign the SSI signal to the specified
GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 298.
Table 15-1. Signals for SSI (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
SSI0Clk
28
PA2 (1)
I/O
TTL
SSI module 0 clock.
SSI0Fss
29
PA3 (1)
I/O
TTL
SSI module 0 frame.
SSI0Rx
30
PA4 (1)
I
TTL
SSI module 0 receive.
SSI0Tx
31
PA5 (1)
O
TTL
SSI module 0 transmit.
SSI1Clk
60
74
76
PF2 (9)
PE0 (2)
PH4 (11)
I/O
TTL
SSI module 1 clock.
SSI1Fss
59
63
75
PF3 (9)
PH5 (11)
PE1 (2)
I/O
TTL
SSI module 1 frame.
SSI1Rx
58
62
95
PF4 (9)
PH6 (11)
PE2 (2)
I
TTL
SSI module 1 receive.
SSI1Tx
15
46
96
PH7 (11)
PF5 (9)
PE3 (2)
O
TTL
SSI module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 15-2. Signals for SSI (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
SSI0Clk
M4
PA2 (1)
I/O
TTL
SSI module 0 clock.
SSI0Fss
L4
PA3 (1)
I/O
TTL
SSI module 0 frame.
SSI0Rx
L5
PA4 (1)
I
TTL
SSI module 0 receive.
SSI0Tx
M5
PA5 (1)
O
TTL
SSI module 0 transmit.
SSI1Clk
J11
B11
B10
PF2 (9)
PE0 (2)
PH4 (11)
I/O
TTL
SSI module 1 clock.
SSI1Fss
J12
F10
A12
PF3 (9)
PH5 (11)
PE1 (2)
I/O
TTL
SSI module 1 frame.
SSI1Rx
L9
G3
A4
PF4 (9)
PH6 (11)
PE2 (2)
I
TTL
SSI module 1 receive.
SSI1Tx
H3
L8
B4
PH7 (11)
PF5 (9)
PE3 (2)
O
TTL
SSI module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
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Stellaris® LM3S5B91 Microcontroller
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes. The SSI also supports the µDMA interface. The transmit and receive FIFOs
can be programmed as destination/source addresses in the µDMA module. µDMA operation is
enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 669).
15.3.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 662). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register (see page 655).
The frequency of the output clock SSIClk is defined by:
SSIClk = SysClk / (CPSDVSR * (1 + SCR))
Note:
For master mode, the system clock must be at least two times faster than the SSIClk. For
slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 1157 to view SSI timing parameters.
15.3.2
FIFO Operation
15.3.2.1
Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 659), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a µDMA request when the FIFO is empty.
15.3.2.2
Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
15.3.3
Interrupts
The SSI can generate interrupts when the following conditions are observed:
■ Transmit FIFO service (when the transmit FIFO is half full or less)
■ Receive FIFO service (when the receive FIFO is half full or more)
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■ Receive FIFO time-out
■ Receive FIFO overrun
■ End of transmission
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
generates a single interrupt request to the controller regardless of the number of active interrupts.
Each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the
SSI Interrupt Mask (SSIIM) register (see page 663). Setting the appropriate mask bit enables the
interrupt.
The individual outputs, along with a combined interrupt output, allow use of either a global interrupt
service routine or modular device drivers to handle interrupts. The transmit and receive dynamic
dataflow interrupts have been separated from the status interrupts so that data can be read or written
in response to the FIFO trigger levels. The status of the individual interrupt sources can be read
from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers
(see page 664 and page 666, respectively).
The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not
SSIClk is currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If
the RX FIFO is emptied before 32 clocks have passed, the time-out period is reset. As a result, the
ISR should clear the Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing
a 1 to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared
so late that the ISR returns before the interrupt is actually cleared, or the ISR may be re-activated
unnecessarily.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely.
This interrupt can be used to indicate when it is safe to turn off the SSI module clock or enter sleep
mode. In addition, because transmitted data and received data complete at exactly the same time,
the interrupt can also indicate that read data is ready immediately, without waiting for the receive
FIFO time-out period to complete.
15.3.4
Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk and
latch data from the other device on the falling edge.
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Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
15.3.4.1
Texas Instruments Synchronous Serial Frame Format
Figure 15-2 on page 645 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
4 to 16 bits
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
each falling edge of SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 15-3 on page 645 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
4 to 16 bits
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15.3.4.2
Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits in the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is set, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing
a clock transition before the first data capture edge. When the SPH phase control bit is clear, data
is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second
clock edge transition.
15.3.4.3
Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 15-4 on page 646 and Figure 15-5 on page 646.
Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx
LSB
MSB
Q
4 to 16 bits
SSITx
MSB
Note:
LSB
Q is undefined.
Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
LSB
MSB
MSB
4 to16 bits
SSITx LSB
MSB
LSB
MSB
In this configuration, during idle periods:
■ SSIClk is forced Low
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■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSIFss master signal being driven Low, causing slave data to be enabled onto the SSIRx input
line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Once both the
master and slave data have been set, the SSIClk master clock pin goes High after one additional
half SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSIFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned
to its idle state one SSIClk period after the last bit has been captured.
15.3.4.4
Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
15-6 on page 647, which covers both single and continuous transfers.
Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSIClk
SSIFss
SSIRx
Q
Q
MSB
LSB
Q
4 to 16 bits
SSITx
LSB
MSB
Note:
Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
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■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSIFss master signal being driven Low. The master SSITx output is enabled. After an additional
one-half SSIClk period, both master and slave valid data are enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words,
and termination is the same as that of the single word transfer.
15.3.4.5
Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 15-7 on page 648 and Figure 15-8 on page 648.
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSIRx
MSB
LSB
Q
4 to 16 bits
SSITx
LSB
MSB
Note:
Q is undefined.
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
LSB
MSB
4 to 16 bits
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
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If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSIFss master signal being driven Low, causing slave data to be immediately transferred onto
the SSIRx line of the master. The master SSITx output pad is enabled.
One-half period later, valid master data is transferred to the SSITx line. Once both the master and
slave data have been set, the SSIClk master clock pin becomes Low after one additional half
SSIClk period, meaning that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSIFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned
to its idle state one SSIClk period after the last bit has been captured.
15.3.4.6
Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
15-9 on page 649, which covers both single and continuous transfers.
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
SSIRx
Q
MSB
LSB
Q
4 to 16 bits
MSB
SSITx
Note:
LSB
Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After an
additional one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
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After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state until the
final bit of the last word has been captured and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
15.3.4.7
MICROWIRE Frame Format
Figure 15-10 on page 650 shows the MICROWIRE frame format for a single frame. Figure
15-11 on page 651 shows the same format when back-to-back frames are transmitted.
Figure 15-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSITx
LSB
MSB
8-bit control
0
SSIRx
MSB
LSB
4 to 16 bits
output data
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex and uses a master-slave message passing technique. Each serial transmission begins
with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of
SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one
clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto
the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge
of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock
period after the last bit has been latched in the receive serial shifter, causing the data to be transferred
to the receive FIFO.
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Note:
The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx
LSB
MSB
LSB
8-bit control
SSIRx
0
MSB
MSB
LSB
4 to 16 bits
output data
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 15-12 on page 651 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
tSetup=(2*tSSIClk)
tHold=tSSIClk
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
15.3.5
DMA Operation
The SSI peripheral provides an interface to the μDMA controller with separate channels for transmit
and receive. The µDMA operation of the SSI is enabled through the SSI DMA Control (SSIDMACTL)
register. When µDMA operation is enabled, the SSI asserts a µDMA request on the receive or
transmit channel when the associated FIFO can transfer data. For the receive channel, a single
transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is
asserted whenever the amount of data in the receive FIFO is 4 or more items. For the transmit
channel, a single transfer request is asserted whenever at least one empty location is in the transmit
FIFO. The burst request is asserted whenever the transmit FIFO has 4 or more empty slots. The
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single and burst µDMA transfer requests are handled automatically by the μDMA controller depending
how the µDMA channel is configured. To enable µDMA operation for the receive channel, the
RXDMAE bit of the DMA Control (SSIDMACTL) register should be set. To enable µDMA operation
for the transmit channel, the TXDMAE bit of SSIDMACTL should be set. If µDMA is enabled, then
the μDMA controller triggers an interrupt when a transfer is complete. The interrupt occurs on the
SSI interrupt vector. Therefore, if interrupts are used for SSI operation and µDMA is enabled, the
SSI interrupt handler must be designed to handle the μDMA completion interrupt.
See “Micro Direct Memory Access (μDMA)” on page 240 for more details about programming the
μDMA controller.
15.4
Initialization and Configuration
To enable and initialize the SSI, the following steps are necessary:
1. Enable the SSI module by setting the SSI bit in the RCGC1 register (see page 179).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register (see page 191). To
find out which GPIO port to enable, refer to Table 24-5 on page 1097.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 323). To determine which GPIOs to
configure, see Table 24-4 on page 1088.
4. Configure the PMCn fields in the GPIOPCTL register to assign the SSI signals to the appropriate
pins. See page 341 and Table 24-5 on page 1097.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Optionally, configure the μDMA channel (see “Micro Direct Memory Access (μDMA)” on page 240)
and enable the DMA option(s) in the SSIDMACTL register.
6. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
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■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
SSIClk = SysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 +
SCR))
In this case, if CPSDVSR=0x2, SCR must be 0x9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is clear.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register.
15.5
Register Map
Table 15-3 on page 653 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 179).
Note:
The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 15-3. SSI Register Map
Offset
Name
Type
Reset
Description
See
page
0x000
SSICR0
R/W
0x0000.0000
SSI Control 0
655
0x004
SSICR1
R/W
0x0000.0000
SSI Control 1
657
0x008
SSIDR
R/W
0x0000.0000
SSI Data
659
0x00C
SSISR
RO
0x0000.0003
SSI Status
660
0x010
SSICPSR
R/W
0x0000.0000
SSI Clock Prescale
662
0x014
SSIIM
R/W
0x0000.0000
SSI Interrupt Mask
663
0x018
SSIRIS
RO
0x0000.0008
SSI Raw Interrupt Status
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Table 15-3. SSI Register Map (continued)
Offset
Name
0x01C
Reset
SSIMIS
RO
0x0000.0000
SSI Masked Interrupt Status
666
0x020
SSIICR
W1C
0x0000.0000
SSI Interrupt Clear
668
0x024
SSIDMACTL
R/W
0x0000.0000
SSI DMA Control
669
0xFD0
SSIPeriphID4
RO
0x0000.0000
SSI Peripheral Identification 4
670
0xFD4
SSIPeriphID5
RO
0x0000.0000
SSI Peripheral Identification 5
671
0xFD8
SSIPeriphID6
RO
0x0000.0000
SSI Peripheral Identification 6
672
0xFDC
SSIPeriphID7
RO
0x0000.0000
SSI Peripheral Identification 7
673
0xFE0
SSIPeriphID0
RO
0x0000.0022
SSI Peripheral Identification 0
674
0xFE4
SSIPeriphID1
RO
0x0000.0000
SSI Peripheral Identification 1
675
0xFE8
SSIPeriphID2
RO
0x0000.0018
SSI Peripheral Identification 2
676
0xFEC
SSIPeriphID3
RO
0x0000.0001
SSI Peripheral Identification 3
677
0xFF0
SSIPCellID0
RO
0x0000.000D
SSI PrimeCell Identification 0
678
0xFF4
SSIPCellID1
RO
0x0000.00F0
SSI PrimeCell Identification 1
679
0xFF8
SSIPCellID2
RO
0x0000.0005
SSI PrimeCell Identification 2
680
0xFFC
SSIPCellID3
RO
0x0000.00B1
SSI PrimeCell Identification 3
681
15.6
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
The SSICR0 register contains bit fields that control various functions within the SSI module.
Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
SPH
SPO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
SCR
Type
Reset
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:8
SCR
R/W
0x00
FRF
R/W
0
DSS
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Serial Clock Rate
This bit field is used to generate the transmit and receive bit rate of the
SSI. The bit rate is:
BR=SSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
7
SPH
R/W
0
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. This bit has the most impact on the first bit transmitted
by either allowing or not allowing a clock transition before the first data
capture edge.
Value Description
6
SPO
R/W
0
0
Data is captured on the first clock edge transition.
1
Data is captured on the second clock edge transition.
SSI Serial Clock Polarity
Value Description
0
A steady state Low value is placed on the SSIClk pin.
1
A steady state High value is placed on the SSIClk pin when
data is not being transferred.
May 24, 2010
655
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Bit/Field
Name
Type
Reset
5:4
FRF
R/W
0x0
Description
SSI Frame Format Select
Value Frame Format
3:0
DSS
R/W
0x0
0x0
Freescale SPI Frame Format
0x1
Texas Instruments Synchronous Serial Frame Format
0x2
MICROWIRE Frame Format
0x3
Reserved
SSI Data Size Select
Value
Data Size
0x0-0x2 Reserved
0x3
4-bit data
0x4
5-bit data
0x5
6-bit data
0x6
7-bit data
0x7
8-bit data
0x8
9-bit data
0x9
10-bit data
0xA
11-bit data
0xB
12-bit data
0xC
13-bit data
0xD
14-bit data
0xE
15-bit data
0xF
16-bit data
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 2: SSI Control 1 (SSICR1), offset 0x004
The SSICR1 register contains bit fields that control various functions within the SSI module. Master
and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
EOT
SOD
MS
SSE
LBM
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.0
4
EOT
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
End of Transmission
Value Description
3
SOD
R/W
0
0
The TXRIS interrupt indicates that the transmit FIFO is half full
or less.
1
The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
Value Description
2
MS
R/W
0
0
SSI can drive the SSITx output in Slave mode.
1
SSI must not drive the SSITx output in Slave mode.
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
the SSI is disabled (SSE=0).
Value Description
0
The SSI is configured as a master.
1
The SSI is configured as a slave.
May 24, 2010
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Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Bit/Field
Name
Type
Reset
1
SSE
R/W
0
Description
SSI Synchronous Serial Port Enable
Value Description
0
SSI operation is disabled.
1
SSI operation is enabled.
Note:
0
LBM
R/W
0
This bit must be cleared before any control registers
are reprogrammed.
SSI Loopback Mode
Value Description
0
Normal serial port operation enabled.
1
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
658
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 3: SSI Data (SSIDR), offset 0x008
Important: Use caution when reading this register. Performing a read may change bit status.
The SSIDR register is 16-bits wide. When the SSIDR register is read, the entry in the receive FIFO
that is pointed to by the current FIFO read pointer is accessed. When a data value is removed by
the SSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO
pointed to by the current FIFO write pointer.
When the SSIDR register is written to, the entry in the transmit FIFO that is pointed to by the write
pointer is written to. Data values are removed from the transmit FIFO one value at a time by the
transmit logic. Each data value is loaded into the transmit serial shifter, then serially shifted out onto
the SSITx pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is cleared, allowing the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
R/W
0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
May 24, 2010
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Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 4: SSI Status (SSISR), offset 0x00C
The SSISR register contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x00C
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BSY
RFF
RNE
TNF
TFE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.00
4
BSY
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Busy Bit
Value Description
3
RFF
RO
0
0
The SSI is idle.
1
The SSI is currently transmitting and/or receiving a frame, or
the transmit FIFO is not empty.
SSI Receive FIFO Full
Value Description
2
RNE
RO
0
0
The receive FIFO is not full.
1
The receive FIFO is full.
SSI Receive FIFO Not Empty
Value Description
1
TNF
RO
1
0
The receive FIFO is empty.
1
The receive FIFO is not empty.
SSI Transmit FIFO Not Full
Value Description
0
The transmit FIFO is full.
1
The transmit FIFO is not full.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
0
TFE
RO
1
Description
SSI Transmit FIFO Empty
Value Description
0
The transmit FIFO is not empty.
1
The transmit FIFO is empty.
May 24, 2010
661
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
The SSICPSR register specifies the division factor which is used to derive the SSIClk from the
system clock. The clock is further divided by a value from 1 to 256, which is 1 + SCR. SCR is
programmed in the SSICR0 register. The frequency of the SSIClk is defined by:
SSIClk = SysClk / (CPSDVSR * (1 + SCR))
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
CPSDVSR
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CPSDVSR
R/W
0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
662
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared on reset.
On a read, this register gives the current value of the mask on the corresponding interrupt. Setting
a bit sets the mask, preventing the interrupt from being signaled to the interrupt controller. Clearing
a bit clears the corresponding mask, enabling the interrupt to be sent to the interrupt controller.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
TXIM
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
TXIM
RXIM
RTIM
RORIM
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Interrupt Mask
Value Description
2
RXIM
R/W
0
0
The transmit FIFO interrupt is masked.
1
The transmit FIFO interrupt is not masked.
SSI Receive FIFO Interrupt Mask
Value Description
1
RTIM
R/W
0
0
The receive FIFO interrupt is masked.
1
The receive FIFO interrupt is not masked.
SSI Receive Time-Out Interrupt Mask
Value Description
0
RORIM
R/W
0
0
The receive FIFO time-out interrupt is masked.
1
The receive FIFO time-out interrupt is not masked.
SSI Receive Overrun Interrupt Mask
Value Description
0
The receive FIFO overrun interrupt is masked.
1
The receive FIFO overrun interrupt is not masked.
May 24, 2010
663
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x018
Type RO, reset 0x0000.0008
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TXRIS
RXRIS
RTRIS
RORRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
TXRIS
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Raw Interrupt Status
Value Description
0
No interrupt.
1
If the EOT bit in the SSICR1 register is clear, the transmit FIFO
is half full or less.
If the EOT bit is set, the transmit FIFO is empty, and the last bit
has been transmitted out of the serializer.
This bit is cleared when the transmit FIFO is more than half full (if the
EOT bit is clear) or when it has any data in it (if the EOT bit is set).
2
RXRIS
RO
0
SSI Receive FIFO Raw Interrupt Status
Value Description
0
No interrupt.
1
The receive FIFO is half full or more.
This bit is cleared when the receive FIFO is less than half full.
1
RTRIS
RO
0
SSI Receive Time-Out Raw Interrupt Status
Value Description
0
No interrupt.
1
The receive time-out has occurred.
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
0
RORRIS
RO
0
Description
SSI Receive Overrun Raw Interrupt Status
Value Description
0
No interrupt.
1
The receive FIFO has overflowed
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
May 24, 2010
665
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TXMIS
RXMIS
RTMIS
RORMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
TXMIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the transmit FIFO
being half full or less (if the EOT bit is clear) or due to the
transmission of the last data bit (if the EOT bit is set).
This bit is cleared when the transmit FIFO is more than half full (if the
EOT bit is clear) or when it has any data in it (if the EOT bit is set).
2
RXMIS
RO
0
SSI Receive FIFO Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receive FIFO
being half full or less.
This bit is cleared when the receive FIFO is less than half full.
1
RTMIS
RO
0
SSI Receive Time-Out Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receive time
out.
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
666
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
0
RORMIS
RO
0
Description
SSI Receive Overrun Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to the receive FIFO
overflowing.
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
May 24, 2010
667
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x020
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RTIC
RORIC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
W1C
0
W1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
RTIC
W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and
the RTMIS bit in the SSIMIS register.
0
RORIC
W1C
0
SSI Receive Overrun Interrupt Clear
Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register and
the RORMIS bit in the SSIMIS register.
668
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024
The SSIDMACTL register is the µDMA control register.
SSI DMA Control (SSIDMACTL)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
TXDMAE
R/W
0
TXDMAE RXDMAE
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit DMA Enable
Value Description
0
RXDMAE
R/W
0
0
µDMA for the transmit FIFO is disabled.
1
µDMA for the transmit FIFO is enabled.
Receive DMA Enable
Value Description
0
µDMA for the receive FIFO is disabled.
1
µDMA for the receive FIFO is enabled.
May 24, 2010
669
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID4
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
670
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID5
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID5
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
May 24, 2010
671
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID6
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID6
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
672
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID7
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID7
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
May 24, 2010
673
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE0
Type RO, reset 0x0000.0022
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x22
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
674
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID1
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
May 24, 2010
675
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID2
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x18
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
676
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
PID3
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x01
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
May 24, 2010
677
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
678
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
CID1
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
May 24, 2010
679
Texas Instruments-Advance Information
Synchronous Serial Interface (SSI)
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID2
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID2
RO
0x05
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
680
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID3
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID3
RO
0xB1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
May 24, 2010
681
Texas Instruments-Advance Information
Inter-Integrated Circuit (I2C) Interface
16
Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S5B91 microcontroller includes two I2C modules, providing the ability to
interact (both transmit and receive) with other I2C devices on the bus.
®
The Stellaris LM3S5B91 controller includes two I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
682
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
16.1
Block Diagram
Figure 16-1. I2C Block Diagram
I2CSCL
I2C Control
Interrupt
I2CMSA
I2CSOAR
I2CMCS
I2CSCSR
I2CMDR
I2CSDR
I2CMTPR
I2CSIM
I2CMIMR
I2CSRIS
I2CMRIS
I2CSMIS
I2CMMIS
I2CSICR
I2C Master Core
I2CSDA
I2CSCL
I2C I/O Select
I2CSDA
I2CSCL
I2C Slave Core
I2CMICR
I2CSDA
I2CMCR
16.2
Signal Description
Table 16-1 on page 683 and Table 16-2 on page 683 list the external signals of the I2C interface and
describe the function of each. The I2C interface signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset., with the exception of the I2C0SCL and I2CSDA pins which
default to the I2C function. The column in the table below titled "Pin Mux/Pin Assignment" lists the
possible GPIO pin placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 323) should be set to choose the I2C function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 341) to assign the I2C signal to the specified GPIO port pin. Note that
the I2C pins should be set to open drain using the GPIO Open Drain Select (GPIOODR) register.
For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 298.
Table 16-1. Signals for I2C (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
I2C0SCL
72
PB2 (1)
I/O
OD
I2C module 0 clock.
I2C0SDA
65
PB3 (1)
I/O
OD
I2C module 0 data.
I2C1SCL
14
19
26
34
PJ0 (11)
PG0 (3)
PA0 (8)
PA6 (1)
I/O
OD
I2C module 1 clock.
I2C1SDA
18
27
35
87
PG1 (3)
PA1 (8)
PA7 (1)
PJ1 (11)
I/O
OD
I2C module 1 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 16-2. Signals for I2C (108BGA)
Pin Name
I2C0SCL
Pin Number Pin Mux / Pin
Assignment
A11
PB2 (1)
a
Pin Type
Buffer Type
I/O
OD
Description
I2C module 0 clock.
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Table 16-2. Signals for I2C (108BGA) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
I2C0SDA
E11
PB3 (1)
I/O
OD
I2C module 0 data.
I2C1SCL
F3
K1
L3
L6
PJ0 (11)
PG0 (3)
PA0 (8)
PA6 (1)
I/O
OD
I2C module 1 clock.
I2C1SDA
K2
M3
M6
B6
PG1 (3)
PA1 (8)
PA7 (1)
PJ1 (11)
I/O
OD
I2C module 1 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
16.3
Functional Description
Each I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 16-2.
See “Inter-Integrated Circuit (I2C) Interface” on page 1159 for I2C timing diagrams.
Figure 16-2. I2C Bus Configuration
RPUP
SCL
SDA
I2C Bus
I2CSCL
I2CSDA
Stellaris®
16.3.1
RPUP
SCL
SDA
3rd Party Device
with I2C Interface
SCL
SDA
3rd Party Device
with I2C Interface
I2C Bus Functional Overview
®
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 684) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
16.3.1.1
START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
16-3.
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Figure 16-3. START and STOP Conditions
SDA
SDA
SCL
SCL
START
condition
STOP
condition
The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated
START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and the Control register is written
with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the
operation is completed (or aborted due an error), the interrupt pin becomes active and the data may
be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the
ACK bit is nornally set causing the I2C bus controller to transmit an acknowledge automatically after
each byte. This bit must be cleared when the I2C bus controller requires no further data to be
transmitted from the slave transmitter.
When operating in slave mode, two bits in the I2CSRIS register indicate detection of start and stop
conditions on the bus; while two bits in the I2CSMIS register allow start and stop conditions to be
promoted to controller interrupts (when interrupts are enabled).
16.3.1.2
Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 16-4. After the START condition, a slave address
is transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S
bit in the I2CMSA register). If the R/S bit is clear, it indicates a transmit operation (send), and if it
is set, it indicates a request for data (receive). A data transfer is always terminated by a STOP
condition generated by the master, however, a master can initiate communications with another
device on the bus by generating a repeated START condition and addressing another slave without
first generating a STOP condition. Various combinations of receive/transmit formats are then possible
within a single transfer.
Figure 16-4. Complete Data Transfer with a 7-Bit Address
SDA
MSB
SCL
1
Start
2
LSB
R/S
ACK
7
8
9
MSB
1
2
Slave address
7
Data
LSB
ACK
8
9
Stop
The first seven bits of the first byte make up the slave address (see Figure 16-5). The eighth bit
determines the direction of the message. A zero in the R/S position of the first byte means that the
master transmits (sends) data to the selected slave, and a one in this position means that the master
receives data from the slave.
Figure 16-5. R/S Bit in First Byte
MSB
LSB
R/S
Slave address
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16.3.1.3
Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 16-6).
Figure 16-6. Data Validity During Bit Transfer on the I2C Bus
SDA
SCL
Data line Change
stable
of data
allowed
16.3.1.4
Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data transmitted out by the receiver during the acknowledge cycle must comply with the
data validity requirements described in “Data Validity” on page 686.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Because the master controls the number of bytes in the transfer, it signals the
end of data to the slave transmitter by not generating an acknowledge on the last data byte. The
slave transmitter must then release SDA to allow the master to generate the STOP or a repeated
START condition.
16.3.1.5
Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a '1' (High) on SDA while another master transmits a '0'
(Low) switches off its data output stage and retires until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
16.3.2
Available Speed Modes
The I2C bus can run in either Standard mode (100 kbps) or Fast mode (400 kbps). The selected
mode should match the speed of the other I2C devices on the bus. The mode is selected by using
a value in the I2C Master Timer Period (I2CMTPR) register that results in an SCL frequency of 100
kbps for Standard mode or 400 kbps for Fast mode.
The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
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TIMER_PRD is the programmed value in the I2CMTPR register (see page 705).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/SCL_PERIOD = 333 Khz
Table 16-3 gives examples of the timer periods that should be used to generate both Standard and
Fast mode SCL frequencies based on various system clock frequencies.
Table 16-3. Examples of I2C Master Timer Period versus Speed Mode
16.3.3
System Clock
Timer Period
Standard Mode
Timer Period
Fast Mode
4 MHz
0x01
100 Kbps
-
-
6 MHz
0x02
100 Kbps
-
-
12.5 MHz
0x06
89 Kbps
0x01
312 Kbps
16.7 MHz
0x08
93 Kbps
0x02
278 Kbps
20 MHz
0x09
100 Kbps
0x02
333 Kbps
25 MHz
0x0C
96.2 Kbps
0x03
312 Kbps
33 MHz
0x10
97.1 Kbps
0x04
330 Kbps
40 MHz
0x13
100 Kbps
0x04
400 Kbps
50 MHz
0x18
100 Kbps
0x06
357 Kbps
80 MHz
0x27
100 Kbps
0x09
400 Kbps
Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
■ Stop condition on bus detected
■ Start condition on bus detected
The I2C master and I2C slave modules have separate interrupt signals. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
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16.3.3.1
I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software
must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledged by the slave, or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in the I2C Master
Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
16.3.3.2
I2C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by setting the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register. Software
determines whether the module should write (transmit) or read (receive) data from the I2C Slave
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by setting the DATAIC bit in the
I2C Slave Interrupt Clear (I2CSICR) register.
In addition, the slave module can generate an interrupt when a start and stop condition is detected.
These interrupts are enabled by setting the STARTIM and STOPIM bits of the I2C Slave Interrupt
Mask (I2CSIMR) register and cleared by writing a 1 to the STOPIC and STARTIC bits of the I2C
Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
16.3.4
Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work by
setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the
SDA and SCL signals from the master and slave modules are tied together.
16.3.5
Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
16.3.5.1
I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
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Figure 16-7. Master Single TRANSMIT
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Write data to
I2CMDR
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---0-111
to I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 16-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Sequence may be
omitted in a Single
Master system
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---00111
to I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Read data from
I2CMDR
Idle
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Figure 16-9. Master TRANSMIT with Repeated START
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
Write data to
I2CMDR
BUSY bit=0?
YES
Read I2CMCS
ERROR bit=0?
NO
NO
NO
BUSBSY bit=0?
YES
Write data to
I2CMDR
YES
Write ---0-011
to I2CMCS
NO
ARBLST bit=1?
YES
Write ---0-001
to I2CMCS
NO
Index=n?
YES
Write ---0-101
to I2CMCS
Write ---0-100
to I2CMCS
Error Service
Idle
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 16-10. Master RECEIVE with Repeated START
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
BUSY bit=0?
Read I2CMCS
NO
YES
NO
BUSBSY bit=0?
ERROR bit=0?
NO
YES
Write ---01011
to I2CMCS
NO
Read data from
I2CMDR
ARBLST bit=1?
YES
Write ---01001
to I2CMCS
NO
Write ---0-100
to I2CMCS
Index=m-1?
Error Service
YES
Write ---00101
to I2CMCS
Idle
Read I2CMCS
BUSY bit=0?
NO
YES
NO
ERROR bit=0?
YES
Error Service
Read data from
I2CMDR
Idle
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Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated START
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011
to I2CMCS
Master operates in
Master Receive mode
Repeated START
condition is generated
with changing data
direction
Idle
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Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated START
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011
to I2CMCS
Master operates in
Master Transmit mode
Repeated START
condition is generated
with changing data
direction
Idle
16.3.5.2
I2C Slave Command Sequences
Figure 16-13 on page 695 presents the command sequence available for the I2C slave.
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Figure 16-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1
to I2CSCSR
Read I2CSCSR
NO
TREQ bit=1?
YES
Write data to
I2CSDR
16.4
NO
RREQ bit=1?
FBR is
also valid
YES
Read data from
I2CSDR
Initialization and Configuration
The following example shows how to configure the I2C module to transmit a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module (see page 179).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module (see page 191). To find out which GPIO port to enable, refer to Table 24-5 on page 1097.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 323). To determine which GPIOs to configure, see Table
24-4 on page 1088.
4. Enable the I2C pins for Open Drain operation. See page 328.
5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate
pins. See page 341 and Table 24-5 on page 1097.
6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010.
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7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (20MHz/(2*(6+4)*100000))-1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
8. Specify the slave address of the master and that the next operation is a Transmit by writing the
I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
9. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the
desired data.
10. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register
with a value of 0x0000.0007 (STOP, START, RUN).
11. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
16.5
Register Map
Table 16-4 on page 696 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■
■
■
■
I2C Master 0: 0x4002.0000
I2C Slave 0: 0x4002.0800
I2C Master 1: 0x4002.1000
I2C Slave 1: 0x4002.1800
Note that the I2C module clock must be enabled before the registers can be programmed (see
page 179).
Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map
Offset
Description
See
page
Name
Type
Reset
0x000
I2CMSA
R/W
0x0000.0000
I2C Master Slave Address
698
0x004
I2CMCS
R/W
0x0000.0000
I2C Master Control/Status
699
0x008
I2CMDR
R/W
0x0000.0000
I2C Master Data
704
0x00C
I2CMTPR
R/W
0x0000.0001
I2C Master Timer Period
705
0x010
I2CMIMR
R/W
0x0000.0000
I2C Master Interrupt Mask
706
0x014
I2CMRIS
RO
0x0000.0000
I2C Master Raw Interrupt Status
707
0x018
I2CMMIS
RO
0x0000.0000
I2C Master Masked Interrupt Status
708
0x01C
I2CMICR
WO
0x0000.0000
I2C Master Interrupt Clear
709
0x020
I2CMCR
R/W
0x0000.0000
I2C Master Configuration
710
I2C Master
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Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued)
Offset
Description
See
page
Name
Type
Reset
0x000
I2CSOAR
R/W
0x0000.0000
I2C Slave Own Address
711
0x004
I2CSCSR
RO
0x0000.0000
I2C Slave Control/Status
712
0x008
I2CSDR
R/W
0x0000.0000
I2C Slave Data
714
0x00C
I2CSIMR
R/W
0x0000.0000
I2C Slave Interrupt Mask
715
0x010
I2CSRIS
RO
0x0000.0000
I2C Slave Raw Interrupt Status
716
0x014
I2CSMIS
RO
0x0000.0000
I2C Slave Masked Interrupt Status
717
0x018
I2CSICR
WO
0x0000.0000
I2C Slave Interrupt Clear
718
I2C Slave
16.6
Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 710.
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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Transmit (Low).
I2C Master Slave Address (I2CMSA)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
SA
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:1
SA
R/W
0x00
R/S
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
0
R/S
R/W
0
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Transmit
(Low).
Value Description
0
Transmit
1
Receive
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses seven status bits when read and four control bits when written.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit
generates the START or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated
START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and the Control register is written
with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the
operation is completed (or aborted due an error), the interrupt pin becomes active and the data may
be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the
ACK bit is nornally set causing the I2C bus controller to transmit an acknowledge automatically after
each byte. This bit must be cleared when the I2C bus controller requires no further data to be
transmitted from the slave transmitter.
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BUSBSY
IDLE
ARBLST
ERROR
BUSY
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6
BUSBSY
RO
0
DATACK ADRACK
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bus Busy
Value Description
0
The I2C bus is idle.
1
The I2C bus is busy.
The bit changes based on the START and STOP conditions.
5
IDLE
RO
0
I2C Idle
Value Description
0
The I2C controller is not idle.
1
The I2C controller is idle.
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Bit/Field
Name
Type
Reset
4
ARBLST
RO
0
Description
Arbitration Lost
Value Description
3
DATACK
RO
0
0
The I2C controller won arbitration.
1
The I2C controller lost arbitration.
Acknowledge Data
Value Description
2
ADRACK
RO
0
0
The transmitted data was acknowledged
1
The transmitted data was not acknowledged.
Acknowledge Address
Value Description
1
ERROR
RO
0
0
The transmitted address was acknowledged
1
The transmitted address was not acknowledged.
Error
Value Description
0
No error was detected on the last operation.
1
An error occurred on the last operation.
The error can be from the slave address not being acknowledged, the
transmit data not being acknowledged, or because the controller lost
arbitration.
0
BUSY
RO
0
I2C Busy
Value Description
0
The controller is idle.
1
The controller is busy.
When the BUSY bit is set, the other status bits are not valid.
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Stellaris® LM3S5B91 Microcontroller
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
8
7
6
5
4
3
2
1
0
ACK
STOP
START
RUN
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
WO
0x0000.000
3
ACK
WO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data Acknowledge Enable
Value Description
2
STOP
WO
0
0
The received data byte is not acknowledged automatically by
the master.
1
The received data byte is acknowledged automatically by the
master. See field decoding in Table 16-5 on page 702.
Generate STOP
Value Description
1
START
WO
0
0
The controller does not generate the STOP condition.
1
The controller generates the STOP condition. See field decoding
in Table 16-5 on page 702.
Generate START
Value Description
0
RUN
WO
0
0
The controller does not generate the START condition.
1
The controller generates the START or repeated START
condition. See field decoding in Table 16-5 on page 702.
I2C Master Enable
Value Description
0
The master is disabled.
1
The master is enabled to transmit or receive data. See field
decoding in Table 16-5 on page 702.
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Inter-Integrated Circuit (I2C) Interface
Table 16-5. Write Field Decoding for I2CMCS[3:0] Field
Current I2CMSA[0]
State
R/S
Idle
I2CMCS[3:0]
ACK
Description
STOP
START
RUN
0
X
a
0
1
1
START condition followed by TRANSMIT (master goes
to the Master Transmit state).
0
X
1
1
1
START condition followed by a TRANSMIT and STOP
condition (master remains in Idle state).
1
0
0
1
1
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1
0
1
1
1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1
1
0
1
1
START condition followed by RECEIVE (master goes to
the Master Receive state).
1
1
1
1
1
Illegal
All other combinations not listed are non-operations.
Master
Transmit
NOP
X
X
0
0
1
TRANSMIT operation (master remains in Master
Transmit state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
X
1
0
1
TRANSMIT followed by STOP condition (master goes
to Idle state).
0
X
0
1
1
Repeated START condition followed by a TRANSMIT
(master remains in Master Transmit state).
0
X
1
1
1
Repeated START condition followed by TRANSMIT and
STOP condition (master goes to Idle state).
1
0
0
1
1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1
0
1
1
1
Repeated START condition followed by a TRANSMIT
and STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE
(master goes to Master Receive state).
1
1
1
1
1
Illegal.
All other combinations not listed are non-operations.
NOP.
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Stellaris® LM3S5B91 Microcontroller
Table 16-5. Write Field Decoding for I2CMCS[3:0] Field (continued)
Current I2CMSA[0]
State
R/S
Master
Receive
I2CMCS[3:0]
Description
ACK
STOP
START
RUN
X
0
0
0
1
RECEIVE operation with negative ACK (master remains
in Master Receive state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
0
1
0
1
RECEIVE followed by STOP condition (master goes to
Idle state).
X
1
0
0
1
RECEIVE operation (master remains in Master Receive
state).
X
1
1
0
1
Illegal.
1
0
0
1
1
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1
0
1
1
1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
0
X
0
1
1
Repeated START condition followed by TRANSMIT
(master goes to Master Transmit state).
0
X
1
1
1
Repeated START condition followed by TRANSMIT and
STOP condition (master goes to Idle state).
All other combinations not listed are non-operations.
b
NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Inter-Integrated Circuit (I2C) Interface
Register 3: I2C Master Data (I2CMDR), offset 0x008
Important: Use caution when reading this register. Performing a read may change bit status.
This register contains the data to be transmitted when in the Master Transmit state and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
DATA
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DATA
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data Transferred
Data transferred during transaction.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur.
I2C Master Timer Period (I2CMTPR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x00C
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
TPR
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6:0
TPR
R/W
0x1
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2×(1 + TPR)×(SCL_LP + SCL_HP)×CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
CLK_PRD is the system clock period in ns.
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Inter-Integrated Circuit (I2C) Interface
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
IM
R/W
0
RO
0
IM
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Mask
Value Description
1
The master interrupt is sent to the interrupt controller when the
RIS bit in the I2CMRIS register is set.
0
The RIS interrupt is suppressed and not sent to the interrupt
controller.
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Stellaris® LM3S5B91 Microcontroller
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
RIS
RO
0
RO
0
RIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Raw Interrupt Status
Value Description
1
A master interrupt is pending.
0
No interrupt.
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
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Inter-Integrated Circuit (I2C) Interface
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
MIS
RO
0
RO
0
MIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Masked Interrupt Status
Value Description
1
An unmasked master interrupt was signaled is pending.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x01C
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
IC
WO
0
RO
0
IC
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Clear
Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the
MIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
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Inter-Integrated Circuit (I2C) Interface
Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
SFE
MFE
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5
SFE
R/W
0
reserved
RO
0
RO
0
LPBK
RO
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave Function Enable
Value Description
4
MFE
R/W
0
1
Slave mode is enabled.
0
Slave mode is disabled.
I2C Master Function Enable
Value Description
3:1
reserved
RO
0x0
0
LPBK
R/W
0
1
Master mode is enabled.
0
Master mode is disabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Loopback
Value Description
16.7
1
The controller in a test mode loopback configuration.
0
Normal operation.
Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 697.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000
®
This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
OAR
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6:0
OAR
R/W
0x00
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
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Inter-Integrated Circuit (I2C) Interface
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First Byte
®
Received (FBR) bit is set only after the Stellaris device detects its own slave address and receives
®
the first data byte from the I2C master. The Receive Request (RREQ) bit indicates that the Stellaris
I2C device has received a data byte from an I2C master. Read one data byte from the I2C Slave
Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit indicates that the
®
Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte into the I2C Slave
Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
®
Stellaris I2C slave operation.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FBR
TREQ
RREQ
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
FBR
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
First Byte Received
Value Description
1
The first byte following the slave’s own address has been
received.
0
The first byte has not been received.
This bit is only valid when the RREQ bit is set and is automatically cleared
when data has been read from the I2CSDR register.
Note:
1
TREQ
RO
0
This bit is not used for slave transmit operations.
Transmit Request
Value Description
1
The I2C controller has been addressed as a slave transmitter
and is using clock stretching to delay the master until data has
been written to the I2CSDR register.
0
No outstanding transmit request.
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Bit/Field
Name
Type
Reset
0
RREQ
RO
0
Description
Receive Request
Value Description
1
The I2C controller has outstanding receive data from the I2C
master and is using clock stretching to delay the master until
the data has been read from the I2CSDR register.
0
No outstanding receive data.
Write-Only Control Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
DA
WO
0
RO
0
DA
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Active
Value Description
0
Disables the I2C slave operation.
1
Enables the I2C slave operation.
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Inter-Integrated Circuit (I2C) Interface
Register 12: I2C Slave Data (I2CSDR), offset 0x008
Important: Use caution when reading this register. Performing a read may change bit status.
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
DATA
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DATA
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
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Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
STOPIM
RO
0
STOPIM STARTIM DATAIM
RO
0
RO
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stop Condition Interrupt Mask
Value Description
1
STARTIM
RO
0
1
The STOP condition interrupt is sent to the interrupt controller
when the STOPRIS bit in the I2CSRIS register is set.
0
The STOPRIS interrupt is suppressed and not sent to the
interrupt controller.
Start Condition Interrupt Mask
Value Description
0
DATAIM
R/W
0
1
The START condition interrupt is sent to the interrupt controller
when the STARTRIS bit in the I2CSRIS register is set.
0
The STARTRIS interrupt is suppressed and not sent to the
interrupt controller.
Data Interrupt Mask
Value Description
1
The data received or data requested interrupt is sent to the
interrupt controller when the DATARIS bit in the I2CSRIS register
is set.
0
The DATARIS interrupt is suppressed and not sent to the
interrupt controller.
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Inter-Integrated Circuit (I2C) Interface
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
STOPRIS
RO
0
STOPRIS STARTRIS DATARIS
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stop Condition Raw Interrupt Status
Value Description
1
A STOP condition interrupt is pending.
0
No interrupt.
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
1
STARTRIS
RO
0
Start Condition Raw Interrupt Status
Value Description
1
A START condition interrupt is pending.
0
No interrupt.
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0
DATARIS
RO
0
Data Raw Interrupt Status
Value Description
1
A data received or data requested interrupt is pending.
0
No interrupt.
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
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Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
STOPMIS
R/W
0
STOPMIS STARTMIS DATAMIS
R/W
0
R/W
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stop Condition Masked Interrupt Status
Value Description
1
An unmasked STOP condition interrupt was signaled is pending.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
1
STARTMIS
R/W
0
Start Condition Masked Interrupt Status
Value Description
1
An unmasked START condition interrupt was signaled is
pending.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0
DATAMIS
RO
0
Data Masked Interrupt Status
Value Description
1
An unmasked data received or data requested interrupt was
signaled is pending.
0
An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
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Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x018
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
STOPIC
WO
0
STOPIC STARTIC
WO
0
WO
0
DATAIC
WO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stop Condition Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register
and the STOPMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
1
STARTIC
WO
0
Start Condition Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register
and the STOPMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
0
DATAIC
WO
0
Data Interrupt Clear
Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register
and the STOPMIS bit in the I2CSMIS register.
A read of this register returns no meaningful data.
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Stellaris® LM3S5B91 Microcontroller
17
Inter-Integrated Circuit Sound (I2S) Interface
The I2S module is a configurable serial audio core that contains a transmit module and a receive
module. The module is configurable for the I2S as well as Left-Justified and Right-Justified serial
audio formats. Data can be in one of four modes: Stereo, Mono, Compact 16-bit Stereo and Compact
8-Bit Stereo.
The transmit and receive modules each have an 8-entry audio-sample FIFO. An audio sample can
consist of a Left and Right Stereo sample, a Mono sample, or a Left and Right Compact Stereo
sample. In Compact 16-Bit Stereo, each FIFO entry contains both the 16-bit left and 16-bit right
samples, allowing efficient data transfers and requiring less memory space. In Compact 8-bit Stereo,
each FIFO entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements
further.
Both the transmitter and receiver are capable of being a master or a slave.
®
The Stellaris I2S module has the following features:
■ Configurable audio format supporting I2S, Left-justification, and Right-justification
■ Configurable sample size from 8 to 32 bits
■ Mono and Stereo support
■ 8-, 16-, and 32-bit FIFO interface for packing memory
■ Independent transmit and receive 8-entry FIFOs
■ Configurable FIFO-level interrupt and µDMA requests
■ Independent transmit and receive MCLK direction control
■ Transmit and receive internal MCLK sources
■ Independent transmit and receive control for serial clock and word select
■ MCLK and SCLK can be independently set to master or slave
■ Configurable transmit zero or last sample when FIFO empty
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Burst requests
– Channel requests asserted when FIFO contains required amount of data
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Inter-Integrated Circuit Sound (I2S) Interface
17.1
Block Diagram
Figure 17-1. I2S Block Diagram
I2S0TXMCLK
I2STXCFG
Transmit FIFO
8 entry
SysClk
I2STXFIFO
I2S0TXSCK
BitClk/WdSel
Generation
I2S0TXWS
I2STXFIFOCFG
System
AHB Bus
I2STXLIMIT
Serial
Encoder
I2STXSD
I2STXLEV
Registers
I2SCFG
Interrupts/
DMA
I2STXISM
Transmit FIFO
I2SIC
I2SRIS
I2SMIS
I2SRXCFG
I2SIM
I2S0RXMCLK
Receive FIFO
8 entry
I2SRXFIFO
I2S0RXSCK
BitClk/WdSel
Generation
I2S0RXWS
I2SRXFIFOCFG
I2SRXLIMIT
Serial
Decoder
I2SRXSD
I2SRXLEV
Receive FIFO
I2SRXISM
17.2
Signal Description
Table 17-1 on page 721 and Table 17-2 on page 721 list the external signals of the I2S module and
describe the function of each. The I2S module signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment"
lists the possible GPIO pin placements for the I2S signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 323) should be set to choose the I2S function. The
number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO
Port Control (GPIOPCTL) register (page 341) to assign the I2S signal to the specified GPIO port
pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 298.
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Table 17-1. Signals for I2S (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
I2S0RXMCLK
16
29
98
PG3 (9)
PA3 (9)
PD5 (8)
I/O
TTL
I2S module 0 receive master clock.
I2S0RXSCK
10
40
PD0 (8)
PG5 (9)
I/O
TTL
I2S module 0 receive clock.
I2S0RXSD
17
28
97
PG2 (9)
PA2 (9)
PD4 (8)
I/O
TTL
I2S module 0 receive data.
I2S0RXWS
11
37
PD1 (8)
PG6 (9)
I/O
TTL
I2S module 0 receive word select.
I2S0TXMCLK
43
61
PF6 (9)
PF1 (8)
I/O
TTL
I2S module 0 transmit master clock.
I2S0TXSCK
30
90
99
PA4 (9)
PB6 (9)
PD6 (8)
I/O
TTL
I2S module 0 transmit clock.
I2S0TXSD
5
47
PE5 (9)
PF0 (8)
I/O
TTL
I2S module 0 transmit data.
I2S0TXWS
6
31
100
PE4 (9)
PA5 (9)
PD7 (8)
I/O
TTL
I2S module 0 transmit word select.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 17-2. Signals for I2S (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
I2S0RXMCLK
J2
L4
C6
PG3 (9)
PA3 (9)
PD5 (8)
I/O
TTL
I2S module 0 receive master clock.
I2S0RXSCK
G1
M7
PD0 (8)
PG5 (9)
I/O
TTL
I2S module 0 receive clock.
I2S0RXSD
J1
M4
B5
PG2 (9)
PA2 (9)
PD4 (8)
I/O
TTL
I2S module 0 receive data.
I2S0RXWS
G2
L7
PD1 (8)
PG6 (9)
I/O
TTL
I2S module 0 receive word select.
I2S0TXMCLK
M8
H12
PF6 (9)
PF1 (8)
I/O
TTL
I2S module 0 transmit master clock.
I2S0TXSCK
L5
A7
A3
PA4 (9)
PB6 (9)
PD6 (8)
I/O
TTL
I2S module 0 transmit clock.
I2S0TXSD
B3
M9
PE5 (9)
PF0 (8)
I/O
TTL
I2S module 0 transmit data.
I2S0TXWS
B2
M5
A2
PE4 (9)
PA5 (9)
PD7 (8)
I/O
TTL
I2S module 0 transmit word select.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
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Inter-Integrated Circuit Sound (I2S) Interface
17.3
Functional Description
The Inter-Integrated Circuit Sound (I2S) module contains separate transmit and receive engines.
Each engine consists of the following:
■ Serial encoder for the transmitter; serial decoder for the receiver
■ 8-entry FIFO to store sample data
■ Independent configuration of all programmable settings
The basic programming model of the I2S block is as follows:
■ Configuration
– Overall I2S module configuration in the I2S Module Configuration (I2SCFG) register. This
register is used to select the MCLK source and enable the receiver and transmitter.
– Transmit and receive configuration in the I2S Transmit Module Configuration (I2STXCFG)
and I2S Receive Module Configuration (I2SRXCFG) registers. These registers set the basic
parameters for the receiver and transmitter such as data configuration (justification, delay,
read mode, sample size, and system data size); SCLK (polarity and source); and word select
polarity.
– Transmit and receive FIFO configuration in the I2S Transmit FIFO Configuration
(I2STXFIFOCFG) and I2S Receive FIFO Configuration (I2SRXFIFOCFG) registers. These
registers select the Compact Stereo mode size (16-bit or 8-bit), provide indication of whether
the next sample is Left or Right, and select mono mode for the receiver.
■ FIFO
– Transmit and receive FIFO data in the I2S Transmit FIFO Data (I2STXFIFO) and I2S Receive
FIFO Data (I2SRXFIFO) registers
– Information on FIFO data levels in the I2S Transmit FIFO Level (I2STXLEV) and I2S Receive
FIFO Level (I2SRXLEV) registers
– Configuration for FIFO service requests based on FIFO levels in the I2S Transmit FIFO Limit
(I2STXLIMIT) and I2S Receive FIFO Limit (I2SRXLIM) registers
■ Interrupt Control
– Interrupt masking configuration in the I2S Interrupt Mask (I2SIM) register
– Raw and masked interrupt status in the I2S Raw Interrupt Status (I2SRIS) and I2S Masked
Interrupt Status (I2SMIS) registers
– Interrupt clearing through the I2S Interrupt Clear (I2SIC) register
– Configuration for FIFO service requests interrupts and transmit/receive error interrupts in the
I2S Transmit Interrupt Status and Mask (I2STXISM) and I2S Receive Interrupt Status
and Mask (I2SRXISM) registers
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Figure 17-2 on page 723 provides an example of an I2S data transfer. Figure 17-3 on page 723
provides an example of an Left-Justified data transfer. Figure 17-4 on page 723 provides an example
of an Right-Justified data transfer.
Figure 17-2. I2S Data Transfer
SCK
Word Select
Serial Data
MSB
LSB
WORD n-1
RIGHT
CHANNEL
MSB
WORD n+1
RIGHT
CHANNEL
WORD n
LEFT
CHANNEL
Figure 17-3. Left-Justified Data Transfer
System Data Size
Right Channel
Word
Select
Left Channel
SCLK
Serial
Data
MSB -1
-2
-3
-4 -5
+5
+4
+3
+2
+1 LSB
MSB -1
-2
-3
-4
+5
+4
+3
+2
+5
+4
+1 LSB
Sample Size
Figure 17-4. Right-Justified Data Transfer
System Data Size
Word
Select
Right Channel
Left Channel
SCLK
Serial 0
Data
MSB
-1
-2
-3
-4
-5
+7
+6
+5
+4
+3
+2
+1 LSB
MSB
-1
-2
-3
-4
-5
+7
+6
+3
+2
+1 LSB
Sample Size
17.3.1
Transmit
The transmitter consists of a serial encoder, an 8-entry FIFO, and control logic. The transmitter has
independent MCLK (I2S0TXMCLK), SCLK (I2S0TXSCK), and Word-Select (I2S0TXWS) signals.
17.3.1.1
Serial Encoder
The serial encoder reads audio samples from the receive FIFO and converts them into an audio
stream. By configuring the serial encoder, common audio formats I2S, Left-Justified, and
Right-Justified are supported. The MSB is transmitted first. The sample size and system data size
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Inter-Integrated Circuit Sound (I2S) Interface
are configurable with the SSZ and SDSZ bits in the I2S Transmit Module Configuration (I2STXCFG)
register. The sample size is the number of bits of data being transmitted, and the system data size
is the number of I2S0TXSCK transitions between the word select transitions. The system data size
must be large enough to accommodate the maximum sample size. In Mono mode, the sample data
is repeated in both the left and right channels. When the FIFO is empty, the user may select either
transmission of zeros or of the last sample. The serial encoder is enabled using the TXEN bit in the
I2S Module Configuration (I2SCFG) register.
17.3.1.2
FIFO Operation
The transmit FIFO stores eight Mono samples or eight Stereo sample-pairs of data and is accessed
through the I2S Transmit FIFO Data (I2STXFIFO) register. The FIFO interface for the audio data
is different based on the Write mode, defined by the I2S Transmit FIFO Configuration
(I2STXFIFOCFG) Compact Stereo Sample Size bit (CSS) and the I2STXCFG Write Mode field (WM).
All data samples are MSB-aligned. Table 17-3 on page 724 defines the interface for each Write mode.
Stereo samples are written first left then right. The next sample (right or left) to be written is indicated
by the LRS bit in the I2STXFIFOCFG register.
Table 17-3. I2S Transmit FIFO Interface
WM field in
I2STXCFG
CSS bit in
I2STXFIFOCFG
0x0
don't care
0x1
Write Mode
Sample Width
Samples per
FIFO Write
Data Alignment
Stereo
8-32 bits
1
MSB
0
Compact Stereo - 16 bit
8-16 bits
2
MSB Right [31:16], Left
[15:0]
0x1
1
Compact Stereo - 8 bit
8 bits
2
Right [15:8], Left[7:0]
0x2
don't care
8-32 bits
1
MSB
Mono
The number of samples in the transmit FIFO can be read using the I2S Transmit FIFO Level
(I2STXLEV) register. The value ranges from 0 to 16. Stereo and compact stereo sample pairs are
counted as two. The mono samples also increment the count by two, therefore, four mono samples
will have a count of eight.
17.3.1.3
Clock Control
The transmitter MCLK and SCLK can be independently programmed to be the master or slave. The
transmitter is programmed to be the master or slave of the SCLK using the MSL bit in the I2STXCFG
register. When the transmitter is the master, the I2S0TXSCK frequency is the specified I2S0TXMCLK
divided by four. The I2S0TXSCK may be inverted using the SCP bit in the I2STXCFG register.
The transmitter can also be the master or slave of the MCLK. When the transmitter is the master,
the PLL must be active and a fractional clock divider must be programmed. See page 142 for the
setup for the master I2S0TXMCLK source. An external transmit I2S0TXMCLK does not require the
use of the PLL and is selected using the TXSLV bit in the I2SCFG register.
The following tables show combinations of the TXINT and TXFRAC bits in the I2S MCLK
Configuration (I2SMCLKCFG) register that provide MCLK frequencies within acceptable error
limits. In the table, Fs is the sampling frequency in kHz and possible crystal frequencies are shown
in MHz across the top row of the table. The words "not supported" in the table mean that it is not
possible to obtain the specified sampling frequencies with the specified crystal frequency within the
error tolerance of 0.3%. The values in the table are based on the following values:
MCLK = Fs × 256 PLL = 400 MHz
The Integer value is taken from the result of the following calculation:
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ROUND(PLL/MCLK)
The remaining fractional component is converted to binary, and the first four bits are the Fractional
value.
Table 17-4. Crystal Frequency (Values from 3.5795 MHz to 5 MHz)
Sampling
Frequency
Fs (kHz)
Crystal Frequency (MHz)
3.5795
3.6864
4
4.096
4.9152
5
Integer Fractional Integer Fractional Integer Fractional Integer Fractional Integer Fractional Integer Fractional
8
195
12
194
6
195
5
196
11.025
142
1
12
130
8
16
97
22.05
24
0
194
6
195
5
141
1
141
12
129
10
130
3
142
4
130
11
141
1
141
12
129
10
130
3
14
97
3
97
10
98
0
97
3
97
10
71
0
70
8
65
4
64
13
70
14
65
2
71
2
70
8
70
14
65
5
64
13
65
2
32
48
15
48
10
48
13
49
0
48
10
48
13
44.1
35
8
35
4
35
7
35
9
35
4
35
7
48
32
10
32
6
32
9
32
11
32
6
32
9
64
24
8
24
5
24
7
24
8
24
5
24
7
88.2
17
12
17
10
17
11
17
12
17
10
17
11
96
16
5
16
3
16
4
16
5
16
3
16
4
128
12
4
12
2
12
3
12
4
12
2
12
3
8
14
8
13
8
14
8
14
8
13
8
14
8
2
8
3
Not supported
8
2
176.4
192
Not supported
Not supported
Table 17-5. Crystal Frequency (Values from 5.12 MHz to 8.192 MHz)
Sampling
Frequency
Fs (kHz)
Crystal Frequency (MHz)
5.12
6
6.144
7.3728
8
8.192
Integer Fractional Integer Fractional Integer Fractional Integer Fractional Integer Fractional Integer Fractional
8
195
0
195
5
195
0
194
6
195
5
194
11
11.025
141
8
141
12
141
8
141
1
141
12
141
4
12
130
0
130
3
130
0
129
10
130
3
129
12
16
97
8
97
10
97
8
97
3
97
10
97
5
22.05
70
12
70
14
70
12
70
8
70
14
70
10
24
65
0
65
2
65
0
64
13
65
2
64
14
32
48
12
48
13
48
12
48
10
48
13
48
11
44.1
35
6
35
7
35
6
35
4
35
7
35
5
48
32
8
32
9
32
8
32
6
32
9
32
7
64
24
6
24
7
24
6
24
5
24
7
24
5
88.2
17
11
17
11
17
11
17
10
17
11
17
11
96
16
4
16
4
16
4
16
3
16
4
16
4
128
12
3
12
3
12
3
12
2
12
3
12
3
Not supported
8
14
Not supported
8
13
8
14
8
13
8
8
2
8
Not supported
8
2
8
2
176.4
192
2
2
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Table 17-6. Crystal Frequency (Values from 10 MHz to 14.3181 MHz)
Sampling
Frequency
Fs (kHz)
Crystal Frequency (MHz)
10
Integer
12
Fractional
Integer
12.288
13.56
Fractional
Integer
Fractional
Integer
14.3181
Fractional
Integer
Fractional
8
195
5
195
5
196
0
194
3
195
12
11.025
141
12
141
12
142
4
140
15
142
1
12
130
3
130
3
130
11
129
8
130
8
16
97
10
97
10
98
0
97
2
97
14
22.05
70
14
70
14
71
2
70f
7
71
0
24
65
2
65
2
65
5
64
12
65
4
32
48
13
48
13
49
0
48
9
48
15
44.1
35
7
35
7
35
9
35
4
35
8
48
32
9
32
9
32
11
32
6
32
10
64
24
7
24
7
24
8
24
4
24
8
88.2
17
11
17
11
17
12
17
10
17
12
96
16
4
16
4
16
5
16
3
16
5
128
12
3
12
3
12
4
12
2
12
4
176.4
8
14
8
14
8
14
8
13
8
14
192
8
2
8
2
8
3
Not supported
Not supported
Table 17-7. Crystal Frequency (Values from 16 MHz to 16.384 MHz)
Sampling Frequency Fs
(kHz)
17.3.1.4
Crystal Frequency (MHz)
16
16.384
Integer
Fractional
Integer
Fractional
8
195
5
192
0
11.025
141
12
139
5
12
130
3
128
0
16
97
10
96
0
22.05
70
14
69
11
24
65
2
64
0
32
48
13
48
0
44.1
35
7
34
13
48
32
9
32
0
64
24
7
24
0
88.2
17
11
17
7
96
16
4
16
0
128
12
3
12
0
176.4
8
14
8
11
192
8
2
8
0
Interrupt Control
A single interrupt is asserted to the CPU whenever any of the transmit or receive sources is asserted.
The transmit module has two interrupt sources: the FIFO service request and write error. The
interrupts may be masked using the TXSRIM and TXWEIM bits in the I2S Interrupt Mask (I2SIM)
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register. The status of the interrupt source is indicated by the I2S Raw Interrupt Status (I2SRIS)
register. The status of enabled interrupts is indicated by the I2S Masked Interrupt Status (I2SMIS)
register. The FIFO level interrupt has a second level of masking using the FFM bit in the I2S Transmit
Interrupt Status and Mask (I2STXISM) register.
The FIFO service request interrupt is asserted when the FIFO level (indicated by the LEVEL field
in the I2S Transmit FIFO Level (I2STXLEV) register) is below the FIFO limit (programmed using
the I2S Transmit FIFO Limit (I2STXLIMIT) register) and both the TXSRIM and FFM bits are set. If
software attempts to write to a full FIFO, a Transmit FIFO Write error occurs (indicated by the
TXWERIS bit in the I2S Raw Interrupt Status (I2SRIS) register). The TXWERIS bit in the I2SRIS
register and the TXWEMIS bit in the I2SMIS register are cleared by setting the TXWEIC bit in the I2S
Interrupt Clear (I2SIC) register.
17.3.1.5
DMA Support
The µDMA can be used to more efficiently stream data to and from the I2S bus. The I2S tranmit and
receive modules have separate µDMA channels. The FIFO Interrupt Mask bit (FFM) in the I2STXISM
register must be set for the request signaling to propagate to the µDMA module. See “Micro Direct
Memory Access (μDMA)” on page 240 for channel configuration.
The I2S module uses the µDMA burst request signal, not the single request. Thus each time a µDMA
request is made, the µDMA controller transfers the number of items specified as the burst size for
the µDMA channel. Therefore, the µDMA channel burst size and the I2S FIFO service request limit
must be set to the same value (using the LIMIT field in the I2STXLIMIT register).
17.3.2
Receive
The receiver consists of a serial decoder, an 8-entry FIFO, and control logic. The receiver has
independent MCLK (I2S0RXMCLK), SCLK (I2S0RXSCK), and Word-Select (I2S0RXWS) signals.
17.3.2.1
Serial Decoder
The serial decoder accepts incoming audio stream data and places the sample data in the receive
FIFO. By configuring the serial decoder, common audio formats I2S, Left-Justified, and Right-Justified
are supported. The MSB is transmitted first. The sample size and system data size are configurable
with the SSZ and SDSZ bits in the I2S Receive Module Configuration (I2SRXCFG) register. The
sample size is the number of bits of data being received, and the system data size is the number
of I2S0RXSCK transitions between the word select transitions. The system data size must be large
enough to accommodate the maximum sample size. Any bits received after the LSB are 0s. If the
FIFO is full, the incoming sample (in Mono) or sample-pairs (Stereo) are dropped until the FIFO has
space. The serial decoder is enabled using the RXEN bit in the I2SCFG register.
17.3.2.2
FIFO Operation
The receive FIFO stores eight Mono samples or eight Stereo sample-pairs of data and is accessed
through the I2S Receive FIFO Data (I2SRXFIFO) register. Table 17-8 on page 728 defines the
interface for each Read mode. All data is stored MSB-aligned. The Stereo data is read left sample
then right.
In Mono mode, the FIFO interface can be configured to read the right or left channel by setting the
FIFO Mono Mode bit (FMM) in the I2S Receive FIFO Configuration (I2SRXFIFOCFG) register. This
enables reads from a single channel, where the channel selected can be either the right or left as
determined by the LRP bit in the I2SRXCFG register.
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Table 17-8. I2S Receive FIFO Interface
RM bit in
I2RXCFG
CSS bit in
Read Mode
I2SRXFIFOCFG
Sample Width
Samples per
FIFO Read
Data Alignment
Stereo
8-32 bits
1
MSB
0
don't care
1
0
Compact Stereo - 16 bit
8-16 bits
2
MSB Right [31:15], Left
[15:0]
1
1
Compact Stereo - 8 bit
8 bits
2
Right [15:8] Left[7:0]
0
don't care
8-32 bits
1
MSB
Mono (FMM bit in the
I2SRXFIFOCFG register must
be set.)
The number of samples in the receive FIFO can be read using the I2S Receive FIFO Level
(I2SRXLEV) register. The value ranges from 0 to 16. Stereo and compact stereo sample pairs are
counted as two. The mono samples also increment the count by two, therefore four Mono samples
will have a count of eight.
17.3.2.3
Clock Control
The receiver MCLK and SCLK can be independently programmed to be the master or slave. The
receiver is programmed to be the master or slave of the SCLK using the MSL bit in the I2SRXCFG
register. When the receiver is the master, the I2S0RXSCK frequency is the specified I2S0RXMCLK
divided by four. The I2S0RXSCK may be inverted using the SCP bit in the I2SRXCFG register.
The receiver can also be the master or slave of the MCLK. When the receiver is the master, the
PLL must be active and a fractional clock divider must be programmed. See page 142 for the setup
for the master I2S0RXMCLK source. An external transmit I2S0RXMCLK does not require the use of
the PLL and is selected using the RXSLV bit in the I2SCFG register.
Refer to “Clock Control” on page 724 for combinations of the RXINT and RXFRAC bits in the I2S
MCLK Configuration (I2SMCLKCFG) register that provide MCLK frequencies within acceptable
error limits. In the table, Fs is the sampling frequency in kHz and possible crystal frequencies are
shown in MHz across the top row of the table. The words "not supported" in the table mean that it
is not possible to obtain the specified sampling frequencies with the specified crystal frequency
within the error tolerance of 0.3%.
17.3.2.4
Interrupt Control
A single interrupt is asserted to the CPU whenever any of the transmit or receive sources is asserted.
The receive module has two interrupt sources: the FIFO service request and read error. The interrupts
may be masked using the RXSRIM and RXREIM bits in the I2SIM register. The status of the interrupt
source is indicated by the I2SRIS register. The status of enabled interrupts is indicated by the I2SMIS
register. The FIFO service request interrupt has a second level of masking using the FFM bit in the
I2S Receive Interrupt Status and Mask (I2SRXISM) register. The sources may be masked using
the I2SIM register.
The FIFO service request interrupt is asserted when the FIFO level (indicated by the LEVEL field
in the I2S Receive FIFO Level (I2SRXLEV) register) is above the FIFO limit (programmed using
the I2S Receive FIFO Limit (I2SRXLIMIT) register) and both the RXSRIM and FFM bits are set. An
error occurs when reading an empty FIFO or if a stereo sample pair is not read left then right. To
clear an interrupt, write a 1 to the appropriate bit in the I2SIC register. If software attempts to read
an empty FIFO or if a stereo sample pair is not read left then right, a Receive FIFO Read error
occurs (indicated by the RXRERIS bit in the I2SRIS register). The RXRERIS bit in the I2SRIS register
and the RXREMIS bit in the I2SMIS register are cleared by setting the RXREIC bit in the I2SIC
register.
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17.3.2.5
DMA Support
The µDMA can be used to more efficiently stream data to and from the I2S bus. The I2S tranmit and
receive modules have separate µDMA channels. The FIFO Interrupt Mask bit (FFM) in the I2SRXISM
register must be set for the request signaling to propagate to the µDMA module. See “Micro Direct
Memory Access (μDMA)” on page 240 for channel configuration.
The I2S module uses the µDMA burst request signal, not the single request. Thus each time a µDMA
request is made, the µDMA controller transfers the number of items specified as the burst size for
the µDMA channel. Therefore, the µDMA channel burst size and the I2S FIFO service request limit
must be set to the same value (using the LIMIT field in the I2SRXLIMIT register).
17.4
Initialization and Configuration
The default setup for the I2S transmit and receive is to use external MCLK, external SCLK, Stereo,
I2S audio format, and 32-bit data samples. The following example shows how to configure a system
using the internal MCLK, internal SCLK, Compact Stereo, and Left-Justified audio format with 16-bit
data samples.
1. Enable the I2S peripheral clock by writing a value of 0x1000.0000 to the RCGC1 register in the
System Control module (see page 179).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module (see page 191). To find out which GPIO port to enable, refer to Table 24-5 on page 1097.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 323). To determine which GPIOs to configure, see Table
24-4 on page 1088.
4. Configure the PMCn fields in the GPIOPCTL register to assign the I2S signals to the appropriate
pins (see page 341 and Table 24-5 on page 1097).
5. Set up the MCLK sources for a 48-kHz sample rate. The input crystal is assumed to be 6 MHz
for this example (internal source).
■ Enable the PLL by clearing the PWRDWN bit in the RCC register in the System Control module
(see page 127).
■ Set the MCLK dividers and enable them by writing 0x0208.0208 to the I2SMCLKCFG register
in the System Control module (see page 142).
■ Enable the MCLK internal sources by writing 0x8208.8208 to the I2SMCLKCFG register in
the System Control module.
To allow an external MCLK to be used, set bits 4 and 5 of the I2SCFG register. Starting up the
PLL and enabling the MCLK sources is not required.
6. Set up the Serial Bit Clock SCLK source. By default, the SCLK is externally sourced.
■ Receiver: Masters the I2S0RXSCK by ORing 0x0040.0000 into the I2SRXCFG register.
■ Transmitter: Masters the I2S0TXSCK by ORing 0x0040.0000 into the I2STXCFG register.
7. Configure the Serial Encoder/Decoder (Left-Justified, Compact Stereo, 16-bit samples, 32-bit
system data size).
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■ Set the audio format using the Justification (JST), Data Delay (DLY), SCLK polarity (SCP),
and Left-Right Polarity (LRP) bits written to the I2STXCFG and I2SRXCFG registers. The
settings are shown in the table below.
Table 17-9. Audio Formats Configuration
Audio Format
I2STXCFG/I2SRXCFG Register Bit
JST
DLY
SCP
LRP
I2S
0
1
0
1
Left-Justified
0
0
0
0
Right-Justified
1
0
0
0
■ Write 0x0140.3DF0 to both the I2STXCFG and I2SRXCFG registers to program the following
configurations:
– Set the sample size to 16 bits using the SSZ field of the I2STXCFG and I2SRXCFG
registers.
– Set the system data size to 32 bits using the SDSZ field of the I2STXCFG and I2SRXCFG
registers.
– Set the Write and Read modes using the WM and RM fields in the I2STXCFG and
I2SRXCFG registers, respectively.
8. Set up the FIFO limits for triggering interrupts (also used for µDMA)
■ Set up the transmit FIFO to trigger when it has less than four sample pairs by writing a
0x0000.0008 to the I2STXLIMIT register.
■ Set up the receive FIFO to trigger when there are more than four sample pairs by writing a
0x0000.00008 to the I2SRXLIMIT register.
9. Enable interrupts.
■ Enable the transmit FIFO interrupt by setting the FFM bit in the I2STXISM register (write
0x0000.0001).
■ Set up the receive FIFO interrupts by setting the FFM bit in the I2SRXISM register (write
0x0000.0001).
■ Enable the TX FIFO service request, the TX Error, the RX FIFO service request, and the
RX Error interrupts to be sent to the CPU by writing a 0x0000.0033 to the I2SSIM register.
10. Enable the Serial Encoder and Serial Decoders by writing a 0x0000.0003 to the I2SCFG register.
17.5
Register Map
Table 17-10 on page 731 lists the I2S registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the I2S interface base address of 0x4005.4000. Note that the I2S
module clock must be enabled before the registers can be programmed (see page 179).
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Table 17-10. Inter-Integrated Circuit Sound (I2S) Interface Register Map
Name
Type
Reset
0x000
I2STXFIFO
WO
0x0000.0000
I2S Transmit FIFO Data
732
0x004
I2STXFIFOCFG
R/W
0x0000.0000
I2S Transmit FIFO Configuration
733
0x008
I2STXCFG
R/W
0x1400.7DF0
I2S Transmit Module Configuration
734
0x00C
I2STXLIMIT
R/W
0x0000.0000
I2S Transmit FIFO Limit
736
0x010
I2STXISM
R/W
0x0000.0000
I2S Transmit Interrupt Status and Mask
737
0x018
I2STXLEV
RO
0x0000.0000
I2S Transmit FIFO Level
738
0x800
I2SRXFIFO
RO
0x0000.0000
I2S Receive FIFO Data
739
0x804
I2SRXFIFOCFG
R/W
0x0000.0000
I2S Receive FIFO Configuration
740
0x808
I2SRXCFG
R/W
0x1400.7DF0
I2S Receive Module Configuration
741
0x80C
I2SRXLIMIT
R/W
0x0000.7FFF
I2S Receive FIFO Limit
744
0x810
I2SRXISM
R/W
0x0000.0000
I2S Receive Interrupt Status and Mask
745
0x818
I2SRXLEV
RO
0x0000.0000
I2S Receive FIFO Level
746
0xC00
I2SCFG
R/W
0x0000.0000
I2S Module Configuration
747
0xC10
I2SIM
R/W
0x0000.0000
I2S Interrupt Mask
749
0xC14
I2SRIS
RO
0x0000.0000
I2S Raw Interrupt Status
751
0xC18
I2SMIS
RO
0x0000.0000
I2S Masked Interrupt Status
753
0xC1C
I2SIC
WO
0x0000.0000
I2S Interrupt Clear
755
17.6
Description
See
page
Offset
Register Descriptions
The remainder of this section lists and describes the I2S registers, in numerical order by address
offset.
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Inter-Integrated Circuit Sound (I2S) Interface
Register 1: I2S Transmit FIFO Data (I2STXFIFO), offset 0x000
This register is the 32-bit serial audio transmit data register. In Stereo mode, the data is written left,
right, left, right, and so on. The LRS bit in the I2S Transmit FIFO Configuration (I2STXFIFOCFG)
register can be read to verify the next position expected. In Compact 16-bit mode, bits [31:16] contain
the right sample, and bits [15:0] contain the left sample. In Compact 8-bit mode, bits [15:8] contain
the right sample, and bits [7:0] contain the left sample. In Mono mode, each 32-bit entry is a single
sample.
Note that if the FIFO is full and a write is attempted, a transmit FIFO write error is generated.
I2S Transmit FIFO Data (I2STXFIFO)
Base 0x4005.4000
Offset 0x000
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
TXFIFO
Type
Reset
TXFIFO
Type
Reset
Bit/Field
Name
Type
31:0
TXFIFO
WO
Reset
Description
0x0000.0000 TX Data
Serial audio sample data to be transmitted.
732
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 2: I2S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004
This register configures the sample for dual-channel operation. In Stereo mode, the LRS bit toggles
between left and right samples as the Transmit FIFO is written. The left sample is written first,
followed by the right.
I2S Transmit FIFO Configuration (I2STXFIFOCFG)
Base 0x4005.4000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
CSS
LRS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
CSS
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Compact Stereo Sample Size
Value Description
0
LRS
R/W
0
0
The transmitter is in Compact 16-bit Stereo Mode with a 16-bit
sample size.
1
The transmitter is in Compact 8-bit Stereo Mode with an 8-bit
sample size.
Left-Right Sample Indicator
Value Description
0
The left sample is the next position.
1
The right sample is the next position.
In Mono mode and Compact stereo mode, this bit toggles as if it were
in Stereo mode, but it has no meaning and should be ignored.
May 24, 2010
733
Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Register 3: I2S Transmit Module Configuration (I2STXCFG), offset 0x008
This register controls the configuration of the Transmit module.
I2S Transmit Module Configuration (I2STXCFG)
Base 0x4005.4000
Offset 0x008
Type R/W, reset 0x1400.7DF0
31
30
reserved
Type
Reset
29
28
27
26
25
24
WM
23
22
20
19
18
17
16
JST
DLY
SCP
LRP
FMT
MSL
RO
0
RO
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
RO
0
RO
0
RO
0
RO
0
SSZ
Type
Reset
21
reserved
SDSZ
Bit/Field
Name
Type
Reset
31:30
reserved
RO
0x0
29
JST
R/W
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Justification of Output Data
Value Description
28
DLY
R/W
1
0
The data is Left-Justified.
1
The data is Right-Justified.
Data Delay
Value Description
27
SCP
R/W
0
0
Data is latched on the next latching edge of I2S0TXSCK as
defined by the SCP bit. This bit should be clear in Left-Justified
or Right-Justified mode.
1
A one-I2S0TXSCK delay from the edge of I2S0TXWS is inserted
before data is latched. This bit should be set in I2S mode.
SCLK Polarity
Value Description
26
LRP
R/W
1
0
Data and the I2S0TXWS signal (when the MSL bit is set) are
launched on the falling edge of I2S0TXSCK.
1
Data and the I2S0TXWS signal (when the MSL bit is set) are
launched on the rising edge of I2S0TXSCK.
Left/Right Clock Polarity
Value Description
0
I2S0TXWS is high during the transmission of the left channel
data.
1
I2S0TXWS is high during the transmission of the right channel
data.
734
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
Description
25:24
WM
R/W
0x0
Write Mode
This bit field selects the mode in which the transmit data is stored in the
FIFO and transmitted.
Value Description
0x0
Stereo mode
0x1
Compact Stereo mode
Left/Right sample packed. Refer to I2STXFIFOCFG for 8/16-bit
sample size selection.
23
FMT
R/W
0
0x2
Mono mode
0x3
reserved
FIFO Empty
Value Description
22
MSL
R/W
0
0
All zeroes are transmitted if the FIFO is empty.
1
The last sample is transmitted if the FIFO is empty.
SCLK Master/Slave
Source of serial bit clock (I2S0TXSCK) and Word Select (I2S0TXWS).
Value Description
0
The transmitter is a slave using the externally driven I2S0TXSCK
and I2S0TXWS signals.
1
The transmitter is a master using the internally generated
I2S0TXSCK and I2S0TXWS signals.
21:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:10
SSZ
R/W
0x1F
Sample Size
This field contains the number of bits minus one in the sample.
Note:
9:4
SDSZ
R/W
0x1F
This field is only used in Right-Justified mode. Unused bits
are not masked.
System Data Size
This field contains the number of bits minus one during the high or low
phase of the I2S0TXWS signal.
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
735
Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Register 4: I2S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C
This register sets the lower FIFO limit at which a FIFO service request is issued.
I2S Transmit FIFO Limit (I2STXLIMIT)
Base 0x4005.4000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
LIMIT
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.00
4:0
LIMIT
R/W
0x00
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Limit
This field sets the FIFO level at which a FIFO service request is issued,
generating an interrupt or a µDMA transfer request.
The transmit FIFO generates a service request when the number of
items in the FIFO is less than the level specified by the LIMIT field. For
example, if the LIMIT field is set to 8, then a service request is
generated when there are less than 8 samples remaining in the transmit
FIFO.
736
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 5: I2S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010
This register indicates the transmit interrupt status and interrupt masking control.
I2S Transmit Interrupt Status and Mask (I2STXISM)
Base 0x4005.4000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
FFI
reserved
Type
Reset
RO
0
FFM
R/W
0
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
FFI
RO
0
Transmit FIFO Service Request Interrupt
Value Description
15:1
reserved
RO
0x000
0
FFM
R/W
0
0
The FIFO level is equal to or above the FIFO limit.
1
The FIFO level is below the FIFO limit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Interrupt Mask
Value Description
0
The FIFO interrupt is masked and not sent to the CPU.
1
The FIFO interrupt is enabled to be sent to the interrupt
controller.
May 24, 2010
737
Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Register 6: I2S Transmit FIFO Level (I2STXLEV), offset 0x018
The number of samples in the transmit FIFO can be read using the I2STXLEV register. The value
ranges from 0 to 16. Stereo and Compact Stereo sample-pairs are counted as two. Mono samples
also increment the count by two. For example, the LEVEL field is set to eight if there are four Mono
samples.
I2S Transmit FIFO Level (I2STXLEV)
Base 0x4005.4000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
LEVEL
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.00
4:0
LEVEL
RO
0x00
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Number of Audio Samples
This field contains the number of samples in the FIFO.
738
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 7: I2S Receive FIFO Data (I2SRXFIFO), offset 0x800
Important: Use caution when reading this register. Performing a read may change bit status.
This register is the 32-bit serial audio receive data register. In Stereo mode, the data is read left,
right, left, right, and so on. The LRS bit in the I2S Receive FIFO Configuration (I2SRXFIFOCFG)
register can be read to verify the next position expected. In Compact 16-bit mode, bits [31:16] contain
the right sample, and bits [15:0] contain the left sample. In Compact 8-bit mode, bits [15:8] contain
the right sample, and bits [7:0] contain the left sample. In Mono mode, each 32-bit entry is a single
sample. If the FIFO is empty, a read of this register returns a value of 0x0000.0000 and generates
a receive FIFO read error.
I2S Receive FIFO Data (I2SRXFIFO)
Base 0x4005.4000
Offset 0x800
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RXFIFO
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RXFIFO
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
31:0
RXFIFO
RO
RO
0
Reset
RO
0
Description
0x0000.0000 RX Data
Serial audio sample data received.
The read of an empty FIFO returns a value of 0x0.
May 24, 2010
739
Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Register 8: I2S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804
This register configures the sample for dual-channel operation. In Stereo mode, the LRS bit toggles
between Left and Right as the samples are read from the receive FIFO. In Mono mode, both the
left and right samples are stored in the FIFO. The FMM bit can be used to read only the left or right
sample as determined by the LRP bit. In Compact Stereo 8- or 16-bit mode, both the left and right
samples are read in one access from the FIFO.
I2S Receive FIFO Configuration (I2SRXFIFOCFG)
Base 0x4005.4000
Offset 0x804
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
FMM
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
0
FMM
CSS
LRS
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Mono Mode
Value Description
0
The receiver is in Stereo Mode.
1
The receiver is in Mono mode.
If the LRP bit in the I2SRXCFG register is clear, data is read
while the I2S0RXWS signal is low (Right Channel); if the LRP
bit is set, data is read while the I2S0RXWS signal is high (Left
Channel).
1
CSS
R/W
0
Compact Stereo Sample Size
Value Description
0
LRS
R/W
0
0
The receiver is in Compact 16-bit Stereo Mode with a 16-bit
sample size.
1
The receiver is in Compact 8-bit Stereo Mode with a 8-bit sample
size.
Left-Right Sample Indicator
Value Description
0
The left sample is the next position to be read.
1
The right sample is the next position to be read.
This bit is only meaningful in Compact Stereo Mode.
740
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 9: I2S Receive Module Configuration (I2SRXCFG), offset 0x808
This register controls the configuration of the receive module.
I2S Receive Module Configuration (I2SRXCFG)
Base 0x4005.4000
Offset 0x808
Type R/W, reset 0x1400.7DF0
31
30
reserved
Type
Reset
29
28
27
26
25
24
23
22
20
19
18
17
16
JST
DLY
SCP
LRP
reserved
RM
reserved
MSL
RO
0
RO
0
R/W
0
R/W
1
R/W
0
R/W
1
RO
0
R/W
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
RO
0
RO
0
RO
0
RO
0
SSZ
Type
Reset
21
reserved
SDSZ
Bit/Field
Name
Type
Reset
31:30
reserved
RO
0x0
29
JST
R/W
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Justification of Input Data
Value Description
28
DLY
R/W
1
0
The data is Left-Justified.
1
The data is Right-Justified.
Data Delay
Value Description
27
SCP
R/W
0
0
Data is latched on the next latching edge of I2S0RXSCK as
defined by the SCP bit. This bit should be clear in Left-Justified
or Right-Justified mode.
1
A one-I2S0RXSCK delay from the edge of I2S0RXWS is inserted
before data is latched. This bit should be set in I2S mode.
SCLK Polarity
Value Description
0
Data is latched on the rising edge and the I2S0RXWS signal
(when the MSL bit is set) is launched on the falling edge of
I2S0RXSCK.
1
Data is latched on the falling edge and the I2S0RXWS signal
(when the MSL bit is set) is launched on the rising edge of
I2S0RXSCK.
May 24, 2010
741
Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Bit/Field
Name
Type
Reset
26
LRP
R/W
1
Description
Left/Right Clock Polarity
Value Description
0
In Stereo mode, I2S0RXWS is high during the transmission of
the left channel data.
In Mono mode, data is read while the I2S0RXWS signal is low
(Right Channel).
1
In Stereo mode, I2S0RXWS is high during the transmission of
the right channel data.
In Mono mode, data is read while the I2S0RXWS signal is high
(Left Channel).
25
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24
RM
R/W
0
Read Mode
This bit selects the mode in which the receive data is received and stored
in the FIFO.
Value Description
0
Stereo/Mono mode
I2SRXFIFOCFG FMM bit specifies Stereo or Mono FIFO read
behavior.
1
Compact Stereo mode
Left/Right sample packed. Refer to I2SRXFIFOCFG for 8/16-bit
sample size selection.
23
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
22
MSL
R/W
0
SCLK Master/Slave
Value Description
0
The receiver is a slave and uses the externally driven
I2S0RXSCK and I2S0RXWS signals.
1
The receiver is a master and uses the internally generated
I2S0RXSCK and I2S0RXWS signals.
21:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:10
SSZ
R/W
0x1F
Sample Size
This field contains the number of bits minus one in the sample.
9:4
SDSZ
R/W
0x1F
System Data Size
This field contains the number of bits minus one during the high or low
phase of the I2S0RXWS signal.
742
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
3:0
reserved
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
743
Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Register 10: I2S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C
This register sets the upper FIFO limit at which a FIFO service request is issued.
I2S Receive FIFO Limit (I2SRXLIMIT)
Base 0x4005.4000
Offset 0x80C
Type R/W, reset 0x0000.7FFF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
reserved
Type
Reset
RO
1
LIMIT
R/W
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:5
reserved
RO
0x7FF
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0
LIMIT
R/W
0x1F
FIFO Limit
This field sets the FIFO level at which a FIFO service request is issued,
generating an interrupt or a µDMA transfer request.
The receive FIFO generates a service request when the number of items
in the FIFO is greater than the level specified by the LIMIT field. For
example, if the LIMIT field is set to 4, then a service request is
generated when there are more than 4 samples remaining in the transmit
FIFO.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 11: I2S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810
This register indicates the receive interrupt status and interrupt masking control.
I2S Receive Interrupt Status and Mask (I2SRXISM)
Base 0x4005.4000
Offset 0x810
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
FFI
reserved
Type
Reset
RO
0
FFM
R/W
0
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
FFI
RO
0
Receive FIFO Service Request Interrupt
Value Description
15:1
reserved
RO
0x000
0
FFM
R/W
0
0
The FIFO level is equal to or below the FIFO limit.
1
The FIFO level is above the FIFO limit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Interrupt Mask
Value Description
0
The FIFO interrupt is masked and not sent to the CPU.
1
The FIFO interrupt is enabled to be sent to the interrupt
controller.
May 24, 2010
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Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Register 12: I2S Receive FIFO Level (I2SRXLEV), offset 0x818
The number of samples in the receive FIFO can be read using the I2SRXLEV register. The value
ranges from 0 to 16. Stereo and Compact Stereo sample pairs are counted as two. Mono samples
also increment the count by two. For example, the LEVEL field is set to eight if there are four Mono
samples.
I2S Receive FIFO Level (I2SRXLEV)
Base 0x4005.4000
Offset 0x818
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
LEVEL
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.00
4:0
LEVEL
RO
0x00
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Number of Audio Samples
This field contains the number of samples in the FIFO.
746
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 13: I2S Module Configuration (I2SCFG), offset 0xC00
This register enables the transmit and receive serial engines and sets the source of the I2S0TXMCLK
and I2S0RXMCLK signals.
I2S Module Configuration (I2SCFG)
Base 0x4005.4000
Offset 0xC00
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RXSLV
TXSLV
RXEN
TXEN
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5
RXSLV
R/W
0
reserved
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Use External I2S0RXMCLK
Value Description
4
TXSLV
R/W
0
0
The receiver uses the internally generated MCLK as the
I2S0RXMCLK signal. See “Clock Control” on page 724 for
information on how to program the I2S0RXMCLK.
1
The receiver uses the externally driven I2S0RXMCLK signal.
Use External I2S0TXMCLK
Value Description
3:2
reserved
RO
0x0
1
RXEN
R/W
0
0
The transmitter uses the internally generated MCLK as the
I2S0TXMCLK signal. See “Clock Control” on page 724 for
information on how to program the I2S0TXMCLK.
1
The transmitter uses the externally driven I2S0TXMCLK signal.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Serial Receive Engine Enable
Value Description
0
Disables the serial receive engine.
1
Enables the serial receive engine.
May 24, 2010
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Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Bit/Field
Name
Type
Reset
0
TXEN
R/W
0
Description
Serial Transmit Engine Enable
Value Description
0
Disables the serial transmit engine.
1
Enables the serial transmit engine.
748
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 14: I2S Interrupt Mask (I2SIM), offset 0xC10
This register masks the interrupts to the CPU.
I2S Interrupt Mask (I2SIM)
Base 0x4005.4000
Offset 0xC10
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RXREIM
RXSRIM
TXWEIM
TXSRIM
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5
RXREIM
R/W
0
reserved
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive FIFO Read Error
Value Description
4
RXSRIM
R/W
0
0
The receive FIFO read error interrupt is masked and not sent
to the CPU.
1
The receive FIFO read error is enabled to be sent to the interrupt
controller.
Receive FIFO Service Request
Value Description
3:2
reserved
RO
0x0
1
TXWEIM
R/W
0
0
The receive FIFO service request interrupt is masked and not
sent to the CPU.
1
The receive FIFO service request is enabled to be sent to the
interrupt controller.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit FIFO Write Error
Value Description
0
The transmit FIFO write error interrupt is masked and not sent
to the CPU.
1
The transmit FIFO write error is enabled to be sent to the
interrupt controller.
May 24, 2010
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Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Bit/Field
Name
Type
Reset
0
TXSRIM
R/W
0
Description
Transmit FIFO Service Request
Value Description
0
The transmit FIFO service request interrupt is masked and not
sent to the CPU.
1
The transmit FIFO service request is enabled to be sent to the
interrupt controller.
750
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 15: I2S Raw Interrupt Status (I2SRIS), offset 0xC14
This register reads the unmasked interrupt status.
I2S Raw Interrupt Status (I2SRIS)
Base 0x4005.4000
Offset 0xC14
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RXRERIS RXSRRIS
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5
RXRERIS
RO
0
RO
0
RO
0
reserved
RO
0
TXWERIS TXSRRIS
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive FIFO Read Error
Value Description
1
A receive FIFO read error interrupt has occurred.
0
No interrupt
This bit is cleared by setting the RXREIC bit in the I2SIC register.
4
RXSRRIS
RO
0
Receive FIFO Service Request
Value Description
1
A receive FIFO service request interrupt has occurred.
0
No interrupt
This bit is cleared when the level in the receive FIFO has risen to a value
greater than the value programmed in the LIMIT field in the I2SRXLIMIT
register.
3:2
reserved
RO
0x0
1
TXWERIS
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit FIFO Write Error
Value Description
1
A transmit FIFO write error interrupt has occurred.
0
No interrupt
This bit is cleared by setting the TXWEIC bit in the I2SIC register.
May 24, 2010
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Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Bit/Field
Name
Type
Reset
0
TXSRRIS
RO
0
Description
Transmit FIFO Service Request
Value Description
1
A transmit FIFO service request interrupt has occurred.
0
No interrupt
This bit is cleared when the level in the transmit FIFO has fallen to a
value less than the value programmed in the LIMIT field in the
I2STXLIMIT register.
752
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 16: I2S Masked Interrupt Status (I2SMIS), offset 0xC18
This register reads the masked interrupt status. The mask is defined in the I2SIM register.
I2S Masked Interrupt Status (I2SMIS)
Base 0x4005.4000
Offset 0xC18
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RXREMIS RXSRMIS
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5
RXREMIS
RO
0
RO
0
RO
0
reserved
RO
s
RO
0
TXWEMIS TXSRMIS
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive FIFO Read Error
Value Description
1
An unmasked interrupt was signaled due to a receive FIFO read
error.
0
An interrupt has not occurred or is masked.
This bit is cleared by setting the RXREIC bit in the I2SIC register.
4
RXSRMIS
RO
0
Receive FIFO Service Request
Value Description
1
An unmasked interrupt was signaled due to a receive FIFO
service request.
0
An interrupt has not occurred or is masked.
This bit is cleared when the level in the receive FIFO has risen to a value
greater than the value programmed in the LIMIT field in the I2SRXLIMIT
register.
3:2
reserved
RO
0s0
1
TXWEMIS
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit FIFO Write Error
Value Description
1
An unmasked interrupt was signaled due to a transmit FIFO
write error.
0
An interrupt has not occurred or is masked.
This bit is cleared by setting the TXWEIC bit in the I2SIC register.
May 24, 2010
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Texas Instruments-Advance Information
Inter-Integrated Circuit Sound (I2S) Interface
Bit/Field
Name
Type
Reset
0
TXSRMIS
RO
0
Description
Transmit FIFO Service Request
Value Description
1
An unmasked interrupt was signaled due to a transmit FIFO
service request.
0
An interrupt has not occurred or is masked.
This bit is cleared when the level in the transmit FIFO has fallen to a
value less than the value programmed in the LIMIT field in the
I2STXLIMIT register.
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 17: I2S Interrupt Clear (I2SIC), offset 0xC1C
Writing a 1 to a bit in this register clears the corresponding interrupt.
I2S Interrupt Clear (I2SIC)
Base 0x4005.4000
Offset 0xC1C
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
8
7
6
5
4
3
2
1
0
TXWEIC
reserved
WO
0
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
WO
0
RXREIC
Bit/Field
Name
Type
Reset
31:6
reserved
WO
0x0000.00
5
RXREIC
WO
0
WO
0
reserved
WO
0
WO
0
WO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive FIFO Read Error
Writing a 1 to this bit clears the RXRERIS bit in the I2CRIS register and
the RXREMIS bit in the I2CMIS register.
4:2
reserved
WO
0x0
1
TXWEIC
WO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit FIFO Write Error
Writing a 1 to this bit clears the TXWERIS bit in the I2CRIS register and
the TXWEMIS bit in the I2CMIS register.
0
reserved
WO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
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Texas Instruments-Advance Information
Controller Area Network (CAN) Module
18
Controller Area Network (CAN) Module
Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, it is also used in many embedded control
applications (such as industrial and medical). Bit rates up to 1 Mbps are possible at network lengths
less than 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at
500 meters).
®
The Stellaris LM3S5B91 microcontroller includes two CAN units with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable Loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
18.1
Block Diagram
Figure 18-1. CAN Controller Block Diagram
CAN Control
CANCTL
CANSTS
CANERR
CANBIT
CANINT
CANTST
CANBRPE
CAN Tx
CAN Interface 1
APB Pins
APB
Interface
CANIF1CRQ
CANIF1CMSK
CANIF1MSK1
CANIF1MSK2
CANIF1ARB1
CANIF1ARB2
CANIF1MCTL
CANIF1DA1
CANIF1DA2
CANIF1DB1
CANIF1DB2
CAN Core
CAN Rx
CAN Interface 2
CANIF2CRQ
CANIF2CMSK
CANIF2MSK1
CANIF2MSK2
CANIF2ARB1
CANIF2ARB2
CANIF2MCTL
CANIF2DA1
CANIF2DA2
CANIF2DB1
CANIF2DB2
Message Object
Registers
CANTXRQ1
CANTXRQ2
CANNWDA1
CANNWDA2
CANMSG1INT
CANMSG2INT
CANMSG1VAL
CANMSG2VAL
Message RAM
32 Message Objects
18.2
Signal Description
Table 18-1 on page 758 and Table 18-2 on page 758 list the external signals of the CAN controller
and describe the function of each. The CAN controller signals are alternate functions for some GPIO
signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin
Assignment" lists the possible GPIO pin placements for the CAN signals. The AFSEL bit in the GPIO
Alternate Function Select (GPIOAFSEL) register (page 323) should be set to choose the CAN
controller function. The number in parentheses is the encoding that must be programmed into the
PMCn field in the GPIO Port Control (GPIOPCTL) register (page 341) to assign the CAN signal to
the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose
Input/Outputs (GPIOs)” on page 298.
May 24, 2010
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Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Table 18-1. Signals for Controller Area Network (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CAN0Rx
10
30
34
92
PD0 (2)
PA4 (5)
PA6 (6)
PB4 (5)
I
TTL
CAN module 0 receive.
CAN0Tx
11
31
35
91
PD1 (2)
PA5 (5)
PA7 (6)
PB5 (5)
O
TTL
CAN module 0 transmit.
CAN1Rx
47
PF0 (1)
I
TTL
CAN module 1 receive.
CAN1Tx
61
PF1 (1)
O
TTL
CAN module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 18-2. Signals for Controller Area Network (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CAN0Rx
G1
L5
L6
A6
PD0 (2)
PA4 (5)
PA6 (6)
PB4 (5)
I
TTL
CAN module 0 receive.
CAN0Tx
G2
M5
M6
B7
PD1 (2)
PA5 (5)
PA7 (6)
PB5 (5)
O
TTL
CAN module 0 transmit.
CAN1Rx
M9
PF0 (1)
I
TTL
CAN module 1 receive.
CAN1Tx
H12
PF1 (1)
O
TTL
CAN module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
18.3
Functional Description
®
The Stellaris CAN controller conforms to the CAN protocol version 2.0 (parts A and B). Message
transfers that include data, remote, error, and overload frames with an 11-bit identifier (standard)
or a 29-bit identifier (extended) are supported. Transfer rates can be programmed up to 1 Mbps.
The CAN module consists of three major parts:
■ CAN protocol controller and message handler
■ Message memory
■ CAN register interface
A data frame contains data for transmission, whereas a remote frame contains no data and is used
to request the transmission of a specific message object. The CAN data/remote frame is constructed
as shown in Figure 18-2.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Figure 18-2. CAN Data/Remote Frame
Remote
Transmission
Request
Start
Of Frame
Bus
Idle
R
S
Control
O Message Delimiter T Field
R
F
Number 1
Of Bits
11 or 29
1
6
Delimiter
Bits
Data Field
CRC
Sequence
A
C
K
EOP
IFS
0 . . . 64
15
1 1 1
7
3
CRC Sequence
End of
Frame
Field
CRC
Field
Arbitration Field
Bit Stuffing
Bus
Idle
Interframe
Field
Acknowledgement
Field
CAN Data Frame
The protocol controller transfers and receives the serial data from the CAN bus and passes the data
on to the message handler. The message handler then loads this information into the appropriate
message object based on the current filtering and identifiers in the message object memory. The
message handler is also responsible for generating interrupts based on events on the CAN bus.
The message object memory is a set of 32 identical memory blocks that hold the current configuration,
status, and actual data for each message object. These memory blocks are accessed via either of
the CAN message object register interfaces.
®
®
The message memory is not directly accessible in the Stellaris memory map, so the Stellaris CAN
controller provides an interface to communicate with the message memory via two CAN interface
register sets for communicating with the message objects. The message object memory cannot be
directly accessed, so these two interfaces must be used to read or write to each message object.
The two message object interfaces allow parallel access to the CAN controller message objects
when multiple objects may have new information that must be processed. In general, one interface
is used for transmit data and one for receive data.
18.3.1
Initialization
To use the CAN controller, the peripheral clock must be enabled using the RCGC0 register (see
page 171). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2
register (see page 191). To find out which GPIO port to enable, refer to Table 24-4 on page 1088. Set
the GPIO AFSEL bits for the appropriate pins (see page 323). Configure the PMCn fields in the
GPIOPCTL register to assign the CAN signals to the appropriate pins. See page 341 and Table
24-5 on page 1097.
Software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register (with
software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error
counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus
are stopped and the CANnTX signal is held High. Entering the initialization state does not change
the configuration of the CAN controller, the message objects, or the error counters. However, some
configuration registers are only accessible while in the initialization state.
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To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each
message object. If a message object is not needed, label it as not valid by clearing the MSGVAL bit
in the CAN IFn Arbitration 2 (CANIFnARB2) register. Otherwise, the whole message object must
be initialized, as the fields of the message object may not have valid information, causing unexpected
results. Both the INIT and CCE bits in the CANCTL register must be set in order to access the
CANBIT register and the CAN Baud Rate Prescaler Extension (CANBRPE) register to configure
the bit timing. To leave the initialization state, the INIT bit must be cleared. Afterwards, the internal
Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for
the occurrence of a sequence of 11 consecutive recessive bits (indicating a bus idle condition)
before it takes part in bus activities and starts message transfers. Message object initialization does
not require the CAN to be in the initialization state and can be done on the fly. However, message
objects should all be configured to particular identifiers or set to not valid before message transfer
starts. To change the configuration of a message object during normal operation, clear the MSGVAL
bit in the CANIFnARB2 register to indicate that the message object is not valid during the change.
When the configuration is completed, set the MSGVAL bit again to indicate that the message object
is once again valid.
18.3.2
Operation
Two sets of CAN Interface Registers (CANIF1x and CANIF2x) are used to access the message
objects in the Message RAM. The CAN controller coordinates transfers to and from the Message
RAM to and from the registers. The two sets are independent and identical and can be used to
queue transactions. Generally, one interface is used to transmit data and one is used to receive
data.
Once the CAN module is initialized and the INIT bit in the CANCTL register is cleared, the CAN
module synchronizes itself to the CAN bus and starts the message transfer. As each message is
received, it goes through the message handler's filtering process, and if it passes through the filter,
is stored in the message object specified by the MNUM bit in the CAN IFn Command Request
(CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and
eight data bytes) is stored in the message object. If the Identifier Mask (the MSK bits in the CAN IFn
Mask 1 and CAN IFn Mask 2 (CANIFnMSKn) registers) is used, the arbitration bits that are masked
to "don't care" may be overwritten in the message object.
The CPU may read or write each message at any time via the CAN Interface Registers. The message
handler guarantees data consistency in case of concurrent accesses.
The transmission of message objects is under the control of the software that is managing the CAN
hardware. Message objects can be used for one-time data transfers or can be permanent message
objects used to respond in a more periodic manner. Permanent message objects have all arbitration
and control set up, and only the data bytes are updated. At the start of transmission, the appropriate
TXRQST bit in the CAN Transmission Request n (CANTXRQn) register and the NEWDAT bit in the
CAN New Data n (CANNWDAn) register are set. If several transmit messages are assigned to the
same message object (when the number of message objects is not sufficient), the whole message
object has to be configured before the transmission of this message is requested.
The transmission of any number of message objects may be requested at the same time; they are
transmitted according to their internal priority, which is based on the message identifier (MNUM) for
the message object, with 1 being the highest priority and 32 being the lowest priority. Messages
may be updated or set to not valid any time, even when their requested transmission is still pending.
The old data is discarded when a message is updated before its pending transmission has started.
Depending on the configuration of the message object, the transmission of a message may be
requested autonomously by the reception of a remote frame with a matching identifier.
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Transmission can be automatically started by the reception of a matching remote frame. To enable
this mode, set the RMTEN bit in the CAN IFn Message Control (CANIFnMCTL) register. A matching
received remote frame causes the TXRQST bit to be set, and the message object automatically
transfers its data or generates an interrupt indicating a remote frame was requested. A remote frame
can be strictly a single message identifier, or it can be a range of values specified in the message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are identified
as remote frame requests. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are identified as a remote frame request. The MXTD
bit in the CANIFnMSK2 register should be set if a remote frame request is expected to be triggered
by 29-bit extended identifiers.
18.3.3
Transmitting Message Objects
If the internal transmit shift register of the CAN module is ready for loading, and if a data transfer is
not occurring between the CAN Interface Registers and message RAM, the valid message object
with the highest priority that has a pending transmission request is loaded into the transmit shift
register by the message handler and the transmission is started. The message object's NEWDAT bit
in the CANNWDAn register is cleared. After a successful transmission, and if no new data was
written to the message object since the start of the transmission, the TXRQST bit in the CANTXRQn
register is cleared. If the CAN controller is configured to interrupt on a successful transmission of a
message object, (the TXIE bit in the CAN IFn Message Control (CANIFnMCTL) register is set),
the INTPND bit in the CANIFnMCTL register is set after a successful transmission. If the CAN
module has lost the arbitration or if an error occurred during the transmission, the message is
re-transmitted as soon as the CAN bus is free again. If, meanwhile, the transmission of a message
with higher priority has been requested, the messages are transmitted in the order of their priority.
18.3.4
Configuring a Transmit Message Object
The following steps illustrate how to configure a transmit message object.
1. In the CAN IFn Command Mask (CANIFnCMASK) register:
■ Set the WRNRD bit to specify a write to the CANIFnCMASK register; specify whether to
transfer the IDMASK, DIR, and MXTD of the message object into the CAN IFn registers using
the MASK bit
■ Specify whether to transfer the ID, DIR, XTD, and MSGVAL of the message object into the
interface registers using the ARB bit
■ Specify whether to transfer the control bits into the interface registers using the CONTROL
bit
■ Specify whether to clear the INTPND bit in the CANIFnMCTL register using the CLRINTPND
bit
■ Specify whether to clear the NEWDAT bit in the CANNWDAn register using the NEWDAT bit
■ Specify which bits to transfer using the DATAA and DATAB bits
2. In the CANIFnMSK1 register, use the MSK[15:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[15:0] in this
register are used for bits [15:0] of the 29-bit message identifier and are not used for an 11-bit
identifier. A value of 0x00 enables all messages to pass through the acceptance filtering. Also
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note that in order for these bits to be used for acceptance filtering, they must be enabled by
setting the UMASK bit in the CANIFnMCTL register.
3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. For a 29-bit identifier, configure ID[15:0] in the CANIFnARB1 register to are used for bits
[15:0] of the message identifier and ID[12:0] in the CANIFnARB2 register to are used for
bits [28:16] of the message identifier. Set the XTD bit to indicate an extended identifier; set the
DIR bit to indicate transmit; and set the MSGVAL bit to indicate that the message object is valid.
5. For an 11-bit identifier, disregard the CANIFnARB1 register and configure ID[12:2] in the
CANIFnARB2 register to are used for bits [10:0] of the message identifier. Clear the XTD bit to
indicate a standard identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to
indicate that the message object is valid.
6. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the TXIE bit to enable the INTPND bit to be set after a successful transmission
■ Optionally set the RMTEN bit to enable the TXRQST bit to be set on the reception of a matching
remote frame allowing automatic transmission
■ Set the EOB bit for a single message object
■ Configure the DLC[3:0] field to specify the size of the data frame. Take care during this
configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
7. Load the data to be transmitted into the CAN IFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1,
CANIFnDB2) registers. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1
register.
8. Program the number of the message object to be transmitted in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register.
9. When everything is properly configured, set the TXRQST bit in the CANIFnMCTL register. Once
this bit is set, the message object is available to be transmitted, depending on priority and bus
availability. Note that setting the RMTEN bit in the CANIFnMCTL register can also start message
transmission if a matching remote frame has been received.
18.3.5
Updating a Transmit Message Object
The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface
Registers and neither the MSGVAL bit in the CANIFnARB2 register nor the TXRQST bits in the
CANIFnMCTL register have to be cleared before the update.
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Even if only some of the data bytes are to be updated, all four bytes of the corresponding
CANIFnDAn/CANIFnDBn register have to be valid before the content of that register is transferred
to the message object. Either the CPU must write all four bytes into the CANIFnDAn/CANIFnDBn
register or the message object is transferred to the CANIFnDAn/CANIFnDBn register before the
CPU writes the new data bytes.
In order to only update the data in a message object, the WRNRD, DATAA and DATAB bits in the
CANIFnMSKn register are set, followed by writing the updated data into CANIFnDA1, CANIFnDA2,
CANIFnDB1, and CANIFnDB2 registers, and then the number of the message object is written to
the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. To begin transmission
of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register.
To prevent the clearing of the TXRQST bit in the CANIFnMCTL register at the end of a transmission
that may already be in progress while the data is updated, the NEWDAT and TXRQST bits have to be
set at the same time in the CANIFnMCTL register. When these bits are set at the same time, NEWDAT
is cleared as soon as the new transmission has started.
18.3.6
Accepting Received Message Objects
When the arbitration and control field (the ID and XTD bits in the CANIFnARB2 and the RMTEN and
DLC[3:0] bits of the CANIFnMCTL register) of an incoming message is completely shifted into
the CAN controller, the message handling capability of the controller starts scanning the message
RAM for a matching valid message object. To scan the message RAM for a matching message
object, the controller uses the acceptance filtering programmed through the mask bits in the
CANIFnMSKn register and enabled using the UMASK bit in the CANIFnMCTL register. Each valid
message object, starting with object 1, is compared with the incoming message to locate a matching
message object in the message RAM. If a match occurs, the scanning is stopped and the message
handler proceeds depending on whether it is a data frame or remote frame that was received.
18.3.7
Receiving a Data Frame
The message handler stores the message from the CAN controller receive shift register into the
matching message object in the message RAM. The data bytes, all arbitration bits, and the DLC bits
are all stored into the corresponding message object. In this manner, the data bytes are connected
with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register
is set to indicate that new data has been received. The CPU should clear this bit when it reads the
message object to indicate to the controller that the message has been received, and the buffer is
free to receive more messages. If the CAN controller receives a message and the NEWDAT bit is
already set, the MSGLST bit in the CANIFnMCTL register is set to indicate that the previous data
was lost. If the system requires an interrupt on successful reception of a frame, the RXIE bit of the
CANIFnMCTL register should be set. In this case, the INTPND bit of the same register is set, causing
the CANINT register to point to the message object that just received a message. The TXRQST bit
of this message object should be cleared to prevent the transmission of a remote frame.
18.3.8
Receiving a Remote Frame
A remote frame contains no data, but instead specifies which object should be transmitted. When
a remote frame is received, three different configurations of the matching message object have to
be considered:
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Table 18-3. Message Object Configurations
Configuration in CANIFnMCTL
■
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object is set. The rest of the message object remains
unchanged, and the controller automatically transfers the data in
RMTEN = 1 (set the TXRQST bit of the
the message object as soon as possible.
CANIFnMCTL register at reception of the frame
to enable transmission)
■
UMASK = 1 or 0
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object remains unchanged, and the remote frame is
ignored. This remote frame is disabled, the data is not transferred
RMTEN = 0 (do not change the TXRQST bit of the and nothing indicates that the remote frame ever happened.
CANIFnMCTL register at reception of the frame)
■
■
UMASK = 0 (ignore mask in the CANIFnMSKn
register)
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object is cleared. The arbitration and control field (ID +
XTD + RMTEN + DLC) from the shift register is stored into the message
RMTEN = 0 (do not change the TXRQST bit of the object in the message RAM, and the NEWDAT bit of this message
CANIFnMCTL register at reception of the frame) object is set. The data field of the message object remains
unchanged; the remote frame is treated similar to a received data
UMASK = 1 (use mask (MSK, MXTD, and MDIR in
frame. This mode is useful for a remote data request from another
the CANIFnMSKn register) for acceptance filtering)
®
CAN device for which the Stellaris controller does not have readily
available data. The software must fill the data and answer the frame
manually.
■
■
18.3.9
Description
Receive/Transmit Priority
The receive/transmit priority for the message objects is controlled by the message number. Message
object 1 has the highest priority, while message object 32 has the lowest priority. If more than one
transmission request is pending, the message objects are transmitted in order based on the message
object with the lowest message number. This prioritization is separate from that of the message
identifier which is enforced by the CAN bus. As a result, if message object 1 and message object
2 both have valid messages to be transmitted, message object 1 is always transmitted first regardless
of the message identifier in the message object itself.
18.3.10
Configuring a Receive Message Object
The following steps illustrate how to configure a receive message object.
1. Program the CAN IFn Command Mask (CANIFnCMASK) register as described in the
“Configuring a Transmit Message Object” on page 761 section, except that the WRNRD bit is set
to specify a write to the message RAM.
2. Program the CANIFnMSK1and CANIFnMSK2 registers as described in the “Configuring a
Transmit Message Object” on page 761 section to configure which bits are used for acceptance
filtering. Note that in order for these bits to be used for acceptance filtering, they must be enabled
by setting the UMASK bit in the CANIFnMCTL register.
3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
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the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. Program the CANIFnARB1 and CANIFnARB2 registers as described in the “Configuring a
Transmit Message Object” on page 761 section to program XTD and ID bits for the message
identifier to be received; set the MSGVAL bit to indicate a valid message; and clear the DIR bit
to specify receive.
5. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the RXIE bit to enable the INTPND bit to be set after a successful reception
■ Clear the RMTEN bit to leave the TXRQST bit unchanged
■ Set the EOB bit for a single message object
■ Configure the DLC[3:0] field to specify the size of the data frame
Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
6. Program the number of the message object to be received in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register. Reception of the message object begins as soon
as a matching frame is available on the CAN bus.
When the message handler stores a data frame in the message object, it stores the received Data
Length Code and eight data bytes in the CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2
register. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. If the
Data Length Code is less than 8, the remaining bytes of the message object are overwritten by
unspecified values.
The CAN mask registers can be used to allow groups of data frames to be received by a message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by
a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register
should be set if only 29-bit extended identifiers are expected by this message object.
18.3.11
Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CANIFnCMSK register and then writes the number of
the message object to the CANIFnCRQ register. That combination transfers the whole received
message from the message RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn,
and CANIFnMCTL). Additionally, the NEWDAT and INTPND bits are cleared in the message RAM,
acknowledging that the message has been read and clearing the pending interrupt generated by
this message object.
If the message object uses masks for acceptance filtering, the CANIFnARBn registers show the
full, unmasked ID for the received message.
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The NEWDAT bit in the CANIFnMCTL register shows whether a new message has been received
since the last time this message object was read. The MSGLST bit in the CANIFnMCTL register
shows whether more than one message has been received since the last time this message object
was read. MSGLST is not automatically cleared, and should be cleared by software after reading its
status.
Using a remote frame, the CPU may request new data from another CAN node on the CAN bus.
Setting the TXRQST bit of a receive object causes the transmission of a remote frame with the receive
object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be
transmitted, the TXRQST bit is automatically reset. This prevents the possible loss of data when the
other device on the CAN bus has already transmitted the data slightly earlier than expected.
18.3.11.1 Configuration of a FIFO Buffer
With the exception of the EOB bit in the CANIFnMCTL register, the configuration of receive message
objects belonging to a FIFO buffer is the same as the configuration of a single receive message
object (see “Configuring a Receive Message Object” on page 764). To concatenate two or more
message objects into a FIFO buffer, the identifiers and masks (if used) of these message objects
have to be programmed to matching values. Due to the implicit priority of the message objects, the
message object with the lowest message object number is the first message object in a FIFO buffer.
The EOB bit of all message objects of a FIFO buffer except the last one must be cleared. The EOB
bit of the last message object of a FIFO buffer is set, indicating it is the last entry in the buffer.
18.3.11.2 Reception of Messages with FIFO Buffers
Received messages with identifiers matching to a FIFO buffer are stored starting with the message
object with the lowest message number. When a message is stored into a message object of a
FIFO buffer, the NEWDAT of the CANIFnMCTL register bit of this message object is set. By setting
NEWDAT while EOB is clear, the message object is locked and cannot be written to by the message
handler until the CPU has cleared the NEWDAT bit. Messages are stored into a FIFO buffer until the
last message object of this FIFO buffer is reached. Until all of the preceding message objects have
been released by clearing the NEWDAT bit, all further messages for this FIFO buffer are written into
the last message object of the FIFO buffer and therefore overwrite previous messages.
18.3.11.3 Reading from a FIFO Buffer
When the CPU transfers the contents of a message object from a FIFO buffer by writing its number
to the CANIFnCRQ register, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should
be set such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the
read. The values of these bits in the CANIFnMCTL register always reflect the status of the message
object before the bits are cleared. To assure the correct function of a FIFO buffer, the CPU should
read out the message objects starting with the message object with the lowest message number.
When reading from the FIFO buffer, the user should be aware that a new received message could
be placed in the location of any message object for which the NEWDAT bit of the CANIFnMCTL
register is clear. As a result, the order of the received messages in the FIFO is not guaranteed.
Figure 18-3 on page 767 shows how a set of message objects which are concatenated to a FIFO
Buffer can be handled by the CPU.
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Figure 18-3. Message Objects in a FIFO Buffer
START
Message Interrupt
Read Interrupt Pointer
0x0000
Case Interrupt Pointer
else
0x8000
END
Status Change
Interrupt Handling
MNUM = Interrupt Pointer
Write MNUM to IFn Command Request
(Read Message to IFn Registers,
Reset NEWDAT = 0,
Reset INTPND = 0
Read IFn Message Control
Yes
No
NEWDAT = 1
Read Data from IFn Data A,B
EOB = 1
Yes
No
MNUM = MNUM + 1
18.3.12
Handling of Interrupts
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. The status interrupt has the highest
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priority. Among the message interrupts, the message object's interrupt with the lowest message
number has the highest priority. A message interrupt is cleared by clearing the message object's
INTPND bit in the CANIFnMCTL register or by reading the CAN Status (CANSTS) register. The
status Interrupt is cleared by reading the CANSTS register.
The interrupt identifier INTID in the CANINT register indicates the cause of the interrupt. When no
interrupt is pending, the register reads as 0x0000. If the value of the INTID field is different from 0,
then an interrupt is pending. If the IE bit is set in the CANCTL register, the interrupt line to the
interrupt controller is active. The interrupt line remains active until the INTID field is 0, meaning
that all interrupt sources have been cleared (the cause of the interrupt is reset), or until IE is cleared,
which disables interrupts from the CAN controller.
The INTID field of the CANINT register points to the pending message interrupt with the highest
interrupt priority. The SIE bit in the CANCTL register controls whether a change of the RXOK, TXOK,
and LEC bits in the CANSTS register can cause an interrupt. The EIE bit in the CANCTLregister
controls whether a change of the BOFF and EWARN bits in the CANSTS register can cause an
interrupt. The IE bit in the CANCTL register controls whether any interrupt from the CAN controller
actually generates an interrupt to the interrupt controller. The CANINT register is updated even
when the IE bit in the CANCTL register is clear, but the interrupt is not indicated to the CPU.
A value of 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN
module has updated, but not necessarily changed, the CANSTS register, indicating that either an
error or status interrupt has been generated. A write access to the CANSTS register can clear the
RXOK, TXOK, and LEC bits in that same register; however, the only way to clear the source of a
status interrupt is to read the CANSTS register.
The source of an interrupt can be determined in two ways during interrupt handling. The first is to
read the INTID bit in the CANINT register to determine the highest priority interrupt that is pending,
and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see
all of the message objects that have pending interrupts.
An interrupt service routine reading the message that is the source of the interrupt may read the
message and clear the message object's INTPND bit at the same time by setting the CLRINTPND
bit in the CANIFnCMSK register. Once the INTPND bit has been cleared, the CANINT register
contains the message number for the next message object with a pending interrupt.
18.3.13
Test Mode
A Test Mode is provided which allows various diagnostics to be performed. Test Mode is entered
by setting the TEST bit in the CANCTL register. Once in Test Mode, the TX[1:0], LBACK, SILENT
and BASIC bits in the CAN Test (CANTST) register can be used to put the CAN controller into the
various diagnostic modes. The RX bit in the CANTST register allows monitoring of the CANnRX
signal. All CANTST register functions are disabled when the TEST bit is cleared.
18.3.13.1 Silent Mode
Silent Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission
of dominant bits (Acknowledge Bits, Error Frames). The CAN Controller is put in Silent Mode setting
the SILENT bit in the CANTST register. In Silent Mode, the CAN controller is able to receive valid
data frames and valid remote frames, but it sends only recessive bits on the CAN bus and cannot
start a transmission. If the CAN Controller is required to send a dominant bit (ACK bit, overload flag,
or active error flag), the bit is rerouted internally so that the CAN Controller monitors this dominant
bit, although the CAN bus remains in recessive state.
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18.3.13.2 Loopback Mode
Loopback mode is useful for self-test functions. In Loopback Mode, the CAN Controller internally
routes the CANnTX signal on to the CANnRX signal and treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into the message buffer. The
CAN Controller is put in Loopback Mode by setting the LBACK bit in the CANTST register. To be
independent from external stimulation, the CAN Controller ignores acknowledge errors (a recessive
bit sampled in the acknowledge slot of a data/remote frame) in Loopback Mode. The actual value
of the CANnRX signal is disregarded by the CAN Controller. The transmitted messages can be
monitored on the CANnTX signal.
18.3.13.3 Loopback Combined with Silent Mode
Loopback Mode and Silent Mode can be combined to allow the CAN Controller to be tested without
affecting a running CAN system connected to the CANnTX and CANnRX signals. In this mode, the
CANnRX signal is disconnected from the CAN Controller and the CANnTX signal is held recessive.
This mode is enabled by setting both the LBACK and SILENT bits in the CANTST register.
18.3.13.4 Basic Mode
Basic Mode allows the CAN Controller to be operated without the Message RAM. In Basic Mode,
The CANIF1 registers are used as the transmit buffer. The transmission of the contents of the IF1
registers is requested by setting the BUSY bit of the CANIF1CRQ register. The CANIF1 registers
are locked while the BUSY bit is set. The BUSY bit indicates that a transmission is pending. As soon
the CAN bus is idle, the CANIF1 registers are loaded into the shift register of the CAN Controller
and transmission is started. When the transmission has completed, the BUSY bit is cleared and the
locked CANIF1 registers are released. A pending transmission can be aborted at any time by clearing
the BUSY bit in the CANIF1CRQ register while the CANIF1 registers are locked. If the CPU has
cleared the BUSY bit, a possible retransmission in case of lost arbitration or an error is disabled.
The CANIF2 Registers are used as a receive buffer. After the reception of a message, the contents
of the shift register are stored in the CANIF2 registers, without any acceptance filtering. Additionally,
the actual contents of the shift register can be monitored during the message transfer. Each time a
read message object is initiated by setting the BUSY bit of the CANIF2CRQ register, the contents
of the shift register are stored into the CANIF2 registers.
In Basic Mode, all message-object-related control and status bits and of the control bits of the
CANIFnCMSK registers are not evaluated. The message number of the CANIFnCRQ registers is
also not evaluated. In the CANIF2MCTL register, the NEWDAT and MSGLST bits retain their function,
the DLC[3:0] field shows the received DLC, the other control bits are cleared.
Basic Mode is enabled by setting the BASIC bit in the CANTST register.
18.3.13.5 Transmit Control
Software can directly override control of the CANnTX signal in four different ways.
■ CANnTX is controlled by the CAN Controller
■ The sample point is driven on the CANnTX signal to monitor the bit timing
■ CANnTX drives a low value
■ CANnTX drives a high value
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The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check
the physical layer of the CAN bus.
The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register.
The three test functions for the CANnTX signal interfere with all CAN protocol functions. TX[1:0]
must be cleared when CAN message transfer or Loopback Mode, Silent Mode, or Basic Mode are
selected.
18.3.14
Bit Timing Configuration Error Considerations
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly. In many cases, the CAN bit
synchronization amends a faulty configuration of the CAN bit timing to such a degree that only
occasionally an error frame is generated. In the case of arbitration, however, when two or more
CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the
transmitters to become error passive. The analysis of such sporadic errors requires a detailed
knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on
the CAN bus.
18.3.15
Bit Time and Bit Rate
The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member
of the CAN network has its own clock generator. The timing parameter of the bit time can be
configured individually for each CAN node, creating a common bit rate even though the CAN nodes'
oscillator periods may be different.
Because of small variations in frequency caused by changes in temperature or voltage and by
deteriorating components, these oscillators are not absolutely stable. As long as the variations
remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the
different bit rates by periodically resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure
18-4 on page 771): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable
number of time quanta (see Table 18-4 on page 771). The length of the time quantum (tq), which is
the basic time unit of the bit time, is defined by the CAN controller's system clock (fsys) and the
Baud Rate Prescaler (BRP):
tq = BRP / fsys
The CAN module's system clock fsys is the frequency of its CAN module clock input.
The Synchronization Segment Sync is that part of the bit time where edges of the CAN bus level
are expected to occur; the distance between an edge that occurs outside of Sync and the Sync is
called the phase error of that edge.
The Propagation Time Segment Prop is intended to compensate for the physical delay times within
the CAN network.
The Phase Buffer Segments Phase1 and Phase2 surround the Sample Point.
The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the
Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase
errors.
A given bit rate may be met by different bit-time configurations, but for the proper function of the
CAN network, the physical delay times and the oscillator's tolerance range have to be considered.
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Figure 18-4. CAN Bit Time
Nominal CAN Bit Time
a
b
TSEG1
Sync
Prop
TSEG2
Phase1
c
1 Time
Quantum
q)
(tq
Phase2
Sample
Point
a. TSEG1 = Prop + Phase1
b. TSEG2 = Phase2
c. Phase1 = Phase2 or Phase1 + 1 = Phase2
a
Table 18-4. CAN Protocol Ranges
Parameter
Range
Remark
BRP
[1 .. 64]
Defines the length of the time quantum tq. The CANBRPE register can
be used to extend the range to 1024.
Sync
1 tq
Fixed length, synchronization of bus input to system clock
Prop
[1 .. 8] tq
Compensates for the physical delay times
Phase1
[1 .. 8] tq
May be lengthened temporarily by synchronization
Phase2
[1 .. 8] tq
May be shortened temporarily by synchronization
SJW
[1 .. 4] tq
May not be longer than either Phase Buffer Segment
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. In the
CANBIT register, the four components TSEG2, TSEG1, SJW, and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1..n],
values in the range of [0..n-1] are programmed. That way, for example, SJW (functional range of
[1..4]) is represented by only two bits in the SJW bit field. Table 18-5 shows the relationship between
the CANBIT register values and the parameters.
Table 18-5. CANBIT Register Values
CANBIT Register Field
Setting
TSEG2
Phase2 - 1
TSEG1
Prop + Phase1 - 1
SJW
SJW - 1
BRP
BRP
Therefore, the length of the bit time is (programmed values):
[TSEG1 + TSEG2 + 3] × tq
or (functional values):
[Sync + Prop + Phase1 + Phase2] × tq
The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud
rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time
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unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the sample point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
The CAN controller translates messages to and from frames. In addition, the controller generates
and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks
the CRC code, performs the error management, and decides which type of synchronization is to be
used. The bit value is received or transmitted at the sample point. The information processing time
(IPT) is the time after the sample point needed to calculate the next bit to be transmitted on the CAN
bus. The IPT includes any of the following: retrieving the next data bit, handling a CRC bit, determining
if bit stuffing is required, generating an error flag or simply going idle.
The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is
the lower limit of the programmed length of Phase2. In case of synchronization, Phase2 may be
shortened to a value less than IPT, which does not affect bus timing.
18.3.16
Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the required bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is Prop. Its length depends on the delay times measured
in the system. A maximum bus length as well as a maximum node delay has to be defined for
expandable CAN bus systems. The resulting time for Prop is converted into time quanta (rounded
up to the nearest integer multiple of tq).
Sync is 1 tq long (fixed), which leaves (bit time - Prop - 1) tq for the two Phase Buffer Segments. If
the number of remaining tq is even, the Phase Buffer Segments have the same length, that is,
Phase2 = Phase1, else Phase2 = Phase1 + 1.
The minimum nominal length of Phase2 has to be regarded as well. Phase2 may not be shorter
than the CAN controller's Information Processing Time, which is, depending on the actual
implementation, in the range of [0..2] tq.
The length of the synchronization jump width is set to the least of 4, Phase1 or Phase2.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formula
given below:
(1 − df ) × fnom ≤ fosc ≤ (1 + df ) × fnom
where:
df
≤
(Phase _ seg1, Phase _ seg2) min
2 × (13 × tbit − Phase _ Seg 2)
■ df = Maximum tolerance of oscillator frequency
■ fosc
Actual=oscillator
df =max
2 × dffrequency
× fnom
■ fnom = Nominal oscillator frequency
Maximum frequency tolerance must take into account the following formulas:
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− )df
× fnom
≤ fosc
+ )df
× fnom
(1 −(1df
× )fnom
≤ fosc
≤ (1≤ +(1df
× )fnom
(Phase
_ seg
1, Phase
_ seg
2) min
(Phase
_ seg
1, Phase
_ seg
2) min
df df
≤ ≤ 2 × (13 × tbit − Phase _ Seg 2)
2 × (13 × tbit − Phase _ Seg 2)
× df
× fnom
df df
maxmax
= 2=× 2df
× fnom
where:
■ Phase1 and Phase2 are from Table 18-4 on page 771
■ tbit = Bit Time
■ dfmax = Maximum difference between two oscillators
If more than one configuration is possible, that configuration allowing the highest oscillator tolerance
range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol-compliant configuration of the
CAN bit timing.
18.3.16.1 Example for Bit Timing at High Baud Rate
In this example, the frequency of CAN clock is 25 MHz, and the bit rate is 1 Mbps.
tq 200 ns = (Baud rate Prescaler)/CAN Clock
tSync = 1 × tq = 200 ns
\\fixed at 1 time quanta
delay
delay
delay
tProp
\\400 is next integer multiple of tq
of bus driver 50 ns
of receiver circuit 30 ns
of bus line (40m) 220 ns
400 ns = 2 × tq
bit time = tSync +
bit time = tSync +
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase1 = 200 ns
tPhase2 = 200 ns
tTSeg1
tTSeg1
tTSeg1
tTSeg2
=
=
=
=
tTSeg1 + tTSeg2
tProp + tPhase 1 + tPhase2
= bit time - tSync - tProp
= 1000 ns - 200 ns - 400 ns
= 400 ns
\\tPhase1 = tPhase2
tProp + tPhase1
400 ns + 200 ns
600 ns = 3 × tq
tPhase2
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tTSeg2 = (Information Processing Time + 1) × tq
tTSeg2 = 200 ns = 1 × tq
\\Assumes IPT=0
tSJW = 1 × tq = 200 ns
\\Least of 4, Phase1 and Phase2 = 1
In the above example, the bit field values for the CANBIT register are:
= TSeg2 -1
TSEG2
= 1-1
=0
= TSeg1 -1
TSEG1
= 3-1
=2
= SJW -1
SJW
= 1-1
=0
= Baud rate prescaler - 1
BRP
= 5-1
=4
The final value programmed into the CANBIT register = 0x0204.
18.3.16.2 Example for Bit Timing at Low Baud Rate
In this example, the frequency of the CAN clock is 50 MHz, and the bit rate is 100 Kbps.
tq 1 µs = (Baud rate Prescaler)/CAN Clock
tSync = 1 × tq = 1 µs
\\fixed at 1 time quanta
delay
delay
delay
tProp
\\1 µs is next integer multiple of tq
of bus driver 200 ns
of receiver circuit 80 ns
of bus line (40m) 220 ns
1 µs = 1 × tq
bit time = tSync +
bit time = tSync +
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase 1 + tPhase2
tPhase1 = 4 µs
tPhase2 = 4 µs
tTSeg1
tTSeg1
tTSeg1
tTSeg2
tTSeg2
tTSeg2
=
=
=
=
=
=
tTSeg1 + tTSeg2
tProp + tPhase 1 + tPhase2
= bit time - tSync - tProp
= 10 µs - 1 µs - 1 µs
= 8 µs
\\tPhase1 = tPhase2
tProp + tPhase1
1 µs + 4 µs
5 µs = 5 × tq
tPhase2
(Information Processing Time + 4) × tq
4 µs = 4 × tq
\\Assumes IPT=0
tSJW = 4 × tq = 4 µs
\\Least of 4, Phase1, and Phase2
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= TSeg2 -1
TSEG2
= 4-1
=3
= TSeg1 -1
TSEG1
= 5-1
=4
= SJW -1
SJW
= 4-1
=3
= Baud rate prescaler - 1
BRP
= 50-1
=49
The final value programmed into the CANBIT register = 0x34F1.
18.4
Register Map
Table 18-6 on page 775 lists the registers. All addresses given are relative to the CAN base address
of:
■ CAN0: 0x4004.0000
■ CAN1: 0x4004.1000
Note that the CAN controller clock must be enabled before the registers can be programmed (see
page 171).
Table 18-6. CAN Register Map
Offset
Name
Type
Reset
Description
See
page
0x000
CANCTL
R/W
0x0000.0001
CAN Control
777
0x004
CANSTS
R/W
0x0000.0000
CAN Status
779
0x008
CANERR
RO
0x0000.0000
CAN Error Counter
782
0x00C
CANBIT
R/W
0x0000.2301
CAN Bit Timing
783
0x010
CANINT
RO
0x0000.0000
CAN Interrupt
785
0x014
CANTST
R/W
0x0000.0000
CAN Test
786
0x018
CANBRPE
R/W
0x0000.0000
CAN Baud Rate Prescaler Extension
788
0x020
CANIF1CRQ
R/W
0x0000.0001
CAN IF1 Command Request
789
0x024
CANIF1CMSK
R/W
0x0000.0000
CAN IF1 Command Mask
791
0x028
CANIF1MSK1
R/W
0x0000.FFFF
CAN IF1 Mask 1
794
0x02C
CANIF1MSK2
R/W
0x0000.FFFF
CAN IF1 Mask 2
795
0x030
CANIF1ARB1
R/W
0x0000.0000
CAN IF1 Arbitration 1
797
0x034
CANIF1ARB2
R/W
0x0000.0000
CAN IF1 Arbitration 2
798
0x038
CANIF1MCTL
R/W
0x0000.0000
CAN IF1 Message Control
800
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Table 18-6. CAN Register Map (continued)
Name
Type
Reset
0x03C
CANIF1DA1
R/W
0x0000.0000
CAN IF1 Data A1
803
0x040
CANIF1DA2
R/W
0x0000.0000
CAN IF1 Data A2
803
0x044
CANIF1DB1
R/W
0x0000.0000
CAN IF1 Data B1
803
0x048
CANIF1DB2
R/W
0x0000.0000
CAN IF1 Data B2
803
0x080
CANIF2CRQ
R/W
0x0000.0001
CAN IF2 Command Request
789
0x084
CANIF2CMSK
R/W
0x0000.0000
CAN IF2 Command Mask
791
0x088
CANIF2MSK1
R/W
0x0000.FFFF
CAN IF2 Mask 1
794
0x08C
CANIF2MSK2
R/W
0x0000.FFFF
CAN IF2 Mask 2
795
0x090
CANIF2ARB1
R/W
0x0000.0000
CAN IF2 Arbitration 1
797
0x094
CANIF2ARB2
R/W
0x0000.0000
CAN IF2 Arbitration 2
798
0x098
CANIF2MCTL
R/W
0x0000.0000
CAN IF2 Message Control
800
0x09C
CANIF2DA1
R/W
0x0000.0000
CAN IF2 Data A1
803
0x0A0
CANIF2DA2
R/W
0x0000.0000
CAN IF2 Data A2
803
0x0A4
CANIF2DB1
R/W
0x0000.0000
CAN IF2 Data B1
803
0x0A8
CANIF2DB2
R/W
0x0000.0000
CAN IF2 Data B2
803
0x100
CANTXRQ1
RO
0x0000.0000
CAN Transmission Request 1
804
0x104
CANTXRQ2
RO
0x0000.0000
CAN Transmission Request 2
804
0x120
CANNWDA1
RO
0x0000.0000
CAN New Data 1
805
0x124
CANNWDA2
RO
0x0000.0000
CAN New Data 2
805
0x140
CANMSG1INT
RO
0x0000.0000
CAN Message 1 Interrupt Pending
806
0x144
CANMSG2INT
RO
0x0000.0000
CAN Message 2 Interrupt Pending
806
0x160
CANMSG1VAL
RO
0x0000.0000
CAN Message 1 Valid
807
0x164
CANMSG2VAL
RO
0x0000.0000
CAN Message 2 Valid
807
18.5
Description
See
page
Offset
CAN Register Descriptions
The remainder of this section lists and describes the CAN registers, in numerical order by address
offset. There are two sets of Interface Registers that are used to access the Message Objects in
the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used
to queue transactions.
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Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is cleared, each time a sequence of 11 High bits has been
monitored, a BITERROR0 code is written to the CANSTS register (the LEC field = 0x5), enabling
the CPU to readily check whether the CAN bus is stuck Low or continuously disturbed, and to monitor
the proceeding of the bus-off recovery sequence.
CAN Control (CANCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x000
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TEST
CCE
DAR
reserved
EIE
SIE
IE
INIT
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
TEST
R/W
0
6
5
CCE
DAR
R/W
R/W
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Test Mode Enable
Value
Description
0
The CAN controller is operating normally.
1
The CAN controller is in test mode.
Configuration Change Enable
Value
Description
0
Write accesses to the CANBIT register are not allowed.
1
Write accesses to the CANBIT register are allowed if the
INIT bit is 1.
Disable Automatic-Retransmission
Value
Description
0
Auto-retransmission of disturbed messages is enabled.
1
Auto-retransmission is disabled.
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Bit/Field
Name
Type
Reset
4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
EIE
R/W
0
Error Interrupt Enable
2
1
0
SIE
IE
INIT
R/W
R/W
R/W
0
0
1
Description
Value
Description
0
No error status interrupt is generated.
1
A change in the BOFF or EWARN bits in the CANSTS
register generates an interrupt.
Status Interrupt Enable
Value
Description
0
No status interrupt is generated.
1
An interrupt is generated when a message has successfully
been transmitted or received, or a CAN bus error has been
detected. A change in the TXOK, RXOK or LEC bits in the
CANSTS register generates an interrupt.
CAN Interrupt Enable
Value
Description
0
Interrupts disabled.
1
Interrupts enabled.
Initialization
Value
Description
0
Normal operation.
1
Initialization started.
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Register 2: CAN Status (CANSTS), offset 0x004
Important: Use caution when reading this register. Performing a read may change bit status.
The status register contains information for interrupt servicing such as Bus-Off, error count threshold,
and error types.
The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This
field is cleared when a message has been transferred (reception or transmission) without error. The
unused error code 0x7 may be written by the CPU to manually set this field to an invalid error so
that it can be checked for a change later.
An error interrupt is generated by the BOFF and EWARN bits, and a status interrupt is generated by
the RXOK, TXOK, and LEC bits, if the corresponding enable bits in the CAN Control (CANCTL)
register are set. A change of the EPASS bit or a write to the RXOK, TXOK, or LEC bits does not
generate an interrupt.
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is
pending.
CAN Status (CANSTS)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
BOFF
RO
0
6
EWARN
RO
0
RO
0
7
6
5
4
3
BOFF
EWARN
EPASS
RXOK
TXOK
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
LEC
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bus-Off Status
Value
Description
0
The CAN controller is not in bus-off state.
1
The CAN controller is in bus-off state.
Warning Status
Value
Description
0
Both error counters are below the error warning limit of
96.
1
At least one of the error counters has reached the error
warning limit of 96.
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Bit/Field
Name
Type
Reset
5
EPASS
RO
0
4
RXOK
R/W
0
Description
Error Passive
Value
Description
0
The CAN module is in the Error Active state, that is, the
receive or transmit error count is less than or equal to 127.
1
The CAN module is in the Error Passive state, that is, the
receive or transmit error count is greater than 127.
Received a Message Successfully
Value
Description
0
Since this bit was last cleared, no message has been
successfully received.
1
Since this bit was last cleared, a message has been
successfully received, independent of the result of the
acceptance filtering.
This bit must be cleared by writing a 0 to it.
3
TXOK
R/W
0
Transmitted a Message Successfully
Value
Description
0
Since this bit was last cleared, no message has been
successfully transmitted.
1
Since this bit was last cleared, a message has been
successfully transmitted error-free and acknowledged by
at least one other node.
This bit must be cleared by writing a 0 to it.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
2:0
LEC
R/W
0x0
Description
Last Error Code
This is the type of the last error to occur on the CAN bus.
Value
Description
0x0
No Error
0x1
Stuff Error
More than 5 equal bits in a sequence have occurred in a part
of a received message where this is not allowed.
0x2
Format Error
A fixed format part of the received frame has the wrong
format.
0x3
ACK Error
The message transmitted was not acknowledged by another
node.
0x4
Bit 1 Error
When a message is transmitted, the CAN controller monitors
the data lines to detect any conflicts. When the arbitration
field is transmitted, data conflicts are a part of the arbitration
protocol. When other frame fields are transmitted, data
conflicts are considered errors.
A Bit 1 Error indicates that the device wanted to send a High
level (logical 1) but the monitored bus value was Low (logical
0).
0x5
Bit 0 Error
A Bit 0 Error indicates that the device wanted to send a Low
level (logical 0), but the monitored bus value was High (logical
1).
During bus-off recovery, this status is set each time a
sequence of 11 High bits has been monitored. By checking
for this status, software can monitor the proceeding of the
bus-off recovery sequence without any disturbances to the
bus.
0x6
CRC Error
The CRC checksum was incorrect in the received message,
indicating that the calculated value received did not match
the calculated CRC of the data.
0x7
No Event
When the LEC bit shows this value, no CAN bus event was
detected since this value was written to the LEC field.
May 24, 2010
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Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x008
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RP
Type
Reset
RO
0
REC
TEC
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
RP
RO
0
14:8
REC
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Received Error Passive
Value
Description
0
The Receive Error counter is below the Error Passive
level (127 or less).
1
The Receive Error counter has reached the Error Passive
level (128 or greater).
Receive Error Counter
This field contains the state of the receiver error counter (0 to 127).
7:0
TEC
RO
0x00
Transmit Error Counter
This field contains the state of the transmit error counter (0 to 255).
782
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 4: CAN Bit Timing (CANBIT), offset 0x00C
This register is used to program the bit width and bit quantum. Values are programmed to the system
clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL
register. See “Bit Time and Bit Rate” on page 770 for more information.
CAN Bit Timing (CANBIT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x00C
Type R/W, reset 0x0000.2301
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
TSEG2
reserved
Type
Reset
RO
0
R/W
0
R/W
1
TSEG1
Bit/Field
Name
Type
Reset
31:15
reserved
RO
0x0000
14:12
TSEG2
R/W
0x2
SJW
BRP
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Time Segment after Sample Point
0x00-0x07: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x2 means that 3 (2+1) bit time
quanta are defined for Phase2 (see Figure 18-4 on page 771). The bit
time quanta is defined by the BRP field.
11:8
TSEG1
R/W
0x3
Time Segment Before Sample Point
0x00-0x0F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x3 means that 4 (3+1) bit time
quanta are defined for Phase1 (see Figure 18-4 on page 771). The bit
time quanta is defined by the BRP field.
7:6
SJW
R/W
0x0
(Re)Synchronization Jump Width
0x00-0x03: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
During the start of frame (SOF), if the CAN controller detects a phase
error (misalignment), it can adjust the length of TSEG2 or TSEG1 by the
value in SJW. So the reset value of 0 adjusts the length by 1 bit time
quanta.
May 24, 2010
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Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
5:0
BRP
R/W
0x1
Description
Baud Rate Prescaler
The value by which the oscillator frequency is divided for generating the
bit time quanta. The bit time is built up from a multiple of this quantum.
0x00-0x03F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
BRP defines the number of CAN clock periods that make up 1 bit time
quanta, so the reset value is 2 bit time quanta (1+1).
The CANBRPE register can be used to further divide the bit time.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 5: CAN Interrupt (CANINT), offset 0x010
This register indicates the source of the interrupt.
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains
pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in
the CANCTL register is set, the interrupt is active. The interrupt line remains active until the INTID
field is cleared by reading the CANSTS register, or until the IE bit in the CANCTL register is cleared.
Note:
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register,
if it is pending.
CAN Interrupt (CANINT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INTID
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
INTID
RO
0x0000
Interrupt Identifier
The number in this field indicates the source of the interrupt.
Value
Description
0x0000
No interrupt pending
0x0001-0x0020
Number of the message object that
caused the interrupt
0x0021-0x7FFF
Reserved
0x8000
Status Interrupt
0x8001-0xFFFF
Reserved
May 24, 2010
785
Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Register 6: CAN Test (CANTST), offset 0x014
This register is used for self-test and external pin access. It is write-enabled by setting the TEST bit
in the CANCTL register. Different test functions may be combined, however, CAN transfers are
affected if the TX bits in this register are not zero.
CAN Test (CANTST)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
LBACK
SILENT
BASIC
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RX
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
RX
RO
0
6:5
TX
R/W
0x0
TX
R/W
0
R/W
0
reserved
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive Observation
Value
Description
0
The CANnRx pin is low.
1
The CANnRx pin is high.
Transmit Control
Overrides control of the CANnTx pin.
Value
Description
0x0
CAN Module Control
CANnTx is controlled by the CAN module; default
operation
0x1
Sample Point
The sample point is driven on the CANnTx signal. This
mode is useful to monitor bit timing.
0x2
Driven Low
CANnTx drives a low value. This mode is useful for
checking the physical layer of the CAN bus.
0x3
Driven High
CANnTx drives a high value. This mode is useful for
checking the physical layer of the CAN bus.
786
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4
LBACK
R/W
0
3
2
1:0
SILENT
BASIC
reserved
R/W
R/W
RO
0
0
0x0
Description
Loopback Mode
Value
Description
0
Loopback mode is disabled.
1
Loopback mode is enabled. In loopback mode, the data
from the transmitter is routed into the receiver. Any data
on the receive input is ignored.
Silent Mode
Value
Description
0
Silent mode is disabled.
1
Silent mode is enabled. In silent mode, the CAN controller
does not transmit data but instead monitors the bus. This
mode is also known as Bus Monitor mode.
Basic Mode
Value
Description
0
Basic mode is disabled.
1
Basic mode is enabled. In basic mode, software should
use the CANIF1 registers as the transmit buffer and use
the CANIF2 registers as the receive buffer.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
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Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018
This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is
write-enabled by setting the CCE bit in the CANCTL register.
CAN Baud Rate Prescaler Extension (CANBRPE)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
BRPE
R/W
0x0
BRPE
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Baud Rate Prescaler Extension
0x00-0x0F: Extend the BRP bit in the CANBIT register to values up to
1023. The actual interpretation by the hardware is one more than the
value programmed by BRPE (MSBs) and BRP (LSBs).
788
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080
A message transfer is started as soon as there is a write of the message object number to the MNUM
field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY
bit is automatically set to indicate that a transfer between the CAN Interface Registers and the
internal message RAM is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer
between the interface register and the message RAM completes, which then clears the BUSY bit.
CAN IF1 Command Request (CANIF1CRQ)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x020
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
BUSY
Type
Reset
RO
0
reserved
RO
0
MNUM
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
BUSY
RO
0
14:6
reserved
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Busy Flag
Value
Description
0
This bit is cleared when read/write action has finished.
1
This bit is set when a write occurs to the message
number in this register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
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Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
Description
5:0
MNUM
R/W
0x01
Message Number
Selects one of the 32 message objects in the message RAM for data
transfer. The message objects are numbered from 1 to 32.
Value
Description
0x00
Reserved
0 is not a valid message number; it is interpreted
as 0x20, or object 32.
0x01-0x20
Message Number
Indicates specified message object 1 to 32.
0x21-0x3F
Reserved
Not a valid message number; values are shifted and
it is interpreted as 0x01-0x1F.
790
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
Reading the Command Mask registers provides status for various functions. Writing to the Command
Mask registers specifies the transfer direction and selects which buffer registers are the source or
target of the data transfer.
Note that when a read from the message object buffer occurs when the WRNRD bit is clear and the
CLRINTPND and/or NEWDAT bits are set, the interrupt pending and/or new data flags in the message
object buffer are cleared.
CAN IF1 Command Mask (CANIF1CMSK)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
DATAA
DATAB
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
WRNRD
R/W
0
6
MASK
R/W
0
WRNRD
MASK
ARB
R/W
0
R/W
0
R/W
0
RO
0
CONTROL CLRINTPND
R/W
0
R/W
0
NEWDAT /
TXRQST
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write, Not Read
Value
Description
0
Transfer the data in the CAN message object specified by
the the MNUM field in the CANIFnCRQ register into the
CANIFn registers.
1
Transfer the data in the CANIFn registers to the CAN
message object specified by the MNUM field in the CAN
Command Request (CANIFnCRQ).
Note:
Interrupt pending and new data conditions in the message
buffer can be cleared by reading from the buffer (WRNRD = 0)
when the CLRINTPND and/or NEWDAT bits are set.
Access Mask Bits
Value
Description
0
Mask bits unchanged.
1
Transfer IDMASK + DIR + MXTD of the message object
into the Interface registers.
May 24, 2010
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Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
5
ARB
R/W
0
4
3
CONTROL
CLRINTPND
R/W
R/W
0
0
Description
Access Arbitration Bits
Value
Description
0
Arbitration bits unchanged.
1
Transfer ID + DIR + XTD + MSGVAL of the message
object into the Interface registers.
Access Control Bits
Value
Description
0
Control bits unchanged.
1
Transfer control bits from the CANIFnMCTL register
into the Interface registers.
Clear Interrupt Pending Bit
The function of this bit depends on the configuration of the WRNRD bit.
Value
0
Description
If WRNRD is clear, the interrupt pending status is transferred
from the message buffer into the CANIFnMCTL register.
If WRNRD is set, the INTPND bit in the message object remains
unchanged.
1
If WRNRD is clear, the interrupt pending status is cleared in the
message buffer. Note the value of this bit that is transferred
to the CANIFnMCTL register always reflects the status of the
bits before clearing.
If WRNRD is set, the INTPND bit is cleared in the message
object.
2
NEWDAT / TXRQST
R/W
0
NEWDAT / TXRQST Bit
The function of this bit depends on the configuration of the WRNRD bit.
Value
0
Description
If WRNRD is clear, the value of the new data status is transferred
from the message buffer into the CANIFnMCTL register.
If WRNRD is set, a transmission is not requested.
1
If WRNRD is clear, the new data status is cleared in the message
buffer. Note the value of this bit that is transferred to the
CANIFnMCTL register always reflects the status of the bits
before clearing.
If WRNRD is set, a transmission is requested. Note that when
this bit is set, the TXRQST bit in the CANIFnMCTL register is
ignored.
792
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
1
DATAA
R/W
0
Description
Access Data Byte 0 to 3
The function of this bit depends on the configuration of the WRNRD bit.
Value
Description
0
Data bytes 0-3 are unchanged.
1
If WRNRD is clear, transfer data bytes 0-3 in CANIFnDA1
and CANIFnDA2 to the message object.
If WRNRD is set, transfer data bytes 0-3 in message object
to CANIFnDA1 and CANIFnDA2.
0
DATAB
R/W
0
Access Data Byte 4 to 7
The function of this bit depends on the configuration of the WRNRD bit
as follows:
Value
Description
0
Data bytes 4-7 are unchanged.
1
If WRNRD is clear, transfer data bytes 4-7 in CANIFnDA1
and CANIFnDA2 to the message object.
If WRNRD is set, transfer data bytes 4-7 in message object
to CANIFnDA1 and CANIFnDA2.
May 24, 2010
793
Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088
The mask information provided in this register accompanies the data (CANIFnDAn), arbitration
information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the
message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance
filtering. Additional mask information is contained in the CANIFnMSK2 register.
CAN IF1 Mask 1 (CANIF1MSK1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x028
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
MSK
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MSK
R/W
0xFFFF
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [15:0] of the
ID. The MSK field in the CANIFnMSK2 register are used for bits [28:16]
of the ID. When using an 11-bit identifier, these bits are ignored.
Value
Description
0
The corresponding identifier field (ID) in the message
object cannot inhibit the match in acceptance filtering.
1
The corresponding identifier field (ID) is used for
acceptance filtering.
794
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C
This register holds extended mask information that accompanies the CANIFnMSK1 register.
CAN IF1 Mask 2 (CANIF1MSK2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
MXTD
MDIR
reserved
R/W
1
R/W
1
RO
1
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
Type
Reset
MSK
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
MXTD
R/W
1
14
13
MDIR
reserved
R/W
RO
1
1
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mask Extended Identifier
Value
Description
0
The extended identifier bit (XTD in the CANIFnARB2
register) has no effect on the acceptance filtering.
1
The extended identifier bit XTD is used for acceptance
filtering.
Mask Message Direction
Value
Description
0
The message direction bit (DIR in the CANIFnARB2
register) has no effect for acceptance filtering.
1
The message direction bit DIR is used for acceptance
filtering.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
795
Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
Description
12:0
MSK
R/W
0xFF
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [28:16] of the
ID. The MSK field in the CANIFnMSK1 register are used for bits [15:0]
of the ID. When using an 11-bit identifier, MSK[12:2] are used for bits
[10:0] of the ID.
Value
Description
0
The corresponding identifier field (ID) in the message
object cannot inhibit the match in acceptance filtering.
1
The corresponding identifier field (ID) is used for
acceptance filtering.
796
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090
These registers hold the identifiers for acceptance filtering.
CAN IF1 Arbitration 1 (CANIF1ARB1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x030
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
ID
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
ID
R/W
0x0000
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, bits 15:0 of the CANIFnARB1 register
are [15:0] of the ID, while bits 12:0 of the CANIFnARB2 register are
[28:16] of the ID.
When using an 11-bit identifier, these bits are not used.
May 24, 2010
797
Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094
These registers hold information for acceptance filtering.
CAN IF1 Arbitration 2 (CANIF1ARB2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x034
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
MSGVAL
XTD
DIR
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
Type
Reset
ID
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
MSGVAL
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Message Valid
Value
Description
0
The message object is ignored by the message handler.
1
The message object is configured and ready to be
considered by the message handler within the CAN
controller.
All unused message objects should have this bit cleared during
initialization and before clearing the INIT bit in the CANCTL register.
The MSGVAL bit must also be cleared before any of the following bits
are modified or if the message object is no longer required: the ID fields
in the CANIFnARBn registers, the XTD and DIR bits in the CANIFnARB2
register, or the DLC field in the CANIFnMCTL register.
14
XTD
R/W
0
Extended Identifier
Value
Description
0
An 11-bit Standard Identifier is used for this message
object.
1
A 29-bit Extended Identifier is used for this message
object.
798
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
13
DIR
R/W
0
12:0
ID
R/W
0x000
Description
Message Direction
Value
Description
0
Receive. When the TXRQST bit in the CANIFnMCTL register
is set, a remote frame with the identifier of this message object
is received. On reception of a data frame with matching
identifier, that message is stored in this message object.
1
Transmit. When the TXRQST bit in the CANIFnMCTL register
is set, the respective message object is transmitted as a data
frame. On reception of a remote frame with matching identifier,
the TXRQST bit of this message object is set (if RMTEN=1).
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, ID[15:0] of the CANIFnARB1 register
are [15:0] of the ID, while these bits, ID[12:0], are [28:16] of the ID.
When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of
the ID. The ID field in the CANIFnARB1 register is ignored.
May 24, 2010
799
Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098
This register holds the control information associated with the message object to be sent to the
Message RAM.
CAN IF1 Message Control (CANIF1MCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
UMASK
TXIE
RXIE
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RMTEN
TXRQST
EOB
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
NEWDAT MSGLST INTPND
Type
Reset
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
NEWDAT
R/W
0
14
MSGLST
R/W
0
reserved
RO
0
RO
0
DLC
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
New Data
Value
Description
0
No new data has been written into the data portion of this
message object by the message handler since the last time
this flag was cleared by the CPU.
1
The message handler or the CPU has written new data into
the data portion of this message object.
Message Lost
Value
Description
0
No message was lost since the last time this bit was
cleared by the CPU.
1
The message handler stored a new message into this
object when NEWDAT was set; the CPU has lost a message.
This bit is only valid for message objects when the DIR bit in the
CANIFnARB2 register is clear (receive).
13
INTPND
R/W
0
Interrupt Pending
Value
Description
0
This message object is not the source of an interrupt.
1
This message object is the source of an interrupt. The
interrupt identifier in the CANINT register points to this
message object if there is not another interrupt source with
a higher priority.
800
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
12
UMASK
R/W
0
11
10
9
8
TXIE
RXIE
RMTEN
TXRQST
R/W
R/W
R/W
R/W
0
0
0
0
Description
Use Acceptance Mask
Value
Description
0
Mask is ignored.
1
Use mask (MSK, MXTD, and MDIR bits in the
CANIFnMSKn registers) for acceptance filtering.
Transmit Interrupt Enable
Value
Description
0
The INTPND bit in the CANIFnMCTL register is unchanged
after a successful transmission of a frame.
1
The INTPND bit in the CANIFnMCTL register is set after
a successful transmission of a frame.
Receive Interrupt Enable
Value
Description
0
The INTPND bit in the CANIFnMCTL register is unchanged
after a successful reception of a frame.
1
The INTPND bit in the CANIFnMCTL register is set after
a successful reception of a frame.
Remote Enable
Value
Description
0
At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is left unchanged.
1
At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is set.
Transmit Request
Value
Description
0
This message object is not waiting for transmission.
1
The transmission of this message object is requested
and is not yet done.
Note:
If the WRNRD and TXRQST bits in the CANIFnCMSK register
are set, this bit is ignored.
May 24, 2010
801
Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
7
EOB
R/W
0
Description
End of Buffer
Value
Description
0
Message object belongs to a FIFO Buffer and is not the
last message object of that FIFO Buffer.
1
Single message object or last message object of a FIFO
Buffer.
This bit is used to concatenate two or more message objects (up to 32)
to build a FIFO buffer. For a single message object (thus not belonging
to a FIFO buffer), this bit must be set.
6:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
DLC
R/W
0x0
Data Length Code
Value
Description
0x0-0x8
Specifies the number of bytes in the data frame.
0x9-0xF
Defaults to a data frame with 8 bytes.
The DLC field in the CANIFnMCTL register of a message object must
be defined the same as in all the corresponding objects with the same
identifier at other nodes. When the message handler stores a data frame,
it writes DLC to the value given by the received message.
802
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8
These registers contain the data to be sent or that has been received. In a CAN data frame, data
byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted
or received. In CAN's serial bit stream, the MSB of each byte is transmitted first.
CAN IF1 Data A1 (CANIF1DA1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x03C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
R/W
0x0000
Data
The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2
data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2
data bytes 7 and 6.
May 24, 2010
803
Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By
reading out these bits, the CPU can check which message object has a transmission request pending.
The TXRQST bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a remote
frame, or (3) the message handler state machine after a successful transmission.
The CANTXRQ1 register contains the TXRQST bits of the first 16 message objects in the message
RAM; the CANTXRQ2 register contains the TXRQST bits of the second 16 message objects.
CAN Transmission Request 1 (CANTXRQ1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x100
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
TXRQST
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TXRQST
RO
0x0000
Transmission Request Bits
Value
Description
0
The corresponding message object is not waiting for
transmission.
1
The transmission of the corresponding message object
is requested and is not yet done.
804
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124
The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By
reading these bits, the CPU can check which message object has its data portion updated. The
NEWDAT bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a data frame,
or (3) the message handler state machine after a successful transmission.
The CANNWDA1 register contains the NEWDAT bits of the first 16 message objects in the message
RAM; the CANNWDA2 register contains the NEWDAT bits of the second 16 message objects.
CAN New Data 1 (CANNWDA1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x120
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
NEWDAT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
NEWDAT
RO
0x0000
New Data Bits
Value
Description
0
No new data has been written into the data portion of the
corresponding message object by the message handler since
the last time this flag was cleared by the CPU.
1
The message handler or the CPU has written new data into
the data portion of the corresponding message object.
May 24, 2010
805
Texas Instruments-Advance Information
Controller Area Network (CAN) Module
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144
The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects.
By reading these bits, the CPU can check which message object has an interrupt pending. The
INTPND bit of a specific message object can be changed through two sources: (1) the CPU via the
CANIFnMCTL register, or (2) the message handler state machine after the reception or transmission
of a frame.
This field is also encoded in the CANINT register.
The CANMSG1INT register contains the INTPND bits of the first 16 message objects in the message
RAM; the CANMSG2INT register contains the INTPND bits of the second 16 message objects.
CAN Message 1 Interrupt Pending (CANMSG1INT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x140
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INTPND
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
INTPND
RO
0x0000
Interrupt Pending Bits
Value
Description
0
The corresponding message object is not the source of
an interrupt.
1
The corresponding message object is the source of an
interrupt.
806
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164
The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects.
By reading these bits, the CPU can check which message object is valid. The message valid bit of
a specific message object can be changed with the CANIFnARB2 register.
The CANMSG1VAL register contains the MSGVAL bits of the first 16 message objects in the message
RAM; the CANMSG2VAL register contains the MSGVAL bits of the second 16 message objects in
the message RAM.
CAN Message 1 Valid (CANMSG1VAL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x160
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
MSGVAL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MSGVAL
RO
0x0000
Message Valid Bits
Value
Description
0
The corresponding message object is not configured and
is ignored by the message handler.
1
The corresponding message object is configured and
should be considered by the message handler.
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Universal Serial Bus (USB) Controller
19
Universal Serial Bus (USB) Controller
®
The Stellaris USB controller operates as a full-speed or low-speed function controller during
point-to-point communications with USB Host, Device, or OTG functions. The controller complies
with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. 32 endpoints including
two hard-wired for control transfers (one endpoint for IN and one endpoint for OUT) plus 30 endpoints
defined by firmware along with a dynamic sizable FIFO support multiple packet queueing. µDMA
access to the FIFO allows minimal interference from system software. Software-controlled connect
and disconnect allows flexibility during USB device start-up. The controller complies with OTG
standard's session request protocol (SRP) and host negotiation protocol (HNP).
®
The Stellaris USB module has the following features:
■ Complies with USB-IF certification standards
■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation
■ Integrated PHY
■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous
■ 32 endpoints
– 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
■ VBUS droop and valid ID detection and interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive for up to three IN endpoints and three OUT
endpoints
– Channel requests asserted when FIFO contains required amount of data
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19.1
Block Diagram
Figure 19-1. USB Module Block Diagram
DMA
Requests
Endpoint Control
Transmit
EP0 – 31
Control
Receive
CPU Interface
Combine
Endpoints
Host
Transaction
Scheduler
Interrupt
Control
Interrupts
EP Reg.
Decoder
USB PHY
USB FS/LS
PHY
UTM
Synchronization
Packet
Encode/Decode
Data Sync
Packet Encode
HNP/SRP
Packet Decode
Timers
CRC Gen/Check
FIFO RAM
Controller
Rx
Rx
Buff
Buff
Tx
Buff
Common
Regs
AHB bus –
Slave mode
Cycle
Control
Tx
Buff
Cycle Control
FIFO
Decoder
USB Data Lines
D+ and D-
19.2
Signal Description
Table 19-1 on page 810 and Table 19-2 on page 810 list the external signals of the USB controller
and describe the function of each. Some USB controller signals are alternate functions for some
GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin
Mux/Pin Assignment" lists the possible GPIO pin placements for these USB signals. The AFSEL bit
in the GPIO Alternate Function Select (GPIOAFSEL) register (page 323) should be set to choose
the USB function. The number in parentheses is the encoding that must be programmed into the
PMCn field in the GPIO Port Control (GPIOPCTL) register (page 341) to assign the USB signal to
the specified GPIO port pin. The USB0VBUS and USB0ID signals are configured by clearing the
appropriate DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on
configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 298. The remaining
signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment
and function.
Note:
When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they
are dedicated pins for the USB controller and directly connect to the USB connector's VBUS
and ID signals. If the USB controller is used as either a dedicated Host or Device, the
DEVMODOTG and DEVMOD bits in the USB General-Purpose Control and Status
(USBGPCS) register can be used to connect the USB0VBUS and USB0ID inputs to fixed
levels internally, freeing the PB0 and PB1 pins for GPIO use. For proper self-powered Device
operation, the VBUS value must still be monitored to assure that if the Host removes VBUS,
the self-powered Device disables the D+/D- pull-up resistors. This function can be
accomplished by connecting a standard GPIO to VBUS.
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Table 19-1. Signals for USB (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
USB0DM
70
fixed
I/O
Analog
Bidirectional differential data pin (D- per USB
specification).
USB0DP
71
fixed
I/O
Analog
Bidirectional differential data pin (D+ per USB
specification).
USB0EPEN
19
24
34
72
83
PG0 (7)
PC5 (6)
PA6 (8)
PB2 (8)
PH3 (4)
O
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
66
PB0
I
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
USB0PFLT
22
23
35
65
74
76
87
PC7 (6)
PC6 (7)
PA7 (8)
PB3 (8)
PE0 (9)
PH4 (4)
PJ1 (9)
I
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0RBIAS
73
fixed
O
Analog
9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
USB0VBUS
67
PB1
I/O
Analog
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 19-2. Signals for USB (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
USB0DM
C11
fixed
I/O
Analog
Bidirectional differential data pin (D- per USB
specification).
USB0DP
C12
fixed
I/O
Analog
Bidirectional differential data pin (D+ per USB
specification).
USB0EPEN
K1
M1
L6
A11
D10
PG0 (7)
PC5 (6)
PA6 (8)
PB2 (8)
PH3 (4)
O
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
E12
PB0
I
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
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Table 19-2. Signals for USB (108BGA) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
USB0PFLT
L2
M2
M6
E11
B11
B10
B6
PC7 (6)
PC6 (7)
PA7 (8)
PB3 (8)
PE0 (9)
PH4 (4)
PJ1 (9)
I
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0RBIAS
B12
fixed
O
Analog
9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
USB0VBUS
D12
PB1
I/O
Analog
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
19.3
Functional Description
Note:
A 9.1-kΩ resistor should be connected between the USB0RBIAS and ground. The 9.1-kΩ
resistor should have a 1% tolerance and should be located in close proximity to the
USB0RBIAS pin. Power dissipation in the resistor is low, so a chip resistor of any geometry
may be used.
®
The Stellaris USB controller provides full OTG negotiation by supporting both the session request
protocol (SRP) and the host negotiation protocol (HNP). The session request protocol allows devices
on the B side of a cable to request the A side device turn on VBUS. The host negotiation protocol
is used after the initial session request protocol has powered the bus and provides a method to
determine which end of the cable will act as the Host controller. When the device is connected to
non-OTG peripherals or devices, the controller can detect which cable end was used and provides
a register to indicate if the controller should act as the Host or the Device controller. This indication
and the mode of operation are handled automatically by the USB controller. This auto-detection
allows the system to use a single A/B connector instead of having both A and B connectors in the
system and supports full OTG negotiations with other OTG devices.
In addition, the USB controller provides support for connecting to non-OTG peripherals or Host
controllers. The USB controller can be configured to act as either a dedicated Host or Device, in
which case, the USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB
controller is acting as a self-powered Device, a GPIO input or analog comparator input must be
connected to VBUS and configured to generate an interrupt when the VBUS level drops. This
interrupt is used to disable the pullup resistor on the USB0DP signal.
Note:
19.3.1
When USB is used in the system, the minimum system frequency is 20 MHz.
Operation as a Device
®
This section describes the Stellaris USB controller's actions when it is being used as a USB Device.
Before the USB controller's operating mode is changed from Device to Host or Host to Device,
software must reset the USB controller by setting the USB0 bit in the Software Reset Control 2
(SRCR2) register (see page 202). IN endpoints, OUT endpoints, entry into and exit from SUSPEND
mode, and recognition of Start of Frame (SOF) are all described.
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When in Device mode, IN transactions are controlled by an endpoint’s transmit interface and use
the transmit endpoint registers for the given endpoint. OUT transactions are handled with an
endpoint's receive interface and use the receive endpoint registers for the given endpoint.
When configuring the size of the FIFOs for endpoints, take into account the maximum packet size
for an endpoint.
■ Bulk. Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the
maximum packet size if double buffering is used (described further in the following section).
■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice
the maximum packet size if double buffering is used.
■ Isochronous. Isochronous endpoints are more flexible and can be up to 1023 bytes.
■ Control. It is also possible to specify a separate control endpoint for a USB Device. However,
in most cases the USB Device should use the dedicated control endpoint on the USB controller’s
endpoint 0.
19.3.1.1
Endpoints
When operating as a Device, the USB controller provides two dedicated control endpoints (IN and
OUT) and 30 configurable endpoints (15 IN and 15 OUT) that can be used for communications with
a Host controller. The endpoint number and direction associated with an endpoint is directly related
to its register designation. For example, when the Host is transmitting to endpoint 1, all configuration
and data is in the endpoint 1 transmit register interface.
Endpoint 0 is a dedicated control endpoint used for all control transactions to endpoint 0 during
enumeration or when any other control requests are made to endpoint 0. Endpoint 0 uses the first
64 bytes of the USB controller's FIFO RAM as a shared memory for both IN and OUT transactions.
The remaining 30 endpoints can be configured as control, bulk, interrupt, or isochronous endpoints.
They should be treated as 15 configurable IN and 15 configurable OUT endpoints. The endpoint
pairs are not required to have the same type for their IN and OUT endpoint configuration. For
example, the OUT portion of an endpoint pair could be a bulk endpoint, while the IN portion of that
endpoint pair could be an interrupt endpoint. The address and size of the FIFOs attached to each
endpoint can be modified to fit the application's needs.
19.3.1.2
IN Transactions as a Device
When operating as a USB Device, data for IN transactions is handled through the FIFOs attached
to the transmit endpoints. The sizes of the FIFOs for the 15 configurable IN endpoints are determined
by the USB Transmit FIFO Start Address (USBTXFIFOADD) register. The maximum size of a
data packet that may be placed in a transmit endpoint’s FIFO for transmission is programmable and
is determined by the value written to the USB Maximum Transmit Data Endpoint n (USBTXMAXPn)
register for that endpoint. The endpoint’s FIFO can also be configured to use double-packet or
single-packet buffering. When double-packet buffering is enabled, two data packets can be buffered
in the FIFO, which also requires that the FIFO is at least two packets in size. When double-packet
buffering is disabled, only one packet can be buffered, even if the packet size is less than half the
FIFO size.
Note:
The maximum packet size set for any endpoint must not exceed the FIFO size. The
USBTXMAXPn register should not be written to while data is in the FIFO as unexpected
results may occur.
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Single-Packet Buffering
If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint
(as set in the USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) register), only one packet
can be buffered in the FIFO and single-packet buffering is required. When each packet is completely
loaded into the transmit FIFO, the TXRDY bit in the USB Transmit Control and Status Endpoint
n Low (USBTXCSRLn) register must be set. If the AUTOSET bit in the USB Transmit Control and
Status Endpoint n High (USBTXCSRHn) register is set, the TXRDY bit is automatically set when
a maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, the
TXRDY bit must be set manually. When the TXRDY bit is set, either manually or automatically, the
packet is ready to be sent. When the packet has been successfully sent, both TXRDY and FIFONE
are cleared, and the appropriate transmit endpoint interrupt signaled. At this point, the next packet
can be loaded into the FIFO.
Double-Packet Buffering
If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint,
two packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is
loaded into the transmit FIFO, the TXRDY bit in the USBTXCSRLn register must be set. If the
AUTOSET bit in the USBTXCSRHn register is set, the TXRDY bit is automatically set when a
maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, TXRDY
must be set manually. When the TXRDY bit is set, either manually or automatically, the packet is
ready to be sent. After the first packet is loaded, TXRDY is immediately cleared and an interrupt is
generated. A second packet can now be loaded into the transmit FIFO and TXRDY set again (either
manually or automatically if the packet is the maximum size). At this point, both packets are ready
to be sent. After each packet has been successfully sent, TXRDY is automatically cleared and the
appropriate transmit endpoint interrupt signaled to indicate that another packet can now be loaded
into the transmit FIFO. The state of the FIFONE bit in the USBTXCSRLn register at this point
indicates how many packets may be loaded. If the FIFONE bit is set, then another packet is in the
FIFO and only one more packet can be loaded. If the FIFONE bit is clear, then no packets are in
the FIFO and two more packets can be loaded.
Note:
19.3.1.3
Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB
Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS) register. This bit is set
by default, so it must be cleared to enable double-packet buffering.
OUT Transactions as a Device
When in Device mode, OUT transactions are handled through the USB controller receive FIFOs.
The sizes of the receive FIFOs for the 15 configurable OUT endpoints are determined by the USB
Receive FIFO Start Address (USBRXFIFOADD) register. The maximum amount of data received
by an endpoint in any packet is determined by the value written to the USB Maximum Receive
Data Endpoint n (USBRXMAXPn) register for that endpoint. When double-packet buffering is
enabled, two data packets can be buffered in the FIFO. When double-packet buffering is disabled,
only one packet can be buffered even if the packet is less than half the FIFO size.
Note:
In all cases, the maximum packet size must not exceed the FIFO size.
Single-Packet Buffering
If the size of the receive endpoint FIFO is less than twice the maximum packet size for an endpoint,
only one data packet can be buffered in the FIFO and single-packet buffering is required. When a
packet is received and placed in the receive FIFO, the RXRDY and FULL bits in the USB Receive
Control and Status Endpoint n Low (USBRXCSRLn) register are set and the appropriate receive
endpoint is signaled, indicating that a packet can now be unloaded from the FIFO. After the packet
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has been unloaded, the RXRDY bit must be cleared in order to allow further packets to be received.
This action also generates the acknowledge signaling to the Host controller. If the AUTOCL bit in the
USB Receive Control and Status Endpoint n High (USBRXCSRHn) register is set and a
maximum-sized packet is unloaded from the FIFO, the RXRDY and FULL bits are cleared
automatically. For packet sizes less than the maximum, RXRDY must be cleared manually.
Double-Packet Buffering
If the size of the receive endpoint FIFO is at least twice the maximum packet size for the endpoint,
two data packets can be buffered and double-packet buffering can be used. When the first packet
is received and loaded into the receive FIFO, the RXRDY bit in the USBRXCSRLn register is set
and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be
unloaded from the FIFO.
Note:
The FULL bit in USBRXCSRLn is not set when the first packet is received. It is only set if
a second packet is received and loaded into the receive FIFO.
After each packet has been unloaded, the RXRDY bit must be cleared to allow further packets to be
received. If the AUTOCL bit in the USBRXCSRHn register is set and a maximum-sized packet is
unloaded from the FIFO, the RXRDY bit is cleared automatically. For packet sizes less than the
maximum, RXRDY must be cleared manually. If the FULL bit is set when RXRDY is cleared, the USB
controller first clears the FULL bit, then sets RXRDY again to indicate that there is another packet
waiting in the FIFO to be unloaded.
Note:
19.3.1.4
Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB
Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) register. This bit is set
by default, so it must be cleared to enable double-packet buffering.
Scheduling
The Device has no control over the scheduling of transactions as scheduling is determined by the
®
Host controller. The Stellaris USB controller can set up a transaction at any time. The USB controller
waits for the request from the Host controller and generates an interrupt when the transaction is
complete or if it was terminated due to some error. If the Host controller makes a request and the
Device controller is not ready, the USB controller sends a busy response (NAK) to all requests until
it is ready.
19.3.1.5
Additional Actions
The USB controller responds automatically to certain conditions on the USB bus or actions by the
Host controller such as when the USB controller automatically stalls a control transfer or unexpected
zero length OUT data packets.
Stalled Control Transfer
The USB controller automatically issues a STALL handshake to a control transfer under the following
conditions:
1. The Host sends more data during an OUT data phase of a control transfer than was specified
in the Device request during the SETUP phase. This condition is detected by the USB controller
when the Host sends an OUT token (instead of an IN token) after the last OUT packet has been
unloaded and the DATAEND bit in the USB Control and Status Endpoint 0 Low (USBCSRL0)
register has been set.
2. The Host requests more data during an IN data phase of a control transfer than was specified
in the Device request during the SETUP phase. This condition is detected by the USB controller
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when the Host sends an IN token (instead of an OUT token) after the CPU has cleared TXRDY
and set DATAEND in response to the ACK issued by the Host to what should have been the last
packet.
3. The Host sends more than USBRXMAXPn bytes of data with an OUT data token.
4. The Host sends more than a zero length data packet for the OUT STATUS phase.
Zero Length OUT Data Packets
A zero-length OUT data packet is used to indicate the end of a control transfer. In normal operation,
such packets should only be received after the entire length of the Device request has been
transferred.
However, if the Host sends a zero-length OUT data packet before the entire length of Device request
has been transferred, it is signaling the premature end of the transfer. In this case, the USB controller
automatically flushes any IN token ready for the data phase from the FIFO and sets the DATAEND
bit in the USBCSRL0 register.
Setting the Device Address
When a Host is attempting to enumerate the USB Device, it requests that the Device change its
address from zero to some other value. The address is changed by writing the value that the Host
requested to the USB Device Functional Address (USBFADDR) register. However, care should
be taken when writing to USBFADDR to avoid changing the address before the transaction is
complete. This register should only be set after the SET_ADDRESS command is complete. Like all
control transactions, the transaction is only complete after the Device has left the STATUS phase.
In the case of a SET_ADDRESS command, the transaction is completed by responding to the IN
request from the Host with a zero-byte packet. Once the Device has responded to the IN request,
the USBFADDR register should be programmed to the new value as soon as possible to avoid
missing any new commands sent to the new address.
Note:
19.3.1.6
If the USBFADDR register is set to the new value as soon as the Device receives the OUT
transaction with the SET_ADDRESS command in the packet, it changes the address during
the control transfer. In this case, the Device does not receive the IN request that allows the
USB transaction to exit the STATUS phase of the control transfer because it is sent to the
old address. As a result, the Host does not get a response to the IN request, and the Host
fails to enumerate the Device.
Device Mode SUSPEND
When no activity has occurred on the USB bus for 3 ms, the USB controller automatically enters
SUSPEND mode. If the SUSPEND interrupt has been enabled in the USB Interrupt Enable (USBIE)
register, an interrupt is generated at this time. When in SUSPEND mode, the PHY also goes into
SUSPEND mode. When RESUME signaling is detected, the USB controller exits SUSPEND mode
and takes the PHY out of SUSPEND. If the RESUME interrupt is enabled, an interrupt is generated.
The USB controller can also be forced to exit SUSPEND mode by setting the RESUME bit in the USB
Power (USBPOWER) register. When this bit is set, the USB controller exits SUSPEND mode and
drives RESUME signaling onto the bus. The RESUME bit must be cleared after 10 ms (a maximum
of 15 ms) to end RESUME signaling.
To meet USB power requirements, the controller can be put into Deep Sleep mode which keeps
the controller in a static state.
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19.3.1.7
Start-of-Frame
When the USB controller is operating in Device mode, it receives a Start-Of-Frame (SOF) packet
from the Host once every millisecond. When the SOF packet is received, the 11-bit frame number
contained in the packet is written into the USB Frame Value (USBFRAME) register, and an SOF
interrupt is also signaled and can be handled by the application. Once the USB controller has started
to receive SOF packets, it expects one every millisecond. If no SOF packet is received after 1.00358
ms, the packet is assumed to have been lost, and the USBFRAME register is not updated. The
USB controller continues and resynchronizes these pulses to the received SOF packets when these
packets are successfully received again.
19.3.1.8
USB RESET
When the USB controller is in Device mode and a RESET condition is detected on the USB bus,
the USB controller automatically performs the following actions:
■ Clears the USBFADDR register.
■ Clears the USB Endpoint Index (USBEPIDX) register.
■ Flushes all endpoint FIFOs.
■ Clears all control/status registers.
■ Enables all endpoint interrupts.
■ Generates a RESET interrupt.
When the application software driving the USB controller receives a RESET interrupt, any open
pipes are closed and the USB controller waits for bus enumeration to begin.
19.3.1.9
Connect/Disconnect
The USB controller connection to the USB bus is handled by software. The USB PHY can be
switched between normal mode and non-driving mode by setting or clearing the SOFTCONN bit of
the USBPOWER register. When the SOFTCONN bit is set, the PHY is placed in its normal mode,
and the USB0DP/USB0DM lines of the USB bus are enabled. At the same time, the USB controller
is placed into a state, in which it does not respond to any USB signaling except a USB RESET.
When the SOFTCONN bit is cleared, the PHY is put into non-driving mode, USB0DP and USB0DM are
tristated, and the USB controller appears to other devices on the USB bus as if it has been
disconnected. The non-driving mode is the default so the USB controller appears disconnected until
the SOFTCONN bit has been set. The application software can then choose when to set the PHY
into its normal mode. Systems with a lengthy initialization procedure may use this to ensure that
initialization is complete, and the system is ready to perform enumeration before connecting to the
USB bus. Once the SOFTCONN bit has been set, the USB controller can be disconnected by clearing
this bit.
Note:
19.3.2
The USB controller does not generate an interrupt when the Device is connected to the
Host. However, an interrupt is generated when the Host terminates a session.
Operation as a Host
®
When the Stellaris USB controller is operating in Host mode, it can either be used for point-to-point
communications with another USB device or, when attached to a hub, for communication with
multiple devices. Before the USB controller's operating mode is changed from Host to Device or
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Device to Host, software must reset the USB controller by setting the USB0 bit in the Software
Reset Control 2 (SRCR2) register (see page 202). Full-speed and low-speed USB devices are
supported, both for point-to-point communication and for operation through a hub. The USB controller
automatically carries out the necessary transaction translation needed to allow a low-speed or
full-speed device to be used with a USB 2.0 hub. Control, bulk, isochronous, and interrupt transactions
are supported. This section describes the USB controller's actions when it is being used as a USB
Host. Configuration of IN endpoints, OUT endpoints, entry into and exit from SUSPEND mode, and
RESET are all described.
When in Host mode, IN transactions are controlled by an endpoint’s receive interface. All IN
transactions use the receive endpoint registers and all OUT endpoints use the transmit endpoint
registers for a given endpoint. As in Device mode, the FIFOs for endpoints should take into account
the maximum packet size for an endpoint.
■ Bulk. Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the
maximum packet size if double buffering is used (described further in the following section).
■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice
the maximum packet size if double buffering is used.
■ Isochronous. Isochronous endpoints are more flexible and can be up to 1023 bytes.
■ Control. It is also possible to specify a separate control endpoint to communicate with a Device.
However, in most cases the USB controller should use the dedicated control endpoint to
communicate with a Device’s endpoint 0.
19.3.2.1
Endpoints
The endpoint registers are used to control the USB endpoint interfaces which communicate with
Device(s) that are connected. The endpoints consist of a dedicated control IN endpoint, a dedicated
control OUT endpoint, 15 configurable OUT endpoints, and 15 configurable IN endpoints.
The dedicated control interface can only be used for control transactions to endpoint 0 of Devices.
These control transactions are used during enumeration or other control functions that communicate
using endpoint 0 of Devices. This control endpoint shares the first 64 bytes of the USB controller’s
FIFO RAM for IN and OUT transactions. The remaining IN and OUT interfaces can be configured
to communicate with control, bulk, interrupt, or isochronous Device endpoints.
These USB interfaces can be used to simultaneously schedule as many as 15 independent OUT
and 15 independent IN transactions to any endpoints on any Device. The IN and OUT controls are
paired in three sets of registers. However, they can be configured to communicate with different
types of endpoints and different endpoints on Devices. For example, the first pair of endpoint controls
can be split so that the OUT portion is communicating with a Device’s bulk OUT endpoint 1, while
the IN portion is communicating with a Device’s interrupt IN endpoint 2.
Before accessing any Device, whether for point-to-point communications or for communications via
a hub, the relevant USB Receive Functional Address Endpoint n (USBRXFUNCADDRn) or USB
Transmit Functional Address Endpoint n (USBTXFUNCADDRn) registers must be set for each
receive or transmit endpoint to record the address of the Device being accessed.
The USB controller also supports connections to Devices through a USB hub by providing a register
that specifies the hub address and port of each USB transfer. The FIFO address and size are
customizable and can be specified for each USB IN and OUT transfer. Customization includes
allowing one FIFO per transaction, sharing a FIFO across transactions, and allowing for
double-buffered FIFOs.
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19.3.2.2
IN Transactions as a Host
IN transactions are handled in a similar manner to the way in which OUT transactions are handled
when the USB controller is in Device mode except that the transaction first must be initiated by
setting the REQPKT bit in the USBCSRL0 register, indicating to the transaction scheduler that there
is an active transaction on this endpoint. The transaction scheduler then sends an IN token to the
target Device. When the packet is received and placed in the receive FIFO, the RXRDY bit in the
USBCSRL0 register is set, and the appropriate receive endpoint interrupt is signaled to indicate
that a packet can now be unloaded from the FIFO.
When the packet has been unloaded, RXRDY must be cleared. The AUTOCL bit in the USBRXCSRHn
register can be used to have RXRDY automatically cleared when a maximum-sized packet has been
unloaded from the FIFO. The AUTORQ bit in USBRXCSRHn causes the REQPKT bit to be automatically
set when the RXRDY bit is cleared. The AUTOCL and AUTORQ bits can be used with µDMA accesses
to perform complete bulk transfers without main processor intervention. When the RXRDY bit is
cleared, the controller sends an acknowledge to the Device. When there is a known number of
packets to be transferred, the USB Request Packet Count in Block Transfer Endpoint n
(USBRQPKTCOUNTn) register associated with the endpoint should be configured to the number
of packets to be transferred. The USB controller decrements the value in the USBRQPKTCOUNTn
register following each request. When the USBRQPKTCOUNTn value decrements to 0, the AUTORQ
bit is cleared to prevent any further transactions being attempted. For cases where the size of the
transfer is unknown, USBRQPKTCOUNTn should be cleared. AUTORQ then remains set until cleared
by the reception of a short packet (that is, less than the MAXLOAD value in the USBRXMAXPn
register) such as may occur at the end of a bulk transfer.
If the Device responds to a bulk or interrupt IN token with a NAK, the USB Host controller keeps
retrying the transaction until any NAK Limit that has been set has been reached. If the target Device
responds with a STALL, however, the USB Host controller does not retry the transaction but sets
the STALLED bit in the USBCSRL0 register. If the target Device does not respond to the IN token
within the required time, or the packet contained a CRC or bit-stuff error, the USB Host controller
retries the transaction. If after three attempts the target Device has still not responded, the USB
Host controller clears the REQPKT bit and sets the ERROR bit in the USBCSRL0 register.
19.3.2.3
OUT Transactions as a Host
OUT transactions are handled in a similar manner to the way in which IN transactions are handled
when the USB controller is in Device mode. The TXRDY bit in the USBTXCSRLn register must be
set as each packet is loaded into the transmit FIFO. Again, setting the AUTOSET bit in the
USBTXCSRHn register automatically sets TXRDY when a maximum-sized packet has been loaded
into the FIFO. Furthermore, AUTOSET can be used with the µDMA controller to perform complete
bulk transfers without software intervention.
If the target Device responds to the OUT token with a NAK, the USB Host controller keeps retrying
the transaction until the NAK Limit that has been set has been reached. However, if the target Device
responds with a STALL, the USB controller does not retry the transaction but interrupts the main
processor by setting the STALLED bit in the USBTXCSRLn register. If the target Device does not
respond to the OUT token within the required time, or the packet contained a CRC or bit-stuff error,
the USB Host controller retries the transaction. If after three attempts the target Device has still not
responded, the USB controller flushes the FIFO and sets the ERROR bit in the USBTXCSRLn register.
19.3.2.4
Transaction Scheduling
Scheduling of transactions is handled automatically by the USB Host controller. The Host controller
allows configuration of the endpoint communication scheduling based on the type of endpoint
transaction. Interrupt transactions can be scheduled to occur in the range of every frame to every
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255 frames in 1 frame increments. Bulk endpoints do not allow scheduling parameters, but do allow
for a NAK timeout in the event an endpoint on a Device is not responding. Isochronous endpoints
can be scheduled from every frame to every 216 frames, in powers of 2.
The USB controller maintains a frame counter. If the target Device is a full-speed device, the USB
controller automatically sends an SOF packet at the start of each frame and increments the frame
counter. If the target Device is a low-speed device, a K state is transmitted on the bus to act as a
keep-alive to stop the low-speed device from going into SUSPEND mode.
After the SOF packet has been transmitted, the USB Host controller cycles through all the configured
endpoints looking for active transactions. An active transaction is defined as a receive endpoint for
which the REQPKT bit is set or a transmit endpoint for which the TXRDY bit and/or the FIFONE bit is
set.
An isochronous or interrupt transaction is started if the transaction is found on the first scheduler
cycle of a frame and if the interval counter for that endpoint has counted down to zero. As a result,
only one interrupt or isochronous transaction occurs per endpoint every n frames, where n is the
interval set via the USB Host Transmit Interval Endpoint n (USBTXINTERVALn) or USB Host
Receive Interval Endpoint n (USBRXINTERVALn) register for that endpoint.
An active bulk transaction starts immediately, provided sufficient time is left in the frame to complete
the transaction before the next SOF packet is due. If the transaction must be retried (for example,
because a NAK was received or the target Device did not respond), then the transaction is not
retried until the transaction scheduler has first checked all the other endpoints for active transactions.
This process ensures that an endpoint that is sending a lot of NAKs does not block other transactions
on the bus. The controller also allows the user to specify a limit to the length of time for NAKs to be
received from a target Device before the endpoint times out.
19.3.2.5
USB Hubs
The following setup requirements apply to the USB Host controller only if it is used with a USB hub.
When a full- or low-speed Device is connected to the USB controller via a USB 2.0 hub, details of
the hub address and the hub port also must be recorded in the corresponding USB Receive Hub
Address Endpoint n (USBRXHUBADDRn) and USB Receive Hub Port Endpoint n
(USBRXHUBPORTn) or the USB Transmit Hub Address Endpoint n (USBTXHUBADDRn) and
USB Transmit Hub Port Endpoint n (USBTXHUBPORTn) registers. In addition, the speed at
which the Device operates (full or low) must be recorded in the USB Type Endpoint 0 (USBTYPE0)
(endpoint 0), USB Host Configure Transmit Type Endpoint n (USBTXTYPEn), or USB Host
Configure Receive Type Endpoint n (USBRXTYPEn) registers for each endpoint that is accessed
by the Device.
For hub communications, the settings in these registers record the current allocation of the endpoints
to the attached USB Devices. To maximize the number of Devices supported, the USB Host controller
allows this allocation to be changed dynamically by simply updating the address and speed
information recorded in these registers. Any changes in the allocation of endpoints to Device functions
must be made following the completion of any on-going transactions on the endpoints affected.
19.3.2.6
Babble
The USB Host controller does not start a transaction until the bus has been inactive for at least the
minimum inter-packet delay. The controller also does not start a transaction unless it can be finished
before the end of the frame. If the bus is still active at the end of a frame, then the USB Host controller
assumes that the target Device to which it is connected has malfunctioned, and the USB controller
suspends all transactions and generates a babble interrupt.
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19.3.2.7
Host SUSPEND
If the SUSPEND bit in the USBPOWER register is set, the USB Host controller completes the current
transaction then stops the transaction scheduler and frame counter. No further transactions are
started and no SOF packets are generated.
To exit SUSPEND mode, set the RESUME bit and clear the SUSPEND bit. While the RESUME bit is
set, the USB Host controller generates RESUME signaling on the bus. After 20 ms, the RESUME bit
must be cleared, at which point the frame counter and transaction scheduler start. The Host supports
the detection of a remote wake-up.
19.3.2.8
USB RESET
If the RESET bit in the USBPOWER register is set, the USB Host controller generates USB RESET
signaling on the bus. The RESET bit must be set for at least 20 ms to ensure correct resetting of the
target Device. After the CPU has cleared the bit, the USB Host controller starts its frame counter
and transaction scheduler.
19.3.2.9
Connect/Disconnect
A session is started by setting the SESSION bit in the USB Device Control (USBDEVCTL) register,
enabling the USB controller to wait for a Device to be connected. When a Device is detected, a
connect interrupt is generated. The speed of the Device that has been connected can be determined
by reading the USBDEVCTL register where the FSDEV bit is set for a full-speed Device, and the
LSDEV bit is set for a low-speed Device. The USB controller must generate a RESET to the Device,
and then the USB Host controller can begin Device enumeration. If the Device is disconnected while
a session is in progress, a disconnect interrupt is generated.
19.3.3
OTG Mode
To conserve power, the USB On-The-Go (OTG) supplement allows VBUS to only be powered up
when required and to be turned off when the bus is not in use. VBUS is always supplied by the A
device on the bus. The USB OTG controller determines whether it is the A device or the B device
by sampling the ID input from the PHY. This signal is pulled Low when an A-type plug is sensed
(signifying that the USB OTG controller should act as the A device) but taken High when a B-type
plug is sensed (signifying that the USB controller is a B device). Note that when switching between
OTG A and OTG B, the USB controller retains all register contents.
19.3.3.1
Starting a Session
When the USB OTG controller is ready to start a session, the SESSION bit must be set in the
USBDEVCTL register. The USB OTG controller then enables ID pin sensing. The ID input is either
taken Low if an A-type connection is detected or High if a B-type connection is detected. The DEV
bit in the USBDEVCTL register is also set to indicate whether the USB OTG controller has adopted
the role of the A device or the B device. The USB OTG controller also provides an interrupt to
indicate that ID pin sensing has completed and the mode value in the USBDEVCTL register is valid.
This interrupt is enabled in the USBIDVIM register, and the status is checked in the USBIDVISC
register. As soon as the USB controller has detected that it is on the A side of the cable, it must
enable VBUS power within 100ms or the USB controller reverts to device mode.
If the USB OTG controller is the A device, then the USB OTG controller enters Host mode (the A
device is always the default Host), turns on VBUS, and waits for VBUS to go above the VBUS Valid
threshold, as indicated by the VBUS bit in the USBDEVCTL register going to 0x3. The USB OTG
controller then waits for a peripheral to be connected. When a peripheral is detected, a Connect
interrupt is signaled and either the FSDEV or LSDEV bit in the USBDEVCTL register is set, depending
whether a full-speed or a low-speed peripheral is detected. The USB controller then issues a RESET
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to the connected Device. The SESSION bit in the USBDEVCTL register can be cleared to end a
session. The USB OTG controller also automatically ends the session if babble is detected or if
VBUS drops below session valid.
Note:
The USB OTG controller may not remain in Host mode when connected to high-current
devices. Some devices draw enough current to momentarily drop VBUS below the
VBUS-valid level causing the controller to drop out of Host mode. The only way to get back
into Host mode is to allow VBUS to go below the Session End level. In this situation, the
device is causing VBUS to drop repeatedly and pull VBUS back low the next time VBUS is
enabled.
In addition, the USB OTG controller may not remain in Host mode when a device is told
that it can start using it's active configuration. At this point the device starts drawing more
current and can also drop VBUS below VBUS valid.
If the USB OTG controller is the B device, then the USB OTG controller requests a session using
the session request protocol defined in the USB On-The-Go supplement, that is, it first discharges
VBUS. Then when VBUS has gone below the Session End threshold (VBUS bit in the USBDEVCTL
register goes to 0x0) and the line state has been a single-ended zero for > 2 ms, the USB OTG
controller pulses the data line, then pulses VBUS. At the end of the session, the SESSION bit is
cleared either by the USB OTG controller or by the application software. The USB OTG controller
then causes the PHY to switch out the pull-up resistor on D+, signaling the A device to end the
session.
19.3.3.2
Detecting Activity
When the other device of the OTG set-up wishes to start a session, it either raises VBUS above the
Session Valid threshold if it is the A device, or if it is the B device, it pulses the data line then pulses
VBUS. Depending on which of these actions happens, the USB controller can determine whether
it is the A device or the B device in the current set-up and act accordingly. If VBUS is raised above
the Session Valid threshold, then the USB controller is the B device. The USB controller sets the
SESSION bit in the USBDEVCTL register. When RESET signaling is detected on the bus, a RESET
interrupt is signaled, which is interpreted as the start of a session.
The USB controller is in Device mode as the B device is the default mode. At the end of the session,
the A device turns off the power to VBUS. When VBUS drops below the Session Valid threshold,
the USB controller detects this drop and clears the SESSION bit to indicate that the session has
ended, causing a disconnect interrupt to be signaled. If data line and VBUS pulsing is detected,
then the USB controller is the A device. The controller generates a SESSION REQUEST interrupt
to indicate that the B device is requesting a session. The SESSION bit in the USBDEVCTL register
must be set to start a session.
19.3.3.3
Host Negotiation
When the USB controller is the A device, ID is Low, and the controller automatically enters Host
mode when a session starts. When the USB controller is the B device, ID is High, and the controller
automatically enters Device mode when a session starts. However, software can request that the
USB controller become the Host by setting the HOSTREQ bit in the USBDEVCTL register. This bit
can be set either at the same time as requesting a Session Start by setting the SESSION bit in the
USBDEVCTL register or at any time after a session has started. When the USB controller next
enters SUSPEND mode and if the HOSTREQ bit remains set, the controller enters Host mode and
begins host negotiation (as specified in the USB On-The-Go supplement) by causing the PHY to
disconnect the pull-up resistor on the D+ line, causing the A device to switch to Device mode and
connect its own pull-up resistor. When the USB controller detects this, a Connect interrupt is
generated and the RESET bit in the USBPOWER register is set to begin resetting the A device. The
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USB controller begins this reset sequence automatically to ensure that RESET is started as required
within 1 ms of the A device connecting its pull-up resistor. The main processor should wait at least
20 ms, then clear the RESET bit and enumerate the A device.
When the USB OTG controller B device has finished using the bus, the USB controller goes into
SUSPEND mode by setting the SUSPEND bit in the USBPOWER register. The A device detects this
and either terminates the session or reverts to Host mode. If the A device is USB OTG controller,
it generates a Disconnect interrupt.
19.3.4
DMA Operation
The USB peripheral provides an interface connected to the μDMA controller with separate channels
for 3 transmit endpoints and 3 receive endpoints. Software selects which endpoints to service with
the μDMA channels using the USB DMA Select (USBDMASEL) register. The μDMA operation of
the USB is enabled through the USBTXCSRHn and USBRXCSRHn registers, for the TX and RX
channels respectively. When μDMA operation is enabled, the USB asserts a μDMA request on the
enabled receive or transmit channel when the associated FIFO can transfer data. When either FIFO
can transfer data, the burst request for that channel is asserted. The μDMA channel must be
configured to operate in Basic mode, and the size of the μDMA transfer must be restricted to whole
multiples of the size of the USB FIFO. Both read and write transfers of the USB FIFOs using μDMA
must be configured in this manner. For example, if the USB endpoint is configured with a FIFO size
of 64 bytes, the μDMA channel can be used to transfer 64 bytes to or from the endpoint FIFO. If the
number of bytes to transfer is less than 64, then a programmed I/O method must be used to copy
the data to or from the FIFO.
If the DMAMOD bit in the USBTXCSRHn/USBRXCSRHn register is clear, an interrupt is generated
after every packet is transferred, but the μDMA continues transferring data. If the DMAMOD bit is set,
an interrupt is generated only when the entire μDMA transfer is complete. The interrupt occurs on
the USB interrupt vector. Therefore, if interrupts are used for USB operation and the μDMA is
enabled, the USB interrupt handler must be designed to handle the μDMA completion interrupt.
Care must be taken when using the μDMA to unload the receive FIFO as data is read from the
receive FIFO in 4 byte chunks regardless of value of the MAXLOAD field in the USBRXCSRHn
register. The RXRDY bit is cleared as follows.
Table 19-3. Remainder (RxMaxP/4)
Value
Description
0
MAXLOAD = 64 bytes
1
MAXLOAD = 61 bytes
2
MAXLOAD = 62 bytes
3
MAXLOAD = 63 bytes
Table 19-4. Actual Bytes Read
Value
Description
0
MAXLOAD
1
MAXLOAD+3
2
MAXLOAD+2
3
MAXLOAD+1
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Table 19-5. Packet Sizes That Clear RXRDY
Value
Description
0
MAXLOAD, MAXLOAD-1, MAXLOAD-2, MAXLOAD-3
1
MAXLOAD
2
MAXLOAD, MAXLOAD-1
3
MAXLOAD, MAXLOAD-1, MAXLOAD-2
To enable DMA operation for the endpoint receive channel, the DMAEN bit of the USBRXCSRHn
register should be set. To enable DMA operation for the endpoint transmit channel, the DMAEN bit
of the USBTXCSRHn register must be set.
See “Micro Direct Memory Access (μDMA)” on page 240 for more details about programming the
μDMA controller.
19.4
Initialization and Configuration
To use the USB Controller, the peripheral clock must be enabled by via the RCGC2 register (see
page 191). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2
register in the System Control module (see page 191). To find out which GPIO port to enable, refer
to Table 24-4 on page 1088. Configure the PMCn fields in the GPIOPCTL register to assign the USB
signals to the appropriate pins (see page 341 and Table 24-5 on page 1097).
The initial configuration in all cases requires that the processor enable the USB controller and USB
controller’s physical layer interface (PHY) before setting any registers. The next step is to enable
the USB PLL so that the correct clocking is provided to the PHY. To ensure that voltage is not
supplied to the bus incorrectly, the external power control signal, USB0EPEN, should be negated on
start up by configuring the USB0EPEN and USB0PFLT pins to be controlled by the USB controller
and not exhibit their default GPIO behavior.
Note:
19.4.1
When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they
are dedicated pins for the USB controller and directly connect to the USB connector's VBUS
and ID signals. If the USB controller is used as either a dedicated Host or Device, the
DEVMODOTG and DEVMOD bits in the USB General-Purpose Control and Status
(USBGPCS) register can be used to connect the USB0VBUS and USB0ID inputs to fixed
levels internally, freeing the PB0 and PB1 pins for GPIO use. For proper self-powered Device
operation, the VBUS value must still be monitored to assure that if the Host removes VBUS,
the self-powered Device disables the D+/D- pull-up resistors. This function can be
accomplished by connecting a standard GPIO to VBUS.
Pin Configuration
When using the Device controller portion of the USB controller in a system that also provides Host
functionality, the power to VBUS must be disabled to allow the external Host controller to supply
power. Usually, the USB0EPEN signal is used to control the external regulator and should be negated
to avoid having two devices driving the USB0VBUS power pin on the USB connector.
When the USB controller is acting as a Host, it is in control of two signals that are attached to an
external voltage supply that provides power to VBUS. The Host controller uses the USB0EPEN signal
to enable or disable power to the USB0VBUS pin on the USB connector. An input pin, USB0PFLT,
provides feedback when there has been a power fault on VBUS. The USB0PFLT signal can be
configured to either automatically negate the USB0EPEN signal to disable power, and/or it can
generate an interrupt to the interrupt controller to allow software to handle the power fault condition.
The polarity and actions related to both USB0EPEN and USB0PFLT are fully configurable in the USB
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controller. The controller also provides interrupts on Device insertion and removal to allow the Host
controller code to respond to these external events.
19.4.2
Endpoint Configuration
To start communication in Host or Device mode, the endpoint registers must first be configured. In
Host mode, this configuration establishes a connection between an endpoint register and an endpoint
on a Device. In Device mode, an endpoint must be configured before enumerating to the Host
controller.
In both cases, the endpoint 0 configuration is limited because it is a fixed-function, fixed-FIFO-size
endpoint. In Device and Host modes, the endpoint requires little setup but does require a
software-based state machine to progress through the setup, data, and status phases of a standard
control transaction. In Device mode, the configuration of the remaining endpoints is done once
before enumerating and then only changed if an alternate configuration is selected by the Host
controller. In Host mode, the endpoints must be configured to operate as control, bulk, interrupt or
isochronous mode. Once the type of endpoint is configured, a FIFO area must be assigned to each
endpoint. In the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per
transaction. Isochronous endpoints can have packets with up to 1023 bytes per packet. In either
mode, the maximum packet size for the given endpoint must be set prior to sending or receiving
data.
Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to
each endpoint. The total FIFO RAM available is 4 Kbytes with the first 64 bytes reserved for endpoint
0. The endpoint’s FIFO must be at least as large as the maximum packet size. The FIFO can also
be configured as a double-buffered FIFO so that interrupts occur at the end of each packet and
allow filling the other half of the FIFO.
If operating as a Device, the USB Device controller's soft connect must be enabled when the Device
is ready to start communications, indicating to the Host controller that the Device is ready to start
the enumeration process. If operating as a Host controller, the Device soft connect must be disabled
and power must be provided to VBUS via the USB0EPEN signal.
19.5
Register Map
Table 19-6 on page 824 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000. Note that the USB controller clock must be enabled before the registers can be
programmed (see page 191).
Table 19-6. Universal Serial Bus (USB) Controller Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
USBFADDR
R/W
0x00
USB Device Functional Address
836
0x001
USBPOWER
R/W
0x20
USB Power
837
0x002
USBTXIS
RO
0x0000
USB Transmit Interrupt Status
840
0x004
USBRXIS
RO
0x0000
USB Receive Interrupt Status
842
0x006
USBTXIE
R/W
0xFFFF
USB Transmit Interrupt Enable
844
0x008
USBRXIE
R/W
0xFFFE
USB Receive Interrupt Enable
846
0x00A
USBIS
RO
0x00
USB General Interrupt Status
848
0x00B
USBIE
R/W
0x06
USB Interrupt Enable
851
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Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
Offset
Name
0x00C
See
page
Type
Reset
Description
USBFRAME
RO
0x0000
USB Frame Value
854
0x00E
USBEPIDX
R/W
0x00
USB Endpoint Index
855
0x00F
USBTEST
R/W
0x00
USB Test Mode
856
0x020
USBFIFO0
R/W
0x0000.0000
USB FIFO Endpoint 0
858
0x024
USBFIFO1
R/W
0x0000.0000
USB FIFO Endpoint 1
858
0x028
USBFIFO2
R/W
0x0000.0000
USB FIFO Endpoint 2
858
0x02C
USBFIFO3
R/W
0x0000.0000
USB FIFO Endpoint 3
858
0x030
USBFIFO4
R/W
0x0000.0000
USB FIFO Endpoint 4
858
0x034
USBFIFO5
R/W
0x0000.0000
USB FIFO Endpoint 5
858
0x038
USBFIFO6
R/W
0x0000.0000
USB FIFO Endpoint 6
858
0x03C
USBFIFO7
R/W
0x0000.0000
USB FIFO Endpoint 7
858
0x040
USBFIFO8
R/W
0x0000.0000
USB FIFO Endpoint 8
858
0x044
USBFIFO9
R/W
0x0000.0000
USB FIFO Endpoint 9
858
0x048
USBFIFO10
R/W
0x0000.0000
USB FIFO Endpoint 10
858
0x04C
USBFIFO11
R/W
0x0000.0000
USB FIFO Endpoint 11
858
0x050
USBFIFO12
R/W
0x0000.0000
USB FIFO Endpoint 12
858
0x054
USBFIFO13
R/W
0x0000.0000
USB FIFO Endpoint 13
858
0x058
USBFIFO14
R/W
0x0000.0000
USB FIFO Endpoint 14
858
0x05C
USBFIFO15
R/W
0x0000.0000
USB FIFO Endpoint 15
858
0x060
USBDEVCTL
R/W
0x80
USB Device Control
860
0x062
USBTXFIFOSZ
R/W
0x00
USB Transmit Dynamic FIFO Sizing
862
0x063
USBRXFIFOSZ
R/W
0x00
USB Receive Dynamic FIFO Sizing
862
0x064
USBTXFIFOADD
R/W
0x0000
USB Transmit FIFO Start Address
863
0x066
USBRXFIFOADD
R/W
0x0000
USB Receive FIFO Start Address
863
0x07A
USBCONTIM
R/W
0x5C
USB Connect Timing
864
0x07B
USBVPLEN
R/W
0x3C
USB OTG VBUS Pulse Timing
865
0x07D
USBFSEOF
R/W
0x77
USB Full-Speed Last Transaction to End of Frame Timing
866
0x07E
USBLSEOF
R/W
0x72
USB Low-Speed Last Transaction to End of Frame
Timing
867
0x080
USBTXFUNCADDR0
R/W
0x00
USB Transmit Functional Address Endpoint 0
868
0x082
USBTXHUBADDR0
R/W
0x00
USB Transmit Hub Address Endpoint 0
870
0x083
USBTXHUBPORT0
R/W
0x00
USB Transmit Hub Port Endpoint 0
872
May 24, 2010
825
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x088
USBTXFUNCADDR1
R/W
0x00
USB Transmit Functional Address Endpoint 1
868
0x08A
USBTXHUBADDR1
R/W
0x00
USB Transmit Hub Address Endpoint 1
870
0x08B
USBTXHUBPORT1
R/W
0x00
USB Transmit Hub Port Endpoint 1
872
0x08C
USBRXFUNCADDR1
R/W
0x00
USB Receive Functional Address Endpoint 1
874
0x08E
USBRXHUBADDR1
R/W
0x00
USB Receive Hub Address Endpoint 1
876
0x08F
USBRXHUBPORT1
R/W
0x00
USB Receive Hub Port Endpoint 1
878
0x090
USBTXFUNCADDR2
R/W
0x00
USB Transmit Functional Address Endpoint 2
868
0x092
USBTXHUBADDR2
R/W
0x00
USB Transmit Hub Address Endpoint 2
870
0x093
USBTXHUBPORT2
R/W
0x00
USB Transmit Hub Port Endpoint 2
872
0x094
USBRXFUNCADDR2
R/W
0x00
USB Receive Functional Address Endpoint 2
874
0x096
USBRXHUBADDR2
R/W
0x00
USB Receive Hub Address Endpoint 2
876
0x097
USBRXHUBPORT2
R/W
0x00
USB Receive Hub Port Endpoint 2
878
0x098
USBTXFUNCADDR3
R/W
0x00
USB Transmit Functional Address Endpoint 3
868
0x09A
USBTXHUBADDR3
R/W
0x00
USB Transmit Hub Address Endpoint 3
870
0x09B
USBTXHUBPORT3
R/W
0x00
USB Transmit Hub Port Endpoint 3
872
0x09C
USBRXFUNCADDR3
R/W
0x00
USB Receive Functional Address Endpoint 3
874
0x09E
USBRXHUBADDR3
R/W
0x00
USB Receive Hub Address Endpoint 3
876
0x09F
USBRXHUBPORT3
R/W
0x00
USB Receive Hub Port Endpoint 3
878
0x0A0
USBTXFUNCADDR4
R/W
0x00
USB Transmit Functional Address Endpoint 4
868
0x0A2
USBTXHUBADDR4
R/W
0x00
USB Transmit Hub Address Endpoint 4
870
0x0A3
USBTXHUBPORT4
R/W
0x00
USB Transmit Hub Port Endpoint 4
872
0x0A4
USBRXFUNCADDR4
R/W
0x00
USB Receive Functional Address Endpoint 4
874
0x0A6
USBRXHUBADDR4
R/W
0x00
USB Receive Hub Address Endpoint 4
876
0x0A7
USBRXHUBPORT4
R/W
0x00
USB Receive Hub Port Endpoint 4
878
0x0A8
USBTXFUNCADDR5
R/W
0x00
USB Transmit Functional Address Endpoint 5
868
0x0AA
USBTXHUBADDR5
R/W
0x00
USB Transmit Hub Address Endpoint 5
870
0x0AB
USBTXHUBPORT5
R/W
0x00
USB Transmit Hub Port Endpoint 5
872
0x0AC
USBRXFUNCADDR5
R/W
0x00
USB Receive Functional Address Endpoint 5
874
0x0AE
USBRXHUBADDR5
R/W
0x00
USB Receive Hub Address Endpoint 5
876
0x0AF
USBRXHUBPORT5
R/W
0x00
USB Receive Hub Port Endpoint 5
878
0x0B0
USBTXFUNCADDR6
R/W
0x00
USB Transmit Functional Address Endpoint 6
868
0x0B2
USBTXHUBADDR6
R/W
0x00
USB Transmit Hub Address Endpoint 6
870
826
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x0B3
USBTXHUBPORT6
R/W
0x00
USB Transmit Hub Port Endpoint 6
872
0x0B4
USBRXFUNCADDR6
R/W
0x00
USB Receive Functional Address Endpoint 6
874
0x0B6
USBRXHUBADDR6
R/W
0x00
USB Receive Hub Address Endpoint 6
876
0x0B7
USBRXHUBPORT6
R/W
0x00
USB Receive Hub Port Endpoint 6
878
0x0B8
USBTXFUNCADDR7
R/W
0x00
USB Transmit Functional Address Endpoint 7
868
0x0BA
USBTXHUBADDR7
R/W
0x00
USB Transmit Hub Address Endpoint 7
870
0x0BB
USBTXHUBPORT7
R/W
0x00
USB Transmit Hub Port Endpoint 7
872
0x0BC
USBRXFUNCADDR7
R/W
0x00
USB Receive Functional Address Endpoint 7
874
0x0BE
USBRXHUBADDR7
R/W
0x00
USB Receive Hub Address Endpoint 7
876
0x0BF
USBRXHUBPORT7
R/W
0x00
USB Receive Hub Port Endpoint 7
878
0x0C0
USBTXFUNCADDR8
R/W
0x00
USB Transmit Functional Address Endpoint 8
868
0x0C2
USBTXHUBADDR8
R/W
0x00
USB Transmit Hub Address Endpoint 8
870
0x0C3
USBTXHUBPORT8
R/W
0x00
USB Transmit Hub Port Endpoint 8
872
0x0C4
USBRXFUNCADDR8
R/W
0x00
USB Receive Functional Address Endpoint 8
874
0x0C6
USBRXHUBADDR8
R/W
0x00
USB Receive Hub Address Endpoint 8
876
0x0C7
USBRXHUBPORT8
R/W
0x00
USB Receive Hub Port Endpoint 8
878
0x0C8
USBTXFUNCADDR9
R/W
0x00
USB Transmit Functional Address Endpoint 9
868
0x0CA
USBTXHUBADDR9
R/W
0x00
USB Transmit Hub Address Endpoint 9
870
0x0CB
USBTXHUBPORT9
R/W
0x00
USB Transmit Hub Port Endpoint 9
872
0x0CC
USBRXFUNCADDR9
R/W
0x00
USB Receive Functional Address Endpoint 9
874
0x0CE
USBRXHUBADDR9
R/W
0x00
USB Receive Hub Address Endpoint 9
876
0x0CF
USBRXHUBPORT9
R/W
0x00
USB Receive Hub Port Endpoint 9
878
0x0D0
USBTXFUNCADDR10
R/W
0x00
USB Transmit Functional Address Endpoint 10
868
0x0D2
USBTXHUBADDR10
R/W
0x00
USB Transmit Hub Address Endpoint 10
870
0x0D3
USBTXHUBPORT10
R/W
0x00
USB Transmit Hub Port Endpoint 10
872
0x0D4
USBRXFUNCADDR10
R/W
0x00
USB Receive Functional Address Endpoint 10
874
0x0D6
USBRXHUBADDR10
R/W
0x00
USB Receive Hub Address Endpoint 10
876
0x0D7
USBRXHUBPORT10
R/W
0x00
USB Receive Hub Port Endpoint 10
878
0x0D8
USBTXFUNCADDR11
R/W
0x00
USB Transmit Functional Address Endpoint 11
868
0x0DA
USBTXHUBADDR11
R/W
0x00
USB Transmit Hub Address Endpoint 11
870
0x0DB
USBTXHUBPORT11
R/W
0x00
USB Transmit Hub Port Endpoint 11
872
0x0DC
USBRXFUNCADDR11
R/W
0x00
USB Receive Functional Address Endpoint 11
874
May 24, 2010
827
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x0DE
USBRXHUBADDR11
R/W
0x00
USB Receive Hub Address Endpoint 11
876
0x0DF
USBRXHUBPORT11
R/W
0x00
USB Receive Hub Port Endpoint 11
878
0x0E0
USBTXFUNCADDR12
R/W
0x00
USB Transmit Functional Address Endpoint 12
868
0x0E2
USBTXHUBADDR12
R/W
0x00
USB Transmit Hub Address Endpoint 12
870
0x0E3
USBTXHUBPORT12
R/W
0x00
USB Transmit Hub Port Endpoint 12
872
0x0E4
USBRXFUNCADDR12
R/W
0x00
USB Receive Functional Address Endpoint 12
874
0x0E6
USBRXHUBADDR12
R/W
0x00
USB Receive Hub Address Endpoint 12
876
0x0E7
USBRXHUBPORT12
R/W
0x00
USB Receive Hub Port Endpoint 12
878
0x0E8
USBTXFUNCADDR13
R/W
0x00
USB Transmit Functional Address Endpoint 13
868
0x0EA
USBTXHUBADDR13
R/W
0x00
USB Transmit Hub Address Endpoint 13
870
0x0EB
USBTXHUBPORT13
R/W
0x00
USB Transmit Hub Port Endpoint 13
872
0x0EC
USBRXFUNCADDR13
R/W
0x00
USB Receive Functional Address Endpoint 13
874
0x0EE
USBRXHUBADDR13
R/W
0x00
USB Receive Hub Address Endpoint 13
876
0x0EF
USBRXHUBPORT13
R/W
0x00
USB Receive Hub Port Endpoint 13
878
0x0F0
USBTXFUNCADDR14
R/W
0x00
USB Transmit Functional Address Endpoint 14
868
0x0F2
USBTXHUBADDR14
R/W
0x00
USB Transmit Hub Address Endpoint 14
870
0x0F3
USBTXHUBPORT14
R/W
0x00
USB Transmit Hub Port Endpoint 14
872
0x0F4
USBRXFUNCADDR14
R/W
0x00
USB Receive Functional Address Endpoint 14
874
0x0F6
USBRXHUBADDR14
R/W
0x00
USB Receive Hub Address Endpoint 14
876
0x0F7
USBRXHUBPORT14
R/W
0x00
USB Receive Hub Port Endpoint 14
878
0x0F8
USBTXFUNCADDR15
R/W
0x00
USB Transmit Functional Address Endpoint 15
868
0x0FA
USBTXHUBADDR15
R/W
0x00
USB Transmit Hub Address Endpoint 15
870
0x0FB
USBTXHUBPORT15
R/W
0x00
USB Transmit Hub Port Endpoint 15
872
0x0FC
USBRXFUNCADDR15
R/W
0x00
USB Receive Functional Address Endpoint 15
874
0x0FE
USBRXHUBADDR15
R/W
0x00
USB Receive Hub Address Endpoint 15
876
0x0FF
USBRXHUBPORT15
R/W
0x00
USB Receive Hub Port Endpoint 15
878
0x102
USBCSRL0
W1C
0x00
USB Control and Status Endpoint 0 Low
882
0x103
USBCSRH0
W1C
0x00
USB Control and Status Endpoint 0 High
886
0x108
USBCOUNT0
RO
0x00
USB Receive Byte Count Endpoint 0
888
0x10A
USBTYPE0
R/W
0x00
USB Type Endpoint 0
889
0x10B
USBNAKLMT
R/W
0x00
USB NAK Limit
890
0x110
USBTXMAXP1
R/W
0x0000
USB Maximum Transmit Data Endpoint 1
880
828
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x112
USBTXCSRL1
R/W
0x00
USB Transmit Control and Status Endpoint 1 Low
891
0x113
USBTXCSRH1
R/W
0x00
USB Transmit Control and Status Endpoint 1 High
896
0x114
USBRXMAXP1
R/W
0x0000
USB Maximum Receive Data Endpoint 1
900
0x116
USBRXCSRL1
R/W
0x00
USB Receive Control and Status Endpoint 1 Low
902
0x117
USBRXCSRH1
R/W
0x00
USB Receive Control and Status Endpoint 1 High
907
0x118
USBRXCOUNT1
RO
0x0000
USB Receive Byte Count Endpoint 1
912
0x11A
USBTXTYPE1
R/W
0x00
USB Host Transmit Configure Type Endpoint 1
914
0x11B
USBTXINTERVAL1
R/W
0x00
USB Host Transmit Interval Endpoint 1
916
0x11C
USBRXTYPE1
R/W
0x00
USB Host Configure Receive Type Endpoint 1
918
0x11D
USBRXINTERVAL1
R/W
0x00
USB Host Receive Polling Interval Endpoint 1
920
0x120
USBTXMAXP2
R/W
0x0000
USB Maximum Transmit Data Endpoint 2
880
0x122
USBTXCSRL2
R/W
0x00
USB Transmit Control and Status Endpoint 2 Low
891
0x123
USBTXCSRH2
R/W
0x00
USB Transmit Control and Status Endpoint 2 High
896
0x124
USBRXMAXP2
R/W
0x0000
USB Maximum Receive Data Endpoint 2
900
0x126
USBRXCSRL2
R/W
0x00
USB Receive Control and Status Endpoint 2 Low
902
0x127
USBRXCSRH2
R/W
0x00
USB Receive Control and Status Endpoint 2 High
907
0x128
USBRXCOUNT2
RO
0x0000
USB Receive Byte Count Endpoint 2
912
0x12A
USBTXTYPE2
R/W
0x00
USB Host Transmit Configure Type Endpoint 2
914
0x12B
USBTXINTERVAL2
R/W
0x00
USB Host Transmit Interval Endpoint 2
916
0x12C
USBRXTYPE2
R/W
0x00
USB Host Configure Receive Type Endpoint 2
918
0x12D
USBRXINTERVAL2
R/W
0x00
USB Host Receive Polling Interval Endpoint 2
920
0x130
USBTXMAXP3
R/W
0x0000
USB Maximum Transmit Data Endpoint 3
880
0x132
USBTXCSRL3
R/W
0x00
USB Transmit Control and Status Endpoint 3 Low
891
0x133
USBTXCSRH3
R/W
0x00
USB Transmit Control and Status Endpoint 3 High
896
0x134
USBRXMAXP3
R/W
0x0000
USB Maximum Receive Data Endpoint 3
900
0x136
USBRXCSRL3
R/W
0x00
USB Receive Control and Status Endpoint 3 Low
902
0x137
USBRXCSRH3
R/W
0x00
USB Receive Control and Status Endpoint 3 High
907
0x138
USBRXCOUNT3
RO
0x0000
USB Receive Byte Count Endpoint 3
912
0x13A
USBTXTYPE3
R/W
0x00
USB Host Transmit Configure Type Endpoint 3
914
0x13B
USBTXINTERVAL3
R/W
0x00
USB Host Transmit Interval Endpoint 3
916
0x13C
USBRXTYPE3
R/W
0x00
USB Host Configure Receive Type Endpoint 3
918
0x13D
USBRXINTERVAL3
R/W
0x00
USB Host Receive Polling Interval Endpoint 3
920
May 24, 2010
829
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x140
USBTXMAXP4
R/W
0x0000
USB Maximum Transmit Data Endpoint 4
880
0x142
USBTXCSRL4
R/W
0x00
USB Transmit Control and Status Endpoint 4 Low
891
0x143
USBTXCSRH4
R/W
0x00
USB Transmit Control and Status Endpoint 4 High
896
0x144
USBRXMAXP4
R/W
0x0000
USB Maximum Receive Data Endpoint 4
900
0x146
USBRXCSRL4
R/W
0x00
USB Receive Control and Status Endpoint 4 Low
902
0x147
USBRXCSRH4
R/W
0x00
USB Receive Control and Status Endpoint 4 High
907
0x148
USBRXCOUNT4
RO
0x0000
USB Receive Byte Count Endpoint 4
912
0x14A
USBTXTYPE4
R/W
0x00
USB Host Transmit Configure Type Endpoint 4
914
0x14B
USBTXINTERVAL4
R/W
0x00
USB Host Transmit Interval Endpoint 4
916
0x14C
USBRXTYPE4
R/W
0x00
USB Host Configure Receive Type Endpoint 4
918
0x14D
USBRXINTERVAL4
R/W
0x00
USB Host Receive Polling Interval Endpoint 4
920
0x150
USBTXMAXP5
R/W
0x0000
USB Maximum Transmit Data Endpoint 5
880
0x152
USBTXCSRL5
R/W
0x00
USB Transmit Control and Status Endpoint 5 Low
891
0x153
USBTXCSRH5
R/W
0x00
USB Transmit Control and Status Endpoint 5 High
896
0x154
USBRXMAXP5
R/W
0x0000
USB Maximum Receive Data Endpoint 5
900
0x156
USBRXCSRL5
R/W
0x00
USB Receive Control and Status Endpoint 5 Low
902
0x157
USBRXCSRH5
R/W
0x00
USB Receive Control and Status Endpoint 5 High
907
0x158
USBRXCOUNT5
RO
0x0000
USB Receive Byte Count Endpoint 5
912
0x15A
USBTXTYPE5
R/W
0x00
USB Host Transmit Configure Type Endpoint 5
914
0x15B
USBTXINTERVAL5
R/W
0x00
USB Host Transmit Interval Endpoint 5
916
0x15C
USBRXTYPE5
R/W
0x00
USB Host Configure Receive Type Endpoint 5
918
0x15D
USBRXINTERVAL5
R/W
0x00
USB Host Receive Polling Interval Endpoint 5
920
0x160
USBTXMAXP6
R/W
0x0000
USB Maximum Transmit Data Endpoint 6
880
0x162
USBTXCSRL6
R/W
0x00
USB Transmit Control and Status Endpoint 6 Low
891
0x163
USBTXCSRH6
R/W
0x00
USB Transmit Control and Status Endpoint 6 High
896
0x164
USBRXMAXP6
R/W
0x0000
USB Maximum Receive Data Endpoint 6
900
0x166
USBRXCSRL6
R/W
0x00
USB Receive Control and Status Endpoint 6 Low
902
0x167
USBRXCSRH6
R/W
0x00
USB Receive Control and Status Endpoint 6 High
907
0x168
USBRXCOUNT6
RO
0x0000
USB Receive Byte Count Endpoint 6
912
0x16A
USBTXTYPE6
R/W
0x00
USB Host Transmit Configure Type Endpoint 6
914
0x16B
USBTXINTERVAL6
R/W
0x00
USB Host Transmit Interval Endpoint 6
916
0x16C
USBRXTYPE6
R/W
0x00
USB Host Configure Receive Type Endpoint 6
918
830
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x16D
USBRXINTERVAL6
R/W
0x00
USB Host Receive Polling Interval Endpoint 6
920
0x170
USBTXMAXP7
R/W
0x0000
USB Maximum Transmit Data Endpoint 7
880
0x172
USBTXCSRL7
R/W
0x00
USB Transmit Control and Status Endpoint 7 Low
891
0x173
USBTXCSRH7
R/W
0x00
USB Transmit Control and Status Endpoint 7 High
896
0x174
USBRXMAXP7
R/W
0x0000
USB Maximum Receive Data Endpoint 7
900
0x176
USBRXCSRL7
R/W
0x00
USB Receive Control and Status Endpoint 7 Low
902
0x177
USBRXCSRH7
R/W
0x00
USB Receive Control and Status Endpoint 7 High
907
0x178
USBRXCOUNT7
RO
0x0000
USB Receive Byte Count Endpoint 7
912
0x17A
USBTXTYPE7
R/W
0x00
USB Host Transmit Configure Type Endpoint 7
914
0x17B
USBTXINTERVAL7
R/W
0x00
USB Host Transmit Interval Endpoint 7
916
0x17C
USBRXTYPE7
R/W
0x00
USB Host Configure Receive Type Endpoint 7
918
0x17D
USBRXINTERVAL7
R/W
0x00
USB Host Receive Polling Interval Endpoint 7
920
0x180
USBTXMAXP8
R/W
0x0000
USB Maximum Transmit Data Endpoint 8
880
0x182
USBTXCSRL8
R/W
0x00
USB Transmit Control and Status Endpoint 8 Low
891
0x183
USBTXCSRH8
R/W
0x00
USB Transmit Control and Status Endpoint 8 High
896
0x184
USBRXMAXP8
R/W
0x0000
USB Maximum Receive Data Endpoint 8
900
0x186
USBRXCSRL8
R/W
0x00
USB Receive Control and Status Endpoint 8 Low
902
0x187
USBRXCSRH8
R/W
0x00
USB Receive Control and Status Endpoint 8 High
907
0x188
USBRXCOUNT8
RO
0x0000
USB Receive Byte Count Endpoint 8
912
0x18A
USBTXTYPE8
R/W
0x00
USB Host Transmit Configure Type Endpoint 8
914
0x18B
USBTXINTERVAL8
R/W
0x00
USB Host Transmit Interval Endpoint 8
916
0x18C
USBRXTYPE8
R/W
0x00
USB Host Configure Receive Type Endpoint 8
918
0x18D
USBRXINTERVAL8
R/W
0x00
USB Host Receive Polling Interval Endpoint 8
920
0x190
USBTXMAXP9
R/W
0x0000
USB Maximum Transmit Data Endpoint 9
880
0x192
USBTXCSRL9
R/W
0x00
USB Transmit Control and Status Endpoint 9 Low
891
0x193
USBTXCSRH9
R/W
0x00
USB Transmit Control and Status Endpoint 9 High
896
0x194
USBRXMAXP9
R/W
0x0000
USB Maximum Receive Data Endpoint 9
900
0x196
USBRXCSRL9
R/W
0x00
USB Receive Control and Status Endpoint 9 Low
902
0x197
USBRXCSRH9
R/W
0x00
USB Receive Control and Status Endpoint 9 High
907
0x198
USBRXCOUNT9
RO
0x0000
USB Receive Byte Count Endpoint 9
912
0x19A
USBTXTYPE9
R/W
0x00
USB Host Transmit Configure Type Endpoint 9
914
0x19B
USBTXINTERVAL9
R/W
0x00
USB Host Transmit Interval Endpoint 9
916
May 24, 2010
831
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x19C
USBRXTYPE9
R/W
0x00
USB Host Configure Receive Type Endpoint 9
918
0x19D
USBRXINTERVAL9
R/W
0x00
USB Host Receive Polling Interval Endpoint 9
920
0x1A0
USBTXMAXP10
R/W
0x0000
USB Maximum Transmit Data Endpoint 10
880
0x1A2
USBTXCSRL10
R/W
0x00
USB Transmit Control and Status Endpoint 10 Low
891
0x1A3
USBTXCSRH10
R/W
0x00
USB Transmit Control and Status Endpoint 10 High
896
0x1A4
USBRXMAXP10
R/W
0x0000
USB Maximum Receive Data Endpoint 10
900
0x1A6
USBRXCSRL10
R/W
0x00
USB Receive Control and Status Endpoint 10 Low
902
0x1A7
USBRXCSRH10
R/W
0x00
USB Receive Control and Status Endpoint 10 High
907
0x1A8
USBRXCOUNT10
RO
0x0000
USB Receive Byte Count Endpoint 10
912
0x1AA
USBTXTYPE10
R/W
0x00
USB Host Transmit Configure Type Endpoint 10
914
0x1AB
USBTXINTERVAL10
R/W
0x00
USB Host Transmit Interval Endpoint 10
916
0x1AC
USBRXTYPE10
R/W
0x00
USB Host Configure Receive Type Endpoint 10
918
0x1AD
USBRXINTERVAL10
R/W
0x00
USB Host Receive Polling Interval Endpoint 10
920
0x1B0
USBTXMAXP11
R/W
0x0000
USB Maximum Transmit Data Endpoint 11
880
0x1B2
USBTXCSRL11
R/W
0x00
USB Transmit Control and Status Endpoint 11 Low
891
0x1B3
USBTXCSRH11
R/W
0x00
USB Transmit Control and Status Endpoint 11 High
896
0x1B4
USBRXMAXP11
R/W
0x0000
USB Maximum Receive Data Endpoint 11
900
0x1B6
USBRXCSRL11
R/W
0x00
USB Receive Control and Status Endpoint 11 Low
902
0x1B7
USBRXCSRH11
R/W
0x00
USB Receive Control and Status Endpoint 11 High
907
0x1B8
USBRXCOUNT11
RO
0x0000
USB Receive Byte Count Endpoint 11
912
0x1BA
USBTXTYPE11
R/W
0x00
USB Host Transmit Configure Type Endpoint 11
914
0x1BB
USBTXINTERVAL11
R/W
0x00
USB Host Transmit Interval Endpoint 11
916
0x1BC
USBRXTYPE11
R/W
0x00
USB Host Configure Receive Type Endpoint 11
918
0x1BD
USBRXINTERVAL11
R/W
0x00
USB Host Receive Polling Interval Endpoint 11
920
0x1C0
USBTXMAXP12
R/W
0x0000
USB Maximum Transmit Data Endpoint 12
880
0x1C2
USBTXCSRL12
R/W
0x00
USB Transmit Control and Status Endpoint 12 Low
891
0x1C3
USBTXCSRH12
R/W
0x00
USB Transmit Control and Status Endpoint 12 High
896
0x1C4
USBRXMAXP12
R/W
0x0000
USB Maximum Receive Data Endpoint 12
900
0x1C6
USBRXCSRL12
R/W
0x00
USB Receive Control and Status Endpoint 12 Low
902
0x1C7
USBRXCSRH12
R/W
0x00
USB Receive Control and Status Endpoint 12 High
907
0x1C8
USBRXCOUNT12
RO
0x0000
USB Receive Byte Count Endpoint 12
912
0x1CA
USBTXTYPE12
R/W
0x00
USB Host Transmit Configure Type Endpoint 12
914
832
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x1CB
USBTXINTERVAL12
R/W
0x00
USB Host Transmit Interval Endpoint 12
916
0x1CC
USBRXTYPE12
R/W
0x00
USB Host Configure Receive Type Endpoint 12
918
0x1CD
USBRXINTERVAL12
R/W
0x00
USB Host Receive Polling Interval Endpoint 12
920
0x1D0
USBTXMAXP13
R/W
0x0000
USB Maximum Transmit Data Endpoint 13
880
0x1D2
USBTXCSRL13
R/W
0x00
USB Transmit Control and Status Endpoint 13 Low
891
0x1D3
USBTXCSRH13
R/W
0x00
USB Transmit Control and Status Endpoint 13 High
896
0x1D4
USBRXMAXP13
R/W
0x0000
USB Maximum Receive Data Endpoint 13
900
0x1D6
USBRXCSRL13
R/W
0x00
USB Receive Control and Status Endpoint 13 Low
902
0x1D7
USBRXCSRH13
R/W
0x00
USB Receive Control and Status Endpoint 13 High
907
0x1D8
USBRXCOUNT13
RO
0x0000
USB Receive Byte Count Endpoint 13
912
0x1DA
USBTXTYPE13
R/W
0x00
USB Host Transmit Configure Type Endpoint 13
914
0x1DB
USBTXINTERVAL13
R/W
0x00
USB Host Transmit Interval Endpoint 13
916
0x1DC
USBRXTYPE13
R/W
0x00
USB Host Configure Receive Type Endpoint 13
918
0x1DD
USBRXINTERVAL13
R/W
0x00
USB Host Receive Polling Interval Endpoint 13
920
0x1E0
USBTXMAXP14
R/W
0x0000
USB Maximum Transmit Data Endpoint 14
880
0x1E2
USBTXCSRL14
R/W
0x00
USB Transmit Control and Status Endpoint 14 Low
891
0x1E3
USBTXCSRH14
R/W
0x00
USB Transmit Control and Status Endpoint 14 High
896
0x1E4
USBRXMAXP14
R/W
0x0000
USB Maximum Receive Data Endpoint 14
900
0x1E6
USBRXCSRL14
R/W
0x00
USB Receive Control and Status Endpoint 14 Low
902
0x1E7
USBRXCSRH14
R/W
0x00
USB Receive Control and Status Endpoint 14 High
907
0x1E8
USBRXCOUNT14
RO
0x0000
USB Receive Byte Count Endpoint 14
912
0x1EA
USBTXTYPE14
R/W
0x00
USB Host Transmit Configure Type Endpoint 14
914
0x1EB
USBTXINTERVAL14
R/W
0x00
USB Host Transmit Interval Endpoint 14
916
0x1EC
USBRXTYPE14
R/W
0x00
USB Host Configure Receive Type Endpoint 14
918
0x1ED
USBRXINTERVAL14
R/W
0x00
USB Host Receive Polling Interval Endpoint 14
920
0x1F0
USBTXMAXP15
R/W
0x0000
USB Maximum Transmit Data Endpoint 15
880
0x1F2
USBTXCSRL15
R/W
0x00
USB Transmit Control and Status Endpoint 15 Low
891
0x1F3
USBTXCSRH15
R/W
0x00
USB Transmit Control and Status Endpoint 15 High
896
0x1F4
USBRXMAXP15
R/W
0x0000
USB Maximum Receive Data Endpoint 15
900
0x1F6
USBRXCSRL15
R/W
0x00
USB Receive Control and Status Endpoint 15 Low
902
0x1F7
USBRXCSRH15
R/W
0x00
USB Receive Control and Status Endpoint 15 High
907
0x1F8
USBRXCOUNT15
RO
0x0000
USB Receive Byte Count Endpoint 15
912
May 24, 2010
833
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
0x1FA
USBTXTYPE15
R/W
0x00
USB Host Transmit Configure Type Endpoint 15
914
0x1FB
USBTXINTERVAL15
R/W
0x00
USB Host Transmit Interval Endpoint 15
916
0x1FC
USBRXTYPE15
R/W
0x00
USB Host Configure Receive Type Endpoint 15
918
0x1FD
USBRXINTERVAL15
R/W
0x00
USB Host Receive Polling Interval Endpoint 15
920
0x304
USBRQPKTCOUNT1
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
1
922
0x308
USBRQPKTCOUNT2
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
2
922
0x30C
USBRQPKTCOUNT3
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
3
922
0x310
USBRQPKTCOUNT4
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
4
922
0x314
USBRQPKTCOUNT5
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
5
922
0x318
USBRQPKTCOUNT6
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
6
922
0x31C
USBRQPKTCOUNT7
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
7
922
0x320
USBRQPKTCOUNT8
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
8
922
0x324
USBRQPKTCOUNT9
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
9
922
0x328
USBRQPKTCOUNT10
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
10
922
0x32C
USBRQPKTCOUNT11
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
11
922
0x330
USBRQPKTCOUNT12
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
12
922
0x334
USBRQPKTCOUNT13
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
13
922
0x338
USBRQPKTCOUNT14
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
14
922
0x33C
USBRQPKTCOUNT15
R/W
0x0000
USB Request Packet Count in Block Transfer Endpoint
15
922
0x340
USBRXDPKTBUFDIS
R/W
0x0000
USB Receive Double Packet Buffer Disable
924
0x342
USBTXDPKTBUFDIS
R/W
0x0000
USB Transmit Double Packet Buffer Disable
926
0x400
USBEPC
R/W
0x0000.0000
USB External Power Control
928
0x404
USBEPCRIS
RO
0x0000.0000
USB External Power Control Raw Interrupt Status
931
0x408
USBEPCIM
R/W
0x0000.0000
USB External Power Control Interrupt Mask
932
834
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 19-6. Universal Serial Bus (USB) Controller Register Map (continued)
Name
Type
Reset
0x40C
USBEPCISC
R/W
0x0000.0000
USB External Power Control Interrupt Status and Clear
933
0x410
USBDRRIS
RO
0x0000.0000
USB Device RESUME Raw Interrupt Status
934
0x414
USBDRIM
R/W
0x0000.0000
USB Device RESUME Interrupt Mask
935
0x418
USBDRISC
W1C
0x0000.0000
USB Device RESUME Interrupt Status and Clear
936
0x41C
USBGPCS
R/W
0x0000.0000
USB General-Purpose Control and Status
937
0x430
USBVDC
R/W
0x0000.0000
USB VBUS Droop Control
938
0x434
USBVDCRIS
RO
0x0000.0000
USB VBUS Droop Control Raw Interrupt Status
939
0x438
USBVDCIM
R/W
0x0000.0000
USB VBUS Droop Control Interrupt Mask
940
0x43C
USBVDCISC
R/W
0x0000.0000
USB VBUS Droop Control Interrupt Status and Clear
941
0x444
USBIDVRIS
RO
0x0000.0000
USB ID Valid Detect Raw Interrupt Status
942
0x448
USBIDVIM
R/W
0x0000.0000
USB ID Valid Detect Interrupt Mask
943
0x44C
USBIDVISC
R/W1C
0x0000.0000
USB ID Valid Detect Interrupt Status and Clear
944
0x450
USBDMASEL
R/W
0x0033.2211
USB DMA Select
945
19.6
Description
See
page
Offset
Register Descriptions
The LM3S5B91 USB controller has On-The-Go (OTG) capabilities as specified in the USB0 bit field
in the DC6 register (see page 160).
OTG B /
Device
OTG A /
Host
OTG
This icon indicates that the register is used in OTG B or Device mode. Some registers are used for
both Host and Device mode and may have different bit definitions depending on the mode.
This icon indicates that the register is used in OTG A or Host mode. Some registers are used for
both Host and Device mode and may have different bit definitions depending on the mode. The
USB controller is in OTG B or Device mode upon reset, so the reset values shown for these registers
apply to the Device mode definition.
This icon indicates that the register is used for OTG-specific functions such as ID detection and
negotiation. Once OTG negotiation is complete, then the USB controller registers are used according
to their Host or Device mode meanings depending on whether the OTG negotiations made the USB
controller OTG A (Host) or OTG B (Device).
May 24, 2010
835
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 1: USB Device Functional Address (USBFADDR), offset 0x000
OTG B /
Device
USBFADDR is an 8-bit register that contains the 7-bit address of the Device part of the transaction.
When the USB controller is being used in Device mode (the HOST bit in the USBDEVCTL register
is clear), this register must be written with the address received through a SET_ADDRESS command,
which is then used for decoding the function address in subsequent token packets.
Important: See the section called “Setting the Device Address” on page 815 for special
considerations when writing this register.
USB Device Functional Address (USBFADDR)
Base 0x4005.0000
Offset 0x000
Type R/W, reset 0x00
7
6
5
4
Type
Reset
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
FUNCADDR
reserved
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
FUNCADDR
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Function Address
Function Address of Device as received through SET_ADDRESS.
836
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 2: USB Power (USBPOWER), offset 0x001
OTG A /
USBPOWER is an 8-bit register used for controlling SUSPEND and RESUME signaling and some
basic operational aspects of the USB controller.
Host
OTG B /
Device
OTG A / Host Mode
USB Power (USBPOWER)
Base 0x4005.0000
Offset 0x001
Type R/W, reset 0x20
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
3
2
RESET
RO
1
RO
0
1
0
RESUME SUSPEND PWRDNPHY
R/W
0
R/W
0
R/W1S
0
Bit/Field
Name
Type
Reset
7:4
reserved
RO
0x2
3
RESET
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RESET Signaling
Value Description
2
RESUME
R/W
0
1
Enables RESET signaling on the bus.
0
Ends RESET signaling on the bus.
RESUME Signaling
Value Description
1
Enables RESUME signaling when the Device is in SUSPEND
mode.
0
Ends RESUME signaling on the bus.
This bit must be cleared by software 20 ms after being set.
1
SUSPEND
R/W1S
0
SUSPEND Mode
Value Description
1
Enables SUSPEND mode.
0
No effect.
May 24, 2010
837
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
0
PWRDNPHY
R/W
0
Description
Power Down PHY
Value Description
1
Powers down the internal USB PHY.
0
No effect.
OTG B / Device Mode
USB Power (USBPOWER)
Base 0x4005.0000
Offset 0x001
Type R/W, reset 0x20
Type
Reset
7
6
ISOUP
SOFTCONN
R/W
0
R/W
0
5
4
reserved
RO
1
RO
0
3
2
RESET
1
0
RESUME SUSPEND PWRDNPHY
RO
0
R/W
0
RO
0
Bit/Field
Name
Type
Reset
7
ISOUP
R/W
0
R/W
0
Description
Isochronous Update
Value Description
1
The USB controller waits for an SOF token from the time the
TXRDY bit is set in the USBTXCSRLn register before sending
the packet. If an IN token is received before an SOF token, then
a zero-length data packet is sent.
0
No effect.
Note:
6
SOFTCONN
R/W
0
This bit is only valid for isochronous transfers.
Soft Connect/Disconnect
Value Description
5:4
reserved
RO
0x2
3
RESET
RO
0
1
The USB D+/D- lines are enabled.
0
The USB D+/D- lines are tri-stated.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RESET Signaling
Value Description
1
RESET signaling is present on the bus.
0
RESET signaling is not present on the bus.
838
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
2
RESUME
R/W
0
Description
RESUME Signaling
Value Description
1
Enables RESUME signaling when the Device is in SUSPEND
mode.
0
Ends RESUME signaling on the bus.
This bit must be cleared by software 10 ms (a maximum of 15 ms) after
being set.
1
SUSPEND
RO
0
SUSPEND Mode
Value Description
0
PWRDNPHY
R/W
0
1
The USB controller is in SUSPEND mode.
0
This bit is cleared when software reads the interrupt register or
sets the RESUME bit above.
Power Down PHY
Value Description
1
Powers down the internal USB PHY.
0
No effect.
May 24, 2010
839
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 3: USB Transmit Interrupt Status (USBTXIS), offset 0x002
Important: Use caution when reading this register. Performing a read may change bit status.
OTG B /
USBTXIS is a 16-bit read-only register that indicates which interrupts are currently active for endpoint
0 and the transmit endpoints 1–15. The meaning of the EPn bits in this register is based on the
mode of the device. The EP1 through EP15 bits always indicate that the USB controller is sending
data; however, in Host mode, the bits refer to OUT endpoints; while in Device mode, the bits refer
to IN endpoints. The EP0 bit is special in Host and Device modes and indicates that either a control
IN or control OUT endpoint has generated an interrupt.
Device
Note:
OTG A /
Host
Bits relating to endpoints that have not been configured always return 0. Note also that all
active interrupts are cleared when this register is read.
USB Transmit Interrupt Status (USBTXIS)
Base 0x4005.0000
Offset 0x002
Type RO, reset 0x0000
Type
Reset
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
15
EP15
RO
0
Description
TX Endpoint 15 Interrupt
Value Description
14
EP14
RO
0
0
No interrupt.
1
The Endpoint 15 transmit interrupt is asserted.
TX Endpoint 14 Interrupt
Same description as EP15.
13
EP13
RO
0
TX Endpoint 13 Interrupt
Same description as EP15.
12
EP12
RO
0
TX Endpoint 12 Interrupt
Same description as EP15.
11
EP11
RO
0
TX Endpoint 11 Interrupt
Same description as EP15.
10
EP10
RO
0
TX Endpoint 10 Interrupt
Same description as EP15.
9
EP9
RO
0
TX Endpoint 9 Interrupt
Same description as EP15.
8
EP8
RO
0
TX Endpoint 8 Interrupt
Same description as EP15.
840
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
7
EP7
RO
0
Description
TX Endpoint 7 Interrupt
Same description as EP15.
6
EP6
RO
0
TX Endpoint 6 Interrupt
Same description as EP15.
5
EP5
RO
0
TX Endpoint 5 Interrupt
Same description as EP15.
4
EP4
RO
0
TX Endpoint 4 Interrupt
Same description as EP15.
3
EP3
RO
0
TX Endpoint 3 Interrupt
Same description as EP15.
2
EP2
RO
0
TX Endpoint 2 Interrupt
Same description as EP15.
1
EP1
RO
0
TX Endpoint 1 Interrupt
Same description as EP15.
0
EP0
RO
0
TX and RX Endpoint 0 Interrupt
Same description as EP15.
May 24, 2010
841
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 4: USB Receive Interrupt Status (USBRXIS), offset 0x004
Important: Use caution when reading this register. Performing a read may change bit status.
OTG A /
USBRXIS is a 16-bit read-only register that indicates which of the interrupts for receive endpoints
1–15 are currently active.
Host
Note:
OTG B /
Device
Type
Reset
Bits relating to endpoints that have not been configured always return 0. Note also that all
active interrupts are cleared when this register is read.
USB Receive Interrupt Status (USBRXIS)
Base 0x4005.0000
Offset 0x004
Type RO, reset 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
15
EP15
RO
0
Description
RX Endpoint 15 Interrupt
Value Description
14
EP14
RO
0
0
No interrupt.
1
The Endpoint 15 receive interrupt is asserted.
RX Endpoint 14 Interrupt
Same description as EP15.
13
EP13
RO
0
RX Endpoint 13 Interrupt
Same description as EP15.
12
EP12
RO
0
RX Endpoint 12 Interrupt
Same description as EP15.
11
EP11
RO
0
RX Endpoint 11 Interrupt
Same description as EP15.
10
EP10
RO
0
RX Endpoint 10 Interrupt
Same description as EP15.
9
EP9
RO
0
RX Endpoint 9 Interrupt
Same description as EP15.
8
EP8
RO
0
RX Endpoint 8 Interrupt
Same description as EP15.
7
EP7
RO
0
RX Endpoint 7 Interrupt
Same description as EP15.
6
EP6
RO
0
RX Endpoint 6 Interrupt
Same description as EP15.
842
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
5
EP5
RO
0
Description
RX Endpoint 5 Interrupt
Same description as EP15.
4
EP4
RO
0
RX Endpoint 4 Interrupt
Same description as EP15.
3
EP3
RO
0
RX Endpoint 3 Interrupt
Same description as EP15.
2
EP2
RO
0
RX Endpoint 2 Interrupt
Same description as EP15.
1
EP1
RO
0
RX Endpoint 1 Interrupt
Same description as EP15.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
843
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 5: USB Transmit Interrupt Enable (USBTXIE), offset 0x006
OTG A /
Host
USBTXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBTXIS
register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the
corresponding interrupt bit in the USBTXIS register is set. When a bit is cleared, the interrupt in the
USBTXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset,
all interrupts are enabled.
OTG B /
Device
USB Transmit Interrupt Enable (USBTXIE)
Base 0x4005.0000
Offset 0x006
Type R/W, reset 0xFFFF
Type
Reset
15
14
13
12
11
10
9
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
15
EP15
R/W
1
8
7
6
5
4
3
2
1
0
Description
TX Endpoint 15 Interrupt Enable
Value Description
14
EP14
R/W
1
1
An interrupt is sent to the interrupt controller when the EP15 bit
in the USBTXIS register is set.
0
The EP15 transmit interrupt is suppressed and not sent to the
interrupt controller.
TX Endpoint 14 Interrupt Enable
Same description as EP15.
13
EP13
R/W
1
TX Endpoint 13 Interrupt Enable
Same description as EP15.
12
EP12
R/W
1
TX Endpoint 12 Interrupt Enable
Same description as EP15.
11
EP11
R/W
1
TX Endpoint 11 Interrupt Enable
Same description as EP15.
10
EP10
R/W
1
TX Endpoint 10 Interrupt Enable
Same description as EP15.
9
EP9
R/W
1
TX Endpoint 9 Interrupt Enable
Same description as EP15.
8
EP8
R/W
1
TX Endpoint 8 Interrupt Enable
Same description as EP15.
7
EP7
R/W
1
TX Endpoint 7 Interrupt Enable
Same description as EP15.
6
EP6
R/W
1
TX Endpoint 6 Interrupt Enable
Same description as EP15.
844
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
5
EP5
R/W
1
Description
TX Endpoint 5 Interrupt Enable
Same description as EP15.
4
EP4
R/W
1
TX Endpoint 4 Interrupt Enable
Same description as EP15.
3
EP3
R/W
1
TX Endpoint 3 Interrupt Enable
Same description as EP15.
2
EP2
R/W
1
TX Endpoint 2 Interrupt Enable
Same description as EP15.
1
EP1
R/W
1
TX Endpoint 1 Interrupt Enable
Same description as EP15.
0
EP0
R/W
1
TX and RX Endpoint 0 Interrupt Enable
Same description as EP15.
May 24, 2010
845
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 6: USB Receive Interrupt Enable (USBRXIE), offset 0x008
OTG A /
Host
USBRXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBRXIS
register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the
corresponding interrupt bit in the USBRXIS register is set. When a bit is cleared, the interrupt in the
USBRXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On
reset, all interrupts are enabled.
OTG B /
Device
USB Receive Interrupt Enable (USBRXIE)
Base 0x4005.0000
Offset 0x008
Type R/W, reset 0xFFFE
Type
Reset
15
14
13
12
11
10
9
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
15
EP15
R/W
1
8
7
6
5
4
3
2
1
0
EP2
EP1
reserved
R/W
1
R/W
1
RO
0
Description
RX Endpoint 15 Interrupt Enable
Value Description
14
EP14
R/W
1
1
An interrupt is sent to the interrupt controller when the EP15 bit
in the USBRXIS register is set.
0
The EP15 receive interrupt is suppressed and not sent to the
interrupt controller.
RX Endpoint 14 Interrupt Enable
Same description as EP15.
13
EP13
R/W
1
RX Endpoint 13 Interrupt Enable
Same description as EP15.
12
EP12
R/W
1
RX Endpoint 12 Interrupt Enable
Same description as EP15.
11
EP11
R/W
1
RX Endpoint 11 Interrupt Enable
Same description as EP15.
10
EP10
R/W
1
RX Endpoint 10 Interrupt Enable
Same description as EP15.
9
EP9
R/W
1
RX Endpoint 9 Interrupt Enable
Same description as EP15.
8
EP8
R/W
1
RX Endpoint 8 Interrupt Enable
Same description as EP15.
7
EP7
R/W
1
RX Endpoint 7 Interrupt Enable
Same description as EP15.
6
EP6
R/W
1
RX Endpoint 6 Interrupt Enable
Same description as EP15.
846
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
5
EP5
R/W
1
Description
RX Endpoint 5 Interrupt Enable
Same description as EP15.
4
EP4
R/W
1
RX Endpoint 4 Interrupt Enable
Same description as EP15.
3
EP3
R/W
1
RX Endpoint 3 Interrupt Enable
Same description as EP15.
2
EP2
R/W
1
RX Endpoint 2 Interrupt Enable
Same description as EP15.
1
EP1
R/W
1
RX Endpoint 1 Interrupt Enable
Same description as EP15.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
847
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 7: USB General Interrupt Status (USBIS), offset 0x00A
Important: Use caution when reading this register. Performing a read may change bit status.
OTG A /
USBIS is an 8-bit read-only register that indicates which USB interrupts are currently active. All
active interrupts are cleared when this register is read.
Host
OTG B /
Device
OTG A / Host Mode
USB General Interrupt Status (USBIS)
Base 0x4005.0000
Offset 0x00A
Type RO, reset 0x00
7
6
5
VBUSERR SESREQ DISCON
Type
Reset
RO
0
RO
0
4
3
CONN
SOF
RO
0
RO
0
RO
0
2
1
BABBLE RESUME
RO
0
RO
0
0
reserved
RO
0
Bit/Field
Name
Type
Reset
Description
7
VBUSERR
RO
0
VBUS Error
Value Description
6
SESREQ
RO
0
1
VBUS has dropped below the VBUS Valid threshold during a
session.
0
No interrupt.
SESSION REQUEST
Value Description
5
DISCON
RO
0
1
SESSION REQUEST signaling has been detected.
0
No interrupt.
Session Disconnect
Value Description
4
CONN
RO
0
1
A Device disconnect has been detected.
0
No interrupt.
Session Connect
Value Description
1
A Device connection has been detected.
0
No interrupt.
848
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
3
SOF
RO
0
Description
Start of Frame
Value Description
2
BABBLE
RO
0
1
A new frame has started.
0
No interrupt.
Babble Detected
Value Description
1
RESUME
RO
0
1
Babble has been detected. This interrupt is active only after the
first SOF has been sent.
0
No interrupt.
RESUME Signaling Detected
Value Description
1
RESUME signaling has been detected on the bus while the
USB controller is in SUSPEND mode.
0
No interrupt.
This interrupt can only be used if the USB controller's system clock is
enabled. If the user disables the clock programming, the USBDRRIS,
USBDRIM, and USBDRISC registers should be used.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
0
OTG B / Device Mode
USB General Interrupt Status (USBIS)
Base 0x4005.0000
Offset 0x00A
Type RO, reset 0x00
7
6
reserved
Type
Reset
RO
0
RO
0
5
4
3
2
DISCON
reserved
SOF
RESET
RO
0
RO
0
RO
0
RO
0
RESUME SUSPEND
RO
0
Bit/Field
Name
Type
Reset
7:6
reserved
RO
0x0
5
DISCON
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Session Disconnect
Value Description
1
The device has been disconnected from the host.
0
No interrupt.
May 24, 2010
849
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
SOF
RO
0
Start of Frame
Value Description
2
RESET
RO
0
1
A new frame has started.
0
No interrupt.
RESET Signaling Detected
Value Description
1
RESUME
RO
0
1
RESET signaling has been detected on the bus.
0
No interrupt.
RESUME Signaling Detected
Value Description
1
RESUME signaling has been detected on the bus while the
USB controller is in SUSPEND mode.
0
No interrupt.
This interrupt can only be used if the USB controller's system clock is
enabled. If the user disables the clock programming, the USBDRRIS,
USBDRIM, and USBDRISC registers should be used.
0
SUSPEND
RO
0
SUSPEND Signaling Detected
Value Description
1
SUSPEND signaling has been detected on the bus.
0
No interrupt.
850
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 8: USB Interrupt Enable (USBIE), offset 0x00B
OTG A /
USBIE is an 8-bit register that provides interrupt enable bits for each of the interrupts in USBIS. At
reset interrupts 1 and 2 are enabled in Device mode.
Host
OTG B /
Device
OTG A / Host Mode
USB Interrupt Enable (USBIE)
Base 0x4005.0000
Offset 0x00B
Type R/W, reset 0x06
7
6
5
VBUSERR SESREQ DISCON
Type
Reset
R/W
0
R/W
0
4
3
CONN
SOF
R/W
0
R/W
0
R/W
0
2
1
BABBLE RESUME
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
7
VBUSERR
R/W
0
0
reserved
RO
0
Description
Enable VBUS Error Interrupt
Value Description
6
SESREQ
R/W
0
1
An interrupt is sent to the interrupt controller when the VBUSERR
bit in the USBIS register is set.
0
The VBUSERR interrupt is suppressed and not sent to the
interrupt controller.
Enable Session Request
Value Description
5
DISCON
R/W
0
1
An interrupt is sent to the interrupt controller when the SESREEQ
bit in the USBIS register is set.
0
The SESREQ interrupt is suppressed and not sent to the interrupt
controller.
Enable Disconnect Interrupt
Value Description
1
An interrupt is sent to the interrupt controller when the DISCON
bit in the USBIS register is set.
0
The DISCON interrupt is suppressed and not sent to the interrupt
controller.
May 24, 2010
851
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
4
CONN
R/W
0
Description
Enable Connect Interrupt
Value Description
3
SOF
R/W
0
1
An interrupt is sent to the interrupt controller when the CONN bit
in the USBIS register is set.
0
The CONN interrupt is suppressed and not sent to the interrupt
controller.
Enable Start-of-Frame Interrupt
Value Description
2
BABBLE
R/W
1
1
An interrupt is sent to the interrupt controller SOF the CONN bit
in the USBIS register is set.
0
The SOF interrupt is suppressed and not sent to the interrupt
controller.
Enable Babble Interrupt
Value Description
1
RESUME
R/W
1
1
An interrupt is sent to the interrupt controller when the BABBLE
bit in the USBIS register is set.
0
The BABBLE interrupt is suppressed and not sent to the interrupt
controller.
Enable RESUME Interrupt
Value Description
0
reserved
RO
1
An interrupt is sent to the interrupt controller when the RESUME
bit in the USBIS register is set.
0
The RESUME interrupt is suppressed and not sent to the interrupt
controller.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
0
OTG B / Device Mode
USB Interrupt Enable (USBIE)
Base 0x4005.0000
Offset 0x00B
Type R/W, reset 0x06
7
6
reserved
Type
Reset
RO
0
RO
0
5
4
3
2
DISCON
reserved
SOF
RESET
R/W
0
RO
0
R/W
0
R/W
1
RESUME SUSPEND
R/W
1
R/W
0
852
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
7:6
reserved
RO
0x0
5
DISCON
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable Disconnect Interrupt
Value Description
1
An interrupt is sent to the interrupt controller when the DISCON
bit in the USBIS register is set.
0
The DISCON interrupt is suppressed and not sent to the interrupt
controller.
4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
SOF
R/W
0
Enable Start-of-Frame Interrupt
Value Description
2
RESET
R/W
1
1
An interrupt is sent to the interrupt controller when the SOF bit
in the USBIS register is set.
0
The SOF interrupt is suppressed and not sent to the interrupt
controller.
Enable RESET Interrupt
Value Description
1
RESUME
R/W
1
1
An interrupt is sent to the interrupt controller when the RESET
bit in the USBIS register is set.
0
The RESET interrupt is suppressed and not sent to the interrupt
controller.
Enable RESUME Interrupt
Value Description
0
SUSPEND
R/W
0
1
An interrupt is sent to the interrupt controller when the RESUME
bit in the USBIS register is set.
0
The RESUME interrupt is suppressed and not sent to the interrupt
controller.
Enable SUSPEND Interrupt
Value Description
1
An interrupt is sent to the interrupt controller when the SUSPEND
bit in the USBIS register is set.
0
The SUSPEND interrupt is suppressed and not sent to the
interrupt controller.
May 24, 2010
853
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 9: USB Frame Value (USBFRAME), offset 0x00C
OTG A /
Host
USBFRAME is a 16-bit read-only register that holds the last received frame number.
USB Frame Value (USBFRAME)
Base 0x4005.0000
Offset 0x00C
Type RO, reset 0x0000
OTG B /
15
14
RO
0
RO
0
Device
13
12
11
10
9
8
7
6
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
FRAME
Bit/Field
Name
Type
Reset
15:11
reserved
RO
0x0
10:0
FRAME
RO
0x000
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Frame Number
854
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 10: USB Endpoint Index (USBEPIDX), offset 0x00E
OTG A /
Host
Each endpoint's buffer can be accessed by configuring a FIFO size and starting address. The
USBEPIDX 16-bit register is used with the USBTXFIFOSZ, USBRXFIFOSZ, USBTXFIFOADD,
and USBRXFIFOADD registers.
USB Endpoint Index (USBEPIDX)
OTG B /
Device
Base 0x4005.0000
Offset 0x00E
Type R/W, reset 0x00
7
6
RO
0
RO
0
5
4
3
2
RO
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
1
0
R/W
0
R/W
0
EPIDX
Bit/Field
Name
Type
Reset
Description
7:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
EPIDX
R/W
0x0
Endpoint Index
This bit field configures which endpoint is accessed when reading or
writing to one of the USB controller's indexed registers. A value of 0x0
corresponds to Endpoint 0 and a value of 0xF corresponds to Endpoint
15.
May 24, 2010
855
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 11: USB Test Mode (USBTEST), offset 0x00F
OTG A /
Host
USBTEST is an 8-bit register that is primarily used to put the USB controller into one of the four test
modes for operation described in the USB 2.0 Specification, in response to a SET FEATURE:
USBTESTMODE command. This register is not used in normal operation.
Note:
Only one of these bits should be set at any time.
OTG B /
Device
OTG A / Host Mode
USB Test Mode (USBTEST)
Base 0x4005.0000
Offset 0x00F
Type R/W, reset 0x00
7
6
5
4
3
FORCEH FIFOACC FORCEFS
Type
Reset
R/W
0
R/W1S
0
R/W
0
2
1
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
7
FORCEH
R/W
0
Description
Force Host Mode
Value Description
1
Forces the USB controller to enter Host mode when the
SESSION bit is set, regardless of whether the USB controller is
connected to any peripheral. The state of the USB0DP and
USB0DM signals is ignored. The USB controller then remains in
Host mode until the SESSION bit is cleared, even if a Device is
disconnected. If the FORCEH bit remains set, the USB controller
re-enters Host mode the next time the SESSION bit is set.
0
No effect.
While in this mode, status of the bus connection may be read using the
DEV bit of the USBDEVCTL register. The operating speed is determined
from the FORCEFS bit.
6
FIFOACC
R/W1S
0
FIFO Access
Value Description
1
Transfers the packet in the endpoint 0 transmit FIFO to the
endpoint 0 receive FIFO.
0
No effect.
This bit is cleared automatically.
5
FORCEFS
R/W
0
Force Full-Speed Mode
Value Description
1
Forces the USB controller into Full-Speed mode upon receiving
a USB RESET.
0
The USB controller operates at Low Speed.
856
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4:0
reserved
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
OTG B / Device Mode
USB Test Mode (USBTEST)
Base 0x4005.0000
Offset 0x00F
Type R/W, reset 0x00
7
reserved
Type
Reset
RO
0
6
5
4
3
FIFOACC FORCEFS
R/W1S
0
R/W
0
2
1
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
FIFOACC
R/W1S
0
FIFO Access
Value Description
1
Transfers the packet in the endpoint 0 transmit FIFO to the
endpoint 0 receive FIFO.
0
No effect.
This bit is cleared automatically.
5
FORCEFS
R/W
0
Force Full-Speed Mode
Value Description
4:0
reserved
RO
0x0
1
Forces the USB controller into Full-Speed mode upon receiving
a USB RESET.
0
The USB controller operates at Low Speed.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
857
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 12: USB FIFO Endpoint 0 (USBFIFO0), offset 0x020
Register 13: USB FIFO Endpoint 1 (USBFIFO1), offset 0x024
Register 14: USB FIFO Endpoint 2 (USBFIFO2), offset 0x028
Register 15: USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C
Register 16: USB FIFO Endpoint 4 (USBFIFO4), offset 0x030
Register 17: USB FIFO Endpoint 5 (USBFIFO5), offset 0x034
Register 18: USB FIFO Endpoint 6 (USBFIFO6), offset 0x038
Register 19: USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C
Register 20: USB FIFO Endpoint 8 (USBFIFO8), offset 0x040
Register 21: USB FIFO Endpoint 9 (USBFIFO9), offset 0x044
Register 22: USB FIFO Endpoint 10 (USBFIFO10), offset 0x048
Register 23: USB FIFO Endpoint 11 (USBFIFO11), offset 0x04C
Register 24: USB FIFO Endpoint 12 (USBFIFO12), offset 0x050
Register 25: USB FIFO Endpoint 13 (USBFIFO13), offset 0x054
Register 26: USB FIFO Endpoint 14 (USBFIFO14), offset 0x058
Register 27: USB FIFO Endpoint 15 (USBFIFO15), offset 0x05C
Important: Use caution when reading this register. Performing a read may change bit status.
OTG A /
Host
OTG B /
Device
These 32-bit registers provide an address for CPU access to the FIFOs for each endpoint. Writing
to these addresses loads data into the Transmit FIFO for the corresponding endpoint. Reading from
these addresses unloads data from the Receive FIFO for the corresponding endpoint.
Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of
accesses is allowed provided the data accessed is contiguous. All transfers associated with one
packet must be of the same width so that the data is consistently byte-, halfword- or word-aligned.
However, the last transfer may contain fewer bytes than the previous transfers in order to complete
an odd-byte or odd-word transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support
either single-packet or double-packet buffering (see the section called “Single-Packet
Buffering” on page 813). Burst writing of multiple packets is not supported as flags must be set after
each packet is written.
Following a STALL response or a transmit error on endpoint 1–15, the associated FIFO is completely
flushed.
858
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB FIFO Endpoint 0 (USBFIFO0)
Base 0x4005.0000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
EPDATA
Type
Reset
EPDATA
Type
Reset
Bit/Field
Name
Type
31:0
EPDATA
R/W
Reset
Description
0x0000.0000 Endpoint Data
Writing to this register loads the data into the Transmit FIFO and reading
unloads data from the Receive FIFO.
May 24, 2010
859
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 28: USB Device Control (USBDEVCTL), offset 0x060
OTG A /
Host
USBDEVCTL is an 8-bit register used for controlling and monitoring the USB VBUS line. If the PHY
is suspended, no PHY clock is received and the VBUS is not sampled. In addition, in Host mode,
USBDEVCTL provides the status information for the current operating mode (Host or Device) of
the USB controller. If the USB controller is in Host mode, this register also indicates if a full- or
low-speed Device has been connected.
USB Device Control (USBDEVCTL)
Base 0x4005.0000
Offset 0x060
Type R/W, reset 0x80
Type
Reset
7
6
5
4
DEV
FSDEV
LSDEV
RO
1
RO
0
RO
0
3
2
VBUS
RO
0
HOST
RO
0
RO
0
1
0
HOSTREQ SESSION
R/W
0
Bit/Field
Name
Type
Reset
7
DEV
RO
1
R/W
0
Description
Device Mode
Value Description
0
The USB controller is operating on the OTG A side of the cable.
1
The USB controller is operating on the OTG B side of the cable.
Note:
6
FSDEV
RO
0
This value is only valid while a session is in progress.
Full-Speed Device Detected
Value Description
5
LSDEV
RO
0
0
A full-speed Device has not been detected on the port.
1
A full-speed Device has been detected on the port.
Low-Speed Device Detected
Value Description
4:3
VBUS
RO
0x0
0
A low-speed Device has not been detected on the port.
1
A low-speed Device has been detected on the port.
VBUS Level
Value Description
0x0
Below SessionEnd
VBUS is detected as under 0.5 V.
0x1
Above SessionEnd, below AValid
VBUS is detected as above 0.5 V and under 1.5 V.
0x2
Above AValid, below VBUSValid
VBUS is detected as above 1.5 V and below 4.5 V.
0x3
Above VBUSValid
VBUS is detected as above 4.5 V.
860
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
Description
2
HOST
RO
0
Host Mode
Value Description
0
The USB controller is acting as a Device.
1
The USB controller is acting as a Host.
Note:
1
HOSTREQ
R/W
0
This value is only valid while a session is in progress.
Host Request
Value Description
0
No effect.
1
Initiates the Host Negotiation when SUSPEND mode is entered.
This bit is cleared when Host Negotiation is completed.
0
SESSION
R/W
0
Session Start/End
When operating as an OTG A device:
Value Description
0
When cleared by software, this bit ends a session.
1
When set by software, this bit starts a session.
When operating as an OTG B device:
Value Description
0
The USB controller has ended a session. When the USB
controller is in SUSPEND mode, this bit may be cleared by
software to perform a software disconnect.
1
The USB controller has started a session. When set by software,
the Session Request Protocol is initiated.
Note:
Clearing this bit when the USB controller is not suspended
results in undefined behavior.
May 24, 2010
861
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 29: USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062
Register 30: USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063
OTG A /
Host
These 8-bit registers allow the selected TX/RX endpoint FIFOs to be dynamically sized. USBEPIDX
is used to configure each transmit endpoint's FIFO size.
USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ)
OTG B /
Base 0x4005.0000
Offset 0x062
Type R/W, reset 0x00
Device
7
6
5
reserved
Type
Reset
RO
0
RO
0
4
3
2
R/W
0
R/W
0
DPB
RO
0
R/W
0
1
0
R/W
0
R/W
0
SIZE
Bit/Field
Name
Type
Reset
7:5
reserved
RO
0x0
4
DPB
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Double Packet Buffer Support
Value Description
3:0
SIZE
R/W
0x0
0
Only single-packet buffering is supported.
1
Double-packet buffering is supported.
Max Packet Size
Maximum packet size to be allowed.
If DPB = 0, the FIFO also is this size; if DPB = 1, the FIFO is twice this
size.
Value
Packet Size (Bytes)
0x0
8
0x1
16
0x2
32
0x3
64
0x4
128
0x5
256
0x6
512
0x7
1024
0x8
2048
0x9-0xF Reserved
862
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 31: USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064
Register 32: USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066
OTG A /
Host
OTG B /
USBTXFIFOADD and USBRXFIFOADD are 16-bit registers that controls the start address of the
selected transmit and receive endpoint FIFOs.
USB Transmit FIFO Start Address (USBTXFIFOADD)
Base 0x4005.0000
Offset 0x064
Type R/W, reset 0x0000
Device
15
14
13
RO
0
RO
0
RO
0
12
11
10
9
8
7
6
5
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR
R/W
0
Bit/Field
Name
Type
Reset
Description
15:9
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8:0
ADDR
R/W
0x00
Transmit/Receive Start Address
Start address of the endpoint FIFO.
Value Start Address
0x0
0
0x1
8
0x2
16
0x3
24
0x4
32
0x5
40
0x6
48
0x7
56
0x8
64
...
...
0x1FF 4095
May 24, 2010
863
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 33: USB Connect Timing (USBCONTIM), offset 0x07A
OTG A /
Host
This 8-bit configuration register specifies connection and negotiation delays.
USB Connect Timing (USBCONTIM)
Base 0x4005.0000
Offset 0x07A
Type R/W, reset 0x5C
OTG B /
7
6
R/W
0
R/W
1
Device
5
4
3
2
R/W
1
R/W
1
R/W
1
WTCON
Type
Reset
R/W
0
1
0
R/W
0
R/W
0
WTID
Bit/Field
Name
Type
Reset
7:4
WTCON
R/W
0x5
Description
Connect Wait
This field configures the wait required to allow for the user’s
connect/disconnect filter, in units of 533.3 ns. The default corresponds
to 2.667 µs.
3:0
WTID
R/W
0xC
Wait ID
This field configures the delay required from the enable of the ID
detection to when the ID value is valid, in units of 4.369 ms. The default
corresponds to 52.43 ms.
864
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 34: USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B
This 8-bit configuration register specifies the duration of the VBUS pulsing charge.
OTG
USB OTG VBUS Pulse Timing (USBVPLEN)
Base 0x4005.0000
Offset 0x07B
Type R/W, reset 0x3C
7
6
5
4
R/W
0
R/W
0
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
0
R/W
0
VPLEN
Type
Reset
Bit/Field
Name
Type
Reset
Description
7:0
VPLEN
R/W
0x3C
VBUS Pulse Length
This field configures the duration of the VBUS pulsing charge in units
of 546.1 µs. The default corresponds to 32.77 ms.
May 24, 2010
865
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 35: USB Full-Speed Last Transaction to End of Frame Timing
(USBFSEOF), offset 0x07D
OTG A /
Host
OTG B /
This 8-bit configuration register specifies the minimum time gap allowed between the start of the
last transaction and the EOF for full-speed transactions.
USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF)
Base 0x4005.0000
Offset 0x07D
Type R/W, reset 0x77
Device
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
FSEOFG
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
Bit/Field
Name
Type
Reset
Description
7:0
FSEOFG
R/W
0x77
Full-Speed End-of-Frame Gap
This field is used during full-speed transactions to configure the gap
between the last transaction and the End-of-Frame (EOF), in units of
533.3 ns. The default corresponds to 63.46 µs.
866
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 36: USB Low-Speed Last Transaction to End of Frame Timing
(USBLSEOF), offset 0x07E
OTG A /
Host
OTG B /
This 8-bit configuration register specifies the minimum time gap that is to be allowed between the
start of the last transaction and the EOF for low-speed transactions.
USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF)
Base 0x4005.0000
Offset 0x07E
Type R/W, reset 0x72
Device
7
6
5
4
3
2
1
0
R/W
0
R/W
1
R/W
0
LSEOFG
Type
Reset
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
Bit/Field
Name
Type
Reset
Description
7:0
LSEOFG
R/W
0x72
Low-Speed End-of-Frame Gap
This field is used during low-speed transactions to set the gap between
the last transaction and the End-of-Frame (EOF), in units of 1.067 µs.
The default corresponds to 121.6 µs.
May 24, 2010
867
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 37: USB Transmit Functional Address Endpoint 0
(USBTXFUNCADDR0), offset 0x080
Register 38: USB Transmit Functional Address Endpoint 1
(USBTXFUNCADDR1), offset 0x088
Register 39: USB Transmit Functional Address Endpoint 2
(USBTXFUNCADDR2), offset 0x090
Register 40: USB Transmit Functional Address Endpoint 3
(USBTXFUNCADDR3), offset 0x098
Register 41: USB Transmit Functional Address Endpoint 4
(USBTXFUNCADDR4), offset 0x0A0
Register 42: USB Transmit Functional Address Endpoint 5
(USBTXFUNCADDR5), offset 0x0A8
Register 43: USB Transmit Functional Address Endpoint 6
(USBTXFUNCADDR6), offset 0x0B0
Register 44: USB Transmit Functional Address Endpoint 7
(USBTXFUNCADDR7), offset 0x0B8
Register 45: USB Transmit Functional Address Endpoint 8
(USBTXFUNCADDR8), offset 0x0C0
Register 46: USB Transmit Functional Address Endpoint 9
(USBTXFUNCADDR9), offset 0x0C8
Register 47: USB Transmit Functional Address Endpoint 10
(USBTXFUNCADDR10), offset 0x0D0
Register 48: USB Transmit Functional Address Endpoint 11
(USBTXFUNCADDR11), offset 0x0D8
Register 49: USB Transmit Functional Address Endpoint 12
(USBTXFUNCADDR12), offset 0x0E0
Register 50: USB Transmit Functional Address Endpoint 13
(USBTXFUNCADDR13), offset 0x0E8
Register 51: USB Transmit Functional Address Endpoint 14
(USBTXFUNCADDR14), offset 0x0F0
Register 52: USB Transmit Functional Address Endpoint 15
(USBTXFUNCADDR15), offset 0x0F8
OTG A /
Host
USBTXFUNCADDRn is an 8-bit read/write register that records the address of the target function
to be accessed through the associated endpoint (EPn). USBTXFUNCADDRn must be defined for
each transmit endpoint that is used.
Note:
USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0.
868
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0)
Base 0x4005.0000
Offset 0x080
Type R/W, reset 0x00
7
6
5
4
R/W
0
R/W
0
R/W
0
RO
0
2
1
0
R/W
0
R/W
0
R/W
0
ADDR
reserved
Type
Reset
3
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
ADDR
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Address
Specifies the USB bus address for the target Device.
May 24, 2010
869
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 53: USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0),
offset 0x082
Register 54: USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1),
offset 0x08A
Register 55: USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2),
offset 0x092
Register 56: USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3),
offset 0x09A
Register 57: USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4),
offset 0x0A2
Register 58: USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5),
offset 0x0AA
Register 59: USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6),
offset 0x0B2
Register 60: USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7),
offset 0x0BA
Register 61: USB Transmit Hub Address Endpoint 8 (USBTXHUBADDR8),
offset 0x0C2
Register 62: USB Transmit Hub Address Endpoint 9 (USBTXHUBADDR9),
offset 0x0CA
Register 63: USB Transmit Hub Address Endpoint 10 (USBTXHUBADDR10),
offset 0x0D2
Register 64: USB Transmit Hub Address Endpoint 11 (USBTXHUBADDR11),
offset 0x0DA
Register 65: USB Transmit Hub Address Endpoint 12 (USBTXHUBADDR12),
offset 0x0E2
Register 66: USB Transmit Hub Address Endpoint 13 (USBTXHUBADDR13),
offset 0x0EA
Register 67: USB Transmit Hub Address Endpoint 14 (USBTXHUBADDR14),
offset 0x0F2
Register 68: USB Transmit Hub Address Endpoint 15 (USBTXHUBADDR15),
offset 0x0FA
OTG A /
Host
USBTXHUBADDRn is an 8-bit read/write register that, like USBTXHUBPORTn, only must be written
when a USB Device is connected to transmit endpoint EPn via a USB 2.0 hub. This register records
the address of the USB 2.0 hub through which the target associated with the endpoint is accessed.
Note:
USBTXHUBADDR0 is used for both receive and transmit for endpoint 0.
870
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0)
Base 0x4005.0000
Offset 0x082
Type R/W, reset 0x00
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
ADDR
MULTTRAN
Type
Reset
3
R/W
0
Bit/Field
Name
Type
Reset
7
MULTTRAN
R/W
0
Description
Multiple Translators
Value Description
6:0
ADDR
R/W
0x00
0
Clear to indicate that the hub has a single transaction translator.
1
Set to indicate that the hub has multiple transaction translators.
Hub Address
This field specifies the USB bus address for the USB 2.0 hub.
May 24, 2010
871
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 69: USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset
0x083
Register 70: USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset
0x08B
Register 71: USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset
0x093
Register 72: USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset
0x09B
Register 73: USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset
0x0A3
Register 74: USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset
0x0AB
Register 75: USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset
0x0B3
Register 76: USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset
0x0BB
Register 77: USB Transmit Hub Port Endpoint 8 (USBTXHUBPORT8), offset
0x0C3
Register 78: USB Transmit Hub Port Endpoint 9 (USBTXHUBPORT9), offset
0x0CB
Register 79: USB Transmit Hub Port Endpoint 10 (USBTXHUBPORT10), offset
0x0D3
Register 80: USB Transmit Hub Port Endpoint 11 (USBTXHUBPORT11), offset
0x0DB
Register 81: USB Transmit Hub Port Endpoint 12 (USBTXHUBPORT12), offset
0x0E3
Register 82: USB Transmit Hub Port Endpoint 13 (USBTXHUBPORT13), offset
0x0EB
Register 83: USB Transmit Hub Port Endpoint 14 (USBTXHUBPORT14), offset
0x0F3
Register 84: USB Transmit Hub Port Endpoint 15 (USBTXHUBPORT15), offset
0x0FB
OTG A /
Host
USBTXHUBPORTn is an 8-bit read/write register that, like USBTXHUBADDRn, only must be written
when a full- or low-speed Device is connected to transmit endpoint EPn via a USB 2.0 hub. This
register records the port of the USB 2.0 hub through which the target associated with the endpoint
is accessed.
Note:
USBTXHUBPORT0 is used for both receive and transmit for endpoint 0.
872
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0)
Base 0x4005.0000
Offset 0x083
Type R/W, reset 0x00
7
6
5
4
R/W
0
R/W
0
R/W
0
RO
0
2
1
0
R/W
0
R/W
0
R/W
0
PORT
reserved
Type
Reset
3
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
PORT
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hub Port
This field specifies the USB hub port number.
May 24, 2010
873
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 85: USB Receive Functional Address Endpoint 1
(USBRXFUNCADDR1), offset 0x08C
Register 86: USB Receive Functional Address Endpoint 2
(USBRXFUNCADDR2), offset 0x094
Register 87: USB Receive Functional Address Endpoint 3
(USBRXFUNCADDR3), offset 0x09C
Register 88: USB Receive Functional Address Endpoint 4
(USBRXFUNCADDR4), offset 0x0A4
Register 89: USB Receive Functional Address Endpoint 5
(USBRXFUNCADDR5), offset 0x0AC
Register 90: USB Receive Functional Address Endpoint 6
(USBRXFUNCADDR6), offset 0x0B4
Register 91: USB Receive Functional Address Endpoint 7
(USBRXFUNCADDR7), offset 0x0BC
Register 92: USB Receive Functional Address Endpoint 8
(USBRXFUNCADDR8), offset 0x0C4
Register 93: USB Receive Functional Address Endpoint 9
(USBRXFUNCADDR9), offset 0x0CC
Register 94: USB Receive Functional Address Endpoint 10
(USBRXFUNCADDR10), offset 0x0D4
Register 95: USB Receive Functional Address Endpoint 11
(USBRXFUNCADDR11), offset 0x0DC
Register 96: USB Receive Functional Address Endpoint 12
(USBRXFUNCADDR12), offset 0x0E4
Register 97: USB Receive Functional Address Endpoint 13
(USBRXFUNCADDR13), offset 0x0EC
Register 98: USB Receive Functional Address Endpoint 14
(USBRXFUNCADDR14), offset 0x0F4
Register 99: USB Receive Functional Address Endpoint 15
(USBRXFUNCADDR15), offset 0x0FC
OTG A /
Host
USBRXFUNCADDRn is an 8-bit read/write register that records the address of the target function
accessed through the associated endpoint (EPn). USBRXFUNCADDRn must be defined for each
receive endpoint that is used.
Note:
USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0.
874
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1)
Base 0x4005.0000
Offset 0x08C
Type R/W, reset 0x00
7
6
5
4
R/W
0
R/W
0
R/W
0
RO
0
2
1
0
R/W
0
R/W
0
R/W
0
ADDR
reserved
Type
Reset
3
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
ADDR
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Device Address
This field specifies the USB bus address for the target Device.
May 24, 2010
875
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 100: USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1),
offset 0x08E
Register 101: USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2),
offset 0x096
Register 102: USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3),
offset 0x09E
Register 103: USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4),
offset 0x0A6
Register 104: USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5),
offset 0x0AE
Register 105: USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6),
offset 0x0B6
Register 106: USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7),
offset 0x0BE
Register 107: USB Receive Hub Address Endpoint 8 (USBRXHUBADDR8),
offset 0x0C6
Register 108: USB Receive Hub Address Endpoint 9 (USBRXHUBADDR9),
offset 0x0CE
Register 109: USB Receive Hub Address Endpoint 10 (USBRXHUBADDR10),
offset 0x0D6
Register 110: USB Receive Hub Address Endpoint 11 (USBRXHUBADDR11),
offset 0x0DE
Register 111: USB Receive Hub Address Endpoint 12 (USBRXHUBADDR12),
offset 0x0E6
Register 112: USB Receive Hub Address Endpoint 13 (USBRXHUBADDR13),
offset 0x0EE
Register 113: USB Receive Hub Address Endpoint 14 (USBRXHUBADDR14),
offset 0x0F6
Register 114: USB Receive Hub Address Endpoint 15 (USBRXHUBADDR15),
offset 0x0FE
OTG A /
Host
USBRXHUBADDRn is an 8-bit read/write register that, like USBRXHUBPORTn, only must be
written when a full- or low-speed Device is connected to receive endpoint EPn via a USB 2.0 hub.
This register records the address of the USB 2.0 hub through which the target associated with the
endpoint is accessed.
Note:
USBTXHUBADDR0 is used for both receive and transmit for endpoint 0.
876
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1)
Base 0x4005.0000
Offset 0x08E
Type R/W, reset 0x00
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
ADDR
MULTTRAN
Type
Reset
3
R/W
0
Bit/Field
Name
Type
Reset
7
MULTTRAN
R/W
0
Description
Multiple Translators
Value Description
6:0
ADDR
R/W
0x00
0
Clear to indicate that the hub has a single transaction translator.
1
Set to indicate that the hub has multiple transaction translators.
Hub Address
This field specifies the USB bus address for the USB 2.0 hub.
May 24, 2010
877
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 115: USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset
0x08F
Register 116: USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset
0x097
Register 117: USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset
0x09F
Register 118: USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset
0x0A7
Register 119: USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset
0x0AF
Register 120: USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset
0x0B7
Register 121: USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset
0x0BF
Register 122: USB Receive Hub Port Endpoint 8 (USBRXHUBPORT8), offset
0x0C7
Register 123: USB Receive Hub Port Endpoint 9 (USBRXHUBPORT9), offset
0x0CF
Register 124: USB Receive Hub Port Endpoint 10 (USBRXHUBPORT10), offset
0x0D7
Register 125: USB Receive Hub Port Endpoint 11 (USBRXHUBPORT11), offset
0x0DF
Register 126: USB Receive Hub Port Endpoint 12 (USBRXHUBPORT12), offset
0x0E7
Register 127: USB Receive Hub Port Endpoint 13 (USBRXHUBPORT13), offset
0x0EF
Register 128: USB Receive Hub Port Endpoint 14 (USBRXHUBPORT14), offset
0x0F7
Register 129: USB Receive Hub Port Endpoint 15 (USBRXHUBPORT15), offset
0x0FF
OTG A /
Host
USBRXHUBPORTn is an 8-bit read/write register that, like USBRXHUBADDRn, only must be
written when a full- or low-speed Device is connected to receive endpoint EPn via a USB 2.0 hub.
This register records the port of the USB 2.0 hub through which the target associated with the
endpoint is accessed.
Note:
USBTXHUBPORT0 is used for both receive and transmit for endpoint 0.
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Stellaris® LM3S5B91 Microcontroller
USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1)
Base 0x4005.0000
Offset 0x08F
Type R/W, reset 0x00
7
6
5
4
R/W
0
R/W
0
R/W
0
RO
0
2
1
0
R/W
0
R/W
0
R/W
0
PORT
reserved
Type
Reset
3
R/W
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
PORT
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hub Port
This field specifies the USB hub port number.
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 130: USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset
0x110
Register 131: USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset
0x120
Register 132: USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset
0x130
Register 133: USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset
0x140
Register 134: USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset
0x150
Register 135: USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset
0x160
Register 136: USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset
0x170
Register 137: USB Maximum Transmit Data Endpoint 8 (USBTXMAXP8), offset
0x180
Register 138: USB Maximum Transmit Data Endpoint 9 (USBTXMAXP9), offset
0x190
Register 139: USB Maximum Transmit Data Endpoint 10 (USBTXMAXP10),
offset 0x1A0
Register 140: USB Maximum Transmit Data Endpoint 11 (USBTXMAXP11),
offset 0x1B0
Register 141: USB Maximum Transmit Data Endpoint 12 (USBTXMAXP12),
offset 0x1C0
Register 142: USB Maximum Transmit Data Endpoint 13 (USBTXMAXP13),
offset 0x1D0
Register 143: USB Maximum Transmit Data Endpoint 14 (USBTXMAXP14),
offset 0x1E0
Register 144: USB Maximum Transmit Data Endpoint 15 (USBTXMAXP15),
offset 0x1F0
OTG A /
Host
OTG B /
Device
The USBTXMAXPn 16-bit register defines the maximum amount of data that can be transferred
through the transmit endpoint in a single operation.
Bits [10:0] define (in bytes) the maximum payload transmitted in a single transaction. The value set
can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet
sizes for bulk, interrupt and isochronous transfers in full-speed operation.
The total amount of data represented by the value written to this register must not exceed the FIFO
size for the transmit endpoint, and must not exceed half the FIFO size if double-buffering is required.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
If this register is changed after packets have been sent from the endpoint, the transmit endpoint
FIFO must be completely flushed (using the FLUSH bit in USBTXCSRL1n) after writing the new
value to this register.
Note:
USBTXMAXPn must be set to an even number of bytes for proper interrupt generation in
µDMA Basic Mode.
USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1)
Base 0x4005.0000
Offset 0x110
Type R/W, reset 0x0000
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MAXLOAD
RO
0
RO
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
15:11
reserved
RO
0x0
10:0
MAXLOAD
R/W
0x000
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Maximum Payload
This field specifies the maximum payload in bytes per transaction.
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 145: USB Control and Status Endpoint 0 Low (USBCSRL0), offset
0x102
OTG A /
USBCSRL0 is an 8-bit register that provides control and status bits for endpoint 0.
Host
OTG B /
Device
OTG A / Host Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
7
NAKTO
Type
Reset
R/W
0
6
5
STATUS REQPKT
R/W
0
4
3
2
1
0
ERROR
SETUP
STALLED
TXRDY
RXRDY
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7
NAKTO
R/W
0
Description
NAK Timeout
Value Description
0
No timeout.
1
Indicates that endpoint 0 is halted following the receipt of NAK
responses for longer than the time set by the USBNAKLMT
register.
Software must clear this bit to allow the endpoint to continue.
6
STATUS
R/W
0
STATUS Packet
Value Description
0
No transaction.
1
Initiates a STATUS stage transaction. This bit must be set at
the same time as the TXRDY or REQPKT bit is set.
Setting this bit ensures that the DT bit is set in the USBCSRH0 register
so that a DATA1 packet is used for the STATUS stage transaction.
This bit is automatically cleared when the STATUS stage is over.
5
REQPKT
R/W
0
Request Packet
Value Description
0
No request.
1
Requests an IN transaction.
This bit is cleared when the RXRDY bit is set.
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4
ERROR
R/W
0
Description
Error
Value Description
0
No error.
1
Three attempts have been made to perform a transaction with
no response from the peripheral. The EP0 bit in the USBTXIS
register is also set in this situation.
Software must clear this bit.
3
SETUP
R/W
0
Setup Packet
Value Description
0
Sends an OUT token.
1
Sends a SETUP token instead of an OUT token for the
transaction. This bit should be set at the same time as the
TXRDY bit is set.
Setting this bit always clears the DT bit in the USBCSRH0 register to
send a DATA0 packet.
2
STALLED
R/W
0
Endpoint Stalled
Value Description
0
No handshake has been received.
1
A STALL handshake has been received.
Software must clear this bit.
1
TXRDY
R/W
0
Transmit Packet Ready
Value Description
0
No transmit packet is ready.
1
Software sets this bit after loading a data packet into the TX
FIFO. The EP0 bit in the USBTXIS register is also set in this
situation.
If both the TXRDY and SETUP bits are set, a setup packet is
sent. If just TXRDY is set, an OUT packet is sent.
This bit is cleared automatically when the data packet has been
transmitted.
0
RXRDY
R/W
0
Receive Packet Ready
Value Description
0
No received packet has been received.
1
Indicates that a data packet has been received in the RX FIFO.
The EP0 bit in the USBTXIS register is also set in this situation.
Software must clear this bit after the packet has been read from the
FIFO to acknowledge that the data has been read from the FIFO.
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
OTG B / Device Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
7
6
SETENDC RXRDYC
Type
Reset
W1C
0
W1C
0
5
STALL
4
3
2
SETEND DATAEND STALLED
R/W
0
RO
0
R/W
0
R/W
0
1
0
TXRDY
RXRDY
R/W
0
RO
0
Bit/Field
Name
Type
Reset
7
SETENDC
W1C
0
Description
Setup End Clear
Writing a 1 to this bit clears the SETEND bit.
6
RXRDYC
W1C
0
RXRDY Clear
Writing a 1 to this bit clears the RXRDY bit.
5
STALL
R/W
0
Send Stall
Value Description
0
No effect.
1
Terminates the current transaction and transmits the STALL
handshake.
This bit is cleared automatically after the STALL handshake is
transmitted.
4
SETEND
RO
0
Setup End
Value Description
0
A control transaction has not ended or ended after the DATAEND
bit was set.
1
A control transaction has ended before the DATAEND bit has
been set. The EP0 bit in the USBTXIS register is also set in this
situation.
This bit is cleared by writing a 1 to the SETENDC bit.
3
DATAEND
R/W
0
Data End
Value Description
0
No effect.
1
Set this bit in the following situations:
■
When setting TXRDY for the last data packet
■
When clearing RXRDY after unloading the last data
packet
■
When setting TXRDY for a zero-length data packet
This bit is cleared automatically.
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
2
STALLED
R/W
0
Description
Endpoint Stalled
Value Description
0
A STALL handshake has not been transmitted.
1
A STALL handshake has been transmitted.
Software must clear this bit.
1
TXRDY
R/W
0
Transmit Packet Ready
Value Description
0
No transmit packet is ready.
1
Software sets this bit after loading an IN data packet into the
TX FIFO. The EP0 bit in the USBTXIS register is also set in this
situation.
This bit is cleared automatically when the data packet has been
transmitted.
0
RXRDY
RO
0
Receive Packet Ready
Value Description
0
No data packet has been received.
1
A data packet has been received. The EP0 bit in the USBTXIS
register is also set in this situation.
This bit is cleared by writing a 1 to the RXRDYC bit.
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 146: USB Control and Status Endpoint 0 High (USBCSRH0), offset
0x103
OTG A /
USBSR0H is an 8-bit register that provides control and status bits for endpoint 0.
Host
OTG B /
Device
OTG A / Host Mode
USB Control and Status Endpoint 0 High (USBCSRH0)
Base 0x4005.0000
Offset 0x103
Type W1C, reset 0x00
7
6
RO
0
RO
0
5
4
3
RO
0
RO
0
2
reserved
Type
Reset
RO
0
1
0
DTWE
DT
FLUSH
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7:3
reserved
RO
0x0
2
DTWE
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data Toggle Write Enable
Value Description
0
The DT bit cannot be written.
1
Enables the current state of the endpoint 0 data toggle to be
written (see DT bit).
This bit is automatically cleared once the new value is written.
1
DT
R/W
0
Data Toggle
When read, this bit indicates the current state of the endpoint 0 data
toggle.
If DTWE is set, this bit may be written with the required setting of the data
toggle. If DTWE is Low, this bit cannot be written. Care should be taken
when writing to this bit as it should only be changed to RESET USB
endpoint 0.
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
Description
0
FLUSH
R/W
0
Flush FIFO
Value Description
0
No effect.
1
Flushes the next packet to be transmitted/read from the endpoint
0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is
cleared.
This bit is automatically cleared after the flush is performed.
Important:
This bit should only be set when TXRDY/RXRDY is set.
At other times, it may cause data to be corrupted.
OTG B / Device Mode
USB Control and Status Endpoint 0 High (USBCSRH0)
Base 0x4005.0000
Offset 0x103
Type W1C, reset 0x00
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
0
FLUSH
RO
0
RO
0
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
7:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
FLUSH
R/W
0
Flush FIFO
Value Description
0
No effect.
1
Flushes the next packet to be transmitted/read from the endpoint
0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is
cleared.
This bit is automatically cleared after the flush is performed.
Important:
This bit should only be set when TXRDY/RXRDY is set.
At other times, it may cause data to be corrupted.
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 147: USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108
OTG A /
Host
USBCOUNT0 is an 8-bit read-only register that indicates the number of received data bytes in the
endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid
while the RXRDY bit is set.
USB Receive Byte Count Endpoint 0 (USBCOUNT0)
OTG B /
Device
Base 0x4005.0000
Offset 0x108
Type RO, reset 0x00
7
6
5
4
RO
0
RO
0
RO
0
RO
0
2
1
0
RO
0
RO
0
RO
0
COUNT
reserved
Type
Reset
3
RO
0
Bit/Field
Name
Type
Reset
7
reserved
RO
0
6:0
COUNT
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Count
COUNT is a read-only value that indicates the number of received data
bytes in the endpoint 0 FIFO.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 148: USB Type Endpoint 0 (USBTYPE0), offset 0x10A
OTG A /
Host
This is an 8-bit register that must be written with the operating speed of the targeted Device being
communicated with using endpoint 0.
USB Type Endpoint 0 (USBTYPE0)
Base 0x4005.0000
Offset 0x10A
Type R/W, reset 0x00
7
6
5
4
3
R/W
0
RO
0
RO
0
RO
0
SPEED
Type
Reset
R/W
0
2
1
0
RO
0
RO
0
RO
0
reserved
Bit/Field
Name
Type
Reset
7:6
SPEED
R/W
0x0
Description
Operating Speed
This field specifies the operating speed of the target Device. If selected,
the target is assumed to have the same connection speed as the USB
controller.
Value
Description
0x0 - 0x1 Reserved
5:0
reserved
RO
0x0
0x2
Full
0x3
Low
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 149: USB NAK Limit (USBNAKLMT), offset 0x10B
OTG A /
Host
USBNAKLMT is an 8-bit register that sets the number of frames after which endpoint 0 should time
out on receiving a stream of NAK responses. (Equivalent settings for other endpoints can be made
through their USBTXINTERVALn and USBRXINTERVALn registers.)
(m-1)
The number of frames selected is 2
(where m is the value set in the register, with valid values
of 2–16). If the Host receives NAK responses from the target for more frames than the number
represented by the limit set in this register, the endpoint is halted.
Note:
A value of 0 or 1 disables the NAK timeout function.
USB NAK Limit (USBNAKLMT)
Base 0x4005.0000
Offset 0x10B
Type R/W, reset 0x00
7
6
5
4
3
2
RO
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
1
0
R/W
0
R/W
0
NAKLMT
R/W
0
Bit/Field
Name
Type
Reset
Description
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0
NAKLMT
R/W
0x0
EP0 NAK Limit
This field specifies the number of frames after receiving a stream of
NAK responses.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 150: USB Transmit Control and Status Endpoint 1 Low
(USBTXCSRL1), offset 0x112
Register 151: USB Transmit Control and Status Endpoint 2 Low
(USBTXCSRL2), offset 0x122
Register 152: USB Transmit Control and Status Endpoint 3 Low
(USBTXCSRL3), offset 0x132
Register 153: USB Transmit Control and Status Endpoint 4 Low
(USBTXCSRL4), offset 0x142
Register 154: USB Transmit Control and Status Endpoint 5 Low
(USBTXCSRL5), offset 0x152
Register 155: USB Transmit Control and Status Endpoint 6 Low
(USBTXCSRL6), offset 0x162
Register 156: USB Transmit Control and Status Endpoint 7 Low
(USBTXCSRL7), offset 0x172
Register 157: USB Transmit Control and Status Endpoint 8 Low
(USBTXCSRL8), offset 0x182
Register 158: USB Transmit Control and Status Endpoint 9 Low
(USBTXCSRL9), offset 0x192
Register 159: USB Transmit Control and Status Endpoint 10 Low
(USBTXCSRL10), offset 0x1A2
Register 160: USB Transmit Control and Status Endpoint 11 Low
(USBTXCSRL11), offset 0x1B2
Register 161: USB Transmit Control and Status Endpoint 12 Low
(USBTXCSRL12), offset 0x1C2
Register 162: USB Transmit Control and Status Endpoint 13 Low
(USBTXCSRL13), offset 0x1D2
Register 163: USB Transmit Control and Status Endpoint 14 Low
(USBTXCSRL14), offset 0x1E2
Register 164: USB Transmit Control and Status Endpoint 15 Low
(USBTXCSRL15), offset 0x1F2
OTG A /
USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected transmit endpoint.
Host
OTG B /
Device
May 24, 2010
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
OTG A / Host Mode
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
Type
Reset
7
6
5
4
3
2
1
0
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7
NAKTO
R/W
0
Description
NAK Timeout
Value Description
6
CLRDT
R/W
0
0
No timeout.
1
Bulk endpoints only: Indicates that the transmit endpoint is halted
following the receipt of NAK responses for longer than the time
set by the NAKLMT field in the USBTXINTERVALn register.
Software must clear this bit to allow the endpoint to continue.
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register.
5
STALLED
R/W
0
Endpoint Stalled
Value Description
0
A STALL handshake has not been received.
1
Indicates that a STALL handshake has been received. When
this bit is set, any µDMA request that is in progress is stopped,
the FIFO is completely flushed, and the TXRDY bit is cleared.
Software must clear this bit.
4
SETUP
R/W
0
Setup Packet
Value Description
0
No SETUP token is sent.
1
Sends a SETUP token instead of an OUT token for the
transaction. This bit should be set at the same time as the
TXRDY bit is set.
Note:
Setting this bit also clears the DT bit in the USBTXCSRHn
register.
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
Description
3
FLUSH
R/W
0
Flush FIFO
Value Description
0
No effect.
1
Flushes the latest packet from the endpoint transmit FIFO. The
FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit
in the USBTXIS register is also set in this situation.
This bit may be set simultaneously with the TXRDY bit to abort the packet
that is currently being loaded into the FIFO. Note that if the FIFO is
double-buffered, FLUSH may have to be set twice to completely clear
the FIFO.
Important:
2
ERROR
R/W
0
This bit should only be set when the TXRDY bit is set. At
other times, it may cause data to be corrupted.
Error
Value Description
0
No error.
1
Three attempts have been made to send a packet and no
handshake packet has been received. The TXRDY bit is cleared,
the EPn bit in the USBTXIS register is set, and the FIFO is
completely flushed in this situation.
Software must clear this bit.
Note:
1
FIFONE
R/W
0
This is valid only when the endpoint is operating in Bulk or
Interrupt mode.
FIFO Not Empty
Value Description
0
TXRDY
R/W
0
0
The FIFO is empty.
1
At least one packet is in the transmit FIFO.
Transmit Packet Ready
Value Description
0
No transmit packet is ready.
1
Software sets this bit after loading a data packet into the TX
FIFO.
This bit is cleared automatically when a data packet has been
transmitted. The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.
May 24, 2010
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
OTG B / Device Mode
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
Type
Reset
7
6
5
4
3
2
1
0
reserved
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
CLRDT
R/W
0
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register.
5
STALLED
R/W
0
Endpoint Stalled
Value Description
0
A STALL handshake has not been transmitted.
1
A STALL handshake has been transmitted. The FIFO is flushed
and the TXRDY bit is cleared.
Software must clear this bit.
4
STALL
R/W
0
Send STALL
Value Description
0
No effect.
1
Issues a STALL handshake to an IN token.
Software clears this bit to terminate the STALL condition.
Note:
3
FLUSH
R/W
0
This bit has no effect in isochronous transfers.
Flush FIFO
Value Description
0
No effect.
1
Flushes the latest packet from the endpoint transmit FIFO. The
FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit
in the USBTXIS register is also set in this situation.
This bit may be set simultaneously with the TXRDY bit to abort the packet
that is currently being loaded into the FIFO. Note that if the FIFO is
double-buffered, FLUSH may have to be set twice to completely clear
the FIFO.
Important:
This bit should only be set when the TXRDY bit is set. At
other times, it may cause data to be corrupted.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
2
UNDRN
R/W
0
Description
Underrun
Value Description
0
No underrun.
1
An IN token has been received when TXRDY is not set.
Software must clear this bit.
1
FIFONE
R/W
0
FIFO Not Empty
Value Description
0
TXRDY
R/W
0
0
The FIFO is empty.
1
At least one packet is in the transmit FIFO.
Transmit Packet Ready
Value Description
0
No transmit packet is ready.
1
Software sets this bit after loading a data packet into the TX
FIFO.
This bit is cleared automatically when a data packet has been
transmitted. The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 165: USB Transmit Control and Status Endpoint 1 High
(USBTXCSRH1), offset 0x113
Register 166: USB Transmit Control and Status Endpoint 2 High
(USBTXCSRH2), offset 0x123
Register 167: USB Transmit Control and Status Endpoint 3 High
(USBTXCSRH3), offset 0x133
Register 168: USB Transmit Control and Status Endpoint 4 High
(USBTXCSRH4), offset 0x143
Register 169: USB Transmit Control and Status Endpoint 5 High
(USBTXCSRH5), offset 0x153
Register 170: USB Transmit Control and Status Endpoint 6 High
(USBTXCSRH6), offset 0x163
Register 171: USB Transmit Control and Status Endpoint 7 High
(USBTXCSRH7), offset 0x173
Register 172: USB Transmit Control and Status Endpoint 8 High
(USBTXCSRH8), offset 0x183
Register 173: USB Transmit Control and Status Endpoint 9 High
(USBTXCSRH9), offset 0x193
Register 174: USB Transmit Control and Status Endpoint 10 High
(USBTXCSRH10), offset 0x1A3
Register 175: USB Transmit Control and Status Endpoint 11 High
(USBTXCSRH11), offset 0x1B3
Register 176: USB Transmit Control and Status Endpoint 12 High
(USBTXCSRH12), offset 0x1C3
Register 177: USB Transmit Control and Status Endpoint 13 High
(USBTXCSRH13), offset 0x1D3
Register 178: USB Transmit Control and Status Endpoint 14 High
(USBTXCSRH14), offset 0x1E3
Register 179: USB Transmit Control and Status Endpoint 15 High
(USBTXCSRH15), offset 0x1F3
OTG A /
USBTXCSRHn is an 8-bit register that provides additional control for transfers through the currently
selected transmit endpoint.
Host
OTG B /
Device
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
OTG A / Host Mode
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1)
Base 0x4005.0000
Offset 0x113
Type R/W, reset 0x00
7
6
AUTOSET reserved
Type
Reset
R/W
0
RO
0
5
4
3
2
1
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7
AUTOSET
R/W
0
0
Description
Auto Set
Value Description
0
The TXRDY bit must be set manually.
1
Enables the TXRDY bit to be automatically set when data of the
maximum packet size (value in USBTXMAXPn) is loaded into
the transmit FIFO. If a packet of less than the maximum packet
size is loaded, then the TXRDY bit must be set manually.
6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
MODE
R/W
0
Mode
Value Description
0
Enables the endpoint direction as RX.
1
Enables the endpoint direction as TX.
Note:
4
DMAEN
R/W
0
This bit only has an effect when the same endpoint FIFO is
used for both transmit and receive transactions.
DMA Request Enable
Value Description
0
Disables the µDMA request for the transmit endpoint.
1
Enables the µDMA request for the transmit endpoint.
Note:
3
FDT
R/W
0
3 TX and 3 /RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAATX,
DMABTX, or DMACTX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
Force Data Toggle
Value Description
0
No effect.
1
Forces the endpoint DT bit to switch and the data packet to be
cleared from the FIFO, regardless of whether an ACK was
received. This bit can be used by interrupt transmit endpoints
that are used to communicate rate feedback for isochronous
endpoints.
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
2
DMAMOD
R/W
0
Description
DMA Request Mode
Value Description
0
An interrupt is generated after every µDMA packet transfer.
1
An interrupt is generated only after the entire μDMA transfer is
complete.
Note:
1
DTWE
R/W
0
This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
Data Toggle Write Enable
Value Description
0
The DT bit cannot be written.
1
Enables the current state of the transmit endpoint data to be
written (see DT bit).
This bit is automatically cleared once the new value is written.
0
DT
R/W
0
Data Toggle
When read, this bit indicates the current state of the transmit endpoint
data toggle.
If DTWE is High, this bit may be written with the required setting of the
data toggle. If DTWE is Low, any value written to this bit is ignored. Care
should be taken when writing to this bit as it should only be changed to
RESET the transmit endpoint.
OTG B / Device Mode
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1)
Base 0x4005.0000
Offset 0x113
Type R/W, reset 0x00
7
Type
Reset
6
5
4
3
2
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
1
0
reserved
RO
0
Bit/Field
Name
Type
Reset
7
AUTOSET
R/W
0
RO
0
Description
Auto Set
Value Description
0
The TXRDY bit must be set manually.
1
Enables the TXRDY bit to be automatically set when data of the
maximum packet size (value in USBTXMAXPn) is loaded into
the transmit FIFO. If a packet of less than the maximum packet
size is loaded, then the TXRDY bit must be set manually.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
6
ISO
R/W
0
Description
Isochronous Transfers
Value Description
5
MODE
R/W
0
0
Enables the transmit endpoint for bulk or interrupt transfers.
1
Enables the transmit endpoint for isochronous transfers.
Mode
Value Description
0
Enables the endpoint direction as RX.
1
Enables the endpoint direction as TX.
Note:
4
DMAEN
R/W
0
This bit only has an effect where the same endpoint FIFO is
used for both transmit and receive transactions.
DMA Request Enable
Value Description
0
Disables the µDMA request for the transmit endpoint.
1
Enables the µDMA request for the transmit endpoint.
Note:
3
FDT
R/W
0
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAATX,
DMABTX, or DMACTX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
Force Data Toggle
Value Description
2
DMAMOD
R/W
0
0
No effect.
1
Forces the endpoint DT bit to switch and the data packet to be
cleared from the FIFO, regardless of whether an ACK was
received. This bit can be used by interrupt transmit endpoints
that are used to communicate rate feedback for isochronous
endpoints.
DMA Request Mode
Value Description
0
An interrupt is generated after every µDMA packet transfer.
1
An interrupt is generated only after the entire μDMA transfer is
complete.
Note:
1:0
reserved
RO
0x0
This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 180: USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset
0x114
Register 181: USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset
0x124
Register 182: USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset
0x134
Register 183: USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset
0x144
Register 184: USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset
0x154
Register 185: USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset
0x164
Register 186: USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset
0x174
Register 187: USB Maximum Receive Data Endpoint 8 (USBRXMAXP8), offset
0x184
Register 188: USB Maximum Receive Data Endpoint 9 (USBRXMAXP9), offset
0x194
Register 189: USB Maximum Receive Data Endpoint 10 (USBRXMAXP10),
offset 0x1A4
Register 190: USB Maximum Receive Data Endpoint 11 (USBRXMAXP11),
offset 0x1B4
Register 191: USB Maximum Receive Data Endpoint 12 (USBRXMAXP12),
offset 0x1C4
Register 192: USB Maximum Receive Data Endpoint 13 (USBRXMAXP13),
offset 0x1D4
Register 193: USB Maximum Receive Data Endpoint 14 (USBRXMAXP14),
offset 0x1E4
Register 194: USB Maximum Receive Data Endpoint 15 (USBRXMAXP15),
offset 0x1F4
OTG A /
Host
OTG B /
Device
The USBRXMAXPn is a 16-bit register which defines the maximum amount of data that can be
transferred through the selected receive endpoint in a single operation.
Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set
can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet
sizes for bulk, interrupt and isochronous transfers in full-speed operations.
The total amount of data represented by the value written to this register must not exceed the FIFO
size for the receive endpoint, and must not exceed half the FIFO size if double-buffering is required.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Note:
USBRXMAXPn must be set to an even number of bytes for proper interrupt generation in
µDMA Basic mode.
USB Maximum Receive Data Endpoint 1 (USBRXMAXP1)
Base 0x4005.0000
Offset 0x114
Type R/W, reset 0x0000
15
14
RO
0
RO
0
13
12
11
10
9
8
7
6
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MAXLOAD
Bit/Field
Name
Type
Reset
15:11
reserved
RO
0x0
10:0
MAXLOAD
R/W
0x000
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Maximum Payload
The maximum payload in bytes per transaction.
May 24, 2010
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 195: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1),
offset 0x116
Register 196: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2),
offset 0x126
Register 197: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3),
offset 0x136
Register 198: USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4),
offset 0x146
Register 199: USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5),
offset 0x156
Register 200: USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6),
offset 0x166
Register 201: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7),
offset 0x176
Register 202: USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8),
offset 0x186
Register 203: USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9),
offset 0x196
Register 204: USB Receive Control and Status Endpoint 10 Low
(USBRXCSRL10), offset 0x1A6
Register 205: USB Receive Control and Status Endpoint 11 Low
(USBRXCSRL11), offset 0x1B6
Register 206: USB Receive Control and Status Endpoint 12 Low
(USBRXCSRL12), offset 0x1C6
Register 207: USB Receive Control and Status Endpoint 13 Low
(USBRXCSRL13), offset 0x1D6
Register 208: USB Receive Control and Status Endpoint 14 Low
(USBRXCSRL14), offset 0x1E6
Register 209: USB Receive Control and Status Endpoint 15 Low
(USBRXCSRL15), offset 0x1F6
OTG A /
USBRXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected receive endpoint.
Host
OTG B /
Device
902
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
OTG A / Host Mode
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1)
Base 0x4005.0000
Offset 0x116
Type R/W, reset 0x00
7
CLRDT
Type
Reset
W1C
0
6
5
STALLED REQPKT
R/W
0
4
FLUSH
R/W
0
R/W
0
3
DATAERR /
NAKTO
2
1
0
ERROR
FULL
RXRDY
R/W
0
RO
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
7
CLRDT
W1C
0
Description
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register.
6
STALLED
R/W
0
Endpoint Stalled
Value Description
0
A STALL handshake has not been received.
1
A STALL handshake has been received. The EPn bit in the
USBRXIS register is also set.
Software must clear this bit.
5
REQPKT
R/W
0
Request Packet
Value Description
0
No request.
1
Requests an IN transaction.
This bit is cleared when RXRDY is set.
4
FLUSH
R/W
0
Flush FIFO
Value Description
0
No effect.
1
Flushes the next packet to be read from the endpoint receive
FIFO. The FIFO pointer is reset and the RXRDY bit is cleared.
Note that if the FIFO is double-buffered, FLUSH may have to be set
twice to completely clear the FIFO.
Important:
This bit should only be set when the RXRDY bit is set. At
other times, it may cause data to be corrupted.
May 24, 2010
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
3
DATAERR / NAKTO
R/W
0
Description
Data Error / NAK Timeout
Value Description
0
Normal operation.
1
Isochronous endpoints only: Indicates that RXRDY is set and
the data packet has a CRC or bit-stuff error. This bit is cleared
when RXRDY is cleared.
Bulk endpoints only: Indicates that the receive endpoint is halted
following the receipt of NAK responses for longer than the time
set by the NAKLMT field in the USBRXINTERVALn register.
Software must clear this bit to allow the endpoint to continue.
2
ERROR
R/W
0
Error
Value Description
0
No error.
1
Three attempts have been made to receive a packet and no
data packet has been received. The EPn bit in the USBRXIS
register is set in this situation.
Software must clear this bit.
Note:
1
FULL
RO
0
This bit is only valid when the receive endpoint is operating
in Bulk or Interrupt mode. In Isochronous mode, it always
returns zero.
FIFO Full
Value Description
0
RXRDY
R/W
0
0
The receive FIFO is not full.
1
No more packets can be loaded into the receive FIFO.
Receive Packet Ready
Value Description
0
No data packet has been received.
1
A data packet has been received. The EPn bit in the USBRXIS
register is also set in this situation.
If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit
is automatically cleared when a packet of USBRXMAXPn bytes has
been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if
packets of less than the maximum packet size are unloaded, then
software must clear this bit manually when the packet has been unloaded
from the receive FIFO.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
OTG B / Device Mode
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1)
Base 0x4005.0000
Offset 0x116
Type R/W, reset 0x00
Type
Reset
7
6
5
CLRDT
STALLED
STALL
W1C
0
R/W
0
R/W
0
4
3
FLUSH DATAERR
R/W
0
2
1
0
OVER
FULL
RXRDY
R/W
0
RO
0
R/W
0
RO
0
Bit/Field
Name
Type
Reset
7
CLRDT
W1C
0
Description
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register.
6
STALLED
R/W
0
Endpoint Stalled
Value Description
0
A STALL handshake has not been transmitted.
1
A STALL handshake has been transmitted.
Software must clear this bit.
5
STALL
R/W
0
Send STALL
Value Description
0
No effect.
1
Issues a STALL handshake.
Software must clear this bit to terminate the STALL condition.
Note:
4
FLUSH
R/W
0
This bit has no effect where the endpoint is being used for
isochronous transfers.
Flush FIFO
Value Description
0
No effect.
1
Flushes the next packet from the endpoint receive FIFO. The
FIFO pointer is reset and the RXRDY bit is cleared.
The CPU writes a 1 to this bit to flush the next packet to be read from
the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared. Note that if the FIFO is double-buffered, FLUSH may have
to be set twice to completely clear the FIFO.
Important:
This bit should only be set when the RXRDY bit is set. At
other times, it may cause data to be corrupted.
May 24, 2010
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Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
3
DATAERR
RO
0
Data Error
Value Description
0
Normal operation.
1
Indicates that RXRDY is set and the data packet has a CRC or
bit-stuff error.
This bit is cleared when RXRDY is cleared.
Note:
2
OVER
R/W
0
This bit is only valid when the endpoint is operating in
Isochronous mode. In Bulk mode, it always returns zero.
Overrun
Value Description
0
No overrun error.
1
Indicates that an OUT packet cannot be loaded into the receive
FIFO.
Software must clear this bit.
Note:
1
FULL
RO
0
This bit is only valid when the endpoint is operating in
Isochronous mode. In Bulk mode, it always returns zero.
FIFO Full
Value Description
0
RXRDY
R/W
0
0
The receive FIFO is not full.
1
No more packets can be loaded into the receive FIFO.
Receive Packet Ready
Value Description
0
No data packet has been received.
1
A data packet has been received. The EPn bit in the USBRXIS
register is also set in this situation.
If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit
is automatically cleared when a packet of USBRXMAXPn bytes has
been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if
packets of less than the maximum packet size are unloaded, then
software must clear this bit manually when the packet has been unloaded
from the receive FIFO.
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 210: USB Receive Control and Status Endpoint 1 High
(USBRXCSRH1), offset 0x117
Register 211: USB Receive Control and Status Endpoint 2 High
(USBRXCSRH2), offset 0x127
Register 212: USB Receive Control and Status Endpoint 3 High
(USBRXCSRH3), offset 0x137
Register 213: USB Receive Control and Status Endpoint 4 High
(USBRXCSRH4), offset 0x147
Register 214: USB Receive Control and Status Endpoint 5 High
(USBRXCSRH5), offset 0x157
Register 215: USB Receive Control and Status Endpoint 6 High
(USBRXCSRH6), offset 0x167
Register 216: USB Receive Control and Status Endpoint 7 High
(USBRXCSRH7), offset 0x177
Register 217: USB Receive Control and Status Endpoint 8 High
(USBRXCSRH8), offset 0x187
Register 218: USB Receive Control and Status Endpoint 9 High
(USBRXCSRH9), offset 0x197
Register 219: USB Receive Control and Status Endpoint 10 High
(USBRXCSRH10), offset 0x1A7
Register 220: USB Receive Control and Status Endpoint 11 High
(USBRXCSRH11), offset 0x1B7
Register 221: USB Receive Control and Status Endpoint 12 High
(USBRXCSRH12), offset 0x1C7
Register 222: USB Receive Control and Status Endpoint 13 High
(USBRXCSRH13), offset 0x1D7
Register 223: USB Receive Control and Status Endpoint 14 High
(USBRXCSRH14), offset 0x1E7
Register 224: USB Receive Control and Status Endpoint 15 High
(USBRXCSRH15), offset 0x1F7
OTG A /
USBRXCSRHn is an 8-bit register that provides additional control and status bits for transfers
through the currently selected receive endpoint.
Host
OTG B /
Device
May 24, 2010
907
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
OTG A / Host Mode
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1)
Base 0x4005.0000
Offset 0x117
Type R/W, reset 0x00
7
6
5
AUTOCL AUTORQ DMAEN
Type
Reset
R/W
0
R/W
0
4
3
2
PIDERR DMAMOD
R/W
0
RO
0
1
0
DTWE
DT
reserved
RO
0
RO
0
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
7
AUTOCL
R/W
0
Auto Clear
Value Description
6
AUTORQ
R/W
0
0
No effect.
1
Enables the RXRDY bit to be automatically cleared when a packet
of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are
unloaded, RXRDY must be cleared manually. Care must be taken
when using µDMA to unload the receive FIFO as data is read
from the receive FIFO in 4 byte chunks regardless of the value
of the MAXLOAD field in the USBRXMAXPn register, see “DMA
Operation” on page 822.
Auto Request
Value Description
0
No effect.
1
Enables the REQPKT bit to be automatically set when the RXRDY
bit is cleared.
Note:
5
DMAEN
R/W
0
This bit is automatically cleared when a short packet is
received.
DMA Request Enable
Value Description
0
Disables the µDMA request for the receive endpoint.
1
Enables the µDMA request for the receive endpoint.
Note:
4
PIDERR
RO
0
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAARX,
DMABRX, or DMACRX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
PID Error
Value Description
0
No error.
1
Indicates a PID error in the received packet of an isochronous
transaction.
This bit is ignored in bulk or interrupt transactions.
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
3
DMAMOD
R/W
0
Description
DMA Request Mode
Value Description
0
An interrupt is generated after every µDMA packet transfer.
1
An interrupt is generated only after the entire μDMA transfer is
complete.
Note:
2
DTWE
RO
0
This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
Data Toggle Write Enable
Value Description
0
The DT bit cannot be written.
1
Enables the current state of the receive endpoint data to be
written (see DT bit).
This bit is automatically cleared once the new value is written.
1
DT
RO
0
Data Toggle
When read, this bit indicates the current state of the receive data toggle.
If DTWE is High, this bit may be written with the required setting of the
data toggle. If DTWE is Low, any value written to this bit is ignored. Care
should be taken when writing to this bit as it should only be changed to
RESET the receive endpoint.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
OTG B / Device Mode
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1)
Base 0x4005.0000
Offset 0x117
Type R/W, reset 0x00
7
Type
Reset
6
5
AUTOCL
ISO
DMAEN
R/W
0
R/W
0
R/W
0
4
DISNYET /
PIDERR
R/W
0
3
2
DMAMOD
R/W
0
1
0
reserved
RO
0
RO
0
RO
0
May 24, 2010
909
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
Description
7
AUTOCL
R/W
0
Auto Clear
Value Description
6
ISO
R/W
0
0
No effect.
1
Enables the RXRDY bit to be automatically cleared when a packet
of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are
unloaded, RXRDY must be cleared manually. Care must be taken
when using µDMA to unload the receive FIFO as data is read
from the receive FIFO in 4 byte chunks regardless of the value
of the MAXLOAD field in the USBRXMAXPn register, see “DMA
Operation” on page 822.
Isochronous Transfers
Value Description
5
DMAEN
R/W
0
0
Enables the receive endpoint for isochronous transfers.
1
Enables the receive endpoint for bulk/interrupt transfers.
DMA Request Enable
Value Description
0
Disables the µDMA request for the receive endpoint.
1
Enables the µDMA request for the receive endpoint.
Note:
4
DISNYET / PIDERR
R/W
0
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAARX,
DMABRX, or DMACRX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
Disable NYET / PID Error
Value Description
0
No effect.
1
For bulk or interrupt transactions: Disables the sending of NYET
handshakes. When this bit is set, all successfully received
packets are acknowledged, including at the point at which the
FIFO becomes full.
For isochronous transactions: Indicates a PID error in the
received packet.
3
DMAMOD
R/W
0
DMA Request Mode
Value Description
0
An interrupt is generated after every µDMA packet transfer.
1
An interrupt is generated only after the entire μDMA transfer is
complete.
Note:
This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
910
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
2:0
reserved
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
911
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 225: USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset
0x118
Register 226: USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset
0x128
Register 227: USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset
0x138
Register 228: USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset
0x148
Register 229: USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset
0x158
Register 230: USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset
0x168
Register 231: USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset
0x178
Register 232: USB Receive Byte Count Endpoint 8 (USBRXCOUNT8), offset
0x188
Register 233: USB Receive Byte Count Endpoint 9 (USBRXCOUNT9), offset
0x198
Register 234: USB Receive Byte Count Endpoint 10 (USBRXCOUNT10), offset
0x1A8
Register 235: USB Receive Byte Count Endpoint 11 (USBRXCOUNT11), offset
0x1B8
Register 236: USB Receive Byte Count Endpoint 12 (USBRXCOUNT12), offset
0x1C8
Register 237: USB Receive Byte Count Endpoint 13 (USBRXCOUNT13), offset
0x1D8
Register 238: USB Receive Byte Count Endpoint 14 (USBRXCOUNT14), offset
0x1E8
Register 239: USB Receive Byte Count Endpoint 15 (USBRXCOUNT15), offset
0x1F8
OTG A /
Host
OTG B /
Note:
The value returned changes as the FIFO is unloaded and is only valid while the RXRDY bit
in the USBRXCSRLn register is set.
USBRXCOUNTn is a 16-bit read-only register that holds the number of data bytes in the packet
currently in line to be read from the receive FIFO. If the packet is transmitted as multiple bulk packets,
the number given is for the combined packet.
Device
912
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB Receive Byte Count Endpoint 1 (USBRXCOUNT1)
Base 0x4005.0000
Offset 0x118
Type RO, reset 0x0000
15
14
13
12
11
10
9
8
7
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
COUNT
Bit/Field
Name
Type
Reset
15:13
reserved
RO
0x0
12:0
COUNT
RO
0x000
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive Packet Count
Indicates the number of bytes in the receive packet.
May 24, 2010
913
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 240: USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1),
offset 0x11A
Register 241: USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2),
offset 0x12A
Register 242: USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3),
offset 0x13A
Register 243: USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4),
offset 0x14A
Register 244: USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5),
offset 0x15A
Register 245: USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6),
offset 0x16A
Register 246: USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7),
offset 0x17A
Register 247: USB Host Transmit Configure Type Endpoint 8 (USBTXTYPE8),
offset 0x18A
Register 248: USB Host Transmit Configure Type Endpoint 9 (USBTXTYPE9),
offset 0x19A
Register 249: USB Host Transmit Configure Type Endpoint 10 (USBTXTYPE10),
offset 0x1AA
Register 250: USB Host Transmit Configure Type Endpoint 11 (USBTXTYPE11),
offset 0x1BA
Register 251: USB Host Transmit Configure Type Endpoint 12 (USBTXTYPE12),
offset 0x1CA
Register 252: USB Host Transmit Configure Type Endpoint 13 (USBTXTYPE13),
offset 0x1DA
Register 253: USB Host Transmit Configure Type Endpoint 14 (USBTXTYPE14),
offset 0x1EA
Register 254: USB Host Transmit Configure Type Endpoint 15 (USBTXTYPE15),
offset 0x1FA
OTG A /
Host
USBTXTYPEn is an 8-bit register that must be written with the endpoint number to be targeted by
the endpoint, the transaction protocol to use for the currently selected transmit endpoint, and its
operating speed.
914
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1)
Base 0x4005.0000
Offset 0x11A
Type R/W, reset 0x00
7
6
5
R/W
0
R/W
0
SPEED
Type
Reset
R/W
0
4
3
2
R/W
0
R/W
0
R/W
0
PROTO
1
0
R/W
0
R/W
0
TEP
Bit/Field
Name
Type
Reset
7:6
SPEED
R/W
0x0
Description
Operating Speed
This bit field specifies the operating speed of the target Device:
Value Description
0x0
Default
The target is assumed to be using the same connection speed
as the USB controller.
5:4
PROTO
R/W
0x0
0x1
Reserved
0x2
Full
0x3
Low
Protocol
Software must configure this bit field to select the required protocol for
the transmit endpoint:
Value Description
3:0
TEP
R/W
0x0
0x0
Control
0x1
Isochronous
0x2
Bulk
0x3
Interrupt
Target Endpoint Number
Software must configure this value to the endpoint number contained
in the transmit endpoint descriptor returned to the USB controller during
Device enumeration.
May 24, 2010
915
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 255: USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1),
offset 0x11B
Register 256: USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2),
offset 0x12B
Register 257: USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3),
offset 0x13B
Register 258: USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4),
offset 0x14B
Register 259: USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5),
offset 0x15B
Register 260: USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6),
offset 0x16B
Register 261: USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7),
offset 0x17B
Register 262: USB Host Transmit Interval Endpoint 8 (USBTXINTERVAL8),
offset 0x18B
Register 263: USB Host Transmit Interval Endpoint 9 (USBTXINTERVAL9),
offset 0x19B
Register 264: USB Host Transmit Interval Endpoint 10 (USBTXINTERVAL10),
offset 0x1AB
Register 265: USB Host Transmit Interval Endpoint 11 (USBTXINTERVAL11),
offset 0x1BB
Register 266: USB Host Transmit Interval Endpoint 12 (USBTXINTERVAL12),
offset 0x1CB
Register 267: USB Host Transmit Interval Endpoint 13 (USBTXINTERVAL13),
offset 0x1DB
Register 268: USB Host Transmit Interval Endpoint 14 (USBTXINTERVAL14),
offset 0x1EB
Register 269: USB Host Transmit Interval Endpoint 15 (USBTXINTERVAL15),
offset 0x1FB
OTG A /
Host
USBTXINTERVALn is an 8-bit register that, for interrupt and isochronous transfers, defines the
polling interval for the currently selected transmit endpoint. For bulk endpoints, this register defines
the number of frames after which the endpoint should time out on receiving a stream of NAK
responses.
The USBTXINTERVALn register value defines a number of frames, as follows:
916
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Transfer Type
Speed
Valid values (m)
Low-Speed or Full-Speed
0x01 – 0xFF
The polling interval is m frames.
Isochronous
Full-Speed
0x01 – 0x10
The polling interval is 2(m-1) frames.
Bulk
Full-Speed
0x02 – 0x10
The NAK Limit is 2(m-1) frames. A value of 0
or 1 disables the NAK timeout function.
Interrupt
Interpretation
USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1)
Base 0x4005.0000
Offset 0x11B
Type R/W, reset 0x00
7
6
5
R/W
0
R/W
0
R/W
0
4
3
2
1
0
R/W
0
R/W
0
R/W
0
TXPOLL / NAKLMT
Type
Reset
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
7:0
TXPOLL / NAKLMT
R/W
0x00
TX Polling / NAK Limit
The polling interval for interrupt/isochronous transfers; the NAK limit for
bulk transfers. See table above for valid entries; other values are
reserved.
May 24, 2010
917
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 270: USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1),
offset 0x11C
Register 271: USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2),
offset 0x12C
Register 272: USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3),
offset 0x13C
Register 273: USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4),
offset 0x14C
Register 274: USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5),
offset 0x15C
Register 275: USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6),
offset 0x16C
Register 276: USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7),
offset 0x17C
Register 277: USB Host Configure Receive Type Endpoint 8 (USBRXTYPE8),
offset 0x18C
Register 278: USB Host Configure Receive Type Endpoint 9 (USBRXTYPE9),
offset 0x19C
Register 279: USB Host Configure Receive Type Endpoint 10 (USBRXTYPE10),
offset 0x1AC
Register 280: USB Host Configure Receive Type Endpoint 11 (USBRXTYPE11),
offset 0x1BC
Register 281: USB Host Configure Receive Type Endpoint 12 (USBRXTYPE12),
offset 0x1CC
Register 282: USB Host Configure Receive Type Endpoint 13 (USBRXTYPE13),
offset 0x1DC
Register 283: USB Host Configure Receive Type Endpoint 14 (USBRXTYPE14),
offset 0x1EC
Register 284: USB Host Configure Receive Type Endpoint 15 (USBRXTYPE15),
offset 0x1FC
OTG A /
Host
USBRXTYPEn is an 8-bit register that must be written with the endpoint number to be targeted by
the endpoint, the transaction protocol to use for the currently selected receive endpoint, and its
operating speed.
918
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1)
Base 0x4005.0000
Offset 0x11C
Type R/W, reset 0x00
7
6
5
R/W
0
R/W
0
SPEED
Type
Reset
R/W
0
4
3
2
R/W
0
R/W
0
R/W
0
PROTO
1
0
R/W
0
R/W
0
TEP
Bit/Field
Name
Type
Reset
7:6
SPEED
R/W
0x0
Description
Operating Speed
This bit field specifies the operating speed of the target Device:
Value Description
0x0
Default
The target is assumed to be using the same connection speed
as the USB controller.
5:4
PROTO
R/W
0x0
0x1
Reserved
0x2
Full
0x3
Low
Protocol
Software must configure this bit field to select the required protocol for
the receive endpoint:
Value Description
3:0
TEP
R/W
0x0
0x0
Control
0x1
Isochronous
0x2
Bulk
0x3
Interrupt
Target Endpoint Number
Software must set this value to the endpoint number contained in the
receive endpoint descriptor returned to the USB controller during Device
enumeration.
May 24, 2010
919
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 285: USB Host Receive Polling Interval Endpoint 1
(USBRXINTERVAL1), offset 0x11D
Register 286: USB Host Receive Polling Interval Endpoint 2
(USBRXINTERVAL2), offset 0x12D
Register 287: USB Host Receive Polling Interval Endpoint 3
(USBRXINTERVAL3), offset 0x13D
Register 288: USB Host Receive Polling Interval Endpoint 4
(USBRXINTERVAL4), offset 0x14D
Register 289: USB Host Receive Polling Interval Endpoint 5
(USBRXINTERVAL5), offset 0x15D
Register 290: USB Host Receive Polling Interval Endpoint 6
(USBRXINTERVAL6), offset 0x16D
Register 291: USB Host Receive Polling Interval Endpoint 7
(USBRXINTERVAL7), offset 0x17D
Register 292: USB Host Receive Polling Interval Endpoint 8
(USBRXINTERVAL8), offset 0x18D
Register 293: USB Host Receive Polling Interval Endpoint 9
(USBRXINTERVAL9), offset 0x19D
Register 294: USB Host Receive Polling Interval Endpoint 10
(USBRXINTERVAL10), offset 0x1AD
Register 295: USB Host Receive Polling Interval Endpoint 11
(USBRXINTERVAL11), offset 0x1BD
Register 296: USB Host Receive Polling Interval Endpoint 12
(USBRXINTERVAL12), offset 0x1CD
Register 297: USB Host Receive Polling Interval Endpoint 13
(USBRXINTERVAL13), offset 0x1DD
Register 298: USB Host Receive Polling Interval Endpoint 14
(USBRXINTERVAL14), offset 0x1ED
Register 299: USB Host Receive Polling Interval Endpoint 15
(USBRXINTERVAL15), offset 0x1FD
OTG A /
Host
USBRXINTERVALn is an 8-bit register that, for interrupt and isochronous transfers, defines the
polling interval for the currently selected receive endpoint. For bulk endpoints, this register defines
the number of frames after which the endpoint should time out on receiving a stream of NAK
responses.
The USBTXINTERVALn register value defines a number of frames, as follows:
Transfer Type
Interrupt
Isochronous
Speed
Valid values (m)
Interpretation
Low-Speed or Full-Speed
0x01 – 0xFF
The polling interval is m frames.
Full-Speed
0x01 – 0x10
The polling interval is 2(m-1) frames.
920
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Transfer Type
Bulk
Speed
Valid values (m)
Full-Speed
0x02 – 0x10
Interpretation
The NAK Limit is 2(m-1) frames. A value of 0
or 1 disables the NAK timeout function.
USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1)
Base 0x4005.0000
Offset 0x11D
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
TXPOLL / NAKLMT
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
7:0
TXPOLL / NAKLMT
R/W
0x00
RX Polling / NAK Limit
The polling interval for interrupt/isochronous transfers; the NAK limit for
bulk transfers. See table above for valid entries; other values are
reserved.
May 24, 2010
921
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 300: USB Request Packet Count in Block Transfer Endpoint 1
(USBRQPKTCOUNT1), offset 0x304
Register 301: USB Request Packet Count in Block Transfer Endpoint 2
(USBRQPKTCOUNT2), offset 0x308
Register 302: USB Request Packet Count in Block Transfer Endpoint 3
(USBRQPKTCOUNT3), offset 0x30C
Register 303: USB Request Packet Count in Block Transfer Endpoint 4
(USBRQPKTCOUNT4), offset 0x310
Register 304: USB Request Packet Count in Block Transfer Endpoint 5
(USBRQPKTCOUNT5), offset 0x314
Register 305: USB Request Packet Count in Block Transfer Endpoint 6
(USBRQPKTCOUNT6), offset 0x318
Register 306: USB Request Packet Count in Block Transfer Endpoint 7
(USBRQPKTCOUNT7), offset 0x31C
Register 307: USB Request Packet Count in Block Transfer Endpoint 8
(USBRQPKTCOUNT8), offset 0x320
Register 308: USB Request Packet Count in Block Transfer Endpoint 9
(USBRQPKTCOUNT9), offset 0x324
Register 309: USB Request Packet Count in Block Transfer Endpoint 10
(USBRQPKTCOUNT10), offset 0x328
Register 310: USB Request Packet Count in Block Transfer Endpoint 11
(USBRQPKTCOUNT11), offset 0x32C
Register 311: USB Request Packet Count in Block Transfer Endpoint 12
(USBRQPKTCOUNT12), offset 0x330
Register 312: USB Request Packet Count in Block Transfer Endpoint 13
(USBRQPKTCOUNT13), offset 0x334
Register 313: USB Request Packet Count in Block Transfer Endpoint 14
(USBRQPKTCOUNT14), offset 0x338
Register 314: USB Request Packet Count in Block Transfer Endpoint 15
(USBRQPKTCOUNT15), offset 0x33C
OTG A /
Host
This 16-bit read/write register is used in Host mode to specify the number of packets that are to be
transferred in a block transfer of one or more bulk packets to receive endpoint n. The USB controller
uses the value recorded in this register to determine the number of requests to issue where the
AUTORQ bit in the USBRXCSRHn register has been set. See “IN Transactions as a Host” on page 818.
Note:
Multiple packets combined into a single bulk packet within the FIFO count as one packet.
922
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1)
Base 0x4005.0000
Offset 0x304
Type R/W, reset 0x0000
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
COUNT
Type
Reset
Bit/Field
Name
Type
Reset
15:0
COUNT
R/W
0x0000
Description
Block Transfer Packet Count
Sets the number of packets of the size defined by the MAXLOAD bit field
that are to be transferred in a block transfer.
Note:
This is only used in Host mode when AUTORQ is set. The bit
has no effect in Device mode or when AUTORQ is not set.
May 24, 2010
923
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 315: USB Receive Double Packet Buffer Disable
(USBRXDPKTBUFDIS), offset 0x340
OTG A /
Host
USBRXDPKTBUFDIS is a 16-bit register that indicates which of the receive endpoints have disabled
the double-packet buffer functionality (see the section called “Double-Packet Buffering” on page 814).
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS)
OTG B /
Base 0x4005.0000
Offset 0x340
Type R/W, reset 0x0000
Device
Type
Reset
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
reserved
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
Bit/Field
Name
Type
Reset
15
EP15
R/W
0
Description
EP15 RX Double-Packet Buffer Disable
Value Description
14
EP14
R/W
0
0
Disables double-packet buffering.
1
Enables double-packet buffering.
EP14 RX Double-Packet Buffer Disable
Same description as EP15.
13
EP13
R/W
0
EP13 RX Double-Packet Buffer Disable
Same description as EP15.
12
EP12
R/W
0
EP12 RX Double-Packet Buffer Disable
Same description as EP15.
11
EP11
R/W
0
EP11 RX Double-Packet Buffer Disable
Same description as EP15.
10
EP10
R/W
0
EP10 RX Double-Packet Buffer Disable
Same description as EP15.
9
EP9
R/W
0
EP9 RX Double-Packet Buffer Disable
Same description as EP15.
8
EP8
R/W
0
EP8 RX Double-Packet Buffer Disable
Same description as EP15.
7
EP7
R/W
0
EP7 RX Double-Packet Buffer Disable
Same description as EP15.
6
EP6
R/W
0
EP6 RX Double-Packet Buffer Disable
Same description as EP15.
5
EP5
R/W
0
EP5 RX Double-Packet Buffer Disable
Same description as EP15.
924
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4
EP4
R/W
0
Description
EP4 RX Double-Packet Buffer Disable
Same description as EP15.
3
EP3
R/W
0
EP3 RX Double-Packet Buffer Disable
Same description as EP15.
2
EP2
R/W
0
EP2 RX Double-Packet Buffer Disable
Same description as EP15.
1
EP1
R/W
0
EP1 RX Double-Packet Buffer Disable
Same description as EP15.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
925
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 316: USB Transmit Double Packet Buffer Disable
(USBTXDPKTBUFDIS), offset 0x342
OTG A /
Host
USBTXDPKTBUFDIS is a 16-bit register that indicates which of the transmit endpoints have disabled
the double-packet buffer functionality (see the section called “Double-Packet Buffering” on page 813).
USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS)
OTG B /
Base 0x4005.0000
Offset 0x342
Type R/W, reset 0x0000
Device
Type
Reset
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
reserved
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
Bit/Field
Name
Type
Reset
15
EP15
R/W
0
Description
EP15 TX Double-Packet Buffer Disable
Value Description
14
EP14
R/W
0
0
Disables double-packet buffering.
1
Enables double-packet buffering.
EP14 TX Double-Packet Buffer Disable
Same description as EP15.
13
EP13
R/W
0
EP13 TX Double-Packet Buffer Disable
Same description as EP15.
12
EP12
R/W
0
EP12 TX Double-Packet Buffer Disable
Same description as EP15.
11
EP11
R/W
0
EP11 TX Double-Packet Buffer Disable
Same description as EP15.
10
EP10
R/W
0
EP10 TX Double-Packet Buffer Disable
Same description as EP15.
9
EP9
R/W
0
EP9 TX Double-Packet Buffer Disable
Same description as EP15.
8
EP8
R/W
0
EP8 TX Double-Packet Buffer Disable
Same description as EP15.
7
EP7
R/W
0
EP7 TX Double-Packet Buffer Disable
Same description as EP15.
6
EP6
R/W
0
EP6 TX Double-Packet Buffer Disable
Same description as EP15.
5
EP5
R/W
0
EP5 TX Double-Packet Buffer Disable
Same description as EP15.
926
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4
EP4
R/W
0
Description
EP4 TX Double-Packet Buffer Disable
Same description as EP15.
3
EP3
R/W
0
EP3 TX Double-Packet Buffer Disable
Same description as EP15.
2
EP2
R/W
0
EP2 TX Double-Packet Buffer Disable
Same description as EP15.
1
EP1
R/W
0
EP1 TX Double-Packet Buffer Disable
Same description as EP15.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
927
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 317: USB External Power Control (USBEPC), offset 0x400
OTG A /
Host
This 32-bit register specifies the function of the two-pin external power interface (USB0EPEN and
USB0PFLT). The assertion of the power fault input may generate an automatic action, as controlled
by the hardware configuration registers. The automatic action is necessary because the fault condition
may require a response faster than one provided by firmware.
OTG B /
USB External Power Control (USBEPC)
Device
Base 0x4005.0000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
EPENDE
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PFLTACT
Bit/Field
Name
Type
Reset
31:10
reserved
RO
0x0000.0
9:8
PFLTACT
R/W
0x0
reserved
R/W
0
PFLTAEN PFLTSEN PFLTEN
RO
0
R/W
0
R/W
0
R/W
0
EPEN
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power Fault Action
This bit field specifies how the USB0EPEN signal is changed when
detecting a USB power fault.
Value Description
0x0
Unchanged
USB0EPEN is controlled by the combination of the EPEN and
EPENDE bits.
0x1
Tristate
USB0EPEN is undriven (tristate).
0x2
Low
USB0EPEN is driven Low.
0x3
High
USB0EPEN is driven High.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
928
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
6
PFLTAEN
R/W
0
Description
Power Fault Action Enable
This bit specifies whether a USB power fault triggers any automatic
corrective action regarding the driven state of the USB0EPEN signal.
Value Description
0
Disabled
USB0EPEN is controlled by the combination of the EPEN and
EPENDE bits.
1
Enabled
The USB0EPEN output is automatically changed to the state
specified by the PFLTACT field.
5
PFLTSEN
R/W
0
Power Fault Sense
This bit specifies the logical sense of the USB0PFLT input signal that
indicates an error condition.
The complementary state is the inactive state.
Value Description
0
Low Fault
If USB0PFLT is driven Low, the power fault is signaled internally
(if enabled by the PFLTEN bit).
1
High Fault
If USB0PFLT is driven High, the power fault is signaled internally
(if enabled by the PFLTEN bit).
4
PFLTEN
R/W
0
Power Fault Input Enable
This bit specifies whether the USB0PFLT input signal is used in internal
logic.
Value Description
0
Not Used
The USB0PFLT signal is ignored.
1
Used
The USB0PFLT signal is used internally.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
929
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
2
EPENDE
R/W
0
Description
EPEN Drive Enable
This bit specifies whether the USB0EPEN signal is driven or undriven
(tristate). When driven, the signal value is specified by the EPEN field.
When not driven, the EPEN field is ignored and the USB0EPEN signal is
placed in a high-impedance state.
Value Description
0
Not Driven
The USB0EPEN signal is high impedance.
1
Driven
The USB0EPEN signal is driven to the logical value specified by
the value of the EPEN field.
The USB0EPEN signal is undriven at reset because the sense of the
external power supply enable is unknown. By adding the high-impedance
state, system designers may bias the power supply enable to the
disabled state using a large resistor (100 kΩ) and later configure and
drive the output signal to enable the power supply.
1:0
EPEN
R/W
0x0
External Power Supply Enable Configuration
This bit field specifies and controls the logical value driven on the
USB0EPEN signal.
Value Description
0x0
Power Enable Active Low
The USB0EPEN signal is driven Low if the EPENDE bit is set.
0x1
Power Enable Active High
The USB0EPEN signal is driven High if the EPENDE bit is set.
0x2
Power Enable High if VBUS Low
The USB0EPEN signal is driven High when the A device is not
recognized.
0x3
Power Enable High if VBUS High
The USB0EPEN signal is driven High when the A device is
recognized.
930
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 318: USB External Power Control Raw Interrupt Status (USBEPCRIS),
offset 0x404
OTG A /
This 32-bit register specifies the unmasked interrupt status of the two-pin external power interface.
USB External Power Control Raw Interrupt Status (USBEPCRIS)
Host
Base 0x4005.0000
Offset 0x404
Type RO, reset 0x0000.0000
OTG B /
31
30
29
28
27
26
25
Device
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PF
RO
0
RO
0
RO
0
0
PF
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Power Fault Interrupt Status
Value Description
1
A Power Fault status has been detected.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the PF bit in the USBEPCISC register.
May 24, 2010
931
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 319: USB External Power Control Interrupt Mask (USBEPCIM), offset
0x408
OTG A /
This 32-bit register specifies the interrupt mask of the two-pin external power interface.
USB External Power Control Interrupt Mask (USBEPCIM)
Host
Base 0x4005.0000
Offset 0x408
Type R/W, reset 0x0000.0000
OTG B /
31
30
29
28
27
26
25
Device
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PF
R/W
0
RO
0
RO
0
0
PF
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Power Fault Interrupt Mask
Value Description
1
The raw interrupt signal from a detected power fault is sent to
the interrupt controller.
0
A detected power fault does not affect the interrupt status.
932
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 320: USB External Power Control Interrupt Status and Clear
(USBEPCISC), offset 0x40C
OTG A /
Host
This 32-bit register specifies the masked interrupt status of the two-pin external power interface. It
also provides a method to clear the interrupt state.
USB External Power Control Interrupt Status and Clear (USBEPCISC)
OTG B /
Base 0x4005.0000
Offset 0x40C
Type R/W, reset 0x0000.0000
Device
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PF
R/W1C
0
RO
0
RO
0
0
PF
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Power Fault Interrupt Status and Clear
Value Description
1
The PF bits in the USBEPCRIS and USBEPCIM registers are
set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the PF bit
in the USBEPCRIS register.
May 24, 2010
933
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 321: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset
0x410
OTG A /
Host
The USBDRRIS 32-bit register is the raw interrupt status register. On a read, this register gives the
current raw status value of the corresponding interrupt prior to masking. A write has no effect.
USB Device RESUME Raw Interrupt Status (USBDRRIS)
OTG B /
Base 0x4005.0000
Offset 0x410
Type RO, reset 0x0000.0000
Device
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
RESUME
RO
0
RO
0
RO
0
0
RESUME
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RESUME Interrupt Status
Value Description
1
A RESUME status has been detected.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the RESUME bit in the USBDRISC
register.
934
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 322: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414
OTG A /
Host
The USBDRIM 32-bit register is the masked interrupt status register. On a read, this register gives
the current masked status value of the corresponding interrupt. A write has no effect.
USB Device RESUME Interrupt Mask (USBDRIM)
OTG B /
Base 0x4005.0000
Offset 0x414
Type R/W, reset 0x0000.0000
Device
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RESUME
R/W
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RESUME
R/W
0
RESUME Interrupt Mask
Value Description
1
The raw interrupt signal from a detected RESUME is sent to
the interrupt controller. This bit should only be set when a
SUSPEND has been detected (the SUSPEND bit in the USBIS
register is set).
0
A detected RESUME does not affect the interrupt status.
May 24, 2010
935
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 323: USB Device RESUME Interrupt Status and Clear (USBDRISC),
offset 0x418
OTG A /
Host
The USBDRISC 32-bit register is the interrupt clear register. On a write of 1, the corresponding
interrupt is cleared. A write of 0 has no effect.
USB Device RESUME Interrupt Status and Clear (USBDRISC)
OTG B /
Base 0x4005.0000
Offset 0x418
Type W1C, reset 0x0000.0000
Device
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
RESUME
R/W1C
0
RO
0
RO
0
0
RESUME
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RESUME Interrupt Status and Clear
Value Description
1
The RESUME bits in the USBDRRIS and USBDRCIM registers
are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the RESUME
bit in the USBDRCRIS register.
936
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 324: USB General-Purpose Control and Status (USBGPCS), offset
0x41C
OTG A /
USBGPCS provides the state of the internal ID signal.
Note:
Host
OTG B /
Device
When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they
are dedicated pins for the USB controller and directly connect to the USB connector's VBUS
and ID signals. If the USB controller is used as either a dedicated Host or Device, the
DEVMODOTG and DEVMOD bits in the USB General-Purpose Control and Status
(USBGPCS) register can be used to connect the USB0VBUS and USB0ID inputs to fixed
levels internally, freeing the PB0 and PB1 pins for GPIO use. For proper self-powered Device
operation, the VBUS value must still be monitored to assure that if the Host removes VBUS,
the self-powered Device disables the D+/D- pull-up resistors. This function can be
accomplished by connecting a standard GPIO to VBUS.
USB General-Purpose Control and Status (USBGPCS)
Base 0x4005.0000
Offset 0x41C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
DEVMODOTG
DEVMOD
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
DEVMODOTG
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable Device Mode
This bit enables the DEVMOD bit to control the state of the internal ID
signal in OTG mode.
Value Description
0
DEVMOD
R/W
0
0
The mode is specified by the state of the internal ID signal.
1
This bit enables the DEVMOD bit to control the internal ID signal.
Device Mode
This bit specifies the state of the internal ID signal in Host mode and in
OTG mode when the DEVMODOTG bit is set.
In Device mode this bit is ignored (assumed set).
Value Description
0
Host mode
1
Device mode
May 24, 2010
937
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 325: USB VBUS Droop Control (USBVDC), offset 0x430
OTG A /
Host
This 32-bit register enables a controlled masking of VBUS to compensate for any in-rush current
by a Device that is connected to the Host controller. The in-rush current can cause VBUS to droop,
causing the USB controller's behavior to be unexpected. The USB Host controller allows VBUS to
fall lower than the VBUS Valid level (4.5 V) but not below AValid (2.0 V) for 65 microseconds without
signaling a VBUSERR interrupt in the controller. Without this, any glitch on VBUS would force the
USB Host controller to remove power from VBUS and then re-enumerate the Device.
USB VBUS Droop Control (USBVDC)
Base 0x4005.0000
Offset 0x430
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
VBDEN
R/W
0
RO
0
VBDEN
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VBUS Droop Enable
Value Description
0
No effect.
1
Any changes from VBUSVALID are masked when VBUS goes
below 4.5 V but not lower than 2.0 V for 65 microseconds.
During this time, the VBUS state indicates VBUSVALID.
938
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 326: USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS),
offset 0x434
OTG A /
Host
This 32-bit register specifies the unmasked interrupt status of the VBUS droop limit of 65
microseconds.
USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS)
Base 0x4005.0000
Offset 0x434
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
VD
RO
0
RO
0
0
VD
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VBUS Droop Raw Interrupt Status
Value Description
1
A VBUS droop lasting for 65 microseconds has been detected.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the VD bit in the USBVDCISC register.
May 24, 2010
939
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 327: USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset
0x438
OTG A /
This 32-bit register specifies the interrupt mask of the VBUS droop.
USB VBUS Droop Control Interrupt Mask (USBVDCIM)
Host
Base 0x4005.0000
Offset 0x438
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
VD
R/W
0
RO
0
0
VD
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VBUS Droop Interrupt Mask
Value Description
1
The raw interrupt signal from a detected VBUS droop is sent to
the interrupt controller.
0
A detected VBUS droop does not affect the interrupt status.
940
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 328: USB VBUS Droop Control Interrupt Status and Clear
(USBVDCISC), offset 0x43C
OTG A /
Host
This 32-bit register specifies the masked interrupt status of the VBUS droop and provides a method
to clear the interrupt state.
USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC)
Base 0x4005.0000
Offset 0x43C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
VD
R/W1C
0
RO
0
0
VD
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VBUS Droop Interrupt Status and Clear
Value Description
1
The VD bits in the USBVDCRIS and USBVDCIM registers are
set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the VD bit
in the USBVDCRIS register.
May 24, 2010
941
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 329: USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset
0x444
This 32-bit register specifies whether the unmasked interrupt status of the ID value is valid.
OTG
USB ID Valid Detect Raw Interrupt Status (USBIDVRIS)
Base 0x4005.0000
Offset 0x444
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ID
RO
0
RO
0
0
ID
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ID Valid Detect Raw Interrupt Status
Value Description
1
A valid ID has been detected.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the ID bit in the USBIDVISC register.
942
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 330: USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448
This 32-bit register specifies the interrupt mask of the ID valid detection.
OTG
USB ID Valid Detect Interrupt Mask (USBIDVIM)
Base 0x4005.0000
Offset 0x448
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ID
R/W
0
RO
0
ID
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ID Valid Detect Interrupt Mask
Value Description
1
The raw interrupt signal from a detected ID valid is sent to the
interrupt controller.
0
A detected ID valid does not affect the interrupt status.
May 24, 2010
943
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Register 331: USB ID Valid Detect Interrupt Status and Clear (USBIDVISC),
offset 0x44C
This 32-bit register specifies the masked interrupt status of the ID valid detect. It also provides a
method to clear the interrupt state.
OTG
USB ID Valid Detect Interrupt Status and Clear (USBIDVISC)
Base 0x4005.0000
Offset 0x44C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ID
R/W1C
0
RO
0
0
ID
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ID Valid Detect Interrupt Status and Clear
Value Description
1
The ID bits in the USBIDVRIS and USBIDVIM registers are
set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the ID bit
in the USBIDVRIS register.
944
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 332: USB DMA Select (USBDMASEL), offset 0x450
OTG A /
Host
OTG B /
This 32-bit register specifies which endpoints are mapped to the 6 allocated µDMA channels, see
Table 8-1 on page 242 for more information on channel assignments.
USB DMA Select (USBDMASEL)
Base 0x4005.0000
Offset 0x450
Type R/W, reset 0x0033.2211
Device
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
R/W
0
R/W
0
27
26
25
24
23
22
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
12
11
10
9
8
7
6
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
R/W
1
20
19
18
R/W
1
R/W
1
R/W
0
R/W
0
R/W
1
R/W
1
5
4
3
2
1
0
R/W
1
R/W
0
R/W
0
DMACTX
DMABTX
Type
Reset
21
DMABRX
R/W
1
16
DMACRX
DMAATX
R/W
0
17
DMAARX
R/W
0
R/W
1
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:20
DMACTX
R/W
0x3
DMA C TX Select
Specifies the TX mapping of the third USB endpoint on µDMA channel
5 (primary assignment).
Value Description
0x0
reserved
0x1
Endpoint 1 TX
0x2
Endpoint 2 TX
0x3
Endpoint 3 TX
0x4
Endpoint 4 TX
0x5
Endpoint 5 TX
0x6
Endpoint 6 TX
0x7
Endpoint 7 TX
0x8
Endpoint 8 TX
0x9
Endpoint 9 TX
0xA
Endpoint 10 TX
0xB
Endpoint 11 TX
0xC
Endpoint 12 TX
0xD
Endpoint 13 TX
0xE
Endpoint 14 TX
0xF
Endpoint 15 TX
May 24, 2010
945
Texas Instruments-Advance Information
Universal Serial Bus (USB) Controller
Bit/Field
Name
Type
Reset
19:16
DMACRX
R/W
0x3
Description
DMA C RX Select
Specifies the RX and TX mapping of the third USB endpoint on µDMA
channel 4 (primary assignment).
Value Description
15:12
DMABTX
R/W
0x2
0x0
reserved
0x1
Endpoint 1 RX
0x2
Endpoint 2 RX
0x3
Endpoint 3 RX
0x4
Endpoint 4 RX
0x5
Endpoint 5 RX
0x6
Endpoint 6 RX
0x7
Endpoint 7 RX
0x8
Endpoint 8 RX
0x9
Endpoint 9 RX
0xA
Endpoint 10 RX
0xB
Endpoint 11 RX
0xC
Endpoint 12 RX
0xD
Endpoint 13 RX
0xE
Endpoint 14 RX
0xF
Endpoint 15 RX
DMA B TX Select
Specifies the TX mapping of the second USB endpoint on µDMA channel
3 (primary assignment).
Same bit definitions as the DMACTX field.
11:8
DMABRX
R/W
0x2
DMA B RX Select
Specifies the RX mapping of the second USB endpoint on µDMA channel
2 (primary assignment).
Same bit definitions as the DMACRX field.
7:4
DMAATX
R/W
0x1
DMA A TX Select
Specifies the TX mapping of the first USB endpoint on µDMA channel
1 (primary assignment).
Same bit definitions as the DMACTX field.
3:0
DMAARX
R/W
0x1
DMA A RX Select
Specifies the RX mapping of the first USB endpoint on µDMA channel
0 (primary assignment).
Same bit definitions as the DMACRX field.
946
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
20
Analog Comparators
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result.
Note:
Not all comparators have the option to drive an output pin.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board. In addition, the comparator can signal the application via interrupts or
trigger the start of a sample sequence in the ADC. The interrupt generation and ADC triggering logic
is separate and independent. This flexibility means, for example, that an interrupt can be generated
on a rising edge and the ADC triggered on a falling edge.
®
The Stellaris LM3S5B91 microcontroller provides three independent integrated analog comparators
with the following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
May 24, 2010
947
Texas Instruments-Advance Information
Analog Comparators
20.1
Block Diagram
Figure 20-1. Analog Comparator Module Block Diagram
C2-
-ve input
C2+
+ve input
Comparator 2
output
+ve input (alternate)
trigger
ACCTL2
C2o
trigger
ACSTAT2
interrupt
reference input
C1-
-ve input
C1+
+ve input
Comparator 1
output
C1o
+ve input (alternate)
trigger
ACCTL1
trigger
ACSTAT1
interrupt
reference input
C0-
-ve input
C0+
+ve input
Comparator 0
output
+ve input (alternate)
trigger
ACCTL0
C0o
trigger
ACSTAT0
interrupt
reference input
Interrupt Control
Voltage
Ref
ACRIS
internal
bus
ACREFCTL
ACMIS
ACINTEN
interrupt
20.2
Signal Description
Table 20-1 on page 948 and Table 20-2 on page 949 list the external signals of the Analog Comparators
and describe the function of each. The Analog Comparator output signals are alternate functions
for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled
"Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the Analog Comparator signals.
The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 323) should be
set to choose the Analog Comparator function. The number in parentheses is the encoding that
must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 341)
to assign the Analog Comparator signal to the specified GPIO port pin. The positive and negative
input signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register.
For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 298.
Table 20-1. Signals for Analog Comparators (100LQFP)
Pin Name
C0+
Pin Number Pin Mux / Pin
Assignment
90
PB6
a
Pin Type
Buffer Type
I
Analog
Description
Analog comparator 0 positive input.
948
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 20-1. Signals for Analog Comparators (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
C0-
92
PB4
I
Analog
Analog comparator 0 negative input.
C0o
24
58
90
91
100
PC5 (3)
PF4 (2)
PB6 (3)
PB5 (1)
PD7 (2)
O
TTL
C1+
24
PC5
I
Analog
Analog comparator 1 positive input.
C1-
91
PB5
I
Analog
Analog comparator 1 negative input.
C1o
2
22
24
46
84
PE6 (2)
PC7 (7)
PC5 (2)
PF5 (2)
PH2 (2)
O
TTL
C2+
23
PC6
I
Analog
Analog comparator 2 positive input.
C2-
22
PC7
I
Analog
Analog comparator 2 negative input.
C2o
1
23
43
PE7 (2)
PC6 (3)
PF6 (2)
O
TTL
Analog comparator 0 output.
Analog comparator 1 output.
Analog comparator 2 output.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 20-2. Signals for Analog Comparators (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
A7
C0+
PB6
a
Pin Type
Buffer Type
Description
I
Analog
Analog comparator 0 positive input.
Analog comparator 0 negative input.
C0-
A6
PB4
I
Analog
C0o
M1
L9
A7
B7
A2
PC5 (3)
PF4 (2)
PB6 (3)
PB5 (1)
PD7 (2)
O
TTL
C1+
M1
PC5
I
Analog
Analog comparator 1 positive input.
C1-
B7
PB5
I
Analog
Analog comparator 1 negative input.
C1o
A1
L2
M1
L8
D11
PE6 (2)
PC7 (7)
PC5 (2)
PF5 (2)
PH2 (2)
O
TTL
C2+
M2
PC6
I
Analog
Analog comparator 2 positive input.
C2-
L2
PC7
I
Analog
Analog comparator 2 negative input.
C2o
B1
M2
M8
PE7 (2)
PC6 (3)
PF6 (2)
O
TTL
Analog comparator 0 output.
Analog comparator 1 output.
Analog comparator 2 output.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
20.3
Functional Description
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
May 24, 2010
949
Texas Instruments-Advance Information
Analog Comparators
VIN- < VIN+, VOUT = 1
VIN- > VIN+, VOUT = 0
As shown in Figure 20-2 on page 950, the input source for VIN- is an external input, Cn-. In addition
to an external input, Cn+, input sources for VIN+ can be the C0+ or an internal reference, VIREF.
Figure 20-2. Structure of Comparator Unit
- ve input
+ ve input (alternate)
reference input
0
output
CINV
1
IntGen
2
TrigGen
internal
bus
ACCTL
ACSTAT
trigger
interrupt
+ ve input
A comparator is configured through two status/control registers, Analog Comparator Control
(ACCTL) and Analog Comparator Status (ACSTAT). The internal reference is configured through
one control register, Analog Comparator Reference Voltage Control (ACREFCTL). Interrupt
status and control are configured through three registers, Analog Comparator Masked Interrupt
Status (ACMIS), Analog Comparator Raw Interrupt Status (ACRIS), and Analog Comparator
Interrupt Enable (ACINTEN).
Typically, the comparator output is used internally to generate an interrupt as controlled by the ISEN
bit in the ACCTL register. The output may also be used to drive an external pin, Co or generate an
analog-to-digital converter (ADC) trigger.
Important: The ASRCP bits in the ACCTL register must be set before using the analog comparators.
20.3.1
Internal Reference Programming
The structure of the internal reference is shown in Figure 20-3 on page 951. The internal reference
is controlled by a single configuration register (ACREFCTL). Table 20-3 on page 951 shows the
programming options to develop specific internal reference values, to compare an external voltage
against a particular voltage generated internally (VIREF).
950
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Figure 20-3. Comparator Internal Reference Structure
8R
VDDA
8R
R
R
R
•••
EN
15
14
•••
1
0
Decoder
VREF
internal
reference
VIREF
RNG
Table 20-3. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register
EN Bit
Value
Output Reference Voltage Based on VREF Field Value
RNG Bit Value
EN=0
RNG=X
0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0 for the
least noisy ground reference.
EN=1
RNG=0
Total resistance in ladder is 31 R.
RVREF
RT
RVREF
VIREF = VDDA × RVREF
RT
+ 8)
VIREF = VDDA × (VREF
VIREF = VDDA × RT
31 + 8)
(VREF
VIREF = VDDA × (VREF + 8)
RVREF
31 × VREF
V
DDA
0DDA
.85×
.106
IREF =
VIREF
= V
V
×+R0VREF
RT 31
IREF = VDDA ×
VIREF
V
= 0.85 +R0VREF
R.T 106 × VREF
IREF =
DDA
V
V
×+R0VREF
V
IREF
=
0
.
85
(
)
VREF
VIREF = VDDA × VREF
R.T 106+ ×8VREF
VIREF = VDDA × R
R
T
IREF = VDDA × (VREF
VIREF
31 + 8)
V
= VDDAreference
× RVREF
RTin 31
The
range
this mode is 0.85-2.448 V.
IREF of=internal
DDA × VREF
V
V
VIREF = VDDA × (VREF
+ 8)
R
T
Total
resistance
in
ladder
is
23
R.
VIREF = V
0DDA
.85×+VREF
023
.106 × VREF
31 × VREF
VIREF = V
0DDA
.85×+VREF
0.106
23
VREF
R
× × VREF
V
IREF = V
0DDA
.143
IREF =
V
23
VIREF
= V
0DDA
.85×+R0VREF
.T 106 × VREF
IREF =
VIREF
× ×RVREF
V
= V
0DDA
.143
RVREF
T
R
V
IREF = 0.143 VREF
×VREF
IREF = VDDA ×
V
VIREF = VDDA × VREF
RT
VIREF = VDDA × 23
23
VREF
× × VREF
VIREF = V
0DDA
.143
VIREF = 0.143 × 23
VREF
VIREF = VDDA ×
RNG=1
VIREF = 0.143 × VREF
The range of internal reference for this mode is 0-2.152 V.
May 24, 2010
951
Texas Instruments-Advance Information
Analog Comparators
20.4
Initialization and Configuration
The following example shows how to configure an analog comparator to read back its output value
from an internal register.
1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register
in the System Control module (see page 179).
2. In the GPIO module, enable the GPIO port/pin associated with the input signals as GPIO inputs.
To determine which GPIO to configure, see Table 24-4 on page 1088.
3. Configure the PMCn fields in the GPIOPCTL register to assign the analog comparator output
signals to the appropriate pins (see page 341 and Table 24-5 on page 1097).
4. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the
value 0x0000.030C.
5. Configure the comparator to use the internal voltage reference and to not invert the output by
writing the ACCTLn register with the value of 0x0000.040C.
6. Delay for 10 µs.
7. Read the comparator output value by reading the ACSTATn register’s OVAL value.
Change the level of the comparator negative input signal C- to see the OVAL value change.
20.5
Register Map
Table 20-4 on page 952 lists the comparator registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Analog Comparator base address of 0x4003.C000. Note
that the analog comparator clock must be enabled before the registers can be programmed (see
page 179).
Table 20-4. Analog Comparators Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
ACMIS
R/W1C
0x0000.0000
Analog Comparator Masked Interrupt Status
954
0x004
ACRIS
RO
0x0000.0000
Analog Comparator Raw Interrupt Status
955
0x008
ACINTEN
R/W
0x0000.0000
Analog Comparator Interrupt Enable
956
0x010
ACREFCTL
R/W
0x0000.0000
Analog Comparator Reference Voltage Control
957
0x020
ACSTAT0
RO
0x0000.0000
Analog Comparator Status 0
958
0x024
ACCTL0
R/W
0x0000.0000
Analog Comparator Control 0
959
0x040
ACSTAT1
RO
0x0000.0000
Analog Comparator Status 1
958
0x044
ACCTL1
R/W
0x0000.0000
Analog Comparator Control 1
959
0x060
ACSTAT2
RO
0x0000.0000
Analog Comparator Status 2
958
0x064
ACCTL2
R/W
0x0000.0000
Analog Comparator Control 2
959
952
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
20.6
Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
May 24, 2010
953
Texas Instruments-Advance Information
Analog Comparators
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
This register provides a summary of the interrupt status (masked) of the comparators.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x000
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
IN2
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator 2 Masked Interrupt Status
Value Description
1
The IN2 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the IN2 bit
in the ACRIS register.
1
IN1
R/W1C
0
Comparator 1 Masked Interrupt Status
Value Description
1
The IN1 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the IN1 bit
in the ACRIS register.
0
IN0
R/W1C
0
Comparator 0 Masked Interrupt Status
Value Description
1
The IN0 bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the IN0 bit
in the ACRIS register.
954
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
This register provides a summary of the interrupt status (raw) of the comparators. The bits in this
register must be enabled to generate interrupts using the ACINTEN register.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
IN2
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator 2 Interrupt Status
Value Description
1
Comparator 2 has generated an interrupt for an event as
configured by the ISEN bit in the ACCTL2 register.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the IN2 bit in the ACMIS register.
1
IN1
RO
0
Comparator 1 Interrupt Status
Value Description
1
Comparator 1 has generated an interruptfor an event as
configured by the ISEN bit in the ACCTL1 register.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the IN1 bit in the ACMIS register.
0
IN0
RO
0
Comparator 0 Interrupt Status
Value Description
1
Comparator 0 has generated an interrupt for an event as
configured by the ISEN bit in the ACCTL0 register.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the IN0 bit in the ACMIS register.
May 24, 2010
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Texas Instruments-Advance Information
Analog Comparators
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008
This register provides the interrupt enable for the comparators.
Analog Comparator Interrupt Enable (ACINTEN)
Base 0x4003.C000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
IN2
R/W
0
Comparator 2 Interrupt Enable
Value Description
1
IN1
R/W
0
1
The raw interrupt signal comparator 2 is sent to the interrupt
controller.
0
A comparator 2 interrupt does not affect the interrupt status.
Comparator 1 Interrupt Enable
Value Description
0
IN0
R/W
0
1
The raw interrupt signal comparator 1 is sent to the interrupt
controller.
0
A comparator 1 interrupt does not affect the interrupt status.
Comparator 0 Interrupt Enable
Value Description
1
The raw interrupt signal comparator 0 is sent to the interrupt
controller.
0
A comparator 0 interrupt does not affect the interrupt status.
956
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x010
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
9
8
EN
RNG
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:10
reserved
RO
0x0000.0
9
EN
R/W
0
reserved
RO
0
RO
0
RO
0
VREF
RO
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Resistor Ladder Enable
Value Description
0
The resistor ladder is unpowered.
1
Powers on the resistor ladder. The resistor ladder is connected
to VDDA.
This bit is cleared at reset so that the internal reference consumes the
least amount of power if it is not used.
8
RNG
R/W
0
Resistor Ladder Range
Value Description
0
The resistor ladder has a total resistance of 31 R.
1
The resistor ladder has a total resistance of 23 R.
7:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
VREF
R/W
0x0
Resistor Ladder Voltage Ref
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
20-3 on page 951 for some output reference voltage examples.
May 24, 2010
957
Texas Instruments-Advance Information
Analog Comparators
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060
These registers specify the current output value of the comparator.
Analog Comparator Status 0 (ACSTAT0)
Base 0x4003.C000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
OVAL
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
OVAL
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator Output Value
Value Description
0
VIN- > VIN+
1
VIN- < VIN+
VIN - is the voltage on the Cn- pin. VIN+ is the voltage on the Cn+ pin,
the C0+ pin, or the internal voltage reference (VIREF) as defined by the
ASRCP bit in the ACCTL register.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
958
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064
These registers configure the comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
reserved
TSLVAL
CINV
reserved
RO
0
R/W
0
R/W
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
TOEN
RO
0
RO
0
ASRCP
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11
TOEN
R/W
0
TSEN
R/W
0
ISLVAL
R/W
0
R/W
0
ISEN
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Trigger Output Enable
Value Description
10:9
ASRCP
R/W
0x0
0
ADC events are suppressed and not sent to the ADC.
1
ADC events are sent to the ADC.
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Value Description
0x0
Pin value of Cn+
0x1
Pin value of C0+
0x2
Internal voltage reference (VIREF)
0x3
Reserved
8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
TSLVAL
R/W
0
Trigger Sense Level Value
Value Description
0
An ADC event is generated if the comparator output is Low.
1
An ADC event is generated if the comparator output is High.
May 24, 2010
959
Texas Instruments-Advance Information
Analog Comparators
Bit/Field
Name
Type
Reset
6:5
TSEN
R/W
0x0
Description
Trigger Sense
The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:
Value Description
4
ISLVAL
R/W
0
0x0
Level sense, see TSLVAL
0x1
Falling edge
0x2
Rising edge
0x3
Either edge
Interrupt Sense Level Value
Value Description
3:2
ISEN
R/W
0x0
0
An interrupt is generated if the comparator output is Low.
1
An interrupt is generated if the comparator output is High.
Interrupt Sense
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
Value Description
1
CINV
R/W
0
0x0
Level sense, see ISLVAL
0x1
Falling edge
0x2
Rising edge
0x3
Either edge
Comparator Output Invert
Value Description
0
reserved
RO
0
0
The output of the comparator is unchanged.
1
The output of the comparator is inverted prior to being processed
by hardware.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
960
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
21
Pulse Width Modulator (PWM)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
®
The Stellaris PWM module consists of four PWM generator blocks and a control block. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that share the same timer and frequency
and can either be programmed with independent actions or as a single pair of complementary signals
with dead-band delays inserted. The output signals, pwmA' and pwmB', of the PWM generation
blocks are managed by the output control block before being passed to the device pins as PWM0
and PWM1 or PWM2 and PWM3, and so on.
®
The Stellaris PWM module provides a great deal of flexibility and can generate simple PWM signals,
such as those required by a simple charge pump as well as paired PWM signals with dead-band
delays, such as those required by a half-H bridge driver. Three generator blocks can also generate
the full six channels of gate controls required by a 3-phase inverter bridge.
The Stellaris LM3S5B91 PWM module consists of four PWM generator blocks and a control block.
Each PWM generator block has the following features:
■ Four fault-condition handling input to quickly provide low-latency shutdown and prevent damage
to the motor being controlled
■ One 16-bit counter
– Runs in Down or Up/Down mode
– Output frequency controlled by a 16-bit load value
– Load value updates can be synchronized
– Produces output signals at zero and load value
■ Two PWM comparators
– Comparator value updates can be synchronized
– Produces output signals on match
■ PWM signal generator
– Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
– Produces two independent PWM signals
■ Dead-band generator
– Produces two PWM signals with programmable dead-band delays suitable for driving a half-H
bridge
– Can be bypassed, leaving input PWM signals unmodified
May 24, 2010
961
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
■ Can initiate an ADC sample sequence
The control block determines the polarity of the PWM signals and which signals are passed through
to the pins. The output of the PWM generation blocks are managed by the output control block
before being passed to the device pins. The PWM control block has the following options:
■ PWM output enable of each PWM signal
■ Optional output inversion of each PWM signal (polarity control)
■ Optional fault handling for each PWM signal
■ Synchronization of timers in the PWM generator blocks
■ Synchronization of timer/comparator updates across the PWM generator blocks
■ Synchronization of PWM output enables across the PWM generator blocks
■ Interrupt status summary of the PWM generator blocks
■ Extended fault capabilities with multiple fault signals, programmable polarities, and filtering
■ PWM generators can be operated independently or synchronized with other generators
21.1
Block Diagram
®
Figure 21-1 on page 963 provides the Stellaris PWM module unit diagram and Figure 21-2 on page
®
963 provides a more detailed diagram of a Stellaris PWM generator. The LM3S5B91 controller
contains four generator blocks (PWM0, PWM1, PWM2, and PWM3) and generates eight independent
PWM signals or four paired PWM signals with dead-band delays inserted.
962
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Figure 21-1. PWM Unit Diagram
PWM Clock
pwm0A’
Triggers / Faults
System Clock
PWM
Generator 0
Control and
Status
PWMCTL
PWMSYNC
PWMSTATUS
PWM 0
pwm0B’
PWM 1
pwm0fault
pwm1A’
PWM
Generator 1
PWM 2
pwm1B’
PWM
PWM 3
pwm1fault
Output
Interrupt
pwm2A’
Interrupts
PWMINTEN
PWMRIS
PWMISC
PWM
Generator 2
Output
PWM
Generator 3
pwm2B’
Control
PWM 4
Logic
PWM 5
pwm2fault
Triggers
pwm3A’
PWMENABLE
PWMINVERT
PWMFAULT
PWMFAULTVAL
PWMENUPD
PWM 6
pwm3B’
PWM 7
pwm3fault
Figure 21-2. PWM Module Block Diagram
PWM Generator Block
Interrupts /
Triggers
Control
PWMnLOAD
PWMnCOUNT
PWMnFLTSRC0
PWMnFLTSRC1
PWMnMINFLTPER
PWMnFLTSEN
PWMnFLTSTAT0
PWMnFLTSTAT1
PWMnINTEN
PWMnRIS
PWMnISC
PWMnCTL
Timer
Fault
Condition
Interrupt and
Trigger
Generator
load
dir
pwmfault
Signal
Generator
pwmA
pwmB
PWM Clock
21.2
Fault(s)
zero
Comparators
PWMnCMPA
PWMnCMPB
Digital Trigger(s)
cmpA
cmpB
PWMnGENA
PWMnGENB
Dead-Band
Generator
PWMnDBCTL
PWMnDBRISE
PWMnDBFALL
pwmA’
pwmB’
Signal Description
Table 21-1 on page 964 and Table 21-2 on page 965 list the external signals of the PWM module and
describe the function of each. The PWM controller signals are alternate functions for some GPIO
May 24, 2010
963
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin
Assignment" lists the possible GPIO pin placements for these PWM signals. The AFSEL bit in the
GPIO Alternate Function Select (GPIOAFSEL) register (page 323) should be set to choose the
PWM function. The number in parentheses is the encoding that must be programmed into the PMCn
field in the GPIO Port Control (GPIOPCTL) register (page 341) to assign the PWM signal to the
specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose
Input/Outputs (GPIOs)” on page 298.
Table 21-1. Signals for PWM (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
Fault0
6
16
17
39
58
65
75
83
99
PE4 (4)
PG3 (8)
PG2 (4)
PJ2 (10)
PF4 (4)
PB3 (2)
PE1 (3)
PH3 (2)
PD6 (1)
I
TTL
PWM Fault 0.
Fault1
37
40
41
42
90
PG6 (8)
PG5 (5)
PG4 (4)
PF7 (9)
PB6 (4)
I
TTL
PWM Fault 1.
Fault2
16
24
63
PG3 (4)
PC5 (4)
PH5 (10)
I
TTL
PWM Fault 2.
Fault3
65
84
PB3 (4)
PH2 (4)
I
TTL
PWM Fault 3.
PWM0
10
14
17
19
34
47
PD0 (1)
PJ0 (10)
PG2 (1)
PG0 (2)
PA6 (4)
PF0 (3)
O
TTL
PWM 0. This signal is controlled by PWM Generator
0.
PWM1
11
16
18
35
61
87
PD1 (1)
PG3 (1)
PG1 (2)
PA7 (4)
PF1 (3)
PJ1 (10)
O
TTL
PWM 1. This signal is controlled by PWM Generator
0.
PWM2
12
60
66
86
PD2 (3)
PF2 (4)
PB0 (2)
PH0 (2)
O
TTL
PWM 2. This signal is controlled by PWM Generator
1.
PWM3
13
59
67
85
PD3 (3)
PF3 (4)
PB1 (2)
PH1 (2)
O
TTL
PWM 3. This signal is controlled by PWM Generator
1.
964
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 21-1. Signals for PWM (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PWM4
2
19
28
34
60
62
74
86
PE6 (1)
PG0 (4)
PA2 (4)
PA6 (5)
PF2 (2)
PH6 (10)
PE0 (1)
PH0 (9)
O
TTL
PWM 4. This signal is controlled by PWM Generator
2.
PWM5
1
15
18
29
35
59
75
85
PE7 (1)
PH7 (10)
PG1 (4)
PA3 (4)
PA7 (5)
PF3 (2)
PE1 (1)
PH1 (9)
O
TTL
PWM 5. This signal is controlled by PWM Generator
2.
PWM6
25
30
37
41
PC4 (4)
PA4 (4)
PG6 (4)
PG4 (9)
O
TTL
PWM 6. This signal is controlled by PWM Generator
3.
PWM7
23
31
36
40
PC6 (4)
PA5 (4)
PG7 (4)
PG5 (8)
O
TTL
PWM 7. This signal is controlled by PWM Generator
3.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 21-2. Signals for PWM (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
Fault0
B2
J2
J1
K6
L9
E11
A12
D10
A3
PE4 (4)
PG3 (8)
PG2 (4)
PJ2 (10)
PF4 (4)
PB3 (2)
PE1 (3)
PH3 (2)
PD6 (1)
I
TTL
PWM Fault 0.
Fault1
L7
M7
K3
K4
A7
PG6 (8)
PG5 (5)
PG4 (4)
PF7 (9)
PB6 (4)
I
TTL
PWM Fault 1.
Fault2
J2
M1
F10
PG3 (4)
PC5 (4)
PH5 (10)
I
TTL
PWM Fault 2.
Fault3
E11
D11
PB3 (4)
PH2 (4)
I
TTL
PWM Fault 3.
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Table 21-2. Signals for PWM (108BGA) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PWM0
G1
F3
J1
K1
L6
M9
PD0 (1)
PJ0 (10)
PG2 (1)
PG0 (2)
PA6 (4)
PF0 (3)
O
TTL
PWM 0. This signal is controlled by PWM Generator
0.
PWM1
G2
J2
K2
M6
H12
B6
PD1 (1)
PG3 (1)
PG1 (2)
PA7 (4)
PF1 (3)
PJ1 (10)
O
TTL
PWM 1. This signal is controlled by PWM Generator
0.
PWM2
H2
J11
E12
C9
PD2 (3)
PF2 (4)
PB0 (2)
PH0 (2)
O
TTL
PWM 2. This signal is controlled by PWM Generator
1.
PWM3
H1
J12
D12
C8
PD3 (3)
PF3 (4)
PB1 (2)
PH1 (2)
O
TTL
PWM 3. This signal is controlled by PWM Generator
1.
PWM4
A1
K1
M4
L6
J11
G3
B11
C9
PE6 (1)
PG0 (4)
PA2 (4)
PA6 (5)
PF2 (2)
PH6 (10)
PE0 (1)
PH0 (9)
O
TTL
PWM 4. This signal is controlled by PWM Generator
2.
PWM5
B1
H3
K2
L4
M6
J12
A12
C8
PE7 (1)
PH7 (10)
PG1 (4)
PA3 (4)
PA7 (5)
PF3 (2)
PE1 (1)
PH1 (9)
O
TTL
PWM 5. This signal is controlled by PWM Generator
2.
PWM6
L1
L5
L7
K3
PC4 (4)
PA4 (4)
PG6 (4)
PG4 (9)
O
TTL
PWM 6. This signal is controlled by PWM Generator
3.
PWM7
M2
M5
C10
M7
PC6 (4)
PA5 (4)
PG7 (4)
PG5 (8)
O
TTL
PWM 7. This signal is controlled by PWM Generator
3.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
21.3
Functional Description
21.3.1
PWM Timer
The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down
mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load
value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the
load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode
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is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used
for generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal
(this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down
mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width
High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero
pulse is immediately followed by the load pulse. In the figures in this chapter, these signals are
labelled "dir," "zero," and "load."
21.3.2
PWM Comparators
Each PWM generator has two comparators that monitor the value of the counter; when either
comparator matches the counter, they output a single-clock-cycle-width High pulse, labelled "cmpA"
and "cmpB" in the figures in this chapter. When in Count-Up/Down mode, these comparators match
both when counting up and when counting down, and thus are qualified by the counter direction
signal. These qualified pulses are used in the PWM generation process. If either comparator match
value is greater than the counter load value, then that comparator never outputs a High pulse.
Figure 21-3 on page 968 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 21-4 on page 968 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode. In these figures,
the following definitions apply:
■ LOAD is the value in the PWMnLOAD register
■ COMPA is the value in the PWMnCMPA register
■ COMPB is the value in the PWMnCMPB register
■ 0 is the value zero
■ load is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to the load value
■ zero is the internal signal that has a single-clock-cycle-width High pulse when the counter is zero
■ cmpA is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPA
■ cmpB is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPB
■ dir is the internal signal that indicates the count direction
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Pulse Width Modulator (PWM)
Figure 21-3. PWM Count-Down Mode
LOAD
COMPA
COMPB
0
load
zero
cmpA
cmpB
dir
BDown
ADown
Figure 21-4. PWM Count-Up/Down Mode
LOAD
COMPA
COMPB
0
load
zero
cmpA
cmpB
dir
BUp
AUp
21.3.3
BDown
ADown
PWM Signal Generator
The PWM generator takes the load, zero, cmpA, and cmpB pulses (qualified by the dir signal) and
generates two internal PWM signals, pwmA and pwmB. In Count-Down mode, there are four events
that can affect these signals: zero, load, match A down, and match B down. In Count-Up/Down
mode, there are six events that can affect these signals: zero, load, match A down, match A up,
match B down, and match B up. The match A or match B events are ignored when they coincide
with the zero or load events. If the match A and match B events coincide, the first signal, pwmA, is
generated based only on the match A event, and the second signal, pwmB, is generated based only
on the match B event.
For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring
the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be
used to generate a pair of PWM signals of various positions and duty cycles, which do or do not
overlap. Figure 21-5 on page 969 shows the use of Count-Up/Down mode to generate a pair of
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Stellaris® LM3S5B91 Microcontroller
center-aligned, overlapped PWM signals that have different duty cycles. This figure shows the pwmA
and pwmB signals before they have passed through the dead-band generator.
Figure 21-5. PWM Generation Example In Count-Up/Down Mode
LOAD
COMPA
COMPB
0
pwmA
pwmB
In this example, the first generator is set to drive High on match A up, drive Low on match A down,
and ignore the other four events. The second generator is set to drive High on match B up, drive
Low on match B down, and ignore the other four events. Changing the value of comparator A
changes the duty cycle of the pwmA signal, and changing the value of comparator B changes the
duty cycle of the pwmB signal.
21.3.4
Dead-Band Generator
The pwmA and pwmB signals produced by the PWM generator are passed to the dead-band
generator. If the dead-band generator is disabled, the PWM signals simply pass through to the
pwmA' and pwmB' signals unmodified. If the dead-band generator is enabled, the pwmB signal is
lost and two PWM signals are generated based on the pwmA signal. The first output PWM signal,
pwmA' is the pwmA signal with the rising edge delayed by a programmable amount. The second
output PWM signal, pwmB', is the inversion of the pwmA signal with a programmable delay added
between the falling edge of the pwmA signal and the rising edge of the pwmB' signal.
The resulting signals are a pair of active High signals where one is always High, except for a
programmable amount of time at transitions where both are Low. These signals are therefore suitable
for driving a half-H bridge, with the dead-band delays preventing shoot-through current from damaging
the power electronics. Figure 21-6 on page 969 shows the effect of the dead-band generator on the
pwmA signal and the resulting pwmA' and pwmB' signals that are transmitted to the output control
block.
Figure 21-6. PWM Dead-Band Generator
pwmA
pwmA’
pwmB’
Rising Edge
Delay
21.3.5
Falling Edge
Delay
Interrupt/ADC-Trigger Selector
The PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a
source for an interrupt; when any of the selected events occur, an interrupt is generated. Additionally,
the same event, a different event, the same set of events, or a different set of events can be selected
as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is
generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position
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Pulse Width Modulator (PWM)
within the pwmA or pwmB signal. Note that interrupts and ADC triggers are based on the raw events;
delays in the PWM signal edges caused by the dead-band generator are not taken into account.
21.3.6
Synchronization Methods
The PWM unit provides four PWM generators providing eight PWM outputs that may be used in a
wide variety of applications. Generally speaking, the PWM is used in of two categories of operation:
■ Unsynchronized. The PWM generator and its two output signals are used alone, independent
of other PWM generators.
■ Synchronized. The PWM generator and its two outputs signals are used in conjunction with
other PWM generators using a common, unified time base. If multiple PWM generators are
configured with the same counter load value, synchronization can be used to guarantee that
they also have the same count value (the PWM generators must be configured before they are
synchronized). With this feature, more than two PWMn signals can be produced with a known
relationship between the edges of those signals because the counters always have the same
values. Other states in the unit provide mechanisms to maintain the common time base and
mutual synchronization.
The counter in a PWM unit generator can be reset to zero by writing the PWM Time Base Sync
(PWMSYNC) register and setting the SYNCn bit associated with the generator. Multiple PWM
generators can be synchronized together by setting all necessary SYNCn bits in one access. For
example, setting the SYNC0 and SYNC1 bits in the PWMSYNC register causes the counters in PWM
generators 0 and 1 to reset together.
Additional synchronization can occur between multiple PWM generators by updating register contents
in one of the following three ways:
■ Immediately. The write value has immediate effect, and the hardware reacts immediately.
■ Locally Synchronized. The write value does not affect the logic until the counter reaches the
value zero at the end of the PWM cycle. In this case, the effect of the write is deferred, providing
a guaranteed defined behavior and preventing overly short or overly long output PWM pulses.
■ Globally Synchronized. The write value does not affect the logic until two sequential events
have occurred: (1) the Update mode for the generator function is programmed for global
synchronization in the PWMnCTL register, and (2) the counter reaches zero at the end of the
PWM cycle. In this case, the effect of the write is deferred until the end of the PWM cycle following
the end of all updates. This mode allows multiple items in multiple PWM generators to be updated
simultaneously without odd effects during the update; everything runs from the old values until
a point at which they all run from the new values. The Update mode of the load and comparator
match values can be individually configured in each PWM generator block. It typically makes
sense to use the synchronous update mechanism across PWM generator blocks when the timers
in those blocks are synchronized, although this is not required in order for this mechanism to
function properly.
The following registers provide either local or global synchronization based on the state of various
Update mode bits and fields in the PWMnCTL register (LOADUPD; CMPAUPD; CMPBUPD):
■ Generator Registers: PWMnLOAD, PWMnCMPA, and PWMnCMPB
The following registers default to immediate update, but are provided with the optional functionality
of synchronously updating rather than having all updates take immediate effect:
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Stellaris® LM3S5B91 Microcontroller
■ Module-Level Register: PWMENABLE (based on the state of the ENUPDn bits in the PWMENUPD
register).
■ Generator Register: PWMnGENA, PWMnGENB, PWMnDBCTL, PWMnDBRISE, and
PWMnDBFALL (based on the state of various Update mode bits and fields in the PWMnCTL
register (GENAUPD; GENBUPD; DBCTLUPD; DBRISEUPD; DBFALLUPD)).
All other registers are considered statically provisioned for the execution of an application or are
used dynamically for purposes unrelated to maintaining synchronization and therefore do not need
synchronous update functionality.
21.3.7
Fault Conditions
A fault condition is one in which the controller must be signaled to stop normal PWM function and
then set the PWMn signals to a safe state. Two basic situations cause fault conditions:
■ The microcontroller is stalled and cannot perform the necessary computation in the time required
for motion control
■ An external error or event is detected
The PWM unit can use the following inputs to generate a fault condition, including:
■ FAULTn pin assertion
■ A stall of the controller generated by the debugger
■ The trigger of an ADC digital comparator
Fault conditions are calculated on a per-PWM generator basis. Each PWM generator configures
the necessary conditions to indicate a fault condition exists. This method allows the development
of applications with dependent and independent control.
Four fault input pins (FAULT0-FAULT3). These inputs may be used with circuits that generate an
active High or active Low signal to indicate an error condition. A FAULTn pins may be individually
programmed for the appropriate logic sense using the PWMnFLTSEN register.
The PWM generator's mode control, including fault condition handling, is provided in the PWMnCTL
register. This register determines whether the FAULT0 input or a combination of FAULTn input
signals and/or digital comparator triggers (as configured by the PWMnFLTSRC0 and PWMnFLTSRC1
registers) is used to generate a fault condition. The PWMnCTL register also selects whether the
fault condition is maintained as long as the external condition lasts or if it is latched until the fault
condition until cleared by software. Finally, this register also enables a counter that may be used to
extend the period of a fault condition for external events to assure that the duration is a minimum
length. The minimum fault period count is specified in the PWMnMINFLTPER register.
Status regarding the specific fault cause is provided in the PWMnFLTSTAT0 and PWMnFLTSTAT1
registers.
PWM generator fault conditions may be promoted to a controller interrupt using the PWMINTEN
register.
21.3.8
Output Control Block
The output control block takes care of the final conditioning of the pwmA' and pwmB' signals before
they go to the pins as the PWMn signals. Via a single register, the PWM Output Enable
(PWNENABLE) register, the set of PWM signals that are actually enabled to the pins can be modified.
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This function can be used, for example, to perform commutation of a brushless DC motor with a
single register write (and without modifying the individual PWM generators, which are modified by
the feedback control loop). In addition, the updating of the bits in the PWMENABLE register can
be configured to be immediate or locally or globally synchronized to the next synchronous update
using the PWM Enable Update (PWMENUPD) register.
During fault conditions, the PWM output signals, PWMn, usually must be driven to safe values so
that external equipment may be safely controlled. The PWMFAULT register specifies whether during
a fault condition, the generated signal continues to be passed driven or to an encoding specified in
the PWMFAULTVAL register.
A final inversion can be applied to any of the PWMn signals, making them active Low instead of the
default active High using the PWM Output Inversion (PWMINVERT). The inversion is applied even
if a value has been enabled in the PWMFAULT register and specified in the PWMFAULTVAL
register. In other words, if a bit is set in the PWMFAULT, PWMFAULTVAL, and PWMINVERT
registers, the output on the PWMn signal is 0, not 1 as specified in the PWMFAULTVAL register.
21.4
Initialization and Configuration
The following example shows how to initialize PWM Generator 0 with a 25-kHz frequency, a 25%
duty cycle on the PWM0 pin, and a 75% duty cycle on the PWM1 pin. This example assumes the
system clock is 20 MHz.
1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System
Control module (see page 171).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module (see page 191).
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. To determine which GPIOs to configure, see Table 24-4 on page 1088.
4. Configure the PMCn fields in the GPIOPCTL register to assign the PWM signals to the appropriate
pins (see page 341 and Table 24-5 on page 1097).
5. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
6. Configure the PWM generator for countdown mode with immediate updates to the parameters.
■ Write the PWM0CTL register with a value of 0x0000.0000.
■ Write the PWM0GENA register with a value of 0x0000.008C.
■ Write the PWM0GENB register with a value of 0x0000.080C.
7. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the system clock divided by 2. Thus there are 400 clock ticks per period.
Use this value to set the PWM0LOAD register. In Count-Down mode, set the LOAD field in the
PWM0LOAD register to the requested period minus one.
■ Write the PWM0LOAD register with a value of 0x0000.018F.
8. Set the pulse width of the PWM0 pin for a 25% duty cycle.
■ Write the PWM0CMPA register with a value of 0x0000.012B.
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9. Set the pulse width of the PWM1 pin for a 75% duty cycle.
■ Write the PWM0CMPB register with a value of 0x0000.0063.
10. Start the timers in PWM generator 0.
■ Write the PWM0CTL register with a value of 0x0000.0001.
11. Enable PWM outputs.
■ Write the PWMENABLE register with a value of 0x0000.0003.
21.5
Register Map
Table 21-3 on page 973 lists the PWM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the PWM base address of 0x4002.8000. Note that the PWM module
clock must be enabled before the registers can be programmed (see page 171).
Table 21-3. PWM Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
PWMCTL
R/W
0x0000.0000
PWM Master Control
977
0x004
PWMSYNC
R/W
0x0000.0000
PWM Time Base Sync
979
0x008
PWMENABLE
R/W
0x0000.0000
PWM Output Enable
980
0x00C
PWMINVERT
R/W
0x0000.0000
PWM Output Inversion
982
0x010
PWMFAULT
R/W
0x0000.0000
PWM Output Fault
984
0x014
PWMINTEN
R/W
0x0000.0000
PWM Interrupt Enable
986
0x018
PWMRIS
RO
0x0000.0000
PWM Raw Interrupt Status
988
0x01C
PWMISC
R/W1C
0x0000.0000
PWM Interrupt Status and Clear
991
0x020
PWMSTATUS
RO
0x0000.0000
PWM Status
994
0x024
PWMFAULTVAL
R/W
0x0000.0000
PWM Fault Condition Value
996
0x028
PWMENUPD
R/W
0x0000.0000
PWM Enable Update
998
0x040
PWM0CTL
R/W
0x0000.0000
PWM0 Control
1002
0x044
PWM0INTEN
R/W
0x0000.0000
PWM0 Interrupt and Trigger Enable
1007
0x048
PWM0RIS
RO
0x0000.0000
PWM0 Raw Interrupt Status
1010
0x04C
PWM0ISC
R/W1C
0x0000.0000
PWM0 Interrupt Status and Clear
1012
0x050
PWM0LOAD
R/W
0x0000.0000
PWM0 Load
1014
0x054
PWM0COUNT
RO
0x0000.0000
PWM0 Counter
1015
0x058
PWM0CMPA
R/W
0x0000.0000
PWM0 Compare A
1016
0x05C
PWM0CMPB
R/W
0x0000.0000
PWM0 Compare B
1017
0x060
PWM0GENA
R/W
0x0000.0000
PWM0 Generator A Control
1018
0x064
PWM0GENB
R/W
0x0000.0000
PWM0 Generator B Control
1021
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Table 21-3. PWM Register Map (continued)
Description
See
page
0x0000.0000
PWM0 Dead-Band Control
1024
R/W
0x0000.0000
PWM0 Dead-Band Rising-Edge Delay
1025
PWM0DBFALL
R/W
0x0000.0000
PWM0 Dead-Band Falling-Edge-Delay
1026
0x074
PWM0FLTSRC0
R/W
0x0000.0000
PWM0 Fault Source 0
1027
0x078
PWM0FLTSRC1
R/W
0x0000.0000
PWM0 Fault Source 1
1029
0x07C
PWM0MINFLTPER
R/W
0x0000.0000
PWM0 Minimum Fault Period
1032
0x080
PWM1CTL
R/W
0x0000.0000
PWM1 Control
1002
0x084
PWM1INTEN
R/W
0x0000.0000
PWM1 Interrupt and Trigger Enable
1007
0x088
PWM1RIS
RO
0x0000.0000
PWM1 Raw Interrupt Status
1010
0x08C
PWM1ISC
R/W1C
0x0000.0000
PWM1 Interrupt Status and Clear
1012
0x090
PWM1LOAD
R/W
0x0000.0000
PWM1 Load
1014
0x094
PWM1COUNT
RO
0x0000.0000
PWM1 Counter
1015
0x098
PWM1CMPA
R/W
0x0000.0000
PWM1 Compare A
1016
0x09C
PWM1CMPB
R/W
0x0000.0000
PWM1 Compare B
1017
0x0A0
PWM1GENA
R/W
0x0000.0000
PWM1 Generator A Control
1018
0x0A4
PWM1GENB
R/W
0x0000.0000
PWM1 Generator B Control
1021
0x0A8
PWM1DBCTL
R/W
0x0000.0000
PWM1 Dead-Band Control
1024
0x0AC
PWM1DBRISE
R/W
0x0000.0000
PWM1 Dead-Band Rising-Edge Delay
1025
0x0B0
PWM1DBFALL
R/W
0x0000.0000
PWM1 Dead-Band Falling-Edge-Delay
1026
0x0B4
PWM1FLTSRC0
R/W
0x0000.0000
PWM1 Fault Source 0
1027
0x0B8
PWM1FLTSRC1
R/W
0x0000.0000
PWM1 Fault Source 1
1029
0x0BC
PWM1MINFLTPER
R/W
0x0000.0000
PWM1 Minimum Fault Period
1032
0x0C0
PWM2CTL
R/W
0x0000.0000
PWM2 Control
1002
0x0C4
PWM2INTEN
R/W
0x0000.0000
PWM2 Interrupt and Trigger Enable
1007
0x0C8
PWM2RIS
RO
0x0000.0000
PWM2 Raw Interrupt Status
1010
0x0CC
PWM2ISC
R/W1C
0x0000.0000
PWM2 Interrupt Status and Clear
1012
0x0D0
PWM2LOAD
R/W
0x0000.0000
PWM2 Load
1014
0x0D4
PWM2COUNT
RO
0x0000.0000
PWM2 Counter
1015
0x0D8
PWM2CMPA
R/W
0x0000.0000
PWM2 Compare A
1016
0x0DC
PWM2CMPB
R/W
0x0000.0000
PWM2 Compare B
1017
0x0E0
PWM2GENA
R/W
0x0000.0000
PWM2 Generator A Control
1018
0x0E4
PWM2GENB
R/W
0x0000.0000
PWM2 Generator B Control
1021
Offset
Name
Type
Reset
0x068
PWM0DBCTL
R/W
0x06C
PWM0DBRISE
0x070
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Table 21-3. PWM Register Map (continued)
Description
See
page
0x0000.0000
PWM2 Dead-Band Control
1024
R/W
0x0000.0000
PWM2 Dead-Band Rising-Edge Delay
1025
PWM2DBFALL
R/W
0x0000.0000
PWM2 Dead-Band Falling-Edge-Delay
1026
0x0F4
PWM2FLTSRC0
R/W
0x0000.0000
PWM2 Fault Source 0
1027
0x0F8
PWM2FLTSRC1
R/W
0x0000.0000
PWM2 Fault Source 1
1029
0x0FC
PWM2MINFLTPER
R/W
0x0000.0000
PWM2 Minimum Fault Period
1032
0x100
PWM3CTL
R/W
0x0000.0000
PWM3 Control
1002
0x104
PWM3INTEN
R/W
0x0000.0000
PWM3 Interrupt and Trigger Enable
1007
0x108
PWM3RIS
RO
0x0000.0000
PWM3 Raw Interrupt Status
1010
0x10C
PWM3ISC
R/W1C
0x0000.0000
PWM3 Interrupt Status and Clear
1012
0x110
PWM3LOAD
R/W
0x0000.0000
PWM3 Load
1014
0x114
PWM3COUNT
RO
0x0000.0000
PWM3 Counter
1015
0x118
PWM3CMPA
R/W
0x0000.0000
PWM3 Compare A
1016
0x11C
PWM3CMPB
R/W
0x0000.0000
PWM3 Compare B
1017
0x120
PWM3GENA
R/W
0x0000.0000
PWM3 Generator A Control
1018
0x124
PWM3GENB
R/W
0x0000.0000
PWM3 Generator B Control
1021
0x128
PWM3DBCTL
R/W
0x0000.0000
PWM3 Dead-Band Control
1024
0x12C
PWM3DBRISE
R/W
0x0000.0000
PWM3 Dead-Band Rising-Edge Delay
1025
0x130
PWM3DBFALL
R/W
0x0000.0000
PWM3 Dead-Band Falling-Edge-Delay
1026
0x134
PWM3FLTSRC0
R/W
0x0000.0000
PWM3 Fault Source 0
1027
0x138
PWM3FLTSRC1
R/W
0x0000.0000
PWM3 Fault Source 1
1029
0x13C
PWM3MINFLTPER
R/W
0x0000.0000
PWM3 Minimum Fault Period
1032
0x800
PWM0FLTSEN
R/W
0x0000.0000
PWM0 Fault Pin Logic Sense
1033
0x804
PWM0FLTSTAT0
-
0x0000.0000
PWM0 Fault Status 0
1034
0x808
PWM0FLTSTAT1
-
0x0000.0000
PWM0 Fault Status 1
1036
0x880
PWM1FLTSEN
R/W
0x0000.0000
PWM1 Fault Pin Logic Sense
1033
0x884
PWM1FLTSTAT0
-
0x0000.0000
PWM1 Fault Status 0
1034
0x888
PWM1FLTSTAT1
-
0x0000.0000
PWM1 Fault Status 1
1036
0x900
PWM2FLTSEN
R/W
0x0000.0000
PWM2 Fault Pin Logic Sense
1033
0x904
PWM2FLTSTAT0
-
0x0000.0000
PWM2 Fault Status 0
1034
0x908
PWM2FLTSTAT1
-
0x0000.0000
PWM2 Fault Status 1
1036
0x980
PWM3FLTSEN
R/W
0x0000.0000
PWM3 Fault Pin Logic Sense
1033
Offset
Name
Type
Reset
0x0E8
PWM2DBCTL
R/W
0x0EC
PWM2DBRISE
0x0F0
May 24, 2010
975
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Table 21-3. PWM Register Map (continued)
Offset
Name
0x984
0x988
21.6
Description
See
page
0x0000.0000
PWM3 Fault Status 0
1034
0x0000.0000
PWM3 Fault Status 1
1036
Type
Reset
PWM3FLTSTAT0
-
PWM3FLTSTAT1
-
Register Descriptions
The remainder of this section lists and describes the PWM registers, in numerical order by address
offset.
976
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation blocks.
PWM Master Control (PWMCTL)
Base 0x4002.8000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
GLOBALSYNC3 GLOBALSYNC2 GLOBALSYNC1 GLOBALSYNC0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000
3
GLOBALSYNC3
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Update PWM Generator 3
Value Description
1
Any queued update to a load or comparator register in PWM
generator 3 is applied the next time the corresponding counter
becomes zero.
0
No effect.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
2
GLOBALSYNC2
R/W
0
Update PWM Generator 2
Value Description
1
Any queued update to a load or comparator register in PWM
generator 2 is applied the next time the corresponding counter
becomes zero.
0
No effect.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
1
GLOBALSYNC1
R/W
0
Update PWM Generator 1
Value Description
1
Any queued update to a load or comparator register in PWM
generator 1 is applied the next time the corresponding counter
becomes zero.
0
No effect.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
May 24, 2010
977
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
0
GLOBALSYNC0
R/W
0
Description
Update PWM Generator 0
Value Description
1
Any queued update to a load or comparator register in PWM
generator 0 is applied the next time the corresponding counter
becomes zero.
0
No effect.
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
978
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Setting a bit in this register causes the specified counter to reset back to 0; setting multiple
bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading
them back as zero indicates that the synchronization has completed.
PWM Time Base Sync (PWMSYNC)
Base 0x4002.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
SYNC3
SYNC2
SYNC1
SYNC0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
SYNC3
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reset Generator 3 Counter
Value Description
2
SYNC2
R/W
0
1
Resets the PWM generator 3 counter.
0
No effect.
Reset Generator 2 Counter
Value Description
1
SYNC1
R/W
0
1
Resets the PWM generator 2 counter.
0
No effect.
Reset Generator 1 Counter
Value Description
0
SYNC0
R/W
0
1
Resets the PWM generator 1 counter.
0
No effect.
Reset Generator 0 Counter
Value Description
1
Resets the PWM generator 0 counter.
0
No effect.
May 24, 2010
979
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 3: PWM Output Enable (PWMENABLE), offset 0x008
This register provides a master control of which generated pwmA' and pwmB' signals are output to
the PWMn pins. By disabling a PWM output, the generation process can continue (for example, when
the time bases are synchronized) without driving PWM signals to the pins. When bits in this register
are set, the corresponding pwmA' or pwmB' signal is passed through to the output stage. When bits
are clear, the pwmA' or pwmB' signal is replaced by a zero value which is also passed to the output
stage. The PWMINVERT register controls the output stage, so if the corresponding bit is set in that
register, the value seen on the PWMn signal is inverted from what is configured by the bits in this
register. Updates to the bits in this register can be immediate or locally or globally synchronized to
the next synchronous update as controlled by the ENUPDn fields in the PWMENUPD register.
PWM Output Enable (PWMENABLE)
Base 0x4002.8000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
PWM7EN PWM6EN PWM5EN PWM4EN PWM3EN PWM2EN PWM1EN PWM0EN
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
PWM7EN
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM7 Output Enable
Value Description
6
PWM6EN
R/W
0
1
The generated pwm3B' signal is passed to the PWM7 pin.
0
The PWM7 signal has a zero value.
PWM6 Output Enable
Value Description
5
PWM5EN
R/W
0
1
The generated pwm3A' signal is passed to the PWM6 pin.
0
The PWM6 signal has a zero value.
PWM5 Output Enable
Value Description
1
The generated pwm2B' signal is passed to the PWM5 pin.
0
The PWM5 signal has a zero value.
980
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4
PWM4EN
R/W
0
Description
PWM4 Output Enable
Value Description
3
PWM3EN
R/W
0
1
The generated pwm2A' signal is passed to the PWM4 pin.
0
The PWM4 signal has a zero value.
PWM3 Output Enable
Value Description
2
PWM2EN
R/W
0
1
The generated pwm1B' signal is passed to the PWM3 pin.
0
The PWM3 signal has a zero value.
PWM2 Output Enable
Value Description
1
PWM1EN
R/W
0
1
The generated pwm1A' signal is passed to the PWM2 pin.
0
The PWM2 signal has a zero value.
PWM1 Output Enable
Value Description
0
PWM0EN
R/W
0
1
The generated pwm0B' signal is passed to the PWM1 pin.
0
The PWM1 signal has a zero value.
PWM0 Output Enable
Value Description
1
The generated pwm0A' signal is passed to the PWM0 pin.
0
The PWM0 signal has a zero value.
May 24, 2010
981
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C
This register provides a master control of the polarity of the PWMn signals on the device pins. The
pwmA' and pwmB' signals generated by the PWM generator are active High; but can be made active
Low via this register. Disabled PWM channels are also passed through the output inverter (if so
configured) so that inactive signals can be High. In addition, if the PWMFAULT register enables a
specific value to be placed on the PWMn signals during a fault condition, that value is inverted if the
corresponding bit in this register is set.
PWM Output Inversion (PWMINVERT)
Base 0x4002.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
PWM7INV PWM6INV PWM5INV PWM4INV PWM3INV PWM2INV PWM1INV PWM0INV
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
PWM7INV
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Invert PWM7 Signal
Value Description
6
PWM6INV
R/W
0
1
The PWM7 signal is inverted.
0
The PWM7 signal is not inverted.
Invert PWM6 Signal
Value Description
5
PWM5INV
R/W
0
1
The PWM6 signal is inverted.
0
The PWM6 signal is not inverted.
Invert PWM5 Signal
Value Description
4
PWM4INV
R/W
0
1
The PWM5 signal is inverted.
0
The PWM5 signal is not inverted.
Invert PWM4 Signal
Value Description
1
The PWM4 signal is inverted.
0
The PWM4 signal is not inverted.
982
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
3
PWM3INV
R/W
0
Description
Invert PWM3 Signal
Value Description
2
PWM2INV
R/W
0
1
The PWM3 signal is inverted.
0
The PWM3 signal is not inverted.
Invert PWM2 Signal
Value Description
1
PWM1INV
R/W
0
1
The PWM2 signal is inverted.
0
The PWM2 signal is not inverted.
Invert PWM1 Signal
Value Description
0
PWM0INV
R/W
0
1
The PWM1 signal is inverted.
0
The PWM1 signal is not inverted.
Invert PWM0 Signal
Value Description
1
The PWM0 signal is inverted.
0
The PWM0 signal is not inverted.
May 24, 2010
983
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 5: PWM Output Fault (PWMFAULT), offset 0x010
This register controls the behavior of the PWMn outputs in the presence of fault conditions. Both the
fault inputs (FAULTn pins and digital comparator outputs) and debug events are considered fault
conditions. On a fault condition, each pwmA' or pwmB' signal can be passed through unmodified
or driven to the value specified by the corresponding bit in the PWMFAULTVAL register. For outputs
that are configured for pass-through, the debug event handling on the corresponding PWM generator
also determines if the pwmA' or pwmB' signal continues to be generated.
Fault condition control occurs before the output inverter, so PWM signals driven to a specified value
on fault are inverted if the channel is configured for inversion (therefore, the pin is driven to the
logical complement of the specified value on a fault condition).
PWM Output Fault (PWMFAULT)
Base 0x4002.8000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
FAULT7
R/W
0
RO
0
RO
0
7
6
5
4
3
2
1
0
FAULT7
FAULT6
FAULT5
FAULT4
FAULT3
FAULT2
FAULT1
FAULT0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM7 Fault
Value Description
6
FAULT6
R/W
0
1
The PWM7 output signal is driven to the value specified by the
PWM7 bit in the PWMFAULTVAL register.
0
The generated pwm3B' signal is passed to the PWM7 pin.
PWM6 Fault
Value Description
5
FAULT5
R/W
0
1
The PWM6 output signal is driven to the value specified by the
PWM6 bit in the PWMFAULTVAL register.
0
The generated pwm3A' signal is passed to the PWM6 pin.
PWM5 Fault
Value Description
1
The PWM5 output signal is driven to the value specified by the
PWM5 bit in the PWMFAULTVAL register.
0
The generated pwm2B' signal is passed to the PWM5 pin.
984
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
Description
4
FAULT4
R/W
0
PWM4 Fault
Value Description
3
FAULT3
R/W
0
1
The PWM4 output signal is driven to the value specified by the
PWM4 bit in the PWMFAULTVAL register.
0
The generated pwm2A' signal is passed to the PWM4 pin.
PWM3 Fault
Value Description
2
FAULT2
R/W
0
1
The PWM3 output signal is driven to the value specified by the
PWM3 bit in the PWMFAULTVAL register.
0
The generated pwm1B' signal is passed to the PWM3 pin.
PWM2 Fault
Value Description
1
FAULT1
R/W
0
1
The PWM2 output signal is driven to the value specified by the
PWM2 bit in the PWMFAULTVAL register.
0
The generated pwm1A' signal is passed to the PWM2 pin.
PWM1 Fault
Value Description
0
FAULT0
R/W
0
1
The PWM1 output signal is driven to the value specified by the
PWM1 bit in the PWMFAULTVAL register.
0
The generated pwm0B' signal is passed to the PWM1 pin.
PWM0 Fault
Value Description
1
The PWM0 output signal is driven to the value specified by the
PWM0 bit in the PWMFAULTVAL register.
0
The generated pwm0A' signal is passed to the PWM0 pin.
May 24, 2010
985
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014
This register controls the global interrupt generation capabilities of the PWM module. The events
that can cause an interrupt are the fault input and the individual interrupts from the PWM generators.
PWM Interrupt Enable (PWMINTEN)
Base 0x4002.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
18
17
16
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
reserved
Type
Reset
19
INTPWM3 INTPWM2 INTPWM1 INTPWM0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
INTFAULT3
R/W
0
Interrupt Fault 3
Value Description
18
INTFAULT2
R/W
0
1
An interrupt is sent to the interrupt controller when the fault
condition for PWM generator 3 is asserted.
0
The fault condition for PWM generator 3 is suppressed and not
sent to the interrupt controller.
Interrupt Fault 2
Value Description
17
INTFAULT1
R/W
0
1
An interrupt is sent to the interrupt controller when the fault
condition for PWM generator 2 is asserted.
0
The fault condition for PWM generator 2 is suppressed and not
sent to the interrupt controller.
Interrupt Fault 1
Value Description
1
An interrupt is sent to the interrupt controller when the fault
condition for PWM generator 1 is asserted.
0
The fault condition for PWM generator 1 is suppressed and not
sent to the interrupt controller.
986
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
16
INTFAULT0
R/W
0
Description
Interrupt Fault 0
Value Description
15:4
reserved
RO
0x000
3
INTPWM3
R/W
0
1
An interrupt is sent to the interrupt controller when the fault
condition for PWM generator 0 is asserted.
0
The fault condition for PWM generator 0 is suppressed and not
sent to the interrupt controller.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM3 Interrupt Enable
Value Description
2
INTPWM2
R/W
0
1
An interrupt is sent to the interrupt controller when the PWM
generator 3 block asserts an interrupt.
0
The PWM generator 3 interrupt is suppressed and not sent to
the interrupt controller.
PWM2 Interrupt Enable
Value Description
1
INTPWM1
R/W
0
1
An interrupt is sent to the interrupt controller when the PWM
generator 2 block asserts an interrupt.
0
The PWM generator 2 interrupt is suppressed and not sent to
the interrupt controller.
PWM1 Interrupt Enable
Value Description
0
INTPWM0
R/W
0
1
An interrupt is sent to the interrupt controller when the PWM
generator 1 block asserts an interrupt.
0
The PWM generator 1 interrupt is suppressed and not sent to
the interrupt controller.
PWM0 Interrupt Enable
Value Description
1
An interrupt is sent to the interrupt controller when the PWM
generator 0 block asserts an interrupt.
0
The PWM generator 0 interrupt is suppressed and not sent to
the interrupt controller.
May 24, 2010
987
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they are enabled to cause an interrupt to be asserted to the interrupt controller. The fault interrupt
is asserted based on the fault condition source that is specified by the PWMnCTL, PWMnFLTSRC0
and PWMnFLTSRC1 registers. The fault interrupt is latched on detection and must be cleared
through the PWM Interrupt Status and Clear (PWMISC) register. The actual value of the FAULTn
signals can be observed using the PWMSTATUS register.
The PWM generator interrupts simply reflect the status of the PWM generators and are cleared via
the interrupt status register in the PWM generator blocks. If a bit is set, the event is active; if a bit
is clear the event is not active.
PWM Raw Interrupt Status (PWMRIS)
Base 0x4002.8000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
19
18
17
16
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
INTFAULT3
RO
0
Interrupt Fault PWM 3
Value Description
1
The fault condition for PWM generator 3 is asserted.
0
The fault condition for PWM generator 3 has not been asserted.
This bit is cleared by writing a 1 to the INTFAULT3 bit in the PWMISC
register.
18
INTFAULT2
RO
0
Interrupt Fault PWM 2
Value Description
1
The fault condition for PWM generator 2 is asserted.
0
The fault condition for PWM generator 2 has not been asserted.
This bit is cleared by writing a 1 to the INTFAULT2 bit in the PWMISC
register.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
17
INTFAULT1
RO
0
Description
Interrupt Fault PWM 1
Value Description
1
The fault condition for PWM generator 1 is asserted.
0
The fault condition for PWM generator 1 has not been asserted.
This bit is cleared by writing a 1 to the INTFAULT1 bit in the PWMISC
register.
16
INTFAULT0
RO
0
Interrupt Fault PWM 0
Value Description
1
The fault condition for PWM generator 0 is asserted.
0
The fault condition for PWM generator 0 has not been asserted.
This bit is cleared by writing a 1 to the INTFAULT0 bit in the PWMISC
register.
15:4
reserved
RO
0x000
3
INTPWM3
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM3 Interrupt Asserted
Value Description
1
The PWM generator 3 block interrupt is asserted.
0
The PWM generator 3 block interrupt has not been asserted.
The PWM3RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM3ISC register.
2
INTPWM2
RO
0
PWM2 Interrupt Asserted
Value Description
1
The PWM generator 2 block interrupt is asserted.
0
The PWM generator 2 block interrupt has not been asserted.
The PWM2RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM2ISC register.
1
INTPWM1
RO
0
PWM1 Interrupt Asserted
Value Description
1
The PWM generator 1 block interrupt is asserted.
0
The PWM generator 1 block interrupt has not been asserted.
The PWM1RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM1ISC register.
May 24, 2010
989
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
0
INTPWM0
RO
0
Description
PWM0 Interrupt Asserted
Value Description
1
The PWM generator 0 block interrupt is asserted.
0
The PWM generator 0 block interrupt has not been asserted.
The PWM0RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM0ISC register.
990
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the individual PWM generator blocks. If
a fault interrupt is set, the corresponding FAULTn input has caused an interrupt. For the fault interrupt,
a write of 1 to that bit position clears the latched interrupt status. If an block interrupt bit is set, the
corresponding generator block is asserting an interrupt. The individual interrupt status registers,
PWMnISC, in each block must be consulted to determine the reason for the interrupt and used to
clear the interrupt.
PWM Interrupt Status and Clear (PWMISC)
Base 0x4002.8000
Offset 0x01C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
18
17
16
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
reserved
Type
Reset
19
INTPWM3 INTPWM2 INTPWM1 INTPWM0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
INTFAULT3
R/W1C
0
FAULT3 Interrupt Asserted
Value Description
1
An enabled interrupt for the fault condition for PWM generator
3 is asserted or is latched.
0
The fault condition for PWM generator 3 has not been asserted
or is not enabled.
Writing a 1 to this bit clears it and the INTFAULT3 bit in the PWMRIS
register.
18
INTFAULT2
R/W1C
0
FAULT2 Interrupt Asserted
Value Description
1
An enabled interrupt for the fault condition for PWM generator
2 is asserted or is latched.
0
The fault condition for PWM generator 2 has not been asserted
or is not enabled.
Writing a 1 to this bit clears it and the INTFAULT2 bit in the PWMRIS
register.
May 24, 2010
991
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
17
INTFAULT1
R/W1C
0
Description
FAULT1 Interrupt Asserted
Value Description
1
An enabled interrupt for the fault condition for PWM generator
1 is asserted or is latched.
0
The fault condition for PWM generator 1 has not been asserted
or is not enabled.
Writing a 1 to this bit clears it and the INTFAULT1 bit in the PWMRIS
register.
16
INTFAULT0
R/W1C
0
FAULT0 Interrupt Asserted
Value Description
1
An enabled interrupt for the fault condition for PWM generator
0 is asserted or is latched.
0
The fault condition for PWM generator 0 has not been asserted
or is not enabled.
Writing a 1 to this bit clears it and the INTFAULT0 bit in the PWMRIS
register.
15:4
reserved
RO
0x000
3
INTPWM3
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM3 Interrupt Status
Value Description
1
An enabled interrupt for the PWM generator 3 block is asserted.
0
The PWM generator 3 block interrupt is not asserted or is not
enabled.
The PWM3RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM3ISC register.
2
INTPWM2
RO
0
PWM2 Interrupt Status
Value Description
1
An enabled interrupt for the PWM generator 2 block is asserted.
0
The PWM generator 2 block interrupt is not asserted or is not
enabled.
The PWM2RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM2ISC register.
1
INTPWM1
RO
0
PWM1 Interrupt Status
Value Description
1
An enabled interrupt for the PWM generator 1 block is asserted.
0
The PWM generator 1 block interrupt is not asserted or is not
enabled.
The PWM1RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM1ISC register.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
0
INTPWM0
RO
0
Description
PWM0 Interrupt Status
Value Description
1
An enabled interrupt for the PWM generator 0 block is asserted.
0
The PWM generator 0 block interrupt is not asserted or is not
enabled.
The PWM0RIS register shows the source of this interrupt. This bit is
cleared by writing a 1 to the corresponding bit in the PWM0ISC register.
May 24, 2010
993
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 9: PWM Status (PWMSTATUS), offset 0x020
This register provides the unlatched status of the PWM generator fault condition.
PWM Status (PWMSTATUS)
Base 0x4002.8000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
FAULT3
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Generator 3 Fault Status
Value Description
1
The fault condition for PWM generator 3 is asserted.
If the FLTSRC bit in the PWM3CTL register is clear, the FAULT0
input is the source of the fault condition, and is therefore
asserted.
0
2
FAULT2
RO
0
The fault condition for PWM generator 3 is not asserted.
Generator 2 Fault Status
Value Description
1
The fault condition for PWM generator 2 is asserted.
If the FLTSRC bit in the PWM2CTL register is clear, the FAULT0
input is the source of the fault condition, and is therefore
asserted.
0
1
FAULT1
RO
0
The fault condition for PWM generator 2 is not asserted.
Generator 1 Fault Status
Value Description
1
The fault condition for PWM generator 1 is asserted.
If the FLTSRC bit in the PWM1CTL register is clear, the FAULT0
input is the source of the fault condition, and is therefore
asserted.
0
The fault condition for PWM generator 1 is not asserted.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
0
FAULT0
RO
0
Description
Generator 0 Fault Status
Value Description
1
The fault condition for PWM generator 0 is asserted.
If the FLTSRC bit in the PWM0CTL register is clear, the FAULT0
input is the source of the fault condition, and is therefore
asserted.
0
The fault condition for PWM generator 0 is not asserted.
May 24, 2010
995
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024
This register specifies the output value driven on the PWMn signals during a fault condition if enabled
by the corresponding bit in the PWMFAULT register. Note that if the corresponding bit in the
PWMINVERT register is set, the output value is driven to the logical NOT of the bit value in this
register.
PWM Fault Condition Value (PWMFAULTVAL)
Base 0x4002.8000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
PWM7
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM7 Fault Value
Value Description
6
PWM6
R/W
0
1
The PWM7 output signal is driven High during fault conditions if
the FAULT7 bit in the PWMFAULT register is set.
0
The PWM7 output signal is driven Low during fault conditions if
the FAULT7 bit in the PWMFAULT register is set.
PWM6 Fault Value
Value Description
5
PWM5
R/W
0
1
The PWM6 output signal is driven High during fault conditions if
the FAULT6 bit in the PWMFAULT register is set.
0
The PWM6 output signal is driven Low during fault conditions if
the FAULT6 bit in the PWMFAULT register is set.
PWM5 Fault Value
Value Description
1
The PWM5 output signal is driven High during fault conditions if
the FAULT5 bit in the PWMFAULT register is set.
0
The PWM5 output signal is driven Low during fault conditions if
the FAULT5 bit in the PWMFAULT register is set.
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4
PWM4
R/W
0
Description
PWM4 Fault Value
Value Description
3
PWM3
R/W
0
1
The PWM4 output signal is driven High during fault conditions if
the FAULT4 bit in the PWMFAULT register is set.
0
The PWM4 output signal is driven Low during fault conditions if
the FAULT4 bit in the PWMFAULT register is set.
PWM3 Fault Value
Value Description
1
0
2
PWM2
R/W
0
The PWM3 output signal is driven High during fault conditions if
the FAULT3 bit in the PWMFAULT register is set.
The PWM3 output signal is driven Low during fault conditions if
the FAULT3 bit in the PWMFAULT register is set.
PWM2 Fault Value
Value Description
1
PWM1
R/W
0
1
The PWM2 output signal is driven High during fault conditions if
the FAULT2 bit in the PWMFAULT register is set.
0
The PWM2 output signal is driven Low during fault conditions if
the FAULT2 bit in the PWMFAULT register is set.
PWM1 Fault Value
Value Description
0
PWM0
R/W
0
1
The PWM1 output signal is driven High during fault conditions if
the FAULT1 bit in the PWMFAULT register is set.
0
The PWM1 output signal is driven Low during fault conditions if
the FAULT1 bit in the PWMFAULT register is set.
PWM0 Fault Value
Value Description
1
The PWM0 output signal is driven High during fault conditions if
the FAULT0 bit in the PWMFAULT register is set.
0
The PWM0 output signal is driven Low during fault conditions if
the FAULT0 bit in the PWMFAULT register is set.
May 24, 2010
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Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 11: PWM Enable Update (PWMENUPD), offset 0x028
This register specifies when updates to the PWMnEn bit in the PWMENABLE register are performed.
The PWMnEn bit enables the pwmA' or pwmB' output to be passed to the microcontroller's pin.
Updates can be immediate or locally or globally synchronized to the next synchronous update.
PWM Enable Update (PWMENUPD)
Base 0x4002.8000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
ENUPD7
Type
Reset
R/W
0
R/W
0
ENUPD6
R/W
0
R/W
0
ENUPD5
R/W
0
R/W
0
ENUPD4
R/W
0
ENUPD3
ENUPD2
ENUPD1
ENUPD0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:14
ENUPD7
R/W
0
PWM7 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM7En bit in the PWMENABLE register are used
by the PWM generator module immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM7En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM7En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0
after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register.
998
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
13:12
ENUPD6
R/W
0
Description
PWM6 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM6En bit in the PWMENABLE register are used
by the PWM generator module immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM6En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM6En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0
after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register.
11:10
ENUPD5
R/W
0
PWM5 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM5En bit in the PWMENABLE register are used
by the PWM generator module immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM5En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM5En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0
after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register.
9:8
ENUPD4
R/W
0
PWM4 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM4En bit in the PWMENABLE register are used
by the PWM generator module immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM4En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM4En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0
after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register.
May 24, 2010
999
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
7:6
ENUPD3
R/W
0
Description
PWM3 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM3En bit in the PWMENABLE register are used
by the PWM generator module immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM3En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM3En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0
after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register.
5:4
ENUPD2
R/W
0
PWM2 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM2En bit in the PWMENABLE register are used
by the PWM generator module immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM2En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM2En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0
after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register.
3:2
ENUPD1
R/W
0
PWM1 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM1En bit in the PWMENABLE register are used
by the PWM generator module immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM1En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM1En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0
after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register.
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
1:0
ENUPD0
R/W
0
Description
PWM0 Enable Update Mode
Value Description
0x0
Immediate
Writes to the PWM0En bit in the PWMENABLE register are used
by the PWM generator module immediately.
0x1
Reserved
0x2
Locally Synchronized
Writes to the PWM0En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0.
0x3
Globally Synchronized
Writes to the PWM0En bit in the PWMENABLE register are used
by the PWM generator module the next time the counter is 0
after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register.
May 24, 2010
1001
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 12: PWM0 Control (PWM0CTL), offset 0x040
Register 13: PWM1 Control (PWM1CTL), offset 0x080
Register 14: PWM2 Control (PWM2CTL), offset 0x0C0
Register 15: PWM3 Control (PWM3CTL), offset 0x100
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and
PWM3 outputs, the PWM2 block produces the PWM4 and PWM5 outputs, and the PWM3 block produces
the PWM6 and PWM7 outputs.
PWM0 Control (PWM0CTL)
Base 0x4002.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
DBFALLUPD
Type
Reset
R/W
0
R/W
0
DBRISEUPD
R/W
0
R/W
0
DBCTLUPD
R/W
0
R/W
0
GENBUPD
R/W
0
18
17
16
LATCH MINFLTPER FLTSRC
GENAUPD
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
5
4
3
2
CMPBUPD CMPAUPD LOADUPD DEBUG
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
1
0
MODE
ENABLE
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:19
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
18
LATCH
R/W
0
Latch Fault Input
Value Description
0
Fault Condition Not Latched
A fault condition is in effect for as long as the generating source
is asserting.
1
Fault Condition Latched
A fault condition is set as the result of the assertion of the
faulting source and is held (latched) while the PWMISC
INTFAULTn bit is set. Clearing the INTFAULTn bit clears the
fault condition.
1002
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
17
MINFLTPER
R/W
0
Description
Minimum Fault Period
This bit specifies that the PWM generator enables a one-shot counter
to provide a minimum fault condition period.
The timer begins counting on the rising edge of the fault condition to
extend the condition for a minimum duration of the count value. The
timer ignores the state of the fault condition while counting.
The minimum fault delay is in effect only when the MINFLTPER bit is
set. If a detected fault is in the process of being extended when the
MINFLTPER bit is cleared, the fault condition extension is aborted.
The delay time is specified by the PWMnMINFLTPER register MFP field
value. The effect of this is to pulse stretch the fault condition input.
The delay value is defined by the PWM clock period. Because the fault
input is not synchronized to the PWM clock, the period of the time is
PWMClock * (MFP value + 1) or PWMClock * (MFP value + 2).
The delay function makes sense only if the fault source is unlatched. A
latched fault source makes the fault condition appear asserted until
cleared by software and negates the utility of the extend feature. It
applies to all fault condition sources as specified in the FLTSRC field.
Value Description
16
FLTSRC
R/W
0
0
The FAULT input deassertion is unaffected.
1
The PWMnMINFLTPER one-shot counter is active and extends
the period of the fault condition to a minimum period.
Fault Condition Source
Value Description
15:14
DBFALLUPD
R/W
0x0
0
The Fault condition is determined by the Fault0 input.
1
The Fault condition is determined by the configuration of the
PWMnFLTSRC0 and PWMnFLTSRC1 registers.
PWMnDBFALL Update Mode
Value Description
0x0
Immediate
The PWMnDBFALL register value is immediately updated on
a write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
May 24, 2010
1003
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
13:12
DBRISEUPD
R/W
0x0
Description
PWMnDBRISE Update Mode
Value Description
0x0
Immediate
The PWMnDBRISE register value is immediately updated on
a write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
11:10
DBCTLUPD
R/W
0x0
PWMnDBCTL Update Mode
Value Description
0x0
Immediate
The PWMnDBCTL register value is immediately updated on a
write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
9:8
GENBUPD
R/W
0x0
PWMnGENB Update Mode
Value Description
0x0
Immediate
The PWMnGENB register value is immediately updated on a
write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
1004
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
7:6
GENAUPD
R/W
0x0
Description
PWMnGENA Update Mode
Value
Description
0x0
Immediate
The PWMnGENA register value is immediately updated
on a write.
0x1
Reserved
0x2
Locally Synchronized
Updates to the register are reflected to the generator the
next time the counter is 0.
0x3
Globally Synchronized
Updates to the register are delayed until the next time
the counter is 0 after a synchronous update has been
requested through the PWMCTL register.
5
CMPBUPD
R/W
0
Comparator B Update Mode
Value Description
0
Locally Synchronized
Updates to the PWMnCMPB register are reflected to the
generator the next time the counter is 0.
1
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
4
CMPAUPD
R/W
0
Comparator A Update Mode
Value Description
0
Locally Synchronized
Updates to the PWMnCMPA register are reflected to the
generator the next time the counter is 0.
1
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
3
LOADUPD
R/W
0
Load Register Update Mode
Value Description
0
Locally Synchronized
Updates to the PWMnLOAD register are reflected to the
generator the next time the counter is 0.
1
Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWMCTL register.
May 24, 2010
1005
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
2
DEBUG
R/W
0
Description
Debug Mode
Value Description
1
MODE
R/W
0
0
The counter stops running when it next reaches 0 and continues
running again when no longer in Debug mode.
1
The counter always runs when in Debug mode.
Counter Mode
Value Description
0
ENABLE
R/W
0
0
The counter counts down from the load value to 0 and then
wraps back to the load value (Count-Down mode).
1
The counter counts up from 0 to the load value, back down to
0, and then repeats (Count-Up/Down mode).
PWM Block Enable
Value Description
0
The entire PWM generation block is disabled and not clocked.
1
The PWM generation block is enabled and produces PWM
signals.
1006
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 16: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 17: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
Register 18: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
Register 19: PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt or an ADC trigger are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the PWMnCMPA register while counting up
■ The counter being equal to the PWMnCMPA register while counting down
■ The counter being equal to the PWMnCMPB register while counting up
■ The counter being equal to the PWMnCMPB register while counting down
Any combination of these events can generate either an interrupt or an ADC trigger, though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified. The PWMnRIS register provides information about which events have caused raw
interrupts.
PWM0 Interrupt and Trigger Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
15
14
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
10
9
8
7
6
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0x0000.0
13
TRCMPBD
R/W
0
R/W
0
reserved
RO
0
RO
0
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Trigger for Counter=PWMnCMPB Down
Value Description
1
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting down.
0
No ADC trigger is output.
May 24, 2010
1007
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
12
TRCMPBU
R/W
0
Description
Trigger for Counter=PWMnCMPB Up
Value Description
11
TRCMPAD
R/W
0
1
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPB register value while counting up.
0
No ADC trigger is output.
Trigger for Counter=PWMnCMPA Down
Value Description
10
TRCMPAU
R/W
0
1
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPA register value while counting down.
0
No ADC trigger is output.
Trigger for Counter=PWMnCMPA Up
Value Description
9
TRCNTLOAD
R/W
0
1
An ADC trigger pulse is output when the counter matches the
value in the PWMnCMPA register value while counting up.
0
No ADC trigger is output.
Trigger for Counter=PWMnLOAD
Value Description
8
TRCNTZERO
R/W
0
1
An ADC trigger pulse is output when the counter matches the
PWMnLOAD register.
0
No ADC trigger is output.
Trigger for Counter=0
Value Description
7:6
reserved
RO
0x0
5
INTCMPBD
R/W
0
1
An ADC trigger pulse is output when the counter is 0.
0
No ADC trigger is output.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt for Counter=PWMnCMPB Down
Value Description
1
A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting down.
0
No interrupt.
1008
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
4
INTCMPBU
R/W
0
Description
Interrupt for Counter=PWMnCMPB Up
Value Description
3
INTCMPAD
R/W
0
1
A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting up.
0
No interrupt.
Interrupt for Counter=PWMnCMPA Down
Value Description
2
INTCMPAU
R/W
0
1
A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting down.
0
No interrupt.
Interrupt for Counter=PWMnCMPA Up
Value Description
1
INTCNTLOAD
R/W
0
1
A raw interrupt occurs when the counter matches the value in
the PWMnCMPA register value while counting up.
0
No interrupt.
Interrupt for Counter=PWMnLOAD
Value Description
0
INTCNTZERO
R/W
0
1
A raw interrupt occurs when the counter matches the value in
the PWMnLOAD register value.
0
No interrupt.
Interrupt for Counter=0
Value Description
1
A raw interrupt occurs when the counter is zero.
0
No interrupt.
May 24, 2010
1009
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 20: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048
Register 21: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088
Register 22: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8
Register 23: PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108
These registers provide the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0
block, and so on). If a bit is set, the event has occurred; if a bit is clear, the event has not occurred.
Bits in this register are cleared by writing a 1 to the corresponding bit in the PWMnISC register.
PWM0 Raw Interrupt Status (PWM0RIS)
Base 0x4002.8000
Offset 0x048
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.000
5
INTCMPBD
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator B Down Interrupt Status
Value Description
1
The counter has matched the value in the PWMnCMPB register
while counting down.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTCMPBD bit in the PWMnISC
register.
4
INTCMPBU
RO
0
Comparator B Up Interrupt Status
Value Description
1
The counter has matched the value in the PWMnCMPB register
while counting up.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTCMPBU bit in the PWMnISC
register.
1010
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
3
INTCMPAD
RO
0
Description
Comparator A Down Interrupt Status
Value Description
1
The counter has matched the value in the PWMnCMPA register
while counting down.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTCMPAD bit in the PWMnISC
register.
2
INTCMPAU
RO
0
Comparator A Up Interrupt Status
Value Description
1
The counter has matched the value in the PWMnCMPA register
while counting up.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTCMPAU bit in the PWMnISC
register.
1
INTCNTLOAD
RO
0
Counter=Load Interrupt Status
Value Description
1
The counter has matched the value in the PWMnLOAD register.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTCNTLOAD bit in the PWMnISC
register.
0
INTCNTZERO
RO
0
Counter=0 Interrupt Status
Value Description
1
The counter has matched zero.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTCNTZERO bit in the PWMnISC
register.
May 24, 2010
1011
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 24: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 25: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
Register 26: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
Register 27: PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C
These registers provide the current set of interrupt sources that are asserted to the interrupt controller
(PWM0ISC controls the PWM generator 0 block, and so on). A bit is set if the event has occurred
and is enabled in the PWMnINTEN register; if a bit is clear, the event has not occurred or is not
enabled. These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt
reason.
PWM0 Interrupt Status and Clear (PWM0ISC)
Base 0x4002.8000
Offset 0x04C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5
INTCMPBD
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator B Down Interrupt
Value Description
1
The INTCMPBD bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPBD bit in the PWMnRIS register.
4
INTCMPBU
R/W1C
0
Comparator B Up Interrupt
Value Description
1
The INTCMPBU bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPBU bit in the PWMnRIS register.
1012
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
3
INTCMPAD
R/W1C
0
Description
Comparator A Down Interrupt
Value Description
1
The INTCMPAD bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPAD bit in the PWMnRIS register.
2
INTCMPAU
R/W1C
0
Comparator A Up Interrupt
Value Description
1
The INTCMPAU bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPAU bit in the PWMnRIS register.
1
INTCNTLOAD
R/W1C
0
Counter=Load Interrupt
Value Description
1
The INTCNTLOAD bits in the PWMnRIS and PWMnINTEN
registers are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCNTLOAD bit in the PWMnRIS register.
0
INTCNTZERO
R/W1C
0
Counter=0 Interrupt
Value Description
1
The INTCNTZERO bits in the PWMnRIS and PWMnINTEN
registers are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCNTZERO bit in the PWMnRIS register.
May 24, 2010
1013
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 28: PWM0 Load (PWM0LOAD), offset 0x050
Register 29: PWM1 Load (PWM1LOAD), offset 0x090
Register 30: PWM2 Load (PWM2LOAD), offset 0x0D0
Register 31: PWM3 Load (PWM3LOAD), offset 0x110
These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM
generator 0 block, and so on). Based on the counter mode configured by the MODE bit in the
PWMnCTL register, this value is either loaded into the counter after it reaches zero or is the limit
of up-counting after which the counter decrements back to zero. When this value matches the
counter, a pulse is output which can be configured to drive the generation of the pwmA and/or pwmB
signal (via the PWMnGENA/PWMnGENB register) or drive an interruptor ADC trigger (via the
PWMnINTEN register).
If the Load Value Update mode is locally synchronized (based on the LOADUPD field encoding in
the PWMnCTL register), the 16-bit LOAD value is used the next time the counter reaches zero. If
the update mode is globally synchronized, it is used the next time the counter reaches zero after a
synchronous update has been requested through the PWM Master Control (PWMCTL) register
(see page 977). If this register is re-written before the actual update occurs, the previous value is
never used and is lost.
PWM0 Load (PWM0LOAD)
Base 0x4002.8000
Offset 0x050
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
LOAD
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
LOAD
R/W
0x0000
Counter Load Value
The counter load value.
1014
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 32: PWM0 Counter (PWM0COUNT), offset 0x054
Register 33: PWM1 Counter (PWM1COUNT), offset 0x094
Register 34: PWM2 Counter (PWM2COUNT), offset 0x0D4
Register 35: PWM3 Counter (PWM3COUNT), offset 0x114
These registers contain the current value of the PWM counter. When this value matches zero or
the value in the PWMnLOAD, PWMnCMPA, or PWMnCMPB registers, a pulse is output which can
be configured to drive the generation of a PWM signal or drive an interrupt or ADC trigger.
PWM0 Counter (PWM0COUNT)
Base 0x4002.8000
Offset 0x054
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
COUNT
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
COUNT
RO
0x0000
Counter Value
The current value of the counter.
May 24, 2010
1015
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 36: PWM0 Compare A (PWM0CMPA), offset 0x058
Register 37: PWM1 Compare A (PWM1CMPA), offset 0x098
Register 38: PWM2 Compare A (PWM2CMPA), offset 0x0D8
Register 39: PWM3 Compare A (PWM3CMPA), offset 0x118
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which
can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA
and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If
the value of this register is greater than the PWMnLOAD register (see page 1014), then no pulse is
ever output.
If the comparator A update mode is locally synchronized (based on the CMPAUPD bit in the PWMnCTL
register), the 16-bit COMPA value is used the next time the counter reaches zero. If the update mode
is globally synchronized, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 977).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWM0 Compare A (PWM0CMPA)
Base 0x4002.8000
Offset 0x058
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
COMPA
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
COMPA
R/W
0x00
Comparator A Value
The value to be compared against the counter.
1016
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 40: PWM0 Compare B (PWM0CMPB), offset 0x05C
Register 41: PWM1 Compare B (PWM1CMPB), offset 0x09C
Register 42: PWM2 Compare B (PWM2CMPB), offset 0x0DC
Register 43: PWM3 Compare B (PWM3CMPB), offset 0x11C
These registers contain a value to be compared against the counter (PWM0CMPB controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which
can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA
and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If
the value of this register is greater than the PWMnLOAD register, no pulse is ever output.
If the comparator B update mode is locally synchronized (based on the CMPBUPD bit in the PWMnCTL
register), the 16-bit COMPB value is used the next time the counter reaches zero. If the update mode
is globally synchronized, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 977).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWM0 Compare B (PWM0CMPB)
Base 0x4002.8000
Offset 0x05C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
COMPB
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
COMPB
R/W
0x0000
Comparator B Value
The value to be compared against the counter.
May 24, 2010
1017
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 44: PWM0 Generator A Control (PWM0GENA), offset 0x060
Register 45: PWM1 Generator A Control (PWM1GENA), offset 0x0A0
Register 46: PWM2 Generator A Control (PWM2GENA), offset 0x0E0
Register 47: PWM3 Generator A Control (PWM3GENA), offset 0x120
These registers control the generation of the pwmA signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM
signal.
The PWM0GENA register controls generation of the pwm0A signal; PWM1GENA, the pwm1A
signal; PWM2GENA, the pwm2A signal; and PWM3GENA, the pwm3A signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
If the Generator A update mode is immediate (based on the GENAUPD field encoding in the PWMnCTL
register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are
used immediately. If the update mode is locally synchronized, these values are used the next time
the counter reaches zero. If the update mode is globally synchronized, these values are used the
next time the counter reaches zero after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register (see page 977). If this register is rewritten before the
actual update occurs, the previous value is never used and is lost.
PWM0 Generator A Control (PWM0GENA)
Base 0x4002.8000
Offset 0x060
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
ACTCMPBD
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
9
8
ACTCMPBU
R/W
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
R/W
0
ACTCMPAD
R/W
0
R/W
0
ACTCMPAU
R/W
0
R/W
0
ACTLOAD
R/W
0
R/W
0
ACTZERO
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1018
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
11:10
ACTCMPBD
R/W
0x0
Description
Action for Comparator B Down
This field specifies the action to be taken when the counter matches
comparator B while counting down.
Value Description
9:8
ACTCMPBU
R/W
0x0
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
Action for Comparator B Up
This field specifies the action to be taken when the counter matches
comparator B while counting up. This action can only occur when the
MODE bit in the PWMnCTL register is set.
Value Description
7:6
ACTCMPAD
R/W
0x0
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
Action for Comparator A Down
This field specifies the action to be taken when the counter matches
comparator A while counting down.
Value Description
5:4
ACTCMPAU
R/W
0x0
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
Action for Comparator A Up
This field specifies the action to be taken when the counter matches
comparator A while counting up. This action can only occur when the
MODE bit in the PWMnCTL register is set.
Value Description
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
May 24, 2010
1019
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
3:2
ACTLOAD
R/W
0x0
Description
Action for Counter=LOAD
This field specifies the action to be taken when the counter matches the
value in the PWMnLOAD register.
Value Description
1:0
ACTZERO
R/W
0x0
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
Action for Counter=0
This field specifies the action to be taken when the counter is zero.
Value Description
0x0
Do nothing.
0x1
Invert pwmA.
0x2
Drive pwmA Low.
0x3
Drive pwmA High.
1020
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 48: PWM0 Generator B Control (PWM0GENB), offset 0x064
Register 49: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
Register 50: PWM2 Generator B Control (PWM2GENB), offset 0x0E4
Register 51: PWM3 Generator B Control (PWM3GENB), offset 0x124
These registers control the generation of the pwmB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM
signal.
The PWM0GENB register controls generation of the pwm0B signal; PWM1GENB, the pwm1B
signal; PWM2GENB, the pwm2B signal; and PWM3GENB, the pwm3B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
If the Generator B update mode is immediate (based on the GENBUPD field encoding in the PWMnCTL
register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are
used immediately. If the update mode is locally synchronized, these values are used the next time
the counter reaches zero. If the update mode is globally synchronized, these values are used the
next time the counter reaches zero after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register (see page 977). If this register is rewritten before the
actual update occurs, the previous value is never used and is lost.
PWM0 Generator B Control (PWM0GENB)
Base 0x4002.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
ACTCMPBD
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
9
8
ACTCMPBU
R/W
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
R/W
0
ACTCMPAD
R/W
0
R/W
0
ACTCMPAU
R/W
0
R/W
0
ACTLOAD
R/W
0
R/W
0
ACTZERO
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
May 24, 2010
1021
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
11:10
ACTCMPBD
R/W
0x0
Description
Action for Comparator B Down
This field specifies the action to be taken when the counter matches
comparator B while counting down.
Value Description
9:8
ACTCMPBU
R/W
0x0
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
Action for Comparator B Up
This field specifies the action to be taken when the counter matches
comparator B while counting up. This action can only occur when the
MODE bit in the PWMnCTL register is set.
Value Description
7:6
ACTCMPAD
R/W
0x0
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
Action for Comparator A Down
This field specifies the action to be taken when the counter matches
comparator A while counting down.
Value Description
5:4
ACTCMPAU
R/W
0x0
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
Action for Comparator A Up
This field specifies the action to be taken when the counter matches
comparator A while counting up. This action can only occur when the
MODE bit in the PWMnCTL register is set.
Value Description
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
1022
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
3:2
ACTLOAD
R/W
0x0
Description
Action for Counter=LOAD
This field specifies the action to be taken when the counter matches the
load value.
Value Description
1:0
ACTZERO
R/W
0x0
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
Action for Counter=0
This field specifies the action to be taken when the counter is 0.
Value Description
0x0
Do nothing.
0x1
Invert pwmB.
0x2
Drive pwmB Low.
0x3
Drive pwmB High.
May 24, 2010
1023
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 52: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068
Register 53: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8
Register 54: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8
Register 55: PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128
The PWMnDBCTL register controls the dead-band generator, which produces the PWMn signals
based on the pwmA and pwmB signals. When disabled, the pwmA signal passes through to the
pwmA' signal and the pwmB signal passes through to the pwmB' signal. When dead-band control
is enabled, the pwmB signal is ignored, the pwmA' signal is generated by delaying the rising edge(s)
of the pwmA signal by the value in the PWMnDBRISE register (see page 1025), and the pwmB' signal
is generated by inverting the pwmA signal and delaying the falling edge(s) of the pwmA signal by
the value in the PWMnDBFALL register (see page 1026). The Output Control block outputs the pwm0A'
signal on the PWM0 signal and the pwm0B' signal on the PWM1 signal. In a similar manner, PWM2
and PWM3 are produced from the pwm1A' and pwm1B' signals, PWM4 and PWM5 are produced from
the pwm2A' and pwm2B' signals, and PWM6 and PWM7 are produced from the pwm3A' and pwm3B'
signals.
If the Dead-Band Control mode is immediate (based on the DBCTLUPD field encoding in the
PWMnCTL register), the ENABLE bit value is used immediately. If the update mode is locally
synchronized, this value is used the next time the counter reaches zero. If the update mode is
globally synchronized, this value is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 977).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWM0 Dead-Band Control (PWM0DBCTL)
Base 0x4002.8000
Offset 0x068
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ENABLE
R/W
0
RO
0
ENABLE
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Generator Enable
Value Description
1
The dead-band generator modifies the pwmA signal by inserting
dead bands into the pwmA' and pwmB' signals.
0
The pwmA and pwmB signals pass through to the pwmA' and
pwmB' signals unmodified.
1024
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 56: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 57: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
Register 58: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset
0x0EC
Register 59: PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset
0x12C
The PWMnDBRISE register contains the number of clock cycles to delay the rising edge of the
pwmA signal when generating the pwmA' signal. If the dead-band generator is disabled through the
PWMnDBCTL register, this register is ignored. If the value of this register is larger than the width
of a High pulse on the pwmA signal, the rising-edge delay consumes the entire High time of the
signal, resulting in no High time on the output. Care must be taken to ensure that the pwmA High
time always exceeds the rising-edge delay.
If the Dead-Band Rising-Edge Delay mode is immediate (based on the DBRISEUPD field encoding
in the PWMnCTL register), the 12-bit RISEDELAY value is used immediately. If the update mode
is locally synchronized, this value is used the next time the counter reaches zero. If the update mode
is globally synchronized, this value is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 977).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)
Base 0x4002.8000
Offset 0x06C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RISEDELAY
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11:0
RISEDELAY
R/W
0x000
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Rise Delay
The number of clock cycles to delay the rising edge of pwmA' after the
rising edge of pwmA.
May 24, 2010
1025
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 60: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
Register 61: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset
0x0B0
Register 62: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset
0x0F0
Register 63: PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset
0x130
The PWMnDBFALL register contains the number of clock cycles to delay the rising edge of the
pwmB' signal from the falling edge of the pwmA signal. If the dead-band generator is disabled
through the PWMnDBCTL register, this register is ignored. If the value of this register is larger than
the width of a Low pulse on the pwmA signal, the falling-edge delay consumes the entire Low time
of the signal, resulting in no Low time on the output. Care must be taken to ensure that the pwmA
Low time always exceeds the falling-edge delay.
If the Dead-Band Falling-Edge-Delay mode is immediate (based on the DBFALLUP field encoding
in the PWMnCTL register), the 12-bit FALLDELAY value is used immediately. If the update mode
is locally synchronized, this value is used the next time the counter reaches zero. If the update mode
is globally synchronized, this value is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 977).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)
Base 0x4002.8000
Offset 0x070
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
FALLDELAY
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11:0
FALLDELAY
R/W
0x000
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Fall Delay
The number of clock cycles to delay the falling edge of pwmB' from the
rising edge of pwmA.
1026
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 64: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074
Register 65: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4
Register 66: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4
Register 67: PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134
This register specifies which fault pin inputs are used to generate a fault condition. Each bit in the
following register indicates whether the corresponding fault pin is included in the fault condition. All
enabled fault pins are ORed together to form the PWMnFLTSRC0 portion of the fault condition.
The PWMnFLTSRC0 fault condition is then ORed with the PWMnFLTSRC1 fault condition to
generate the final fault condition for the PWM generator.
If the FLTSRC bit in the PWMnCTL register (see page 1002) is clear, only the Fault0 signal affects
the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1
affect the fault condition generated.
PWM0 Fault Source 0 (PWM0FLTSRC0)
Base 0x4002.8000
Offset 0x074
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000
3
FAULT3
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault3 Input
Value Description
0
The Fault3 signal is suppressed and cannot generate a fault
condition.
1
The Fault3 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
May 24, 2010
1027
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
2
FAULT2
R/W
0
Description
Fault2 Input
Value Description
0
The Fault2 signal is suppressed and cannot generate a fault
condition.
1
The Fault2 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note:
1
FAULT1
R/W
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Fault1 Input
Value Description
0
The Fault1 signal is suppressed and cannot generate a fault
condition.
1
The Fault1 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note:
0
FAULT0
R/W
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Fault0 Input
Value Description
0
The Fault0 signal is suppressed and cannot generate a fault
condition.
1
The Fault0 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
1028
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 68: PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078
Register 69: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8
Register 70: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8
Register 71: PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138
This register specifies which digital comparator triggers from the ADC are used to generate a fault
condition. Each bit in the following register indicates whether the corresponding digital comparator
trigger is included in the fault condition. All enabled digital comparator triggers are ORed together
to form the PWMnFLTSRC1 portion of the fault condition. The PWMnFLTSRC1 fault condition is
then ORed with the PWMnFLTSRC0 fault condition to generate the final fault condition for the PWM
generator.
If the FLTSRC bit in the PWMnCTL register (see page 1002) is clear, only the PWM Fault0 pin affects
the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1
affect the fault condition generated.
PWM0 Fault Source 1 (PWM0FLTSRC1)
Base 0x4002.8000
Offset 0x078
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
DCMP7
R/W
0
RO
0
7
6
5
4
3
2
1
0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator 7
Value Description
0
The trigger from digital comparator 7 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 7 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
May 24, 2010
1029
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
6
DCMP6
R/W
0
Description
Digital Comparator 6
Value Description
0
The trigger from digital comparator 6 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 6 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
5
DCMP5
R/W
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 5
Value Description
0
The trigger from digital comparator 5 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 5 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
4
DCMP4
R/W
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 4
Value Description
0
The trigger from digital comparator 4 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 4 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
3
DCMP3
R/W
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 3
Value Description
0
The trigger from digital comparator 3 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 3 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
1030
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
2
DCMP2
R/W
0
Description
Digital Comparator 2
Value Description
0
The trigger from digital comparator 2 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 2 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
1
DCMP1
R/W
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 1
Value Description
0
The trigger from digital comparator 1 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 1 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
0
DCMP0
R/W
0
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Digital Comparator 0
Value Description
0
The trigger from digital comparator 0 is suppressed and cannot
generate a fault condition.
1
The trigger from digital comparator 0 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note:
The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
May 24, 2010
1031
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 72: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C
Register 73: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC
Register 74: PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC
Register 75: PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C
If the MINFLTPER bit in the PWMnCTL register is set, this register specifies the 16-bit time-extension
value to be used in extending the fault condition. The value is loaded into a 16-bit down counter,
and the counter value is used to extend the fault condition. The fault condition is released in the
clock immediately after the counter value reaches 0. The fault condition is asynchronous to the
PWM clock; and the delay value is the product of the PWM clock period and the (MFP field value
+ 1) or (MFP field value + 2) depending on when the fault condition asserts with respect to the PWM
clock. The counter decrements at the PWM clock rate, without pause or condition.
PWM0 Minimum Fault Period (PWM0MINFLTPER)
Base 0x4002.8000
Offset 0x07C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
MFP
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
R/W
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MFP
RO
0x0000
Minimum Fault Period
The number of PWM clocks by which a fault condition is extended when
the delay is enabled by PWMnCTL MINFLTPER.
1032
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 76: PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800
Register 77: PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880
Register 78: PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900
Register 79: PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980
This register defines the PWM fault pin logic sense.
PWM0 Fault Pin Logic Sense (PWM0FLTSEN)
Base 0x4002.8000
Offset 0x800
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
FAULT3
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault3 Sense
Value Description
2
FAULT2
R/W
0
0
An error is indicated if the Fault3 signal is High.
1
An error is indicated if the Fault3 signal is Low.
Fault2 Sense
Value Description
1
FAULT1
R/W
0
0
An error is indicated if the Fault2 signal is High.
1
An error is indicated if the Fault2 signal is Low.
Fault1 Sense
Value Description
0
FAULT0
R/W
0
0
An error is indicated if the Fault1 signal is High.
1
An error is indicated if the Fault1 signal is Low.
Fault0 Sense
Value Description
0
An error is indicated if the Fault0 signal is High.
1
An error is indicated if the Fault0 signal is Low.
May 24, 2010
1033
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 80: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804
Register 81: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884
Register 82: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904
Register 83: PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984
Along with the PWMnFLTSTAT1 register, this register provides status regarding the fault condition
inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT0 register
are read-only (RO) and provide the current state of the FAULTn inputs.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT0 register are
read / write 1 to clear (R/W1C) and provide a latched version of the FAULTn inputs. In this mode,
the register bits are cleared by writing a 1 to a set bit. The FAULTn inputs are recorded after their
sense is adjusted in the generator.
The contents of this register can only be written if the fault source extensions are enabled (the
FLTSRC bit in the PWMnCTL register is set).
PWM0 Fault Status 0 (PWM0FLTSTAT0)
Base 0x4002.8000
Offset 0x804
Type -, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
RO
0
RO
0
RO
0
RO
0
RO
0
0
0
0
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000
3
FAULT3
-
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Input 3
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the FAULT3 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is R/W1C and
represents a sticky version of the FAULT3 input signal after the logic
sense adjustment.
■
If FAULT3 is set, the input transitioned to the active state previously.
■
If FAULT3 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■
The FAULT3 bit is cleared by writing it with the value 1.
1034
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
Description
2
FAULT2
-
0
Fault Input 2
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the FAULT2 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is R/W1C and
represents a sticky version of the FAULT2 input signal after the logic
sense adjustment.
1
FAULT1
-
0
■
If FAULT2 is set, the input transitioned to the active state previously.
■
If FAULT2 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■
The FAULT2 bit is cleared by writing it with the value 1.
Fault Input 1
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the FAULT1 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is R/W1C and
represents a sticky version of the FAULT1 input signal after the logic
sense adjustment.
0
FAULT0
-
0
■
If FAULT1 is set, the input transitioned to the active state previously.
■
If FAULT1 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■
The FAULT1 bit is cleared by writing it with the value 1.
Fault Input 0
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the FAULT0 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is R/W1C and
represents a sticky version of the FAULT0 input signal after the logic
sense adjustment.
■
If FAULT0 is set, the input transitioned to the active state previously.
■
If FAULT0 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■
The FAULT0 bit is cleared by writing it with the value 1.
May 24, 2010
1035
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Register 84: PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808
Register 85: PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888
Register 86: PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908
Register 87: PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988
Along with the PWMnFLTSTAT0 register, this register provides status regarding the fault condition
inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT1 register
are read-only (RO) and provide the current state of the digital comparator triggers.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT1 register are
read / write 1 to clear (R/W1C) and provide a latched version of the digital comparator triggers. In
this mode, the register bits are cleared by writing a 1 to a set bit. The contents of this register can
only be written if the fault source extensions are enabled (the FLTSRC bit in the PWMnCTL register
is set).
PWM0 Fault Status 1 (PWM0FLTSTAT1)
Base 0x4002.8000
Offset 0x808
Type -, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
0
0
0
0
0
0
0
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
DCMP7
-
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator 7 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 7 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
■
If DCMP7 is set, the trigger transitioned to the active state previously.
■
If DCMP7 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP7 bit is cleared by writing it with the value 1.
1036
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
6
DCMP6
-
0
Description
Digital Comparator 6 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 6 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
5
DCMP5
-
0
■
If DCMP6 is set, the trigger transitioned to the active state previously.
■
If DCMP6 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP6 bit is cleared by writing it with the value 1.
Digital Comparator 5 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 5 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
4
DCMP4
-
0
■
If DCMP5 is set, the trigger transitioned to the active state previously.
■
If DCMP5 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP5 bit is cleared by writing it with the value 1.
Digital Comparator 4 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 4 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
3
DCMP3
-
0
■
If DCMP4 is set, the trigger transitioned to the active state previously.
■
If DCMP4 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP4 bit is cleared by writing it with the value 1.
Digital Comparator 3 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 3 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
■
If DCMP3 is set, the trigger transitioned to the active state previously.
■
If DCMP3 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP3 bit is cleared by writing it with the value 1.
May 24, 2010
1037
Texas Instruments-Advance Information
Pulse Width Modulator (PWM)
Bit/Field
Name
Type
Reset
2
DCMP2
-
0
Description
Digital Comparator 2 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 2 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
1
DCMP1
-
0
■
If DCMP2 is set, the trigger transitioned to the active state previously.
■
If DCMP2 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP2 bit is cleared by writing it with the value 1.
Digital Comparator 1 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 1 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
0
DCMP0
-
0
■
If DCMP1 is set, the trigger transitioned to the active state previously.
■
If DCMP1 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP1 bit is cleared by writing it with the value 1.
Digital Comparator 0 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 0 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
■
If DCMP0 is set, the trigger transitioned to the active state previously.
■
If DCMP0 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
■
The DCMP0 bit is cleared by writing it with the value 1.
1038
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
22
Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The LM3S5B91 microcontroller includes two quadrature encoder interface (QEI) modules. Each
QEI module interprets the code produced by a quadrature encoder wheel to integrate position over
time and determine direction of rotation. In addition, it can capture a running estimate of the velocity
of the encoder wheel.
®
The Stellaris LM3S5B91 microcontroller includes two QEI modules providing control of two motors
at the same time with the following features:
■ Position integrator that tracks the encoder position
■ Programmable noise filter on the inputs
■ Velocity capture using built-in timer
■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
■ Interrupt generation on:
– Index pulse
– Velocity-timer expiration
– Direction change
– Quadrature error detection
22.1
Block Diagram
®
Figure 22-1 on page 1040 provides a block diagram of a Stellaris QEI module.
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Quadrature Encoder Interface (QEI)
Figure 22-1. QEI Block Diagram
QEILOAD
Control & Status
Velocity Timer
QEITIME
QEICTL
QEISTAT
Velocity Accumulator
Velocity
Predivider
clk
PhA
PhB
QEICOUNT
QEISPEED
QEIMAXPOS
Quadrature
Encoder dir
Position Integrator
QEIPOS
IDX
QEIINTEN
Interrupt Control
Interrupt
QEIRIS
QEIISC
22.2
Signal Description
Table 22-1 on page 1040 and Table 22-2 on page 1041 list the external signals of the QEI module and
describe the function of each. The QEI signals are alternate functions for some GPIO signals and
default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment"
lists the possible GPIO pin placements for these QEI signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 323) should be set to choose the QEI function. The
number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO
Port Control (GPIOPCTL) register (page 341) to assign the QEI signal to the specified GPIO port
pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 298.
Table 22-1. Signals for QEI (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
IDX0
10
40
72
90
92
100
PD0 (3)
PG5 (4)
PB2 (2)
PB6 (5)
PB4 (6)
PD7 (1)
I
TTL
QEI module 0 index.
IDX1
17
61
84
PG2 (8)
PF1 (2)
PH2 (1)
I
TTL
QEI module 1 index.
PhA0
11
25
43
95
PD1 (3)
PC4 (2)
PF6 (4)
PE2 (4)
I
TTL
QEI module 0 phase A.
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 22-1. Signals for QEI (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PhA1
37
96
PG6 (1)
PE3 (3)
I
TTL
QEI module 1 phase A.
PhB0
22
23
42
47
83
96
PC7 (2)
PC6 (2)
PF7 (4)
PF0 (2)
PH3 (1)
PE3 (4)
I
TTL
QEI module 0 phase B.
PhB1
11
36
95
PD1 (11)
PG7 (1)
PE2 (3)
I
TTL
QEI module 1 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 22-2. Signals for QEI (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
IDX0
G1
M7
A11
A7
A6
A2
PD0 (3)
PG5 (4)
PB2 (2)
PB6 (5)
PB4 (6)
PD7 (1)
I
TTL
QEI module 0 index.
IDX1
J1
H12
D11
PG2 (8)
PF1 (2)
PH2 (1)
I
TTL
QEI module 1 index.
PhA0
G2
L1
M8
A4
PD1 (3)
PC4 (2)
PF6 (4)
PE2 (4)
I
TTL
QEI module 0 phase A.
PhA1
L7
B4
PG6 (1)
PE3 (3)
I
TTL
QEI module 1 phase A.
PhB0
L2
M2
K4
M9
D10
B4
PC7 (2)
PC6 (2)
PF7 (4)
PF0 (2)
PH3 (1)
PE3 (4)
I
TTL
QEI module 0 phase B.
PhB1
G2
C10
A4
PD1 (11)
PG7 (1)
PE2 (3)
I
TTL
QEI module 1 phase B.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
22.3
Functional Description
The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate
position over time and determine direction of rotation. In addition, it can capture a running estimate
of the velocity of the encoder wheel.
The position integrator and velocity capture can be independently enabled, though the position
integrator must be enabled before the velocity capture can be enabled. The two phase signals, PhA
and PhB, can be swapped before being interpreted by the QEI module to change the meaning of
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Quadrature Encoder Interface (QEI)
forward and backward and to correct for miswiring of the system. Alternatively, the phase signals
can be interpreted as a clock and direction signal as output by some encoders.
The QEI module input signals have a digital noise filter on them that can be enabled to prevent
spurious operation. The noise filter requires that the inputs be stable for a specified number of
consecutive clock cycles before updating the edge detector. The filter is enabled by the FILTEN bit
in the QEI Control (QEICTL) register. The frequency of the input update is programmable using
the FILTCNT bit field in the QEICTL register.
The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction
mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of
phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode,
the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction
of rotation. This mode is determined by the SIGMODE bit of the QEICTL register (see page 1046).
When the QEI module is set to use the quadrature phase mode (SIGMODE bit is clear), the capture
mode for the position integrator can be set to update the position counter on every edge of the PhA
signal or to update on every edge of both PhA and PhB. Updating the position counter on every PhA
and PhB edge provides more positional resolution at the cost of less range in the positional counter.
When edges on PhA lead edges on PhB, the position counter is incremented. When edges on PhB
lead edges on PhA, the position counter is decremented. When a rising and falling edge pair is seen
on one of the phases without any edges on the other, the direction of rotation has changed.
The positional counter is automatically reset on one of two conditions: sensing the index pulse or
reaching the maximum position value. The reset mode is determined by the RESMODE bit of the
QEICTL register.
When RESMODE is set, the positional counter is reset when the index pulse is sensed. This mode
limits the positional counter to the values [0:N-1], where N is the number of phase edges in a full
revolution of the encoder wheel. The QEI Maximum Position (QEIMAXPOS) register must be
programmed with N-1 so that the reverse direction from position 0 can move the position counter
to N-1. In this mode, the position register contains the absolute position of the encoder relative to
the index (or home) position once an index pulse has been seen.
When RESMODE is clear, the positional counter is constrained to the range [0:M], where M is the
programmable maximum value. The index pulse is ignored by the positional counter in this mode.
Velocity capture uses a configurable timer and a count register. The timer counts the number of
phase edges (using the same configuration as for the position integrator) in a given time period.
The edge count from the previous time period is available to the controller via the QEI Velocity
(QEISPEED) register, while the edge count for the current time period is being accumulated in the
QEI Velocity Counter (QEICOUNT) register. As soon as the current time period is complete, the
total number of edges counted in that time period is made available in the QEISPEED register
(overwriting the previous value), the QEICOUNT register is cleared, and counting commences on
a new time period. The number of edges counted in a given time period is directly proportional to
the velocity of the encoder.
®
Figure 22-2 on page 1043 shows how the Stellaris quadrature encoder converts the phase input
signals into clock pulses, the direction signal, and how the velocity predivider operates (in Divide
by 4 mode).
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Stellaris® LM3S5B91 Microcontroller
Figure 22-2. Quadrature Encoder and Velocity Predivider Operation
PhA
PhB
clk
clkdiv
dir
pos
rel
-1 -1 -1 -1 -1 -1 -1 -1 -1
+1
+1
+1
+1 +1 +1 +1 +1 +1 +1 +1
+1
+1
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+1
+1
+1
The period of the timer is configurable by specifying the load value for the timer in the QEI Timer
Load (QEILOAD) register. When the timer reaches zero, an interrupt can be triggered, and the
hardware reloads the timer with the QEILOAD value and continues to count down. At lower encoder
speeds, a longer timer period is required to be able to capture enough edges to have a meaningful
result. At higher encoder speeds, both a shorter timer period and/or the velocity predivider can be
used.
The following equation converts the velocity counter value into an rpm value:
rpm = (clock * (2 ^ VELDIV) * SPEED * 60) ÷ (LOAD * ppr * edges)
where:
clock is the controller clock rate
ppr is the number of pulses per revolution of the physical encoder
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CAPMODE clear and
4 for CAPMODE set)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder
is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of
÷1 (VELDIV is clear) and clocking on both PhA and PhB edges, this results in 81,920 pulses per
second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load
value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation:
rpm = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 rpm
Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second,
or 102,400 every ¼ of a second. Again, the above equation gives:
rpm = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 rpm
Care must be taken when evaluating this equation because intermediate values may exceed the
capacity of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500;
both could be predivided by 100 (at compile time if they are constants) and therefore be 100 and
25. In fact, if they were compile-time constants, they could also be reduced to a simple multiply by
4, cancelled by the ÷4 for the edge-count factor.
Important: Reducing constant factors at compile time is the best way to control the intermediate
values of this equation and reduce the processing requirement of computing this
equation.
The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a
simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses
per revolution, the load value can be a power of 2. For other encoders, a load value must be selected
such that the product is very close to a power of 2. For example, a 100 pulse-per-revolution encoder
May 24, 2010
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Quadrature Encoder Interface (QEI)
could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 214. In this
case a shift by 15 would be an adequate approximation of the divide in most cases. If absolute
accuracy were required, the microcontroller’s divide instruction could be used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.
22.4
Initialization and Configuration
The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:
1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System
Control module (see page 179).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module (see page 191).
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. To determine which GPIOs to configure, see Table 24-4 on page 1088.
4. Configure the PMCn fields in the GPIOPCTL register to assign the QEI signals to the appropriate
pins (see page 341 and Table 24-5 on page 1097).
5. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. A 1000-line encoder with four edges per line, results in
4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) as the count
is zero-based.
■ Write the QEICTL register with the value of 0x0000.0018.
■ Write the QEIMAXPOS register with the value of 0x0000.0F9F.
6. Enable the quadrature encoder by setting bit 0 of the QEICTL register.
7. Delay until the encoder position is required.
8. Read the encoder position by reading the QEI Position (QEIPOS) register value.
22.5
Register Map
Table 22-3 on page 1045 lists the QEI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the module’s base address:
■ QEI0: 0x4002.C000
■ QEI1: 0x4002.D000
Note that the QEI module clock must be enabled before the registers can be programmed (see
page 179).
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Stellaris® LM3S5B91 Microcontroller
Table 22-3. QEI Register Map
Offset
Name
Type
Reset
Description
See
page
0x000
QEICTL
R/W
0x0000.0000
QEI Control
1046
0x004
QEISTAT
RO
0x0000.0000
QEI Status
1049
0x008
QEIPOS
R/W
0x0000.0000
QEI Position
1050
0x00C
QEIMAXPOS
R/W
0x0000.0000
QEI Maximum Position
1051
0x010
QEILOAD
R/W
0x0000.0000
QEI Timer Load
1052
0x014
QEITIME
RO
0x0000.0000
QEI Timer
1053
0x018
QEICOUNT
RO
0x0000.0000
QEI Velocity Counter
1054
0x01C
QEISPEED
RO
0x0000.0000
QEI Velocity
1055
0x020
QEIINTEN
R/W
0x0000.0000
QEI Interrupt Enable
1056
0x024
QEIRIS
RO
0x0000.0000
QEI Raw Interrupt Status
1058
0x028
QEIISC
R/W1C
0x0000.0000
QEI Interrupt Status and Clear
1060
22.6
Register Descriptions
The remainder of this section lists and describes the QEI registers, in numerical order by address
offset.
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Quadrature Encoder Interface (QEI)
Register 1: QEI Control (QEICTL), offset 0x000
This register contains the configuration of the QEI module. Separate enables are provided for the
quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in
order to capture the velocity, but the velocity does not need to be captured in applications that do
not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset
mode, and velocity predivider are all set via this register.
QEI Control (QEICTL)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
FILTEN
STALLEN
R/W
0
R/W
0
25
24
23
22
21
20
19
18
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
10
9
8
7
6
5
4
3
2
1
0
INVI
INVB
INVA
SWAP
ENABLE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
17
16
FILTCNT
VELDIV
R/W
0
R/W
0
VELEN RESMODE CAPMODE SIGMODE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:16
FILTCNT
R/W
0x0
Input Filter Prescale Count
This field controls the frequency of the input update.
When this field is clear, the input is sampled after 2 system clocks. When
this field ix 0x1, the input is sampled after 3 system clocks. Similarly,
when this field is 0xF, the input is sampled after 17 clocks.
15:14
reserved
RO
0x0
13
FILTEN
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable Input Filter
Value Description
12
STALLEN
R/W
0
0
The QEI inputs are not filtered.
1
Enables the digital noise filter on the QEI input signals. Inputs
must be stable for 3 consecutive clock edges before the edge
detector is updated.
Stall QEI
Value Description
0
The QEI module does not stall when the microcontroller is
stopped by a debugger.
1
The QEI module stalls when the microcontroller is stopped by
a debugger.
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Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
11
INVI
R/W
0
Description
Invert Index Pulse
Value Description
10
INVB
R/W
0
0
No effect.
1
Inverts the IDX input.
Invert PhB
Value Description
9
INVA
R/W
0
0
No effect.
1
Inverts the PhB input.
Invert PhA
Value Description
8:6
VELDIV
R/W
0x0
0
No effect.
1
Inverts the PhA input.
Predivide Velocity
This field defines the predivider of the input quadrature pulses before
being applied to the QEICOUNT accumulator.
Value Predivider
5
VELEN
R/W
0
0x0
÷1
0x1
÷2
0x2
÷4
0x3
÷8
0x4
÷16
0x5
÷32
0x6
÷64
0x7
÷128
Capture Velocity
Value Description
4
RESMODE
R/W
0
0
No effect.
1
Enables capture of the velocity of the quadrature encoder.
Reset Mode
Value Description
0
The position counter is reset when it reaches the maximum as
defined by the MAXPOS field in the QEIMAXPOS register.
1
The position counter is reset when the index pulse is captured.
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Quadrature Encoder Interface (QEI)
Bit/Field
Name
Type
Reset
3
CAPMODE
R/W
0
Description
Capture Mode
Value Description
2
SIGMODE
R/W
0
0
Only the PhA edges are counted.
1
The PhA and PhB edges are counted, providing twice the
positional resolution but half the range.
Signal Mode
Value Description
1
SWAP
R/W
0
0
The PhA and PhB signals operate as quadrature phase signals.
1
The PhA and PhB signals operate as clock and direction.
Swap Signals
Value Description
0
ENABLE
R/W
0
0
No effect.
1
Swaps the PhA and PhB signals.
Enable QEI
Value Description
0
No effect.
1
Enables the quadrature encoder module.
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Stellaris® LM3S5B91 Microcontroller
Register 2: QEI Status (QEISTAT), offset 0x004
This register provides status about the operation of the QEI module.
QEI Status (QEISTAT)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
DIRECTION
ERROR
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
DIRECTION
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Direction of Rotation
Indicates the direction the encoder is rotating.
Value Description
0
ERROR
RO
0
0
The encoder is rotating forward.
1
The encoder is rotating in reverse.
Error Detected
Value Description
0
No error.
1
An error was detected in the gray code sequence (that is, both
signals changing at the same time).
May 24, 2010
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Quadrature Encoder Interface (QEI)
Register 3: QEI Position (QEIPOS), offset 0x008
This register contains the current value of the position integrator. The value is updated by the status
of the QEI phase inputs and can be set to a specific value by writing to it.
QEI Position (QEIPOS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
POSITION
Type
Reset
POSITION
Type
Reset
Bit/Field
Name
Type
31:0
POSITION
R/W
Reset
R/W
0
Description
0x0000.0000 Current Position Integrator Value
The current value of the position integrator.
1050
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C
This register contains the maximum value of the position integrator. When moving forward, the
position register resets to zero when it increments past this value. When moving in reverse, the
position register resets to this value when it decrements from zero.
QEI Maximum Position (QEIMAXPOS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MAXPOS
Type
Reset
MAXPOS
Type
Reset
Bit/Field
Name
Type
31:0
MAXPOS
R/W
Reset
Description
0x0000.0000 Maximum Position Integrator Value
The maximum value of the position integrator.
May 24, 2010
1051
Texas Instruments-Advance Information
Quadrature Encoder Interface (QEI)
Register 5: QEI Timer Load (QEILOAD), offset 0x010
This register contains the load value for the velocity timer. Because this value is loaded into the
timer on the clock cycle after the timer is zero, this value should be one less than the number of
clocks in the desired period. So, for example, to have 2000 decimal clocks per timer period, this
register should contain 1999 decimal.
QEI Timer Load (QEILOAD)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
LOAD
Type
Reset
LOAD
Type
Reset
Bit/Field
Name
Type
31:0
LOAD
R/W
Reset
Description
0x0000.0000 Velocity Timer Load Value
The load value for the velocity timer.
1052
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 6: QEI Timer (QEITIME), offset 0x014
This register contains the current value of the velocity timer. This counter does not increment when
the VELEN bit in the QEICTL register is clear.
QEI Timer (QEITIME)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
TIME
Type
Reset
TIME
Type
Reset
Bit/Field
Name
Type
31:0
TIME
RO
Reset
Description
0x0000.0000 Velocity Timer Current Value
The current value of the velocity timer.
May 24, 2010
1053
Texas Instruments-Advance Information
Quadrature Encoder Interface (QEI)
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018
This register contains the running count of velocity pulses for the current time period. Because this
count is a running total, the time period to which it applies cannot be known with precision (that is,
a read of this register does not necessarily correspond to the time returned by the QEITIME register
because there is a small window of time between the two reads, during which either value may have
changed). The QEISPEED register should be used to determine the actual encoder velocity; this
register is provided for information purposes only. This counter does not increment when the VELEN
bit in the QEICTL register is clear.
QEI Velocity Counter (QEICOUNT)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
COUNT
Type
Reset
COUNT
Type
Reset
Bit/Field
Name
Type
31:0
COUNT
RO
Reset
Description
0x0000.0000 Velocity Pulse Count
The running total of encoder pulses during this velocity timer period.
1054
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Register 8: QEI Velocity (QEISPEED), offset 0x01C
This register contains the most recently measured velocity of the quadrature encoder. This value
corresponds to the number of velocity pulses counted in the previous velocity timer period. This
register does not update when the VELEN bit in the QEICTL register is clear.
QEI Velocity (QEISPEED)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
SPEED
Type
Reset
SPEED
Type
Reset
Bit/Field
Name
Type
31:0
SPEED
RO
Reset
Description
0x0000.0000 Velocity
The measured speed of the quadrature encoder in pulses per period.
May 24, 2010
1055
Texas Instruments-Advance Information
Quadrature Encoder Interface (QEI)
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module interrupts. An interrupt is asserted to the
interrupt controller if the corresponding bit in this register is set.
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
INTERROR
INTDIR
INTTIMER
INTINDEX
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
INTERROR
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Interrupt Enable
Value Description
2
INTDIR
R/W
0
1
An interrupt is sent to the interrupt controller when the
INTERROR bit in the QEIRIS register is set.
0
The INTERROR interrupt is suppressed and not sent to the
interrupt controller.
Direction Change Interrupt Enable
Value Description
1
INTTIMER
R/W
0
1
An interrupt is sent to the interrupt controller when the INTDIR
bit in the QEIRIS register is set.
0
The INTDIR interrupt is suppressed and not sent to the interrupt
controller.
Timer Expires Interrupt Enable
Value Description
1
An interrupt is sent to the interrupt controller when the
INTTIMER bit in the QEIRIS register is set.
0
The INTTIMER interrupt is suppressed and not sent to the
interrupt controller.
1056
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
0
INTINDEX
R/W
0
Description
Index Pulse Detected Interrupt Enable
Value Description
1
An interrupt is sent to the interrupt controller when the
INTINDEX bit in the QEIRIS register is set.
0
The INTINDEX interrupt is suppressed and not sent to the
interrupt controller.
May 24, 2010
1057
Texas Instruments-Advance Information
Quadrature Encoder Interface (QEI)
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (configured through the QEIINTEN register).
If a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x024
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
INTERROR
INTDIR
INTTIMER
INTINDEX
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
INTERROR
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Detected
Value Description
1
A phase error has been detected.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTERROR bit in the QEIISC
register.
2
INTDIR
RO
0
Direction Change Detected
Value Description
1
The rotation direction has changed
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTDIR bit in the QEIISC register.
1
INTTIMER
RO
0
Velocity Timer Expired
Value Description
1
The velocity timer has expired.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTTIMER bit in the QEIISC
register.
1058
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
0
INTINDEX
RO
0
Description
Index Pulse Asserted
Value Description
1
The index pulse has occurred.
0
An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTINDEX bit in the QEIISC
register.
May 24, 2010
1059
Texas Instruments-Advance Information
Quadrature Encoder Interface (QEI)
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. If a bit
is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the
event in question has not occurred or is not enabled to generate an interrupt. This register is R/W1C;
writing a 1 to a bit position clears the bit and the corresponding interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x028
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
INTERROR
INTDIR
INTTIMER
INTINDEX
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3
INTERROR
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Interrupt
Value Description
1
The INTERROR bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTERROR bit in the QEIRIS register.
2
INTDIR
R/W1C
0
Direction Change Interrupt
Value Description
1
The INTDIR bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the INTDIR
bit in the QEIRIS register.
1
INTTIMER
R/W1C
0
Velocity Timer Expired Interrupt
Value Description
1
The INTTIMER bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTTIMER bit in the QEIRIS register.
1060
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Bit/Field
Name
Type
Reset
0
INTINDEX
R/W1C
0
Description
Index Pulse Interrupt
Value Description
1
The INTINDEX bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
0
No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTINDEX bit in the QEIRIS register.
May 24, 2010
1061
Texas Instruments-Advance Information
Pin Diagram
23
Pin Diagram
The LM3S5B91 microcontroller pin diagrams are shown below.
Each GPIO signal is identified by its GPIO port unless it defaults to an alternate function on reset.
In this case, the GPIO port name is followed by the default alternate function. To see a complete
list of possible functions for each pin, see Table 24-5 on page 1097.
Figure 23-1. 100-Pin LQFP Package Pin Diagram
1062
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Figure 23-2. 108-Ball BGA Package Pin Diagram (Top View)
May 24, 2010
1063
Texas Instruments-Advance Information
Signal Tables
24
Signal Tables
The following tables list the signals available for each pin. Signals are configured as GPIOs on reset,
except for those noted below. Use the GPIOAMSEL register (see page 339) to select analog mode.
For a GPIO pin to be used for an alternate digital function, the corresponding bit in the GPIOAFSEL
register (see page 323) must be set. Further pin muxing options are provided through the PMCx bit
field in the GPIOPCTL register (see page 341), which selects one of several available peripheral
functions for that GPIO.
Important: All GPIO pins are configured as GPIOs by default with the exception of the pins shown
in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their
default state.
Table 24-1. GPIO Pins With Default Alternate Functions
GPIO Pin
Default State
GPIOAFSEL Bit
GPIOPCTL PMCx Bit Field
PA[1:0]
UART0
1
0x1
PA[5:2]
SSI0
1
0x1
PB[3:2]
I2C0
1
0x1
PC[3:0]
JTAG/SWD
1
0x3
Table 24-2 on page 1065 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Each possible alternate analog and digital function is listed for each pin.
Table 24-3 on page 1077 lists the signals in alphabetical order by signal name. If it is possible for a
signal to be on multiple pins, each possible pin assignment is listed. The "Pin Mux" column indicates
the GPIO and the encoding needed in the PMCx bit field in the GPIOPCTL register.
Table 24-4 on page 1088 groups the signals by functionality, except for GPIOs. If it is possible for a
signal to be on multiple pins, each possible pin assignment is listed.
Table 24-5 on page 1097 lists the GPIO pins and their analog and digital alternate functions. The AINx
and VREFA analog signals are not 5-V tolerant and go through an isolation circuit before reaching
their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital
Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode
Select (GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to
their circuitry (C0-, C0+, C1-, C1+, C2-, C2+, USB0VBUS, USB0ID). These signals are configured
by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. The digital signals are
enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and
GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL)
register to the numeric enoding shown in the table below. Table entries that are shaded gray are
the default values for the corresponding GPIO pin.
Table 24-6 on page 1100 lists the signals based on number of possible pin assignments. This table
can be used to plan how to configure the pins for a particular functionality. Application Note AN01274
Configuring Stellaris® Microcontrollers with Pin Multiplexing provides an overview of the pin muxing
implementation, an explanation of how a system designer defines a pin configuration, and examples
of the pin configuration process.
1064
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
24.1
100-Pin LQFP Package Pin Tables
Table 24-2. Signals by Pin Number
a
Pin Number
Pin Name
Pin Type
Buffer Type
1
PE7
I/O
TTL
AIN0
I
Analog
C2o
O
TTL
Analog comparator 2 output.
2
Description
GPIO port E bit 7.
Analog-to-digital converter input 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
PE6
I/O
TTL
GPIO port E bit 6.
AIN1
I
Analog
C1o
O
TTL
Analog comparator 1 output.
Analog-to-digital converter input 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
U1CTS
I
TTL
UART module 1 Clear To Send modem status input signal.
3
VDDA
-
Power
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
4
GNDA
-
Power
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
5
6
PE5
I/O
TTL
AIN2
I
Analog
GPIO port E bit 5.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
I2S0TXSD
I/O
TTL
I2S module 0 transmit data.
PE4
I/O
TTL
GPIO port E bit 4.
AIN3
I
Analog
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
Analog-to-digital converter input 2.
Analog-to-digital converter input 3.
Fault0
I
TTL
PWM Fault 0.
I2S0TXWS
I/O
TTL
I2S module 0 transmit word select.
U2Tx
O
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
7
LDO
-
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the logic, the LDO pin
must also be connected to the VDDC pins at the board level in
addition to the decoupling capacitor(s).
8
VDD
-
Power
Positive supply for I/O and some logic.
9
GND
-
Power
Ground reference for logic and I/O pins.
May 24, 2010
1065
Texas Instruments-Advance Information
Signal Tables
Table 24-2. Signals by Pin Number (continued)
Pin Number
10
11
12
13
Pin Name
Pin Type
a
Buffer Type
Description
PD0
I/O
TTL
AIN15
I
Analog
GPIO port D bit 0.
CAN0Rx
I
TTL
CAN module 0 receive.
Analog-to-digital converter input 15.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
I2S0RXSCK
I/O
TTL
I2S module 0 receive clock.
IDX0
I
TTL
QEI module 0 index.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
U1CTS
I
TTL
UART module 1 Clear To Send modem status input signal.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
GPIO port D bit 1.
PD1
I/O
TTL
AIN14
I
Analog
CAN0Tx
O
TTL
CAN module 0 transmit.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
I2S0RXWS
I/O
TTL
I2S module 0 receive word select.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PhA0
I
TTL
QEI module 0 phase A.
Analog-to-digital converter input 14.
PhB1
I
TTL
QEI module 1 phase B.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
U2Tx
O
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
PD2
I/O
TTL
GPIO port D bit 2.
AIN13
I
Analog
CCP5
I/O
TTL
Capture/Compare/PWM 5.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S20
I/O
TTL
EPI module 0 signal 20.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
GPIO port D bit 3.
Analog-to-digital converter input 13.
PD3
I/O
TTL
AIN12
I
Analog
CCP0
I/O
TTL
Capture/Compare/PWM 0.
Analog-to-digital converter input 12.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
EPI0S21
I/O
TTL
EPI module 0 signal 21.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
1066
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-2. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
Buffer Type
14
EPI0S16
I/O
TTL
EPI module 0 signal 16.
I2C1SCL
I/O
OD
I2C module 1 clock.
PJ0
I/O
TTL
GPIO port J bit 0.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PH7
I/O
TTL
GPIO port H bit 7.
EPI0S27
I/O
TTL
EPI module 0 signal 27.
15
16
17
Description
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
SSI1Tx
O
TTL
SSI module 1 transmit.
PG3
I/O
TTL
GPIO port G bit 3.
Fault0
I
TTL
PWM Fault 0.
Fault2
I
TTL
PWM Fault 2.
I2S0RXMCLK
I/O
TTL
I2S module 0 receive master clock.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PG2
I/O
TTL
GPIO port G bit 2.
Fault0
I
TTL
PWM Fault 0.
I2S0RXSD
I/O
TTL
I2S module 0 receive data.
IDX1
I
TTL
QEI module 1 index.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PG1
I/O
TTL
GPIO port G bit 1.
EPI0S14
I/O
TTL
EPI module 0 signal 14.
I2C1SDA
I/O
OD
I2C module 1 data.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
U2Tx
O
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
PG0
I/O
TTL
GPIO port G bit 0.
EPI0S13
I/O
TTL
EPI module 0 signal 13.
I2C1SCL
I/O
OD
I2C module 1 clock.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
20
VDD
-
Power
Positive supply for I/O and some logic.
21
GND
-
Power
Ground reference for logic and I/O pins.
18
19
May 24, 2010
1067
Texas Instruments-Advance Information
Signal Tables
Table 24-2. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
Buffer Type
22
PC7
I/O
TTL
GPIO port C bit 7.
C1o
O
TTL
Analog comparator 1 output.
C2-
I
Analog
CCP0
I/O
TTL
Capture/Compare/PWM 0.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S5
I/O
TTL
EPI module 0 signal 5.
PhB0
I
TTL
QEI module 0 phase B.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PC6
I/O
TTL
GPIO port C bit 6.
C2+
I
Analog
C2o
O
TTL
Analog comparator 2 output.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
23
24
25
Description
Analog comparator 2 negative input.
Analog comparator 2 positive input.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S4
I/O
TTL
EPI module 0 signal 4.
PWM7
O
TTL
PWM 7. This signal is controlled by PWM Generator 3.
PhB0
I
TTL
QEI module 0 phase B.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PC5
I/O
TTL
GPIO port C bit 5.
C0o
O
TTL
Analog comparator 0 output.
C1+
I
Analog
C1o
O
TTL
Analog comparator 1 output.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S3
I/O
TTL
EPI module 0 signal 3.
Fault2
I
TTL
PWM Fault 2.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
PC4
I/O
TTL
GPIO port C bit 4.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
Analog comparator 1 positive input.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
EPI0S2
I/O
TTL
EPI module 0 signal 2.
PWM6
O
TTL
PWM 6. This signal is controlled by PWM Generator 3.
PhA0
I
TTL
QEI module 0 phase A.
1068
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-2. Signals by Pin Number (continued)
Pin Number
26
27
28
29
30
31
a
Pin Name
Pin Type
Buffer Type
Description
PA0
I/O
TTL
GPIO port A bit 0.
I2C1SCL
I/O
OD
I2C module 1 clock.
U0Rx
I
TTL
UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
PA1
I/O
TTL
GPIO port A bit 1.
I2C1SDA
I/O
OD
I2C module 1 data.
U0Tx
O
TTL
UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
PA2
I/O
TTL
GPIO port A bit 2.
I2S0RXSD
I/O
TTL
I2S module 0 receive data.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
SSI0Clk
I/O
TTL
SSI module 0 clock.
PA3
I/O
TTL
GPIO port A bit 3.
I2S0RXMCLK
I/O
TTL
I2S module 0 receive master clock.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
SSI0Fss
I/O
TTL
SSI module 0 frame.
PA4
I/O
TTL
GPIO port A bit 4.
CAN0Rx
I
TTL
CAN module 0 receive.
I2S0TXSCK
I/O
TTL
I2S module 0 transmit clock.
PWM6
O
TTL
PWM 6. This signal is controlled by PWM Generator 3.
SSI0Rx
I
TTL
SSI module 0 receive.
PA5
I/O
TTL
GPIO port A bit 5.
CAN0Tx
O
TTL
CAN module 0 transmit.
I2S0TXWS
I/O
TTL
I2S module 0 transmit word select.
PWM7
O
TTL
PWM 7. This signal is controlled by PWM Generator 3.
SSI0Tx
O
TTL
SSI module 0 transmit.
32
VDD
-
Power
Positive supply for I/O and some logic.
33
GND
-
Power
Ground reference for logic and I/O pins.
34
PA6
I/O
TTL
GPIO port A bit 6.
CAN0Rx
I
TTL
CAN module 0 receive.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
I2C1SCL
I/O
OD
I2C module 1 clock.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
U1CTS
I
TTL
UART module 1 Clear To Send modem status input signal.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
May 24, 2010
1069
Texas Instruments-Advance Information
Signal Tables
Table 24-2. Signals by Pin Number (continued)
Pin Number
35
36
37
38
39
40
41
a
Pin Name
Pin Type
Buffer Type
Description
PA7
I/O
TTL
GPIO port A bit 7.
CAN0Tx
O
TTL
CAN module 0 transmit.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
I2C1SDA
I/O
OD
I2C module 1 data.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PG7
I/O
TTL
GPIO port G bit 7.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
EPI0S31
I/O
TTL
EPI module 0 signal 31.
PWM7
O
TTL
PWM 7. This signal is controlled by PWM Generator 3.
PhB1
I
TTL
QEI module 1 phase B.
PG6
I/O
TTL
GPIO port G bit 6.
Fault1
I
TTL
PWM Fault 1.
I2S0RXWS
I/O
TTL
I2S module 0 receive word select.
PWM6
O
TTL
PWM 6. This signal is controlled by PWM Generator 3.
PhA1
I
TTL
QEI module 1 phase A.
U1RI
I
TTL
UART module 1 Ring Indicator modem status input signal.
VDDC
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
EPI0S18
I/O
TTL
EPI module 0 signal 18.
Fault0
I
TTL
PWM Fault 0.
PJ2
I/O
TTL
GPIO port J bit 2.
PG5
I/O
TTL
GPIO port G bit 5.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
Fault1
I
TTL
PWM Fault 1.
I2S0RXSCK
I/O
TTL
I2S module 0 receive clock.
IDX0
I
TTL
QEI module 0 index.
PWM7
O
TTL
PWM 7. This signal is controlled by PWM Generator 3.
U1DTR
O
TTL
UART module 1 Data Terminal Ready modem status input signal.
PG4
I/O
TTL
GPIO port G bit 4.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S15
I/O
TTL
EPI module 0 signal 15.
Fault1
I
TTL
PWM Fault 1.
PWM6
O
TTL
PWM 6. This signal is controlled by PWM Generator 3.
U1RI
I
TTL
UART module 1 Ring Indicator modem status input signal.
1070
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-2. Signals by Pin Number (continued)
Pin Number
42
a
Pin Name
Pin Type
Buffer Type
Description
PF7
I/O
TTL
GPIO port F bit 7.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S12
I/O
TTL
EPI module 0 signal 12.
Fault1
I
TTL
PWM Fault 1.
PhB0
I
TTL
QEI module 0 phase B.
PF6
I/O
TTL
GPIO port F bit 6.
C2o
O
TTL
Analog comparator 2 output.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
I2S0TXMCLK
I/O
TTL
I2S module 0 transmit master clock.
PhA0
I
TTL
QEI module 0 phase A.
U1RTS
O
TTL
UART module 1 Request to Send modem output control line.
44
VDD
-
Power
Positive supply for I/O and some logic.
45
GND
-
Power
Ground reference for logic and I/O pins.
46
PF5
I/O
TTL
GPIO port F bit 5.
C1o
O
TTL
Analog comparator 1 output.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
EPI0S15
I/O
TTL
EPI module 0 signal 15.
SSI1Tx
O
TTL
SSI module 1 transmit.
43
47
PF0
I/O
TTL
GPIO port F bit 0.
CAN1Rx
I
TTL
CAN module 1 receive.
I2S0TXSD
I/O
TTL
I2S module 0 transmit data.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PhB0
I
TTL
QEI module 0 phase B.
U1DSR
I
TTL
UART module 1 Data Set Ready modem output control line.
48
OSC0
I
Analog
Main oscillator crystal input or an external clock reference input.
49
OSC1
O
Analog
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
50
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S19
I/O
TTL
EPI module 0 signal 19.
PJ3
I/O
TTL
GPIO port J bit 3.
U1CTS
I
TTL
UART module 1 Clear To Send modem status input signal.
51
NC
-
-
52
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S28
I/O
TTL
EPI module 0 signal 28.
PJ4
I/O
TTL
GPIO port J bit 4.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
53
No connect. Leave the pin electrically unconnected/isolated.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
EPI0S29
I/O
TTL
EPI module 0 signal 29.
PJ5
I/O
TTL
GPIO port J bit 5.
U1DSR
I
TTL
UART module 1 Data Set Ready modem output control line.
May 24, 2010
1071
Texas Instruments-Advance Information
Signal Tables
Table 24-2. Signals by Pin Number (continued)
Pin Number
54
55
a
Pin Name
Pin Type
Buffer Type
Description
CCP1
I/O
TTL
Capture/Compare/PWM 1.
EPI0S30
I/O
TTL
EPI module 0 signal 30.
PJ6
I/O
TTL
GPIO port J bit 6.
U1RTS
O
TTL
UART module 1 Request to Send modem output control line.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
PJ7
I/O
TTL
GPIO port J bit 7.
U1DTR
O
TTL
UART module 1 Data Terminal Ready modem status input signal.
56
VDD
-
Power
Positive supply for I/O and some logic.
57
GND
-
Power
Ground reference for logic and I/O pins.
58
PF4
I/O
TTL
GPIO port F bit 4.
59
60
61
62
63
64
C0o
O
TTL
Analog comparator 0 output.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
EPI0S12
I/O
TTL
EPI module 0 signal 12.
Fault0
I
TTL
PWM Fault 0.
SSI1Rx
I
TTL
SSI module 1 receive.
PF3
I/O
TTL
GPIO port F bit 3.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
SSI1Fss
I/O
TTL
SSI module 1 frame.
PF2
I/O
TTL
GPIO port F bit 2.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
SSI1Clk
I/O
TTL
SSI module 1 clock.
PF1
I/O
TTL
GPIO port F bit 1.
CAN1Tx
O
TTL
CAN module 1 transmit.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
I2S0TXMCLK
I/O
TTL
I2S module 0 transmit master clock.
IDX1
I
TTL
QEI module 1 index.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
U1RTS
O
TTL
UART module 1 Request to Send modem output control line.
PH6
I/O
TTL
GPIO port H bit 6.
EPI0S26
I/O
TTL
EPI module 0 signal 26.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
SSI1Rx
I
TTL
SSI module 1 receive.
PH5
I/O
TTL
GPIO port H bit 5.
EPI0S11
I/O
TTL
EPI module 0 signal 11.
Fault2
I
TTL
PWM Fault 2.
SSI1Fss
I/O
TTL
SSI module 1 frame.
RST
I
TTL
System reset input.
1072
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-2. Signals by Pin Number (continued)
Pin Number
65
a
Pin Name
Pin Type
Buffer Type
Description
PB3
I/O
TTL
GPIO port B bit 3.
Fault0
I
TTL
PWM Fault 0.
Fault3
I
TTL
PWM Fault 3.
I2C0SDA
I/O
OD
I2C module 0 data.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PB0
I/O
TTL
GPIO port B bit 0.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
USB0ID
I
Analog
This signal senses the state of the USB ID signal. The USB PHY
enables an integrated pull-up, and an external element (USB
connector) indicates the initial state of the USB controller (pulled
down is the A side of the cable and pulled up is the B side).
PB1
I/O
TTL
GPIO port B bit 1.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
USB0VBUS
I/O
Analog
This signal is used during the session request protocol. This signal
allows the USB PHY to both sense the voltage level of VBUS, and
pull up VBUS momentarily during VBUS pulsing.
68
VDD
-
Power
Positive supply for I/O and some logic.
69
GND
-
Power
Ground reference for logic and I/O pins.
70
USB0DM
I/O
Analog
Bidirectional differential data pin (D- per USB specification).
71
USB0DP
I/O
Analog
Bidirectional differential data pin (D+ per USB specification).
66
67
72
PB2
I/O
TTL
GPIO port B bit 2.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
I2C0SCL
I/O
OD
I2C module 0 clock.
IDX0
I
TTL
QEI module 0 index.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
73
USB0RBIAS
O
Analog
74
PE0
I/O
TTL
GPIO port E bit 0.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S8
I/O
TTL
EPI module 0 signal 8.
9.1-kΩ resistor (1% precision) used internally for USB analog
circuitry.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
SSI1Clk
I/O
TTL
SSI module 1 clock.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
May 24, 2010
1073
Texas Instruments-Advance Information
Signal Tables
Table 24-2. Signals by Pin Number (continued)
Pin Number
75
76
77
78
79
80
a
Pin Name
Pin Type
Buffer Type
Description
PE1
I/O
TTL
GPIO port E bit 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S9
I/O
TTL
EPI module 0 signal 9.
Fault0
I
TTL
PWM Fault 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
SSI1Fss
I/O
TTL
SSI module 1 frame.
PH4
I/O
TTL
GPIO port H bit 4.
EPI0S10
I/O
TTL
EPI module 0 signal 10.
SSI1Clk
I/O
TTL
SSI module 1 clock.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PC3
I/O
TTL
GPIO port C bit 3.
SWO
O
TTL
JTAG TDO and SWO.
TDO
O
TTL
JTAG TDO and SWO.
PC2
I/O
TTL
GPIO port C bit 2.
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I
TTL
JTAG TMS and SWDIO.
PC0
I/O
TTL
GPIO port C bit 0.
SWCLK
I
TTL
JTAG/SWD CLK.
TCK
I
TTL
JTAG/SWD CLK.
81
VDD
-
Power
Positive supply for I/O and some logic.
82
GND
-
Power
Ground reference for logic and I/O pins.
83
84
85
PH3
I/O
TTL
GPIO port H bit 3.
EPI0S0
I/O
TTL
EPI module 0 signal 0.
Fault0
I
TTL
PWM Fault 0.
PhB0
I
TTL
QEI module 0 phase B.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
PH2
I/O
TTL
GPIO port H bit 2.
C1o
O
TTL
Analog comparator 1 output.
EPI0S1
I/O
TTL
EPI module 0 signal 1.
Fault3
I
TTL
PWM Fault 3.
IDX1
I
TTL
QEI module 1 index.
PH1
I/O
TTL
GPIO port H bit 1.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
EPI0S7
I/O
TTL
EPI module 0 signal 7.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
1074
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-2. Signals by Pin Number (continued)
Pin Number
86
87
a
Pin Name
Pin Type
Buffer Type
Description
PH0
I/O
TTL
GPIO port H bit 0.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S6
I/O
TTL
EPI module 0 signal 6.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
EPI0S17
I/O
TTL
EPI module 0 signal 17.
I2C1SDA
I/O
OD
I2C module 1 data.
PJ1
I/O
TTL
GPIO port J bit 1.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
88
VDDC
-
Power
89
PB7
I/O
TTL
GPIO port B bit 7.
NMI
I
TTL
Non-maskable interrupt.
PB6
I/O
TTL
GPIO port B bit 6.
C0+
I
Analog
90
91
Positive supply for most of the logic function, including the
processor core and most peripherals.
Analog comparator 0 positive input.
C0o
O
TTL
Analog comparator 0 output.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
Fault1
I
TTL
PWM Fault 1.
I2S0TXSCK
I/O
TTL
I2S module 0 transmit clock.
QEI module 0 index.
IDX0
I
TTL
VREFA
I
Analog
PB5
I/O
TTL
AIN11
I
Analog
C0o
O
TTL
This input provides a reference voltage used to specify the input
voltage at which the ADC converts to a maximum value. In other
words, the voltage that is applied to VREFA is the voltage with which
an AINn signal is converted to 1023. The VREFA input is limited
to the range specified in Table 26-2 on page 1142.
GPIO port B bit 5.
Analog-to-digital converter input 11.
Analog comparator 0 output.
C1-
I
Analog
CAN0Tx
O
TTL
Analog comparator 1 negative input.
CAN module 0 transmit.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S22
I/O
TTL
EPI module 0 signal 22.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
May 24, 2010
1075
Texas Instruments-Advance Information
Signal Tables
Table 24-2. Signals by Pin Number (continued)
Pin Number
92
Pin Name
Pin Type
a
Buffer Type
Description
PB4
I/O
TTL
AIN10
I
Analog
GPIO port B bit 4.
Analog-to-digital converter input 10.
C0-
I
Analog
Analog comparator 0 negative input.
CAN0Rx
I
TTL
CAN module 0 receive.
EPI0S23
I/O
TTL
EPI module 0 signal 23.
IDX0
I
TTL
QEI module 0 index.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
93
VDD
-
Power
Positive supply for I/O and some logic.
94
GND
-
Power
Ground reference for logic and I/O pins.
95
96
97
PE2
I/O
TTL
AIN9
I
Analog
GPIO port E bit 2.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
Analog-to-digital converter input 9.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S24
I/O
TTL
EPI module 0 signal 24.
PhA0
I
TTL
QEI module 0 phase A.
PhB1
I
TTL
QEI module 1 phase B.
SSI1Rx
I
TTL
SSI module 1 receive.
GPIO port E bit 3.
PE3
I/O
TTL
AIN8
I
Analog
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
EPI0S25
I/O
TTL
EPI module 0 signal 25.
PhA1
I
TTL
QEI module 1 phase A.
PhB0
I
TTL
QEI module 0 phase B.
SSI1Tx
O
TTL
SSI module 1 transmit.
PD4
I/O
TTL
GPIO port D bit 4.
AIN7
I
Analog
CCP0
I/O
TTL
Capture/Compare/PWM 0.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S19
I/O
TTL
EPI module 0 signal 19.
I2S0RXSD
I/O
TTL
I2S module 0 receive data.
U1RI
I
TTL
UART module 1 Ring Indicator modem status input signal.
Analog-to-digital converter input 8.
Analog-to-digital converter input 7.
1076
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-2. Signals by Pin Number (continued)
Pin Number
98
99
100
Pin Name
Pin Type
a
Buffer Type
Description
PD5
I/O
TTL
AIN6
I
Analog
GPIO port D bit 5.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
Analog-to-digital converter input 6.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S28
I/O
TTL
EPI module 0 signal 28.
I2S0RXMCLK
I/O
TTL
I2S module 0 receive master clock.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
GPIO port D bit 6.
PD6
I/O
TTL
AIN5
I
Analog
EPI0S29
I/O
TTL
EPI module 0 signal 29.
Fault0
I
TTL
PWM Fault 0.
I2S0TXSCK
I/O
TTL
I2S module 0 transmit clock.
U2Tx
O
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
GPIO port D bit 7.
Analog-to-digital converter input 5.
PD7
I/O
TTL
AIN4
I
Analog
C0o
O
TTL
Analog comparator 0 output.
Analog-to-digital converter input 4.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
EPI0S30
I/O
TTL
EPI module 0 signal 30.
I2S0TXWS
I/O
TTL
I2S module 0 transmit word select.
IDX0
I
TTL
QEI module 0 index.
U1DTR
O
TTL
UART module 1 Data Terminal Ready modem status input signal.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 24-3. Signals by Signal Name
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
AIN0
1
PE7
I
Analog
Analog-to-digital converter input 0.
AIN1
2
PE6
I
Analog
Analog-to-digital converter input 1.
AIN2
5
PE5
I
Analog
Analog-to-digital converter input 2.
AIN3
6
PE4
I
Analog
Analog-to-digital converter input 3.
AIN4
100
PD7
I
Analog
Analog-to-digital converter input 4.
AIN5
99
PD6
I
Analog
Analog-to-digital converter input 5.
AIN6
98
PD5
I
Analog
Analog-to-digital converter input 6.
AIN7
97
PD4
I
Analog
Analog-to-digital converter input 7.
AIN8
96
PE3
I
Analog
Analog-to-digital converter input 8.
AIN9
95
PE2
I
Analog
Analog-to-digital converter input 9.
AIN10
92
PB4
I
Analog
Analog-to-digital converter input 10.
AIN11
91
PB5
I
Analog
Analog-to-digital converter input 11.
AIN12
13
PD3
I
Analog
Analog-to-digital converter input 12.
AIN13
12
PD2
I
Analog
Analog-to-digital converter input 13.
May 24, 2010
1077
Texas Instruments-Advance Information
Signal Tables
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
AIN14
11
PD1
I
Analog
Analog-to-digital converter input 14.
AIN15
10
PD0
I
Analog
Analog-to-digital converter input 15.
C0+
90
PB6
I
Analog
Analog comparator 0 positive input.
C0-
92
PB4
I
Analog
Analog comparator 0 negative input.
C0o
24
58
90
91
100
PC5 (3)
PF4 (2)
PB6 (3)
PB5 (1)
PD7 (2)
O
TTL
C1+
24
PC5
I
Analog
Analog comparator 1 positive input.
C1-
91
PB5
I
Analog
Analog comparator 1 negative input.
C1o
2
22
24
46
84
PE6 (2)
PC7 (7)
PC5 (2)
PF5 (2)
PH2 (2)
O
TTL
C2+
23
PC6
I
Analog
Analog comparator 2 positive input.
C2-
22
PC7
I
Analog
Analog comparator 2 negative input.
C2o
1
23
43
PE7 (2)
PC6 (3)
PF6 (2)
O
TTL
Analog comparator 2 output.
CAN0Rx
10
30
34
92
PD0 (2)
PA4 (5)
PA6 (6)
PB4 (5)
I
TTL
CAN module 0 receive.
CAN0Tx
11
31
35
91
PD1 (2)
PA5 (5)
PA7 (6)
PB5 (5)
O
TTL
CAN module 0 transmit.
CAN1Rx
47
PF0 (1)
I
TTL
CAN module 1 receive.
CAN1Tx
61
PF1 (1)
O
TTL
CAN module 1 transmit.
CCP0
13
22
23
39
55
58
66
72
91
97
PD3 (4)
PC7 (4)
PC6 (6)
PJ2 (9)
PJ7 (10)
PF4 (1)
PB0 (1)
PB2 (5)
PB5 (4)
PD4 (1)
I/O
TTL
Capture/Compare/PWM 0.
CCP1
24
25
34
43
54
67
90
96
100
PC5 (1)
PC4 (9)
PA6 (2)
PF6 (1)
PJ6 (10)
PB1 (4)
PB6 (1)
PE3 (1)
PD7 (3)
I/O
TTL
Capture/Compare/PWM 1.
Analog comparator 0 output.
Analog comparator 1 output.
1078
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CCP2
6
11
25
46
53
67
75
91
95
98
PE4 (6)
PD1 (10)
PC4 (5)
PF5 (1)
PJ5 (10)
PB1 (1)
PE1 (4)
PB5 (6)
PE2 (5)
PD5 (1)
I/O
TTL
Capture/Compare/PWM 2.
CCP3
6
23
24
35
41
61
72
74
97
PE4 (1)
PC6 (1)
PC5 (5)
PA7 (7)
PG4 (1)
PF1 (10)
PB2 (4)
PE0 (3)
PD4 (2)
I/O
TTL
Capture/Compare/PWM 3.
CCP4
22
25
35
42
52
95
98
PC7 (1)
PC4 (6)
PA7 (2)
PF7 (1)
PJ4 (10)
PE2 (1)
PD5 (2)
I/O
TTL
Capture/Compare/PWM 4.
CCP5
5
12
25
36
40
90
91
PE5 (1)
PD2 (4)
PC4 (1)
PG7 (8)
PG5 (1)
PB6 (6)
PB5 (2)
I/O
TTL
Capture/Compare/PWM 5.
CCP6
10
12
50
75
86
91
PD0 (6)
PD2 (2)
PJ3 (10)
PE1 (5)
PH0 (1)
PB5 (3)
I/O
TTL
Capture/Compare/PWM 6.
CCP7
11
13
85
90
96
PD1 (6)
PD3 (2)
PH1 (1)
PB6 (2)
PE3 (5)
I/O
TTL
Capture/Compare/PWM 7.
EPI0S0
83
PH3 (8)
I/O
TTL
EPI module 0 signal 0.
EPI0S1
84
PH2 (8)
I/O
TTL
EPI module 0 signal 1.
EPI0S2
25
PC4 (8)
I/O
TTL
EPI module 0 signal 2.
EPI0S3
24
PC5 (8)
I/O
TTL
EPI module 0 signal 3.
EPI0S4
23
PC6 (8)
I/O
TTL
EPI module 0 signal 4.
EPI0S5
22
PC7 (8)
I/O
TTL
EPI module 0 signal 5.
EPI0S6
86
PH0 (8)
I/O
TTL
EPI module 0 signal 6.
EPI0S7
85
PH1 (8)
I/O
TTL
EPI module 0 signal 7.
May 24, 2010
1079
Texas Instruments-Advance Information
Signal Tables
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
EPI0S8
74
a
Pin Type
Buffer Type
Description
PE0 (8)
I/O
TTL
EPI module 0 signal 8.
EPI0S9
75
PE1 (8)
I/O
TTL
EPI module 0 signal 9.
EPI0S10
76
PH4 (8)
I/O
TTL
EPI module 0 signal 10.
EPI0S11
63
PH5 (8)
I/O
TTL
EPI module 0 signal 11.
EPI0S12
42
58
PF7 (8)
PF4 (8)
I/O
TTL
EPI module 0 signal 12.
EPI0S13
19
PG0 (8)
I/O
TTL
EPI module 0 signal 13.
EPI0S14
18
PG1 (8)
I/O
TTL
EPI module 0 signal 14.
EPI0S15
41
46
PG4 (8)
PF5 (8)
I/O
TTL
EPI module 0 signal 15.
EPI0S16
14
PJ0 (8)
I/O
TTL
EPI module 0 signal 16.
EPI0S17
87
PJ1 (8)
I/O
TTL
EPI module 0 signal 17.
EPI0S18
39
PJ2 (8)
I/O
TTL
EPI module 0 signal 18.
EPI0S19
50
97
PJ3 (8)
PD4 (10)
I/O
TTL
EPI module 0 signal 19.
EPI0S20
12
PD2 (8)
I/O
TTL
EPI module 0 signal 20.
EPI0S21
13
PD3 (8)
I/O
TTL
EPI module 0 signal 21.
EPI0S22
91
PB5 (8)
I/O
TTL
EPI module 0 signal 22.
EPI0S23
92
PB4 (8)
I/O
TTL
EPI module 0 signal 23.
EPI0S24
95
PE2 (8)
I/O
TTL
EPI module 0 signal 24.
EPI0S25
96
PE3 (8)
I/O
TTL
EPI module 0 signal 25.
EPI0S26
62
PH6 (8)
I/O
TTL
EPI module 0 signal 26.
EPI0S27
15
PH7 (8)
I/O
TTL
EPI module 0 signal 27.
EPI0S28
52
98
PJ4 (8)
PD5 (10)
I/O
TTL
EPI module 0 signal 28.
EPI0S29
53
99
PJ5 (8)
PD6 (10)
I/O
TTL
EPI module 0 signal 29.
EPI0S30
54
100
PJ6 (8)
PD7 (10)
I/O
TTL
EPI module 0 signal 30.
EPI0S31
36
PG7 (9)
I/O
TTL
EPI module 0 signal 31.
Fault0
6
16
17
39
58
65
75
83
99
PE4 (4)
PG3 (8)
PG2 (4)
PJ2 (10)
PF4 (4)
PB3 (2)
PE1 (3)
PH3 (2)
PD6 (1)
I
TTL
PWM Fault 0.
Fault1
37
40
41
42
90
PG6 (8)
PG5 (5)
PG4 (4)
PF7 (9)
PB6 (4)
I
TTL
PWM Fault 1.
Fault2
16
24
63
PG3 (4)
PC5 (4)
PH5 (10)
I
TTL
PWM Fault 2.
1080
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PWM Fault 3.
Fault3
65
84
PB3 (4)
PH2 (4)
I
TTL
GND
9
21
33
45
57
69
82
94
fixed
-
Power
Ground reference for logic and I/O pins.
GNDA
4
fixed
-
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
I2C0SCL
72
PB2 (1)
I/O
OD
I2C module 0 clock.
I2C0SDA
65
PB3 (1)
I/O
OD
I2C module 0 data.
I2C1SCL
14
19
26
34
PJ0 (11)
PG0 (3)
PA0 (8)
PA6 (1)
I/O
OD
I2C module 1 clock.
I2C1SDA
18
27
35
87
PG1 (3)
PA1 (8)
PA7 (1)
PJ1 (11)
I/O
OD
I2C module 1 data.
I2S0RXMCLK
16
29
98
PG3 (9)
PA3 (9)
PD5 (8)
I/O
TTL
I2S module 0 receive master clock.
I2S0RXSCK
10
40
PD0 (8)
PG5 (9)
I/O
TTL
I2S module 0 receive clock.
I2S0RXSD
17
28
97
PG2 (9)
PA2 (9)
PD4 (8)
I/O
TTL
I2S module 0 receive data.
I2S0RXWS
11
37
PD1 (8)
PG6 (9)
I/O
TTL
I2S module 0 receive word select.
I2S0TXMCLK
43
61
PF6 (9)
PF1 (8)
I/O
TTL
I2S module 0 transmit master clock.
I2S0TXSCK
30
90
99
PA4 (9)
PB6 (9)
PD6 (8)
I/O
TTL
I2S module 0 transmit clock.
I2S0TXSD
5
47
PE5 (9)
PF0 (8)
I/O
TTL
I2S module 0 transmit data.
I2S0TXWS
6
31
100
PE4 (9)
PA5 (9)
PD7 (8)
I/O
TTL
I2S module 0 transmit word select.
IDX0
10
40
72
90
92
100
PD0 (3)
PG5 (4)
PB2 (2)
PB6 (5)
PB4 (6)
PD7 (1)
I
TTL
QEI module 0 index.
May 24, 2010
1081
Texas Instruments-Advance Information
Signal Tables
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
IDX1
17
61
84
PG2 (8)
PF1 (2)
PH2 (1)
I
TTL
QEI module 1 index.
LDO
7
fixed
-
Power
NC
51
fixed
-
-
NMI
89
PB7 (4)
I
TTL
OSC0
48
fixed
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
49
fixed
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
PA0
26
-
I/O
TTL
GPIO port A bit 0.
PA1
27
-
I/O
TTL
GPIO port A bit 1.
PA2
28
-
I/O
TTL
GPIO port A bit 2.
PA3
29
-
I/O
TTL
GPIO port A bit 3.
PA4
30
-
I/O
TTL
GPIO port A bit 4.
PA5
31
-
I/O
TTL
GPIO port A bit 5.
PA6
34
-
I/O
TTL
GPIO port A bit 6.
PA7
35
-
I/O
TTL
GPIO port A bit 7.
PB0
66
-
I/O
TTL
GPIO port B bit 0.
PB1
67
-
I/O
TTL
GPIO port B bit 1.
PB2
72
-
I/O
TTL
GPIO port B bit 2.
PB3
65
-
I/O
TTL
GPIO port B bit 3.
PB4
92
-
I/O
TTL
GPIO port B bit 4.
PB5
91
-
I/O
TTL
GPIO port B bit 5.
PB6
90
-
I/O
TTL
GPIO port B bit 6.
PB7
89
-
I/O
TTL
GPIO port B bit 7.
PC0
80
-
I/O
TTL
GPIO port C bit 0.
PC1
79
-
I/O
TTL
GPIO port C bit 1.
PC2
78
-
I/O
TTL
GPIO port C bit 2.
PC3
77
-
I/O
TTL
GPIO port C bit 3.
PC4
25
-
I/O
TTL
GPIO port C bit 4.
PC5
24
-
I/O
TTL
GPIO port C bit 5.
PC6
23
-
I/O
TTL
GPIO port C bit 6.
PC7
22
-
I/O
TTL
GPIO port C bit 7.
PD0
10
-
I/O
TTL
GPIO port D bit 0.
PD1
11
-
I/O
TTL
GPIO port D bit 1.
PD2
12
-
I/O
TTL
GPIO port D bit 2.
PD3
13
-
I/O
TTL
GPIO port D bit 3.
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin must
also be connected to the VDDC pins at the board
level in addition to the decoupling capacitor(s).
No connect. Leave the pin electrically
unconnected/isolated.
Non-maskable interrupt.
1082
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PD4
97
-
I/O
TTL
GPIO port D bit 4.
PD5
98
-
I/O
TTL
GPIO port D bit 5.
PD6
99
-
I/O
TTL
GPIO port D bit 6.
PD7
100
-
I/O
TTL
GPIO port D bit 7.
PE0
74
-
I/O
TTL
GPIO port E bit 0.
PE1
75
-
I/O
TTL
GPIO port E bit 1.
PE2
95
-
I/O
TTL
GPIO port E bit 2.
PE3
96
-
I/O
TTL
GPIO port E bit 3.
PE4
6
-
I/O
TTL
GPIO port E bit 4.
PE5
5
-
I/O
TTL
GPIO port E bit 5.
PE6
2
-
I/O
TTL
GPIO port E bit 6.
PE7
1
-
I/O
TTL
GPIO port E bit 7.
PF0
47
-
I/O
TTL
GPIO port F bit 0.
PF1
61
-
I/O
TTL
GPIO port F bit 1.
PF2
60
-
I/O
TTL
GPIO port F bit 2.
PF3
59
-
I/O
TTL
GPIO port F bit 3.
PF4
58
-
I/O
TTL
GPIO port F bit 4.
PF5
46
-
I/O
TTL
GPIO port F bit 5.
PF6
43
-
I/O
TTL
GPIO port F bit 6.
PF7
42
-
I/O
TTL
GPIO port F bit 7.
PG0
19
-
I/O
TTL
GPIO port G bit 0.
PG1
18
-
I/O
TTL
GPIO port G bit 1.
PG2
17
-
I/O
TTL
GPIO port G bit 2.
PG3
16
-
I/O
TTL
GPIO port G bit 3.
PG4
41
-
I/O
TTL
GPIO port G bit 4.
PG5
40
-
I/O
TTL
GPIO port G bit 5.
PG6
37
-
I/O
TTL
GPIO port G bit 6.
PG7
36
-
I/O
TTL
GPIO port G bit 7.
PH0
86
-
I/O
TTL
GPIO port H bit 0.
PH1
85
-
I/O
TTL
GPIO port H bit 1.
PH2
84
-
I/O
TTL
GPIO port H bit 2.
PH3
83
-
I/O
TTL
GPIO port H bit 3.
PH4
76
-
I/O
TTL
GPIO port H bit 4.
PH5
63
-
I/O
TTL
GPIO port H bit 5.
PH6
62
-
I/O
TTL
GPIO port H bit 6.
PH7
15
-
I/O
TTL
GPIO port H bit 7.
PhA0
11
25
43
95
PD1 (3)
PC4 (2)
PF6 (4)
PE2 (4)
I
TTL
QEI module 0 phase A.
PhA1
37
96
PG6 (1)
PE3 (3)
I
TTL
QEI module 1 phase A.
May 24, 2010
1083
Texas Instruments-Advance Information
Signal Tables
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PhB0
22
23
42
47
83
96
PC7 (2)
PC6 (2)
PF7 (4)
PF0 (2)
PH3 (1)
PE3 (4)
I
TTL
QEI module 0 phase B.
PhB1
11
36
95
PD1 (11)
PG7 (1)
PE2 (3)
I
TTL
QEI module 1 phase B.
PJ0
14
-
I/O
TTL
GPIO port J bit 0.
PJ1
87
-
I/O
TTL
GPIO port J bit 1.
PJ2
39
-
I/O
TTL
GPIO port J bit 2.
PJ3
50
-
I/O
TTL
GPIO port J bit 3.
PJ4
52
-
I/O
TTL
GPIO port J bit 4.
PJ5
53
-
I/O
TTL
GPIO port J bit 5.
PJ6
54
-
I/O
TTL
GPIO port J bit 6.
PJ7
55
-
I/O
TTL
GPIO port J bit 7.
PWM0
10
14
17
19
34
47
PD0 (1)
PJ0 (10)
PG2 (1)
PG0 (2)
PA6 (4)
PF0 (3)
O
TTL
PWM 0. This signal is controlled by PWM Generator
0.
PWM1
11
16
18
35
61
87
PD1 (1)
PG3 (1)
PG1 (2)
PA7 (4)
PF1 (3)
PJ1 (10)
O
TTL
PWM 1. This signal is controlled by PWM Generator
0.
PWM2
12
60
66
86
PD2 (3)
PF2 (4)
PB0 (2)
PH0 (2)
O
TTL
PWM 2. This signal is controlled by PWM Generator
1.
PWM3
13
59
67
85
PD3 (3)
PF3 (4)
PB1 (2)
PH1 (2)
O
TTL
PWM 3. This signal is controlled by PWM Generator
1.
PWM4
2
19
28
34
60
62
74
86
PE6 (1)
PG0 (4)
PA2 (4)
PA6 (5)
PF2 (2)
PH6 (10)
PE0 (1)
PH0 (9)
O
TTL
PWM 4. This signal is controlled by PWM Generator
2.
1084
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PWM5
1
15
18
29
35
59
75
85
PE7 (1)
PH7 (10)
PG1 (4)
PA3 (4)
PA7 (5)
PF3 (2)
PE1 (1)
PH1 (9)
O
TTL
PWM 5. This signal is controlled by PWM Generator
2.
PWM6
25
30
37
41
PC4 (4)
PA4 (4)
PG6 (4)
PG4 (9)
O
TTL
PWM 6. This signal is controlled by PWM Generator
3.
PWM7
23
31
36
40
PC6 (4)
PA5 (4)
PG7 (4)
PG5 (8)
O
TTL
PWM 7. This signal is controlled by PWM Generator
3.
RST
64
fixed
I
TTL
System reset input.
SSI0Clk
28
PA2 (1)
I/O
TTL
SSI module 0 clock.
SSI0Fss
29
PA3 (1)
I/O
TTL
SSI module 0 frame.
SSI0Rx
30
PA4 (1)
I
TTL
SSI module 0 receive.
SSI0Tx
31
PA5 (1)
O
TTL
SSI module 0 transmit.
SSI1Clk
60
74
76
PF2 (9)
PE0 (2)
PH4 (11)
I/O
TTL
SSI module 1 clock.
SSI1Fss
59
63
75
PF3 (9)
PH5 (11)
PE1 (2)
I/O
TTL
SSI module 1 frame.
SSI1Rx
58
62
95
PF4 (9)
PH6 (11)
PE2 (2)
I
TTL
SSI module 1 receive.
SSI1Tx
15
46
96
PH7 (11)
PF5 (9)
PE3 (2)
O
TTL
SSI module 1 transmit.
SWCLK
80
PC0 (3)
I
TTL
JTAG/SWD CLK.
SWDIO
79
PC1 (3)
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
PC3 (3)
O
TTL
JTAG TDO and SWO.
TCK
80
PC0 (3)
I
TTL
JTAG/SWD CLK.
TDI
78
PC2 (3)
I
TTL
JTAG TDI.
TDO
77
PC3 (3)
O
TTL
JTAG TDO and SWO.
TMS
79
PC1 (3)
I
TTL
JTAG TMS and SWDIO.
U0Rx
26
PA0 (1)
I
TTL
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx
27
PA1 (1)
O
TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1CTS
2
10
34
50
PE6 (9)
PD0 (9)
PA6 (9)
PJ3 (9)
I
TTL
UART module 1 Clear To Send modem status input
signal.
May 24, 2010
1085
Texas Instruments-Advance Information
Signal Tables
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
U1DCD
1
11
35
52
PE7 (9)
PD1 (9)
PA7 (9)
PJ4 (9)
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
47
53
PF0 (9)
PJ5 (9)
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
40
55
100
PG5 (10)
PJ7 (9)
PD7 (9)
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
37
41
97
PG6 (10)
PG4 (10)
PD4 (9)
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
43
54
61
PF6 (10)
PJ6 (9)
PF1 (9)
O
TTL
UART module 1 Request to Send modem output
control line.
U1Rx
10
12
23
26
66
92
PD0 (5)
PD2 (1)
PC6 (5)
PA0 (9)
PB0 (5)
PB4 (7)
I
TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Tx
11
13
22
27
67
91
PD1 (5)
PD3 (1)
PC7 (5)
PA1 (9)
PB1 (5)
PB5 (7)
O
TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx
10
19
92
98
PD0 (4)
PG0 (1)
PB4 (4)
PD5 (9)
I
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx
6
11
18
99
PE4 (5)
PD1 (4)
PG1 (1)
PD6 (9)
O
TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
USB0DM
70
fixed
I/O
Analog
Bidirectional differential data pin (D- per USB
specification).
USB0DP
71
fixed
I/O
Analog
Bidirectional differential data pin (D+ per USB
specification).
USB0EPEN
19
24
34
72
83
PG0 (7)
PC5 (6)
PA6 (8)
PB2 (8)
PH3 (4)
O
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
66
PB0
I
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
1086
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
USB0PFLT
22
23
35
65
74
76
87
PC7 (6)
PC6 (7)
PA7 (8)
PB3 (8)
PE0 (9)
PH4 (4)
PJ1 (9)
I
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0RBIAS
73
fixed
O
Analog
9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
USB0VBUS
67
PB1
I/O
Analog
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
VDD
8
20
32
44
56
68
81
93
fixed
-
Power
Positive supply for I/O and some logic.
VDDA
3
fixed
-
Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
VDDC
38
88
fixed
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VREFA
90
PB6
I
Analog
This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 1023. The VREFA
input is limited to the range specified in Table
26-2 on page 1142.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
May 24, 2010
1087
Texas Instruments-Advance Information
Signal Tables
Table 24-4. Signals by Function, Except for GPIO
Function
ADC
Analog Comparators
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
AIN0
1
I
Analog
Analog-to-digital converter input 0.
AIN1
2
I
Analog
Analog-to-digital converter input 1.
AIN2
5
I
Analog
Analog-to-digital converter input 2.
AIN3
6
I
Analog
Analog-to-digital converter input 3.
AIN4
100
I
Analog
Analog-to-digital converter input 4.
AIN5
99
I
Analog
Analog-to-digital converter input 5.
AIN6
98
I
Analog
Analog-to-digital converter input 6.
AIN7
97
I
Analog
Analog-to-digital converter input 7.
AIN8
96
I
Analog
Analog-to-digital converter input 8.
AIN9
95
I
Analog
Analog-to-digital converter input 9.
AIN10
92
I
Analog
Analog-to-digital converter input 10.
AIN11
91
I
Analog
Analog-to-digital converter input 11.
AIN12
13
I
Analog
Analog-to-digital converter input 12.
AIN13
12
I
Analog
Analog-to-digital converter input 13.
AIN14
11
I
Analog
Analog-to-digital converter input 14.
AIN15
10
I
Analog
Analog-to-digital converter input 15.
VREFA
90
I
Analog
This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 1023. The VREFA
input is limited to the range specified in Table
26-2 on page 1142.
C0+
90
I
Analog
Analog comparator 0 positive input.
C0-
92
I
Analog
Analog comparator 0 negative input.
C0o
24
58
90
91
100
O
TTL
C1+
24
I
Analog
Analog comparator 1 positive input.
C1-
91
I
Analog
Analog comparator 1 negative input.
C1o
2
22
24
46
84
O
TTL
C2+
23
I
Analog
Analog comparator 2 positive input.
C2-
22
I
Analog
Analog comparator 2 negative input.
C2o
1
23
43
O
TTL
Analog comparator 0 output.
Analog comparator 1 output.
Analog comparator 2 output.
1088
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-4. Signals by Function, Except for GPIO (continued)
Function
Controller Area
Network
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
CAN0Rx
10
30
34
92
I
TTL
CAN module 0 receive.
CAN0Tx
11
31
35
91
O
TTL
CAN module 0 transmit.
CAN1Rx
47
I
TTL
CAN module 1 receive.
CAN1Tx
61
O
TTL
CAN module 1 transmit.
May 24, 2010
1089
Texas Instruments-Advance Information
Signal Tables
Table 24-4. Signals by Function, Except for GPIO (continued)
Function
External Peripheral
Interface
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
EPI0S0
83
I/O
TTL
EPI module 0 signal 0.
EPI0S1
84
I/O
TTL
EPI module 0 signal 1.
EPI0S2
25
I/O
TTL
EPI module 0 signal 2.
EPI0S3
24
I/O
TTL
EPI module 0 signal 3.
EPI0S4
23
I/O
TTL
EPI module 0 signal 4.
EPI0S5
22
I/O
TTL
EPI module 0 signal 5.
EPI0S6
86
I/O
TTL
EPI module 0 signal 6.
EPI0S7
85
I/O
TTL
EPI module 0 signal 7.
EPI0S8
74
I/O
TTL
EPI module 0 signal 8.
EPI0S9
75
I/O
TTL
EPI module 0 signal 9.
EPI0S10
76
I/O
TTL
EPI module 0 signal 10.
EPI0S11
63
I/O
TTL
EPI module 0 signal 11.
EPI0S12
42
58
I/O
TTL
EPI module 0 signal 12.
EPI0S13
19
I/O
TTL
EPI module 0 signal 13.
EPI0S14
18
I/O
TTL
EPI module 0 signal 14.
EPI0S15
41
46
I/O
TTL
EPI module 0 signal 15.
EPI0S16
14
I/O
TTL
EPI module 0 signal 16.
EPI0S17
87
I/O
TTL
EPI module 0 signal 17.
EPI0S18
39
I/O
TTL
EPI module 0 signal 18.
EPI0S19
50
97
I/O
TTL
EPI module 0 signal 19.
EPI0S20
12
I/O
TTL
EPI module 0 signal 20.
EPI0S21
13
I/O
TTL
EPI module 0 signal 21.
EPI0S22
91
I/O
TTL
EPI module 0 signal 22.
EPI0S23
92
I/O
TTL
EPI module 0 signal 23.
EPI0S24
95
I/O
TTL
EPI module 0 signal 24.
EPI0S25
96
I/O
TTL
EPI module 0 signal 25.
EPI0S26
62
I/O
TTL
EPI module 0 signal 26.
EPI0S27
15
I/O
TTL
EPI module 0 signal 27.
EPI0S28
52
98
I/O
TTL
EPI module 0 signal 28.
EPI0S29
53
99
I/O
TTL
EPI module 0 signal 29.
EPI0S30
54
100
I/O
TTL
EPI module 0 signal 30.
EPI0S31
36
I/O
TTL
EPI module 0 signal 31.
1090
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-4. Signals by Function, Except for GPIO (continued)
Function
General-Purpose
Timers
Pin Name
a
Pin Number
Pin Type
Buffer Type
CCP0
13
22
23
39
55
58
66
72
91
97
I/O
TTL
Capture/Compare/PWM 0.
CCP1
24
25
34
43
54
67
90
96
100
I/O
TTL
Capture/Compare/PWM 1.
CCP2
6
11
25
46
53
67
75
91
95
98
I/O
TTL
Capture/Compare/PWM 2.
CCP3
6
23
24
35
41
61
72
74
97
I/O
TTL
Capture/Compare/PWM 3.
CCP4
22
25
35
42
52
95
98
I/O
TTL
Capture/Compare/PWM 4.
CCP5
5
12
25
36
40
90
91
I/O
TTL
Capture/Compare/PWM 5.
I/O
TTL
Capture/Compare/PWM 6.
CCP6
Description
May 24, 2010
1091
Texas Instruments-Advance Information
Signal Tables
Table 24-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name
Pin Number
a
Pin Type
Buffer Type
Description
10
12
50
75
86
91
I2C
I2S
JTAG/SWD/SWO
CCP7
11
13
85
90
96
I/O
TTL
Capture/Compare/PWM 7.
I2C0SCL
72
I/O
OD
I2C module 0 clock.
I2C0SDA
65
I/O
OD
I2C module 0 data.
I2C1SCL
14
19
26
34
I/O
OD
I2C module 1 clock.
I2C1SDA
18
27
35
87
I/O
OD
I2C module 1 data.
I2S0RXMCLK
16
29
98
I/O
TTL
I2S module 0 receive master clock.
I2S0RXSCK
10
40
I/O
TTL
I2S module 0 receive clock.
I2S0RXSD
17
28
97
I/O
TTL
I2S module 0 receive data.
I2S0RXWS
11
37
I/O
TTL
I2S module 0 receive word select.
I2S0TXMCLK
43
61
I/O
TTL
I2S module 0 transmit master clock.
I2S0TXSCK
30
90
99
I/O
TTL
I2S module 0 transmit clock.
I2S0TXSD
5
47
I/O
TTL
I2S module 0 transmit data.
I2S0TXWS
6
31
100
I/O
TTL
I2S module 0 transmit word select.
SWCLK
80
I
TTL
JTAG/SWD CLK.
SWDIO
79
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
O
TTL
JTAG TDO and SWO.
TCK
80
I
TTL
JTAG/SWD CLK.
TDI
78
I
TTL
JTAG TDI.
TDO
77
O
TTL
JTAG TDO and SWO.
TMS
79
I
TTL
JTAG TMS and SWDIO.
1092
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-4. Signals by Function, Except for GPIO (continued)
Function
PWM
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
Fault0
6
16
17
39
58
65
75
83
99
I
TTL
PWM Fault 0.
Fault1
37
40
41
42
90
I
TTL
PWM Fault 1.
Fault2
16
24
63
I
TTL
PWM Fault 2.
Fault3
65
84
I
TTL
PWM Fault 3.
PWM0
10
14
17
19
34
47
O
TTL
PWM 0. This signal is controlled by PWM Generator
0.
PWM1
11
16
18
35
61
87
O
TTL
PWM 1. This signal is controlled by PWM Generator
0.
PWM2
12
60
66
86
O
TTL
PWM 2. This signal is controlled by PWM Generator
1.
PWM3
13
59
67
85
O
TTL
PWM 3. This signal is controlled by PWM Generator
1.
PWM4
2
19
28
34
60
62
74
86
O
TTL
PWM 4. This signal is controlled by PWM Generator
2.
PWM5
1
15
18
29
35
59
75
85
O
TTL
PWM 5. This signal is controlled by PWM Generator
2.
May 24, 2010
1093
Texas Instruments-Advance Information
Signal Tables
Table 24-4. Signals by Function, Except for GPIO (continued)
Function
Power
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
PWM6
25
30
37
41
O
TTL
PWM 6. This signal is controlled by PWM Generator
3.
PWM7
23
31
36
40
O
TTL
PWM 7. This signal is controlled by PWM Generator
3.
GND
9
21
33
45
57
69
82
94
-
Power
Ground reference for logic and I/O pins.
GNDA
4
-
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
LDO
7
-
Power
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin must
also be connected to the VDDC pins at the board
level in addition to the decoupling capacitor(s).
VDD
8
20
32
44
56
68
81
93
-
Power
Positive supply for I/O and some logic.
VDDA
3
-
Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
VDDC
38
88
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
1094
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-4. Signals by Function, Except for GPIO (continued)
Function
QEI
SSI
System Control &
Clocks
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
IDX0
10
40
72
90
92
100
I
TTL
QEI module 0 index.
IDX1
17
61
84
I
TTL
QEI module 1 index.
PhA0
11
25
43
95
I
TTL
QEI module 0 phase A.
PhA1
37
96
I
TTL
QEI module 1 phase A.
PhB0
22
23
42
47
83
96
I
TTL
QEI module 0 phase B.
PhB1
11
36
95
I
TTL
QEI module 1 phase B.
SSI0Clk
28
I/O
TTL
SSI module 0 clock.
SSI0Fss
29
I/O
TTL
SSI module 0 frame.
SSI0Rx
30
I
TTL
SSI module 0 receive.
SSI0Tx
31
O
TTL
SSI module 0 transmit.
SSI1Clk
60
74
76
I/O
TTL
SSI module 1 clock.
SSI1Fss
59
63
75
I/O
TTL
SSI module 1 frame.
SSI1Rx
58
62
95
I
TTL
SSI module 1 receive.
SSI1Tx
15
46
96
O
TTL
SSI module 1 transmit.
NMI
89
I
TTL
Non-maskable interrupt.
OSC0
48
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
49
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
64
I
TTL
System reset input.
May 24, 2010
1095
Texas Instruments-Advance Information
Signal Tables
Table 24-4. Signals by Function, Except for GPIO (continued)
Function
UART
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
U0Rx
26
I
TTL
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx
27
O
TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1CTS
2
10
34
50
I
TTL
UART module 1 Clear To Send modem status input
signal.
U1DCD
1
11
35
52
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
47
53
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
40
55
100
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
37
41
97
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
43
54
61
O
TTL
UART module 1 Request to Send modem output
control line.
U1Rx
10
12
23
26
66
92
I
TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Tx
11
13
22
27
67
91
O
TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx
10
19
92
98
I
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx
6
11
18
99
O
TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
1096
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-4. Signals by Function, Except for GPIO (continued)
Function
USB
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
USB0DM
70
I/O
Analog
Bidirectional differential data pin (D- per USB
specification).
USB0DP
71
I/O
Analog
Bidirectional differential data pin (D+ per USB
specification).
USB0EPEN
19
24
34
72
83
O
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
66
I
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
USB0PFLT
22
23
35
65
74
76
87
I
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0RBIAS
73
O
Analog
9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
USB0VBUS
67
I/O
Analog
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 24-5. GPIO Pins and Alternate Functions
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
U0Rx
-
-
-
-
-
-
I2C1SCL
U1Rx
-
-
-
U0Tx
-
-
-
-
-
-
I2C1SDA
U1Tx
-
-
-
SSI0Clk
-
-
PWM4
-
-
-
-
I2S0RXSD
-
-
PA3 29
-
SSI0Fss
-
-
PWM5
-
-
-
-
I2S0RXMCLK
-
-
PA4 30
-
SSI0Rx
-
-
PWM6
CAN0Rx
-
-
-
I2S0TXSCK
-
-
PA5 31
-
SSI0Tx
-
-
PWM7
CAN0Tx
-
-
-
I2S0TXWS
-
-
PA6 34
-
I2C1SCL
CCP1
-
PWM0
PWM4
CAN0Rx
-
USB0EPEN
U1CTS
-
-
PA7 35
-
I2C1SDA
CCP4
-
PWM1
PWM5
CAN0Tx
CCP3
USB0PFLT
U1DCD
-
-
PB0 66
USB0ID
CCP0
PWM2
-
-
U1Rx
-
-
-
-
-
-
PA0 26
-
PA1 27
PA2 28
PB1 67 USB0VBUS
CCP2
PWM3
-
CCP1
U1Tx
-
-
-
-
-
-
PB2 72
-
I2C0SCL
IDX0
-
CCP3
CCP0
-
-
USB0EPEN
-
-
-
PB3 65
-
I2C0SDA Fault0
-
Fault3
-
-
-
USB0PFLT
-
-
-
PB4 92
AIN10
C0-
-
-
-
U2Rx
CAN0Rx
IDX0
U1Rx
EPI0S23
-
-
-
PB5 91
AIN11
C1-
C0o
CCP5
CCP6
CCP0
CAN0Tx
CCP2
U1Tx
EPI0S22
-
-
-
May 24, 2010
1097
Texas Instruments-Advance Information
Signal Tables
Table 24-5. GPIO Pins and Alternate Functions (continued)
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PB6 90
VREFA
C0+
CCP1
CCP7
C0o
Fault1
IDX0
CCP5
-
-
I2S0TXSCK
-
-
PB7 89
-
-
-
-
NMI
-
-
-
-
-
-
-
PC0 80
-
-
-
TCK
SWCLK
-
-
-
-
-
-
-
-
PC1 79
-
-
-
TMS
SWDIO
-
-
-
-
-
-
-
-
PC2 78
-
-
-
TDI
-
-
-
-
-
-
-
-
PC3 77
-
-
-
TDO SWO
-
-
-
-
-
-
-
-
PC4 25
-
CCP5
PhA0
-
PWM6
CCP2
CCP4
-
EPI0S2
CCP1
-
-
PC5 24
C1+
CCP1
C1o
C0o
Fault2
CCP3
USB0EPEN
-
EPI0S3
-
-
-
PC6 23
C2+
CCP3
PhB0
C2o
PWM7
U1Rx
CCP0
USB0PFLT EPI0S4
-
-
-
PC7 22
C2-
CCP4
PhB0
-
CCP0
U1Tx
USB0PFLT
C1o
EPI0S5
-
-
-
PD0 10
AIN15
PWM0
CAN0Rx
IDX0
U2Rx
U1Rx
CCP6
-
I2S0RXSCK
U1CTS
-
-
PD1 11
AIN14
PWM1
CAN0Tx
PhA0
U2Tx
U1Tx
CCP7
-
I2S0RXWS
U1DCD
CCP2
PhB1
PD2 12
AIN13
U1Rx
CCP6
PWM2
CCP5
-
-
-
EPI0S20
-
-
-
PD3 13
AIN12
U1Tx
CCP7
PWM3
CCP0
-
-
-
EPI0S21
-
-
-
PD4 97
AIN7
CCP0
CCP3
-
-
-
-
-
I2S0RXSD
U1RI
EPI0S19
-
PD5 98
AIN6
CCP2
CCP4
-
-
-
-
-
I2S0RXMCLK
U2Rx
EPI0S28
-
PD6 99
AIN5
Fault0
-
-
-
-
-
-
I2S0TXSCK
U2Tx
EPI0S29
-
PD7 100
AIN4
IDX0
C0o
CCP1
-
-
-
-
I2S0TXWS
U1DTR
EPI0S30
-
PE0 74
-
PWM4
SSI1Clk
CCP3
-
-
-
-
EPI0S8 USB0PFLT
-
-
PE1 75
-
PWM5
SSI1Fss Fault0
CCP2
CCP6
-
-
EPI0S9
-
-
-
PE2 95
AIN9
CCP4
SSI1Rx
PhB1
PhA0
CCP2
-
-
EPI0S24
-
-
-
PE3 96
AIN8
CCP1
SSI1Tx
PhA1
PhB0
CCP7
-
-
EPI0S25
-
-
-
PE4
6
AIN3
CCP3
-
-
Fault0
U2Tx
CCP2
-
-
I2S0TXWS
-
-
PE5
5
AIN2
CCP5
-
-
-
-
-
-
-
I2S0TXSD
-
-
PE6
2
AIN1
PWM4
C1o
-
-
-
-
-
-
U1CTS
-
-
PE7
1
AIN0
PWM5
C2o
-
-
-
-
-
-
U1DCD
-
-
PF0 47
-
CAN1Rx
PhB0
PWM0
-
-
-
-
I2S0TXSD
U1DSR
-
-
PF1 61
-
CAN1Tx
IDX1
PWM1
-
-
-
-
I2S0TXMCLK
U1RTS
CCP3
-
PF2 60
-
-
PWM4
-
PWM2
-
-
-
-
SSI1Clk
-
-
PF3 59
-
-
PWM5
-
PWM3
-
-
-
-
SSI1Fss
-
-
PF4 58
-
CCP0
C0o
-
Fault0
-
-
-
EPI0S12 SSI1Rx
-
-
PF5 46
-
CCP2
C1o
-
-
-
-
-
EPI0S15 SSI1Tx
PF6 43
-
CCP1
C2o
-
PhA0
-
-
-
PF7 42
-
CCP4
-
-
PhB0
-
-
-
PG0 19
-
U2Rx
PWM0
I2C1SCL
PWM4
-
-
PG1 18
-
U2Tx
PWM1
I2C1SDA
PWM5
-
-
-
PG2 17
-
PWM0
-
-
Fault0
-
-
-
PG3 16
-
PWM1
-
-
Fault2
-
-
-
-
EPI0S12 Fault1
-
-
U1RTS
-
-
-
-
-
-
EPI0S14
-
-
-
IDX1
I2S0RXSD
-
-
Fault0 I2S0RXMCLK
-
-
USB0EPEN EPI0S13
1098
I2S0TXMCLK
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-5. GPIO Pins and Alternate Functions (continued)
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PG4 41
-
CCP3
-
-
Fault1
-
-
-
EPI0S15
PWM6
U1RI
-
PG5 40
-
CCP5
-
-
IDX0
Fault1
-
-
PWM7
I2S0RXSCK
U1DTR
-
PG6 37
-
PhA1
-
-
PWM6
-
-
-
U1RI
-
PG7 36
-
PhB1
-
-
PWM7
-
-
-
CCP5
EPI0S31
-
-
PH0 86
-
CCP6
PWM2
-
-
-
-
-
EPI0S6
PWM4
-
-
PH1 85
-
CCP7
PWM3
-
-
-
-
-
EPI0S7
PWM5
-
-
PH2 84
-
IDX1
C1o
-
Fault3
-
-
-
EPI0S1
-
-
-
PH3 83
-
PhB0
Fault0
-
USB0EPEN
-
-
-
EPI0S0
-
-
-
PH4 76
-
-
-
-
USB0PFLT
-
-
-
EPI0S10
-
-
SSI1Clk
PH5 63
-
-
-
-
-
-
-
-
EPI0S11
-
PH6 62
-
-
-
-
-
-
-
-
EPI0S26
-
PWM4
SSI1Rx
PH7 15
-
-
-
-
-
-
-
-
EPI0S27
-
PWM5
SSI1Tx
PJ0 14
-
-
-
-
-
-
-
-
EPI0S16
-
PWM0
I2C1SCL
PJ1 87
-
-
-
-
-
-
-
-
EPI0S17 USB0PFLT
PWM1
I2C1SDA
PJ2 39
-
-
-
-
-
-
-
-
EPI0S18
CCP0
Fault0
-
PJ3 50
-
-
-
-
-
-
-
-
EPI0S19
U1CTS
CCP6
-
PJ4 52
-
-
-
-
-
-
-
-
EPI0S28
U1DCD
CCP4
-
PJ5 53
-
-
-
-
-
-
-
-
EPI0S29
U1DSR
CCP2
-
PJ6 54
-
-
-
-
-
-
-
-
EPI0S30
U1RTS
CCP1
-
PJ7 55
-
-
-
-
-
-
-
-
-
U1DTR
CCP0
-
Fault1 I2S0RXWS
Fault2 SSI1Fss
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin.
May 24, 2010
1099
Texas Instruments-Advance Information
Signal Tables
Table 24-6. Possible Pin Assignments for Alternate Functions
# of Possible Assignments
Alternate Function
GPIO Function
one
AIN0
PE7
AIN1
PE6
AIN10
PB4
AIN11
PB5
AIN12
PD3
AIN13
PD2
AIN14
PD1
AIN15
PD0
AIN2
PE5
AIN3
PE4
AIN4
PD7
AIN5
PD6
AIN6
PD5
AIN7
PD4
AIN8
PE3
AIN9
PE2
C0+
PB6
C0-
PB4
C1+
PC5
C1-
PB5
C2+
PC6
C2-
PC7
CAN1Rx
PF0
CAN1Tx
PF1
I2C0SCL
PB2
I2C0SDA
PB3
NMI
PB7
SSI0Clk
PA2
SSI0Fss
PA3
SSI0Rx
PA4
SSI0Tx
PA5
SWCLK
PC0
SWDIO
PC1
SWO
PC3
TCK
PC0
TDI
PC2
TDO
PC3
TMS
PC1
U0Rx
PA0
U0Tx
PA1
USB0ID
PB0
1100
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-6. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
two
three
four
Alternate Function
GPIO Function
USB0VBUS
PB1
VREFA
PB6
Fault3
PB3 PH2
I2S0RXSCK
PD0 PG5
I2S0RXWS
PD1 PG6
I2S0TXMCLK
PF1 PF6
I2S0TXSD
PE5 PF0
PhA1
PE3 PG6
U1DSR
PF0 PJ5
C2o
PC6 PE7 PF6
Fault2
PC5 PG3 PH5
I2S0RXMCLK
PA3 PD5 PG3
I2S0RXSD
PA2 PD4 PG2
I2S0TXSCK
PA4 PB6 PD6
I2S0TXWS
PA5 PD7 PE4
IDX1
PF1 PG2 PH2
PhB1
PD1 PE2 PG7
SSI1Clk
PE0 PF2 PH4
SSI1Fss
PE1 PF3 PH5
SSI1Rx
PE2 PF4 PH6
SSI1Tx
PE3 PF5 PH7
U1DTR
PD7 PG5 PJ7
U1RI
PD4 PG4 PG6
U1RTS
PF1 PF6 PJ6
CAN0Rx
PA4 PA6 PB4 PD0
CAN0Tx
PA5 PA7 PB5 PD1
I2C1SCL
PA0 PA6 PG0 PJ0
I2C1SDA
PA1 PA7 PG1 PJ1
PWM2
PB0 PD2 PF2 PH0
PWM3
PB1 PD3 PF3 PH1
PWM6
PA4 PC4 PG4 PG6
PWM7
PA5 PC6 PG5 PG7
PhA0
PC4 PD1 PE2 PF6
U1CTS
PA6 PD0 PE6 PJ3
U1DCD
PA7 PD1 PE7 PJ4
U2Rx
PB4 PD0 PD5 PG0
U2Tx
PD1 PD6 PE4 PG1
May 24, 2010
1101
Texas Instruments-Advance Information
Signal Tables
Table 24-6. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
Alternate Function
five
C0o
PB5 PB6 PC5 PD7 PF4
C1o
PC5 PC7 PE6 PF5 PH2
CCP7
PB6 PD1 PD3 PE3 PH1
Fault1
PB6 PF7 PG4 PG5 PG6
USB0EPEN
PA6 PB2 PC5 PG0 PH3
six
seven
CCP6
PB5 PD0 PD2 PE1 PH0 PJ3
IDX0
PB2 PB4 PB6 PD0 PD7 PG5
PWM0
PA6 PD0 PF0 PG0 PG2 PJ0
PWM1
PA7 PD1 PF1 PG1 PG3 PJ1
PhB0
PC6 PC7 PE3 PF0 PF7 PH3
U1Rx
PA0 PB0 PB4 PC6 PD0 PD2
U1Tx
PA1 PB1 PB5 PC7 PD1 PD3
CCP4
PA7 PC4 PC7 PD5 PE2 PF7 PJ4
CCP5
PB5 PB6 PC4 PD2 PE5 PG5 PG7
USB0PFLT
PA7 PB3 PC6 PC7 PE0 PH4 PJ1
PWM4
PA2 PA6 PE0 PE6 PF2 PG0 PH0 PH6
PWM5
PA3 PA7 PE1 PE7 PF3 PG1 PH1 PH7
CCP1
PA6 PB1 PB6 PC4 PC5 PD7 PE3 PF6 PJ6
CCP3
PA7 PB2 PC5 PC6 PD4 PE0 PE4 PF1 PG4
Fault0
PB3 PD6 PE1 PE4 PF4 PG2 PG3 PH3 PJ2
eight
nine
ten
24.2
GPIO Function
CCP0
PB0 PB2 PB5 PC6 PC7 PD3 PD4 PF4 PJ2 PJ7
CCP2
PB1 PB5 PC4 PD1 PD5 PE1 PE2 PE4 PF5 PJ5
108-Pin BGA Package Pin Tables
Table 24-7. Signals by Pin Number
Pin Number
A1
A2
Pin Name
Pin Type
a
Buffer Type
Description
PE6
I/O
TTL
AIN1
I
Analog
GPIO port E bit 6.
C1o
O
TTL
Analog comparator 1 output.
Analog-to-digital converter input 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
U1CTS
I
TTL
UART module 1 Clear To Send modem status input signal.
GPIO port D bit 7.
PD7
I/O
TTL
AIN4
I
Analog
C0o
O
TTL
Analog comparator 0 output.
Analog-to-digital converter input 4.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
EPI0S30
I/O
TTL
EPI module 0 signal 30.
I2S0TXWS
I/O
TTL
I2S module 0 transmit word select.
IDX0
I
TTL
QEI module 0 index.
U1DTR
O
TTL
UART module 1 Data Terminal Ready modem status input signal.
1102
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-7. Signals by Pin Number (continued)
Pin Number
A3
A4
Pin Name
Pin Type
a
Buffer Type
Description
PD6
I/O
TTL
AIN5
I
Analog
GPIO port D bit 6.
EPI0S29
I/O
TTL
EPI module 0 signal 29.
Analog-to-digital converter input 5.
Fault0
I
TTL
PWM Fault 0.
I2S0TXSCK
I/O
TTL
I2S module 0 transmit clock.
U2Tx
O
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
PE2
I/O
TTL
GPIO port E bit 2.
AIN9
I
Analog
CCP2
I/O
TTL
Capture/Compare/PWM 2.
Analog-to-digital converter input 9.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S24
I/O
TTL
EPI module 0 signal 24.
PhA0
I
TTL
QEI module 0 phase A.
PhB1
I
TTL
QEI module 1 phase B.
SSI1Rx
I
TTL
SSI module 1 receive.
A5
GNDA
-
Power
A6
PB4
I/O
TTL
AIN10
I
Analog
Analog-to-digital converter input 10.
C0-
I
Analog
Analog comparator 0 negative input.
A7
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
GPIO port B bit 4.
CAN0Rx
I
TTL
CAN module 0 receive.
EPI0S23
I/O
TTL
EPI module 0 signal 23.
IDX0
I
TTL
QEI module 0 index.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
PB6
I/O
TTL
GPIO port B bit 6.
C0+
I
Analog
C0o
O
TTL
Analog comparator 0 output.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
Analog comparator 0 positive input.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
Fault1
I
TTL
PWM Fault 1.
I2S0TXSCK
I/O
TTL
I2S module 0 transmit clock.
IDX0
I
TTL
QEI module 0 index.
VREFA
I
Analog
This input provides a reference voltage used to specify the input
voltage at which the ADC converts to a maximum value. In other
words, the voltage that is applied to VREFA is the voltage with which
an AINn signal is converted to 1023. The VREFA input is limited
to the range specified in Table 26-2 on page 1142.
May 24, 2010
1103
Texas Instruments-Advance Information
Signal Tables
Table 24-7. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
Buffer Type
A8
PB7
I/O
TTL
GPIO port B bit 7.
NMI
I
TTL
Non-maskable interrupt.
PC0
I/O
TTL
GPIO port C bit 0.
SWCLK
I
TTL
JTAG/SWD CLK.
TCK
I
TTL
JTAG/SWD CLK.
PC3
I/O
TTL
GPIO port C bit 3.
SWO
O
TTL
JTAG TDO and SWO.
TDO
O
TTL
JTAG TDO and SWO.
A9
A10
A11
A12
B1
B2
B3
Description
PB2
I/O
TTL
GPIO port B bit 2.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
I2C0SCL
I/O
OD
I2C module 0 clock.
IDX0
I
TTL
QEI module 0 index.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
PE1
I/O
TTL
GPIO port E bit 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S9
I/O
TTL
EPI module 0 signal 9.
Fault0
I
TTL
PWM Fault 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
SSI1Fss
I/O
TTL
SSI module 1 frame.
PE7
I/O
TTL
GPIO port E bit 7.
AIN0
I
Analog
C2o
O
TTL
Analog comparator 2 output.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
PE4
I/O
TTL
GPIO port E bit 4.
AIN3
I
Analog
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
Analog-to-digital converter input 0.
Analog-to-digital converter input 3.
Fault0
I
TTL
PWM Fault 0.
I2S0TXWS
I/O
TTL
I2S module 0 transmit word select.
U2Tx
O
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
PE5
I/O
TTL
GPIO port E bit 5.
AIN2
I
Analog
CCP5
I/O
TTL
Capture/Compare/PWM 5.
I2S0TXSD
I/O
TTL
I2S module 0 transmit data.
Analog-to-digital converter input 2.
1104
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-7. Signals by Pin Number (continued)
Pin Number
B4
B5
B6
B7
B8
B9
Pin Name
Pin Type
a
Buffer Type
Description
PE3
I/O
TTL
AIN8
I
Analog
GPIO port E bit 3.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
Analog-to-digital converter input 8.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
EPI0S25
I/O
TTL
EPI module 0 signal 25.
PhA1
I
TTL
QEI module 1 phase A.
PhB0
I
TTL
QEI module 0 phase B.
SSI1Tx
O
TTL
SSI module 1 transmit.
GPIO port D bit 4.
PD4
I/O
TTL
AIN7
I
Analog
CCP0
I/O
TTL
Capture/Compare/PWM 0.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S19
I/O
TTL
EPI module 0 signal 19.
I2S0RXSD
I/O
TTL
I2S module 0 receive data.
U1RI
I
TTL
UART module 1 Ring Indicator modem status input signal.
EPI0S17
I/O
TTL
EPI module 0 signal 17.
I2C1SDA
I/O
OD
I2C module 1 data.
PJ1
I/O
TTL
GPIO port J bit 1.
Analog-to-digital converter input 7.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
GPIO port B bit 5.
PB5
I/O
TTL
AIN11
I
Analog
C0o
O
TTL
C1-
I
Analog
CAN0Tx
O
TTL
CAN module 0 transmit.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S22
I/O
TTL
EPI module 0 signal 22.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
PC2
I/O
TTL
GPIO port C bit 2.
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I
TTL
JTAG TMS and SWDIO.
Analog-to-digital converter input 11.
Analog comparator 0 output.
Analog comparator 1 negative input.
May 24, 2010
1105
Texas Instruments-Advance Information
Signal Tables
Table 24-7. Signals by Pin Number (continued)
Pin Number
B10
B11
a
Pin Name
Pin Type
Buffer Type
Description
PH4
I/O
TTL
GPIO port H bit 4.
EPI0S10
I/O
TTL
EPI module 0 signal 10.
SSI1Clk
I/O
TTL
SSI module 1 clock.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PE0
I/O
TTL
GPIO port E bit 0.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S8
I/O
TTL
EPI module 0 signal 8.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
SSI1Clk
I/O
TTL
SSI module 1 clock.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
B12
USB0RBIAS
O
Analog
9.1-kΩ resistor (1% precision) used internally for USB analog
circuitry.
C1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C3
VDDC
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
C4
GND
-
Power
Ground reference for logic and I/O pins.
C5
GND
-
Power
Ground reference for logic and I/O pins.
C6
PD5
I/O
TTL
AIN6
I
Analog
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
C7
C8
C9
GPIO port D bit 5.
Analog-to-digital converter input 6.
EPI0S28
I/O
TTL
EPI module 0 signal 28.
I2S0RXMCLK
I/O
TTL
I2S module 0 receive master clock.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
VDDA
-
Power
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
PH1
I/O
TTL
GPIO port H bit 1.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
EPI0S7
I/O
TTL
EPI module 0 signal 7.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
PH0
I/O
TTL
GPIO port H bit 0.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S6
I/O
TTL
EPI module 0 signal 6.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
1106
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-7. Signals by Pin Number (continued)
Pin Number
C10
a
Pin Name
Pin Type
Buffer Type
Description
PG7
I/O
TTL
GPIO port G bit 7.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
EPI0S31
I/O
TTL
EPI module 0 signal 31.
PWM7
O
TTL
PWM 7. This signal is controlled by PWM Generator 3.
PhB1
I
TTL
QEI module 1 phase B.
C11
USB0DM
I/O
Analog
Bidirectional differential data pin (D- per USB specification).
C12
USB0DP
I/O
Analog
Bidirectional differential data pin (D+ per USB specification).
D1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D3
VDDC
-
Power
D10
PH3
I/O
TTL
GPIO port H bit 3.
EPI0S0
I/O
TTL
EPI module 0 signal 0.
Fault0
I
TTL
PWM Fault 0.
PhB0
I
TTL
QEI module 0 phase B.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
PH2
I/O
TTL
GPIO port H bit 2.
C1o
O
TTL
Analog comparator 1 output.
EPI0S1
I/O
TTL
EPI module 0 signal 1.
Fault3
I
TTL
PWM Fault 3.
IDX1
I
TTL
QEI module 1 index.
D11
D12
Positive supply for most of the logic function, including the
processor core and most peripherals.
PB1
I/O
TTL
GPIO port B bit 1.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
USB0VBUS
I/O
Analog
This signal is used during the session request protocol. This signal
allows the USB PHY to both sense the voltage level of VBUS, and
pull up VBUS momentarily during VBUS pulsing.
E1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
E2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
E3
LDO
-
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the logic, the LDO pin
must also be connected to the VDDC pins at the board level in
addition to the decoupling capacitor(s).
E10
VDD
-
Power
Positive supply for I/O and some logic.
May 24, 2010
1107
Texas Instruments-Advance Information
Signal Tables
Table 24-7. Signals by Pin Number (continued)
Pin Number
E11
E12
F1
a
Pin Name
Pin Type
Buffer Type
Description
PB3
I/O
TTL
GPIO port B bit 3.
Fault0
I
TTL
PWM Fault 0.
Fault3
I
TTL
PWM Fault 3.
I2C0SDA
I/O
OD
I2C module 0 data.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PB0
I/O
TTL
GPIO port B bit 0.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
USB0ID
I
Analog
This signal senses the state of the USB ID signal. The USB PHY
enables an integrated pull-up, and an external element (USB
connector) indicates the initial state of the USB controller (pulled
down is the A side of the cable and pulled up is the B side).
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
F2
NC
-
-
F3
EPI0S16
I/O
TTL
EPI module 0 signal 16.
I2C1SCL
I/O
OD
I2C module 1 clock.
F10
PJ0
I/O
TTL
GPIO port J bit 0.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PH5
I/O
TTL
GPIO port H bit 5.
EPI0S11
I/O
TTL
EPI module 0 signal 11.
Fault2
I
TTL
PWM Fault 2.
SSI module 1 frame.
SSI1Fss
I/O
TTL
F11
GND
-
Power
Ground reference for logic and I/O pins.
F12
GND
-
Power
Ground reference for logic and I/O pins.
PD0
I/O
TTL
AIN15
I
Analog
CAN0Rx
I
TTL
CAN module 0 receive.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
I2S0RXSCK
I/O
TTL
I2S module 0 receive clock.
IDX0
I
TTL
QEI module 0 index.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
U1CTS
I
TTL
UART module 1 Clear To Send modem status input signal.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
G1
GPIO port D bit 0.
Analog-to-digital converter input 15.
1108
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-7. Signals by Pin Number (continued)
Pin Number
G2
G3
Pin Name
Pin Type
a
Buffer Type
Description
PD1
I/O
TTL
AIN14
I
Analog
GPIO port D bit 1.
CAN0Tx
O
TTL
CAN module 0 transmit.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
I2S0RXWS
I/O
TTL
I2S module 0 receive word select.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PhA0
I
TTL
QEI module 0 phase A.
Analog-to-digital converter input 14.
PhB1
I
TTL
QEI module 1 phase B.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
U2Tx
O
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
PH6
I/O
TTL
GPIO port H bit 6.
EPI0S26
I/O
TTL
EPI module 0 signal 26.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
SSI module 1 receive.
SSI1Rx
I
TTL
G10
VDD
-
Power
Positive supply for I/O and some logic.
G11
VDD
-
Power
Positive supply for I/O and some logic.
G12
VDD
-
Power
Positive supply for I/O and some logic.
H1
PD3
I/O
TTL
AIN12
I
Analog
CCP0
I/O
TTL
Capture/Compare/PWM 0.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
EPI0S21
I/O
TTL
EPI module 0 signal 21.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
PD2
I/O
TTL
GPIO port D bit 2.
AIN13
I
Analog
CCP5
I/O
TTL
Capture/Compare/PWM 5.
H2
H3
H10
GPIO port D bit 3.
Analog-to-digital converter input 12.
Analog-to-digital converter input 13.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S20
I/O
TTL
EPI module 0 signal 20.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
PH7
I/O
TTL
GPIO port H bit 7.
EPI0S27
I/O
TTL
EPI module 0 signal 27.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
SSI1Tx
O
TTL
SSI module 1 transmit.
VDD
-
Power
Positive supply for I/O and some logic.
May 24, 2010
1109
Texas Instruments-Advance Information
Signal Tables
Table 24-7. Signals by Pin Number (continued)
Pin Number
Pin Name
H11
H12
J1
J2
a
Pin Type
Buffer Type
Description
RST
I
TTL
System reset input.
PF1
I/O
TTL
GPIO port F bit 1.
CAN1Tx
O
TTL
CAN module 1 transmit.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
I2S0TXMCLK
I/O
TTL
I2S module 0 transmit master clock.
IDX1
I
TTL
QEI module 1 index.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
U1RTS
O
TTL
UART module 1 Request to Send modem output control line.
PG2
I/O
TTL
GPIO port G bit 2.
Fault0
I
TTL
PWM Fault 0.
I2S0RXSD
I/O
TTL
I2S module 0 receive data.
IDX1
I
TTL
QEI module 1 index.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PG3
I/O
TTL
GPIO port G bit 3.
Fault0
I
TTL
PWM Fault 0.
Fault2
I
TTL
PWM Fault 2.
I2S0RXMCLK
I/O
TTL
I2S module 0 receive master clock.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
J3
GND
-
Power
Ground reference for logic and I/O pins.
J10
GND
-
Power
Ground reference for logic and I/O pins.
J11
PF2
I/O
TTL
GPIO port F bit 2.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
SSI1Clk
I/O
TTL
SSI module 1 clock.
PF3
I/O
TTL
GPIO port F bit 3.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
J12
K1
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
SSI1Fss
I/O
TTL
SSI module 1 frame.
PG0
I/O
TTL
GPIO port G bit 0.
EPI0S13
I/O
TTL
EPI module 0 signal 13.
I2C1SCL
I/O
OD
I2C module 1 clock.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
1110
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-7. Signals by Pin Number (continued)
Pin Number
K2
K3
K4
a
Pin Name
Pin Type
Buffer Type
Description
PG1
I/O
TTL
GPIO port G bit 1.
EPI0S14
I/O
TTL
EPI module 0 signal 14.
I2C1SDA
I/O
OD
I2C module 1 data.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
U2Tx
O
TTL
UART module 2 transmit. When in IrDA mode, this signal has IrDA
modulation.
PG4
I/O
TTL
GPIO port G bit 4.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S15
I/O
TTL
EPI module 0 signal 15.
Fault1
I
TTL
PWM Fault 1.
PWM6
O
TTL
PWM 6. This signal is controlled by PWM Generator 3.
U1RI
I
TTL
UART module 1 Ring Indicator modem status input signal.
PF7
I/O
TTL
GPIO port F bit 7.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S12
I/O
TTL
EPI module 0 signal 12.
Fault1
I
TTL
PWM Fault 1.
PhB0
I
TTL
QEI module 0 phase B.
K5
GND
-
Power
K6
CCP0
I/O
TTL
Ground reference for logic and I/O pins.
Capture/Compare/PWM 0.
EPI0S18
I/O
TTL
EPI module 0 signal 18.
Fault0
I
TTL
PWM Fault 0.
PJ2
I/O
TTL
GPIO port J bit 2.
K7
VDD
-
Power
Positive supply for I/O and some logic.
K8
VDD
-
Power
Positive supply for I/O and some logic.
K9
VDD
-
Power
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
K10
GND
-
Power
K11
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S28
I/O
TTL
EPI module 0 signal 28.
PJ4
I/O
TTL
GPIO port J bit 4.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
K12
CCP2
I/O
TTL
Capture/Compare/PWM 2.
EPI0S29
I/O
TTL
EPI module 0 signal 29.
PJ5
I/O
TTL
GPIO port J bit 5.
U1DSR
I
TTL
UART module 1 Data Set Ready modem output control line.
May 24, 2010
1111
Texas Instruments-Advance Information
Signal Tables
Table 24-7. Signals by Pin Number (continued)
Pin Number
L1
L2
L3
L4
L5
L6
a
Pin Name
Pin Type
Buffer Type
Description
PC4
I/O
TTL
GPIO port C bit 4.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
EPI0S2
I/O
TTL
EPI module 0 signal 2.
PWM6
O
TTL
PWM 6. This signal is controlled by PWM Generator 3.
PhA0
I
TTL
QEI module 0 phase A.
PC7
I/O
TTL
GPIO port C bit 7.
C1o
O
TTL
Analog comparator 1 output.
C2-
I
Analog
CCP0
I/O
TTL
Analog comparator 2 negative input.
Capture/Compare/PWM 0.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S5
I/O
TTL
EPI module 0 signal 5.
PhB0
I
TTL
QEI module 0 phase B.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
PA0
I/O
TTL
GPIO port A bit 0.
I2C1SCL
I/O
OD
I2C module 1 clock.
U0Rx
I
TTL
UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
PA3
I/O
TTL
GPIO port A bit 3.
I2S0RXMCLK
I/O
TTL
I2S module 0 receive master clock.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
SSI0Fss
I/O
TTL
SSI module 0 frame.
PA4
I/O
TTL
GPIO port A bit 4.
CAN0Rx
I
TTL
CAN module 0 receive.
I2S0TXSCK
I/O
TTL
I2S module 0 transmit clock.
PWM6
O
TTL
PWM 6. This signal is controlled by PWM Generator 3.
SSI0Rx
I
TTL
SSI module 0 receive.
PA6
I/O
TTL
GPIO port A bit 6.
CAN0Rx
I
TTL
CAN module 0 receive.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
I2C1SCL
I/O
OD
I2C module 1 clock.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
U1CTS
I
TTL
UART module 1 Clear To Send modem status input signal.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
1112
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-7. Signals by Pin Number (continued)
Pin Number
L7
L8
L9
L10
a
Pin Name
Pin Type
Buffer Type
Description
PG6
I/O
TTL
GPIO port G bit 6.
Fault1
I
TTL
PWM Fault 1.
I2S0RXWS
I/O
TTL
I2S module 0 receive word select.
PWM6
O
TTL
PWM 6. This signal is controlled by PWM Generator 3.
PhA1
I
TTL
QEI module 1 phase A.
U1RI
I
TTL
UART module 1 Ring Indicator modem status input signal.
PF5
I/O
TTL
GPIO port F bit 5.
C1o
O
TTL
Analog comparator 1 output.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
EPI0S15
I/O
TTL
EPI module 0 signal 15.
SSI1Tx
O
TTL
SSI module 1 transmit.
PF4
I/O
TTL
GPIO port F bit 4.
C0o
O
TTL
Analog comparator 0 output.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
EPI0S12
I/O
TTL
EPI module 0 signal 12.
Fault0
I
TTL
PWM Fault 0.
SSI1Rx
I
TTL
SSI module 1 receive.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
EPI0S30
I/O
TTL
EPI module 0 signal 30.
PJ6
I/O
TTL
GPIO port J bit 6.
U1RTS
O
TTL
UART module 1 Request to Send modem output control line.
L11
OSC0
I
Analog
L12
CCP0
I/O
TTL
Capture/Compare/PWM 0.
M1
Main oscillator crystal input or an external clock reference input.
PJ7
I/O
TTL
GPIO port J bit 7.
U1DTR
O
TTL
UART module 1 Data Terminal Ready modem status input signal.
PC5
I/O
TTL
GPIO port C bit 5.
C0o
O
TTL
Analog comparator 0 output.
C1+
I
Analog
Analog comparator 1 positive input.
C1o
O
TTL
Analog comparator 1 output.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S3
I/O
TTL
EPI module 0 signal 3.
Fault2
I
TTL
PWM Fault 2.
USB0EPEN
O
TTL
Optionally used in Host mode to control an external power source
to supply power to the USB bus.
May 24, 2010
1113
Texas Instruments-Advance Information
Signal Tables
Table 24-7. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
M2
PC6
I/O
TTL
C2+
I
Analog
C2o
O
TTL
Analog comparator 2 output.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
EPI0S4
I/O
TTL
EPI module 0 signal 4.
PWM7
O
TTL
PWM 7. This signal is controlled by PWM Generator 3.
PhB0
I
TTL
QEI module 0 phase B.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
M3
M4
M5
M6
Buffer Type
Description
GPIO port C bit 6.
Analog comparator 2 positive input.
PA1
I/O
TTL
GPIO port A bit 1.
I2C1SDA
I/O
OD
I2C module 1 data.
U0Tx
O
TTL
UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
PA2
I/O
TTL
GPIO port A bit 2.
I2S0RXSD
I/O
TTL
I2S module 0 receive data.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
SSI0Clk
I/O
TTL
SSI module 0 clock.
PA5
I/O
TTL
GPIO port A bit 5.
CAN0Tx
O
TTL
CAN module 0 transmit.
I2S0TXWS
I/O
TTL
I2S module 0 transmit word select.
PWM7
O
TTL
PWM 7. This signal is controlled by PWM Generator 3.
SSI0Tx
O
TTL
SSI module 0 transmit.
PA7
I/O
TTL
GPIO port A bit 7.
CAN0Tx
O
TTL
CAN module 0 transmit.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
CCP4
I/O
TTL
Capture/Compare/PWM 4.
I2C1SDA
I/O
OD
I2C module 1 data.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
U1DCD
I
TTL
UART module 1 Data Carrier Detect modem status input signal.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
1114
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-7. Signals by Pin Number (continued)
Pin Number
M7
M8
M9
M10
a
Pin Name
Pin Type
Buffer Type
Description
PG5
I/O
TTL
GPIO port G bit 5.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
Fault1
I
TTL
PWM Fault 1.
I2S0RXSCK
I/O
TTL
I2S module 0 receive clock.
IDX0
I
TTL
QEI module 0 index.
PWM7
O
TTL
PWM 7. This signal is controlled by PWM Generator 3.
U1DTR
O
TTL
UART module 1 Data Terminal Ready modem status input signal.
PF6
I/O
TTL
GPIO port F bit 6.
C2o
O
TTL
Analog comparator 2 output.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
I2S0TXMCLK
I/O
TTL
I2S module 0 transmit master clock.
PhA0
I
TTL
QEI module 0 phase A.
U1RTS
O
TTL
UART module 1 Request to Send modem output control line.
PF0
I/O
TTL
GPIO port F bit 0.
CAN1Rx
I
TTL
CAN module 1 receive.
I2S0TXSD
I/O
TTL
I2S module 0 transmit data.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PhB0
I
TTL
QEI module 0 phase B.
U1DSR
I
TTL
UART module 1 Data Set Ready modem output control line.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S19
I/O
TTL
EPI module 0 signal 19.
PJ3
I/O
TTL
GPIO port J bit 3.
U1CTS
I
TTL
UART module 1 Clear To Send modem status input signal.
M11
OSC1
O
Analog
M12
NC
-
-
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
No connect. Leave the pin electrically unconnected/isolated.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 24-8. Signals by Signal Name
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
AIN0
B1
PE7
I
Analog
Analog-to-digital converter input 0.
AIN1
A1
PE6
I
Analog
Analog-to-digital converter input 1.
AIN2
B3
PE5
I
Analog
Analog-to-digital converter input 2.
AIN3
B2
PE4
I
Analog
Analog-to-digital converter input 3.
AIN4
A2
PD7
I
Analog
Analog-to-digital converter input 4.
AIN5
A3
PD6
I
Analog
Analog-to-digital converter input 5.
AIN6
C6
PD5
I
Analog
Analog-to-digital converter input 6.
AIN7
B5
PD4
I
Analog
Analog-to-digital converter input 7.
AIN8
B4
PE3
I
Analog
Analog-to-digital converter input 8.
AIN9
A4
PE2
I
Analog
Analog-to-digital converter input 9.
AIN10
A6
PB4
I
Analog
Analog-to-digital converter input 10.
May 24, 2010
1115
Texas Instruments-Advance Information
Signal Tables
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
AIN11
B7
PB5
I
Analog
Analog-to-digital converter input 11.
AIN12
H1
PD3
I
Analog
Analog-to-digital converter input 12.
AIN13
H2
PD2
I
Analog
Analog-to-digital converter input 13.
AIN14
G2
PD1
I
Analog
Analog-to-digital converter input 14.
AIN15
G1
PD0
I
Analog
Analog-to-digital converter input 15.
C0+
A7
PB6
I
Analog
Analog comparator 0 positive input.
Analog comparator 0 negative input.
C0-
A6
PB4
I
Analog
C0o
M1
L9
A7
B7
A2
PC5 (3)
PF4 (2)
PB6 (3)
PB5 (1)
PD7 (2)
O
TTL
C1+
M1
PC5
I
Analog
Analog comparator 1 positive input.
C1-
B7
PB5
I
Analog
Analog comparator 1 negative input.
C1o
A1
L2
M1
L8
D11
PE6 (2)
PC7 (7)
PC5 (2)
PF5 (2)
PH2 (2)
O
TTL
C2+
M2
PC6
I
Analog
Analog comparator 2 positive input.
C2-
L2
PC7
I
Analog
Analog comparator 2 negative input.
C2o
B1
M2
M8
PE7 (2)
PC6 (3)
PF6 (2)
O
TTL
Analog comparator 2 output.
CAN0Rx
G1
L5
L6
A6
PD0 (2)
PA4 (5)
PA6 (6)
PB4 (5)
I
TTL
CAN module 0 receive.
CAN0Tx
G2
M5
M6
B7
PD1 (2)
PA5 (5)
PA7 (6)
PB5 (5)
O
TTL
CAN module 0 transmit.
CAN1Rx
M9
PF0 (1)
I
TTL
CAN module 1 receive.
CAN1Tx
H12
PF1 (1)
O
TTL
CAN module 1 transmit.
CCP0
H1
L2
M2
K6
L12
L9
E12
A11
B7
B5
PD3 (4)
PC7 (4)
PC6 (6)
PJ2 (9)
PJ7 (10)
PF4 (1)
PB0 (1)
PB2 (5)
PB5 (4)
PD4 (1)
I/O
TTL
Capture/Compare/PWM 0.
Analog comparator 0 output.
Analog comparator 1 output.
1116
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CCP1
M1
L1
L6
M8
L10
D12
A7
B4
A2
PC5 (1)
PC4 (9)
PA6 (2)
PF6 (1)
PJ6 (10)
PB1 (4)
PB6 (1)
PE3 (1)
PD7 (3)
I/O
TTL
Capture/Compare/PWM 1.
CCP2
B2
G2
L1
L8
K12
D12
A12
B7
A4
C6
PE4 (6)
PD1 (10)
PC4 (5)
PF5 (1)
PJ5 (10)
PB1 (1)
PE1 (4)
PB5 (6)
PE2 (5)
PD5 (1)
I/O
TTL
Capture/Compare/PWM 2.
CCP3
B2
M2
M1
M6
K3
H12
A11
B11
B5
PE4 (1)
PC6 (1)
PC5 (5)
PA7 (7)
PG4 (1)
PF1 (10)
PB2 (4)
PE0 (3)
PD4 (2)
I/O
TTL
Capture/Compare/PWM 3.
CCP4
L2
L1
M6
K4
K11
A4
C6
PC7 (1)
PC4 (6)
PA7 (2)
PF7 (1)
PJ4 (10)
PE2 (1)
PD5 (2)
I/O
TTL
Capture/Compare/PWM 4.
CCP5
B3
H2
L1
C10
M7
A7
B7
PE5 (1)
PD2 (4)
PC4 (1)
PG7 (8)
PG5 (1)
PB6 (6)
PB5 (2)
I/O
TTL
Capture/Compare/PWM 5.
CCP6
G1
H2
M10
A12
C9
B7
PD0 (6)
PD2 (2)
PJ3 (10)
PE1 (5)
PH0 (1)
PB5 (3)
I/O
TTL
Capture/Compare/PWM 6.
CCP7
G2
H1
C8
A7
B4
PD1 (6)
PD3 (2)
PH1 (1)
PB6 (2)
PE3 (5)
I/O
TTL
Capture/Compare/PWM 7.
EPI0S0
D10
PH3 (8)
I/O
TTL
EPI module 0 signal 0.
EPI0S1
D11
PH2 (8)
I/O
TTL
EPI module 0 signal 1.
May 24, 2010
1117
Texas Instruments-Advance Information
Signal Tables
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
EPI0S2
L1
PC4 (8)
I/O
TTL
EPI module 0 signal 2.
EPI0S3
M1
PC5 (8)
I/O
TTL
EPI module 0 signal 3.
EPI0S4
M2
PC6 (8)
I/O
TTL
EPI module 0 signal 4.
EPI0S5
L2
PC7 (8)
I/O
TTL
EPI module 0 signal 5.
EPI0S6
C9
PH0 (8)
I/O
TTL
EPI module 0 signal 6.
EPI0S7
C8
PH1 (8)
I/O
TTL
EPI module 0 signal 7.
EPI0S8
B11
PE0 (8)
I/O
TTL
EPI module 0 signal 8.
EPI0S9
A12
PE1 (8)
I/O
TTL
EPI module 0 signal 9.
EPI0S10
B10
PH4 (8)
I/O
TTL
EPI module 0 signal 10.
EPI0S11
F10
PH5 (8)
I/O
TTL
EPI module 0 signal 11.
EPI0S12
K4
L9
PF7 (8)
PF4 (8)
I/O
TTL
EPI module 0 signal 12.
EPI0S13
K1
PG0 (8)
I/O
TTL
EPI module 0 signal 13.
EPI0S14
K2
PG1 (8)
I/O
TTL
EPI module 0 signal 14.
EPI0S15
K3
L8
PG4 (8)
PF5 (8)
I/O
TTL
EPI module 0 signal 15.
EPI0S16
F3
PJ0 (8)
I/O
TTL
EPI module 0 signal 16.
EPI0S17
B6
PJ1 (8)
I/O
TTL
EPI module 0 signal 17.
EPI0S18
K6
PJ2 (8)
I/O
TTL
EPI module 0 signal 18.
EPI0S19
M10
B5
PJ3 (8)
PD4 (10)
I/O
TTL
EPI module 0 signal 19.
EPI0S20
H2
PD2 (8)
I/O
TTL
EPI module 0 signal 20.
EPI0S21
H1
PD3 (8)
I/O
TTL
EPI module 0 signal 21.
EPI0S22
B7
PB5 (8)
I/O
TTL
EPI module 0 signal 22.
EPI0S23
A6
PB4 (8)
I/O
TTL
EPI module 0 signal 23.
EPI0S24
A4
PE2 (8)
I/O
TTL
EPI module 0 signal 24.
EPI0S25
B4
PE3 (8)
I/O
TTL
EPI module 0 signal 25.
EPI0S26
G3
PH6 (8)
I/O
TTL
EPI module 0 signal 26.
EPI0S27
H3
PH7 (8)
I/O
TTL
EPI module 0 signal 27.
EPI0S28
K11
C6
PJ4 (8)
PD5 (10)
I/O
TTL
EPI module 0 signal 28.
EPI0S29
K12
A3
PJ5 (8)
PD6 (10)
I/O
TTL
EPI module 0 signal 29.
EPI0S30
L10
A2
PJ6 (8)
PD7 (10)
I/O
TTL
EPI module 0 signal 30.
EPI0S31
C10
PG7 (9)
I/O
TTL
EPI module 0 signal 31.
Fault0
B2
J2
J1
K6
L9
E11
A12
D10
A3
PE4 (4)
PG3 (8)
PG2 (4)
PJ2 (10)
PF4 (4)
PB3 (2)
PE1 (3)
PH3 (2)
PD6 (1)
I
TTL
PWM Fault 0.
1118
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
Fault1
L7
M7
K3
K4
A7
PG6 (8)
PG5 (5)
PG4 (4)
PF7 (9)
PB6 (4)
I
TTL
PWM Fault 1.
Fault2
J2
M1
F10
PG3 (4)
PC5 (4)
PH5 (10)
I
TTL
PWM Fault 2.
Fault3
E11
D11
PB3 (4)
PH2 (4)
I
TTL
PWM Fault 3.
GND
C4
C5
J3
K5
K10
J10
F11
F12
fixed
-
Power
Ground reference for logic and I/O pins.
GNDA
A5
fixed
-
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
I2C0SCL
A11
PB2 (1)
I/O
OD
I2C module 0 clock.
I2C0SDA
E11
PB3 (1)
I/O
OD
I2C module 0 data.
I2C1SCL
F3
K1
L3
L6
PJ0 (11)
PG0 (3)
PA0 (8)
PA6 (1)
I/O
OD
I2C module 1 clock.
I2C1SDA
K2
M3
M6
B6
PG1 (3)
PA1 (8)
PA7 (1)
PJ1 (11)
I/O
OD
I2C module 1 data.
I2S0RXMCLK
J2
L4
C6
PG3 (9)
PA3 (9)
PD5 (8)
I/O
TTL
I2S module 0 receive master clock.
I2S0RXSCK
G1
M7
PD0 (8)
PG5 (9)
I/O
TTL
I2S module 0 receive clock.
I2S0RXSD
J1
M4
B5
PG2 (9)
PA2 (9)
PD4 (8)
I/O
TTL
I2S module 0 receive data.
I2S0RXWS
G2
L7
PD1 (8)
PG6 (9)
I/O
TTL
I2S module 0 receive word select.
I2S0TXMCLK
M8
H12
PF6 (9)
PF1 (8)
I/O
TTL
I2S module 0 transmit master clock.
I2S0TXSCK
L5
A7
A3
PA4 (9)
PB6 (9)
PD6 (8)
I/O
TTL
I2S module 0 transmit clock.
I2S0TXSD
B3
M9
PE5 (9)
PF0 (8)
I/O
TTL
I2S module 0 transmit data.
May 24, 2010
1119
Texas Instruments-Advance Information
Signal Tables
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
I2S0TXWS
B2
M5
A2
PE4 (9)
PA5 (9)
PD7 (8)
I/O
TTL
I2S module 0 transmit word select.
IDX0
G1
M7
A11
A7
A6
A2
PD0 (3)
PG5 (4)
PB2 (2)
PB6 (5)
PB4 (6)
PD7 (1)
I
TTL
QEI module 0 index.
IDX1
J1
H12
D11
PG2 (8)
PF1 (2)
PH2 (1)
I
TTL
QEI module 1 index.
LDO
E3
fixed
-
Power
NC
M12
C1
C2
D2
D1
E1
E2
F1
F2
fixed
-
-
NMI
A8
PB7 (4)
I
TTL
OSC0
L11
fixed
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
M11
fixed
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
PA0
L3
-
I/O
TTL
GPIO port A bit 0.
PA1
M3
-
I/O
TTL
GPIO port A bit 1.
PA2
M4
-
I/O
TTL
GPIO port A bit 2.
PA3
L4
-
I/O
TTL
GPIO port A bit 3.
PA4
L5
-
I/O
TTL
GPIO port A bit 4.
PA5
M5
-
I/O
TTL
GPIO port A bit 5.
PA6
L6
-
I/O
TTL
GPIO port A bit 6.
PA7
M6
-
I/O
TTL
GPIO port A bit 7.
PB0
E12
-
I/O
TTL
GPIO port B bit 0.
PB1
D12
-
I/O
TTL
GPIO port B bit 1.
PB2
A11
-
I/O
TTL
GPIO port B bit 2.
PB3
E11
-
I/O
TTL
GPIO port B bit 3.
PB4
A6
-
I/O
TTL
GPIO port B bit 4.
PB5
B7
-
I/O
TTL
GPIO port B bit 5.
PB6
A7
-
I/O
TTL
GPIO port B bit 6.
PB7
A8
-
I/O
TTL
GPIO port B bit 7.
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin must
also be connected to the VDDC pins at the board
level in addition to the decoupling capacitor(s).
No connect. Leave the pin electrically
unconnected/isolated.
Non-maskable interrupt.
1120
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PC0
A9
-
I/O
TTL
GPIO port C bit 0.
PC1
B9
-
I/O
TTL
GPIO port C bit 1.
PC2
B8
-
I/O
TTL
GPIO port C bit 2.
PC3
A10
-
I/O
TTL
GPIO port C bit 3.
PC4
L1
-
I/O
TTL
GPIO port C bit 4.
PC5
M1
-
I/O
TTL
GPIO port C bit 5.
PC6
M2
-
I/O
TTL
GPIO port C bit 6.
PC7
L2
-
I/O
TTL
GPIO port C bit 7.
PD0
G1
-
I/O
TTL
GPIO port D bit 0.
PD1
G2
-
I/O
TTL
GPIO port D bit 1.
PD2
H2
-
I/O
TTL
GPIO port D bit 2.
PD3
H1
-
I/O
TTL
GPIO port D bit 3.
PD4
B5
-
I/O
TTL
GPIO port D bit 4.
PD5
C6
-
I/O
TTL
GPIO port D bit 5.
PD6
A3
-
I/O
TTL
GPIO port D bit 6.
PD7
A2
-
I/O
TTL
GPIO port D bit 7.
PE0
B11
-
I/O
TTL
GPIO port E bit 0.
PE1
A12
-
I/O
TTL
GPIO port E bit 1.
PE2
A4
-
I/O
TTL
GPIO port E bit 2.
PE3
B4
-
I/O
TTL
GPIO port E bit 3.
PE4
B2
-
I/O
TTL
GPIO port E bit 4.
PE5
B3
-
I/O
TTL
GPIO port E bit 5.
PE6
A1
-
I/O
TTL
GPIO port E bit 6.
PE7
B1
-
I/O
TTL
GPIO port E bit 7.
PF0
M9
-
I/O
TTL
GPIO port F bit 0.
PF1
H12
-
I/O
TTL
GPIO port F bit 1.
PF2
J11
-
I/O
TTL
GPIO port F bit 2.
PF3
J12
-
I/O
TTL
GPIO port F bit 3.
PF4
L9
-
I/O
TTL
GPIO port F bit 4.
PF5
L8
-
I/O
TTL
GPIO port F bit 5.
PF6
M8
-
I/O
TTL
GPIO port F bit 6.
PF7
K4
-
I/O
TTL
GPIO port F bit 7.
PG0
K1
-
I/O
TTL
GPIO port G bit 0.
PG1
K2
-
I/O
TTL
GPIO port G bit 1.
PG2
J1
-
I/O
TTL
GPIO port G bit 2.
PG3
J2
-
I/O
TTL
GPIO port G bit 3.
PG4
K3
-
I/O
TTL
GPIO port G bit 4.
PG5
M7
-
I/O
TTL
GPIO port G bit 5.
PG6
L7
-
I/O
TTL
GPIO port G bit 6.
PG7
C10
-
I/O
TTL
GPIO port G bit 7.
PH0
C9
-
I/O
TTL
GPIO port H bit 0.
May 24, 2010
1121
Texas Instruments-Advance Information
Signal Tables
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
C8
-
I/O
TTL
GPIO port H bit 1.
PH2
D11
-
I/O
TTL
GPIO port H bit 2.
PH3
D10
-
I/O
TTL
GPIO port H bit 3.
PH4
B10
-
I/O
TTL
GPIO port H bit 4.
PH5
F10
-
I/O
TTL
GPIO port H bit 5.
PH6
G3
-
I/O
TTL
GPIO port H bit 6.
PH1
PH7
H3
-
I/O
TTL
GPIO port H bit 7.
PhA0
G2
L1
M8
A4
PD1 (3)
PC4 (2)
PF6 (4)
PE2 (4)
I
TTL
QEI module 0 phase A.
PhA1
L7
B4
PG6 (1)
PE3 (3)
I
TTL
QEI module 1 phase A.
PhB0
L2
M2
K4
M9
D10
B4
PC7 (2)
PC6 (2)
PF7 (4)
PF0 (2)
PH3 (1)
PE3 (4)
I
TTL
QEI module 0 phase B.
PhB1
G2
C10
A4
PD1 (11)
PG7 (1)
PE2 (3)
I
TTL
QEI module 1 phase B.
PJ0
F3
-
I/O
TTL
GPIO port J bit 0.
PJ1
B6
-
I/O
TTL
GPIO port J bit 1.
PJ2
K6
-
I/O
TTL
GPIO port J bit 2.
PJ3
M10
-
I/O
TTL
GPIO port J bit 3.
PJ4
K11
-
I/O
TTL
GPIO port J bit 4.
PJ5
K12
-
I/O
TTL
GPIO port J bit 5.
PJ6
L10
-
I/O
TTL
GPIO port J bit 6.
PJ7
L12
-
I/O
TTL
GPIO port J bit 7.
PWM0
G1
F3
J1
K1
L6
M9
PD0 (1)
PJ0 (10)
PG2 (1)
PG0 (2)
PA6 (4)
PF0 (3)
O
TTL
PWM 0. This signal is controlled by PWM Generator
0.
PWM1
G2
J2
K2
M6
H12
B6
PD1 (1)
PG3 (1)
PG1 (2)
PA7 (4)
PF1 (3)
PJ1 (10)
O
TTL
PWM 1. This signal is controlled by PWM Generator
0.
PWM2
H2
J11
E12
C9
PD2 (3)
PF2 (4)
PB0 (2)
PH0 (2)
O
TTL
PWM 2. This signal is controlled by PWM Generator
1.
1122
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
PWM3
H1
J12
D12
C8
PD3 (3)
PF3 (4)
PB1 (2)
PH1 (2)
O
TTL
PWM 3. This signal is controlled by PWM Generator
1.
PWM4
A1
K1
M4
L6
J11
G3
B11
C9
PE6 (1)
PG0 (4)
PA2 (4)
PA6 (5)
PF2 (2)
PH6 (10)
PE0 (1)
PH0 (9)
O
TTL
PWM 4. This signal is controlled by PWM Generator
2.
PWM5
B1
H3
K2
L4
M6
J12
A12
C8
PE7 (1)
PH7 (10)
PG1 (4)
PA3 (4)
PA7 (5)
PF3 (2)
PE1 (1)
PH1 (9)
O
TTL
PWM 5. This signal is controlled by PWM Generator
2.
PWM6
L1
L5
L7
K3
PC4 (4)
PA4 (4)
PG6 (4)
PG4 (9)
O
TTL
PWM 6. This signal is controlled by PWM Generator
3.
PWM7
M2
M5
C10
M7
PC6 (4)
PA5 (4)
PG7 (4)
PG5 (8)
O
TTL
PWM 7. This signal is controlled by PWM Generator
3.
RST
H11
fixed
I
TTL
System reset input.
SSI0Clk
M4
PA2 (1)
I/O
TTL
SSI module 0 clock.
SSI0Fss
L4
PA3 (1)
I/O
TTL
SSI module 0 frame.
SSI0Rx
L5
PA4 (1)
I
TTL
SSI module 0 receive.
SSI0Tx
M5
PA5 (1)
O
TTL
SSI module 0 transmit.
SSI1Clk
J11
B11
B10
PF2 (9)
PE0 (2)
PH4 (11)
I/O
TTL
SSI module 1 clock.
SSI1Fss
J12
F10
A12
PF3 (9)
PH5 (11)
PE1 (2)
I/O
TTL
SSI module 1 frame.
SSI1Rx
L9
G3
A4
PF4 (9)
PH6 (11)
PE2 (2)
I
TTL
SSI module 1 receive.
SSI1Tx
H3
L8
B4
PH7 (11)
PF5 (9)
PE3 (2)
O
TTL
SSI module 1 transmit.
SWCLK
A9
PC0 (3)
I
TTL
JTAG/SWD CLK.
SWDIO
B9
PC1 (3)
I/O
TTL
JTAG TMS and SWDIO.
SWO
A10
PC3 (3)
O
TTL
JTAG TDO and SWO.
TCK
A9
PC0 (3)
I
TTL
JTAG/SWD CLK.
TDI
B8
PC2 (3)
I
TTL
JTAG TDI.
May 24, 2010
1123
Texas Instruments-Advance Information
Signal Tables
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
TDO
A10
PC3 (3)
O
TTL
JTAG TDO and SWO.
TMS
B9
PC1 (3)
I
TTL
JTAG TMS and SWDIO.
U0Rx
L3
PA0 (1)
I
TTL
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx
M3
PA1 (1)
O
TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1CTS
A1
G1
L6
M10
PE6 (9)
PD0 (9)
PA6 (9)
PJ3 (9)
I
TTL
UART module 1 Clear To Send modem status input
signal.
U1DCD
B1
G2
M6
K11
PE7 (9)
PD1 (9)
PA7 (9)
PJ4 (9)
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
M9
K12
PF0 (9)
PJ5 (9)
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
M7
L12
A2
PG5 (10)
PJ7 (9)
PD7 (9)
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
L7
K3
B5
PG6 (10)
PG4 (10)
PD4 (9)
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
M8
L10
H12
PF6 (10)
PJ6 (9)
PF1 (9)
O
TTL
UART module 1 Request to Send modem output
control line.
U1Rx
G1
H2
M2
L3
E12
A6
PD0 (5)
PD2 (1)
PC6 (5)
PA0 (9)
PB0 (5)
PB4 (7)
I
TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Tx
G2
H1
L2
M3
D12
B7
PD1 (5)
PD3 (1)
PC7 (5)
PA1 (9)
PB1 (5)
PB5 (7)
O
TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx
G1
K1
A6
C6
PD0 (4)
PG0 (1)
PB4 (4)
PD5 (9)
I
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx
B2
G2
K2
A3
PE4 (5)
PD1 (4)
PG1 (1)
PD6 (9)
O
TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
USB0DM
C11
fixed
I/O
Analog
Bidirectional differential data pin (D- per USB
specification).
USB0DP
C12
fixed
I/O
Analog
Bidirectional differential data pin (D+ per USB
specification).
1124
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
USB0EPEN
K1
M1
L6
A11
D10
PG0 (7)
PC5 (6)
PA6 (8)
PB2 (8)
PH3 (4)
O
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
E12
PB0
I
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
USB0PFLT
L2
M2
M6
E11
B11
B10
B6
PC7 (6)
PC6 (7)
PA7 (8)
PB3 (8)
PE0 (9)
PH4 (4)
PJ1 (9)
I
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0RBIAS
B12
fixed
O
Analog
9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
USB0VBUS
D12
PB1
I/O
Analog
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
VDD
K7
G12
K8
K9
H10
G10
E10
G11
fixed
-
Power
Positive supply for I/O and some logic.
VDDA
C7
fixed
-
Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
VDDC
D3
C3
fixed
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VREFA
A7
PB6
I
Analog
This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 1023. The VREFA
input is limited to the range specified in Table
26-2 on page 1142.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
May 24, 2010
1125
Texas Instruments-Advance Information
Signal Tables
Table 24-9. Signals by Function, Except for GPIO
Function
ADC
Analog Comparators
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
AIN0
B1
I
Analog
Analog-to-digital converter input 0.
AIN1
A1
I
Analog
Analog-to-digital converter input 1.
AIN2
B3
I
Analog
Analog-to-digital converter input 2.
AIN3
B2
I
Analog
Analog-to-digital converter input 3.
AIN4
A2
I
Analog
Analog-to-digital converter input 4.
AIN5
A3
I
Analog
Analog-to-digital converter input 5.
AIN6
C6
I
Analog
Analog-to-digital converter input 6.
AIN7
B5
I
Analog
Analog-to-digital converter input 7.
AIN8
B4
I
Analog
Analog-to-digital converter input 8.
AIN9
A4
I
Analog
Analog-to-digital converter input 9.
AIN10
A6
I
Analog
Analog-to-digital converter input 10.
AIN11
B7
I
Analog
Analog-to-digital converter input 11.
AIN12
H1
I
Analog
Analog-to-digital converter input 12.
AIN13
H2
I
Analog
Analog-to-digital converter input 13.
AIN14
G2
I
Analog
Analog-to-digital converter input 14.
AIN15
G1
I
Analog
Analog-to-digital converter input 15.
VREFA
A7
I
Analog
This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 1023. The VREFA
input is limited to the range specified in Table
26-2 on page 1142.
C0+
A7
I
Analog
Analog comparator 0 positive input.
Analog comparator 0 negative input.
C0-
A6
I
Analog
C0o
M1
L9
A7
B7
A2
O
TTL
C1+
M1
I
Analog
Analog comparator 1 positive input.
C1-
B7
I
Analog
Analog comparator 1 negative input.
C1o
A1
L2
M1
L8
D11
O
TTL
C2+
M2
I
Analog
Analog comparator 2 positive input.
C2-
L2
I
Analog
Analog comparator 2 negative input.
C2o
B1
M2
M8
O
TTL
Analog comparator 0 output.
Analog comparator 1 output.
Analog comparator 2 output.
1126
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-9. Signals by Function, Except for GPIO (continued)
Function
Controller Area
Network
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
CAN0Rx
G1
L5
L6
A6
I
TTL
CAN module 0 receive.
CAN0Tx
G2
M5
M6
B7
O
TTL
CAN module 0 transmit.
CAN1Rx
M9
I
TTL
CAN module 1 receive.
CAN1Tx
H12
O
TTL
CAN module 1 transmit.
May 24, 2010
1127
Texas Instruments-Advance Information
Signal Tables
Table 24-9. Signals by Function, Except for GPIO (continued)
Function
External Peripheral
Interface
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
EPI0S0
D10
I/O
TTL
EPI module 0 signal 0.
EPI0S1
D11
I/O
TTL
EPI module 0 signal 1.
EPI0S2
L1
I/O
TTL
EPI module 0 signal 2.
EPI0S3
M1
I/O
TTL
EPI module 0 signal 3.
EPI0S4
M2
I/O
TTL
EPI module 0 signal 4.
EPI0S5
L2
I/O
TTL
EPI module 0 signal 5.
EPI0S6
C9
I/O
TTL
EPI module 0 signal 6.
EPI0S7
C8
I/O
TTL
EPI module 0 signal 7.
EPI0S8
B11
I/O
TTL
EPI module 0 signal 8.
EPI0S9
A12
I/O
TTL
EPI module 0 signal 9.
EPI0S10
B10
I/O
TTL
EPI module 0 signal 10.
EPI0S11
F10
I/O
TTL
EPI module 0 signal 11.
EPI0S12
K4
L9
I/O
TTL
EPI module 0 signal 12.
EPI0S13
K1
I/O
TTL
EPI module 0 signal 13.
EPI0S14
K2
I/O
TTL
EPI module 0 signal 14.
EPI0S15
K3
L8
I/O
TTL
EPI module 0 signal 15.
EPI0S16
F3
I/O
TTL
EPI module 0 signal 16.
EPI0S17
B6
I/O
TTL
EPI module 0 signal 17.
EPI0S18
K6
I/O
TTL
EPI module 0 signal 18.
EPI0S19
M10
B5
I/O
TTL
EPI module 0 signal 19.
EPI0S20
H2
I/O
TTL
EPI module 0 signal 20.
EPI0S21
H1
I/O
TTL
EPI module 0 signal 21.
EPI0S22
B7
I/O
TTL
EPI module 0 signal 22.
EPI0S23
A6
I/O
TTL
EPI module 0 signal 23.
EPI0S24
A4
I/O
TTL
EPI module 0 signal 24.
EPI0S25
B4
I/O
TTL
EPI module 0 signal 25.
EPI0S26
G3
I/O
TTL
EPI module 0 signal 26.
EPI0S27
H3
I/O
TTL
EPI module 0 signal 27.
EPI0S28
K11
C6
I/O
TTL
EPI module 0 signal 28.
EPI0S29
K12
A3
I/O
TTL
EPI module 0 signal 29.
EPI0S30
L10
A2
I/O
TTL
EPI module 0 signal 30.
EPI0S31
C10
I/O
TTL
EPI module 0 signal 31.
1128
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-9. Signals by Function, Except for GPIO (continued)
Function
General-Purpose
Timers
Pin Name
a
Pin Number
Pin Type
Buffer Type
CCP0
H1
L2
M2
K6
L12
L9
E12
A11
B7
B5
I/O
TTL
Capture/Compare/PWM 0.
CCP1
M1
L1
L6
M8
L10
D12
A7
B4
A2
I/O
TTL
Capture/Compare/PWM 1.
CCP2
B2
G2
L1
L8
K12
D12
A12
B7
A4
C6
I/O
TTL
Capture/Compare/PWM 2.
CCP3
B2
M2
M1
M6
K3
H12
A11
B11
B5
I/O
TTL
Capture/Compare/PWM 3.
CCP4
L2
L1
M6
K4
K11
A4
C6
I/O
TTL
Capture/Compare/PWM 4.
CCP5
B3
H2
L1
C10
M7
A7
B7
I/O
TTL
Capture/Compare/PWM 5.
I/O
TTL
Capture/Compare/PWM 6.
CCP6
Description
May 24, 2010
1129
Texas Instruments-Advance Information
Signal Tables
Table 24-9. Signals by Function, Except for GPIO (continued)
Function
Pin Name
Pin Number
a
Pin Type
Buffer Type
Description
G1
H2
M10
A12
C9
B7
I2C
I2S
JTAG/SWD/SWO
CCP7
G2
H1
C8
A7
B4
I/O
TTL
Capture/Compare/PWM 7.
I2C0SCL
A11
I/O
OD
I2C module 0 clock.
I2C0SDA
E11
I/O
OD
I2C module 0 data.
I2C1SCL
F3
K1
L3
L6
I/O
OD
I2C module 1 clock.
I2C1SDA
K2
M3
M6
B6
I/O
OD
I2C module 1 data.
I2S0RXMCLK
J2
L4
C6
I/O
TTL
I2S module 0 receive master clock.
I2S0RXSCK
G1
M7
I/O
TTL
I2S module 0 receive clock.
I2S0RXSD
J1
M4
B5
I/O
TTL
I2S module 0 receive data.
I2S0RXWS
G2
L7
I/O
TTL
I2S module 0 receive word select.
I2S0TXMCLK
M8
H12
I/O
TTL
I2S module 0 transmit master clock.
I2S0TXSCK
L5
A7
A3
I/O
TTL
I2S module 0 transmit clock.
I2S0TXSD
B3
M9
I/O
TTL
I2S module 0 transmit data.
I2S0TXWS
B2
M5
A2
I/O
TTL
I2S module 0 transmit word select.
SWCLK
A9
I
TTL
JTAG/SWD CLK.
SWDIO
B9
I/O
TTL
JTAG TMS and SWDIO.
SWO
A10
O
TTL
JTAG TDO and SWO.
TCK
A9
I
TTL
JTAG/SWD CLK.
TDI
B8
I
TTL
JTAG TDI.
TDO
A10
O
TTL
JTAG TDO and SWO.
TMS
B9
I
TTL
JTAG TMS and SWDIO.
1130
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-9. Signals by Function, Except for GPIO (continued)
Function
PWM
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
Fault0
B2
J2
J1
K6
L9
E11
A12
D10
A3
I
TTL
PWM Fault 0.
Fault1
L7
M7
K3
K4
A7
I
TTL
PWM Fault 1.
Fault2
J2
M1
F10
I
TTL
PWM Fault 2.
Fault3
E11
D11
I
TTL
PWM Fault 3.
PWM0
G1
F3
J1
K1
L6
M9
O
TTL
PWM 0. This signal is controlled by PWM Generator
0.
PWM1
G2
J2
K2
M6
H12
B6
O
TTL
PWM 1. This signal is controlled by PWM Generator
0.
PWM2
H2
J11
E12
C9
O
TTL
PWM 2. This signal is controlled by PWM Generator
1.
PWM3
H1
J12
D12
C8
O
TTL
PWM 3. This signal is controlled by PWM Generator
1.
PWM4
A1
K1
M4
L6
J11
G3
B11
C9
O
TTL
PWM 4. This signal is controlled by PWM Generator
2.
PWM5
B1
H3
K2
L4
M6
J12
A12
C8
O
TTL
PWM 5. This signal is controlled by PWM Generator
2.
May 24, 2010
1131
Texas Instruments-Advance Information
Signal Tables
Table 24-9. Signals by Function, Except for GPIO (continued)
Function
Power
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
PWM6
L1
L5
L7
K3
O
TTL
PWM 6. This signal is controlled by PWM Generator
3.
PWM7
M2
M5
C10
M7
O
TTL
PWM 7. This signal is controlled by PWM Generator
3.
GND
C4
C5
J3
K5
K10
J10
F11
F12
-
Power
Ground reference for logic and I/O pins.
GNDA
A5
-
Power
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
LDO
E3
-
Power
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin must
also be connected to the VDDC pins at the board
level in addition to the decoupling capacitor(s).
VDD
K7
G12
K8
K9
H10
G10
E10
G11
-
Power
Positive supply for I/O and some logic.
VDDA
C7
-
Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
VDDC
D3
C3
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
1132
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-9. Signals by Function, Except for GPIO (continued)
Function
QEI
SSI
System Control &
Clocks
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
IDX0
G1
M7
A11
A7
A6
A2
I
TTL
QEI module 0 index.
IDX1
J1
H12
D11
I
TTL
QEI module 1 index.
PhA0
G2
L1
M8
A4
I
TTL
QEI module 0 phase A.
PhA1
L7
B4
I
TTL
QEI module 1 phase A.
PhB0
L2
M2
K4
M9
D10
B4
I
TTL
QEI module 0 phase B.
PhB1
G2
C10
A4
I
TTL
QEI module 1 phase B.
SSI0Clk
M4
I/O
TTL
SSI module 0 clock.
SSI0Fss
L4
I/O
TTL
SSI module 0 frame.
SSI0Rx
L5
I
TTL
SSI module 0 receive.
SSI0Tx
M5
O
TTL
SSI module 0 transmit.
SSI1Clk
J11
B11
B10
I/O
TTL
SSI module 1 clock.
SSI1Fss
J12
F10
A12
I/O
TTL
SSI module 1 frame.
SSI1Rx
L9
G3
A4
I
TTL
SSI module 1 receive.
SSI1Tx
H3
L8
B4
O
TTL
SSI module 1 transmit.
NMI
A8
I
TTL
Non-maskable interrupt.
OSC0
L11
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
M11
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
H11
I
TTL
System reset input.
May 24, 2010
1133
Texas Instruments-Advance Information
Signal Tables
Table 24-9. Signals by Function, Except for GPIO (continued)
Function
UART
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
U0Rx
L3
I
TTL
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx
M3
O
TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1CTS
A1
G1
L6
M10
I
TTL
UART module 1 Clear To Send modem status input
signal.
U1DCD
B1
G2
M6
K11
I
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
M9
K12
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
M7
L12
A2
O
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
L7
K3
B5
I
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
M8
L10
H12
O
TTL
UART module 1 Request to Send modem output
control line.
U1Rx
G1
H2
M2
L3
E12
A6
I
TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Tx
G2
H1
L2
M3
D12
B7
O
TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx
G1
K1
A6
C6
I
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx
B2
G2
K2
A3
O
TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
1134
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-9. Signals by Function, Except for GPIO (continued)
Function
USB
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
USB0DM
C11
I/O
Analog
Bidirectional differential data pin (D- per USB
specification).
USB0DP
C12
I/O
Analog
Bidirectional differential data pin (D+ per USB
specification).
USB0EPEN
K1
M1
L6
A11
D10
O
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
E12
I
Analog
This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
USB0PFLT
L2
M2
M6
E11
B11
B10
B6
I
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0RBIAS
B12
O
Analog
9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
USB0VBUS
D12
I/O
Analog
This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 24-10. GPIO Pins and Alternate Functions
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
U0Rx
-
-
-
-
-
-
I2C1SCL
U1Rx
-
-
-
U0Tx
-
-
-
-
-
-
I2C1SDA
U1Tx
-
-
-
SSI0Clk
-
-
PWM4
-
-
-
-
I2S0RXSD
-
-
PA3 L4
-
SSI0Fss
-
-
PWM5
-
-
-
-
I2S0RXMCLK
-
-
PA4 L5
-
SSI0Rx
-
-
PWM6
CAN0Rx
-
-
-
I2S0TXSCK
-
-
PA5 M5
-
SSI0Tx
-
-
PWM7
CAN0Tx
-
-
-
I2S0TXWS
-
-
PA6 L6
-
I2C1SCL
CCP1
-
PWM0
PWM4
CAN0Rx
-
USB0EPEN
U1CTS
-
-
PA7 M6
-
I2C1SDA
CCP4
-
PWM1
PWM5
CAN0Tx
CCP3
USB0PFLT
U1DCD
-
-
CCP0
PWM2
-
-
U1Rx
-
-
-
-
-
-
PA0 L3
-
PA1 M3
PA2 M4
PB0 E12 USB0ID
PB1 D12 USB0VBUS
CCP2
PWM3
-
CCP1
U1Tx
-
-
-
-
-
-
PB2 A11
-
I2C0SCL
IDX0
-
CCP3
CCP0
-
-
USB0EPEN
-
-
-
PB3 E11
-
I2C0SDA Fault0
-
Fault3
-
-
-
USB0PFLT
-
-
-
PB4 A6
AIN10
C0-
-
-
-
U2Rx
CAN0Rx
IDX0
U1Rx
EPI0S23
-
-
-
PB5 B7
AIN11
C1-
C0o
CCP5
CCP6
CCP0
CAN0Tx
CCP2
U1Tx
EPI0S22
-
-
-
May 24, 2010
1135
Texas Instruments-Advance Information
Signal Tables
Table 24-10. GPIO Pins and Alternate Functions (continued)
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PB6 A7
VREFA
C0+
CCP1
CCP7
C0o
Fault1
IDX0
CCP5
-
-
I2S0TXSCK
-
-
PB7 A8
-
-
-
-
NMI
-
-
-
-
-
-
-
PC0 A9
-
-
-
TCK
SWCLK
-
-
-
-
-
-
-
-
PC1 B9
-
-
-
TMS
SWDIO
-
-
-
-
-
-
-
-
PC2 B8
-
-
-
TDI
-
-
-
-
-
-
-
-
PC3 A10
-
-
-
TDO SWO
-
-
-
-
-
-
-
-
PC4 L1
-
CCP5
PhA0
-
PWM6
CCP2
CCP4
-
EPI0S2
CCP1
-
-
PC5 M1
C1+
CCP1
C1o
C0o
Fault2
CCP3
USB0EPEN
-
EPI0S3
-
-
-
PC6 M2
C2+
CCP3
PhB0
C2o
PWM7
U1Rx
CCP0
USB0PFLT EPI0S4
-
-
-
PC7 L2
C2-
CCP4
PhB0
-
CCP0
U1Tx
USB0PFLT
C1o
-
-
-
PD0 G1
AIN15
PWM0
CAN0Rx
IDX0
U2Rx
U1Rx
CCP6
-
I2S0RXSCK U1CTS
-
-
PD1 G2
AIN14
PWM1
CAN0Tx
PhA0
U2Tx
U1Tx
CCP7
-
I2S0RXWS
U1DCD
CCP2
PhB1
PD2 H2
AIN13
U1Rx
CCP6
PWM2
CCP5
-
-
-
EPI0S20
-
-
-
PD3 H1
AIN12
U1Tx
CCP7
PWM3
CCP0
-
-
-
EPI0S21
-
-
-
PD4 B5
AIN7
CCP0
CCP3
-
-
-
-
-
I2S0RXSD
U1RI
EPI0S19
-
PD5 C6
AIN6
CCP2
CCP4
-
-
-
-
-
I2S0RXMCLK
U2Rx
EPI0S28
-
PD6 A3
AIN5
Fault0
-
-
-
-
-
-
I2S0TXSCK
U2Tx
EPI0S29
-
PD7 A2
AIN4
IDX0
C0o
CCP1
-
-
-
-
I2S0TXWS
U1DTR
EPI0S30
-
PE0 B11
-
PWM4
SSI1Clk
CCP3
-
-
-
-
EPI0S8 USB0PFLT
-
-
PE1 A12
-
PWM5
SSI1Fss Fault0
CCP2
CCP6
-
-
EPI0S9
-
-
-
PE2 A4
AIN9
CCP4
SSI1Rx
PhB1
PhA0
CCP2
-
-
EPI0S24
-
-
-
PE3 B4
AIN8
CCP1
SSI1Tx
PhA1
PhB0
CCP7
-
-
EPI0S25
-
-
-
PE4 B2
AIN3
CCP3
-
-
Fault0
U2Tx
CCP2
-
-
I2S0TXWS
-
-
PE5 B3
AIN2
CCP5
-
-
-
-
-
-
-
I2S0TXSD
-
-
PE6 A1
AIN1
PWM4
C1o
-
-
-
-
-
-
U1CTS
-
-
PE7 B1
AIN0
PWM5
C2o
-
-
-
-
-
-
U1DCD
-
-
PF0 M9
-
CAN1Rx
PhB0
PWM0
-
-
-
-
I2S0TXSD
U1DSR
PF1 H12
-
CAN1Tx
IDX1
PWM1
-
-
-
-
I2S0TXMCLK U1RTS
PF2 J11
-
-
PWM4
-
PWM2
-
-
-
PF3 J12
-
-
PWM5
-
PWM3
-
-
-
PF4 L9
-
CCP0
C0o
-
Fault0
-
-
-
PF5 L8
-
CCP2
C1o
-
-
-
-
-
EPI0S15 SSI1Tx
PF6 M8
-
CCP1
C2o
-
PhA0
-
-
-
PF7 K4
-
CCP4
-
-
PhB0
-
-
-
PG0 K1
-
U2Rx
PWM0
I2C1SCL
PWM4
-
-
PG1 K2
-
U2Tx
PWM1
I2C1SDA
PWM5
-
-
-
PG2 J1
-
PWM0
-
-
Fault0
-
-
-
PG3 J2
-
PWM1
-
-
Fault2
-
-
-
EPI0S5
-
-
SSI1Clk
-
-
-
SSI1Fss
-
-
EPI0S12 SSI1Rx
-
-
-
-
-
I2S0TXMCLK U1RTS
EPI0S12 Fault1
-
-
-
-
-
-
EPI0S14
-
-
-
IDX1
I2S0RXSD
-
-
Fault0 I2S0RXMCLK
-
-
USB0EPEN EPI0S13
1136
CCP3
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-10. GPIO Pins and Alternate Functions (continued)
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PG4 K3
-
CCP3
-
-
Fault1
-
-
-
EPI0S15
PWM6
U1RI
-
PG5 M7
-
CCP5
-
-
IDX0
Fault1
-
-
PWM7
PG6 L7
-
PhA1
-
-
PWM6
-
-
-
U1RI
-
PG7 C10
-
PhB1
-
-
PWM7
-
-
-
CCP5
EPI0S31
-
-
PH0 C9
-
CCP6
PWM2
-
-
-
-
-
EPI0S6
PWM4
-
-
PH1 C8
-
CCP7
PWM3
-
-
-
-
-
EPI0S7
PWM5
-
-
PH2 D11
-
IDX1
C1o
-
Fault3
-
-
-
EPI0S1
-
-
-
PH3 D10
-
PhB0
Fault0
-
USB0EPEN
-
-
-
EPI0S0
-
-
-
PH4 B10
-
-
-
-
USB0PFLT
-
-
-
EPI0S10
-
-
SSI1Clk
PH5 F10
-
-
-
-
-
-
-
-
EPI0S11
-
PH6 G3
-
-
-
-
-
-
-
-
EPI0S26
-
PWM4
SSI1Rx
PH7 H3
-
-
-
-
-
-
-
-
EPI0S27
-
PWM5
SSI1Tx
PJ0 F3
-
-
-
-
-
-
-
-
EPI0S16
-
PWM0
I2C1SCL
PJ1 B6
-
-
-
-
-
-
-
-
EPI0S17 USB0PFLT
PWM1
I2C1SDA
PJ2 K6
-
-
-
-
-
-
-
-
EPI0S18
CCP0
Fault0
-
PJ3 M10
-
-
-
-
-
-
-
-
EPI0S19
U1CTS
CCP6
-
PJ4 K11
-
-
-
-
-
-
-
-
EPI0S28
U1DCD
CCP4
-
PJ5 K12
-
-
-
-
-
-
-
-
EPI0S29
U1DSR
CCP2
-
PJ6 L10
-
-
-
-
-
-
-
-
EPI0S30
U1RTS
CCP1
-
PJ7 L12
-
-
-
-
-
-
-
-
-
U1DTR
CCP0
-
I2S0RXSCK U1DTR
Fault1 I2S0RXWS
-
Fault2 SSI1Fss
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin.
May 24, 2010
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Texas Instruments-Advance Information
Signal Tables
Table 24-11. Possible Pin Assignments for Alternate Functions
# of Possible Assignments
Alternate Function
GPIO Function
one
AIN0
PE7
AIN1
PE6
AIN10
PB4
AIN11
PB5
AIN12
PD3
AIN13
PD2
AIN14
PD1
AIN15
PD0
AIN2
PE5
AIN3
PE4
AIN4
PD7
AIN5
PD6
AIN6
PD5
AIN7
PD4
AIN8
PE3
AIN9
PE2
C0+
PB6
C0-
PB4
C1+
PC5
C1-
PB5
C2+
PC6
C2-
PC7
CAN1Rx
PF0
CAN1Tx
PF1
I2C0SCL
PB2
I2C0SDA
PB3
NMI
PB7
SSI0Clk
PA2
SSI0Fss
PA3
SSI0Rx
PA4
SSI0Tx
PA5
SWCLK
PC0
SWDIO
PC1
SWO
PC3
TCK
PC0
TDI
PC2
TDO
PC3
TMS
PC1
U0Rx
PA0
U0Tx
PA1
USB0ID
PB0
1138
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 24-11. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
two
three
four
Alternate Function
GPIO Function
USB0VBUS
PB1
VREFA
PB6
Fault3
PB3 PH2
I2S0RXSCK
PD0 PG5
I2S0RXWS
PD1 PG6
I2S0TXMCLK
PF6 PF1
I2S0TXSD
PE5 PF0
PhA1
PG6 PE3
U1DSR
PF0 PJ5
C2o
PE7 PC6 PF6
Fault2
PG3 PC5 PH5
I2S0RXMCLK
PG3 PA3 PD5
I2S0RXSD
PG2 PA2 PD4
I2S0TXSCK
PA4 PB6 PD6
I2S0TXWS
PE4 PA5 PD7
IDX1
PG2 PF1 PH2
PhB1
PD1 PG7 PE2
SSI1Clk
PF2 PE0 PH4
SSI1Fss
PF3 PH5 PE1
SSI1Rx
PF4 PH6 PE2
SSI1Tx
PH7 PF5 PE3
U1DTR
PG5 PJ7 PD7
U1RI
PG6 PG4 PD4
U1RTS
PF6 PJ6 PF1
CAN0Rx
PD0 PA4 PA6 PB4
CAN0Tx
PD1 PA5 PA7 PB5
I2C1SCL
PJ0 PG0 PA0 PA6
I2C1SDA
PG1 PA1 PA7 PJ1
PWM2
PD2 PF2 PB0 PH0
PWM3
PD3 PF3 PB1 PH1
PWM6
PC4 PA4 PG6 PG4
PWM7
PC6 PA5 PG7 PG5
PhA0
PD1 PC4 PF6 PE2
U1CTS
PE6 PD0 PA6 PJ3
U1DCD
PE7 PD1 PA7 PJ4
U2Rx
PD0 PG0 PB4 PD5
U2Tx
PE4 PD1 PG1 PD6
May 24, 2010
1139
Texas Instruments-Advance Information
Signal Tables
Table 24-11. Possible Pin Assignments for Alternate Functions (continued)
# of Possible Assignments
Alternate Function
five
C0o
PC5 PF4 PB6 PB5 PD7
C1o
PE6 PC7 PC5 PF5 PH2
six
seven
eight
nine
ten
GPIO Function
CCP7
PD1 PD3 PH1 PB6 PE3
Fault1
PG6 PG5 PG4 PF7 PB6
USB0EPEN
PG0 PC5 PA6 PB2 PH3
CCP6
PD0 PD2 PJ3 PE1 PH0 PB5
IDX0
PD0 PG5 PB2 PB6 PB4 PD7
PWM0
PD0 PJ0 PG2 PG0 PA6 PF0
PWM1
PD1 PG3 PG1 PA7 PF1 PJ1
PhB0
PC7 PC6 PF7 PF0 PH3 PE3
U1Rx
PD0 PD2 PC6 PA0 PB0 PB4
U1Tx
PD1 PD3 PC7 PA1 PB1 PB5
CCP4
PC7 PC4 PA7 PF7 PJ4 PE2 PD5
CCP5
PE5 PD2 PC4 PG7 PG5 PB6 PB5
USB0PFLT
PC7 PC6 PA7 PB3 PE0 PH4 PJ1
PWM4
PE6 PG0 PA2 PA6 PF2 PH6 PE0 PH0
PWM5
PE7 PH7 PG1 PA3 PA7 PF3 PE1 PH1
CCP1
PC5 PC4 PA6 PF6 PJ6 PB1 PB6 PE3 PD7
CCP3
PE4 PC6 PC5 PA7 PG4 PF1 PB2 PE0 PD4
Fault0
PE4 PG3 PG2 PJ2 PF4 PB3 PE1 PH3 PD6
CCP0
PD3 PC7 PC6 PJ2 PJ7 PF4 PB0 PB2 PB5 PD4
CCP2
PE4 PD1 PC4 PF5 PJ5 PB1 PE1 PB5 PE2 PD5
1140
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
25
Operating Characteristics
Table 25-1. Temperature Characteristics
Characteristic
Symbol Value
Unit
Industrial operating temperature range TA
-40 to +85
°C
Unpowered storage temperature range TS
-65 to +150
°C
Table 25-2. Thermal Characteristics
Characteristic
Symbol Value
a
Thermal resistance (junction to ambient) ΘJA
b
Average junction temperature
Unit
34
TJ
°C/W
TA + (PAVG • ΘJA)
°C
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
a
Table 25-3. ESD Absolute Maximum Ratings
Parameter Name
Min
Nom
Max
Unit
VESDHBM
-
-
2.0
kV
VESDCDM
-
-
1.0
kV
VESDMM
-
-
100
V
a. All Stellaris parts are ESD tested following the JEDEC standard.
May 24, 2010
1141
Texas Instruments-Advance Information
Electrical Characteristics
26
Electrical Characteristics
26.1
DC Characteristics
26.1.1
Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note:
The device is not guaranteed to operate properly at the maximum ratings.
Table 26-1. Maximum Ratings
Parameter
a
Parameter Name
VDD
I/O supply voltage (VDD)
VDDA
Analog supply voltage (VDDA)
VIN
I
Value
Input voltage
Unit
Min
Max
0
4
V
0
4
V
-0.3
5.5
V
-
25
mA
Maximum current per output pins
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
26.1.2
Recommended DC Operating Conditions
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
Table 26-2. Recommended DC Operating Conditions
Parameter
Parameter Name
Min
Nom
Max
Unit
VDD
I/O supply voltage
3.0
3.3
3.6
V
VDDA
Analog supply voltage
3.0
3.3
3.6
V
Core supply voltage
1.08
1.2
1.32
V
a
VDDC
VIH
High-level input voltage
2.0
-
5.0
V
VIL
Low-level input voltage
-0.3
-
1.3
V
b
VOH
High-level output voltage
2.4
-
-
V
VOLa
Low-level output voltage
-
-
0.4
V
1142
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 26-2. Recommended DC Operating Conditions (continued)
Parameter
IOH
IOL
Parameter Name
Min
Nom
Max
Unit
2-mA Drive
2.0
-
-
mA
4-mA Drive
4.0
-
-
mA
8-mA Drive
8.0
-
-
mA
2-mA Drive
2.0
-
-
mA
4-mA Drive
4.0
-
-
mA
8-mA Drive
8.0
-
-
mA
High-level source current, VOH=2.4 V
Low-level sink current, VOL=0.4 V
a. VDDC is supplied from the output of the LDO.
b. VOL and VOH shift to 1.2 V when using high-current GPIOs.
26.1.3
On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 26-3. LDO Regulator Characteristics
Parameter
26.1.4
Parameter Name
Min
Nom
Max
Unit
CLDO
External filter capacitor size for internal
power supply
1.0
-
3.0
µF
VLDO
LDO output voltage
1.08
1.2
1.32
V
Flash Memory Characteristics
Table 26-4. Flash Memory Characteristics
Parameter
PECYC
TRET
Parameter Name
Number of guaranteed mass program/erase
a
cycles before failure
Min
Nom
Max
Unit
15,000
-
-
cycles
10
-
-
years
Data retention at average operating temperature
of 125˚C
TPROG
Word program time
-
-
1
ms
TBPROG
Buffer program time
-
-
1
ms
TERASE
Page erase time
-
-
12
ms
TME
Mass erase time
-
-
16
ms
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1. Caution should be used when performing block
erases, as repeated block erases can shorten the number of guaranteed erase cycles, see “Flash Memory
Programming” on page 207.
26.1.5
GPIO Module Characteristics
Table 26-5. GPIO Module DC Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
RGPIOPU
GPIO internal pull-up resistor
50
-
110
kΩ
RGPIOPD
GPIO internal pull-down resistor
55
-
180
kΩ
May 24, 2010
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Texas Instruments-Advance Information
Electrical Characteristics
26.1.6
USB Module Characteristics
®
The Stellaris USB controller DC electrical specifications are compliant with the “Universal Serial
Bus Specification Rev. 2.0” (full-speed and low-speed support) and the “On-The-Go Supplement
to the USB 2.0 Specification Rev. 1.0”. Some components of the USB system are integrated within
®
the LM3S5B91 microcontroller and specific to the Stellaris microcontroller design. An external
component resistor is needed as specified in Table 26-6.
Table 26-6. USB Controller DC Characteristics
Parameter
RUBIAS
26.1.7
Parameter Name
Value of the pull-down resistor on the USB0RBIAS pin
Value
Unit
9.1K ± 1 %
Ω
Current Specifications
This section provides information on typical and maximum power consumption under various
conditions.
26.1.7.1
Preliminary Current Consumption Specifications
The following table provides preliminary figures for current consumption while ongoing characterization
is completed.
Table 26-7. Preliminary Current Consumption
Parameter
IDD_RUN
Parameter Name
Conditions
Run mode 1 (Flash loop) VDD = 3.3 V
Nom
Max
Unit
56
-
mA
8
-
mA
550
-
µA
Code= while(1){} executed in Flash
Peripherals = All ON
System Clock = 50 MHz (with PLL)
Temp = 25°C
IDD_SLEEP
Sleep mode
VDD = 3.3 V
Peripherals = All clock gated
System Clock = 50 MHz (with PLL)
Temp = 25°C
IDD_DEEPSLEEP
Deep-sleep mode
Peripherals = All OFF
System Clock = IOSC30KHZ/64
Temp = 25°C
26.2
AC Characteristics
26.2.1
Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements.
1144
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Figure 26-1. Load Conditions
CL = 16 pF for EPI0S[31:0] signals
50 pF for other digital I/O signals
pin
GND
26.2.2
Clocks
The following sections provide specifications on the various clock sources and mode.
26.2.2.1
PLL Specifications
The following tables provide specifications for using the PLL.
Table 26-8. Phase Locked Loop (PLL) Characteristics
Parameter
fREF_XTAL
Parameter Name
a
Crystal reference
referencea
fREF_EXT
External clock
fPLL
PLL frequency
TREADY
b
Min
Nom
Max
Unit
3.579545
-
16.384
MHz
3.579545
-
16.384
MHz
-
400
-
MHz
c
PLL lock time
0.562
-
d
1.38
ms
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
c. Using a 16.384-MHz crystal
d. Using 3.5795-MHz crystal
Table 26-9 on page 1145 shows the actual frequency of the PLL based on the crystal frequency used
(defined by the XTAL field in the RCC register).
Table 26-9. Actual PLL Frequency
XTAL
Crystal Frequency (MHz)
PLL Frequency (MHz)
Error
0x04
0x05
3.5795
400.904
0.0023%
3.6864
398.1312
0.0047%
0x06
4.0
400
-
0x07
4.096
401.408
0.0035%
0x08
4.9152
398.1312
0.0047%
0x09
5.0
400
-
0x0A
5.12
399.36
0.0016%
0x0B
6.0
400
-
0x0C
6.144
399.36
0.0016%
0x0D
7.3728
398.1312
0.0047%
0x0E
8.0
400
0.0047%
0x0F
8.192
398.6773333
0.0033%
0x10
10.0
400
-
0x11
12.0
400
-
May 24, 2010
1145
Texas Instruments-Advance Information
Electrical Characteristics
Table 26-9. Actual PLL Frequency (continued)
26.2.2.2
XTAL
Crystal Frequency (MHz)
PLL Frequency (MHz)
Error
0x12
12.288
401.408
0.0035%
0x13
13.56
397.76
0.0056%
0x14
14.318
400.90904
0.0023%
0x15
16.0
400
-
0x16
16.384
404.1386667
0.010%
PIOSC Specifications
Table 26-10. PIOSC Clock Characteristics
Parameter
26.2.2.3
Min
Nom
Max
Unit
fPIOSC25
Parameter Name
Internal 16-MHz precision oscillator frequency variance,
factory calibrated at 25 °C
-
±0.25%
±1%
-
fPIOSCT
Internal 16-MHz precision oscillator frequency variance,
factory calibrated at 25 °C, across specified temperature
range
-
-
±3%
-
Internal 30-kHz Oscillator Specifications
Table 26-11. 30-kHz Clock Characteristics
26.2.2.4
Parameter
Parameter Name
fIOSC30KHZ
Internal 30-KHz oscillator frequency
Min
Nom
Max
Unit
15
30
45
KHz
Main Oscillator Specifications
Table 26-12. Main Oscillator Clock Characteristics
Parameter
fMOSC
tMOSC_PER
tMOSC_SETTLE
Parameter Name
Min
Nom
Max
Unit
Main oscillator frequency
1
-
16.384
MHz
Main oscillator period
61
-
1000
ns
17.5
-
20
ms
Main oscillator settling time
fREF_XTAL_BYPASS
Crystal reference using the main oscillator
a
(PLL in BYPASS mode)
1
-
16.384
MHz
fREF_EXT_BYPASS
External clock reference (PLL in BYPASS
a
mode)
0
-
80
MHz
a. The ADC must be clocked from the PLL or directly from a 14- to 18-MHz clock source to operate properly.
Table 26-13. MOSC Oscillator Input Characteristics
Name
Frequency
Frequency tolerance
Oscillation mode
Equivalent series resistance
(max)
Value
16
12
8
Condition
6
4
3.5
MHz
±100
±100
±100
±100
±100
±100
PPM
parallel
parallel
parallel
parallel
parallel
parallel
-
70
90
120
160
200
220
Ω
Load capacitance
16
16
16
16
16
16
pF
Drive level (typ)
100
100
100
100
100
100
µw
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May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
26.2.2.5
System Clock Specifications with ADC Operation
Table 26-14. System Clock Characteristics with ADC Operation
Parameter
fsysadc
26.2.3
Parameter Name
System clock frequency when the ADC module is
operating (when PLL is bypassed)
Min
Nom
Max
Unit
16
-
-
MHz
JTAG and Boundary Scan
Table 26-15. JTAG Characteristics
Parameter
No.
Parameter
Parameter Name
J1
fTCK
TCK operational clock frequency
J2
tTCK
TCK operational clock period
Min
Nom
Max
Unit
0
-
10
MHz
100
-
-
ns
J3
tTCK_LOW
TCK clock Low time
-
tTCK
-
ns
J4
tTCK_HIGH
TCK clock High time
-
tTCK
-
ns
J5
tTCK_R
TCK rise time
0
-
10
ns
J6
tTCK_F
TCK fall time
0
-
10
ns
J7
tTMS_SU
TMS setup time to TCK rise
20
-
-
ns
J8
tTMS_HLD
TMS hold time from TCK rise
20
-
-
ns
J9
tTDI_SU
TDI setup time to TCK rise
25
-
-
ns
J10
tTDI_HLD
TDI hold time from TCK rise
25
-
-
ns
J11
TCK fall to Data
Valid from High-Z
-
23
35
ns
4-mA drive
15
26
ns
8-mA drive
14
25
ns
18
29
ns
21
35
ns
4-mA drive
14
25
ns
8-mA drive
13
24
ns
8-mA drive with slew rate control
18
28
ns
t TDO_ZDV
2-mA drive
8-mA drive with slew rate control
J12
t TDO_DV
J13
t TDO_DVZ
TCK fall to Data
Valid from Data
Valid
TCK fall to High-Z
from Data Valid
2-mA drive
-
2-mA drive
9
11
ns
4-mA drive
-
7
9
ns
8-mA drive
6
8
ns
8-mA drive with slew rate control
7
9
ns
Figure 26-2. JTAG Test Clock Input Timing
J2
J3
J4
TCK
J6
J5
May 24, 2010
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Texas Instruments-Advance Information
Electrical Characteristics
Figure 26-3. JTAG Test Access Port (TAP) Timing
TCK
J7
TMS
TDI
J8
J8
TMS Input Valid
TMS Input Valid
J9
J9
J10
TDI Input Valid
J11
J10
TDI Input Valid
J12
TDO
26.2.4
J7
J13
TDO Output Valid
TDO Output Valid
Reset
Table 26-16. Reset Characteristics
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
-
2.0
-
V
2.85
2.9
2.95
V
R1
VTH
Reset threshold
R2
VBTH
Brown-Out threshold
R3
TPOR
Power-On Reset timeout
6
-
18
ms
R4
TBOR
Brown-Out timeout
-
500
-
µs
R5
TIRPOR
Internal reset timeout after POR
-
-
95
system clocks
R6
TIRBOR
Internal reset timeout after BOR
-
-
7
system clocks
R7
TIRHWR
Internal reset timeout after hardware
reset (RST pin)
-
-
7
system clocks
R8
TIRSWR
Internal reset timeout after
software-initiated system reset
-
-
16
system clocks
R9
TIRWDR
Internal reset timeout after watchdog
reset
-
-
16
system clocks
R10
TIRMFR
Internal reset timeout after MOSC failure
reset
-
-
32
system clocks
R11
TVDDRISE
Supply voltage (VDD) rise time (0V-3.3V)
-
-
250
µs
R12
TMIN
Minimum RST pulse width
2
-
-
µs
Figure 26-4. External Reset Timing (RST)
RST
R12
R7
/Reset
(Internal)
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Figure 26-5. Power-On Reset Timing
R1
VDD
R3
/POR
(Internal)
R5
/Reset
(Internal)
Figure 26-6. Brown-Out Reset Timing
R2
VDD
R4
/BOR
(Internal)
R6
/Reset
(Internal)
Figure 26-7. Software Reset Timing
SW Reset
R8
/Reset
(Internal)
Figure 26-8. Watchdog Reset Timing
WDOG
Reset
(Internal)
R9
/Reset
(Internal)
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Electrical Characteristics
Figure 26-9. MOSC Failure Reset Timing
MOSC
Fail Reset
(Internal)
R10
/Reset
(Internal)
26.2.5
Sleep Modes
a
Table 26-17. Sleep Modes AC Characteristics
Parameter
No
Parameter
D1
tWAKE_S
D2
tWAKE_PLL_S
D3
tENTER_DS
Parameter Name
Min
Nom
Max
Unit
Time to wake from interrupt in sleep or
deep-sleep mode, not using the PLL
-
-
7
system clocks
Time to wake from interrupt in sleep or
deep-sleep mode when using the PLL
-
-
TREADY
ms
Time to enter deep-sleep mode from sleep
request
-
0
16
ms
b
a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode.
b. Nominal specification occurs 99.9995% of the time.
26.2.6
General-Purpose I/O (GPIO)
Note:
All GPIOs are 5-V tolerant.
Table 26-18. GPIO Characteristics
Parameter Parameter Name
tGPIOR
Condition
GPIO Rise Time
(from 20% to 80%
of VDD)
Min
Nom
Max
Unit
-
14
20
ns
4-mA drive
7
10
ns
8-mA drive
4
5
ns
2-mA drive
8-mA drive with slew rate control
tGPIOF
26.2.7
6
8
ns
14
21
ns
4-mA drive
7
11
ns
8-mA drive
4
6
ns
8-mA drive with slew rate control
6
8
ns
GPIO Fall Time
(from 80% to 20%
of VDD)
2-mA drive
-
External Peripheral Interface (EPI)
When the EPI module is in SDRAM mode, the drive strength must be configured to 8 mA. Table
26-19 on page 1150 shows the rise and fall times in SDRAM mode with 16 pF load conditions. When
the EPI module is in Host-Bus or General-Purpose mode, the values in Table 26-18 on page 1150
should be used.
Table 26-19. EPI SDRAM Characteristics
Parameter
tSDRAMR
Parameter Name
EPI Rise Time (from 20% to 80% of
VDD)
Condition
8-mA drive, CL = 16 pF
1150
Min
Nom
Max
Unit
-
2
3
ns
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Table 26-19. EPI SDRAM Characteristics (continued)
Parameter
tSDRAMF
Parameter Name
Condition
EPI Fall Time (from 80% to 20% of
VDD)
8-mA drive, CL = 16 pF
Min
Nom
Max
Unit
-
2
3
ns
a
Table 26-20. EPI SDRAM Interface Characteristics
Parameter No
Parameter
E1
tCK
E2
E3
E4
Parameter Name
Min
Nom
Max
Unit
SDRAM Clock period
20
-
-
ns
tCH
SDRAM Clock high time
10
-
-
ns
tCL
SDRAM Clock low time
10
-
-
ns
tCOV
CLK to output valid
-5
-
5
ns
E5
tCOI
CLK to output invalid
-5
-
5
ns
E6
tCOT
CLK to output tristate
-5
-
5
ns
E7
tS
Input set up to CLK
10
-
-
ns
E8
tH
CLK to input hold
0
-
-
ns
E9
tPU
Power-up time
100
-
-
µs
E10
tRP
Precharge all banks
20
-
-
ns
E11
tRFC
Auto refresh
66
-
-
ns
E12
tMRD
Program mode register
40
40
40
ns
a. The EPI SDRAM interface must use 8-mA drive.
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Electrical Characteristics
Figure 26-10. SDRAM Initialization and Load Mode Register Timing
T0
T1
E1
CLK
(EPI31)
Tn +1
Tp +2
Tp +1
To +1
E3
Tp +3
E2
CKE
(EPI30)
Command
(EPI[29:28],
EPI[19:18])
NOP
NOP
Precharge
Auto
Refresh
Auto
Refresh
NOP
Active
Load Mode
Register
NOP
DQML,DQMH
(EPI[17:16])
A11, A[9-0]
(EPI11,
EPI[9:0])
Code
Row
Code
Row
All Banks
A10
(EPI10)
Single Bank
All Banks
BA[1:0]
(EPI[14:13]
Bank
High-Z
D[15:0]
(EPI[15:0])
E9
E10
E12
E11
Valid Data
Notes:
1. If CS is high at clock high time, all applied commands are NOP.
2. The Mode register may be loaded prior to the auto refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
Don’t Care
Figure 26-11. SDRAM Read Timing
CLK
(EPI0S31)
CKE
(EPI0S30)
E4
E5
E6
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
E7
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
Column
NOP
NOP
Read
E8
Data 0
Data 1
...
Data n
Burst
Term
NOP
AD [15:0] driven in
AD [15:0] driven out
AD [15:0] driven out
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Figure 26-12. SDRAM Write Timing
CLK
(EPI0S31)
CKE
(EPI0S30)
E4
E5
E6
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Column-1
Activate
NOP
NOP
Data 0
Data 1
...
Data n
Burst
Term
Write
AD [15:0] driven out
AD [15:0] driven out
Table 26-21. EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics
Parameter No
Parameter
E14
tISU
E15
E16
E17
Parameter Name
Min
Nom
Max
Unit
Read data set up time
10
-
-
ns
tIH
Read data hold time
0
-
-
ns
tDV
WEn to write data valid
-
-
5
ns
tDI
Data hold from WEn invalid
2
-
-
EPI Clocks
E18
tOV
CSn to output valid
-5
-
5
ns
E19
tOINV
CSn to output invalid
-5
-
5
ns
E20
tSTLOW
WEn / RDn strobe width low
2
-
-
EPI Clocks
E21
tFIFO
FEMPTY and FFULL setup time to
clock edge
2
-
-
System Clocks
E22
tALEHIGH
ALE width high
-
1
-
EPI Clocks
E23
tCSLOW
CSn width low
4
-
-
EPI Clocks
E24
tALEST
ALE rising to WEn / RDn strobe falling
2
-
-
EPI Clocks
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Electrical Characteristics
Figure 26-13. Host-Bus 8/16 Mode Read Timing
E22
ALE
(EPI0S30)
E18
E23
CSn
(EPI0S30)
WRn
(EPI0S29)
E18
E19
E24
E20
RDn/OEn
(EPI0S28)
Address
E15
E14
Data
Data
Figure 26-14. Host-Bus 8/16 Mode Write Timing
E22
ALE
(EPI0S30)
E18
E23
CSn
(EPI0S30)
E18
E19
E20
WRn
(EPI0S29)
E24
RDn/OEn
(EPI0S28)
Address
E16
Data
Data
Table 26-22. EPI General-Purpose Interface Characteristics
Parameter No
Parameter
E25
tCK
E26
E27
E28
Parameter Name
Min
Nom
Max
Unit
General-Purpose Clock period
20
-
-
ns
tCH
General-Purpose Clock high time
10
-
-
ns
tCL
General-Purpose Clock low time
10
-
-
ns
tISU
Input signal set up time to rising clock edge
10
-
-
ns
E29
tIH
Input signal hold time from rising clock edge
10
-
-
ns
E30
tDV
Falling clock edge to output valid
-5
-
5
ns
E31
tDI
Falling clock edge to output invalid
-5
-
5
ns
E32
tRDYSU
iRDY assertion or deassertion set up time to
falling clock edge
20
-
-
ns
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Figure 26-15. General-Purpose Mode Read and Write Timing
E25
E27
Clock (EPI0S31)
E30
Frame
(EPI0S30)
RD (EPI0S29)
WR (EPI0S28)
Address
E30
E28
Data
Data
E31
Data
E29
Read
Write
The above figure illustrates accesses where the FRM50 bit is clear, the FRMCNT field is 0x0, the
RD2CYC bit is clear, and the WR2CYC bit is clear.
Figure 26-16. General-Purpose Mode iRDY Timing
Clock (EPI0S31)
Frame
(EPI0S30)
RD (EPI0S29)
E32
E32
iRDY (EPI0S27)
Address
Data
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Electrical Characteristics
26.2.8
Analog-to-Digital Converter
a
Table 26-23. ADC Characteristics
Parameter
VADCIN
N
fADC
Parameter Name
Min
Nom
Max
Unit
Maximum single-ended, full-scale analog input voltage,
using internal reference
-
-
3.0
V
Maximum single-ended, full-scale analog input voltage,
using external reference
-
-
VREFA
V
Minimum single-ended, full-scale analog input voltage
0.0
-
-
V
Maximum differential, full-scale analog input voltage,
using internal reference
-
-
1.5
V
Maximum differential, full-scale analog input voltage,
using external reference
-
-
VREFA/2
V
Minimum differential, full-scale analog input voltage
0.0
-
-
V
14
16
18
MHz
Resolution
10
b
ADC internal clock frequency
c
bits
tADCCONV
Conversion time
1
µs
f ADCCONV
Conversion rate
1000
k samples/s
c
tLT
Latency from trigger to start of conversion
-
2
-
IL
system clocks
ADC input leakage
-
-
±1.0
µA
RADC
ADC equivalent resistance
-
-
10
kΩ
CADC
ADC equivalent capacitance
0.9
1.0
1.1
pF
EL
Integral nonlinearity error
-
-
±1
LSB
ED
Differential nonlinearity error
-
-
±1
LSB
EO
Offset error
-
-
±1
LSB
EG
Full-scale gain error
-
-
±3
LSB
ETS
Temperature sensor accuracy
-
-
±5
°C
a. The ADC reference voltage is 3.0 V. This reference voltage is internally generated from the 3.3 VDDA supply by a band
gap circuit.
b. The ADC must be clocked from the PLL or directly from an external clock source to operate properly.
c. The conversion time and rate scale from the specified number if the ADC internal clock frequency is any value other than
16 MHz.
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Figure 26-17. ADC Input Equivalency Diagram
Stellaris® Microcontroller
VDD
ESD
Clamp
RADC
ESD
Clamp
VIN
10-bit
converter
IL
CADC
Sample and hold
ADC converter
a
Table 26-24. ADC Module External Reference Characteristics
Parameter
VREFA
IL
Parameter Name
b
External voltage reference for ADC
External voltage reference leakage current
Min
Nom
Max
Unit
2.4
-
VDD
V
-
±1.0
-
µA
a. Care must be taken to supply a reference voltage of acceptable quality.
b. Ground is always used as the reference level for the minimum conversion value.
Table 26-25. ADC Module Internal Reference Characteristics
Parameter
VREFI
EIR
26.2.9
Parameter Name
Min
Nom
Max
Unit
Internal voltage reference for ADC
-
3.0
-
V
Internal voltage reference error
-
-
±2.5
%
Synchronous Serial Interface (SSI)
Table 26-26. SSI Characteristics
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
S1
tCLK_PER
SSIClk cycle time
2
-
65024
system clocks
S2
tCLK_HIGH
SSIClk high time
-
0.5
-
t clk_per
S3
tCLK_LOW
SSIClk low time
-
0.5
-
t clk_per
S4
tCLKRF
SSIClk rise/fall time
-
7.4
26
ns
S5
tDMD
Data from master valid delay time
0
-
1
system clocks
S6
tDMS
Data from master setup time
1
-
-
system clocks
S7
tDMH
Data from master hold time
2
-
-
system clocks
S8
tDSS
Data from slave setup time
1
-
-
system clocks
S9
tDSH
Data from slave hold time
2
-
-
system clocks
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Electrical Characteristics
Figure 26-18. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
S1
S4
S2
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 26-19. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
S2
S1
SSIClk
S3
SSIFss
SSITx
MSB
LSB
8-bit control
SSIRx
0
MSB
LSB
4 to 16 bits output data
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Figure 26-20. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
S1
S4
S2
SSIClk
(SPO=0)
S3
SSIClk
(SPO=1)
S6
SSITx
(master)
S7
MSB
S5
S8
SSIRx
(slave)
LSB
S9
MSB
LSB
SSIFss
26.2.10
Inter-Integrated Circuit (I2C) Interface
Figure 26-21. I2C Timing
I2
I6
I5
I2CSCL
I1
I4
I7
I8
I3
I9
I2CSDA
26.2.11
Inter-Integrated Circuit Sound (I2S) Interface
Table 26-27. I2S Master Clock (Receive and Transmit)
Parameter No.
Parameter
Parameter Name
Min
Nom
Max
Unit
M1
tMCLK_PER
Cycle time
20.3
-
-
ns
Rise/fall time
See Table 26-18 on page 1150.
M2
tMCLKRF
M3
tMCLK_HIGH
High time
10
-
-
ns
M4
tMCLK_LOW
Low time
10
-
-
ns
M5
tMDC
Duty cycle
48
-
52
%
M6
tMJITTER
-
-
2.5
ns
Jitter
ns
Table 26-28. I2S Slave Clock (Receive and Transmit)
Parameter No.
Min
Nom
Max
Unit
M7
Parameter
tSCLK_PER
Parameter Name
Cycle time
80
-
-
ns
M8
tSCLK_HIGH
High time
40
-
-
ns
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Electrical Characteristics
Table 26-28. I2S Slave Clock (Receive and Transmit) (continued)
Parameter No.
Parameter
Parameter Name
M9
tSCLK_LOW
Low time
M10
tSDC
Min
Duty cycle
Nom
Max
Unit
40
-
-
ns
-
50
-
%
Table 26-29. I2S Master Mode
Parameter No.
Parameter
Min
Nom
Max
Unit
SCK fall to WS valid
-
-
10
ns
tMSD
SCK fall to TXSD valid
-
-
10
ns
M13
tMSDS
RXSD setup time to SCK rise
10
-
-
ns
M14
tMSDH
RXSD hold time from SCK rise
10
-
-
ns
Min
Nom
Max
Unit
M11
tMSWS
M12
Parameter Name
Figure 26-22. I2S Master Mode Transmit Timing
SCK
WS
M11
TXSD
Data
M12
Figure 26-23. I2S Master Mode Receive Timing
SCK
M13
RXSD
M14
Data
Table 26-30. I2S Slave Mode
Parameter No.
Parameter
Parameter Name
M15
tSCLK_PER
Cycle time
80
-
-
ns
M16
tSCLK_HIGH
High time
40
-
-
ns
M17
tSCLK_LOW
Low time
40
-
-
ns
M18
tSDC
Duty cycle
-
50
-
%
M19
tSSETUP
WS setup time to SCK rise
-
-
25
ns
M20
tSHOLD
WS hold time from SCK rise
-
-
10
ns
M21
tSSD
SCK fall to TXSD valid
-
-
20
ns
M22
tSLSD
Left-justified mode, WS to TXSD
-
-
20
ns
M23
tSSDS
RXSD setup time to SCK rise
10
-
-
ns
M24
tSSDH
RXSD hold time from SCK rise
10
-
-
ns
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May 24, 2010
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Figure 26-24. I2S Slave Mode Transmit Timing
SCK
M19
M20
WS
M22
Data
TXSD
M21
Figure 26-25. I2S Slave Mode Receive Timing
SCK
M23
Data
RXSD
26.2.12
M24
Universal Serial Bus (USB) Controller
®
The Stellaris USB controller AC electrical specifications are compliant with the “Universal Serial
Bus Specification Rev. 2.0” (full-speed and low-speed support) and the “On-The-Go Supplement
to the USB 2.0 Specification Rev. 1.0”.
26.2.13
Analog Comparator
Table 26-31. Analog Comparator Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
VOS
Input offset voltage
-
±10
±25
mV
VCM
Input common mode voltage range
0
-
VDD-1.5
V
CMRR
Common mode rejection ratio
50
-
-
dB
TRT
Response time
-
-
1
µs
TMC
Comparator mode change to Output Valid
-
-
10
µs
Table 26-32. Analog Comparator Voltage Reference Characteristics
Parameter
Min
Nom
Max
Unit
RHR
Parameter Name
Resolution high range
-
VDD/31
-
LSB
RLR
Resolution low range
-
VDD/23
-
LSB
AHR
Absolute accuracy high range
-
-
±1/2
LSB
ALR
Absolute accuracy low range
-
-
±1/4
LSB
May 24, 2010
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Boot Loader
A
Boot Loader
A.1
Boot Loader Overview
®
The Stellaris Boot Loader is executed from the ROM when the Flash memory is empty and is used
to download code to the Flash memory of a device without the use of a debug interface. At any
reset that resets the core, the user has the opportunity to direct the core to execute the ROM Boot
Loader or the application in Flash memory by using any GPIO signal in Ports A-H as configured in
the Boot Configuration (BOOTCFG) register. If the ROM boot loader is not selected, code in the
ROM checks address 0x000.0004 to see if the Flash memory has a valid reset vector. If the data
at address 0x0000.0004 is 0xFFFF.FFFF, then it is assumed that the Flash memory has not yet
been programmed, and the core executes the ROM Boot Loader.
The boot loader uses a simple packet interface to provide synchronous communication with the
device. The speed of the boot loader is determined by the internal oscillator (PIOSC) frequency as
it does not enable the PLL. The following serial interfaces can be used:
■ UART0
■ SSI0
■ I2C0
For simplicity, both the data format and communication protocol are identical for all serial interfaces.
Note:
The Flash-memory-resident version of the Boot Loader also supports CAN and USB.
See the Stellaris® Boot Loader User's Guide for information on the boot loader software.
A.2
Serial Interfaces
This section describes how the boot loader operates using a serial interface.
A.2.1
Serial Configuration
Once communication with the boot loader is established via one of the serial interfaces, that interface
is used until the boot loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the boot loader via the UART are disabled
until the device is reset.
A.2.1.1
UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the boot loader and can be any valid baud rate supported by the host and
the device. The auto detection sequence requires that the baud rate should be no more than 1/16
the internal oscillator (PIOSC) frequency of the board that is running the boot loader (which is at
least 8.4 MHz, providing support for up to 262,500 baud). The maximum regular speed baud rate
®
for any UART on a Stellaris device is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the boot loader must determine the relationship between the
internal oscillator and the baud rate. With this information, the boot loader can configure the UART
to the same baud rate as the host. This automatic baud-rate detection allows the host to use any
valid baud rate to communicate with the device.
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The method used to perform this automatic synchronization requires the host to send the boot loader
two bytes that are both 0x55. With this series of pulses, the boot loader can calculate the ratios
needed to program the UART to match the host’s baud rate. After the host sends the pattern, it
attempts to read back one byte of data from the UART. The boot loader returns the value of 0xCC
to indicate successful detection of the baud rate. If this byte is not received after at least twice the
time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait
for the 0xCC byte again until the boot loader acknowledges that it has received a synchronization
pattern correctly. For example, the time to wait for data back from the boot loader should be calculated
as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate of 115200, this time is 2*(20/115200)
or 0.35 ms.
A.2.1.2
SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the default framing defined as Motorola format with both the SPH and SPO bits set in the SSICR0
register. See “Frame Formats” on page 644 for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum frequency of the
SSIClk signal to be at most 1/12 the internal oscillator (PIOSC) frequency of the board running the
boot loader (which is at least 8.4 MHz, providing support for up to 700 KHz). Because the host
device is the master, the SSI on the boot loader device does not need to determine the clock as it
is provided directly by the host.
A.2.1.3
I2C
The Inter-Integrated Circuit (I2C) port operates in slave mode with a slave address of 0x42. The I2C
port works at both 100-kHz and 400-kHz I2CSCL clock frequency. Because the host device is the
master, the I2C on the boot loader device does not need to determine the clock as it is provided
directly by the host.
A.2.2
Serial Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.2.2.1
Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize
The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum
This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data
This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
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A.2.2.2
Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause Flash memory access should limit the download sizes to prevent losing bytes
during Flash memory programming. This limitation is discussed further in the section that describes
the boot loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 1165).
Once the packet has been formatted correctly by the host, it should be sent out over the serial
interface. Then the host should poll the interface for the first non-zero data returned from the device.
The first non-zero byte is either an ACK (0xCC) or a NAK (0x33) byte from the device indicating the
packet was received successfully (ACK) or unsuccessfully (NAK). This response does not indicate
that the actual contents of the command issued in the data portion of the packet were valid, just
that the packet was received correctly.
A.2.2.3
Receiving Packets
The boot loader sends a packet of data in the same format that it receives a packet. The boot loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte and finally followed by the data itself. The
data is sent without a break after the first non-zero byte is sent from the boot loader. Once the device
communicating with the boot loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the boot loader is to resend the command that failed and request the data again. If needed, the host
may send leading zeros before sending down the ACK/NAK signal to the boot loader, as the boot
loader only accepts the first non-zero data as a valid response. This zero padding is needed by the
SSI interface in order to receive data to or from the boot loader.
A.2.3
Serial Commands
The next section defines the list of commands that can be sent to the boot loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.2.3.1
COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Because the ping command has no real return
status, the receipt of an ACK can be interpreted as a successful ping to the boot loader.
A.2.3.2
COMMAND_DOWNLOAD (0x21)
This command is sent to the boot loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands
and results in a longer time to receive the ACK/NAK back from the board. This command should
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be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the boot loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.2.3.3
COMMAND_RUN (0x22)
This command is used to tell the boot loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the boot loader responds with an ACK
signal back to the host device before actually executing the code at the given address. The ACK
response tells the host that the command was received successfully, and the code is running.
Byte[0]
Byte[1]
Byte[2]
Byte[3]
Byte[4]
Byte[5]
Byte[6]
A.2.3.4
=
=
=
=
=
=
=
7
checksum(Bytes[2:6])
COMMAND_RUN
Execute Address[31:24]
Execute Address[23:16]
Execute Address[15:8]
Execute Address[7:0]
COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the boot loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.2.3.5
COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. For packets
which do not contain the final portion of the downloaded data, a multiple of four bytes should always
be transferred. The command terminates programming once the number of bytes indicated by the
COMMAND_DOWNLOAD command has been received. Each time this function is called, it should be
followed by a COMMAND_GET_STATUS to ensure that the data was successfully programmed into
the Flash memory. If the boot loader sends a NAK to this command, the boot loader does not
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increment the current address to allow retransmission of the previous data. The following example
shows a COMMAND_SEND_DATA packet with 8 bytes of packet data:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.2.3.6
COMMAND_RESET (0x25)
This command is used to tell the boot loader device to reset. Unlike the COMMAND_RUN, this command
allows the initial stack pointer to be read by the hardware and set up for the new code.
COMMAND_RESET can also be used to reset the boot loader if a critical error occurs, and the host
device wants to restart communication with the boot loader.
Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The boot loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the boot loader. The ACK tells the host that the command was
received successfully and the part will be reset.
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B
ROM DriverLib Functions
B.1
DriverLib Functions Included in the Integrated ROM
®
The Stellaris Peripheral Driver Library (DriverLib) APIs that are available in the integrated ROM of
®
the Stellaris family of devices are listed below. The detailed description of each function is available
in the Stellaris® ROM User’s Guide.
ROM_ADCComparatorConfigure
// Configures an ADC digital comparator.
ROM_ADCComparatorIntClear
// Clears sample sequence comparator interrupt source.
ROM_ADCComparatorIntDisable
// Disables a sample sequence comparator interrupt.
ROM_ADCComparatorIntEnable
// Enables a sample sequence comparator interrupt.
ROM_ADCComparatorIntStatus
// Gets the current comparator interrupt status.
ROM_ADCComparatorRegionSet
// Defines the ADC digital comparator regions.
ROM_ADCComparatorReset
// Resets the current ADC digital comparator conditions.
ROM_ADCHardwareOversampleConfigure
// Configures the hardware oversampling factor of the ADC.
ROM_ADCIntClear
// Clears sample sequence interrupt source.
ROM_ADCIntDisable
// Disables a sample sequence interrupt.
ROM_ADCIntEnable
// Enables a sample sequence interrupt.
ROM_ADCIntStatus
// Gets the current interrupt status.
ROM_ADCProcessorTrigger
// Causes a processor trigger for a sample sequence.
ROM_ADCSequenceConfigure
// Configures the trigger source and priority of a sample sequence.
ROM_ADCSequenceDataGet
// Gets the captured data for a sample sequence.
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ROM_ADCSequenceDisable
// Disables a sample sequence.
ROM_ADCSequenceEnable
// Enables a sample sequence.
ROM_ADCSequenceOverflow
// Determines if a sample sequence overflow occurred.
ROM_ADCSequenceOverflowClear
// Clears the overflow condition on a sample sequence.
ROM_ADCSequenceStepConfigure
// Configure a step of the sample sequencer.
ROM_ADCSequenceUnderflow
// Determines if a sample sequence underflow occurred.
ROM_ADCSequenceUnderflowClear
// Clears the underflow condition on a sample sequence.
ROM_CANBitRateSet
// This function is used to set the CAN bit timing values to a nominal setting based on a desired
bit rate.
ROM_CANBitTimingGet
// Reads the current settings for the CAN controller bit timing.
ROM_CANBitTimingSet
// Configures the CAN controller bit timing.
ROM_CANDisable
// Disables the CAN controller.
ROM_CANEnable
// Enables the CAN controller.
ROM_CANErrCntrGet
// Reads the CAN controller error counter register.
ROM_CANInit
// Initializes the CAN controller after reset.
ROM_CANIntClear
// Clears a CAN interrupt source.
ROM_CANIntDisable
// Disables individual CAN controller interrupt sources.
ROM_CANIntEnable
// Enables individual CAN controller interrupt sources.
ROM_CANIntStatus
// Returns the current CAN controller interrupt status.
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ROM_CANMessageClear
// Clears a message object so that it is no longer used.
ROM_CANMessageGet
// Reads a CAN message from one of the message object buffers.
ROM_CANMessageSet
// Configures a message object in the CAN controller.
ROM_CANRetryGet
// Returns the current setting for automatic retransmission.
ROM_CANRetrySet
// Sets the CAN controller automatic retransmission behavior.
ROM_CANStatusGet
// Reads one of the controller status registers.
ROM_ComparatorConfigure
// Configures a comparator.
ROM_ComparatorIntClear
// Clears a comparator interrupt.
ROM_ComparatorIntDisable
// Disables the comparator interrupt.
ROM_ComparatorIntEnable
// Enables the comparator interrupt.
ROM_ComparatorIntStatus
// Gets the current interrupt status.
ROM_ComparatorRefSet
// Sets the internal reference voltage.
ROM_ComparatorValueGet
// Gets the current comparator output value.
ROM_Crc16Array
// Calculates the CRC-16 of an array of words.
ROM_Crc16Array3
// Calculates three CRC-16s of an array of words.
ROM_EPIAddressMapSet
// Configures the address map for the external interface.
ROM_EPIConfigGPModeSet
// Configures the interface for general-purpose mode operation.
ROM_EPIConfigHB16Set
// Configures the interface for Host-bus 16 operation.
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ROM_EPIConfigHB8Set
// Configures the interface for Host-bus 8 operation.
ROM_EPIConfigSDRAMSet
// Configures the SDRAM mode of operation.
ROM_EPIDividerSet
// Sets the clock divider for the EPI module.
ROM_EPIFIFOConfig
// Configures the read FIFO.
ROM_EPIIntDisable
// Disables EPI interrupt sources.
ROM_EPIIntEnable
// Enables EPI interrupt sources.
ROM_EPIIntErrorClear
// Clears pending EPI error sources.
ROM_EPIIntErrorStatus
// Gets the EPI error interrupt status.
ROM_EPIIntStatus
// Gets the EPI interrupt status.
ROM_EPIModeSet
// Sets the usage mode of the EPI module.
ROM_EPINonBlockingReadAvail
// Get the count of items available in the read FIFO.
ROM_EPINonBlockingReadConfigure
// Configures a non-blocking read transaction.
ROM_EPINonBlockingReadCount
// Get the count remaining for a non-blocking transaction.
ROM_EPINonBlockingReadGet16
// Read available data from the read FIFO, as 16-bit data items.
ROM_EPINonBlockingReadGet32
// Read available data from the read FIFO, as 32-bit data items.
ROM_EPINonBlockingReadGet8
// Read available data from the read FIFO, as 8-bit data items.
ROM_EPINonBlockingReadStart
// Starts a non-blocking read transaction.
ROM_EPINonBlockingReadStop
// Stops a non-blocking read transaction.
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ROM_EPIWriteFIFOCountGet
// Reads the number of empty slots in the write transaction FIFO.
ROM_FlashErase
// Erases a block of flash.
ROM_FlashIntClear
// Clears flash controller interrupt sources.
ROM_FlashIntDisable
// Disables individual flash controller interrupt sources.
ROM_FlashIntEnable
// Enables individual flash controller interrupt sources.
ROM_FlashIntGetStatus
// Gets the current interrupt status.
ROM_FlashProgram
// Programs flash.
ROM_FlashProtectGet
// Gets the protection setting for a block of flash.
ROM_FlashProtectSave
// Saves the flash protection settings.
ROM_FlashProtectSet
// Sets the protection setting for a block of flash.
ROM_FlashUsecGet
// Gets the number of processor clocks per micro-second.
ROM_FlashUsecSet
// Sets the number of processor clocks per micro-second.
ROM_FlashUserGet
// Gets the user registers.
ROM_FlashUserSave
// Saves the user registers.
ROM_FlashUserSet
// Sets the user registers.
ROM_GPIODirModeGet
// Gets the direction and mode of a pin.
ROM_GPIODirModeSet
// Sets the direction and mode of the specified pin(s).
ROM_GPIOIntTypeGet
// Gets the interrupt type for a pin.
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ROM_GPIOIntTypeSet
// Sets the interrupt type for the specified pin(s).
ROM_GPIOPadConfigGet
// Gets the pad configuration for a pin.
ROM_GPIOPadConfigSet
// Sets the pad configuration for the specified pin(s).
ROM_GPIOPinConfigure
// Configures the alternate function of a GPIO pin.
ROM_GPIOPinIntClear
// Clears the interrupt for the specified pin(s).
ROM_GPIOPinIntDisable
// Disables interrupts for the specified pin(s).
ROM_GPIOPinIntEnable
// Enables interrupts for the specified pin(s).
ROM_GPIOPinIntStatus
// Gets interrupt status for the specified GPIO port.
ROM_GPIOPinRead
// Reads the values present of the specified pin(s).
ROM_GPIOPinTypeADC
// Configures pin(s) for use as analog-to-digital converter inputs.
ROM_GPIOPinTypeCAN
// Configures pin(s) for use as a CAN device.
ROM_GPIOPinTypeComparator
// Configures pin(s) for use as an analog comparator input.
ROM_GPIOPinTypeGPIOInput
// Configures pin(s) for use as GPIO inputs.
ROM_GPIOPinTypeGPIOOutput
// Configures pin(s) for use as GPIO outputs.
ROM_GPIOPinTypeGPIOOutputOD
// Configures pin(s) for use as GPIO open drain outputs.
ROM_GPIOPinTypeI2C
// Configures pin(s) for use by the I2C peripheral.
ROM_GPIOPinTypeI2S
// Configures pin(s) for use by the I2S peripheral.
ROM_GPIOPinTypePWM
// Configures pin(s) for use by the PWM peripheral.
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ROM_GPIOPinTypeQEI
// Configures pin(s) for use by the QEI peripheral.
ROM_GPIOPinTypeSSI
// Configures pin(s) for use by the SSI peripheral.
ROM_GPIOPinTypeTimer
// Configures pin(s) for use by the Timer peripheral.
ROM_GPIOPinTypeUART
// Configures pin(s) for use by the UART peripheral.
ROM_GPIOPinTypeUSBAnalog
// Configures pin(s) for use by the USB peripheral.
ROM_GPIOPinTypeUSBDigital
// Configures pin(s) for use by the USB peripheral.
ROM_GPIOPinWrite
// Writes a value to the specified pin(s).
ROM_I2CMasterBusBusy
// Indicates whether or not the I2C bus is busy.
ROM_I2CMasterBusy
// Indicates whether or not the I2C Master is busy.
ROM_I2CMasterControl
// Controls the state of the I2C Master module.
ROM_I2CMasterDataGet
// Receives a byte that has been sent to the I2C Master.
ROM_I2CMasterDataPut
// Transmits a byte from the I2C Master.
ROM_I2CMasterDisable
// Disables the I2C master block.
ROM_I2CMasterEnable
// Enables the I2C Master block.
ROM_I2CMasterErr
// Gets the error status of the I2C Master module.
ROM_I2CMasterInitExpClk
// Initializes the I2C Master block.
ROM_I2CMasterIntClear
// Clears I2C Master interrupt sources.
ROM_I2CMasterIntDisable
// Disables the I2C Master interrupt.
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ROM_I2CMasterIntEnable
// Enables the I2C Master interrupt.
ROM_I2CMasterIntStatus
// Gets the current I2C Master interrupt status.
ROM_I2CMasterSlaveAddrSet
// Sets the address that the I2C Master will place on the bus.
ROM_I2CSlaveDataGet
// Receives a byte that has been sent to the I2C Slave.
ROM_I2CSlaveDataPut
// Transmits a byte from the I2C Slave.
ROM_I2CSlaveDisable
// Disables the I2C slave block.
ROM_I2CSlaveEnable
// Enables the I2C Slave block.
ROM_I2CSlaveInit
// Initializes the I2C Slave block.
ROM_I2CSlaveIntClear
// Clears I2C Slave interrupt sources.
ROM_I2CSlaveIntClearEx
// Clears I2C Slave interrupt sources.
ROM_I2CSlaveIntDisable
// Disables the I2C Slave interrupt.
ROM_I2CSlaveIntDisableEx
// Disables individual I2C Slave interrupt sources.
ROM_I2CSlaveIntEnable
// Enables the I2C Slave interrupt.
ROM_I2CSlaveIntEnableEx
// Enables individual I2C Slave interrupt sources.
ROM_I2CSlaveIntStatus
// Gets the current I2C Slave interrupt status.
ROM_I2CSlaveIntStatusEx
// Gets the current I2C Slave interrupt status.
ROM_I2CSlaveStatus
// Gets the I2C Slave module status
ROM_I2SIntClear
// Clears pending I2S interrupt sources.
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ROM_I2SIntDisable
// Disables I2S interrupt sources.
ROM_I2SIntEnable
// Enables I2S interrupt sources.
ROM_I2SIntStatus
// Gets the I2S interrupt status.
ROM_I2SMasterClockSelect
// Selects the source of the master clock, internal or external.
ROM_I2SRxConfigSet
// Configures the I2S receive module.
ROM_I2SRxDataGet
// Reads data samples from the I2S receive FIFO with blocking.
ROM_I2SRxDataGetNonBlocking
// Reads data samples from the I2S receive FIFO without blocking.
ROM_I2SRxDisable
// Disables the I2S receive module for operation.
ROM_I2SRxEnable
// Enables the I2S receive module for operation.
ROM_I2SRxFIFOLevelGet
// Gets the number of samples in the receive FIFO.
ROM_I2SRxFIFOLimitGet
// Gets the current setting of the FIFO service request level.
ROM_I2SRxFIFOLimitSet
// Sets the FIFO level at which a service request is generated.
ROM_I2STxConfigSet
// Configures the I2S transmit module.
ROM_I2STxDataPut
// Writes data samples to the I2S transmit FIFO with blocking.
ROM_I2STxDataPutNonBlocking
// Writes data samples to the I2S transmit FIFO without blocking.
ROM_I2STxDisable
// Disables the I2S transmit module for operation.
ROM_I2STxEnable
// Enables the I2S transmit module for operation.
ROM_I2STxFIFOLevelGet
// Gets the number of samples in the transmit FIFO.
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ROM_I2STxFIFOLimitGet
// Gets the current setting of the FIFO service request level.
ROM_I2STxFIFOLimitSet
// Sets the FIFO level at which a service request is generated.
ROM_I2STxRxConfigSet
// Configures the I2S transmit and receive modules.
ROM_I2STxRxDisable
// Disables the I2S transmit and receive modules.
ROM_I2STxRxEnable
// Enables the I2S transmit and receive modules for operation.
ROM_IntDisable
// Disables an interrupt.
ROM_IntEnable
// Enables an interrupt.
ROM_IntMasterDisable
// Disables the processor interrupt.
ROM_IntMasterEnable
// Enables the processor interrupt.
ROM_IntPendClear
// Unpends an interrupt.
ROM_IntPendSet
// Pends an interrupt.
ROM_IntPriorityGet
// Gets the priority of an interrupt.
ROM_IntPriorityGroupingGet
// Gets the priority grouping of the interrupt controller.
ROM_IntPriorityGroupingSet
// Sets the priority grouping of the interrupt controller.
ROM_IntPrioritySet
// Sets the priority of an interrupt.
ROM_MPUDisable
// Disables the MPU for use.
ROM_MPUEnable
// Enables and configures the MPU for use.
ROM_MPURegionCountGet
// Gets the count of regions supported by the MPU.
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ROM_MPURegionDisable
// Disables a specific region.
ROM_MPURegionEnable
// Enables a specific region.
ROM_MPURegionGet
// Gets the current settings for a specific region.
ROM_MPURegionSet
// Sets up the access rules for a specific region.
ROM_pvAESTable
// AES forward, reverse, S-box, and reverse S-box tables.
ROM_PWMDeadBandDisable
// Disables the PWM dead band output.
ROM_PWMDeadBandEnable
// Enables the PWM dead band output, and sets the dead band delays.
ROM_PWMFaultIntClear
// Clears the fault interrupt for a PWM module.
ROM_PWMFaultIntClearExt
// Clears the fault interrupt for a PWM module.
ROM_PWMGenConfigure
// Configures a PWM generator.
ROM_PWMGenDisable
// Disables the timer/counter for a PWM generator block.
ROM_PWMGenEnable
// Enables the timer/counter for a PWM generator block.
ROM_PWMGenFaultClear
// Clears one or more latched fault triggers for a given PWM generator.
ROM_PWMGenFaultConfigure
// Configures the minimum fault period and fault pin senses for a given PWM generator.
ROM_PWMGenFaultStatus
// Returns the current state of the fault triggers for a given PWM generator.
ROM_PWMGenFaultTriggerGet
// Returns the set of fault triggers currently configured for a given PWM generator.
ROM_PWMGenFaultTriggerSet
// Configures the set of fault triggers for a given PWM generator.
ROM_PWMGenIntClear
// Clears the specified interrupt(s) for the specified PWM generator block.
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ROM_PWMGenIntStatus
// Gets interrupt status for the specified PWM generator block.
ROM_PWMGenIntTrigDisable
// Disables interrupts for the specified PWM generator block.
ROM_PWMGenIntTrigEnable
// Enables interrupts and triggers for the specified PWM generator block.
ROM_PWMGenPeriodGet
// Gets the period of a PWM generator block.
ROM_PWMGenPeriodSet
// Set the period of a PWM generator.
ROM_PWMIntDisable
// Disables generator and fault interrupts for a PWM module.
ROM_PWMIntEnable
// Enables generator and fault interrupts for a PWM module.
ROM_PWMIntStatus
// Gets the interrupt status for a PWM module.
ROM_PWMOutputFault
// Specifies the state of PWM outputs in response to a fault condition.
ROM_PWMOutputFaultLevel
// Specifies the level of PWM outputs suppressed in response to a fault condition.
ROM_PWMOutputInvert
// Selects the inversion mode for PWM outputs.
ROM_PWMOutputState
// Enables or disables PWM outputs.
ROM_PWMPulseWidthGet
// Gets the pulse width of a PWM output.
ROM_PWMPulseWidthSet
// Sets the pulse width for the specified PWM output.
ROM_PWMSyncTimeBase
// Synchronizes the counters in one or multiple PWM generator blocks.
ROM_PWMSyncUpdate
// Synchronizes all pending updates.
ROM_QEIConfigure
// Configures the quadrature encoder.
ROM_QEIDirectionGet
// Gets the current direction of rotation.
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ROM_QEIDisable
// Disables the quadrature encoder.
ROM_QEIEnable
// Enables the quadrature encoder.
ROM_QEIErrorGet
// Gets the encoder error indicator.
ROM_QEIIntClear
// Clears quadrature encoder interrupt sources.
ROM_QEIIntDisable
// Disables individual quadrature encoder interrupt sources.
ROM_QEIIntEnable
// Enables individual quadrature encoder interrupt sources.
ROM_QEIIntStatus
// Gets the current interrupt status.
ROM_QEIPositionGet
// Gets the current encoder position.
ROM_QEIPositionSet
// Sets the current encoder position.
ROM_QEIVelocityConfigure
// Configures the velocity capture.
ROM_QEIVelocityDisable
// Disables the velocity capture.
ROM_QEIVelocityEnable
// Enables the velocity capture.
ROM_QEIVelocityGet
// Gets the current encoder speed.
ROM_SSIBusy
// Determines whether the SSI transmitter is busy or not.
ROM_SSIConfigSetExpClk
// Configures the synchronous serial interface.
ROM_SSIDataGet
// Gets a data element from the SSI receive FIFO.
ROM_SSIDataGetNonBlocking
// Gets a data element from the SSI receive FIFO.
ROM_SSIDataPut
// Puts a data element into the SSI transmit FIFO.
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ROM_SSIDataPutNonBlocking
// Puts a data element into the SSI transmit FIFO.
ROM_SSIDisable
// Disables the synchronous serial interface.
ROM_SSIDMADisable
// Disable SSI DMA operation.
ROM_SSIDMAEnable
// Enable SSI DMA operation.
ROM_SSIEnable
// Enables the synchronous serial interface.
ROM_SSIIntClear
// Clears SSI interrupt sources.
ROM_SSIIntDisable
// Disables individual SSI interrupt sources.
ROM_SSIIntEnable
// Enables individual SSI interrupt sources.
ROM_SSIIntStatus
// Gets the current interrupt status.
ROM_SysCtlADCSpeedGet
// Gets the sample rate of the ADC.
ROM_SysCtlADCSpeedSet
// Sets the sample rate of the ADC.
ROM_SysCtlClockGet
// Gets the processor clock rate.
ROM_SysCtlClockSet
// Sets the clocking of the device.
ROM_SysCtlDeepSleep
// Puts the processor into deep-sleep mode.
ROM_SysCtlDelay
// Provides a small delay.
ROM_SysCtlFlashSizeGet
// Gets the size of the flash.
ROM_SysCtlGPIOAHBDisable
// Disables a GPIO peripheral for access from the AHB.
ROM_SysCtlGPIOAHBEnable
// Enables a GPIO peripheral for access from the AHB.
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ROM_SysCtlI2SMClkSet
// Sets the MCLK frequency provided to the I2S module.
ROM_SysCtlIntClear
// Clears system control interrupt sources.
ROM_SysCtlIntDisable
// Disables individual system control interrupt sources.
ROM_SysCtlIntEnable
// Enables individual system control interrupt sources.
ROM_SysCtlIntStatus
// Gets the current interrupt status.
ROM_SysCtlLDOGet
// Gets the output voltage of the LDO.
ROM_SysCtlLDOSet
// Sets the output voltage of the LDO.
ROM_SysCtlPeripheralClockGating
// Controls peripheral clock gating in sleep and deep-sleep mode.
ROM_SysCtlPeripheralDeepSleepDisable
// Disables a peripheral in deep-sleep mode.
ROM_SysCtlPeripheralDeepSleepEnable
// Enables a peripheral in deep-sleep mode.
ROM_SysCtlPeripheralDisable
// Disables a peripheral.
ROM_SysCtlPeripheralEnable
// Enables a peripheral.
ROM_SysCtlPeripheralPresent
// Determines if a peripheral is present.
ROM_SysCtlPeripheralReset
// Performs a software reset of a peripheral.
ROM_SysCtlPeripheralSleepDisable
// Disables a peripheral in sleep mode.
ROM_SysCtlPeripheralSleepEnable
// Enables a peripheral in sleep mode.
ROM_SysCtlPinPresent
// Determines if a pin is present.
ROM_SysCtlPWMClockGet
// Gets the current PWM clock configuration.
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ROM DriverLib Functions
ROM_SysCtlPWMClockSet
// Sets the PWM clock configuration.
ROM_SysCtlReset
// Resets the device.
ROM_SysCtlResetCauseClear
// Clears reset reasons.
ROM_SysCtlResetCauseGet
// Gets the reason for a reset.
ROM_SysCtlSleep
// Puts the processor into sleep mode.
ROM_SysCtlSRAMSizeGet
// Gets the size of the SRAM.
ROM_SysCtlUSBPLLDisable
// Powers down the USB PLL.
ROM_SysCtlUSBPLLEnable
// Powers up the USB PLL.
ROM_SysTickDisable
// Disables the SysTick counter.
ROM_SysTickEnable
// Enables the SysTick counter.
ROM_SysTickIntDisable
// Disables the SysTick interrupt.
ROM_SysTickIntEnable
// Enables the SysTick interrupt.
ROM_SysTickPeriodGet
// Gets the period of the SysTick counter.
ROM_SysTickPeriodSet
// Sets the period of the SysTick counter.
ROM_SysTickValueGet
// Gets the current value of the SysTick counter.
ROM_TimerConfigure
// Configures the timer(s).
ROM_TimerControlEvent
// Controls the event type.
ROM_TimerControlLevel
// Controls the output level.
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ROM_TimerControlStall
// Controls the stall handling.
ROM_TimerControlTrigger
// Enables or disables the trigger output.
ROM_TimerDisable
// Disables the timer(s).
ROM_TimerEnable
// Enables the timer(s).
ROM_TimerIntClear
// Clears timer interrupt sources.
ROM_TimerIntDisable
// Disables individual timer interrupt sources.
ROM_TimerIntEnable
// Enables individual timer interrupt sources.
ROM_TimerIntStatus
// Gets the current interrupt status.
ROM_TimerLoadGet
// Gets the timer load value.
ROM_TimerLoadSet
// Sets the timer load value.
ROM_TimerMatchGet
// Gets the timer match value.
ROM_TimerMatchSet
// Sets the timer match value.
ROM_TimerPrescaleGet
// Get the timer prescale value.
ROM_TimerPrescaleSet
// Set the timer prescale value.
ROM_TimerRTCDisable
// Disable RTC counting.
ROM_TimerRTCEnable
// Enable RTC counting.
ROM_TimerValueGet
// Gets the current timer value.
ROM_UARTBreakCtl
// Causes a BREAK to be sent.
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ROM DriverLib Functions
ROM_UARTBusy
// Determines whether the UART transmitter is busy or not.
ROM_UARTCharGet
// Waits for a character from the specified port.
ROM_UARTCharGetNonBlocking
// Receives a character from the specified port.
ROM_UARTCharPut
// Waits to send a character from the specified port.
ROM_UARTCharPutNonBlocking
// Sends a character to the specified port.
ROM_UARTCharsAvail
// Determines if there are any characters in the receive FIFO.
ROM_UARTConfigGetExpClk
// Gets the current configuration of a UART.
ROM_UARTConfigSetExpClk
// Sets the configuration of a UART.
ROM_UARTDisable
// Disables transmitting and receiving.
ROM_UARTDisableSIR
// Disables SIR (IrDA) mode on the specified UART.
ROM_UARTDMADisable
// Disable UART DMA operation.
ROM_UARTDMAEnable
// Enable UART DMA operation.
ROM_UARTEnable
// Enables transmitting and receiving.
ROM_UARTEnableSIR
// Enables SIR (IrDA) mode on the specified UART.
ROM_UARTFIFODisable
// Disables the transmit and receive FIFOs.
ROM_UARTFIFOEnable
// Enables the transmit and receive FIFOs.
ROM_UARTFIFOLevelGet
// Gets the FIFO level at which interrupts are generated.
ROM_UARTFIFOLevelSet
// Sets the FIFO level at which interrupts are generated.
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ROM_UARTIntClear
// Clears UART interrupt sources.
ROM_UARTIntDisable
// Disables individual UART interrupt sources.
ROM_UARTIntEnable
// Enables individual UART interrupt sources.
ROM_UARTIntStatus
// Gets the current interrupt status.
ROM_UARTParityModeGet
// Gets the type of parity currently being used.
ROM_UARTParityModeSet
// Sets the type of parity.
ROM_UARTRxErrorClear
// Clears all reported receiver errors.
ROM_UARTRxErrorGet
// Gets current receiver errors.
ROM_UARTSpaceAvail
// Determines if there is any space in the transmit FIFO.
ROM_UARTTxIntModeGet
// Returns the current operating mode for the UART transmit interrupt.
ROM_UARTTxIntModeSet
// Sets the operating mode for the UART transmit interrupt.
ROM_uDMAChannelAttributeDisable
// Disables attributes of a uDMA channel.
ROM_uDMAChannelAttributeEnable
// Enables attributes of a uDMA channel.
ROM_uDMAChannelAttributeGet
// Gets the enabled attributes of a uDMA channel.
ROM_uDMAChannelControlSet
// Sets the control parameters for a uDMA channel.
ROM_uDMAChannelDisable
// Disables a uDMA channel for operation.
ROM_uDMAChannelEnable
// Enables a uDMA channel for operation.
ROM_uDMAChannelIsEnabled
// Checks if a uDMA channel is enabled for operation.
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ROM DriverLib Functions
ROM_uDMAChannelModeGet
// Gets the transfer mode for a uDMA channel.
ROM_uDMAChannelRequest
// Requests a uDMA channel to start a transfer.
ROM_uDMAChannelSelectDefault
// Selects the default peripheral for a set of uDMA channels.
ROM_uDMAChannelSelectSecondary
// Selects the secondary peripheral for a set of uDMA channels.
ROM_uDMAChannelSizeGet
// Gets the current transfer size for a uDMA channel.
ROM_uDMAChannelTransferSet
// Sets the transfer parameters for a uDMA channel.
ROM_uDMAControlBaseGet
// Gets the base address for the channel control table.
ROM_uDMAControlBaseSet
// Sets the base address for the channel control table.
ROM_uDMADisable
// Disables the uDMA controller for use.
ROM_uDMAEnable
// Enables the uDMA controller for use.
ROM_uDMAErrorStatusClear
// Clears the uDMA error interrupt.
ROM_uDMAErrorStatusGet
// Gets the uDMA error status.
ROM_UpdateI2C
// Starts an update over the I2C0 interface.
ROM_UpdateSSI
// Starts an update over the SSI0 interface.
ROM_UpdateUART
// Starts an update over the UART0 interface.
ROM_USBDevAddrGet
// Returns the current device address in device mode.
ROM_USBDevAddrSet
// Sets the address in device mode.
ROM_USBDevConnect
// Connects the USB controller to the bus in device mode.
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ROM_USBDevDisconnect
// Removes the USB controller from the bus in device mode.
ROM_USBDevEndpointConfigGet
// Gets the current configuration for an endpoint.
ROM_USBDevEndpointConfigSet
// Sets the configuration for an endpoint.
ROM_USBDevEndpointDataAck
// Acknowledge that data was read from the given endpoint's FIFO in device mode.
ROM_USBDevEndpointStall
// Stalls the specified endpoint in device mode.
ROM_USBDevEndpointStallClear
// Clears the stall condition on the specified endpoint in device mode.
ROM_USBDevEndpointStatusClear
// Clears the status bits in this endpoint in device mode.
ROM_USBEndpointDataAvail
// Determine the number of bytes of data available in a given endpoint's FIFO.
ROM_USBEndpointDataGet
// Retrieves data from the given endpoint's FIFO.
ROM_USBEndpointDataPut
// Puts data into the given endpoint's FIFO.
ROM_USBEndpointDataSend
// Starts the transfer of data from an endpoint's FIFO.
ROM_USBEndpointDataToggleClear
// Sets the Data toggle on an endpoint to zero.
ROM_USBEndpointDMAChannel
// Sets the DMA channel to use for a given endpoint.
ROM_USBEndpointDMADisable
// Disable DMA on a given endpoint.
ROM_USBEndpointDMAEnable
// Enable DMA on a given endpoint.
ROM_USBEndpointStatus
// Returns the current status of an endpoint.
ROM_USBFIFOAddrGet
// Returns the absolute FIFO address for a given endpoint.
ROM_USBFIFOConfigGet
// Returns the FIFO configuration for an endpoint.
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ROM DriverLib Functions
ROM_USBFIFOConfigSet
// Sets the FIFO configuration for an endpoint.
ROM_USBFIFOFlush
// Forces a flush of an endpoint's FIFO.
ROM_USBFrameNumberGet
// Get the current frame number.
ROM_USBHostAddrGet
// Gets the current functional device address for an endpoint.
ROM_USBHostAddrSet
// Sets the functional address for the device that is connected to an endpoint in host mode.
ROM_USBHostEndpointConfig
// Sets the base configuration for a host endpoint.
ROM_USBHostEndpointDataAck
// Acknowledge that data was read from the given endpoint's FIFO in host mode.
ROM_USBHostEndpointDataToggle
// Sets the value data toggle on an endpoint in host mode.
ROM_USBHostEndpointStatusClear
// Clears the status bits in this endpoint in host mode.
ROM_USBHostHubAddrGet
// Get the current device hub address for this endpoint.
ROM_USBHostHubAddrSet
// Set the hub address for the device that is connected to an endpoint.
ROM_USBHostMode
// Change the mode of the USB controller to host.
ROM_USBHostPwrDisable
// Disables the external power pin.
ROM_USBHostPwrEnable
// Enables the external power pin.
ROM_USBHostPwrFaultConfig
// Sets the configuration for USB power fault.
ROM_USBHostPwrFaultDisable
// Disables power fault detection.
ROM_USBHostPwrFaultEnable
// Enables power fault detection.
ROM_USBHostRequestIN
// Schedules a request for an IN transaction on an endpoint in host mode.
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ROM_USBHostRequestStatus
// Issues a request for a status IN transaction on endpoint zero.
ROM_USBHostReset
// Handles the USB bus reset condition.
ROM_USBHostResume
// Handles the USB bus resume condition.
ROM_USBHostSpeedGet
// Returns the current speed of the USB device connected.
ROM_USBHostSuspend
// Puts the USB bus in a suspended state.
ROM_USBIntDisable
// Disables the sources for USB interrupts.
ROM_USBIntDisableControl
// Disable control interrupts on a given USB controller.
ROM_USBIntDisableEndpoint
// Disable endpoint interrupts on a given USB controller.
ROM_USBIntEnable
// Enables the sources for USB interrupts.
ROM_USBIntEnableControl
// Enable control interrupts on a given USB controller.
ROM_USBIntEnableEndpoint
// Enable endpoint interrupts on a given USB controller.
ROM_USBIntStatus
// Returns the status of the USB interrupts.
ROM_USBIntStatusControl
// Returns the control interrupt status on a given USB controller.
ROM_USBIntStatusEndpoint
// Returns the endpoint interrupt status on a given USB controller.
ROM_USBModeGet
// Returns the current operating mode of the controller.
ROM_USBOTGHostRequest
// This function will enable host negotiation protocol when in device mode.
ROM_WatchdogEnable
// Enables the watchdog timer.
ROM_WatchdogIntClear
// Clears the watchdog timer interrupt.
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ROM DriverLib Functions
ROM_WatchdogIntEnable
// Enables the watchdog timer interrupt.
ROM_WatchdogIntStatus
// Gets the current watchdog timer interrupt status.
ROM_WatchdogLock
// Enables the watchdog timer lock mechanism.
ROM_WatchdogLockState
// Gets the state of the watchdog timer lock mechanism.
ROM_WatchdogReloadGet
// Gets the watchdog timer reload value.
ROM_WatchdogReloadSet
// Sets the watchdog timer reload value.
ROM_WatchdogResetDisable
// Disables the watchdog timer reset.
ROM_WatchdogResetEnable
// Enables the watchdog timer reset.
ROM_WatchdogRunning
// Determines if the watchdog timer is enabled.
ROM_WatchdogStallDisable
// Disables stalling of the watchdog timer during debug events.
ROM_WatchdogStallEnable
// Enables stalling of the watchdog timer during debug events.
ROM_WatchdogUnlock
// Disables the watchdog timer lock mechanism.
ROM_WatchdogValueGet
// Gets the current watchdog timer value.
ROM_ADCComparatorConfigure
// Configures an ADC digital comparator.
ROM_ADCComparatorIntClear
// Clears sample sequence comparator interrupt source.
ROM_ADCComparatorIntDisable
// Disables a sample sequence comparator interrupt.
ROM_ADCComparatorIntEnable
// Enables a sample sequence comparator interrupt.
ROM_ADCComparatorIntStatus
// Gets the current comparator interrupt status.
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ROM_ADCComparatorRegionSet
// Defines the ADC digital comparator regions.
ROM_ADCComparatorReset
// Resets the current ADC digital comparator conditions.
ROM_ADCHardwareOversampleConfigure
// Configures the hardware oversampling factor of the ADC.
ROM_ADCIntClear
// Clears sample sequence interrupt source.
ROM_ADCIntDisable
// Disables a sample sequence interrupt.
ROM_ADCIntEnable
// Enables a sample sequence interrupt.
ROM_ADCIntStatus
// Gets the current interrupt status.
ROM_ADCProcessorTrigger
// Causes a processor trigger for a sample sequence.
ROM_ADCSequenceConfigure
// Configures the trigger source and priority of a sample sequence.
ROM_ADCSequenceDataGet
// Gets the captured data for a sample sequence.
ROM_ADCSequenceDisable
// Disables a sample sequence.
ROM_ADCSequenceEnable
// Enables a sample sequence.
ROM_ADCSequenceOverflow
// Determines if a sample sequence overflow occurred.
ROM_ADCSequenceOverflowClear
// Clears the overflow condition on a sample sequence.
ROM_ADCSequenceStepConfigure
// Configure a step of the sample sequencer.
ROM_ADCSequenceUnderflow
// Determines if a sample sequence underflow occurred.
ROM_ADCSequenceUnderflowClear
// Clears the underflow condition on a sample sequence.
ROM_CANBitRateSet
// This function is used to set the CAN bit timing values to a nominal setting based on a desired
bit rate.
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ROM DriverLib Functions
ROM_CANBitTimingGet
// Reads the current settings for the CAN controller bit timing.
ROM_CANBitTimingSet
// Configures the CAN controller bit timing.
ROM_CANDisable
// Disables the CAN controller.
ROM_CANEnable
// Enables the CAN controller.
ROM_CANErrCntrGet
// Reads the CAN controller error counter register.
ROM_CANInit
// Initializes the CAN controller after reset.
ROM_CANIntClear
// Clears a CAN interrupt source.
ROM_CANIntDisable
// Disables individual CAN controller interrupt sources.
ROM_CANIntEnable
// Enables individual CAN controller interrupt sources.
ROM_CANIntStatus
// Returns the current CAN controller interrupt status.
ROM_CANMessageClear
// Clears a message object so that it is no longer used.
ROM_CANMessageGet
// Reads a CAN message from one of the message object buffers.
ROM_CANMessageSet
// Configures a message object in the CAN controller.
ROM_CANRetryGet
// Returns the current setting for automatic retransmission.
ROM_CANRetrySet
// Sets the CAN controller automatic retransmission behavior.
ROM_CANStatusGet
// Reads one of the controller status registers.
ROM_ComparatorConfigure
// Configures a comparator.
ROM_ComparatorIntClear
// Clears a comparator interrupt.
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ROM_ComparatorIntDisable
// Disables the comparator interrupt.
ROM_ComparatorIntEnable
// Enables the comparator interrupt.
ROM_ComparatorIntStatus
// Gets the current interrupt status.
ROM_ComparatorRefSet
// Sets the internal reference voltage.
ROM_ComparatorValueGet
// Gets the current comparator output value.
ROM_Crc16Array
// Calculates the CRC-16 of an array of words.
ROM_Crc16Array3
// Calculates three CRC-16s of an array of words.
ROM_EPIAddressMapSet
// Configures the address map for the external interface.
ROM_EPIConfigGPModeSet
// Configures the interface for general-purpose mode operation.
ROM_EPIConfigHB16Set
// Configures the interface for Host-bus 16 operation.
ROM_EPIConfigHB8Set
// Configures the interface for Host-bus 8 operation.
ROM_EPIConfigSDRAMSet
// Configures the SDRAM mode of operation.
ROM_EPIDividerSet
// Sets the clock divider for the EPI module.
ROM_EPIFIFOConfig
// Configures the read FIFO.
ROM_EPIIntDisable
// Disables EPI interrupt sources.
ROM_EPIIntEnable
// Enables EPI interrupt sources.
ROM_EPIIntErrorClear
// Clears pending EPI error sources.
ROM_EPIIntErrorStatus
// Gets the EPI error interrupt status.
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ROM DriverLib Functions
ROM_EPIIntStatus
// Gets the EPI interrupt status.
ROM_EPIModeSet
// Sets the usage mode of the EPI module.
ROM_EPINonBlockingReadAvail
// Get the count of items available in the read FIFO.
ROM_EPINonBlockingReadConfigure
// Configures a non-blocking read transaction.
ROM_EPINonBlockingReadCount
// Get the count remaining for a non-blocking transaction.
ROM_EPINonBlockingReadGet16
// Read available data from the read FIFO, as 16-bit data items.
ROM_EPINonBlockingReadGet32
// Read available data from the read FIFO, as 32-bit data items.
ROM_EPINonBlockingReadGet8
// Read available data from the read FIFO, as 8-bit data items.
ROM_EPINonBlockingReadStart
// Starts a non-blocking read transaction.
ROM_EPINonBlockingReadStop
// Stops a non-blocking read transaction.
ROM_EPIWriteFIFOCountGet
// Reads the number of empty slots in the write transaction FIFO.
ROM_FlashErase
// Erases a block of flash.
ROM_FlashIntClear
// Clears flash controller interrupt sources.
ROM_FlashIntDisable
// Disables individual flash controller interrupt sources.
ROM_FlashIntEnable
// Enables individual flash controller interrupt sources.
ROM_FlashIntGetStatus
// Gets the current interrupt status.
ROM_FlashProgram
// Programs flash.
ROM_FlashProtectGet
// Gets the protection setting for a block of flash.
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ROM_FlashProtectSave
// Saves the flash protection settings.
ROM_FlashProtectSet
// Sets the protection setting for a block of flash.
ROM_FlashUsecGet
// Gets the number of processor clocks per micro-second.
ROM_FlashUsecSet
// Sets the number of processor clocks per micro-second.
ROM_FlashUserGet
// Gets the user registers.
ROM_FlashUserSave
// Saves the user registers.
ROM_FlashUserSet
// Sets the user registers.
ROM_GPIODirModeGet
// Gets the direction and mode of a pin.
ROM_GPIODirModeSet
// Sets the direction and mode of the specified pin(s).
ROM_GPIOIntTypeGet
// Gets the interrupt type for a pin.
ROM_GPIOIntTypeSet
// Sets the interrupt type for the specified pin(s).
ROM_GPIOPadConfigGet
// Gets the pad configuration for a pin.
ROM_GPIOPadConfigSet
// Sets the pad configuration for the specified pin(s).
ROM_GPIOPinConfigure
// Configures the alternate function of a GPIO pin.
ROM_GPIOPinIntClear
// Clears the interrupt for the specified pin(s).
ROM_GPIOPinIntDisable
// Disables interrupts for the specified pin(s).
ROM_GPIOPinIntEnable
// Enables interrupts for the specified pin(s).
ROM_GPIOPinIntStatus
// Gets interrupt status for the specified GPIO port.
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ROM DriverLib Functions
ROM_GPIOPinRead
// Reads the values present of the specified pin(s).
ROM_GPIOPinTypeADC
// Configures pin(s) for use as analog-to-digital converter inputs.
ROM_GPIOPinTypeCAN
// Configures pin(s) for use as a CAN device.
ROM_GPIOPinTypeComparator
// Configures pin(s) for use as an analog comparator input.
ROM_GPIOPinTypeGPIOInput
// Configures pin(s) for use as GPIO inputs.
ROM_GPIOPinTypeGPIOOutput
// Configures pin(s) for use as GPIO outputs.
ROM_GPIOPinTypeGPIOOutputOD
// Configures pin(s) for use as GPIO open drain outputs.
ROM_GPIOPinTypeI2C
// Configures pin(s) for use by the I2C peripheral.
ROM_GPIOPinTypeI2S
// Configures pin(s) for use by the I2S peripheral.
ROM_GPIOPinTypePWM
// Configures pin(s) for use by the PWM peripheral.
ROM_GPIOPinTypeQEI
// Configures pin(s) for use by the QEI peripheral.
ROM_GPIOPinTypeSSI
// Configures pin(s) for use by the SSI peripheral.
ROM_GPIOPinTypeTimer
// Configures pin(s) for use by the Timer peripheral.
ROM_GPIOPinTypeUART
// Configures pin(s) for use by the UART peripheral.
ROM_GPIOPinTypeUSBAnalog
// Configures pin(s) for use by the USB peripheral.
ROM_GPIOPinTypeUSBDigital
// Configures pin(s) for use by the USB peripheral.
ROM_GPIOPinWrite
// Writes a value to the specified pin(s).
ROM_I2CMasterBusBusy
// Indicates whether or not the I2C bus is busy.
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ROM_I2CMasterBusy
// Indicates whether or not the I2C Master is busy.
ROM_I2CMasterControl
// Controls the state of the I2C Master module.
ROM_I2CMasterDataGet
// Receives a byte that has been sent to the I2C Master.
ROM_I2CMasterDataPut
// Transmits a byte from the I2C Master.
ROM_I2CMasterDisable
// Disables the I2C master block.
ROM_I2CMasterEnable
// Enables the I2C Master block.
ROM_I2CMasterErr
// Gets the error status of the I2C Master module.
ROM_I2CMasterInitExpClk
// Initializes the I2C Master block.
ROM_I2CMasterIntClear
// Clears I2C Master interrupt sources.
ROM_I2CMasterIntDisable
// Disables the I2C Master interrupt.
ROM_I2CMasterIntEnable
// Enables the I2C Master interrupt.
ROM_I2CMasterIntStatus
// Gets the current I2C Master interrupt status.
ROM_I2CMasterSlaveAddrSet
// Sets the address that the I2C Master will place on the bus.
ROM_I2CSlaveDataGet
// Receives a byte that has been sent to the I2C Slave.
ROM_I2CSlaveDataPut
// Transmits a byte from the I2C Slave.
ROM_I2CSlaveDisable
// Disables the I2C slave block.
ROM_I2CSlaveEnable
// Enables the I2C Slave block.
ROM_I2CSlaveInit
// Initializes the I2C Slave block.
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ROM DriverLib Functions
ROM_I2CSlaveIntClear
// Clears I2C Slave interrupt sources.
ROM_I2CSlaveIntClearEx
// Clears I2C Slave interrupt sources.
ROM_I2CSlaveIntDisable
// Disables the I2C Slave interrupt.
ROM_I2CSlaveIntDisableEx
// Disables individual I2C Slave interrupt sources.
ROM_I2CSlaveIntEnable
// Enables the I2C Slave interrupt.
ROM_I2CSlaveIntEnableEx
// Enables individual I2C Slave interrupt sources.
ROM_I2CSlaveIntStatus
// Gets the current I2C Slave interrupt status.
ROM_I2CSlaveIntStatusEx
// Gets the current I2C Slave interrupt status.
ROM_I2CSlaveStatus
// Gets the I2C Slave module status
ROM_I2SIntClear
// Clears pending I2S interrupt sources.
ROM_I2SIntDisable
// Disables I2S interrupt sources.
ROM_I2SIntEnable
// Enables I2S interrupt sources.
ROM_I2SIntStatus
// Gets the I2S interrupt status.
ROM_I2SMasterClockSelect
// Selects the source of the master clock, internal or external.
ROM_I2SRxConfigSet
// Configures the I2S receive module.
ROM_I2SRxDataGet
// Reads data samples from the I2S receive FIFO with blocking.
ROM_I2SRxDataGetNonBlocking
// Reads data samples from the I2S receive FIFO without blocking.
ROM_I2SRxDisable
// Disables the I2S receive module for operation.
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ROM_I2SRxEnable
// Enables the I2S receive module for operation.
ROM_I2SRxFIFOLevelGet
// Gets the number of samples in the receive FIFO.
ROM_I2SRxFIFOLimitGet
// Gets the current setting of the FIFO service request level.
ROM_I2SRxFIFOLimitSet
// Sets the FIFO level at which a service request is generated.
ROM_I2STxConfigSet
// Configures the I2S transmit module.
ROM_I2STxDataPut
// Writes data samples to the I2S transmit FIFO with blocking.
ROM_I2STxDataPutNonBlocking
// Writes data samples to the I2S transmit FIFO without blocking.
ROM_I2STxDisable
// Disables the I2S transmit module for operation.
ROM_I2STxEnable
// Enables the I2S transmit module for operation.
ROM_I2STxFIFOLevelGet
// Gets the number of samples in the transmit FIFO.
ROM_I2STxFIFOLimitGet
// Gets the current setting of the FIFO service request level.
ROM_I2STxFIFOLimitSet
// Sets the FIFO level at which a service request is generated.
ROM_I2STxRxConfigSet
// Configures the I2S transmit and receive modules.
ROM_I2STxRxDisable
// Disables the I2S transmit and receive modules.
ROM_I2STxRxEnable
// Enables the I2S transmit and receive modules for operation.
ROM_IntDisable
// Disables an interrupt.
ROM_IntEnable
// Enables an interrupt.
ROM_IntMasterDisable
// Disables the processor interrupt.
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ROM DriverLib Functions
ROM_IntMasterEnable
// Enables the processor interrupt.
ROM_IntPendClear
// Unpends an interrupt.
ROM_IntPendSet
// Pends an interrupt.
ROM_IntPriorityGet
// Gets the priority of an interrupt.
ROM_IntPriorityGroupingGet
// Gets the priority grouping of the interrupt controller.
ROM_IntPriorityGroupingSet
// Sets the priority grouping of the interrupt controller.
ROM_IntPrioritySet
// Sets the priority of an interrupt.
ROM_MPUDisable
// Disables the MPU for use.
ROM_MPUEnable
// Enables and configures the MPU for use.
ROM_MPURegionCountGet
// Gets the count of regions supported by the MPU.
ROM_MPURegionDisable
// Disables a specific region.
ROM_MPURegionEnable
// Enables a specific region.
ROM_MPURegionGet
// Gets the current settings for a specific region.
ROM_MPURegionSet
// Sets up the access rules for a specific region.
ROM_pvAESTable
// AES forward, reverse, S-box, and reverse S-box tables.
ROM_PWMDeadBandDisable
// Disables the PWM dead band output.
ROM_PWMDeadBandEnable
// Enables the PWM dead band output, and sets the dead band delays.
ROM_PWMFaultIntClear
// Clears the fault interrupt for a PWM module.
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Stellaris® LM3S5B91 Microcontroller
ROM_PWMFaultIntClearExt
// Clears the fault interrupt for a PWM module.
ROM_PWMGenConfigure
// Configures a PWM generator.
ROM_PWMGenDisable
// Disables the timer/counter for a PWM generator block.
ROM_PWMGenEnable
// Enables the timer/counter for a PWM generator block.
ROM_PWMGenFaultClear
// Clears one or more latched fault triggers for a given PWM generator.
ROM_PWMGenFaultConfigure
// Configures the minimum fault period and fault pin senses for a given PWM generator.
ROM_PWMGenFaultStatus
// Returns the current state of the fault triggers for a given PWM generator.
ROM_PWMGenFaultTriggerGet
// Returns the set of fault triggers currently configured for a given PWM generator.
ROM_PWMGenFaultTriggerSet
// Configures the set of fault triggers for a given PWM generator.
ROM_PWMGenIntClear
// Clears the specified interrupt(s) for the specified PWM generator block.
ROM_PWMGenIntStatus
// Gets interrupt status for the specified PWM generator block.
ROM_PWMGenIntTrigDisable
// Disables interrupts for the specified PWM generator block.
ROM_PWMGenIntTrigEnable
// Enables interrupts and triggers for the specified PWM generator block.
ROM_PWMGenPeriodGet
// Gets the period of a PWM generator block.
ROM_PWMGenPeriodSet
// Set the period of a PWM generator.
ROM_PWMIntDisable
// Disables generator and fault interrupts for a PWM module.
ROM_PWMIntEnable
// Enables generator and fault interrupts for a PWM module.
ROM_PWMIntStatus
// Gets the interrupt status for a PWM module.
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ROM DriverLib Functions
ROM_PWMOutputFault
// Specifies the state of PWM outputs in response to a fault condition.
ROM_PWMOutputFaultLevel
// Specifies the level of PWM outputs suppressed in response to a fault condition.
ROM_PWMOutputInvert
// Selects the inversion mode for PWM outputs.
ROM_PWMOutputState
// Enables or disables PWM outputs.
ROM_PWMPulseWidthGet
// Gets the pulse width of a PWM output.
ROM_PWMPulseWidthSet
// Sets the pulse width for the specified PWM output.
ROM_PWMSyncTimeBase
// Synchronizes the counters in one or multiple PWM generator blocks.
ROM_PWMSyncUpdate
// Synchronizes all pending updates.
ROM_QEIConfigure
// Configures the quadrature encoder.
ROM_QEIDirectionGet
// Gets the current direction of rotation.
ROM_QEIDisable
// Disables the quadrature encoder.
ROM_QEIEnable
// Enables the quadrature encoder.
ROM_QEIErrorGet
// Gets the encoder error indicator.
ROM_QEIIntClear
// Clears quadrature encoder interrupt sources.
ROM_QEIIntDisable
// Disables individual quadrature encoder interrupt sources.
ROM_QEIIntEnable
// Enables individual quadrature encoder interrupt sources.
ROM_QEIIntStatus
// Gets the current interrupt status.
ROM_QEIPositionGet
// Gets the current encoder position.
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Stellaris® LM3S5B91 Microcontroller
ROM_QEIPositionSet
// Sets the current encoder position.
ROM_QEIVelocityConfigure
// Configures the velocity capture.
ROM_QEIVelocityDisable
// Disables the velocity capture.
ROM_QEIVelocityEnable
// Enables the velocity capture.
ROM_QEIVelocityGet
// Gets the current encoder speed.
ROM_SSIBusy
// Determines whether the SSI transmitter is busy or not.
ROM_SSIConfigSetExpClk
// Configures the synchronous serial interface.
ROM_SSIDataGet
// Gets a data element from the SSI receive FIFO.
ROM_SSIDataGetNonBlocking
// Gets a data element from the SSI receive FIFO.
ROM_SSIDataPut
// Puts a data element into the SSI transmit FIFO.
ROM_SSIDataPutNonBlocking
// Puts a data element into the SSI transmit FIFO.
ROM_SSIDisable
// Disables the synchronous serial interface.
ROM_SSIDMADisable
// Disable SSI DMA operation.
ROM_SSIDMAEnable
// Enable SSI DMA operation.
ROM_SSIEnable
// Enables the synchronous serial interface.
ROM_SSIIntClear
// Clears SSI interrupt sources.
ROM_SSIIntDisable
// Disables individual SSI interrupt sources.
ROM_SSIIntEnable
// Enables individual SSI interrupt sources.
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ROM DriverLib Functions
ROM_SSIIntStatus
// Gets the current interrupt status.
ROM_SysCtlADCSpeedGet
// Gets the sample rate of the ADC.
ROM_SysCtlADCSpeedSet
// Sets the sample rate of the ADC.
ROM_SysCtlClockGet
// Gets the processor clock rate.
ROM_SysCtlClockSet
// Sets the clocking of the device.
ROM_SysCtlDeepSleep
// Puts the processor into deep-sleep mode.
ROM_SysCtlDelay
// Provides a small delay.
ROM_SysCtlFlashSizeGet
// Gets the size of the flash.
ROM_SysCtlGPIOAHBDisable
// Disables a GPIO peripheral for access from the AHB.
ROM_SysCtlGPIOAHBEnable
// Enables a GPIO peripheral for access from the AHB.
ROM_SysCtlI2SMClkSet
// Sets the MCLK frequency provided to the I2S module.
ROM_SysCtlIntClear
// Clears system control interrupt sources.
ROM_SysCtlIntDisable
// Disables individual system control interrupt sources.
ROM_SysCtlIntEnable
// Enables individual system control interrupt sources.
ROM_SysCtlIntStatus
// Gets the current interrupt status.
ROM_SysCtlLDOGet
// Gets the output voltage of the LDO.
ROM_SysCtlLDOSet
// Sets the output voltage of the LDO.
ROM_SysCtlPeripheralClockGating
// Controls peripheral clock gating in sleep and deep-sleep mode.
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Stellaris® LM3S5B91 Microcontroller
ROM_SysCtlPeripheralDeepSleepDisable
// Disables a peripheral in deep-sleep mode.
ROM_SysCtlPeripheralDeepSleepEnable
// Enables a peripheral in deep-sleep mode.
ROM_SysCtlPeripheralDisable
// Disables a peripheral.
ROM_SysCtlPeripheralEnable
// Enables a peripheral.
ROM_SysCtlPeripheralPresent
// Determines if a peripheral is present.
ROM_SysCtlPeripheralReset
// Performs a software reset of a peripheral.
ROM_SysCtlPeripheralSleepDisable
// Disables a peripheral in sleep mode.
ROM_SysCtlPeripheralSleepEnable
// Enables a peripheral in sleep mode.
ROM_SysCtlPinPresent
// Determines if a pin is present.
ROM_SysCtlPWMClockGet
// Gets the current PWM clock configuration.
ROM_SysCtlPWMClockSet
// Sets the PWM clock configuration.
ROM_SysCtlReset
// Resets the device.
ROM_SysCtlResetCauseClear
// Clears reset reasons.
ROM_SysCtlResetCauseGet
// Gets the reason for a reset.
ROM_SysCtlSleep
// Puts the processor into sleep mode.
ROM_SysCtlSRAMSizeGet
// Gets the size of the SRAM.
ROM_SysCtlUSBPLLDisable
// Powers down the USB PLL.
ROM_SysCtlUSBPLLEnable
// Powers up the USB PLL.
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ROM DriverLib Functions
ROM_SysTickDisable
// Disables the SysTick counter.
ROM_SysTickEnable
// Enables the SysTick counter.
ROM_SysTickIntDisable
// Disables the SysTick interrupt.
ROM_SysTickIntEnable
// Enables the SysTick interrupt.
ROM_SysTickPeriodGet
// Gets the period of the SysTick counter.
ROM_SysTickPeriodSet
// Sets the period of the SysTick counter.
ROM_SysTickValueGet
// Gets the current value of the SysTick counter.
ROM_TimerConfigure
// Configures the timer(s).
ROM_TimerControlEvent
// Controls the event type.
ROM_TimerControlLevel
// Controls the output level.
ROM_TimerControlStall
// Controls the stall handling.
ROM_TimerControlTrigger
// Enables or disables the trigger output.
ROM_TimerDisable
// Disables the timer(s).
ROM_TimerEnable
// Enables the timer(s).
ROM_TimerIntClear
// Clears timer interrupt sources.
ROM_TimerIntDisable
// Disables individual timer interrupt sources.
ROM_TimerIntEnable
// Enables individual timer interrupt sources.
ROM_TimerIntStatus
// Gets the current interrupt status.
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Stellaris® LM3S5B91 Microcontroller
ROM_TimerLoadGet
// Gets the timer load value.
ROM_TimerLoadSet
// Sets the timer load value.
ROM_TimerMatchGet
// Gets the timer match value.
ROM_TimerMatchSet
// Sets the timer match value.
ROM_TimerPrescaleGet
// Get the timer prescale value.
ROM_TimerPrescaleSet
// Set the timer prescale value.
ROM_TimerRTCDisable
// Disable RTC counting.
ROM_TimerRTCEnable
// Enable RTC counting.
ROM_TimerValueGet
// Gets the current timer value.
ROM_UARTBreakCtl
// Causes a BREAK to be sent.
ROM_UARTBusy
// Determines whether the UART transmitter is busy or not.
ROM_UARTCharGet
// Waits for a character from the specified port.
ROM_UARTCharGetNonBlocking
// Receives a character from the specified port.
ROM_UARTCharPut
// Waits to send a character from the specified port.
ROM_UARTCharPutNonBlocking
// Sends a character to the specified port.
ROM_UARTCharsAvail
// Determines if there are any characters in the receive FIFO.
ROM_UARTConfigGetExpClk
// Gets the current configuration of a UART.
ROM_UARTConfigSetExpClk
// Sets the configuration of a UART.
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ROM DriverLib Functions
ROM_UARTDisable
// Disables transmitting and receiving.
ROM_UARTDisableSIR
// Disables SIR (IrDA) mode on the specified UART.
ROM_UARTDMADisable
// Disable UART DMA operation.
ROM_UARTDMAEnable
// Enable UART DMA operation.
ROM_UARTEnable
// Enables transmitting and receiving.
ROM_UARTEnableSIR
// Enables SIR (IrDA) mode on the specified UART.
ROM_UARTFIFODisable
// Disables the transmit and receive FIFOs.
ROM_UARTFIFOEnable
// Enables the transmit and receive FIFOs.
ROM_UARTFIFOLevelGet
// Gets the FIFO level at which interrupts are generated.
ROM_UARTFIFOLevelSet
// Sets the FIFO level at which interrupts are generated.
ROM_UARTIntClear
// Clears UART interrupt sources.
ROM_UARTIntDisable
// Disables individual UART interrupt sources.
ROM_UARTIntEnable
// Enables individual UART interrupt sources.
ROM_UARTIntStatus
// Gets the current interrupt status.
ROM_UARTParityModeGet
// Gets the type of parity currently being used.
ROM_UARTParityModeSet
// Sets the type of parity.
ROM_UARTRxErrorClear
// Clears all reported receiver errors.
ROM_UARTRxErrorGet
// Gets current receiver errors.
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Stellaris® LM3S5B91 Microcontroller
ROM_UARTSpaceAvail
// Determines if there is any space in the transmit FIFO.
ROM_UARTTxIntModeGet
// Returns the current operating mode for the UART transmit interrupt.
ROM_UARTTxIntModeSet
// Sets the operating mode for the UART transmit interrupt.
ROM_uDMAChannelAttributeDisable
// Disables attributes of a uDMA channel.
ROM_uDMAChannelAttributeEnable
// Enables attributes of a uDMA channel.
ROM_uDMAChannelAttributeGet
// Gets the enabled attributes of a uDMA channel.
ROM_uDMAChannelControlSet
// Sets the control parameters for a uDMA channel.
ROM_uDMAChannelDisable
// Disables a uDMA channel for operation.
ROM_uDMAChannelEnable
// Enables a uDMA channel for operation.
ROM_uDMAChannelIsEnabled
// Checks if a uDMA channel is enabled for operation.
ROM_uDMAChannelModeGet
// Gets the transfer mode for a uDMA channel.
ROM_uDMAChannelRequest
// Requests a uDMA channel to start a transfer.
ROM_uDMAChannelSelectDefault
// Selects the default peripheral for a set of uDMA channels.
ROM_uDMAChannelSelectSecondary
// Selects the secondary peripheral for a set of uDMA channels.
ROM_uDMAChannelSizeGet
// Gets the current transfer size for a uDMA channel.
ROM_uDMAChannelTransferSet
// Sets the transfer parameters for a uDMA channel.
ROM_uDMAControlBaseGet
// Gets the base address for the channel control table.
ROM_uDMAControlBaseSet
// Sets the base address for the channel control table.
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ROM DriverLib Functions
ROM_uDMADisable
// Disables the uDMA controller for use.
ROM_uDMAEnable
// Enables the uDMA controller for use.
ROM_uDMAErrorStatusClear
// Clears the uDMA error interrupt.
ROM_uDMAErrorStatusGet
// Gets the uDMA error status.
ROM_UpdateI2C
// Starts an update over the I2C0 interface.
ROM_UpdateSSI
// Starts an update over the SSI0 interface.
ROM_UpdateUART
// Starts an update over the UART0 interface.
ROM_USBDevAddrGet
// Returns the current device address in device mode.
ROM_USBDevAddrSet
// Sets the address in device mode.
ROM_USBDevConnect
// Connects the USB controller to the bus in device mode.
ROM_USBDevDisconnect
// Removes the USB controller from the bus in device mode.
ROM_USBDevEndpointConfigGet
// Gets the current configuration for an endpoint.
ROM_USBDevEndpointConfigSet
// Sets the configuration for an endpoint.
ROM_USBDevEndpointDataAck
// Acknowledge that data was read from the given endpoint's FIFO in device mode.
ROM_USBDevEndpointStall
// Stalls the specified endpoint in device mode.
ROM_USBDevEndpointStallClear
// Clears the stall condition on the specified endpoint in device mode.
ROM_USBDevEndpointStatusClear
// Clears the status bits in this endpoint in device mode.
ROM_USBEndpointDataAvail
// Determine the number of bytes of data available in a given endpoint's FIFO.
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Stellaris® LM3S5B91 Microcontroller
ROM_USBEndpointDataGet
// Retrieves data from the given endpoint's FIFO.
ROM_USBEndpointDataPut
// Puts data into the given endpoint's FIFO.
ROM_USBEndpointDataSend
// Starts the transfer of data from an endpoint's FIFO.
ROM_USBEndpointDataToggleClear
// Sets the Data toggle on an endpoint to zero.
ROM_USBEndpointDMAChannel
// Sets the DMA channel to use for a given endpoint.
ROM_USBEndpointDMADisable
// Disable DMA on a given endpoint.
ROM_USBEndpointDMAEnable
// Enable DMA on a given endpoint.
ROM_USBEndpointStatus
// Returns the current status of an endpoint.
ROM_USBFIFOAddrGet
// Returns the absolute FIFO address for a given endpoint.
ROM_USBFIFOConfigGet
// Returns the FIFO configuration for an endpoint.
ROM_USBFIFOConfigSet
// Sets the FIFO configuration for an endpoint.
ROM_USBFIFOFlush
// Forces a flush of an endpoint's FIFO.
ROM_USBFrameNumberGet
// Get the current frame number.
ROM_USBHostAddrGet
// Gets the current functional device address for an endpoint.
ROM_USBHostAddrSet
// Sets the functional address for the device that is connected to an endpoint in host mode.
ROM_USBHostEndpointConfig
// Sets the base configuration for a host endpoint.
ROM_USBHostEndpointDataAck
// Acknowledge that data was read from the given endpoint's FIFO in host mode.
ROM_USBHostEndpointDataToggle
// Sets the value data toggle on an endpoint in host mode.
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ROM DriverLib Functions
ROM_USBHostEndpointStatusClear
// Clears the status bits in this endpoint in host mode.
ROM_USBHostHubAddrGet
// Get the current device hub address for this endpoint.
ROM_USBHostHubAddrSet
// Set the hub address for the device that is connected to an endpoint.
ROM_USBHostMode
// Change the mode of the USB controller to host.
ROM_USBHostPwrDisable
// Disables the external power pin.
ROM_USBHostPwrEnable
// Enables the external power pin.
ROM_USBHostPwrFaultConfig
// Sets the configuration for USB power fault.
ROM_USBHostPwrFaultDisable
// Disables power fault detection.
ROM_USBHostPwrFaultEnable
// Enables power fault detection.
ROM_USBHostRequestIN
// Schedules a request for an IN transaction on an endpoint in host mode.
ROM_USBHostRequestStatus
// Issues a request for a status IN transaction on endpoint zero.
ROM_USBHostReset
// Handles the USB bus reset condition.
ROM_USBHostResume
// Handles the USB bus resume condition.
ROM_USBHostSpeedGet
// Returns the current speed of the USB device connected.
ROM_USBHostSuspend
// Puts the USB bus in a suspended state.
ROM_USBIntDisable
// Disables the sources for USB interrupts.
ROM_USBIntDisableControl
// Disable control interrupts on a given USB controller.
ROM_USBIntDisableEndpoint
// Disable endpoint interrupts on a given USB controller.
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ROM_USBIntEnable
// Enables the sources for USB interrupts.
ROM_USBIntEnableControl
// Enable control interrupts on a given USB controller.
ROM_USBIntEnableEndpoint
// Enable endpoint interrupts on a given USB controller.
ROM_USBIntStatus
// Returns the status of the USB interrupts.
ROM_USBIntStatusControl
// Returns the control interrupt status on a given USB controller.
ROM_USBIntStatusEndpoint
// Returns the endpoint interrupt status on a given USB controller.
ROM_USBModeGet
// Returns the current operating mode of the controller.
ROM_USBOTGHostRequest
// This function will enable host negotiation protocol when in device mode.
ROM_WatchdogEnable
// Enables the watchdog timer.
ROM_WatchdogIntClear
// Clears the watchdog timer interrupt.
ROM_WatchdogIntEnable
// Enables the watchdog timer interrupt.
ROM_WatchdogIntStatus
// Gets the current watchdog timer interrupt status.
ROM_WatchdogLock
// Enables the watchdog timer lock mechanism.
ROM_WatchdogLockState
// Gets the state of the watchdog timer lock mechanism.
ROM_WatchdogReloadGet
// Gets the watchdog timer reload value.
ROM_WatchdogReloadSet
// Sets the watchdog timer reload value.
ROM_WatchdogResetDisable
// Disables the watchdog timer reset.
ROM_WatchdogResetEnable
// Enables the watchdog timer reset.
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ROM DriverLib Functions
ROM_WatchdogRunning
// Determines if the watchdog timer is enabled.
ROM_WatchdogStallDisable
// Disables stalling of the watchdog timer during debug events.
ROM_WatchdogStallEnable
// Enables stalling of the watchdog timer during debug events.
ROM_WatchdogUnlock
// Disables the watchdog timer lock mechanism.
ROM_WatchdogValueGet
// Gets the current watchdog timer value.
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Stellaris® LM3S5B91 Microcontroller
C
Advance Encryption Standard and Cyclic
Redundancy Check Software in ROM
AES and CRC software is available in the integrated ROM of the LM3S5B91 microcontroller. For
more information on this software, see the Stellaris® ROM User’s Guide.
C.1
Advanced Encryption Standard Software
The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government. It is a strong encryption method with reasonable performance and size. AES is
fast in both hardware and software, is fairly easy to implement, and requires little memory. AES is
ideal for applications that can use pre-arranged keys, such as setup during manufacturing or
configuration.
C.2
Cyclic Redundancy Check Software
CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents
as when previously checked. This technique can be used to validate correct receipt of messages
(nothing lost or modified in transit), to validate data after decompression, to validate that Flash
memory contents have not been changed, and for other cases where the data needs to be validated.
A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more
readily.
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Register Quick Reference
D
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset VER
CLASS
MAJOR
MINOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD
BORIOR
RIS, type RO, offset 0x050, reset 0x0000.0000
MOSCPUPRIS USBPLLLRIS
PLLLRIS
BORRIS
MOSCPUPIM USBPLLLIM
PLLLIM
BORIM
MOSCPUPMIS USBPLLLMIS
PLLLMIS
BORMIS
IMC, type R/W, offset 0x054, reset 0x0000.0000
MISC, type R/W1C, offset 0x058, reset 0x0000.0000
RESC, type R/W, offset 0x05C, reset MOSCFAIL
WDT1
SW
WDT0
BOR
POR
EXT
RCC, type R/W, offset 0x060, reset 0x078E.3AD1
ACG
PWRDN
SYSDIV
BYPASS
USESYSDIV
XTAL
PWMDIV
USEPWMDIV
OSCSRC
IOSCDIS MOSCDIS
PLLCFG, type RO, offset 0x064, reset -
F
R
GPIOHBCTL, type R/W, offset 0x06C, reset 0x0000.0000
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
RCC2, type R/W, offset 0x070, reset 0x07C0.6810
USERCC2
DIV400
USBPWRDN
SYSDIV2
PWRDN2
SYSDIV2LSB
BYPASS2
OSCSRC2
MOSCCTL, type R/W, offset 0x07C, reset 0x0000.0000
CVAL
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000
DSDIVORIDE
DSOSCSRC
PIOSCCAL, type R/W, offset 0x150, reset 0x0000.0000
UTEN
UPDATE
UT
I2SMCLKCFG, type R/W, offset 0x170, reset 0x0000.0000
RXEN
RXI
RXF
TXEN
TXI
TXF
DID1, type RO, offset 0x004, reset VER
FAM
PARTNO
PINCOUNT
TEMP
PKG
ROHS
QUAL
DC0, type RO, offset 0x008, reset 0x017F.007F
SRAMSZ
FLASHSZ
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Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAN1
CAN0
ADC1
ADC0
WDT0
SWO
SWD
JTAG
TIMER3
TIMER2
TIMER1
TIMER0
UART2
UART1
UART0
DC1, type RO, offset 0x010, reset WDT1
MINSYSDIV
MAXADC1SPD
MAXADC0SPD
PWM
MPU
TEMPSNS
PLL
SSI1
SSI0
ADC0AIN5
ADC0AIN4
ADC0AIN3
ADC0AIN2
ADC0AIN1
ADC0AIN0
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
PWM3
PWM2
PWM1
PWM0
DC2, type RO, offset 0x014, reset 0x570F.5337
EPI0
I2S0
I2C1
I2C0
COMP2
COMP1
COMP0
QEI1
QEI0
CCP1
CCP0
DC3, type RO, offset 0x018, reset 0xBFFF.FFFF
32KHZ
PWMFAULT
CCP5
C2O
CCP4
C2PLUS C2MINUS
CCP3
C1O
CCP2
C1PLUS C1MINUS
C0O
ADC0AIN7
ADC0AIN6
C0PLUS C0MINUS
DC4, type RO, offset 0x01C, reset 0x0000.F1FF
CCP7
CCP6
UDMA
ROM
GPIOJ
GPIOH
GPIOG
PWM7
PWM6
DC5, type RO, offset 0x020, reset 0x0F30.00FF
PWMEFLT PWMESYNC
PWMFAULT3 PWMFAULT2 PWMFAULT1 PWMFAULT0
PWM5
PWM4
DC6, type RO, offset 0x024, reset 0x0000.0013
USB0PHY
USB0
DC7, type RO, offset 0x028, reset 0xFFFF.FFFF
DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16
DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 DMACH3 DMACH2 DMACH1 DMACH0
DC8, type RO, offset 0x02C, reset 0xFFFF.FFFF
ADC1AIN15 ADC1AIN14 ADC1AIN13 ADC1AIN12 ADC1AIN11 ADC1AIN10 ADC1AIN9
ADC1AIN8
ADC1AIN7
ADC1AIN6
ADC1AIN5
ADC1AIN4
ADC1AIN3
ADC1AIN2
ADC1AIN1
ADC1AIN0
ADC0AIN15 ADC0AIN14 ADC0AIN13 ADC0AIN12 ADC0AIN11 ADC0AIN10 ADC0AIN9
ADC0AIN8
ADC0AIN7
ADC0AIN6
ADC0AIN5
ADC0AIN4
ADC0AIN3
ADC0AIN2
ADC0AIN1
ADC0AIN0
DC9, type RO, offset 0x190, reset 0x00FF.00FF
ADC1DC7 ADC1DC6 ADC1DC5 ADC1DC4 ADC1DC3 ADC1DC2 ADC1DC1 ADC1DC0
ADC0DC7 ADC0DC6 ADC0DC5 ADC0DC4 ADC0DC3 ADC0DC2 ADC0DC1 ADC0DC0
NVMSTAT, type RO, offset 0x1A0, reset 0x0000.0001
FWB
RCGC0, type R/W, offset 0x100, reset 0x00000040
WDT1
CAN1
MAXADC1SPD
CAN0
PWM
MAXADC0SPD
ADC1
ADC0
ADC1
ADC0
ADC1
ADC0
TIMER2
TIMER1
TIMER0
UART2
UART1
UART0
TIMER2
TIMER1
TIMER0
UART2
UART1
UART0
TIMER2
TIMER1
TIMER0
UART2
UART1
UART0
GPIOC
GPIOB
GPIOA
WDT0
SCGC0, type R/W, offset 0x110, reset 0x00000040
WDT1
CAN1
MAXADC1SPD
CAN0
PWM
MAXADC0SPD
WDT0
DCGC0, type R/W, offset 0x120, reset 0x00000040
WDT1
CAN1
CAN0
PWM
WDT0
RCGC1, type R/W, offset 0x104, reset 0x00000000
EPI0
I2S0
I2C1
I2C0
COMP2
COMP1
COMP0
QEI1
QEI0
COMP1
COMP0
QEI1
QEI0
COMP1
COMP0
QEI1
QEI0
TIMER3
SSI1
SSI0
SSI1
SSI0
SSI1
SSI0
GPIOF
GPIOE
SCGC1, type R/W, offset 0x114, reset 0x00000000
EPI0
I2S0
I2C1
I2C0
COMP2
TIMER3
DCGC1, type R/W, offset 0x124, reset 0x00000000
EPI0
I2S0
I2C1
I2C0
COMP2
TIMER3
RCGC2, type R/W, offset 0x108, reset 0x00000000
USB0
UDMA
GPIOJ
GPIOH
GPIOG
May 24, 2010
GPIOD
1217
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
ADC1
ADC0
TIMER2
TIMER1
TIMER0
UART2
UART1
UART0
GPIOC
GPIOB
GPIOA
SCGC2, type R/W, offset 0x118, reset 0x00000000
USB0
UDMA
DCGC2, type R/W, offset 0x128, reset 0x00000000
USB0
UDMA
SRCR0, type R/W, offset 0x040, reset 0x00000000
WDT1
CAN1
CAN0
PWM
WDT0
SRCR1, type R/W, offset 0x044, reset 0x00000000
EPI0
I2S0
I2C1
I2C0
COMP2
COMP1
COMP0
QEI1
QEI0
TIMER3
SSI1
SSI0
GPIOF
GPIOE
SRCR2, type R/W, offset 0x048, reset 0x00000000
USB0
UDMA
GPIOJ
GPIOH
GPIOG
GPIOD
Internal Memory
Flash Memory Registers (Flash Control Offset)
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
OFFSET
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
COMT
MERASE
ERASE
WRITE
PRIS
ARIS
PMASK
AMASK
PMISC
AMISC
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
FCIM, type R/W, offset 0x010, reset 0x0000.0000
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
FMC2, type R/W, offset 0x020, reset 0x0000.0000
WRKEY
WRBUF
FWBVAL, type R/W, offset 0x030, reset 0x0000.0000
FWB[n]
FWB[n]
FWBn, type R/W, offset 0x100 - 0x17C, reset 0x0000.0000
DATA
DATA
FCTL, type R/W, offset 0x0F8, reset 0x0000.0000
USDACK USDREQ
1218
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Internal Memory
Memory Registers (System Control Offset)
Base 0x400F.E000
RMCTL, type R/W1C, offset 0x0F0, reset -
BA
RMVER, type RO, offset 0x0F4, reset 0x0202.5400
CONT
SIZE
VER
REV
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
BOOTCFG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW
PORT
PIN
POL
EN
DBG1
DBG0
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW
DATA
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW
DATA
DATA
USER_REG2, type R/W, offset 0x1E8, reset 0xFFFF.FFFF
NW
DATA
DATA
USER_REG3, type R/W, offset 0x1EC, reset 0xFFFF.FFFF
NW
DATA
DATA
FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
May 24, 2010
1219
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Micro Direct Memory Access (μDMA)
μDMA Channel Control Structure (Offset from Channel Control Table Base)
Base n/a
DMASRCENDP, type R/W, offset 0x000, reset ADDR
ADDR
DMADSTENDP, type R/W, offset 0x004, reset ADDR
ADDR
DMACHCTL, type R/W, offset 0x008, reset DSTINC
DSTSIZE
SRCINC
ARBSIZE
SRCSIZE
ARBSIZE
XFERSIZE
NXTUSEBURST
XFERMODE
Micro Direct Memory Access (μDMA)
μDMA Registers (Offset from μDMA Base Address)
Base 0x400F.F000
DMASTAT, type RO, offset 0x000, reset 0x001F.0000
DMACHANS
STATE
MASTEN
DMACFG, type WO, offset 0x004, reset -
MASTEN
DMACTLBASE, type R/W, offset 0x008, reset 0x0000.0000
ADDR
ADDR
DMAALTBASE, type RO, offset 0x00C, reset 0x0000.0200
ADDR
ADDR
DMAWAITSTAT, type RO, offset 0x010, reset 0x0000.0000
WAITREQ[n]
WAITREQ[n]
DMASWREQ, type WO, offset 0x014, reset SWREQ[n]
SWREQ[n]
DMAUSEBURSTSET, type R/W, offset 0x018, reset 0x0000.0000
SET[n]
SET[n]
DMAUSEBURSTCLR, type WO, offset 0x01C, reset CLR[n]
CLR[n]
DMAREQMASKSET, type R/W, offset 0x020, reset 0x0000.0000
SET[n]
SET[n]
DMAREQMASKCLR, type WO, offset 0x024, reset CLR[n]
CLR[n]
DMAENASET, type R/W, offset 0x028, reset 0x0000.0000
SET[n]
SET[n]
DMAENACLR, type WO, offset 0x02C, reset CLR[n]
CLR[n]
1220
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMAALTSET, type R/W, offset 0x030, reset 0x0000.0000
SET[n]
SET[n]
DMAALTCLR, type WO, offset 0x034, reset CLR[n]
CLR[n]
DMAPRIOSET, type R/W, offset 0x038, reset 0x0000.0000
SET[n]
SET[n]
DMAPRIOCLR, type WO, offset 0x03C, reset CLR[n]
CLR[n]
DMAERRCLR, type R/W, offset 0x04C, reset 0x0000.0000
ERRCLR
DMACHALT, type R/W, offset 0x500, reset 0x0000.0000
CHALT[n]
CHALT[n]
DMAPeriphID0, type RO, offset 0xFE0, reset 0x0000.0030
PID0
DMAPeriphID1, type RO, offset 0xFE4, reset 0x0000.00B2
PID1
DMAPeriphID2, type RO, offset 0xFE8, reset 0x0000.000B
PID2
DMAPeriphID3, type RO, offset 0xFEC, reset 0x0000.0000
PID3
DMAPeriphID4, type RO, offset 0xFD0, reset 0x0000.0004
PID4
DMAPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
DMAPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
DMAPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
DMAPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
May 24, 2010
1221
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
General-Purpose Input/Outputs (GPIOs)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000
DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000
DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000
IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000
IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000
IEV
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000
IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000
RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000
MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000
IC
GPIOAFSEL, type R/W, offset 0x420, reset -
AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF
DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000
DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000
DRV8
1222
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000
ODE
GPIOPUR, type R/W, offset 0x510, reset -
PUE
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000
PDE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000
SRL
GPIODEN, type R/W, offset 0x51C, reset -
DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset -
CR
GPIOAMSEL, type R/W, offset 0x528, reset 0x0000.0000
GPIOAMSEL
GPIOPCTL, type R/W, offset 0x52C, reset PMC7
PMC6
PMC5
PMC4
PMC3
PMC2
PMC1
PMC0
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061
PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
May 24, 2010
1223
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
External Peripheral Interface (EPI)
Base 0x400D.0000
EPICFG, type R/W, offset 0x000, reset 0x0000.0000
BLKEN
MODE
EPIBAUD, type R/W, offset 0x004, reset 0x0000.0000
COUNT1
COUNT0
EPISDRAMCFG, type R/W, offset 0x010, reset 0x42EE.0000
FREQ
RFSH
SLEEP
SIZE
EPIHB8CFG, type R/W, offset 0x010, reset 0x0000.0000
XFFEN
MAXWAIT
XFEEN
WRHIGH RDHIGH
WRWS
RDWS
MODE
EPIHB16CFG, type R/W, offset 0x010, reset 0x0000.0000
XFFEN
MAXWAIT
XFEEN
WRHIGH RDHIGH
WRWS
RDWS
BSEL
MODE
EPIGPCFG, type R/W, offset 0x010, reset 0x0000.0000
CLKPIN
CLKGATE
RDYEN
FRMPIN
FRM50
FRMCNT
RW
MAXWAIT
WR2CYC RD2CYC
ASIZE
DSIZE
EPIHB8CFG2, type R/W, offset 0x014, reset 0x0000.0000
WORD
CSBAUD
CSCFG
EPIHB16CFG2, type R/W, offset 0x014, reset 0x0000.0000
WORD
CSBAUD
CSCFG
EPIGPCFG2, type R/W, offset 0x014, reset 0x0000.0000
WORD
EPIADDRMAP, type R/W, offset 0x01C, reset 0x0000.0000
EPSZ
EPADR
ERSZ
ERADR
EPIRSIZE0, type R/W, offset 0x020, reset 0x0000.0003
SIZE
EPIRSIZE1, type R/W, offset 0x030, reset 0x0000.0003
SIZE
EPIRADDR0, type R/W, offset 0x024, reset 0x0000.0000
ADDR
ADDR
1224
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
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19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WBUSY
NBRBUSY
EPIRADDR1, type R/W, offset 0x034, reset 0x0000.0000
ADDR
ADDR
EPIRPSTD0, type R/W, offset 0x028, reset 0x0000.0000
POSTCNT
EPIRPSTD1, type R/W, offset 0x038, reset 0x0000.0000
POSTCNT
EPISTAT, type RO, offset 0x060, reset 0x0000.0000
CELOW
XFFULL
XFEMPTY INITSEQ
ACTIVE
EPIRFIFOCNT, type RO, offset 0x06C, reset -
COUNT
EPIREADFIFO, type RO, offset 0x070, reset DATA
DATA
EPIREADFIFO1, type RO, offset 0x074, reset DATA
DATA
EPIREADFIFO2, type RO, offset 0x078, reset DATA
DATA
EPIREADFIFO3, type RO, offset 0x07C, reset DATA
DATA
EPIREADFIFO4, type RO, offset 0x080, reset DATA
DATA
EPIREADFIFO5, type RO, offset 0x084, reset DATA
DATA
EPIREADFIFO6, type RO, offset 0x088, reset DATA
DATA
EPIREADFIFO7, type RO, offset 0x08C, reset DATA
DATA
EPIFIFOLVL, type R/W, offset 0x200, reset 0x0000.0033
WFERR
WRFIFO
RSERR
RDFIFO
EPIWFIFOCNT, type RO, offset 0x204, reset 0x0000.0004
WTAV
EPIIM, type R/W, offset 0x210, reset 0x0000.0000
WRIM
RDIM
ERRIM
WRRIS
RDRIS
ERRRIS
EPIRIS, type RO, offset 0x214, reset 0x0000.0004
May 24, 2010
1225
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WRMIS
RDMIS
ERRMIS
WTFULL
RSTALL
TOUT
EPIMIS, type RO, offset 0x218, reset 0x0000.0000
EPIEISC, type R/W1C, offset 0x21C, reset 0x0000.0000
General-Purpose Timers
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000
GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000
TASNAPS
TAWOT
TAMIE
TACDIR
TAAMS
TACMR
TAMR
TBSNAPS
TBWOT
TBMIE
TBCDIR
TBAMS
TBCMR
TBMR
TAPWML
TAOTE
RTCEN
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000
TBPWML
TBOTE
TBEVENT
TBSTALL
TBEN
TAEVENT
TASTALL
TAEN
CBEIM
CBMIM
TBTOIM
TAMIM
RTCIM
CAEIM
CAMIM
TATOIM
CBERIS
CBMRIS TBTORIS
TAMRIS
RTCRIS
CAERIS
CAMRIS
TATORIS
CBEMIS
CBMMIS TBTOMIS
TAMMIS
RTCMIS
CAEMIS
CAMMIS TATOMIS
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000
TBMIM
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000
TBMRIS
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000
TBMMIS
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000
TBMCINT CBECINT CBMCINT TBTOCINT
TAMCINT RTCCINT CAECINT CAMCINT TATOCINT
GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF
TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF
TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000
TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000
TBPSR
1226
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESEN
INTEN
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000
TAPSMR
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000
TBPSMR
GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF
TARH
TARL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (Input Edge-Count Mode)
TBRL
TBRL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (All Modes Except Input Edge-Count Mode)
TBRL
GPTMTAV, type RW, offset 0x050, reset 0xFFFF.FFFF
TAVH
TAVL
GPTMTBV, type RW, offset 0x054, reset 0x0000.FFFF
TBVL
Watchdog Timers
WDT0 base: 0x4000.0000
WDT1 base: 0x4000.1000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF
WDTLOAD
WDTLOAD
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF
WDTVALUE
WDTVALUE
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 (WDT0) and 0x8000.0000 (WDT1)
WRC
WDTICR, type WO, offset 0x00C, reset WDTINTCLR
WDTINTCLR
WDTRIS, type RO, offset 0x010, reset 0x0000.0000
WDTRIS
WDTMIS, type RO, offset 0x014, reset 0x0000.0000
WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000
WDTLOCK
WDTLOCK
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
May 24, 2010
1227
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ASEN3
ASEN2
ASEN1
ASEN0
INR3
INR2
INR1
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005
PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018
PID1
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0006
CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Analog-to-Digital Converter (ADC)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000
ADCRIS, type RO, offset 0x004, reset 0x0000.0000
INRDC
INR0
ADCIM, type R/W, offset 0x008, reset 0x0000.0000
DCONSS3 DCONSS2 DCONSS1 DCONSS0
MASK3
MASK2
MASK1
MASK0
ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000
DCINSS3 DCINSS2 DCINSS1 DCINSS0
IN3
IN2
IN1
IN0
OV3
OV2
OV1
OV0
ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000
1228
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UV1
UV0
ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000
EM3
EM2
EM1
EM0
ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000
UV3
UV2
ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210
SS3
SS2
SS1
SS0
ADCSPC, type R/W, offset 0x024, reset 0x0000.0000
PHASE
ADCPSSI, type R/W, offset 0x028, reset GSYNC
SYNCWAIT
SS3
SS2
SS1
SS0
ADCSAC, type R/W, offset 0x030, reset 0x0000.0000
AVG
ADCDCISC, type R/W1C, offset 0x034, reset 0x0000.0000
DCINT7
DCINT6
DCINT5
DCINT4
DCINT3
DCINT2
DCINT1
DCINT0
ADCCTL, type R/W, offset 0x038, reset 0x0000.0000
VREF
ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000
MUX7
MUX6
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000
TS7
IE7
END7
D7
TS6
IE6
END6
D6
TS5
IE5
END5
D5
TS4
IE4
END4
D4
TS3
IE3
END3
D3
TS2
IE2
END2
D2
TS1
IE1
END1
D1
TS0
IE0
END0
D0
ADCSSFIFO0, type RO, offset 0x048, reset -
DATA
ADCSSFIFO1, type RO, offset 0x068, reset -
DATA
ADCSSFIFO2, type RO, offset 0x088, reset -
DATA
ADCSSFIFO3, type RO, offset 0x0A8, reset -
DATA
ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100
FULL
EMPTY
HPTR
TPTR
EMPTY
HPTR
TPTR
EMPTY
HPTR
TPTR
ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100
FULL
ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100
FULL
May 24, 2010
1229
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100
FULL
EMPTY
HPTR
TPTR
ADCSSOP0, type R/W, offset 0x050, reset 0x0000.0000
S7DCOP
S6DCOP
S5DCOP
S4DCOP
S3DCOP
S2DCOP
S1DCOP
S0DCOP
ADCSSDC0, type R/W, offset 0x054, reset 0x0000.0000
S7DCSEL
S6DCSEL
S5DCSEL
S4DCSEL
S3DCSEL
S2DCSEL
S1DCSEL
S0DCSEL
MUX2
MUX1
MUX0
MUX2
MUX1
MUX0
ADCSSMUX1, type R/W, offset 0x060, reset 0x0000.0000
MUX3
ADCSSMUX2, type R/W, offset 0x080, reset 0x0000.0000
MUX3
ADCSSCTL1, type R/W, offset 0x064, reset 0x0000.0000
TS3
IE3
END3
D3
TS2
IE2
END2
D2
TS1
IE1
END1
D1
TS0
IE0
END0
D0
IE2
END2
D2
TS1
IE1
END1
D1
TS0
IE0
END0
D0
ADCSSCTL2, type R/W, offset 0x084, reset 0x0000.0000
TS3
IE3
END3
D3
TS2
ADCSSOP1, type R/W, offset 0x070, reset 0x0000.0000
S3DCOP
S2DCOP
S1DCOP
S0DCOP
S2DCOP
S1DCOP
S0DCOP
ADCSSOP2, type R/W, offset 0x090, reset 0x0000.0000
S3DCOP
ADCSSDC1, type R/W, offset 0x074, reset 0x0000.0000
S3DCSEL
S2DCSEL
S1DCSEL
S0DCSEL
S2DCSEL
S1DCSEL
S0DCSEL
ADCSSDC2, type R/W, offset 0x094, reset 0x0000.0000
S3DCSEL
ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000
MUX0
ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002
TS0
IE0
END0
D0
ADCSSOP3, type R/W, offset 0x0B0, reset 0x0000.0000
S0DCOP
ADCSSDC3, type R/W, offset 0x0B4, reset 0x0000.0000
S0DCSEL
ADCDCRIC, type R/W, offset 0xD00, reset 0x0000.0000
DCTRIG7 DCTRIG6 DCTRIG5 DCTRIG4 DCTRIG3 DCTRIG2 DCTRIG1 DCTRIG0
DCINT7
DCINT6
DCINT5
DCINT4
DCINT3
DCINT2
DCINT1
DCINT0
ADCDCCTL0, type R/W, offset 0xE00, reset 0x0000.0000
CTE
CTC
CTM
1230
CIE
CIC
CIM
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADCDCCTL1, type R/W, offset 0xE04, reset 0x0000.0000
CTE
CTC
CTM
CIE
CIC
CIM
CTM
CIE
CIC
CIM
CTM
CIE
CIC
CIM
CTM
CIE
CIC
CIM
CTM
CIE
CIC
CIM
CTM
CIE
CIC
CIM
CTM
CIE
CIC
CIM
ADCDCCTL2, type R/W, offset 0xE08, reset 0x0000.0000
CTE
CTC
ADCDCCTL3, type R/W, offset 0xE0C, reset 0x0000.0000
CTE
CTC
ADCDCCTL4, type R/W, offset 0xE10, reset 0x0000.0000
CTE
CTC
ADCDCCTL5, type R/W, offset 0xE14, reset 0x0000.0000
CTE
CTC
ADCDCCTL6, type R/W, offset 0xE18, reset 0x0000.0000
CTE
CTC
ADCDCCTL7, type R/W, offset 0xE1C, reset 0x0000.0000
CTE
CTC
ADCDCCMP0, type R/W, offset 0xE40, reset 0x0000.0000
COMP1
COMP0
ADCDCCMP1, type R/W, offset 0xE44, reset 0x0000.0000
COMP1
COMP0
ADCDCCMP2, type R/W, offset 0xE48, reset 0x0000.0000
COMP1
COMP0
ADCDCCMP3, type R/W, offset 0xE4C, reset 0x0000.0000
COMP1
COMP0
ADCDCCMP4, type R/W, offset 0xE50, reset 0x0000.0000
COMP1
COMP0
ADCDCCMP5, type R/W, offset 0xE54, reset 0x0000.0000
COMP1
COMP0
ADCDCCMP6, type R/W, offset 0xE58, reset 0x0000.0000
COMP1
COMP0
ADCDCCMP7, type R/W, offset 0xE5C, reset 0x0000.0000
COMP1
COMP0
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000
OE
BE
PE
FE
May 24, 2010
DATA
1231
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OE
BE
PE
FE
BUSY
DCD
DSR
CTS
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Read-Only Status Register)
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Write-Only Error Clear Register)
DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090
RI
TXFE
RXFF
TXFF
RXFE
UARTILPR, type R/W, offset 0x020, reset 0x0000.0000
ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000
DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000
DIVFRAC
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000
SPS
WLEN
FEN
STP2
EPS
PEN
BRK
EOT
SMART
SIRLP
SIREN
UARTEN
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300
CTSEN
RTSEN
RTS
DTR
RXE
TXE
LBE
LIN
HSE
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012
RXIFLSEL
TXIFLSEL
UARTIM, type R/W, offset 0x038, reset 0x0000.0000
LME5IM
LME1IM
LMSBIM
OEIM
BEIM
PEIM
FEIM
RTIM
TXIM
RXIM
DSRIM
DCDIM
CTSIM
RIIM
OERIS
BERIS
PERIS
FERIS
RTRIS
TXRIS
RXRIS
DSRRIS
DCDRIS
CTSRIS
RIRIS
OEMIS
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
DSRMIS
DCDMIS
CTSMIS
RIMIS
OEIC
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
DSRMIC
DCDMIC
CTSMIC
RIMIC
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F
LME5RIS LME1RIS LMSBRIS
UARTMIS, type RO, offset 0x040, reset 0x0000.0000
LME5MIS LME1MIS LMSBMIS
UARTICR, type W1C, offset 0x044, reset 0x0000.0000
LME5MIC LME1MIC LMSBMIC
UARTDMACTL, type R/W, offset 0x048, reset 0x0000.0000
DMAERR TXDMAE RXDMAE
UARTLCTL, type R/W, offset 0x090, reset 0x0000.0000
BLEN
MASTER
UARTLSS, type RO, offset 0x094, reset 0x0000.0000
TSS
UARTLTIM, type RO, offset 0x098, reset 0x0000.0000
TIMER
1232
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0060
PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000
SCR
SPH
SPO
FRF
DSS
SSICR1, type R/W, offset 0x004, reset 0x0000.0000
EOT
SOD
MS
SSE
LBM
BSY
RFF
RNE
TNF
TFE
SSIDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
SSISR, type RO, offset 0x00C, reset 0x0000.0003
May 24, 2010
1233
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXIM
RXIM
RTIM
RORIM
TXRIS
RXRIS
RTRIS
RORRIS
TXMIS
RXMIS
RTMIS
RORMIS
RTIC
RORIC
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000
CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000
SSIRIS, type RO, offset 0x018, reset 0x0000.0008
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000
SSIICR, type W1C, offset 0x020, reset 0x0000.0000
SSIDMACTL, type R/W, offset 0x024, reset 0x0000.0000
TXDMAE RXDMAE
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022
PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
1234
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Inter-Integrated Circuit (I2C) Interface
I2C Master
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
SA
R/S
I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Read-Only Status Register)
BUSBSY
IDLE
ARBLST
DATACK
ADRACK
ERROR
BUSY
ACK
STOP
START
RUN
I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Write-Only Control Register)
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
TPR
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
SFE
Inter-Integrated Circuit
(I2C)
MFE
LPBK
Interface
I2C Slave
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
I2CSOAR, type R/W, offset 0x000, reset 0x0000.0000
OAR
I2CSCSR, type RO, offset 0x004, reset 0x0000.0000 (Read-Only Status Register)
FBR
TREQ
RREQ
I2CSCSR, type WO, offset 0x004, reset 0x0000.0000 (Write-Only Control Register)
DA
I2CSDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
May 24, 2010
1235
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOPIM
STARTIM
DATAIM
I2CSIMR, type R/W, offset 0x00C, reset 0x0000.0000
I2CSRIS, type RO, offset 0x010, reset 0x0000.0000
STOPRIS STARTRIS DATARIS
I2CSMIS, type RO, offset 0x014, reset 0x0000.0000
STOPMIS STARTMIS DATAMIS
I2CSICR, type WO, offset 0x018, reset 0x0000.0000
STOPIC
STARTIC
DATAIC
CSS
LRS
Inter-Integrated Circuit Sound (I2S) Interface
Base 0x4005.4000
I2STXFIFO, type WO, offset 0x000, reset 0x0000.0000
TXFIFO
TXFIFO
I2STXFIFOCFG, type R/W, offset 0x004, reset 0x0000.0000
I2STXCFG, type R/W, offset 0x008, reset 0x1400.7DF0
JST
DLY
SCP
LRP
WM
FMT
SSZ
MSL
SDSZ
I2STXLIMIT, type R/W, offset 0x00C, reset 0x0000.0000
LIMIT
I2STXISM, type R/W, offset 0x010, reset 0x0000.0000
FFI
FFM
I2STXLEV, type RO, offset 0x018, reset 0x0000.0000
LEVEL
I2SRXFIFO, type RO, offset 0x800, reset 0x0000.0000
RXFIFO
RXFIFO
I2SRXFIFOCFG, type R/W, offset 0x804, reset 0x0000.0000
FMM
CSS
LRS
I2SRXCFG, type R/W, offset 0x808, reset 0x1400.7DF0
JST
DLY
SCP
LRP
SSZ
RM
MSL
SDSZ
I2SRXLIMIT, type R/W, offset 0x80C, reset 0x0000.7FFF
LIMIT
I2SRXISM, type R/W, offset 0x810, reset 0x0000.0000
FFI
FFM
I2SRXLEV, type RO, offset 0x818, reset 0x0000.0000
LEVEL
1236
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RXSLV
TXSLV
RXEN
TXEN
RXREIM
RXSRIM
TXWEIM
TXSRIM
I2SCFG, type R/W, offset 0xC00, reset 0x0000.0000
I2SIM, type R/W, offset 0xC10, reset 0x0000.0000
I2SRIS, type RO, offset 0xC14, reset 0x0000.0000
RXRERIS RXSRRIS
TXWERIS TXSRRIS
RXREMIS RXSRMIS
TXWEMIS TXSRMIS
I2SMIS, type RO, offset 0xC18, reset 0x0000.0000
I2SIC, type WO, offset 0xC1C, reset 0x0000.0000
RXREIC
TXWEIC
Controller Area Network (CAN) Module
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CANCTL, type R/W, offset 0x000, reset 0x0000.0001
TEST
CCE
DAR
BOFF
EWARN
EPASS
EIE
SIE
IE
INIT
CANSTS, type R/W, offset 0x004, reset 0x0000.0000
RXOK
TXOK
LEC
CANERR, type RO, offset 0x008, reset 0x0000.0000
RP
REC
TEC
CANBIT, type R/W, offset 0x00C, reset 0x0000.2301
TSEG2
TSEG1
SJW
BRP
CANINT, type RO, offset 0x010, reset 0x0000.0000
INTID
CANTST, type R/W, offset 0x014, reset 0x0000.0000
RX
TX
LBACK
SILENT
BASIC
CANBRPE, type R/W, offset 0x018, reset 0x0000.0000
BRPE
CANIF1CRQ, type R/W, offset 0x020, reset 0x0000.0001
BUSY
MNUM
CANIF2CRQ, type R/W, offset 0x080, reset 0x0000.0001
BUSY
MNUM
CANIF1CMSK, type R/W, offset 0x024, reset 0x0000.0000
WRNRD
MASK
ARB
CONTROL CLRINTPND
WRNRD
MASK
ARB
CONTROL CLRINTPND
NEWDAT /
TXRQST
DATAA
DATAB
DATAA
DATAB
CANIF2CMSK, type R/W, offset 0x084, reset 0x0000.0000
May 24, 2010
NEWDAT /
TXRQST
1237
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CANIF1MSK1, type R/W, offset 0x028, reset 0x0000.FFFF
MSK
CANIF2MSK1, type R/W, offset 0x088, reset 0x0000.FFFF
MSK
CANIF1MSK2, type R/W, offset 0x02C, reset 0x0000.FFFF
MXTD
MDIR
MSK
CANIF2MSK2, type R/W, offset 0x08C, reset 0x0000.FFFF
MXTD
MDIR
MSK
CANIF1ARB1, type R/W, offset 0x030, reset 0x0000.0000
ID
CANIF2ARB1, type R/W, offset 0x090, reset 0x0000.0000
ID
CANIF1ARB2, type R/W, offset 0x034, reset 0x0000.0000
MSGVAL
XTD
DIR
ID
CANIF2ARB2, type R/W, offset 0x094, reset 0x0000.0000
MSGVAL
XTD
DIR
ID
CANIF1MCTL, type R/W, offset 0x038, reset 0x0000.0000
NEWDAT MSGLST
INTPND
UMASK
TXIE
RXIE
RMTEN
TXRQST
EOB
DLC
RMTEN
TXRQST
EOB
DLC
CANIF2MCTL, type R/W, offset 0x098, reset 0x0000.0000
NEWDAT MSGLST
INTPND
UMASK
TXIE
RXIE
CANIF1DA1, type R/W, offset 0x03C, reset 0x0000.0000
DATA
CANIF1DA2, type R/W, offset 0x040, reset 0x0000.0000
DATA
CANIF1DB1, type R/W, offset 0x044, reset 0x0000.0000
DATA
CANIF1DB2, type R/W, offset 0x048, reset 0x0000.0000
DATA
CANIF2DA1, type R/W, offset 0x09C, reset 0x0000.0000
DATA
CANIF2DA2, type R/W, offset 0x0A0, reset 0x0000.0000
DATA
CANIF2DB1, type R/W, offset 0x0A4, reset 0x0000.0000
DATA
1238
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CANIF2DB2, type R/W, offset 0x0A8, reset 0x0000.0000
DATA
CANTXRQ1, type RO, offset 0x100, reset 0x0000.0000
TXRQST
CANTXRQ2, type RO, offset 0x104, reset 0x0000.0000
TXRQST
CANNWDA1, type RO, offset 0x120, reset 0x0000.0000
NEWDAT
CANNWDA2, type RO, offset 0x124, reset 0x0000.0000
NEWDAT
CANMSG1INT, type RO, offset 0x140, reset 0x0000.0000
INTPND
CANMSG2INT, type RO, offset 0x144, reset 0x0000.0000
INTPND
CANMSG1VAL, type RO, offset 0x160, reset 0x0000.0000
MSGVAL
CANMSG2VAL, type RO, offset 0x164, reset 0x0000.0000
MSGVAL
Universal Serial Bus (USB) Controller
Base 0x4005.0000
USBFADDR, type R/W, offset 0x000, reset 0x00
FUNCADDR
USBPOWER, type R/W, offset 0x001, reset 0x20 (OTG A / Host Mode)
RESET
RESUME SUSPEND PWRDNPHY
RESET
RESUME SUSPEND PWRDNPHY
USBPOWER, type R/W, offset 0x001, reset 0x20 (OTG B / Device Mode)
ISOUP
SOFTCONN
USBTXIS, type RO, offset 0x002, reset 0x0000
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP10
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
DISCON
CONN
SOF
BABBLE RESUME
SOF
RESET
SOF
BABBLE RESUME
SOF
RESET
EP0
USBRXIS, type RO, offset 0x004, reset 0x0000
EP15
EP14
EP13
EP12
EP11
USBTXIE, type R/W, offset 0x006, reset 0xFFFF
EP15
EP14
EP13
EP12
EP11
EP0
USBRXIE, type R/W, offset 0x008, reset 0xFFFE
EP15
EP14
EP13
EP12
EP11
USBIS, type RO, offset 0x00A, reset 0x00 (OTG A / Host Mode)
VBUSERR SESREQ
USBIS, type RO, offset 0x00A, reset 0x00 (OTG B / Device Mode)
DISCON
RESUME SUSPEND
USBIE, type R/W, offset 0x00B, reset 0x06 (OTG A / Host Mode)
VBUSERR SESREQ
DISCON
CONN
USBIE, type R/W, offset 0x00B, reset 0x06 (OTG B / Device Mode)
DISCON
May 24, 2010
RESUME SUSPEND
1239
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
USBFRAME, type RO, offset 0x00C, reset 0x0000
FRAME
USBEPIDX, type R/W, offset 0x00E, reset 0x00
EPIDX
USBTEST, type R/W, offset 0x00F, reset 0x00 (OTG A / Host Mode)
FORCEH FIFOACC FORCEFS
USBTEST, type R/W, offset 0x00F, reset 0x00 (OTG B / Device Mode)
FIFOACC FORCEFS
USBFIFO0, type R/W, offset 0x020, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO1, type R/W, offset 0x024, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO2, type R/W, offset 0x028, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO3, type R/W, offset 0x02C, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO4, type R/W, offset 0x030, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO5, type R/W, offset 0x034, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO6, type R/W, offset 0x038, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO7, type R/W, offset 0x03C, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO8, type R/W, offset 0x040, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO9, type R/W, offset 0x044, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO10, type R/W, offset 0x048, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO11, type R/W, offset 0x04C, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO12, type R/W, offset 0x050, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO13, type R/W, offset 0x054, reset 0x0000.0000
EPDATA
EPDATA
1240
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEV
FSDEV
LSDEV
USBFIFO14, type R/W, offset 0x058, reset 0x0000.0000
EPDATA
EPDATA
USBFIFO15, type R/W, offset 0x05C, reset 0x0000.0000
EPDATA
EPDATA
USBDEVCTL, type R/W, offset 0x060, reset 0x80
VBUS
HOST
HOSTREQ SESSION
USBTXFIFOSZ, type R/W, offset 0x062, reset 0x00
DPB
SIZE
DPB
SIZE
USBRXFIFOSZ, type R/W, offset 0x063, reset 0x00
USBTXFIFOADD, type R/W, offset 0x064, reset 0x0000
ADDR
USBRXFIFOADD, type R/W, offset 0x066, reset 0x0000
ADDR
USBCONTIM, type R/W, offset 0x07A, reset 0x5C
WTCON
WTID
USBVPLEN, type R/W, offset 0x07B, reset 0x3C
VPLEN
USBFSEOF, type R/W, offset 0x07D, reset 0x77
FSEOFG
USBLSEOF, type R/W, offset 0x07E, reset 0x72
LSEOFG
USBTXFUNCADDR0, type R/W, offset 0x080, reset 0x00
ADDR
USBTXFUNCADDR1, type R/W, offset 0x088, reset 0x00
ADDR
USBTXFUNCADDR2, type R/W, offset 0x090, reset 0x00
ADDR
USBTXFUNCADDR3, type R/W, offset 0x098, reset 0x00
ADDR
USBTXFUNCADDR4, type R/W, offset 0x0A0, reset 0x00
ADDR
USBTXFUNCADDR5, type R/W, offset 0x0A8, reset 0x00
ADDR
USBTXFUNCADDR6, type R/W, offset 0x0B0, reset 0x00
ADDR
USBTXFUNCADDR7, type R/W, offset 0x0B8, reset 0x00
ADDR
USBTXFUNCADDR8, type R/W, offset 0x0C0, reset 0x00
ADDR
USBTXFUNCADDR9, type R/W, offset 0x0C8, reset 0x00
ADDR
USBTXFUNCADDR10, type R/W, offset 0x0D0, reset 0x00
ADDR
USBTXFUNCADDR11, type R/W, offset 0x0D8, reset 0x00
ADDR
USBTXFUNCADDR12, type R/W, offset 0x0E0, reset 0x00
ADDR
USBTXFUNCADDR13, type R/W, offset 0x0E8, reset 0x00
ADDR
May 24, 2010
1241
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
USBTXFUNCADDR14, type R/W, offset 0x0F0, reset 0x00
ADDR
USBTXFUNCADDR15, type R/W, offset 0x0F8, reset 0x00
ADDR
USBTXHUBADDR0, type R/W, offset 0x082, reset 0x00
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
USBTXHUBADDR1, type R/W, offset 0x08A, reset 0x00
USBTXHUBADDR2, type R/W, offset 0x092, reset 0x00
USBTXHUBADDR3, type R/W, offset 0x09A, reset 0x00
USBTXHUBADDR4, type R/W, offset 0x0A2, reset 0x00
USBTXHUBADDR5, type R/W, offset 0x0AA, reset 0x00
USBTXHUBADDR6, type R/W, offset 0x0B2, reset 0x00
USBTXHUBADDR7, type R/W, offset 0x0BA, reset 0x00
USBTXHUBADDR8, type R/W, offset 0x0C2, reset 0x00
USBTXHUBADDR9, type R/W, offset 0x0CA, reset 0x00
USBTXHUBADDR10, type R/W, offset 0x0D2, reset 0x00
USBTXHUBADDR11, type R/W, offset 0x0DA, reset 0x00
USBTXHUBADDR12, type R/W, offset 0x0E2, reset 0x00
USBTXHUBADDR13, type R/W, offset 0x0EA, reset 0x00
USBTXHUBADDR14, type R/W, offset 0x0F2, reset 0x00
USBTXHUBADDR15, type R/W, offset 0x0FA, reset 0x00
USBTXHUBPORT0, type R/W, offset 0x083, reset 0x00
PORT
USBTXHUBPORT1, type R/W, offset 0x08B, reset 0x00
PORT
USBTXHUBPORT2, type R/W, offset 0x093, reset 0x00
PORT
USBTXHUBPORT3, type R/W, offset 0x09B, reset 0x00
PORT
USBTXHUBPORT4, type R/W, offset 0x0A3, reset 0x00
PORT
USBTXHUBPORT5, type R/W, offset 0x0AB, reset 0x00
PORT
USBTXHUBPORT6, type R/W, offset 0x0B3, reset 0x00
PORT
USBTXHUBPORT7, type R/W, offset 0x0BB, reset 0x00
PORT
1242
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
USBTXHUBPORT8, type R/W, offset 0x0C3, reset 0x00
PORT
USBTXHUBPORT9, type R/W, offset 0x0CB, reset 0x00
PORT
USBTXHUBPORT10, type R/W, offset 0x0D3, reset 0x00
PORT
USBTXHUBPORT11, type R/W, offset 0x0DB, reset 0x00
PORT
USBTXHUBPORT12, type R/W, offset 0x0E3, reset 0x00
PORT
USBTXHUBPORT13, type R/W, offset 0x0EB, reset 0x00
PORT
USBTXHUBPORT14, type R/W, offset 0x0F3, reset 0x00
PORT
USBTXHUBPORT15, type R/W, offset 0x0FB, reset 0x00
PORT
USBRXFUNCADDR1, type R/W, offset 0x08C, reset 0x00
ADDR
USBRXFUNCADDR2, type R/W, offset 0x094, reset 0x00
ADDR
USBRXFUNCADDR3, type R/W, offset 0x09C, reset 0x00
ADDR
USBRXFUNCADDR4, type R/W, offset 0x0A4, reset 0x00
ADDR
USBRXFUNCADDR5, type R/W, offset 0x0AC, reset 0x00
ADDR
USBRXFUNCADDR6, type R/W, offset 0x0B4, reset 0x00
ADDR
USBRXFUNCADDR7, type R/W, offset 0x0BC, reset 0x00
ADDR
USBRXFUNCADDR8, type R/W, offset 0x0C4, reset 0x00
ADDR
USBRXFUNCADDR9, type R/W, offset 0x0CC, reset 0x00
ADDR
USBRXFUNCADDR10, type R/W, offset 0x0D4, reset 0x00
ADDR
USBRXFUNCADDR11, type R/W, offset 0x0DC, reset 0x00
ADDR
USBRXFUNCADDR12, type R/W, offset 0x0E4, reset 0x00
ADDR
USBRXFUNCADDR13, type R/W, offset 0x0EC, reset 0x00
ADDR
USBRXFUNCADDR14, type R/W, offset 0x0F4, reset 0x00
ADDR
USBRXFUNCADDR15, type R/W, offset 0x0FC, reset 0x00
ADDR
USBRXHUBADDR1, type R/W, offset 0x08E, reset 0x00
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
USBRXHUBADDR2, type R/W, offset 0x096, reset 0x00
USBRXHUBADDR3, type R/W, offset 0x09E, reset 0x00
May 24, 2010
1243
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
USBRXHUBADDR4, type R/W, offset 0x0A6, reset 0x00
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
MULTTRAN
ADDR
USBRXHUBADDR5, type R/W, offset 0x0AE, reset 0x00
USBRXHUBADDR6, type R/W, offset 0x0B6, reset 0x00
USBRXHUBADDR7, type R/W, offset 0x0BE, reset 0x00
USBRXHUBADDR8, type R/W, offset 0x0C6, reset 0x00
USBRXHUBADDR9, type R/W, offset 0x0CE, reset 0x00
USBRXHUBADDR10, type R/W, offset 0x0D6, reset 0x00
USBRXHUBADDR11, type R/W, offset 0x0DE, reset 0x00
USBRXHUBADDR12, type R/W, offset 0x0E6, reset 0x00
USBRXHUBADDR13, type R/W, offset 0x0EE, reset 0x00
USBRXHUBADDR14, type R/W, offset 0x0F6, reset 0x00
USBRXHUBADDR15, type R/W, offset 0x0FE, reset 0x00
USBRXHUBPORT1, type R/W, offset 0x08F, reset 0x00
PORT
USBRXHUBPORT2, type R/W, offset 0x097, reset 0x00
PORT
USBRXHUBPORT3, type R/W, offset 0x09F, reset 0x00
PORT
USBRXHUBPORT4, type R/W, offset 0x0A7, reset 0x00
PORT
USBRXHUBPORT5, type R/W, offset 0x0AF, reset 0x00
PORT
USBRXHUBPORT6, type R/W, offset 0x0B7, reset 0x00
PORT
USBRXHUBPORT7, type R/W, offset 0x0BF, reset 0x00
PORT
USBRXHUBPORT8, type R/W, offset 0x0C7, reset 0x00
PORT
USBRXHUBPORT9, type R/W, offset 0x0CF, reset 0x00
PORT
USBRXHUBPORT10, type R/W, offset 0x0D7, reset 0x00
PORT
USBRXHUBPORT11, type R/W, offset 0x0DF, reset 0x00
PORT
USBRXHUBPORT12, type R/W, offset 0x0E7, reset 0x00
PORT
USBRXHUBPORT13, type R/W, offset 0x0EF, reset 0x00
PORT
USBRXHUBPORT14, type R/W, offset 0x0F7, reset 0x00
PORT
1244
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STALLED
TXRDY
RXRDY
SETEND DATAEND STALLED
TXRDY
RXRDY
DT
FLUSH
USBRXHUBPORT15, type R/W, offset 0x0FF, reset 0x00
PORT
USBTXMAXP1, type R/W, offset 0x110, reset 0x0000
MAXLOAD
USBTXMAXP2, type R/W, offset 0x120, reset 0x0000
MAXLOAD
USBTXMAXP3, type R/W, offset 0x130, reset 0x0000
MAXLOAD
USBTXMAXP4, type R/W, offset 0x140, reset 0x0000
MAXLOAD
USBTXMAXP5, type R/W, offset 0x150, reset 0x0000
MAXLOAD
USBTXMAXP6, type R/W, offset 0x160, reset 0x0000
MAXLOAD
USBTXMAXP7, type R/W, offset 0x170, reset 0x0000
MAXLOAD
USBTXMAXP8, type R/W, offset 0x180, reset 0x0000
MAXLOAD
USBTXMAXP9, type R/W, offset 0x190, reset 0x0000
MAXLOAD
USBTXMAXP10, type R/W, offset 0x1A0, reset 0x0000
MAXLOAD
USBTXMAXP11, type R/W, offset 0x1B0, reset 0x0000
MAXLOAD
USBTXMAXP12, type R/W, offset 0x1C0, reset 0x0000
MAXLOAD
USBTXMAXP13, type R/W, offset 0x1D0, reset 0x0000
MAXLOAD
USBTXMAXP14, type R/W, offset 0x1E0, reset 0x0000
MAXLOAD
USBTXMAXP15, type R/W, offset 0x1F0, reset 0x0000
MAXLOAD
USBCSRL0, type W1C, offset 0x102, reset 0x00 (OTG A / Host Mode)
NAKTO
STATUS
REQPKT
ERROR
SETUP
USBCSRL0, type W1C, offset 0x102, reset 0x00 (OTG B / Device Mode)
SETENDC RXRDYC
STALL
USBCSRH0, type W1C, offset 0x103, reset 0x00 (OTG A / Host Mode)
DTWE
USBCSRH0, type W1C, offset 0x103, reset 0x00 (OTG B / Device Mode)
FLUSH
USBCOUNT0, type RO, offset 0x108, reset 0x00
COUNT
USBTYPE0, type R/W, offset 0x10A, reset 0x00
SPEED
USBNAKLMT, type R/W, offset 0x10B, reset 0x00
NAKLMT
USBTXCSRL1, type R/W, offset 0x112, reset 0x00 (OTG A / Host Mode)
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
USBTXCSRL2, type R/W, offset 0x122, reset 0x00 (OTG A / Host Mode)
USBTXCSRL3, type R/W, offset 0x132, reset 0x00 (OTG A / Host Mode)
May 24, 2010
1245
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
NAKTO
CLRDT
STALLED
SETUP
FLUSH
ERROR
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
USBTXCSRL4, type R/W, offset 0x142, reset 0x00 (OTG A / Host Mode)
USBTXCSRL5, type R/W, offset 0x152, reset 0x00 (OTG A / Host Mode)
USBTXCSRL6, type R/W, offset 0x162, reset 0x00 (OTG A / Host Mode)
USBTXCSRL7, type R/W, offset 0x172, reset 0x00 (OTG A / Host Mode)
USBTXCSRL8, type R/W, offset 0x182, reset 0x00 (OTG A / Host Mode)
USBTXCSRL9, type R/W, offset 0x192, reset 0x00 (OTG A / Host Mode)
USBTXCSRL10, type R/W, offset 0x1A2, reset 0x00 (OTG A / Host Mode)
USBTXCSRL11, type R/W, offset 0x1B2, reset 0x00 (OTG A / Host Mode)
USBTXCSRL12, type R/W, offset 0x1C2, reset 0x00 (OTG A / Host Mode)
USBTXCSRL13, type R/W, offset 0x1D2, reset 0x00 (OTG A / Host Mode)
USBTXCSRL14, type R/W, offset 0x1E2, reset 0x00 (OTG A / Host Mode)
USBTXCSRL15, type R/W, offset 0x1F2, reset 0x00 (OTG A / Host Mode)
USBTXCSRL1, type R/W, offset 0x112, reset 0x00 (OTG B / Device Mode)
USBTXCSRL2, type R/W, offset 0x122, reset 0x00 (OTG B / Device Mode)
USBTXCSRL3, type R/W, offset 0x132, reset 0x00 (OTG B / Device Mode)
USBTXCSRL4, type R/W, offset 0x142, reset 0x00 (OTG B / Device Mode)
USBTXCSRL5, type R/W, offset 0x152, reset 0x00 (OTG B / Device Mode)
USBTXCSRL6, type R/W, offset 0x162, reset 0x00 (OTG B / Device Mode)
USBTXCSRL7, type R/W, offset 0x172, reset 0x00 (OTG B / Device Mode)
USBTXCSRL8, type R/W, offset 0x182, reset 0x00 (OTG B / Device Mode)
USBTXCSRL9, type R/W, offset 0x192, reset 0x00 (OTG B / Device Mode)
USBTXCSRL10, type R/W, offset 0x1A2, reset 0x00 (OTG B / Device Mode)
USBTXCSRL11, type R/W, offset 0x1B2, reset 0x00 (OTG B / Device Mode)
USBTXCSRL12, type R/W, offset 0x1C2, reset 0x00 (OTG B / Device Mode)
USBTXCSRL13, type R/W, offset 0x1D2, reset 0x00 (OTG B / Device Mode)
USBTXCSRL14, type R/W, offset 0x1E2, reset 0x00 (OTG B / Device Mode)
1246
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLRDT
STALLED
STALL
FLUSH
UNDRN
FIFONE
TXRDY
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
AUTOSET
MODE
DMAEN
FDT
DMAMOD
DTWE
DT
USBTXCSRL15, type R/W, offset 0x1F2, reset 0x00 (OTG B / Device Mode)
USBTXCSRH1, type R/W, offset 0x113, reset 0x00 (OTG A / Host Mode)
USBTXCSRH2, type R/W, offset 0x123, reset 0x00 (OTG A / Host Mode)
USBTXCSRH3, type R/W, offset 0x133, reset 0x00 (OTG A / Host Mode)
USBTXCSRH4, type R/W, offset 0x143, reset 0x00 (OTG A / Host Mode)
USBTXCSRH5, type R/W, offset 0x153, reset 0x00 (OTG A / Host Mode)
USBTXCSRH6, type R/W, offset 0x163, reset 0x00 (OTG A / Host Mode)
USBTXCSRH7, type R/W, offset 0x173, reset 0x00 (OTG A / Host Mode)
USBTXCSRH8, type R/W, offset 0x183, reset 0x00 (OTG A / Host Mode)
USBTXCSRH9, type R/W, offset 0x193, reset 0x00 (OTG A / Host Mode)
USBTXCSRH10, type R/W, offset 0x1A3, reset 0x00 (OTG A / Host Mode)
USBTXCSRH11, type R/W, offset 0x1B3, reset 0x00 (OTG A / Host Mode)
USBTXCSRH12, type R/W, offset 0x1C3, reset 0x00 (OTG A / Host Mode)
USBTXCSRH13, type R/W, offset 0x1D3, reset 0x00 (OTG A / Host Mode)
USBTXCSRH14, type R/W, offset 0x1E3, reset 0x00 (OTG A / Host Mode)
USBTXCSRH15, type R/W, offset 0x1F3, reset 0x00 (OTG A / Host Mode)
USBTXCSRH1, type R/W, offset 0x113, reset 0x00 (OTG B / Device Mode)
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
USBTXCSRH2, type R/W, offset 0x123, reset 0x00 (OTG B / Device Mode)
USBTXCSRH3, type R/W, offset 0x133, reset 0x00 (OTG B / Device Mode)
USBTXCSRH4, type R/W, offset 0x143, reset 0x00 (OTG B / Device Mode)
USBTXCSRH5, type R/W, offset 0x153, reset 0x00 (OTG B / Device Mode)
USBTXCSRH6, type R/W, offset 0x163, reset 0x00 (OTG B / Device Mode)
USBTXCSRH7, type R/W, offset 0x173, reset 0x00 (OTG B / Device Mode)
USBTXCSRH8, type R/W, offset 0x183, reset 0x00 (OTG B / Device Mode)
USBTXCSRH9, type R/W, offset 0x193, reset 0x00 (OTG B / Device Mode)
USBTXCSRH10, type R/W, offset 0x1A3, reset 0x00 (OTG B / Device Mode)
May 24, 2010
1247
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
AUTOSET
ISO
MODE
DMAEN
FDT
DMAMOD
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
USBTXCSRH11, type R/W, offset 0x1B3, reset 0x00 (OTG B / Device Mode)
USBTXCSRH12, type R/W, offset 0x1C3, reset 0x00 (OTG B / Device Mode)
USBTXCSRH13, type R/W, offset 0x1D3, reset 0x00 (OTG B / Device Mode)
USBTXCSRH14, type R/W, offset 0x1E3, reset 0x00 (OTG B / Device Mode)
USBTXCSRH15, type R/W, offset 0x1F3, reset 0x00 (OTG B / Device Mode)
USBRXMAXP1, type R/W, offset 0x114, reset 0x0000
MAXLOAD
USBRXMAXP2, type R/W, offset 0x124, reset 0x0000
MAXLOAD
USBRXMAXP3, type R/W, offset 0x134, reset 0x0000
MAXLOAD
USBRXMAXP4, type R/W, offset 0x144, reset 0x0000
MAXLOAD
USBRXMAXP5, type R/W, offset 0x154, reset 0x0000
MAXLOAD
USBRXMAXP6, type R/W, offset 0x164, reset 0x0000
MAXLOAD
USBRXMAXP7, type R/W, offset 0x174, reset 0x0000
MAXLOAD
USBRXMAXP8, type R/W, offset 0x184, reset 0x0000
MAXLOAD
USBRXMAXP9, type R/W, offset 0x194, reset 0x0000
MAXLOAD
USBRXMAXP10, type R/W, offset 0x1A4, reset 0x0000
MAXLOAD
USBRXMAXP11, type R/W, offset 0x1B4, reset 0x0000
MAXLOAD
USBRXMAXP12, type R/W, offset 0x1C4, reset 0x0000
MAXLOAD
USBRXMAXP13, type R/W, offset 0x1D4, reset 0x0000
MAXLOAD
USBRXMAXP14, type R/W, offset 0x1E4, reset 0x0000
MAXLOAD
USBRXMAXP15, type R/W, offset 0x1F4, reset 0x0000
MAXLOAD
USBRXCSRL1, type R/W, offset 0x116, reset 0x00 (OTG A / Host Mode)
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
DATAERR /
NAKTO
USBRXCSRL2, type R/W, offset 0x126, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL3, type R/W, offset 0x136, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL4, type R/W, offset 0x146, reset 0x00 (OTG A / Host Mode)
1248
DATAERR /
NAKTO
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
ERROR
FULL
RXRDY
USBRXCSRL5, type R/W, offset 0x156, reset 0x00 (OTG A / Host Mode)
DATAERR /
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED REQPKT
FLUSH
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
NAKTO
USBRXCSRL6, type R/W, offset 0x166, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL7, type R/W, offset 0x176, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL8, type R/W, offset 0x186, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL9, type R/W, offset 0x196, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL10, type R/W, offset 0x1A6, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL11, type R/W, offset 0x1B6, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL12, type R/W, offset 0x1C6, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL13, type R/W, offset 0x1D6, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL14, type R/W, offset 0x1E6, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL15, type R/W, offset 0x1F6, reset 0x00 (OTG A / Host Mode)
DATAERR /
NAKTO
USBRXCSRL1, type R/W, offset 0x116, reset 0x00 (OTG B / Device Mode)
USBRXCSRL2, type R/W, offset 0x126, reset 0x00 (OTG B / Device Mode)
USBRXCSRL3, type R/W, offset 0x136, reset 0x00 (OTG B / Device Mode)
USBRXCSRL4, type R/W, offset 0x146, reset 0x00 (OTG B / Device Mode)
USBRXCSRL5, type R/W, offset 0x156, reset 0x00 (OTG B / Device Mode)
USBRXCSRL6, type R/W, offset 0x166, reset 0x00 (OTG B / Device Mode)
USBRXCSRL7, type R/W, offset 0x176, reset 0x00 (OTG B / Device Mode)
USBRXCSRL8, type R/W, offset 0x186, reset 0x00 (OTG B / Device Mode)
USBRXCSRL9, type R/W, offset 0x196, reset 0x00 (OTG B / Device Mode)
USBRXCSRL10, type R/W, offset 0x1A6, reset 0x00 (OTG B / Device Mode)
USBRXCSRL11, type R/W, offset 0x1B6, reset 0x00 (OTG B / Device Mode)
May 24, 2010
1249
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
CLRDT
STALLED
STALL
FLUSH
DATAERR
OVER
FULL
RXRDY
USBRXCSRL12, type R/W, offset 0x1C6, reset 0x00 (OTG B / Device Mode)
USBRXCSRL13, type R/W, offset 0x1D6, reset 0x00 (OTG B / Device Mode)
USBRXCSRL14, type R/W, offset 0x1E6, reset 0x00 (OTG B / Device Mode)
USBRXCSRL15, type R/W, offset 0x1F6, reset 0x00 (OTG B / Device Mode)
USBRXCSRH1, type R/W, offset 0x117, reset 0x00 (OTG A / Host Mode)
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL AUTORQ
DMAEN
PIDERR DMAMOD
DTWE
DT
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
USBRXCSRH2, type R/W, offset 0x127, reset 0x00 (OTG A / Host Mode)
USBRXCSRH3, type R/W, offset 0x137, reset 0x00 (OTG A / Host Mode)
USBRXCSRH4, type R/W, offset 0x147, reset 0x00 (OTG A / Host Mode)
USBRXCSRH5, type R/W, offset 0x157, reset 0x00 (OTG A / Host Mode)
USBRXCSRH6, type R/W, offset 0x167, reset 0x00 (OTG A / Host Mode)
USBRXCSRH7, type R/W, offset 0x177, reset 0x00 (OTG A / Host Mode)
USBRXCSRH8, type R/W, offset 0x187, reset 0x00 (OTG A / Host Mode)
USBRXCSRH9, type R/W, offset 0x197, reset 0x00 (OTG A / Host Mode)
USBRXCSRH10, type R/W, offset 0x1A7, reset 0x00 (OTG A / Host Mode)
USBRXCSRH11, type R/W, offset 0x1B7, reset 0x00 (OTG A / Host Mode)
USBRXCSRH12, type R/W, offset 0x1C7, reset 0x00 (OTG A / Host Mode)
USBRXCSRH13, type R/W, offset 0x1D7, reset 0x00 (OTG A / Host Mode)
USBRXCSRH14, type R/W, offset 0x1E7, reset 0x00 (OTG A / Host Mode)
USBRXCSRH15, type R/W, offset 0x1F7, reset 0x00 (OTG A / Host Mode)
USBRXCSRH1, type R/W, offset 0x117, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH2, type R/W, offset 0x127, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH3, type R/W, offset 0x137, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH4, type R/W, offset 0x147, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH5, type R/W, offset 0x157, reset 0x00 (OTG B / Device Mode)
1250
DISNYET /
PIDERR
DMAMOD
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
AUTOCL
ISO
DMAEN
USBRXCSRH6, type R/W, offset 0x167, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH7, type R/W, offset 0x177, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH8, type R/W, offset 0x187, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH9, type R/W, offset 0x197, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH10, type R/W, offset 0x1A7, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH11, type R/W, offset 0x1B7, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH12, type R/W, offset 0x1C7, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH13, type R/W, offset 0x1D7, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH14, type R/W, offset 0x1E7, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCSRH15, type R/W, offset 0x1F7, reset 0x00 (OTG B / Device Mode)
DISNYET /
PIDERR
DMAMOD
USBRXCOUNT1, type RO, offset 0x118, reset 0x0000
COUNT
USBRXCOUNT2, type RO, offset 0x128, reset 0x0000
COUNT
USBRXCOUNT3, type RO, offset 0x138, reset 0x0000
COUNT
USBRXCOUNT4, type RO, offset 0x148, reset 0x0000
COUNT
USBRXCOUNT5, type RO, offset 0x158, reset 0x0000
COUNT
USBRXCOUNT6, type RO, offset 0x168, reset 0x0000
COUNT
USBRXCOUNT7, type RO, offset 0x178, reset 0x0000
COUNT
USBRXCOUNT8, type RO, offset 0x188, reset 0x0000
COUNT
USBRXCOUNT9, type RO, offset 0x198, reset 0x0000
COUNT
USBRXCOUNT10, type RO, offset 0x1A8, reset 0x0000
COUNT
USBRXCOUNT11, type RO, offset 0x1B8, reset 0x0000
COUNT
USBRXCOUNT12, type RO, offset 0x1C8, reset 0x0000
COUNT
USBRXCOUNT13, type RO, offset 0x1D8, reset 0x0000
COUNT
May 24, 2010
1251
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
USBRXCOUNT14, type RO, offset 0x1E8, reset 0x0000
COUNT
USBRXCOUNT15, type RO, offset 0x1F8, reset 0x0000
COUNT
USBTXTYPE1, type R/W, offset 0x11A, reset 0x00
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
USBTXTYPE2, type R/W, offset 0x12A, reset 0x00
USBTXTYPE3, type R/W, offset 0x13A, reset 0x00
USBTXTYPE4, type R/W, offset 0x14A, reset 0x00
USBTXTYPE5, type R/W, offset 0x15A, reset 0x00
USBTXTYPE6, type R/W, offset 0x16A, reset 0x00
USBTXTYPE7, type R/W, offset 0x17A, reset 0x00
USBTXTYPE8, type R/W, offset 0x18A, reset 0x00
USBTXTYPE9, type R/W, offset 0x19A, reset 0x00
USBTXTYPE10, type R/W, offset 0x1AA, reset 0x00
USBTXTYPE11, type R/W, offset 0x1BA, reset 0x00
USBTXTYPE12, type R/W, offset 0x1CA, reset 0x00
USBTXTYPE13, type R/W, offset 0x1DA, reset 0x00
USBTXTYPE14, type R/W, offset 0x1EA, reset 0x00
USBTXTYPE15, type R/W, offset 0x1FA, reset 0x00
USBTXINTERVAL1, type R/W, offset 0x11B, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL2, type R/W, offset 0x12B, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL3, type R/W, offset 0x13B, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL4, type R/W, offset 0x14B, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL5, type R/W, offset 0x15B, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL6, type R/W, offset 0x16B, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL7, type R/W, offset 0x17B, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL8, type R/W, offset 0x18B, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL9, type R/W, offset 0x19B, reset 0x00
TXPOLL / NAKLMT
1252
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
USBTXINTERVAL10, type R/W, offset 0x1AB, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL11, type R/W, offset 0x1BB, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL12, type R/W, offset 0x1CB, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL13, type R/W, offset 0x1DB, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL14, type R/W, offset 0x1EB, reset 0x00
TXPOLL / NAKLMT
USBTXINTERVAL15, type R/W, offset 0x1FB, reset 0x00
TXPOLL / NAKLMT
USBRXTYPE1, type R/W, offset 0x11C, reset 0x00
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
SPEED
PROTO
TEP
USBRXTYPE2, type R/W, offset 0x12C, reset 0x00
USBRXTYPE3, type R/W, offset 0x13C, reset 0x00
USBRXTYPE4, type R/W, offset 0x14C, reset 0x00
USBRXTYPE5, type R/W, offset 0x15C, reset 0x00
USBRXTYPE6, type R/W, offset 0x16C, reset 0x00
USBRXTYPE7, type R/W, offset 0x17C, reset 0x00
USBRXTYPE8, type R/W, offset 0x18C, reset 0x00
USBRXTYPE9, type R/W, offset 0x19C, reset 0x00
USBRXTYPE10, type R/W, offset 0x1AC, reset 0x00
USBRXTYPE11, type R/W, offset 0x1BC, reset 0x00
USBRXTYPE12, type R/W, offset 0x1CC, reset 0x00
USBRXTYPE13, type R/W, offset 0x1DC, reset 0x00
USBRXTYPE14, type R/W, offset 0x1EC, reset 0x00
USBRXTYPE15, type R/W, offset 0x1FC, reset 0x00
USBRXINTERVAL1, type R/W, offset 0x11D, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL2, type R/W, offset 0x12D, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL3, type R/W, offset 0x13D, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL4, type R/W, offset 0x14D, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL5, type R/W, offset 0x15D, reset 0x00
TXPOLL / NAKLMT
May 24, 2010
1253
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EP2
EP1
USBRXINTERVAL6, type R/W, offset 0x16D, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL7, type R/W, offset 0x17D, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL8, type R/W, offset 0x18D, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL9, type R/W, offset 0x19D, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL10, type R/W, offset 0x1AD, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL11, type R/W, offset 0x1BD, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL12, type R/W, offset 0x1CD, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL13, type R/W, offset 0x1DD, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL14, type R/W, offset 0x1ED, reset 0x00
TXPOLL / NAKLMT
USBRXINTERVAL15, type R/W, offset 0x1FD, reset 0x00
TXPOLL / NAKLMT
USBRQPKTCOUNT1, type R/W, offset 0x304, reset 0x0000
COUNT
USBRQPKTCOUNT2, type R/W, offset 0x308, reset 0x0000
COUNT
USBRQPKTCOUNT3, type R/W, offset 0x30C, reset 0x0000
COUNT
USBRQPKTCOUNT4, type R/W, offset 0x310, reset 0x0000
COUNT
USBRQPKTCOUNT5, type R/W, offset 0x314, reset 0x0000
COUNT
USBRQPKTCOUNT6, type R/W, offset 0x318, reset 0x0000
COUNT
USBRQPKTCOUNT7, type R/W, offset 0x31C, reset 0x0000
COUNT
USBRQPKTCOUNT8, type R/W, offset 0x320, reset 0x0000
COUNT
USBRQPKTCOUNT9, type R/W, offset 0x324, reset 0x0000
COUNT
USBRQPKTCOUNT10, type R/W, offset 0x328, reset 0x0000
COUNT
USBRQPKTCOUNT11, type R/W, offset 0x32C, reset 0x0000
COUNT
USBRQPKTCOUNT12, type R/W, offset 0x330, reset 0x0000
COUNT
USBRQPKTCOUNT13, type R/W, offset 0x334, reset 0x0000
COUNT
USBRQPKTCOUNT14, type R/W, offset 0x338, reset 0x0000
COUNT
USBRQPKTCOUNT15, type R/W, offset 0x33C, reset 0x0000
COUNT
USBRXDPKTBUFDIS, type R/W, offset 0x340, reset 0x0000
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
EP6
EP5
1254
EP4
EP3
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EP9
EP8
EP7
EP6
EP5
EP4
EP3
EP2
EP1
USBTXDPKTBUFDIS, type R/W, offset 0x342, reset 0x0000
EP15
EP14
EP13
EP12
EP11
EP10
USBEPC, type R/W, offset 0x400, reset 0x0000.0000
PFLTACT
PFLTAEN PFLTSEN PFLTEN
EPENDE
EPEN
USBEPCRIS, type RO, offset 0x404, reset 0x0000.0000
PF
USBEPCIM, type R/W, offset 0x408, reset 0x0000.0000
PF
USBEPCISC, type R/W, offset 0x40C, reset 0x0000.0000
PF
USBDRRIS, type RO, offset 0x410, reset 0x0000.0000
RESUME
USBDRIM, type R/W, offset 0x414, reset 0x0000.0000
RESUME
USBDRISC, type W1C, offset 0x418, reset 0x0000.0000
RESUME
USBGPCS, type R/W, offset 0x41C, reset 0x0000.0000
DEVMODOTG
DEVMOD
USBVDC, type R/W, offset 0x430, reset 0x0000.0000
VBDEN
USBVDCRIS, type RO, offset 0x434, reset 0x0000.0000
VD
USBVDCIM, type R/W, offset 0x438, reset 0x0000.0000
VD
USBVDCISC, type R/W, offset 0x43C, reset 0x0000.0000
VD
USBIDVRIS, type RO, offset 0x444, reset 0x0000.0000
ID
USBIDVIM, type R/W, offset 0x448, reset 0x0000.0000
ID
USBIDVISC, type R/W1C, offset 0x44C, reset 0x0000.0000
ID
USBDMASEL, type R/W, offset 0x450, reset 0x0033.2211
DMABTX
DMABRX
DMACTX
DMACRX
DMAATX
DMAARX
May 24, 2010
1255
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IN2
IN1
IN0
IN2
IN1
IN0
IN2
IN1
IN0
Analog Comparators
Base 0x4003.C000
ACMIS, type R/W1C, offset 0x000, reset 0x0000.0000
ACRIS, type RO, offset 0x004, reset 0x0000.0000
ACINTEN, type R/W, offset 0x008, reset 0x0000.0000
ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000
EN
RNG
VREF
ACSTAT0, type RO, offset 0x020, reset 0x0000.0000
OVAL
ACSTAT1, type RO, offset 0x040, reset 0x0000.0000
OVAL
ACSTAT2, type RO, offset 0x060, reset 0x0000.0000
OVAL
ACCTL0, type R/W, offset 0x024, reset 0x0000.0000
TOEN
ASRCP
TSLVAL
TSEN
ISLVAL
ISEN
CINV
ASRCP
TSLVAL
TSEN
ISLVAL
ISEN
CINV
ASRCP
TSLVAL
TSEN
ISLVAL
ISEN
CINV
ACCTL1, type R/W, offset 0x044, reset 0x0000.0000
TOEN
ACCTL2, type R/W, offset 0x064, reset 0x0000.0000
TOEN
Pulse Width Modulator (PWM)
Base 0x4002.8000
PWMCTL, type R/W, offset 0x000, reset 0x0000.0000
GLOBALSYNC3 GLOBALSYNC2 GLOBALSYNC1 GLOBALSYNC0
PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000
SYNC3
SYNC2
SYNC1
SYNC0
PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000
PWM7EN PWM6EN PWM5EN PWM4EN PWM3EN PWM2EN PWM1EN PWM0EN
PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000
PWM7INV PWM6INV PWM5INV PWM4INV PWM3INV PWM2INV PWM1INV PWM0INV
PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000
FAULT7
FAULT6
FAULT5
FAULT4
FAULT3
FAULT2
FAULT1
FAULT0
PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
1256
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWMRIS, type RO, offset 0x018, reset 0x0000.0000
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000
FAULT3
FAULT2
FAULT1
FAULT0
PWM3
PWM2
PWM1
PWM0
PWMFAULTVAL, type R/W, offset 0x024, reset 0x0000.0000
PWM7
PWM6
PWM5
PWM4
PWMENUPD, type R/W, offset 0x028, reset 0x0000.0000
ENUPD7
ENUPD6
ENUPD5
ENUPD4
ENUPD3
ENUPD2
ENUPD1
ENUPD0
LATCH
MINFLTPER
FLTSRC
GENBUPD
GENAUPD
CMPBUPD CMPAUPD LOADUPD
DEBUG
MODE
ENABLE
LATCH
MINFLTPER
FLTSRC
GENBUPD
GENAUPD
CMPBUPD CMPAUPD LOADUPD
DEBUG
MODE
ENABLE
LATCH
MINFLTPER
FLTSRC
GENBUPD
GENAUPD
CMPBUPD CMPAUPD LOADUPD
DEBUG
MODE
ENABLE
LATCH
MINFLTPER
FLTSRC
GENBUPD
GENAUPD
CMPBUPD CMPAUPD LOADUPD
DEBUG
MODE
ENABLE
PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000
DBFALLUPD
DBRISEUPD
DBCTLUPD
PWM1CTL, type R/W, offset 0x080, reset 0x0000.0000
DBFALLUPD
DBRISEUPD
DBCTLUPD
PWM2CTL, type R/W, offset 0x0C0, reset 0x0000.0000
DBFALLUPD
DBRISEUPD
DBCTLUPD
PWM3CTL, type R/W, offset 0x100, reset 0x0000.0000
DBFALLUPD
DBRISEUPD
DBCTLUPD
PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM1INTEN, type R/W, offset 0x084, reset 0x0000.0000
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM2INTEN, type R/W, offset 0x0C4, reset 0x0000.0000
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM3INTEN, type R/W, offset 0x104, reset 0x0000.0000
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM0RIS, type RO, offset 0x048, reset 0x0000.0000
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM1RIS, type RO, offset 0x088, reset 0x0000.0000
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM2RIS, type RO, offset 0x0C8, reset 0x0000.0000
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM3RIS, type RO, offset 0x108, reset 0x0000.0000
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
May 24, 2010
1257
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM1ISC, type R/W1C, offset 0x08C, reset 0x0000.0000
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM2ISC, type R/W1C, offset 0x0CC, reset 0x0000.0000
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM3ISC, type R/W1C, offset 0x10C, reset 0x0000.0000
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM0LOAD, type R/W, offset 0x050, reset 0x0000.0000
LOAD
PWM1LOAD, type R/W, offset 0x090, reset 0x0000.0000
LOAD
PWM2LOAD, type R/W, offset 0x0D0, reset 0x0000.0000
LOAD
PWM3LOAD, type R/W, offset 0x110, reset 0x0000.0000
LOAD
PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000
COUNT
PWM1COUNT, type RO, offset 0x094, reset 0x0000.0000
COUNT
PWM2COUNT, type RO, offset 0x0D4, reset 0x0000.0000
COUNT
PWM3COUNT, type RO, offset 0x114, reset 0x0000.0000
COUNT
PWM0CMPA, type R/W, offset 0x058, reset 0x0000.0000
COMPA
PWM1CMPA, type R/W, offset 0x098, reset 0x0000.0000
COMPA
PWM2CMPA, type R/W, offset 0x0D8, reset 0x0000.0000
COMPA
PWM3CMPA, type R/W, offset 0x118, reset 0x0000.0000
COMPA
PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000
COMPB
1258
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWM1CMPB, type R/W, offset 0x09C, reset 0x0000.0000
COMPB
PWM2CMPB, type R/W, offset 0x0DC, reset 0x0000.0000
COMPB
PWM3CMPB, type R/W, offset 0x11C, reset 0x0000.0000
COMPB
PWM0GENA, type R/W, offset 0x060, reset 0x0000.0000
ACTCMPBD
ACTCMPBU
ACTCMPAD
ACTCMPAU
ACTLOAD
ACTZERO
ACTCMPBU
ACTCMPAD
ACTCMPAU
ACTLOAD
ACTZERO
ACTCMPBU
ACTCMPAD
ACTCMPAU
ACTLOAD
ACTZERO
ACTCMPBU
ACTCMPAD
ACTCMPAU
ACTLOAD
ACTZERO
ACTCMPBU
ACTCMPAD
ACTCMPAU
ACTLOAD
ACTZERO
ACTCMPBU
ACTCMPAD
ACTCMPAU
ACTLOAD
ACTZERO
ACTCMPBU
ACTCMPAD
ACTCMPAU
ACTLOAD
ACTZERO
ACTCMPBU
ACTCMPAD
ACTCMPAU
ACTLOAD
ACTZERO
PWM1GENA, type R/W, offset 0x0A0, reset 0x0000.0000
ACTCMPBD
PWM2GENA, type R/W, offset 0x0E0, reset 0x0000.0000
ACTCMPBD
PWM3GENA, type R/W, offset 0x120, reset 0x0000.0000
ACTCMPBD
PWM0GENB, type R/W, offset 0x064, reset 0x0000.0000
ACTCMPBD
PWM1GENB, type R/W, offset 0x0A4, reset 0x0000.0000
ACTCMPBD
PWM2GENB, type R/W, offset 0x0E4, reset 0x0000.0000
ACTCMPBD
PWM3GENB, type R/W, offset 0x124, reset 0x0000.0000
ACTCMPBD
PWM0DBCTL, type R/W, offset 0x068, reset 0x0000.0000
ENABLE
PWM1DBCTL, type R/W, offset 0x0A8, reset 0x0000.0000
ENABLE
PWM2DBCTL, type R/W, offset 0x0E8, reset 0x0000.0000
ENABLE
PWM3DBCTL, type R/W, offset 0x128, reset 0x0000.0000
ENABLE
PWM0DBRISE, type R/W, offset 0x06C, reset 0x0000.0000
RISEDELAY
PWM1DBRISE, type R/W, offset 0x0AC, reset 0x0000.0000
RISEDELAY
May 24, 2010
1259
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
PWM2DBRISE, type R/W, offset 0x0EC, reset 0x0000.0000
RISEDELAY
PWM3DBRISE, type R/W, offset 0x12C, reset 0x0000.0000
RISEDELAY
PWM0DBFALL, type R/W, offset 0x070, reset 0x0000.0000
FALLDELAY
PWM1DBFALL, type R/W, offset 0x0B0, reset 0x0000.0000
FALLDELAY
PWM2DBFALL, type R/W, offset 0x0F0, reset 0x0000.0000
FALLDELAY
PWM3DBFALL, type R/W, offset 0x130, reset 0x0000.0000
FALLDELAY
PWM0FLTSRC0, type R/W, offset 0x074, reset 0x0000.0000
PWM1FLTSRC0, type R/W, offset 0x0B4, reset 0x0000.0000
PWM2FLTSRC0, type R/W, offset 0x0F4, reset 0x0000.0000
PWM3FLTSRC0, type R/W, offset 0x134, reset 0x0000.0000
PWM0FLTSRC1, type R/W, offset 0x078, reset 0x0000.0000
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
PWM1FLTSRC1, type R/W, offset 0x0B8, reset 0x0000.0000
PWM2FLTSRC1, type R/W, offset 0x0F8, reset 0x0000.0000
PWM3FLTSRC1, type R/W, offset 0x138, reset 0x0000.0000
PWM0MINFLTPER, type R/W, offset 0x07C, reset 0x0000.0000
MFP
PWM1MINFLTPER, type R/W, offset 0x0BC, reset 0x0000.0000
MFP
PWM2MINFLTPER, type R/W, offset 0x0FC, reset 0x0000.0000
MFP
1260
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
FAULT3
FAULT2
FAULT1
FAULT0
PWM3MINFLTPER, type R/W, offset 0x13C, reset 0x0000.0000
MFP
PWM0FLTSEN, type R/W, offset 0x800, reset 0x0000.0000
PWM1FLTSEN, type R/W, offset 0x880, reset 0x0000.0000
PWM2FLTSEN, type R/W, offset 0x900, reset 0x0000.0000
PWM3FLTSEN, type R/W, offset 0x980, reset 0x0000.0000
PWM0FLTSTAT0, type -, offset 0x804, reset 0x0000.0000
PWM1FLTSTAT0, type -, offset 0x884, reset 0x0000.0000
PWM2FLTSTAT0, type -, offset 0x904, reset 0x0000.0000
PWM3FLTSTAT0, type -, offset 0x984, reset 0x0000.0000
PWM0FLTSTAT1, type -, offset 0x808, reset 0x0000.0000
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
DCMP7
DCMP6
DCMP5
DCMP4
DCMP3
DCMP2
DCMP1
DCMP0
PWM1FLTSTAT1, type -, offset 0x888, reset 0x0000.0000
PWM2FLTSTAT1, type -, offset 0x908, reset 0x0000.0000
PWM3FLTSTAT1, type -, offset 0x988, reset 0x0000.0000
Quadrature Encoder Interface (QEI)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
QEICTL, type R/W, offset 0x000, reset 0x0000.0000
FILTCNT
FILTEN
STALLEN
INVI
INVB
INVA
VELDIV
VELEN
RESMODE CAPMODE SIGMODE
SWAP
ENABLE
DIRECTION
ERROR
QEISTAT, type RO, offset 0x004, reset 0x0000.0000
QEIPOS, type R/W, offset 0x008, reset 0x0000.0000
POSITION
POSITION
May 24, 2010
1261
Texas Instruments-Advance Information
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTERROR
INTDIR
INTTIMER
INTINDEX
INTERROR
INTDIR
INTTIMER
INTINDEX
INTERROR
INTDIR
INTTIMER
INTINDEX
QEIMAXPOS, type R/W, offset 0x00C, reset 0x0000.0000
MAXPOS
MAXPOS
QEILOAD, type R/W, offset 0x010, reset 0x0000.0000
LOAD
LOAD
QEITIME, type RO, offset 0x014, reset 0x0000.0000
TIME
TIME
QEICOUNT, type RO, offset 0x018, reset 0x0000.0000
COUNT
COUNT
QEISPEED, type RO, offset 0x01C, reset 0x0000.0000
SPEED
SPEED
QEIINTEN, type R/W, offset 0x020, reset 0x0000.0000
QEIRIS, type RO, offset 0x024, reset 0x0000.0000
QEIISC, type R/W1C, offset 0x028, reset 0x0000.0000
1262
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
E
Ordering and Contact Information
E.1
Ordering Information
LM3Snnnn–gppss–rrm
Part Number
nnn = Sandstorm-class parts
nnnn = All other Stellaris® parts
Shipping Medium
T = Tape-and-reel
Omitted = Default shipping (tray or tube)
Temperature
E = –40°C to +105°C
I = –40°C to +85°C
Revision
Speed
20 = 20 MHz
25 = 25 MHz
50 = 50 MHz
80 = 80 MHz
Package
BZ = 108-ball BGA
QC = 100-pin LQFP
QN = 48-pin LQFP
QR = 64-pin LQFP
GZ = 48-pin QFN
Table E-1. Part Ordering Information
E.2
Orderable Part Number
Description
LM3S5B91-IQC80-C1
Stellaris LM3S5B91 Microcontroller Industrial Temperature 100-pin LQFP
LM3S5B91-IBZ80-C1
Stellaris LM3S5B91 Microcontroller Industrial Temperature 108-ball BGA
LM3S5B91-IQC80-C1T
Stellaris LM3S5B91 Microcontroller Industrial Temperature 100-pin LQFP
Tape-and-reel
LM3S5B91-IBZ80-C1T
Stellaris LM3S5B91 Microcontroller Industrial Temperature 108-ball BGA
Tape-and-reel
®
®
®
®
Part Markings
®
The Stellaris microcontrollers are marked with an identifying number. This code contains the
following information:
■ The first line indicates the part number. In the example below, this is the LM3S9B90.
■ In the second line, the first seven characters indicate the temperature, package, speed, and
revision. In the example below, this is an Industrial temperature (I), 100-pin LQFP package (QC),
80-MHz (80), revision C0 (C0) device.
■ The third line contain internal tracking numbers.
May 24, 2010
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Texas Instruments-Advance Information
Ordering and Contact Information
E.3
Kits
®
The Stellaris Family provides the hardware and software tools that engineers need to begin
development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files
®
■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers
before purchase
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box
See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor.
E.4
Support Information
®
For support on Stellaris products, contact the TI Worldwide Product Information Center nearest
you: http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm.
1264
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Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
F
Package Information
Figure F-1. 100-Pin LQFP Package
Note:
The following notes apply to the package drawing.
1. All dimensions shown in mm.
2. Dimensions shown are nominal with tolerances indicated.
3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
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Texas Instruments-Advance Information
Package Information
Body +2.00 mm Footprint, 1.4 mm package thickness
Symbols
Leads
100L
A
Max.
1.60
A1
-
0.05 Min./0.15 Max.
A2
±0.05
1.40
D
±0.20
16.00
D1
±0.05
14.00
E
±0.20
16.00
E1
±0.05
14.00
L
+0.15/-0.10
0.60
e
Basic
0.50
b
+0.05
0.22
θ
-
0˚-7˚
ddd
Max.
0.08
ccc
Max.
0.08
JEDEC Reference Drawing
MS-026
Variation Designator
BED
1266
May 24, 2010
Texas Instruments-Advance Information
Stellaris® LM3S5B91 Microcontroller
Figure F-2. 108-Ball BGA Package
May 24, 2010
1267
Texas Instruments-Advance Information
Package Information
Note:
The following notes apply to the package drawing.
Symbols
MIN
NOM
MAX
A
1.22
1.36
1.50
A1
0.29
0.34
0.39
A3
0.65
0.70
0.75
c
0.28
0.32
0.36
D
9.85
10.00
10.15
D1
E
8.80 BSC
9.85
E1
b
10.00
8.80 BSC
0.43
0.48
bbb
0.53
.20
ddd
.12
e
0.80 BSC
f
10.15
-
0.60
M
12
n
108
-
REF: JEDEC MO-219F
1268
May 24, 2010
Texas Instruments-Advance Information
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