LM3S9L71-IQC80-C5

厂商：
BURR-BROWN(德州仪器)
封装：
LQFP100
描述：
IC MCU 32BIT 128KB FLASH 100LQFP

数据手册：

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LM3S9L71-IQC80-C5 数据手册

TE X AS I NS TRUM E NTS - P RO DUCTION D ATA ® Stellaris LM3S9L71 Microcontroller D ATA SHE E T D S -LM 3S 9L71 - 9 9 7 0 C opyri ght © 200 7-2011 Texas Instruments Incorporated Copyright Copyright © 2007-2011 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare® are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm 2 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table of Contents Revision History ............................................................................................................................. 37 About This Document .................................................................................................................... 45 Audience .............................................................................................................................................. About This Manual ................................................................................................................................ Related Documents ............................................................................................................................... Documentation Conventions .................................................................................................................. 45 45 45 46 1 Architectural Overview .......................................................................................... 48 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 1.2 1.3 1.4 Functional Overview ...................................................................................................... 50 ARM Cortex-M3 ............................................................................................................ 50 On-Chip Memory ........................................................................................................... 52 Serial Communications Peripherals ................................................................................ 53 System Integration ........................................................................................................ 59 Advanced Motion Control ............................................................................................... 63 Analog .......................................................................................................................... 65 JTAG and ARM Serial Wire Debug ................................................................................ 67 Packaging and Temperature .......................................................................................... 68 Target Applications ........................................................................................................ 68 High-Level Block Diagram ............................................................................................. 68 Hardware Details .......................................................................................................... 70 2 The Cortex-M3 Processor ...................................................................................... 71 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.5 2.5.1 2.5.2 2.5.3 Block Diagram .............................................................................................................. 72 Overview ...................................................................................................................... 73 System-Level Interface .................................................................................................. 73 Integrated Configurable Debug ...................................................................................... 73 Trace Port Interface Unit (TPIU) ..................................................................................... 74 Cortex-M3 System Component Details ........................................................................... 74 Programming Model ...................................................................................................... 75 Processor Mode and Privilege Levels for Software Execution ........................................... 75 Stacks .......................................................................................................................... 75 Register Map ................................................................................................................ 76 Register Descriptions .................................................................................................... 77 Exceptions and Interrupts .............................................................................................. 90 Data Types ................................................................................................................... 90 Memory Model .............................................................................................................. 90 Memory Regions, Types and Attributes ........................................................................... 92 Memory System Ordering of Memory Accesses .............................................................. 93 Behavior of Memory Accesses ....................................................................................... 93 Software Ordering of Memory Accesses ......................................................................... 94 Bit-Banding ................................................................................................................... 95 Data Storage ................................................................................................................ 97 Synchronization Primitives ............................................................................................. 98 Exception Model ........................................................................................................... 99 Exception States ........................................................................................................... 99 Exception Types .......................................................................................................... 100 Exception Handlers ..................................................................................................... 103 July 22, 2011 3 Texas Instruments-Production Data Table of Contents 2.5.4 2.5.5 2.5.6 2.5.7 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.7.1 2.7.2 2.8 Vector Table ................................................................................................................ Exception Priorities ...................................................................................................... Interrupt Priority Grouping ............................................................................................ Exception Entry and Return ......................................................................................... Fault Handling ............................................................................................................. Fault Types ................................................................................................................. Fault Escalation and Hard Faults .................................................................................. Fault Status Registers and Fault Address Registers ...................................................... Lockup ....................................................................................................................... Power Management .................................................................................................... Entering Sleep Modes ................................................................................................. Wake Up from Sleep Mode .......................................................................................... Instruction Set Summary .............................................................................................. 103 104 105 105 107 107 108 109 109 109 109 110 111 3 Cortex-M3 Peripherals ......................................................................................... 114 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.3 3.4 3.5 3.6 Functional Description ................................................................................................. 114 System Timer (SysTick) ............................................................................................... 114 Nested Vectored Interrupt Controller (NVIC) .................................................................. 115 System Control Block (SCB) ........................................................................................ 117 Memory Protection Unit (MPU) ..................................................................................... 117 Register Map .............................................................................................................. 122 System Timer (SysTick) Register Descriptions .............................................................. 124 NVIC Register Descriptions .......................................................................................... 128 System Control Block (SCB) Register Descriptions ........................................................ 141 Memory Protection Unit (MPU) Register Descriptions .................................................... 170 4 JTAG Interface ...................................................................................................... 180 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.5 4.5.1 4.5.2 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. JTAG Interface Pins ..................................................................................................... JTAG TAP Controller ................................................................................................... Shift Registers ............................................................................................................ Operational Considerations .......................................................................................... Initialization and Configuration ..................................................................................... Register Descriptions .................................................................................................. Instruction Register (IR) ............................................................................................... Data Registers ............................................................................................................ 181 181 182 182 184 184 185 187 188 188 190 5 System Control ..................................................................................................... 192 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 5.4 5.5 Signal Description ....................................................................................................... Functional Description ................................................................................................. Device Identification .................................................................................................... Reset Control .............................................................................................................. Non-Maskable Interrupt ............................................................................................... Power Control ............................................................................................................. Clock Control .............................................................................................................. System Control ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 4 192 192 193 193 198 198 199 206 207 207 209 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 6 Internal Memory ................................................................................................... 297 6.1 6.2 6.2.1 6.2.2 6.2.3 6.3 6.4 6.5 Block Diagram ............................................................................................................ 297 Functional Description ................................................................................................. 297 SRAM ........................................................................................................................ 298 ROM .......................................................................................................................... 298 Flash Memory ............................................................................................................. 300 Register Map .............................................................................................................. 304 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 305 Memory Register Descriptions (System Control Offset) .................................................. 317 7 Micro Direct Memory Access (μDMA) ................................................................ 333 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.6 Block Diagram ............................................................................................................ 334 Functional Description ................................................................................................. 334 Channel Assignments .................................................................................................. 335 Priority ........................................................................................................................ 336 Arbitration Size ............................................................................................................ 336 Request Types ............................................................................................................ 336 Channel Configuration ................................................................................................. 337 Transfer Modes ........................................................................................................... 339 Transfer Size and Increment ........................................................................................ 347 Peripheral Interface ..................................................................................................... 347 Software Request ........................................................................................................ 347 Interrupts and Errors .................................................................................................... 348 Initialization and Configuration ..................................................................................... 348 Module Initialization ..................................................................................................... 348 Configuring a Memory-to-Memory Transfer ................................................................... 348 Configuring a Peripheral for Simple Transmit ................................................................ 350 Configuring a Peripheral for Ping-Pong Receive ............................................................ 351 Configuring Channel Assignments ................................................................................ 354 Register Map .............................................................................................................. 354 μDMA Channel Control Structure ................................................................................. 355 μDMA Register Descriptions ........................................................................................ 362 8 General-Purpose Input/Outputs (GPIOs) ........................................................... 391 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.4 8.5 Signal Description ....................................................................................................... 391 Functional Description ................................................................................................. 396 Data Control ............................................................................................................... 398 Interrupt Control .......................................................................................................... 399 Mode Control .............................................................................................................. 400 Commit Control ........................................................................................................... 400 Pad Control ................................................................................................................. 401 Identification ............................................................................................................... 401 Initialization and Configuration ..................................................................................... 401 Register Map .............................................................................................................. 402 Register Descriptions .................................................................................................. 405 9 General-Purpose Timers ...................................................................................... 448 9.1 9.2 9.3 9.3.1 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. GPTM Reset Conditions .............................................................................................. July 22, 2011 449 449 452 453 5 Texas Instruments-Production Data Table of Contents 9.3.2 9.3.3 9.3.4 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.5 9.6 Timer Modes ............................................................................................................... DMA Operation ........................................................................................................... Accessing Concatenated Register Values ..................................................................... Initialization and Configuration ..................................................................................... One-Shot/Periodic Timer Mode .................................................................................... Real-Time Clock (RTC) Mode ...................................................................................... Input Edge-Count Mode ............................................................................................... Input Edge Timing Mode .............................................................................................. PWM Mode ................................................................................................................. Register Map .............................................................................................................. Register Descriptions .................................................................................................. 453 459 459 460 460 461 461 462 462 463 464 10 Watchdog Timers ................................................................................................. 495 10.1 10.2 10.2.1 10.3 10.4 10.5 Block Diagram ............................................................................................................ Functional Description ................................................................................................. Register Access Timing ............................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 496 496 497 497 497 498 11 Analog-to-Digital Converter (ADC) ..................................................................... 520 11.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.4 11.4.1 11.4.2 11.5 11.6 Block Diagram ............................................................................................................ 521 Signal Description ....................................................................................................... 522 Functional Description ................................................................................................. 524 Sample Sequencers .................................................................................................... 524 Module Control ............................................................................................................ 525 Hardware Sample Averaging Circuit ............................................................................. 527 Analog-to-Digital Converter .......................................................................................... 528 Differential Sampling ................................................................................................... 530 Internal Temperature Sensor ........................................................................................ 533 Digital Comparator Unit ............................................................................................... 533 Initialization and Configuration ..................................................................................... 538 Module Initialization ..................................................................................................... 538 Sample Sequencer Configuration ................................................................................. 539 Register Map .............................................................................................................. 539 Register Descriptions .................................................................................................. 541 12 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 599 12.1 Block Diagram ............................................................................................................ 12.2 Signal Description ....................................................................................................... 12.3 Functional Description ................................................................................................. 12.3.1 Transmit/Receive Logic ............................................................................................... 12.3.2 Baud-Rate Generation ................................................................................................. 12.3.3 Data Transmission ...................................................................................................... 12.3.4 Serial IR (SIR) ............................................................................................................. 12.3.5 ISO 7816 Support ....................................................................................................... 12.3.6 Modem Handshake Support ......................................................................................... 12.3.7 LIN Support ................................................................................................................ 12.3.8 FIFO Operation ........................................................................................................... 12.3.9 Interrupts .................................................................................................................... 12.3.10 Loopback Operation .................................................................................................... 6 600 600 602 603 603 604 604 605 606 607 608 609 609 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 12.3.11 12.4 12.5 12.6 DMA Operation ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 609 610 611 612 13 Synchronous Serial Interface (SSI) .................................................................... 660 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.4 13.5 13.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Bit Rate Generation ..................................................................................................... FIFO Operation ........................................................................................................... Interrupts .................................................................................................................... Frame Formats ........................................................................................................... DMA Operation ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 14 Inter-Integrated Circuit (I2C) Interface ................................................................ 702 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.4 14.5 14.6 14.7 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. I2C Bus Functional Overview ........................................................................................ Available Speed Modes ............................................................................................... Interrupts .................................................................................................................... Loopback Operation .................................................................................................... Command Sequence Flow Charts ................................................................................ Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions (I2C Master) ............................................................................... Register Descriptions (I2C Slave) ................................................................................. 15 Inter-Integrated Circuit Sound (I2S) Interface .................................................... 739 15.1 15.2 15.3 15.3.1 15.3.2 15.4 15.5 15.6 Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Transmit ..................................................................................................................... Receive ...................................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 661 661 662 663 663 663 664 671 672 673 674 703 703 704 704 706 707 708 709 716 717 718 730 740 740 742 743 747 749 750 751 16 Controller Area Network (CAN) Module ............................................................. 776 16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 Block Diagram ............................................................................................................ 777 Signal Description ....................................................................................................... 777 Functional Description ................................................................................................. 778 Initialization ................................................................................................................. 779 Operation ................................................................................................................... 780 Transmitting Message Objects ..................................................................................... 781 Configuring a Transmit Message Object ........................................................................ 781 Updating a Transmit Message Object ........................................................................... 782 July 22, 2011 7 Texas Instruments-Production Data Table of Contents 16.3.6 Accepting Received Message Objects .......................................................................... 783 16.3.7 Receiving a Data Frame .............................................................................................. 783 16.3.8 Receiving a Remote Frame .......................................................................................... 783 16.3.9 Receive/Transmit Priority ............................................................................................. 784 16.3.10 Configuring a Receive Message Object ........................................................................ 784 16.3.11 Handling of Received Message Objects ........................................................................ 785 16.3.12 Handling of Interrupts .................................................................................................. 787 16.3.13 Test Mode ................................................................................................................... 788 16.3.14 Bit Timing Configuration Error Considerations ............................................................... 790 16.3.15 Bit Time and Bit Rate ................................................................................................... 790 16.3.16 Calculating the Bit Timing Parameters .......................................................................... 792 16.4 Register Map .............................................................................................................. 795 16.5 CAN Register Descriptions .......................................................................................... 796 17 Ethernet Controller .............................................................................................. 827 17.1 17.2 17.3 17.3.1 17.3.2 17.3.3 17.3.4 17.4 17.4.1 17.5 17.6 Block Diagram ............................................................................................................ 827 Signal Description ....................................................................................................... 828 Functional Description ................................................................................................. 830 MAC Operation ........................................................................................................... 830 Media Independent Interface ........................................................................................ 834 Interrupts .................................................................................................................... 837 DMA Operation ........................................................................................................... 837 Initialization and Configuration ..................................................................................... 838 Software Configuration ................................................................................................ 838 Register Map .............................................................................................................. 838 Ethernet MAC Register Descriptions ............................................................................. 839 18 Universal Serial Bus (USB) Controller ............................................................... 863 18.1 18.2 18.3 18.3.1 18.3.2 18.3.3 18.3.4 18.4 18.4.1 18.4.2 18.5 18.6 Block Diagram ............................................................................................................ 864 Signal Description ....................................................................................................... 864 Functional Description ................................................................................................. 866 Operation as a Device ................................................................................................. 866 Operation as a Host .................................................................................................... 871 OTG Mode .................................................................................................................. 875 DMA Operation ........................................................................................................... 877 Initialization and Configuration ..................................................................................... 878 Pin Configuration ......................................................................................................... 878 Endpoint Configuration ................................................................................................ 878 Register Map .............................................................................................................. 879 Register Descriptions .................................................................................................. 890 19 Analog Comparators .......................................................................................... 1002 19.1 19.2 19.3 19.3.1 19.4 19.5 19.6 Block Diagram ........................................................................................................... Signal Description ..................................................................................................... Functional Description ............................................................................................... Internal Reference Programming ................................................................................ Initialization and Configuration .................................................................................... Register Map ............................................................................................................ Register Descriptions ................................................................................................. 8 1002 1003 1004 1004 1006 1006 1007 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 20 Pulse Width Modulator (PWM) .......................................................................... 1015 20.1 20.2 20.3 20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.3.6 20.3.7 20.3.8 20.4 20.5 20.6 Block Diagram ........................................................................................................... 1016 Signal Description ..................................................................................................... 1017 Functional Description ............................................................................................... 1020 PWM Timer ............................................................................................................... 1020 PWM Comparators .................................................................................................... 1020 PWM Signal Generator .............................................................................................. 1022 Dead-Band Generator ............................................................................................... 1023 Interrupt/ADC-Trigger Selector ................................................................................... 1023 Synchronization Methods .......................................................................................... 1023 Fault Conditions ........................................................................................................ 1024 Output Control Block .................................................................................................. 1025 Initialization and Configuration .................................................................................... 1026 Register Map ............................................................................................................ 1026 Register Descriptions ................................................................................................. 1029 21 Quadrature Encoder Interface (QEI) ................................................................. 1088 21.1 21.2 21.3 21.4 21.5 21.6 Block Diagram ........................................................................................................... Signal Description ..................................................................................................... Functional Description ............................................................................................... Initialization and Configuration .................................................................................... Register Map ............................................................................................................ Register Descriptions ................................................................................................. 22 Pin Diagram ........................................................................................................ 1111 1088 1089 1090 1093 1093 1094 23 Signal Tables ...................................................................................................... 1113 23.1 23.2 23.3 100-Pin LQFP Package Pin Tables ............................................................................. 1114 108-Ball BGA Package Pin Tables .............................................................................. 1151 Connections for Unused Signals ................................................................................. 1187 24 Operating Characteristics ................................................................................. 1189 25 Electrical Characteristics .................................................................................. 1190 25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.8.1 25.8.2 25.8.3 25.8.4 25.8.5 25.9 25.10 25.11 25.12 25.13 Maximum Ratings ...................................................................................................... 1190 Recommended Operating Conditions ......................................................................... 1190 Load Conditions ........................................................................................................ 1191 JTAG and Boundary Scan .......................................................................................... 1191 Power and Brown-out ................................................................................................ 1192 Reset ........................................................................................................................ 1194 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1195 Clocks ...................................................................................................................... 1195 PLL Specifications ..................................................................................................... 1195 PIOSC Specifications ................................................................................................ 1196 Internal 30-kHz Oscillator Specifications ..................................................................... 1196 Main Oscillator Specifications ..................................................................................... 1196 System Clock Specification with ADC Operation .......................................................... 1197 Sleep Modes ............................................................................................................. 1198 Flash Memory .......................................................................................................... 1198 GPIO Module ............................................................................................................ 1198 Analog-to-Digital Converter (ADC) .............................................................................. 1199 Synchronous Serial Interface (SSI) ............................................................................. 1200 July 22, 2011 9 Texas Instruments-Production Data Table of Contents 25.14 Inter-Integrated Circuit (I2C) Interface ......................................................................... 25.15 Inter-Integrated Circuit Sound (I2S) Interface ............................................................... 25.16 Ethernet Controller .................................................................................................... 25.17 Universal Serial Bus (USB) Controller ......................................................................... 25.18 Analog Comparator ................................................................................................... 25.19 USB Module .............................................................................................................. 25.20 Current Consumption ................................................................................................. 25.20.1 Nominal Power Consumption ..................................................................................... 25.20.2 Maximum Current Consumption ................................................................................. A 1202 1203 1204 1206 1207 1207 1207 1207 1208 Register Quick Reference ................................................................................. 1210 B Ordering and Contact Information ................................................................... 1259 B.1 B.2 B.3 B.4 Ordering Information .................................................................................................. Part Markings ............................................................................................................ Kits ........................................................................................................................... Support Information ................................................................................................... 1259 1259 1260 1260 C Package Information .......................................................................................... 1261 C.1 C.1.1 C.1.2 C.1.3 C.2 C.2.1 C.2.2 C.2.3 100-Pin LQFP Package ............................................................................................. Package Dimensions ................................................................................................. Tray Dimensions ....................................................................................................... Tape and Reel Dimensions ........................................................................................ 108-Ball BGA Package .............................................................................................. Package Dimensions ................................................................................................. Tray Dimensions ....................................................................................................... Tape and Reel Dimensions ........................................................................................ 10 1261 1261 1263 1263 1265 1265 1267 1268 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 7-5. Figure 7-6. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 10-1. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure 11-5. Figure 11-6. Figure 11-7. Figure 11-8. Figure 11-9. Figure 11-10. Stellaris LM3S9L71 Microcontroller High-Level Block Diagram .............................. 69 CPU Block Diagram ............................................................................................. 73 TPIU Block Diagram ............................................................................................ 74 Cortex-M3 Register Set ........................................................................................ 76 Bit-Band Mapping ................................................................................................ 97 Data Storage ....................................................................................................... 98 Vector Table ...................................................................................................... 104 Exception Stack Frame ...................................................................................... 106 SRD Use Example ............................................................................................. 120 JTAG Module Block Diagram .............................................................................. 181 Test Access Port State Machine ......................................................................... 184 IDCODE Register Format ................................................................................... 190 BYPASS Register Format ................................................................................... 190 Boundary Scan Register Format ......................................................................... 191 Basic RST Configuration .................................................................................... 195 External Circuitry to Extend Power-On Reset ....................................................... 195 Reset Circuit Controlled by Switch ...................................................................... 196 Power Architecture ............................................................................................ 199 Main Clock Tree ................................................................................................ 201 Internal Memory Block Diagram .......................................................................... 297 μDMA Block Diagram ......................................................................................... 334 Example of Ping-Pong μDMA Transaction ........................................................... 340 Memory Scatter-Gather, Setup and Configuration ................................................ 342 Memory Scatter-Gather, μDMA Copy Sequence .................................................. 343 Peripheral Scatter-Gather, Setup and Configuration ............................................. 345 Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 346 Digital I/O Pads ................................................................................................. 397 Analog/Digital I/O Pads ...................................................................................... 398 GPIODATA Write Example ................................................................................. 399 GPIODATA Read Example ................................................................................. 399 GPTM Module Block Diagram ............................................................................ 449 Timer Daisy Chain ............................................................................................. 455 Input Edge-Count Mode Example ....................................................................... 456 16-Bit Input Edge-Time Mode Example ............................................................... 458 16-Bit PWM Mode Example ................................................................................ 459 WDT Module Block Diagram .............................................................................. 496 Implementation of Two ADC Blocks .................................................................... 521 ADC Module Block Diagram ............................................................................... 522 ADC Sample Phases ......................................................................................... 526 Doubling the ADC Sample Rate .......................................................................... 527 Skewed Sampling .............................................................................................. 527 Sample Averaging Example ............................................................................... 528 Internal Voltage Conversion Result ..................................................................... 529 External Voltage Conversion Result .................................................................... 530 Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 531 Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 532 July 22, 2011 11 Texas Instruments-Production Data Table of Contents Figure 11-11. Figure 11-12. Figure 11-13. Figure 11-14. Figure 11-15. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Figure 13-12. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 14-6. Figure 14-7. Figure 14-8. Figure 14-9. Figure 14-10. Figure 14-11. Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 532 Internal Temperature Sensor Characteristic ......................................................... 533 Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 536 Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 537 High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 538 UART Module Block Diagram ............................................................................. 600 UART Character Frame ..................................................................................... 603 IrDA Data Modulation ......................................................................................... 605 LIN Message ..................................................................................................... 607 LIN Synchronization Field ................................................................................... 608 SSI Module Block Diagram ................................................................................. 661 TI Synchronous Serial Frame Format (Single Transfer) ........................................ 665 TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 665 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 666 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 666 Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 667 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 668 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 668 Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 669 MICROWIRE Frame Format (Single Frame) ........................................................ 670 MICROWIRE Frame Format (Continuous Transfer) ............................................. 671 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 671 I2C Block Diagram ............................................................................................. 703 I2C Bus Configuration ........................................................................................ 704 START and STOP Conditions ............................................................................. 705 Complete Data Transfer with a 7-Bit Address ....................................................... 705 R/S Bit in First Byte ............................................................................................ 706 Data Validity During Bit Transfer on the I2C Bus ................................................... 706 Master Single TRANSMIT .................................................................................. 710 Master Single RECEIVE ..................................................................................... 711 Master TRANSMIT with Repeated START ........................................................... 712 Master RECEIVE with Repeated START ............................................................. 713 Master RECEIVE with Repeated START after TRANSMIT with Repeated START .............................................................................................................. 714 Figure 14-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated START .............................................................................................................. 715 Figure 14-13. Slave Command Sequence ................................................................................ 716 Figure 15-1. I2S Block Diagram ............................................................................................. 740 Figure 15-2. I2S Data Transfer ............................................................................................... 743 Figure 15-3. Left-Justified Data Transfer ................................................................................ 743 Figure 15-4. Right-Justified Data Transfer .............................................................................. 743 Figure 16-1. CAN Controller Block Diagram ............................................................................ 777 Figure 16-2. CAN Data/Remote Frame .................................................................................. 779 Figure 16-3. Message Objects in a FIFO Buffer ...................................................................... 787 Figure 16-4. CAN Bit Time .................................................................................................... 791 Figure 17-1. Ethernet Controller ............................................................................................. 827 Figure 17-2. Ethernet MAC Block Diagram ............................................................................. 828 Figure 17-3. Ethernet Frame ................................................................................................. 830 12 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 17-4. Figure 18-1. Figure 19-1. Figure 19-2. Figure 19-3. Figure 20-1. Figure 20-2. Figure 20-3. Figure 20-4. Figure 20-5. Figure 20-6. Figure 21-1. Figure 21-2. Figure 22-1. Figure 22-2. Figure 25-1. Figure 25-2. Figure 25-3. Figure 25-4. Figure 25-5. Figure 25-6. Figure 25-7. Figure 25-8. Figure 25-9. Figure 25-10. Figure 25-11. Figure 25-12. Figure 25-13. Figure 25-14. Figure 25-15. Figure 25-16. Figure 25-17. Figure 25-18. Figure 25-19. Figure C-1. Figure C-2. Figure C-3. Figure C-4. Figure C-5. Figure C-6. Management Frame Format ............................................................................... 836 USB Module Block Diagram ............................................................................... 864 Analog Comparator Module Block Diagram ....................................................... 1002 Structure of Comparator Unit ............................................................................ 1004 Comparator Internal Reference Structure .......................................................... 1005 PWM Module Diagram ..................................................................................... 1017 PWM Generator Block Diagram ........................................................................ 1017 PWM Count-Down Mode .................................................................................. 1021 PWM Count-Up/Down Mode ............................................................................. 1022 PWM Generation Example In Count-Up/Down Mode .......................................... 1022 PWM Dead-Band Generator ............................................................................. 1023 QEI Block Diagram .......................................................................................... 1089 Quadrature Encoder and Velocity Predivider Operation ...................................... 1092 100-Pin LQFP Package Pin Diagram ................................................................ 1111 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1112 Load Conditions ............................................................................................... 1191 JTAG Test Clock Input Timing ........................................................................... 1192 JTAG Test Access Port (TAP) Timing ................................................................ 1192 Power-On Reset Timing ................................................................................... 1193 Brown-Out Reset Timing .................................................................................. 1193 Power-On Reset and Voltage Parameters ......................................................... 1194 External Reset Timing (RST) ............................................................................ 1194 Software Reset Timing ..................................................................................... 1194 Watchdog Reset Timing ................................................................................... 1195 MOSC Failure Reset Timing ............................................................................. 1195 ADC Input Equivalency Diagram ....................................................................... 1200 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................. 1201 SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1201 SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1202 I2C Timing ....................................................................................................... 1203 I2S Master Mode Transmit Timing ..................................................................... 1203 I2S Master Mode Receive Timing ...................................................................... 1204 I2S Slave Mode Transmit Timing ....................................................................... 1204 I2S Slave Mode Receive Timing ........................................................................ 1204 100-Pin LQFP Package Dimensions ................................................................. 1261 100-Pin LQFP Tray Dimensions ........................................................................ 1263 100-Pin LQFP Tape and Reel Dimensions ......................................................... 1264 108-Ball BGA Package Dimensions .................................................................. 1265 108-Ball BGA Tray Dimensions ......................................................................... 1267 108-Ball BGA Tape and Reel Dimensions .......................................................... 1268 July 22, 2011 13 Texas Instruments-Production Data Table of Contents List of Tables Table 1. Table 2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 6-1. Table 6-2. Table 6-3. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table 7-6. Revision History .................................................................................................. 37 Documentation Conventions ................................................................................ 46 Summary of Processor Mode, Privilege Level, and Stack Use ................................ 76 Processor Register Map ....................................................................................... 77 PSR Register Combinations ................................................................................. 82 Memory Map ....................................................................................................... 90 Memory Access Behavior ..................................................................................... 93 SRAM Memory Bit-Banding Regions .................................................................... 95 Peripheral Memory Bit-Banding Regions ............................................................... 95 Exception Types ................................................................................................ 101 Interrupts .......................................................................................................... 102 Exception Return Behavior ................................................................................. 107 Faults ............................................................................................................... 107 Fault Status and Fault Address Registers ............................................................ 109 Cortex-M3 Instruction Summary ......................................................................... 111 Core Peripheral Register Regions ....................................................................... 114 Memory Attributes Summary .............................................................................. 117 TEX, S, C, and B Bit Field Encoding ................................................................... 120 Cache Policy for Memory Attribute Encoding ....................................................... 121 AP Bit Field Encoding ........................................................................................ 121 Memory Region Attributes for Stellaris Microcontrollers ........................................ 121 Peripherals Register Map ................................................................................... 122 Interrupt Priority Levels ...................................................................................... 149 Example SIZE Field Values ................................................................................ 177 Signals for JTAG_SWD_SWO (100LQFP) ........................................................... 181 Signals for JTAG_SWD_SWO (108BGA) ............................................................ 182 JTAG Port Pins State after Power-On Reset or RST assertion .............................. 183 JTAG Instruction Register Commands ................................................................. 188 Signals for System Control & Clocks (100LQFP) .................................................. 192 Signals for System Control & Clocks (108BGA) ................................................... 192 Reset Sources ................................................................................................... 193 Clock Source Options ........................................................................................ 200 Possible System Clock Frequencies Using the SYSDIV Field ............................... 202 Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 202 Examples of Possible System Clock Frequencies with DIV400=1 ......................... 203 System Control Register Map ............................................................................. 208 RCC2 Fields that Override RCC Fields ............................................................... 229 Flash Memory Protection Policy Combinations .................................................... 301 User-Programmable Flash Memory Resident Registers ....................................... 304 Flash Register Map ............................................................................................ 305 μDMA Channel Assignments .............................................................................. 335 Request Type Support ....................................................................................... 337 Control Structure Memory Map ........................................................................... 338 Channel Control Structure .................................................................................. 338 μDMA Read Example: 8-Bit Peripheral ................................................................ 347 μDMA Interrupt Assignments .............................................................................. 348 14 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 7-7. Table 7-8. Table 7-9. Table 7-10. Table 7-11. Table 7-12. Table 7-13. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table 8-7. Table 8-8. Table 8-9. Table 8-10. Table 8-11. Table 8-12. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 10-1. Table 11-1. Table 11-2. Table 11-3. Table 11-4. Table 11-5. Table 12-1. Table 12-2. Table 12-3. Table 12-4. Table 13-1. Table 13-2. Table 13-3. Table 14-1. Table 14-2. Table 14-3. Table 14-4. Table 14-5. Table 15-1. Table 15-2. Table 15-3. Table 15-4. Channel Control Structure Offsets for Channel 30 ................................................ 349 Channel Control Word Configuration for Memory Transfer Example ...................... 349 Channel Control Structure Offsets for Channel 7 .................................................. 350 Channel Control Word Configuration for Peripheral Transmit Example .................. 351 Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 352 Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............................................................................................................ 353 μDMA Register Map .......................................................................................... 354 GPIO Pins With Non-Zero Reset Values .............................................................. 392 GPIO Pins and Alternate Functions (100LQFP) ................................................... 392 GPIO Pins and Alternate Functions (108BGA) ..................................................... 394 GPIO Pad Configuration Examples ..................................................................... 401 GPIO Interrupt Configuration Example ................................................................ 402 GPIO Pins With Non-Zero Reset Values .............................................................. 403 GPIO Register Map ........................................................................................... 403 GPIO Pins With Non-Zero Reset Values .............................................................. 416 GPIO Pins With Non-Zero Reset Values .............................................................. 422 GPIO Pins With Non-Zero Reset Values .............................................................. 424 GPIO Pins With Non-Zero Reset Values .............................................................. 427 GPIO Pins With Non-Zero Reset Values .............................................................. 434 Available CCP Pins ............................................................................................ 449 Signals for General-Purpose Timers (100LQFP) .................................................. 450 Signals for General-Purpose Timers (108BGA) .................................................... 451 General-Purpose Timer Capabilities .................................................................... 453 16-Bit Timer With Prescaler Configurations ......................................................... 454 Timers Register Map .......................................................................................... 463 Watchdog Timers Register Map .......................................................................... 498 Signals for ADC (100LQFP) ............................................................................... 522 Signals for ADC (108BGA) ................................................................................. 523 Samples and FIFO Depth of Sequencers ............................................................ 524 Differential Sampling Pairs ................................................................................. 530 ADC Register Map ............................................................................................. 539 Signals for UART (100LQFP) ............................................................................. 601 Signals for UART (108BGA) ............................................................................... 601 Flow Control Mode ............................................................................................. 607 UART Register Map ........................................................................................... 611 Signals for SSI (100LQFP) ................................................................................. 662 Signals for SSI (108BGA) ................................................................................... 662 SSI Register Map .............................................................................................. 673 Signals for I2C (100LQFP) ................................................................................. 703 Signals for I2C (108BGA) ................................................................................... 703 Examples of I2C Master Timer Period versus Speed Mode ................................... 707 Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 717 Write Field Decoding for I2CMCS[3:0] Field ......................................................... 722 Signals for I2S (100LQFP) ................................................................................. 741 Signals for I2S (108BGA) ................................................................................... 741 I2S Transmit FIFO Interface ................................................................................ 744 Crystal Frequency (Values from 3.5795 MHz to 5 MHz) ........................................ 745 July 22, 2011 15 Texas Instruments-Production Data Table of Contents Table 15-5. Table 15-6. Table 15-7. Table 15-8. Table 15-9. Table 15-10. Table 16-1. Table 16-2. Table 16-3. Table 16-4. Table 16-5. Table 16-6. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 17-5. Table 17-6. Table 18-1. Table 18-2. Table 18-3. Table 18-4. Table 18-5. Table 18-6. Table 19-1. Table 19-2. Table 19-3. Table 19-4. Table 20-1. Table 20-2. Table 20-3. Table 21-1. Table 21-2. Table 21-3. Table 23-1. Table 23-2. Table 23-3. Table 23-4. Table 23-5. Table 23-6. Table 23-7. Table 23-8. Table 23-9. Table 23-10. Table 23-11. Table 23-12. Table 23-13. Table 24-1. Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) ..................................... 745 Crystal Frequency (Values from 10 MHz to 14.3181 MHz) .................................... 746 Crystal Frequency (Values from 16 MHz to 16.384 MHz) ...................................... 746 I2S Receive FIFO Interface ................................................................................. 748 Audio Formats Configuration .............................................................................. 750 Inter-Integrated Circuit Sound (I2S) Interface Register Map ................................... 751 Signals for Controller Area Network (100LQFP) ................................................... 778 Signals for Controller Area Network (108BGA) ..................................................... 778 Message Object Configurations .......................................................................... 784 CAN Protocol Ranges ........................................................................................ 791 CANBIT Register Values .................................................................................... 791 CAN Register Map ............................................................................................. 795 Signals for Ethernet (100LQFP) .......................................................................... 828 Signals for Ethernet (108BGA) ............................................................................ 829 TX & RX FIFO Organization ............................................................................... 832 Receive Signal Encoding ................................................................................... 834 Transmit Signal Encoding ................................................................................... 835 Ethernet Register Map ....................................................................................... 839 Signals for USB (100LQFP) ................................................................................ 864 Signals for USB (108BGA) ................................................................................. 865 Remainder (MAXLOAD/4) .................................................................................. 877 Actual Bytes Read ............................................................................................. 877 Packet Sizes That Clear RXRDY ........................................................................ 877 Universal Serial Bus (USB) Controller Register Map ............................................ 879 Signals for Analog Comparators (100LQFP) ...................................................... 1003 Signals for Analog Comparators (108BGA) ........................................................ 1003 Internal Reference Voltage and ACREFCTL Field Values ................................... 1005 Analog Comparators Register Map ................................................................... 1006 Signals for PWM (100LQFP) ............................................................................ 1018 Signals for PWM (108BGA) .............................................................................. 1019 PWM Register Map .......................................................................................... 1027 Signals for QEI (100LQFP) ............................................................................... 1089 Signals for QEI (108BGA) ................................................................................. 1090 QEI Register Map ............................................................................................ 1094 GPIO Pins With Default Alternate Functions ...................................................... 1113 Signals by Pin Number ..................................................................................... 1114 Signals by Signal Name ................................................................................... 1126 Signals by Function, Except for GPIO ............................................................... 1137 GPIO Pins and Alternate Functions ................................................................... 1145 Possible Pin Assignments for Alternate Functions .............................................. 1148 Signals by Pin Number ..................................................................................... 1151 Signals by Signal Name ................................................................................... 1164 Signals by Function, Except for GPIO ............................................................... 1174 GPIO Pins and Alternate Functions ................................................................... 1182 Possible Pin Assignments for Alternate Functions .............................................. 1185 Connections for Unused Signals (100-Pin LQFP) ............................................... 1188 Connections for Unused Signals (108-Ball BGA) ................................................ 1188 Temperature Characteristics ............................................................................. 1189 16 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 24-2. Table 24-3. Table 25-1. Table 25-2. Table 25-3. Table 25-4. Table 25-5. Table 25-6. Table 25-7. Table 25-8. Table 25-9. Table 25-10. Table 25-11. Table 25-12. Table 25-13. Table 25-14. Table 25-15. Table 25-16. Table 25-17. Table 25-18. Table 25-19. Table 25-20. Table 25-21. Table 25-22. Table 25-23. Table 25-24. Table 25-25. Table 25-26. Table 25-27. Table 25-28. Table 25-29. Table 25-30. Table 25-31. Table 25-32. Table 25-33. Table 25-34. Table 25-35. Table 25-36. Table 25-37. Table 25-38. Table 25-39. Table 25-40. Table B-1. Thermal Characteristics ................................................................................... 1189 ESD Absolute Maximum Ratings ...................................................................... 1189 Maximum Ratings ............................................................................................ 1190 Recommended DC Operating Conditions .......................................................... 1190 JTAG Characteristics ....................................................................................... 1191 Power Characteristics ...................................................................................... 1192 Reset Characteristics ....................................................................................... 1194 LDO Regulator Characteristics ......................................................................... 1195 Phase Locked Loop (PLL) Characteristics ......................................................... 1195 Actual PLL Frequency ...................................................................................... 1196 PIOSC Clock Characteristics ............................................................................ 1196 30-kHz Clock Characteristics ............................................................................ 1196 Main Oscillator Clock Characteristics ................................................................ 1196 Supported MOSC Crystal Frequencies .............................................................. 1197 System Clock Characteristics with ADC Operation ............................................. 1197 Sleep Modes AC Characteristics ....................................................................... 1198 Flash Memory Characteristics ........................................................................... 1198 GPIO Module Characteristics ............................................................................ 1198 ADC Characteristics ......................................................................................... 1199 ADC Module External Reference Characteristics ............................................... 1200 ADC Module Internal Reference Characteristics ................................................ 1200 SSI Characteristics .......................................................................................... 1200 I2C Characteristics ........................................................................................... 1202 I2S Master Clock (Receive and Transmit) .......................................................... 1203 I2S Slave Clock (Receive and Transmit) ............................................................ 1203 I2S Master Mode .............................................................................................. 1203 I2S Slave Mode ................................................................................................ 1204 Ethernet Station Management .......................................................................... 1204 100BASE-TX Transmitter Characteristics .......................................................... 1205 100BASE-TX Transmitter Characteristics (informative) ....................................... 1205 100BASE-TX Receiver Characteristics .............................................................. 1205 10BASE-T Transmitter Characteristics .............................................................. 1205 10BASE-T Transmitter Characteristics (informative) ........................................... 1206 10BASE-T Receiver Characteristics .................................................................. 1206 Isolation Transformers ...................................................................................... 1206 USB Controller Characteristics ......................................................................... 1207 Analog Comparator Characteristics ................................................................... 1207 Analog Comparator Voltage Reference Characteristics ...................................... 1207 USB Controller DC Characteristics .................................................................... 1207 Nominal Power Consumption ........................................................................... 1208 Detailed Current Specifications ......................................................................... 1208 External VDDC Source Current Specifications ..................................................... 1209 Part Ordering Information ................................................................................. 1259 July 22, 2011 17 Texas Instruments-Production Data Table of Contents List of Registers The Cortex-M3 Processor ............................................................................................................. 71 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Cortex General-Purpose Register 0 (R0) ........................................................................... 78 Cortex General-Purpose Register 1 (R1) ........................................................................... 78 Cortex General-Purpose Register 2 (R2) ........................................................................... 78 Cortex General-Purpose Register 3 (R3) ........................................................................... 78 Cortex General-Purpose Register 4 (R4) ........................................................................... 78 Cortex General-Purpose Register 5 (R5) ........................................................................... 78 Cortex General-Purpose Register 6 (R6) ........................................................................... 78 Cortex General-Purpose Register 7 (R7) ........................................................................... 78 Cortex General-Purpose Register 8 (R8) ........................................................................... 78 Cortex General-Purpose Register 9 (R9) ........................................................................... 78 Cortex General-Purpose Register 10 (R10) ....................................................................... 78 Cortex General-Purpose Register 11 (R11) ........................................................................ 78 Cortex General-Purpose Register 12 (R12) ....................................................................... 78 Stack Pointer (SP) ........................................................................................................... 79 Link Register (LR) ............................................................................................................ 80 Program Counter (PC) ..................................................................................................... 81 Program Status Register (PSR) ........................................................................................ 82 Priority Mask Register (PRIMASK) .................................................................................... 86 Fault Mask Register (FAULTMASK) .................................................................................. 87 Base Priority Mask Register (BASEPRI) ............................................................................ 88 Control Register (CONTROL) ........................................................................................... 89 Cortex-M3 Peripherals ................................................................................................................. 114 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 125 SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 127 SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 128 Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 129 Interrupt 32-54 Set Enable (EN1), offset 0x104 ................................................................ 130 Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 131 Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ............................................................ 132 Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 133 Interrupt 32-54 Set Pending (PEND1), offset 0x204 ......................................................... 134 Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 135 Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 .................................................. 136 Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 137 Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ........................................................... 138 Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 139 Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 139 Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 139 Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 139 Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 139 Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 139 Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 139 Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 139 Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 139 18 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 139 Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 139 Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 139 Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 139 Interrupt 52-54 Priority (PRI13), offset 0x434 ................................................................... 139 Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 141 Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 142 CPU ID Base (CPUID), offset 0xD00 ............................................................................... 144 Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 145 Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 148 Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 149 System Control (SYSCTRL), offset 0xD10 ....................................................................... 151 Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 153 System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 155 System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 156 System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 157 System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 158 Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 162 Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 168 Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 169 Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 170 MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 171 MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 172 MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 174 MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 175 MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 175 MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 175 MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 175 MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 177 MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 177 MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 177 MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 177 System Control ............................................................................................................................ 192 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Device Identification 0 (DID0), offset 0x000 ..................................................................... 210 Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 212 Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 213 Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 215 Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 217 Reset Cause (RESC), offset 0x05C ................................................................................ 219 Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 221 XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 226 GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 227 Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 229 Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 232 Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 233 Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 235 I2S MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 236 Device Identification 1 (DID1), offset 0x004 ..................................................................... 238 July 22, 2011 19 Texas Instruments-Production Data Table of Contents Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 240 Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 241 Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 244 Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 246 Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 249 Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 251 Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 253 Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 254 Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 258 Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 261 Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 263 Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 264 Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 267 Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 270 Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 272 Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 275 Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 278 Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 281 Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 284 Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 287 Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 290 Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 292 Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 295 Internal Memory ........................................................................................................................... 297 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Flash Memory Address (FMA), offset 0x000 .................................................................... 306 Flash Memory Data (FMD), offset 0x004 ......................................................................... 307 Flash Memory Control (FMC), offset 0x008 ..................................................................... 308 Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 311 Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 312 Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 313 Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 314 Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 315 Flash Control (FCTL), offset 0x0F8 ................................................................................. 316 Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 317 ROM Control (RMCTL), offset 0x0F0 .............................................................................. 318 Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 319 Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 320 Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 321 User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 323 User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 324 User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 325 User Register 3 (USER_REG3), offset 0x1EC ................................................................. 326 Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 327 Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 328 Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 329 Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 330 Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 331 Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 332 20 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Micro Direct Memory Access (μDMA) ........................................................................................ 333 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 356 DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 357 DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 358 DMA Status (DMASTAT), offset 0x000 ............................................................................ 363 DMA Configuration (DMACFG), offset 0x004 ................................................................... 365 DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 366 DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 367 DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 368 DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 369 DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 370 DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 371 DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 372 DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 373 DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 374 DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 375 DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 376 DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 377 DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 378 DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 379 DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 380 DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 381 DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 382 DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 383 DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 384 DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 385 DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 386 DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 387 DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 388 DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 389 DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 390 General-Purpose Input/Outputs (GPIOs) ................................................................................... 391 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 406 GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 407 GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 408 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 409 GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 410 GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 411 GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 412 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 413 GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 415 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 416 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 418 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 419 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 420 GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 421 GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 422 GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 424 July 22, 2011 21 Texas Instruments-Production Data Table of Contents Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 426 GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 427 GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 429 GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 430 GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 432 GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 434 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 436 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 437 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 438 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 439 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 440 GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 441 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 442 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 443 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 444 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 445 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 446 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 447 General-Purpose Timers ............................................................................................................. 448 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 465 GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 466 GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 468 GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 470 GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 473 GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 475 GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 478 GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 481 GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 483 GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 484 GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 485 GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 486 GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 487 GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 488 GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 489 GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 490 GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 491 GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 492 GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 493 GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 494 Watchdog Timers ......................................................................................................................... 495 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 499 Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 500 Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 501 Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 503 Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 504 Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 505 Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 506 Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 507 22 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 508 509 510 511 512 513 514 515 516 517 518 519 Analog-to-Digital Converter (ADC) ............................................................................................. 520 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 542 ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 543 ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 545 ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 547 ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 550 ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 552 ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 557 ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 558 ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 560 ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 562 ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 564 ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 565 ADC Control (ADCCTL), offset 0x038 ............................................................................. 567 ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 568 ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 570 ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 573 ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 573 ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 573 ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 573 ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 574 ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 574 ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 574 ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 574 ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 576 ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 578 ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 580 ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 580 ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 581 ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 581 ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 583 ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 583 ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 584 ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 584 ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 586 ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 587 July 22, 2011 23 Texas Instruments-Production Data Table of Contents Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 588 ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 589 ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 590 ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 595 ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 595 ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 595 ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 595 ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 595 ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 595 ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 595 ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 595 ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 598 ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 598 ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 598 ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 598 ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 598 ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 598 ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 598 ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 598 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 599 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: UART Data (UARTDR), offset 0x000 ............................................................................... 613 UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 615 UART Flag (UARTFR), offset 0x018 ................................................................................ 618 UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 621 UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 622 UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 623 UART Line Control (UARTLCRH), offset 0x02C ............................................................... 624 UART Control (UARTCTL), offset 0x030 ......................................................................... 626 UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 630 UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 632 UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 636 UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 639 UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 642 UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 644 UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 645 UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 646 UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 647 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 648 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 649 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 650 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 651 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 652 UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 653 UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 654 UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 655 UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 656 UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 657 UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 658 24 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 29: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 659 Synchronous Serial Interface (SSI) ............................................................................................ 660 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 675 SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 677 SSI Data (SSIDR), offset 0x008 ...................................................................................... 679 SSI Status (SSISR), offset 0x00C ................................................................................... 680 SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 682 SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 683 SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 684 SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 686 SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 688 SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 689 SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 690 SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 691 SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 692 SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 693 SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 694 SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 695 SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 696 SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 697 SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 698 SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 699 SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 700 SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 701 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 702 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 719 I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 720 I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 724 I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 725 I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 726 I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 727 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 728 I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 729 I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 730 I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 731 I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 732 I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 734 I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 735 I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 736 I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 737 I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 738 Inter-Integrated Circuit Sound (I2S) Interface ............................................................................ 739 Register 1: Register 2: Register 3: Register 4: I2S Transmit FIFO Data (I2STXFIFO), offset 0x000 .......................................................... I2S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ...................................... I2S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... I2S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ July 22, 2011 752 753 754 756 25 Texas Instruments-Production Data Table of Contents Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: I2S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 757 I2S Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 758 I2S Receive FIFO Data (I2SRXFIFO), offset 0x800 .......................................................... 759 I2S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ...................................... 760 I2S Receive Module Configuration (I2SRXCFG), offset 0x808 ........................................... 761 I2S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ......................................................... 764 I2S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 ..................................... 765 I2S Receive FIFO Level (I2SRXLEV), offset 0x818 ........................................................... 766 I2S Module Configuration (I2SCFG), offset 0xC00 ............................................................ 767 I2S Interrupt Mask (I2SIM), offset 0xC10 ......................................................................... 769 I2S Raw Interrupt Status (I2SRIS), offset 0xC14 ............................................................... 771 I2S Masked Interrupt Status (I2SMIS), offset 0xC18 ......................................................... 773 I2S Interrupt Clear (I2SIC), offset 0xC1C ......................................................................... 775 Controller Area Network (CAN) Module ..................................................................................... 776 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: CAN Control (CANCTL), offset 0x000 ............................................................................. 798 CAN Status (CANSTS), offset 0x004 ............................................................................... 800 CAN Error Counter (CANERR), offset 0x008 ................................................................... 803 CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 804 CAN Interrupt (CANINT), offset 0x010 ............................................................................. 805 CAN Test (CANTST), offset 0x014 .................................................................................. 806 CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 808 CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 809 CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 809 CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 810 CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 810 CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 813 CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 813 CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 814 CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 814 CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 816 CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 816 CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 817 CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 817 CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 819 CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 819 CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 822 CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 822 CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 822 CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 822 CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 822 CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 822 CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 822 CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 822 CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 823 CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 823 CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 824 CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 824 26 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 34: Register 35: Register 36: Register 37: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 825 825 826 826 Ethernet Controller ...................................................................................................................... 827 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... Ethernet MAC Management Address (MACMADD), offset 0x028 ...................................... Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... Ethernet MAC Timer Support (MACTS), offset 0x03C ...................................................... 840 843 845 847 849 851 852 853 855 856 857 858 859 860 861 862 Universal Serial Bus (USB) Controller ....................................................................................... 863 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: USB Device Functional Address (USBFADDR), offset 0x000 ............................................ 891 USB Power (USBPOWER), offset 0x001 ......................................................................... 892 USB Transmit Interrupt Status (USBTXIS), offset 0x002 ................................................... 895 USB Receive Interrupt Status (USBRXIS), offset 0x004 ................................................... 897 USB Transmit Interrupt Enable (USBTXIE), offset 0x006 .................................................. 899 USB Receive Interrupt Enable (USBRXIE), offset 0x008 .................................................. 901 USB General Interrupt Status (USBIS), offset 0x00A ........................................................ 903 USB Interrupt Enable (USBIE), offset 0x00B .................................................................... 906 USB Frame Value (USBFRAME), offset 0x00C ................................................................ 909 USB Endpoint Index (USBEPIDX), offset 0x00E .............................................................. 910 USB Test Mode (USBTEST), offset 0x00F ....................................................................... 911 USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 ............................................................. 913 USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 ............................................................. 913 USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 ............................................................. 913 USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C ............................................................ 913 USB FIFO Endpoint 4 (USBFIFO4), offset 0x030 ............................................................. 913 USB FIFO Endpoint 5 (USBFIFO5), offset 0x034 ............................................................. 913 USB FIFO Endpoint 6 (USBFIFO6), offset 0x038 ............................................................. 913 USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C ............................................................ 913 USB FIFO Endpoint 8 (USBFIFO8), offset 0x040 ............................................................. 913 USB FIFO Endpoint 9 (USBFIFO9), offset 0x044 ............................................................. 913 USB FIFO Endpoint 10 (USBFIFO10), offset 0x048 ......................................................... 913 USB FIFO Endpoint 11 (USBFIFO11), offset 0x04C ......................................................... 913 USB FIFO Endpoint 12 (USBFIFO12), offset 0x050 ......................................................... 913 USB FIFO Endpoint 13 (USBFIFO13), offset 0x054 ......................................................... 913 USB FIFO Endpoint 14 (USBFIFO14), offset 0x058 ......................................................... 913 July 22, 2011 27 Texas Instruments-Production Data Table of Contents Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: Register 69: Register 70: Register 71: Register 72: Register 73: Register 74: USB FIFO Endpoint 15 (USBFIFO15), offset 0x05C ......................................................... 913 USB Device Control (USBDEVCTL), offset 0x060 ............................................................ 915 USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 ................................. 917 USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 .................................. 917 USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 ................................. 918 USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 .................................. 918 USB Connect Timing (USBCONTIM), offset 0x07A .......................................................... 919 USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B .............................................. 920 USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D ...... 921 USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E ...... 922 USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 ........... 923 USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 ........... 923 USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 ........... 923 USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 ........... 923 USB Transmit Functional Address Endpoint 4 (USBTXFUNCADDR4), offset 0x0A0 ........... 923 USB Transmit Functional Address Endpoint 5 (USBTXFUNCADDR5), offset 0x0A8 ........... 923 USB Transmit Functional Address Endpoint 6 (USBTXFUNCADDR6), offset 0x0B0 ........... 923 USB Transmit Functional Address Endpoint 7 (USBTXFUNCADDR7), offset 0x0B8 ........... 923 USB Transmit Functional Address Endpoint 8 (USBTXFUNCADDR8), offset 0x0C0 .......... 923 USB Transmit Functional Address Endpoint 9 (USBTXFUNCADDR9), offset 0x0C8 .......... 923 USB Transmit Functional Address Endpoint 10 (USBTXFUNCADDR10), offset 0x0D0 ....... 923 USB Transmit Functional Address Endpoint 11 (USBTXFUNCADDR11), offset 0x0D8 ....... 923 USB Transmit Functional Address Endpoint 12 (USBTXFUNCADDR12), offset 0x0E0 ....... 923 USB Transmit Functional Address Endpoint 13 (USBTXFUNCADDR13), offset 0x0E8 ....... 923 USB Transmit Functional Address Endpoint 14 (USBTXFUNCADDR14), offset 0x0F0 ....... 923 USB Transmit Functional Address Endpoint 15 (USBTXFUNCADDR15), offset 0x0F8 ....... 923 USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 ...................... 925 USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A ...................... 925 USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 ...................... 925 USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A ...................... 925 USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4), offset 0x0A2 ...................... 925 USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5), offset 0x0AA ...................... 925 USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6), offset 0x0B2 ...................... 925 USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7), offset 0x0BA ...................... 925 USB Transmit Hub Address Endpoint 8 (USBTXHUBADDR8), offset 0x0C2 ...................... 925 USB Transmit Hub Address Endpoint 9 (USBTXHUBADDR9), offset 0x0CA ..................... 925 USB Transmit Hub Address Endpoint 10 (USBTXHUBADDR10), offset 0x0D2 .................. 925 USB Transmit Hub Address Endpoint 11 (USBTXHUBADDR11), offset 0x0DA .................. 925 USB Transmit Hub Address Endpoint 12 (USBTXHUBADDR12), offset 0x0E2 .................. 925 USB Transmit Hub Address Endpoint 13 (USBTXHUBADDR13), offset 0x0EA .................. 925 USB Transmit Hub Address Endpoint 14 (USBTXHUBADDR14), offset 0x0F2 .................. 925 USB Transmit Hub Address Endpoint 15 (USBTXHUBADDR15), offset 0x0FA .................. 925 USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 ............................. 927 USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B ............................ 927 USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 ............................. 927 USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B ............................ 927 USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset 0x0A3 ............................ 927 USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset 0x0AB ............................ 927 28 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 75: Register 76: Register 77: Register 78: Register 79: Register 80: Register 81: Register 82: Register 83: Register 84: Register 85: Register 86: Register 87: Register 88: Register 89: Register 90: Register 91: Register 92: Register 93: Register 94: Register 95: Register 96: Register 97: Register 98: Register 99: Register 100: Register 101: Register 102: Register 103: Register 104: Register 105: Register 106: Register 107: Register 108: Register 109: Register 110: Register 111: Register 112: Register 113: Register 114: Register 115: Register 116: Register 117: Register 118: Register 119: Register 120: Register 121: Register 122: USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset 0x0B3 ............................ 927 USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset 0x0BB ............................ 927 USB Transmit Hub Port Endpoint 8 (USBTXHUBPORT8), offset 0x0C3 ............................ 927 USB Transmit Hub Port Endpoint 9 (USBTXHUBPORT9), offset 0x0CB ............................ 927 USB Transmit Hub Port Endpoint 10 (USBTXHUBPORT10), offset 0x0D3 ........................ 927 USB Transmit Hub Port Endpoint 11 (USBTXHUBPORT11), offset 0x0DB ......................... 927 USB Transmit Hub Port Endpoint 12 (USBTXHUBPORT12), offset 0x0E3 ......................... 927 USB Transmit Hub Port Endpoint 13 (USBTXHUBPORT13), offset 0x0EB ........................ 927 USB Transmit Hub Port Endpoint 14 (USBTXHUBPORT14), offset 0x0F3 ......................... 927 USB Transmit Hub Port Endpoint 15 (USBTXHUBPORT15), offset 0x0FB ........................ 927 USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C ........... 929 USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 ........... 929 USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C ........... 929 USB Receive Functional Address Endpoint 4 (USBRXFUNCADDR4), offset 0x0A4 ........... 929 USB Receive Functional Address Endpoint 5 (USBRXFUNCADDR5), offset 0x0AC .......... 929 USB Receive Functional Address Endpoint 6 (USBRXFUNCADDR6), offset 0x0B4 ........... 929 USB Receive Functional Address Endpoint 7 (USBRXFUNCADDR7), offset 0x0BC .......... 929 USB Receive Functional Address Endpoint 8 (USBRXFUNCADDR8), offset 0x0C4 ........... 929 USB Receive Functional Address Endpoint 9 (USBRXFUNCADDR9), offset 0x0CC .......... 929 USB Receive Functional Address Endpoint 10 (USBRXFUNCADDR10), offset 0x0D4 ....... 929 USB Receive Functional Address Endpoint 11 (USBRXFUNCADDR11), offset 0x0DC ....... 929 USB Receive Functional Address Endpoint 12 (USBRXFUNCADDR12), offset 0x0E4 ....... 929 USB Receive Functional Address Endpoint 13 (USBRXFUNCADDR13), offset 0x0EC ....... 929 USB Receive Functional Address Endpoint 14 (USBRXFUNCADDR14), offset 0x0F4 ....... 929 USB Receive Functional Address Endpoint 15 (USBRXFUNCADDR15), offset 0x0FC ....... 929 USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E ...................... 931 USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 ....................... 931 USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E ...................... 931 USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4), offset 0x0A6 ...................... 931 USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5), offset 0x0AE ...................... 931 USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6), offset 0x0B6 ...................... 931 USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7), offset 0x0BE ...................... 931 USB Receive Hub Address Endpoint 8 (USBRXHUBADDR8), offset 0x0C6 ...................... 931 USB Receive Hub Address Endpoint 9 (USBRXHUBADDR9), offset 0x0CE ...................... 931 USB Receive Hub Address Endpoint 10 (USBRXHUBADDR10), offset 0x0D6 ................... 931 USB Receive Hub Address Endpoint 11 (USBRXHUBADDR11), offset 0x0DE ................... 931 USB Receive Hub Address Endpoint 12 (USBRXHUBADDR12), offset 0x0E6 ................... 931 USB Receive Hub Address Endpoint 13 (USBRXHUBADDR13), offset 0x0EE .................. 931 USB Receive Hub Address Endpoint 14 (USBRXHUBADDR14), offset 0x0F6 ................... 931 USB Receive Hub Address Endpoint 15 (USBRXHUBADDR15), offset 0x0FE ................... 931 USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F ............................. 933 USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 ............................. 933 USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F ............................. 933 USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset 0x0A7 ............................. 933 USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset 0x0AF ............................. 933 USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset 0x0B7 ............................. 933 USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset 0x0BF ............................. 933 USB Receive Hub Port Endpoint 8 (USBRXHUBPORT8), offset 0x0C7 ............................. 933 July 22, 2011 29 Texas Instruments-Production Data Table of Contents Register 123: Register 124: Register 125: Register 126: Register 127: Register 128: Register 129: Register 130: Register 131: Register 132: Register 133: Register 134: Register 135: Register 136: Register 137: Register 138: Register 139: Register 140: Register 141: Register 142: Register 143: Register 144: Register 145: Register 146: Register 147: Register 148: Register 149: Register 150: Register 151: Register 152: Register 153: Register 154: Register 155: Register 156: Register 157: Register 158: Register 159: Register 160: Register 161: Register 162: Register 163: Register 164: Register 165: Register 166: Register 167: Register 168: Register 169: Register 170: USB Receive Hub Port Endpoint 9 (USBRXHUBPORT9), offset 0x0CF ............................ 933 USB Receive Hub Port Endpoint 10 (USBRXHUBPORT10), offset 0x0D7 ......................... 933 USB Receive Hub Port Endpoint 11 (USBRXHUBPORT11), offset 0x0DF ......................... 933 USB Receive Hub Port Endpoint 12 (USBRXHUBPORT12), offset 0x0E7 ......................... 933 USB Receive Hub Port Endpoint 13 (USBRXHUBPORT13), offset 0x0EF ......................... 933 USB Receive Hub Port Endpoint 14 (USBRXHUBPORT14), offset 0x0F7 ......................... 933 USB Receive Hub Port Endpoint 15 (USBRXHUBPORT15), offset 0x0FF ......................... 933 USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 .......................... 935 USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 .......................... 935 USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 .......................... 935 USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset 0x140 .......................... 935 USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset 0x150 .......................... 935 USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset 0x160 .......................... 935 USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset 0x170 .......................... 935 USB Maximum Transmit Data Endpoint 8 (USBTXMAXP8), offset 0x180 .......................... 935 USB Maximum Transmit Data Endpoint 9 (USBTXMAXP9), offset 0x190 .......................... 935 USB Maximum Transmit Data Endpoint 10 (USBTXMAXP10), offset 0x1A0 ...................... 935 USB Maximum Transmit Data Endpoint 11 (USBTXMAXP11), offset 0x1B0 ....................... 935 USB Maximum Transmit Data Endpoint 12 (USBTXMAXP12), offset 0x1C0 ...................... 935 USB Maximum Transmit Data Endpoint 13 (USBTXMAXP13), offset 0x1D0 ...................... 935 USB Maximum Transmit Data Endpoint 14 (USBTXMAXP14), offset 0x1E0 ...................... 935 USB Maximum Transmit Data Endpoint 15 (USBTXMAXP15), offset 0x1F0 ...................... 935 USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 ................................. 937 USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 ............................... 941 USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 ................................... 943 USB Type Endpoint 0 (USBTYPE0), offset 0x10A ............................................................ 944 USB NAK Limit (USBNAKLMT), offset 0x10B .................................................................. 945 USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 ............... 946 USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 ............... 946 USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 ............... 946 USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142 ............... 946 USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152 ............... 946 USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162 ............... 946 USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172 ............... 946 USB Transmit Control and Status Endpoint 8 Low (USBTXCSRL8), offset 0x182 ............... 946 USB Transmit Control and Status Endpoint 9 Low (USBTXCSRL9), offset 0x192 ............... 946 USB Transmit Control and Status Endpoint 10 Low (USBTXCSRL10), offset 0x1A2 ........... 946 USB Transmit Control and Status Endpoint 11 Low (USBTXCSRL11), offset 0x1B2 ........... 946 USB Transmit Control and Status Endpoint 12 Low (USBTXCSRL12), offset 0x1C2 .......... 946 USB Transmit Control and Status Endpoint 13 Low (USBTXCSRL13), offset 0x1D2 .......... 946 USB Transmit Control and Status Endpoint 14 Low (USBTXCSRL14), offset 0x1E2 ........... 946 USB Transmit Control and Status Endpoint 15 Low (USBTXCSRL15), offset 0x1F2 ........... 946 USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 .............. 951 USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 ............. 951 USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 ............. 951 USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143 ............. 951 USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153 ............. 951 USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163 ............. 951 30 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 171: Register 172: Register 173: Register 174: Register 175: Register 176: Register 177: Register 178: Register 179: Register 180: Register 181: Register 182: Register 183: Register 184: Register 185: Register 186: Register 187: Register 188: Register 189: Register 190: Register 191: Register 192: Register 193: Register 194: Register 195: Register 196: Register 197: Register 198: Register 199: Register 200: Register 201: Register 202: Register 203: Register 204: Register 205: Register 206: Register 207: Register 208: Register 209: Register 210: Register 211: Register 212: Register 213: Register 214: Register 215: Register 216: Register 217: Register 218: USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173 ............. 951 USB Transmit Control and Status Endpoint 8 High (USBTXCSRH8), offset 0x183 ............. 951 USB Transmit Control and Status Endpoint 9 High (USBTXCSRH9), offset 0x193 ............. 951 USB Transmit Control and Status Endpoint 10 High (USBTXCSRH10), offset 0x1A3 ......... 951 USB Transmit Control and Status Endpoint 11 High (USBTXCSRH11), offset 0x1B3 .......... 951 USB Transmit Control and Status Endpoint 12 High (USBTXCSRH12), offset 0x1C3 ......... 951 USB Transmit Control and Status Endpoint 13 High (USBTXCSRH13), offset 0x1D3 ......... 951 USB Transmit Control and Status Endpoint 14 High (USBTXCSRH14), offset 0x1E3 ......... 951 USB Transmit Control and Status Endpoint 15 High (USBTXCSRH15), offset 0x1F3 ......... 951 USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 ........................... 955 USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 ........................... 955 USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 ........................... 955 USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144 ........................... 955 USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154 ........................... 955 USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164 ........................... 955 USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174 ........................... 955 USB Maximum Receive Data Endpoint 8 (USBRXMAXP8), offset 0x184 ........................... 955 USB Maximum Receive Data Endpoint 9 (USBRXMAXP9), offset 0x194 ........................... 955 USB Maximum Receive Data Endpoint 10 (USBRXMAXP10), offset 0x1A4 ....................... 955 USB Maximum Receive Data Endpoint 11 (USBRXMAXP11), offset 0x1B4 ....................... 955 USB Maximum Receive Data Endpoint 12 (USBRXMAXP12), offset 0x1C4 ...................... 955 USB Maximum Receive Data Endpoint 13 (USBRXMAXP13), offset 0x1D4 ...................... 955 USB Maximum Receive Data Endpoint 14 (USBRXMAXP14), offset 0x1E4 ....................... 955 USB Maximum Receive Data Endpoint 15 (USBRXMAXP15), offset 0x1F4 ....................... 955 USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 ............... 957 USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 ............... 957 USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 ............... 957 USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146 ............... 957 USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156 ............... 957 USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166 ............... 957 USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 ............... 957 USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8), offset 0x186 ............... 957 USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9), offset 0x196 ............... 957 USB Receive Control and Status Endpoint 10 Low (USBRXCSRL10), offset 0x1A6 ........... 957 USB Receive Control and Status Endpoint 11 Low (USBRXCSRL11), offset 0x1B6 ........... 957 USB Receive Control and Status Endpoint 12 Low (USBRXCSRL12), offset 0x1C6 ........... 957 USB Receive Control and Status Endpoint 13 Low (USBRXCSRL13), offset 0x1D6 ........... 957 USB Receive Control and Status Endpoint 14 Low (USBRXCSRL14), offset 0x1E6 ........... 957 USB Receive Control and Status Endpoint 15 Low (USBRXCSRL15), offset 0x1F6 ........... 957 USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 .............. 962 USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 .............. 962 USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 .............. 962 USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147 .............. 962 USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157 .............. 962 USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167 .............. 962 USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177 .............. 962 USB Receive Control and Status Endpoint 8 High (USBRXCSRH8), offset 0x187 .............. 962 USB Receive Control and Status Endpoint 9 High (USBRXCSRH9), offset 0x197 .............. 962 July 22, 2011 31 Texas Instruments-Production Data Table of Contents Register 219: Register 220: Register 221: Register 222: Register 223: Register 224: Register 225: Register 226: Register 227: Register 228: Register 229: Register 230: Register 231: Register 232: Register 233: Register 234: Register 235: Register 236: Register 237: Register 238: Register 239: Register 240: Register 241: Register 242: Register 243: Register 244: Register 245: Register 246: Register 247: Register 248: Register 249: Register 250: Register 251: Register 252: Register 253: Register 254: Register 255: Register 256: Register 257: Register 258: Register 259: Register 260: Register 261: Register 262: Register 263: Register 264: Register 265: Register 266: USB Receive Control and Status Endpoint 10 High (USBRXCSRH10), offset 0x1A7 .......... 962 USB Receive Control and Status Endpoint 11 High (USBRXCSRH11), offset 0x1B7 .......... 962 USB Receive Control and Status Endpoint 12 High (USBRXCSRH12), offset 0x1C7 ......... 962 USB Receive Control and Status Endpoint 13 High (USBRXCSRH13), offset 0x1D7 ......... 962 USB Receive Control and Status Endpoint 14 High (USBRXCSRH14), offset 0x1E7 .......... 962 USB Receive Control and Status Endpoint 15 High (USBRXCSRH15), offset 0x1F7 .......... 962 USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 .............................. 967 USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 .............................. 967 USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 .............................. 967 USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148 .............................. 967 USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158 .............................. 967 USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168 .............................. 967 USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178 .............................. 967 USB Receive Byte Count Endpoint 8 (USBRXCOUNT8), offset 0x188 .............................. 967 USB Receive Byte Count Endpoint 9 (USBRXCOUNT9), offset 0x198 .............................. 967 USB Receive Byte Count Endpoint 10 (USBRXCOUNT10), offset 0x1A8 .......................... 967 USB Receive Byte Count Endpoint 11 (USBRXCOUNT11), offset 0x1B8 ........................... 967 USB Receive Byte Count Endpoint 12 (USBRXCOUNT12), offset 0x1C8 .......................... 967 USB Receive Byte Count Endpoint 13 (USBRXCOUNT13), offset 0x1D8 .......................... 967 USB Receive Byte Count Endpoint 14 (USBRXCOUNT14), offset 0x1E8 .......................... 967 USB Receive Byte Count Endpoint 15 (USBRXCOUNT15), offset 0x1F8 .......................... 967 USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ................... 969 USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ................... 969 USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ................... 969 USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4), offset 0x14A ................... 969 USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5), offset 0x15A ................... 969 USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6), offset 0x16A ................... 969 USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7), offset 0x17A ................... 969 USB Host Transmit Configure Type Endpoint 8 (USBTXTYPE8), offset 0x18A ................... 969 USB Host Transmit Configure Type Endpoint 9 (USBTXTYPE9), offset 0x19A ................... 969 USB Host Transmit Configure Type Endpoint 10 (USBTXTYPE10), offset 0x1AA ............... 969 USB Host Transmit Configure Type Endpoint 11 (USBTXTYPE11), offset 0x1BA ............... 969 USB Host Transmit Configure Type Endpoint 12 (USBTXTYPE12), offset 0x1CA .............. 969 USB Host Transmit Configure Type Endpoint 13 (USBTXTYPE13), offset 0x1DA .............. 969 USB Host Transmit Configure Type Endpoint 14 (USBTXTYPE14), offset 0x1EA ............... 969 USB Host Transmit Configure Type Endpoint 15 (USBTXTYPE15), offset 0x1FA ............... 969 USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B ....................... 971 USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B ....................... 971 USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B ....................... 971 USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4), offset 0x14B ....................... 971 USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5), offset 0x15B ....................... 971 USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6), offset 0x16B ....................... 971 USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7), offset 0x17B ....................... 971 USB Host Transmit Interval Endpoint 8 (USBTXINTERVAL8), offset 0x18B ....................... 971 USB Host Transmit Interval Endpoint 9 (USBTXINTERVAL9), offset 0x19B ....................... 971 USB Host Transmit Interval Endpoint 10 (USBTXINTERVAL10), offset 0x1AB ................... 971 USB Host Transmit Interval Endpoint 11 (USBTXINTERVAL11), offset 0x1BB ................... 971 USB Host Transmit Interval Endpoint 12 (USBTXINTERVAL12), offset 0x1CB ................... 971 32 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 267: Register 268: Register 269: Register 270: Register 271: Register 272: Register 273: Register 274: Register 275: Register 276: Register 277: Register 278: Register 279: Register 280: Register 281: Register 282: Register 283: Register 284: Register 285: Register 286: Register 287: Register 288: Register 289: Register 290: Register 291: Register 292: Register 293: Register 294: Register 295: Register 296: Register 297: Register 298: Register 299: Register 300: Register 301: Register 302: Register 303: Register 304: Register 305: Register 306: Register 307: USB Host Transmit Interval Endpoint 13 (USBTXINTERVAL13), offset 0x1DB ................... 971 USB Host Transmit Interval Endpoint 14 (USBTXINTERVAL14), offset 0x1EB ................... 971 USB Host Transmit Interval Endpoint 15 (USBTXINTERVAL15), offset 0x1FB ................... 971 USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................... 973 USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................... 973 USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ................... 973 USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4), offset 0x14C ................... 973 USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5), offset 0x15C ................... 973 USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6), offset 0x16C ................... 973 USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7), offset 0x17C ................... 973 USB Host Configure Receive Type Endpoint 8 (USBRXTYPE8), offset 0x18C ................... 973 USB Host Configure Receive Type Endpoint 9 (USBRXTYPE9), offset 0x19C ................... 973 USB Host Configure Receive Type Endpoint 10 (USBRXTYPE10), offset 0x1AC ............... 973 USB Host Configure Receive Type Endpoint 11 (USBRXTYPE11), offset 0x1BC ............... 973 USB Host Configure Receive Type Endpoint 12 (USBRXTYPE12), offset 0x1CC ............... 973 USB Host Configure Receive Type Endpoint 13 (USBRXTYPE13), offset 0x1DC ............... 973 USB Host Configure Receive Type Endpoint 14 (USBRXTYPE14), offset 0x1EC ............... 973 USB Host Configure Receive Type Endpoint 15 (USBRXTYPE15), offset 0x1FC ............... 973 USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D ............. 975 USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ............ 975 USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ............ 975 USB Host Receive Polling Interval Endpoint 4 (USBRXINTERVAL4), offset 0x14D ............ 975 USB Host Receive Polling Interval Endpoint 5 (USBRXINTERVAL5), offset 0x15D ............ 975 USB Host Receive Polling Interval Endpoint 6 (USBRXINTERVAL6), offset 0x16D ............ 975 USB Host Receive Polling Interval Endpoint 7 (USBRXINTERVAL7), offset 0x17D ............ 975 USB Host Receive Polling Interval Endpoint 8 (USBRXINTERVAL8), offset 0x18D ............ 975 USB Host Receive Polling Interval Endpoint 9 (USBRXINTERVAL9), offset 0x19D ............ 975 USB Host Receive Polling Interval Endpoint 10 (USBRXINTERVAL10), offset 0x1AD ........ 975 USB Host Receive Polling Interval Endpoint 11 (USBRXINTERVAL11), offset 0x1BD ......... 975 USB Host Receive Polling Interval Endpoint 12 (USBRXINTERVAL12), offset 0x1CD ........ 975 USB Host Receive Polling Interval Endpoint 13 (USBRXINTERVAL13), offset 0x1DD ........ 975 USB Host Receive Polling Interval Endpoint 14 (USBRXINTERVAL14), offset 0x1ED ........ 975 USB Host Receive Polling Interval Endpoint 15 (USBRXINTERVAL15), offset 0x1FD ........ 975 USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset 0x304 ........................................................................................................................... 977 USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset 0x308 ........................................................................................................................... 977 USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset 0x30C ........................................................................................................................... 977 USB Request Packet Count in Block Transfer Endpoint 4 (USBRQPKTCOUNT4), offset 0x310 ........................................................................................................................... 977 USB Request Packet Count in Block Transfer Endpoint 5 (USBRQPKTCOUNT5), offset 0x314 ........................................................................................................................... 977 USB Request Packet Count in Block Transfer Endpoint 6 (USBRQPKTCOUNT6), offset 0x318 ........................................................................................................................... 977 USB Request Packet Count in Block Transfer Endpoint 7 (USBRQPKTCOUNT7), offset 0x31C ........................................................................................................................... 977 USB Request Packet Count in Block Transfer Endpoint 8 (USBRQPKTCOUNT8), offset 0x320 ........................................................................................................................... 977 July 22, 2011 33 Texas Instruments-Production Data Table of Contents Register 308: USB Request Packet Count in Block Transfer Endpoint 9 (USBRQPKTCOUNT9), offset 0x324 ........................................................................................................................... 977 Register 309: USB Request Packet Count in Block Transfer Endpoint 10 (USBRQPKTCOUNT10), offset 0x328 ........................................................................................................................... 977 Register 310: USB Request Packet Count in Block Transfer Endpoint 11 (USBRQPKTCOUNT11), offset 0x32C ........................................................................................................................... 977 Register 311: USB Request Packet Count in Block Transfer Endpoint 12 (USBRQPKTCOUNT12), offset 0x330 ........................................................................................................................... 977 Register 312: USB Request Packet Count in Block Transfer Endpoint 13 (USBRQPKTCOUNT13), offset 0x334 ........................................................................................................................... 977 Register 313: USB Request Packet Count in Block Transfer Endpoint 14 (USBRQPKTCOUNT14), offset 0x338 ........................................................................................................................... 977 Register 314: USB Request Packet Count in Block Transfer Endpoint 15 (USBRQPKTCOUNT15), offset 0x33C ........................................................................................................................... 977 Register 315: USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ............. 979 Register 316: USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 ............ 981 Register 317: USB External Power Control (USBEPC), offset 0x400 ...................................................... 983 Register 318: USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ................. 986 Register 319: USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 ............................ 987 Register 320: USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ......... 988 Register 321: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 ............................ 989 Register 322: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ....................................... 990 Register 323: USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................... 991 Register 324: USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................... 992 Register 325: USB VBUS Droop Control (USBVDC), offset 0x430 ......................................................... 993 Register 326: USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS), offset 0x434 .................... 994 Register 327: USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset 0x438 ............................... 995 Register 328: USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC), offset 0x43C ............ 996 Register 329: USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset 0x444 .............................. 997 Register 330: USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448 ......................................... 998 Register 331: USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C ...................... 999 Register 332: USB DMA Select (USBDMASEL), offset 0x450 .............................................................. 1000 Analog Comparators ................................................................................................................. 1002 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1008 1009 1010 1011 1012 1012 1013 1013 Pulse Width Modulator (PWM) .................................................................................................. 1015 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: PWM Master Control (PWMCTL), offset 0x000 .............................................................. PWM Time Base Sync (PWMSYNC), offset 0x004 ......................................................... PWM Output Enable (PWMENABLE), offset 0x008 ........................................................ PWM Output Inversion (PWMINVERT), offset 0x00C ..................................................... PWM Output Fault (PWMFAULT), offset 0x010 .............................................................. PWM Interrupt Enable (PWMINTEN), offset 0x014 ......................................................... 34 1030 1031 1032 1034 1036 1038 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ...................................................... 1040 PWM Interrupt Status and Clear (PWMISC), offset 0x01C .............................................. 1042 PWM Status (PWMSTATUS), offset 0x020 .................................................................... 1044 PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ........................................... 1046 PWM Enable Update (PWMENUPD), offset 0x028 ......................................................... 1048 PWM0 Control (PWM0CTL), offset 0x040 ...................................................................... 1051 PWM1 Control (PWM1CTL), offset 0x080 ...................................................................... 1051 PWM2 Control (PWM2CTL), offset 0x0C0 ..................................................................... 1051 PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 ................................... 1056 PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 ................................... 1056 PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 ................................... 1056 PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 ................................................... 1059 PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 ................................................... 1059 PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 .................................................. 1059 PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C .......................................... 1061 PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C .......................................... 1061 PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC .......................................... 1061 PWM0 Load (PWM0LOAD), offset 0x050 ...................................................................... 1063 PWM1 Load (PWM1LOAD), offset 0x090 ...................................................................... 1063 PWM2 Load (PWM2LOAD), offset 0x0D0 ...................................................................... 1063 PWM0 Counter (PWM0COUNT), offset 0x054 ............................................................... 1064 PWM1 Counter (PWM1COUNT), offset 0x094 ............................................................... 1064 PWM2 Counter (PWM2COUNT), offset 0x0D4 .............................................................. 1064 PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................ 1065 PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................ 1065 PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................ 1065 PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................ 1066 PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................ 1066 PWM2 Compare B (PWM2CMPB), offset 0x0DC ........................................................... 1066 PWM0 Generator A Control (PWM0GENA), offset 0x060 ............................................... 1067 PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ............................................... 1067 PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ............................................... 1067 PWM0 Generator B Control (PWM0GENB), offset 0x064 ............................................... 1070 PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ............................................... 1070 PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ............................................... 1070 PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ............................................... 1073 PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ............................................... 1073 PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ............................................... 1073 PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................ 1074 PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................ 1074 PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................ 1074 PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................ 1075 PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................ 1075 PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................ 1075 PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 .................................................. 1076 PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 .................................................. 1076 PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 .................................................. 1076 PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078 .................................................. 1078 July 22, 2011 35 Texas Instruments-Production Data Table of Contents Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: Register 69: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 .................................................. 1078 PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 .................................................. 1078 PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C ................................... 1081 PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC ................................... 1081 PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC ................................... 1081 PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 .......................................... 1082 PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880 .......................................... 1082 PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900 .......................................... 1082 PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980 .......................................... 1082 PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 ................................................... 1083 PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 ................................................... 1083 PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 ................................................... 1083 PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808 ................................................... 1085 PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888 ................................................... 1085 PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908 ................................................... 1085 Quadrature Encoder Interface (QEI) ........................................................................................ 1088 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: QEI Control (QEICTL), offset 0x000 .............................................................................. QEI Status (QEISTAT), offset 0x004 .............................................................................. QEI Position (QEIPOS), offset 0x008 ............................................................................ QEI Maximum Position (QEIMAXPOS), offset 0x00C ..................................................... QEI Timer Load (QEILOAD), offset 0x010 ..................................................................... QEI Timer (QEITIME), offset 0x014 ............................................................................... QEI Velocity Counter (QEICOUNT), offset 0x018 ........................................................... QEI Velocity (QEISPEED), offset 0x01C ........................................................................ QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................. QEI Raw Interrupt Status (QEIRIS), offset 0x024 ........................................................... QEI Interrupt Status and Clear (QEIISC), offset 0x028 ................................................... 36 1095 1098 1099 1100 1101 1102 1103 1104 1105 1107 1109 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Revision History The revision history table notes changes made between the indicated revisions of the LM3S9L71 data sheet. Table 1. Revision History Date Revision July 2011 9970 Description ■ Corrected "Reset Sources" table. ■ Added missing PICAL (PIOSC Calibrate) bit to DC4 register. ■ Added Important Note that RCC register must be written before RCC2 register. ■ In Hibernation Module chapter, deleted section "Special Considerations When Using a 4.194304-MHz Crystal" as the content was added to the errata document. ■ Added a note that all GPIO signals are 5-V tolerant when configured as inputs except for PB0 and PB1, which are limited to 3.6 V. ■ Note that the state of the HSE bit in the UARTCTL register has no effect on clock generation in ISO 7816 smart card mode (when the SMART bit in the UARTCTL register is set). ■ Corrected LIN Mode bit names in UART Interrupt Clear (UARTICR) register. ■ Corrected pin number for RST in table "Connections for Unused Signals" (other pin tables were correct). ■ In the "Operating Characteristics" chapter: – In the "Thermal Characteristics" table, the Thermal resistance value was changed. – In the "ESD Absolute Maximum Ratings" table, the VESDCDM parameter was changed and the VESDMM parameter was deleted. ■ The "Electrical Characteristics" chapter was reorganized by module. In addition, some of the Recommended DC Operating Conditions, LDO Regulator, Clock, GPIO, ADC, and SSI characteristics were finalized. ■ Added missing ordering table. ■ Additional minor data sheet clarifications and corrections. July 22, 2011 37 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision March 2011 9538 January 2011 9161 Description ■ Clarified "Reset Control" section in the "System Control" chapter. ■ Corrected USB PLL speed in "Main Clock Tree" diagram. ■ Corrected reset value for DMA Channel Wait-on-Request Status (DMAWAITSTAT) register. ■ Corrected "GPIO Pins With Non-Zero Reset Values" table. ■ Clarified that that the timer reload only happens in periodic mode. ■ Clarified that only bit 0 in the Watchdog Control (WDTCTL) register is protected from writes once set. ■ Added "Sample Averaging Example" diagram to ADC chapter. ■ Corrected "SSI Timing for SPI Frame Format" figure. ■ In "Electrical Characteristics" chapter: – Deleted TPORMIN parameter from "Power Characteristics" table, and deleted corresponding diagram. – Added tADCSAMP sample time parameter to "ADC Characteristics" table. ■ Additional minor data sheet clarifications and corrections. ■ Clarified Main Oscillator verification circuit sequence. ■ Added note that there must be a delay of 3 system clocks after the module clock is enabled before any of that module's registers are accessed. ■ Corrected reset of Device Mode (DEVMOD) bitfield in USB General-Purpose Control and Status (USBGPCS) register. ■ Clarified initialization and configuration procedure in "Analog Comparators" chapter. ■ In Electrical Characteristics chapter: ■ – Added specification for maximum input voltage on a non-power pin when the microcontroller is unpowered (VNON parameter in Maximum Ratings table). – Replaced Preliminary Current Consumption Specifications with Nominal Power Consumption, Maximum Current Specifications, and Typical Current Consumption vs. Frequency sections. – Clarified Reset, and Power and Brown-out Characteristics and added a new specification for powering down before powering back up. – Added characteristics required when using an external regulator to provide power for VDDC. Additional minor data sheet clarifications and corrections. 38 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 1. Revision History (continued) Date Revision December 2010 8832 Description ■ Information on Advanced Encryption Standard (AES) cryptography tables and Cyclic Redundancy Check (CRC) error detection functionality was inadvertently omitted from some datasheets. This has been added. ■ In APINT register, changed bit name from SYSRESETREQ to SYSRESREQ. ■ Added DEBUG (Debug Priority) bit field to SYSPRI3 register. ■ Clarified Flash memory caution. ■ Restructured the General-Purpose Timer chapter to combine duplicated text. ■ Combined High and Low bit fields in GPTMTAILR, GPTMTAMATCHR, GPTMTAR, GPTMTAV, GPTMTBILR, GPTMTAMATCHR, GPTMTBR and GPTMTBV registers for compatibility with future releases. ■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported. ■ Added SSI master clock restriction that SSIClk cannot be faster than 25 MHz. ■ Changed I2C master and slave register base addresses and offsets to be relative to I2C module base, so register base and offsets were changed for all I2C slave registers. ■ In Electrical Characteristics chapter: – Added single-ended clock source input voltage values to "Recommended DC Operating Conditions" table. – Deleted Oscillation mode value from "MOSC Oscillator Input Characteristics" table. – Added TVDD2_3 supply voltage parameter to "Reset Characteristics" table. – Added "Power-On Reset and Voltage Parameters" timing diagram. July 22, 2011 39 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision September 2010 7794 Description ■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was added, including all the Cortex-M3 registers. ■ Changed register names to be consistent with StellarisWare names: the Cortex-M3 Interrupt Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register. ■ In the System Control chapter: – Corrected Reset Sources table (see Table 5-3 on page 193). – Added section "Special Considerations for Reset." ■ In the Internal Memory chapter: – Added clarification of instruction execution during Flash operations. – Deleted ROM Version (RMVER) register as it is not used. ■ Modified Figure 8-1 on page 397 and Figure 8-2 on page 398 to clarify operation of the GPIO inputs when used as an alternate function. ■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits wide, bits[7:0]. ■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode. ■ In CAN chapter, clarified CAN bit timing examples. ■ In Operating Characteristics chapter, corrected Thermal resistance (junction to ambient) value to 32. ■ In Electrical Characteristics chapter: – Added "Input voltage for a GPIO configured as an analog input" value to Table 25-1 on page 1190. – Added ILKG parameter (GPIO input leakage current) to Table 25-16 on page 1198. – Corrected reset timing in Table 25-5 on page 1194. – Specified Max value for VREFA in Table 25-18 on page 1200. – Corrected values for tCLKRF (SSIClk rise/fall time) in Table 25-20 on page 1200. – Added I2C Characteristics table (see Table 25-21 on page 1202). ■ Added dimensions for Tray and Tape and Reel shipping mediums. ® June 2010 7413 ■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32. June 2010 7299 ■ Removed 4.194304-MHz crystal as a source for the system clock and PLL. ■ Summarized ROM contents descriptions in the "Internal Memory" chapter and removed various ROM appendices. ■ Clarified DMA channel terminology: changed name of DMA Channel Alternate Select (DMACHALT) register to DMA Channel Assignment (DMACHASGN) register, changed CHALT bit field to CHASGN, and changed terminology from primary and alternate channels to primary and secondary channels. ■ In Signal Tables chapter, added table "Connections for Unused Signals." ■ In "Electrical Characteristics" chapter: – In "Reset Characteristics" table, corrected Supply voltage (VDD) rise time. – Clarified figure "SDRAM Initialization and Load Mode Register Timing". 40 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 1. Revision History (continued) Date Revision May 2010 7164 May 2010 March 2010 March 2010 7101 6983 6912 Description ■ Added data sheets for five new Stellaris® Tempest-class parts: LM3S1R26, LM3S1621, LM3S1B21, LM3S9781, and LM3S9B81. ■ Additional minor data sheet clarifications and corrections. ■ Added pin table "Possible Pin Assignments for Alternate Functions", which lists the signals based on number of possible pin assignments. This table can be used to plan how to configure the pins for a particular functionality. ■ Additional minor data sheet clarifications and corrections. ■ Extended TBRL bit field in GPTMTBR register. ■ Additional minor data sheet clarifications and corrections. ■ Renamed the USER_DBG register to the BOOTCFG register in the Internal Memory chapter. Added information on how to use a GPIO pin to force the ROM Boot Loader to execute on reset. ■ Added three figures to the ADC chapter on sample phase control. ■ Clarified configuration of USB0VBUS and USB0ID in OTG mode. July 22, 2011 41 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision February 2010 6790 Description ■ Added 108-ball BGA package. ■ In "System Control" chapter: – Clarified functional description for external reset and brown-out reset. – Clarified Debug Access Port operation after Sleep modes. – Corrected the reset value of the Run-Mode Clock Configuration 2 (RCC2) register. ■ In "Internal Memory" chapter, clarified wording on Flash memory access errors and added a section on interrupts to the Flash memory description. ■ Added clarification about timer operating modes and added register descriptions for the GPTM Timer n Prescale Match (GPTMTnPMR) registers. ■ Clarified register descriptions for GPTM Timer A Value (GPTMTAV) and GPTM Timer B Value (GPTMTBV) registers. ■ Corrected the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers. ■ Added ADC Sample Phase Control (ADCSPC) register at offset 0x24. ■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed field width to 7 bits. ■ In the "Controller Area Network" chapter, added clarification about reading from the CAN FIFO buffer and clarified packet timestamps functional description. ■ In the "Ethernet Controller" chapter: – Corrected the reset value and the LED1 bit positions of the Ethernet MAC LED Encoding (MACLED) register. – Added clarification about the use of the NPR field in the Ethernet MAC Number of Packets (MACNP) register. – Corrected reset values for Ethernet PHY Management Register 0 – Control (MR0) and Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5) registers. ■ Added Session Disconnect (DISCON) bit to the USB General Interrupt Status (USBIS) and USB Interrupt Enable (USBIE) registers. ■ Made these changes to the Operating Characteristics chapter: – Added storage temperature ratings to "Temperature Characteristics" table – Added "ESD Absolute Maximum Ratings" table ■ Made these changes to the Electrical Characteristics chapter: – In "Flash Memory Characteristics" table, corrected Mass erase time – Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) – In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time – Modified the preliminary current consumption specification for Run mode 1 and Deep-Sleep mode. – Added table entry for VDD3ON power consumption to Table 25-38 on page 1208. ■ Added additional DriverLib functions to appendix. 42 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 1. Revision History (continued) Date Revision October 2009 6458 Description ® ■ Released new 1000, 3000, 5000 and 9000 series Stellaris devices. ■ The IDCODE value was corrected to be 0x4BA0.0477. ■ Clarified that the NMISET bit in the ICSR register in the NVIC is also a source for NMI. ■ Clarified the use of the LDO. ■ To clarify clock operation, reorganized clocking section, changed the USEFRACT bit to the DIV400 bit and the FRACT bit to the SYSDIV2LSB bit in the RCC2 register, added tables, and rewrote descriptions. ■ Corrected bit description of the DSDIVORIDE field in the DSLPCLKCFG register. ■ Removed the DSFLASHCFG register at System Control offset 0x14C as it does not function correctly. ■ Removed the MAXADC1SPD and MAXADC0SPD fields from the DCGC0 as they have no function in deep-sleep mode. ■ Corrected address offsets for the Flash Write Buffer (FWBn) registers. ■ Added Flash Control (FCTL) register at Internal memory offset 0x0F8 to help control frequent power cycling when hibernation is not used. ■ Changed the name of the EPI channels for clarification: EPI0_TX became EPI0_WFIFO and EPI0_RX became EPI0_NBRFIFO. This change was also made in the DC7 bit descriptions. ■ Removed the DMACHIS register at DMA module offset 0x504 as it does not function correctly. ■ Corrected alternate channel assignments for the µDMA controller. ■ Major improvements to the EPI chapter. ■ EPISDRAMCFG2 register was deleted as its function is not needed. ■ Clarified CAN bit timing and corrected examples. ■ Clarified PWM source for ADC triggering ■ Corrected ADDR field in the USBTXFIFOADD register to be 9 bits instead of 13 bits. ■ Changed SSI set up and hold times to be expressed in system clocks, not ns. ■ Updated Electrical Characteristics chapter with latest data. Changes were made to ADC and EPI content. ■ Additional minor data sheet clarifications and corrections. July 22, 2011 43 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision July 2009 5930 June 2009 May 2009 5779 5285 Description ■ Corrected values for MAXADC0SPD and MAXADC1SPD bits in DC1, RCGC0, SCGC0, and DCGC0 registers. ■ Corrected figure "TI Synchronous Serial Frame Format (Single Transfer)". ■ Added description for Ethernet PHY power-saving modes. ■ Made a number of corrections to the Electrical Characteristics chapter: – Deleted VBAT and VREFA parameters from and added footnotes to Recommended DC Operating Conditions table. – Deleted Nominal and Maximum Current Specifications section. – Deleted SDRAM Read Command Timing, SDRAM Write Command Timing, SDRAM Write Burst Timing, SDRAM Precharge Command Timing and SDRAM CAS Latency Timing figures and replaced with SDRAM Read Timing and SDRAM Write Timing figures. – Modified Host-Bus 8/16 Mode Write Timing figure. – Modified General-Purpose Mode Read and Write Timing figure. – Major changes to ADC Characteristics tables, including adding additonal tables and diagram. ■ Added missing ROM_I2SIntStatus function to ROM DriverLib Functions appendix. ■ Corrected ordering part numbers. ■ Additional minor data sheet clarifications and corrections. ■ In System Control chapter, clarified power-on reset and external reset pin descriptions in "Reset Sources" section. ■ Added missing comparator output pin bits to DC3 register; reset value changed as well. ■ Clarified explanation of nonvolatile register programming in Internal Memory chapter. ■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0 registers. ■ In Request Type Support table in DMA chapter, corrected general-purpose timer row. ■ In General-Purpose Timers chapter, clarified DMA operation. ■ Added table "Preliminary Current Consumption" to Characteristics chapter. ■ Corrected Nom and Max values in EPI Characteristics table. ■ Added "CSn to output invalid" parameter to EPI table "EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics" and figure "Host-Bus 8/16 Mode Read Timing". ■ Corrected INL, DNL, OFF and GAIN values in ADC Characteristics table. ■ Updated ROM DriverLib appendix with RevC0 functions. ■ Updated part ordering numbers. ■ Additional minor data sheet clarifications and corrections. Started tracking revision history. 44 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller About This Document This data sheet provides reference information for the LM3S9L71 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents ® The following related documents are available on the Stellaris web site at www.ti.com/stellaris: ■ Stellaris® Errata ■ ARM® Cortex™-M3 Errata ■ Cortex™-M3 Instruction Set Technical User's Manual ■ Stellaris® Boot Loader User's Guide ■ Stellaris® Graphics Library User's Guide ■ Stellaris® Peripheral Driver Library User's Guide ■ Stellaris® ROM User’s Guide ■ Stellaris® USB Library User's Guide The following related documents are also referenced: ■ ARM® Debug Interface V5 Architecture Specification ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers. July 22, 2011 45 Texas Instruments-Production Data About This Document Documentation Conventions This document uses the conventions shown in Table 2 on page 46. Table 2. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. bit A single bit in a register. bit field Two or more consecutive and related bits. offset 0xnnn A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 2-4 on page 90. Register N Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. reserved Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. yy:xx The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. Register Bit/Field Types This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. R/WC Software can read or write this field. Writing to it with any value clears the register. R/W1C Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1S Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit value in the register. W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field Reset Value This value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. 46 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 2. Documentation Conventions (continued) Notation Meaning assert a signal Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). deassert a signal Change the value of the signal from the logically True state to the logically False state. SIGNAL Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. 0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. July 22, 2011 47 Texas Instruments-Production Data Architectural Overview 1 Architectural Overview ® Texas Instruments is the industry leader in bringing 32-bit capabilities and the full benefits of ARM Cortex™-M3-based microcontrollers to the broadest reach of the microcontroller market. For current ® users of 8- and 16-bit MCUs, Stellaris with Cortex-M3 offers a direct path to the strongest ecosystem of development tools, software and knowledge in the industry. Designers who migrate to Stellaris benefit from great tools, small code footprint and outstanding performance. Even more important, designers can enter the ARM ecosystem with full confidence in a compatible roadmap from $1 to 1 GHz. For users of current 32-bit MCUs, the Stellaris family offers the industry’s first implementation of Cortex-M3 and the Thumb-2 instruction set. With blazingly-fast responsiveness, Thumb-2 technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density and performance. Thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system cost while delivering 25 percent better performance. The Texas Instruments Stellaris family of microcontrollers—the first ARM Cortex-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S9L71 microcontroller has the following features: ■ ARM Cortex-M3 Processor Core – 80-MHz operation; 100 DMIPS performance – ARM Cortex SysTick Timer – Nested Vectored Interrupt Controller (NVIC) ■ On-Chip Memory – 128 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance above 50 MHz – 48 KB single-cycle SRAM ® – Internal ROM loaded with StellarisWare software: • Stellaris Peripheral Driver Library • Stellaris Boot Loader • Advanced Encryption Standard (AES) cryptography tables • Cyclic Redundancy Check (CRC) error detection functionality ■ Advanced Serial Integration – 10/100 Ethernet MAC with Media Independent Interface (MII) and IEEE 1588 PTP hardware support – Two CAN 2.0 A/B controllers – USB 2.0 OTG/Host/Device – Three UARTs with IrDA and ISO 7816 support (one UART with modem flow control and status) – Two I2C modules 48 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller – Two Synchronous Serial Interface modules (SSI) – Integrated Interchip Sound (I2S) module ■ System Integration – Direct Memory Access Controller (DMA) – System control and clocks including on-chip precision 16-MHz oscillator – Four 32-bit timers (up to eight 16-bit), with real-time clock capability – Eight Capture Compare PWM pins (CCP) – Two Watchdog Timers • One timer runs off the main oscillator • One timer runs off the precision internal oscillator – Up to 72 GPIOs, depending on configuration • Highly flexible pin muxing allows use as GPIO or one of several peripheral functions • Independently configurable to 2, 4 or 8 mA drive capability • Up to 4 GPIOs can have 18 mA drive capability ■ Advanced Motion Control – Six advanced PWM outputs for motion and energy applications – Four fault inputs to promote low-latency shutdown – Two Quadrature Encoder Inputs (QEI) ■ Analog – Two 10-bit Analog-to-Digital Converters (ADC) with 16 analog input channels and a sample rate of one million samples/second – Two analog comparators – 16 digital comparators – On-chip voltage regulator ■ JTAG and ARM Serial Wire Debug (SWD) ■ 100-pin LQFP package ■ 108-ball BGA package ■ Industrial (-40°C to 85°C) Temperature Range The LM3S9L71 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, power and energy, transportation, and fire and security. July 22, 2011 49 Texas Instruments-Production Data Architectural Overview In addition, the LM3S9L71 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S9L71 microcontroller is code-compatible to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise needs. Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact Information” on page 1259 for ordering information for Stellaris family devices. 1.1 Functional Overview The following sections provide an overview of the features of the LM3S9L71 microcontroller. The page number in parentheses indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 1259. 1.1.1 ARM Cortex-M3 The following sections provide an overview of the ARM Cortex-M3 processor core and instruction set, the integrated System Timer (SysTick) and the Nested Vectored Interrupt Controller. 1.1.1.1 Processor Core (see page 71) All members of the Stellaris product family, including the LM3S9L71 microcontroller, are designed around an ARM Cortex-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. ■ 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast multiplier ■ Deterministic, high-performance interrupt handling for time-critical applications 50 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing ■ Migration from the ARM7 processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage ■ Ultra-low power consumption with integrated sleep modes ■ 80-MHz operation ■ 1.25 DMIPS/MHz 1.1.1.2 Memory Map (see page 90) A memory map lists the location of instructions and data in memory. The memory map for the LM3S9L71 controller can be found in “Memory Model” on page 90. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. 1.1.1.3 System Timer (SysTick) (see page 114) ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine ■ A high-speed alarm timer using the system clock ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter ■ A simple counter used to measure time to completion and time used ■ An internal clock-source control based on missing/meeting durations. 1.1.1.4 Nested Vectored Interrupt Controller (NVIC) (see page 115) The LM3S9L71 controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC and Cortex-M3 prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 50 interrupts. ■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining ■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler for safety critical applications July 22, 2011 51 Texas Instruments-Production Data Architectural Overview ■ Dynamically reprioritizable interrupts ■ Exceptional interrupt handling via hardware implementation of required register manipulations 1.1.1.5 System Control Block (SCB) (see page 117) The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 1.1.1.6 Memory Protection Unit (MPU) (see page 117) The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 1.1.2 On-Chip Memory The following sections describe the on-chip memory modules. 1.1.2.1 SRAM (see page 298) The LM3S9L71 microcontroller provides 48 KB of single-cycle on-chip SRAM. The internal SRAM of the Stellaris devices is located at offset 0x2000.0000 of the device memory map. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller (µDMA). 1.1.2.2 Flash Memory (see page 300) The LM3S9L71 microcontroller provides 128 KB of single-cycle on-chip Flash memory (above 50 MHz, the Flash memory can be accessed in a single cycle as long as the code is linear; branches incur a one-cycle stall). The Flash memory is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.1.2.3 ROM (see page 298) The LM3S9L71 ROM is preprogrammed with the following software and programs: ■ Stellaris Peripheral Driver Library ■ Stellaris Boot Loader ■ Advanced Encryption Standard (AES) cryptography tables ■ Cyclic Redundancy Check (CRC) error-detection functionality 52 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller The Stellaris Peripheral Driver Library is a royalty-free software library for controlling on-chip peripherals with a boot-loader capability. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M3 core. No special pragmas or custom assembly code prologue/epilogue functions are required. For applications that require in-field programmability, the royalty-free Stellaris Boot Loader can act as an application loader and support in-field firmware updates. The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government. AES is a strong encryption method with reasonable performance and size. In addition, it is fast in both hardware and software, is fairly easy to implement, and requires little memory. The Texas Instruments encryption package is available with full source code, and is based on lesser general public license (LGPL) source. An LGPL means that the code can be used within an application without any copyleft implications for the application (the code does not automatically become open source). Modifications to the package source, however, must be open source. CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents as when previously checked. This technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that Flash memory contents have not been changed, and for other cases where the data needs to be validated. A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more readily. 1.1.3 Serial Communications Peripherals The LM3S9L71 controller supports both asynchronous and synchronous serial communications with: ■ 10/100 Ethernet MAC with Media Independent Interface (MII) and IEEE 1588 PTP hardware support ■ Two CAN 2.0 A/B controllers ■ USB 2.0 OTG/Host/Device ■ Three UARTs with IrDA and ISO 7816 support (one UART with modem flow control and status) ■ Two I2C modules ■ Two Synchronous Serial Interface modules (SSI) ■ Integrated Interchip Sound (I2S) module The following sections provide more detail on each of these communications functions. 1.1.3.1 Ethernet Controller (see page 827) Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet has been standardized as IEEE 802.3. This specification defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer, and a common addressing format. The Stellaris Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface and has the following features: ■ Conforms to the IEEE 802.3-2002 specification July 22, 2011 53 Texas Instruments-Production Data Architectural Overview ■ Multiple operational modes – Full- and half-duplex 100 Mbps – Full- and half-duplex 10 Mbps ■ Highly configurable – Programmable MAC address – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts ■ Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers ■ IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive channel request asserted on packet receipt – Transmit channel request asserted on empty transmit FIFO 1.1.3.2 Controller Area Network (see page 776) Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally created for automotive purposes, it is now used in many embedded control applications (for example, industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m). A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information. The LM3S9L71 microcontroller includes two CAN units with the following features: ■ CAN protocol version 2.0 part A/B ■ Bit rates up to 1 Mbps ■ 32 message objects with individual identifier masks ■ Maskable interrupt ■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications ■ Programmable Loopback mode for self-test operation ■ Programmable FIFO mode enables storage of multiple message objects 54 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals 1.1.3.3 USB (see page 863) Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface without rebooting the system. The LM3S9L71 microcontroller supports three configurations in USB 2.0 full and low speed: USB Device, USB Host, and USB On-The-Go (negotiated on-the-go as host or device when connected to other USB-enabled systems). The USB module has the following features: ■ Complies with USB-IF certification standards ■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation with integrated PHY ■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous ■ 32 endpoints – 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint – 15 configurable IN endpoints and 15 configurable OUT endpoints ■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size ■ VBUS droop and valid ID detection and interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints – Channel requests asserted when FIFO contains required amount of data 1.1.3.4 UART (see page 599) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S9L71 microcontroller includes three fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, modem status, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and are unmasked. The three UARTs have the following features: ■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by 16) and 10 Mbps for high speed (divide by 8) ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface July 22, 2011 55 Texas Instruments-Production Data Architectural Overview ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Standard asynchronous communication bits for start, stop, and parity ■ Line-break generation and detection ■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Support for communication with ISO 7816 smart cards ■ Full modem handshake support (on UART1) ■ LIN protocol support ■ Standard FIFO-level and End-of-Transmission interrupts ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level 1.1.3.5 I2C (see page 702) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. Each device on the I2C bus can be designated as either a master or a slave. Each I2C module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts. The LM3S9L71 microcontroller includes two I2C modules with the following features: 56 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ Devices on the I2C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation ■ Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive ■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) ■ Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected ■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 1.1.3.6 SSI (see page 660) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts data between parallel and serial. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The LM3S9L71 microcontroller includes two SSI modules with the following features: ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Master or slave operation ■ Programmable clock bit rate and prescaler ■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing July 22, 2011 57 Texas Instruments-Production Data Architectural Overview ■ Standard FIFO-based interrupts and End-of-Transmission interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries – Transmit single request asserted when there is space in the FIFO; burst request asserted when FIFO contains 4 entries 1.1.3.7 Inter-Integrated Circuit Sound (I2S) Interface (see page 739) The I2S interface is a configurable serial audio core that contains a transmit module and a receive module. The module is configurable for the I2S as well as Left-Justified and Right-Justified serial audio formats. Data can be in one of four modes: Stereo, Mono, Compact 16-bit Stereo and Compact 8-Bit Stereo. The transmit and receive modules each have an 8-entry audio-sample FIFO. An audio sample can consist of a Left and Right Stereo sample, a Mono sample, or a Left and Right Compact Stereo sample. In Compact 16-Bit Stereo, each FIFO entry contains both the 16-bit left and 16-bit right samples, allowing efficient data transfers and requiring less memory space. In Compact 8-bit Stereo, each FIFO entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements further. Both the transmitter and receiver are capable of being a master or a slave. The Stellaris I2S interface has the following features: ■ Configurable audio format supporting I2S, Left-justification, and Right-justification ■ Configurable sample size from 8 to 32 bits ■ Mono and Stereo support ■ 8-, 16-, and 32-bit FIFO interface for packing memory ■ Independent transmit and receive 8-entry FIFOs ■ Configurable FIFO-level interrupt and µDMA requests ■ Independent transmit and receive MCLK direction control ■ Transmit and receive internal MCLK sources ■ Independent transmit and receive control for serial clock and word select ■ MCLK and SCLK can be independently set to master or slave ■ Configurable transmit zero or last sample when FIFO empty ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Burst requests 58 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller – Channel requests asserted when FIFO contains required amount of data 1.1.4 System Integration The LM3S9L71 microcontroller provides a variety of standard system functions integrated into the device, including: ■ Direct Memory Access Controller (DMA) ■ System control and clocks including on-chip precision 16-MHz oscillator ■ Four 32-bit timers (up to eight 16-bit), with real-time clock capability ■ Eight Capture Compare PWM pins (CCP) ■ Two Watchdog Timers – One timer runs off the main oscillator – One timer runs off the precision internal oscillator ■ Up to 72 GPIOs, depending on configuration – Highly flexible pin muxing allows use as GPIO or one of several peripheral functions – Independently configurable to 2, 4 or 8 mA drive capability – Up to 4 GPIOs can have 18 mA drive capability The following sections provide more detail on each of these functions. 1.1.4.1 Direct Memory Access (see page 333) The LM3S9L71 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: ® ■ ARM PrimeCell 32-channel configurable µDMA controller ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Primary and secondary channel assignments – One channel each for receive and transmit path for bidirectional modules July 22, 2011 59 Texas Instruments-Production Data Architectural Overview – Dedicated channel for software-initiated transfers – Per-channel configurable priority scheme – Optional software-initiated requests for any channel ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping – Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Transfer size is programmable in binary steps from 1 to 1024 ■ Source and destination address increment size of byte, half-word, word, or no increment ■ Maskable peripheral requests 1.1.4.2 System Control and Clocks (see page 192) System control determines the overall operation of the device. It provides information about the device, controls power-saving features, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. ■ Device identification information: version, part number, SRAM size, Flash memory size, and so on ■ Power control – On-chip fixed Low Drop-Out (LDO) voltage regulator – Low-power options for microcontroller: Sleep and Deep-sleep modes with clock gating – Low-power options for on-chip modules: software controls shutdown of individual peripherals and memory – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Multiple clock sources for microcontroller system clock – Precision Oscillator (PIOSC): On-chip resource providing a 16 MHz ±1% frequency at room temperature • 16 MHz ±3% across temperature • Can be recalibrated with 7-bit trim resolution • Software power down control for low power modes – Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. 60 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller • • External crystal used with or without on-chip PLL: select supported frequencies from 1 MHz to 16.384 MHz. External oscillator: from DC to maximum device speed – Internal 30-kHz Oscillator: on chip resource providing a 30 kHz ± 50% frequency, used during power-saving modes ■ Flexible reset sources – Power-on reset (POR) – Reset pin assertion – Brown-out reset (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – MOSC failure 1.1.4.3 Programmable Timers (see page 448) Programmable timers can be used to count or time external events that drive the Timer input pins. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional options: ■ Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 16-bit input-edge count- or time-capture modes – 16-bit PWM mode with software-programmable output inversion of the PWM signal ■ Count up or down ■ Eight Capture Compare PWM pins (CCP) ■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events ■ ADC event trigger ■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding RTC mode) July 22, 2011 61 Texas Instruments-Production Data Architectural Overview ■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each timer – Burst request generated on timer interrupt 1.1.4.4 CCP Pins (see page 455) Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin. The LM3S9L71 microcontroller includes eight Capture Compare PWM pins (CCP) that can be programmed to operate in the following modes: ■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer captures and stores the current timer value when a programmed event occurs. ■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer compares the current value with a stored value and generates an interrupt when a match occurs. ■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated based on a match between the counter value and a value stored in a match register and is output on the CCP pin. 1.1.4.5 Watchdog Timers (see page 495) A watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer can generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. The LM3S9L71 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris Watchdog Timer module has the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug 62 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 1.1.4.6 Programmable GPIOs (see page 391) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris GPIO module is comprised of nine physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 0-72 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1113 for the signals available to each GPIO pin). ■ Up to 72 GPIOs, depending on configuration ■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions ■ 5-V-tolerant in input configuration ■ Fast toggle capable of a change every two clock cycles ■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with existing code ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can be used to initiate an ADC sample sequence ■ Pins configured as digital inputs are Schmitt-triggered ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 1.1.5 Advanced Motion Control The LM3S9L71 microcontroller provides motion control functions integrated into the device, including: ■ Six advanced PWM outputs for motion and energy applications ■ Four fault inputs to promote low-latency shutdown ■ Two Quadrature Encoder Inputs (QEI) July 22, 2011 63 Texas Instruments-Production Data Architectural Overview The following provides more detail on these motion control functions. 1.1.5.1 PWM (see page 1015) Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. The LM3S9L71 PWM module consists of three PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. Each PWM generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. Each PWM generator has the following features: ■ Four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled ■ One 16-bit counter – Runs in Down or Up/Down mode – Output frequency controlled by a 16-bit load value – Load value updates can be synchronized – Produces output signals at zero and load value ■ Two PWM comparators – Comparator value updates can be synchronized – Produces output signals on match ■ PWM signal generator – Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals – Produces two independent PWM signals ■ Dead-band generator – Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge – Can be bypassed, leaving input PWM signals unmodified ■ Can initiate an ADC sample sequence The control block determines the polarity of the PWM signals and which signals are passed through to the pins. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. The PWM control block has the following options: ■ PWM output enable of each PWM signal ■ Optional output inversion of each PWM signal (polarity control) 64 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ Optional fault handling for each PWM signal ■ Synchronization of timers in the PWM generator blocks ■ Synchronization of timer/comparator updates across the PWM generator blocks ■ Synchronization of PWM output enables across the PWM generator blocks ■ Interrupt status summary of the PWM generator blocks ■ Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering ■ PWM generators can be operated independently or synchronized with other generators 1.1.5.2 QEI (see page 1088) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index signal, can be used to reset the position counter. The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 20 MHz for a 80-MHz system). The LM3S9L71 microcontroller includes two QEI modules providing control of two motors at the same time with the following features: ■ Position integrator that tracks the encoder position ■ Programmable noise filter on the inputs ■ Velocity capture using built-in timer ■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system) ■ Interrupt generation on: – Index pulse – Velocity-timer expiration – Direction change – Quadrature error detection 1.1.6 Analog The LM3S9L71 microcontroller provides analog functions integrated into the device, including: ■ Two 10-bit Analog-to-Digital Converters (ADC) with 16 analog input channels and a sample rate of one million samples/second ■ Two analog comparators ■ 16 digital comparators July 22, 2011 65 Texas Instruments-Production Data Architectural Overview ■ On-chip voltage regulator The following provides more detail on these analog functions. 1.1.6.1 ADC (see page 520) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris ADC module features 10-bit conversion resolution and supports 16 input channels plus an internal temperature sensor. Four buffered sample sequencers allow rapid sampling of up to 16 analog input sources without controller intervention. Each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator function that allows the conversion value to be diverted to a comparison unit that provides eight digital comparators. The LM3S9L71 microcontroller provides two ADC modules with the following features: ■ 16 shared analog input channels ■ Single-ended and differential-input configurations ■ On-chip internal temperature sensor ■ Maximum sample rate of one million samples/second ■ Optional phase shift in sample time programmable from 22.5º to 337.5º ■ Four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – PWM – GPIO ■ Hardware averaging of up to 64 samples ■ Digital comparison unit providing eight digital comparators ■ Converter uses an internal 3-V reference or an external reference ■ Power and ground for the analog circuitry is separate from the digital power and ground ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each sample sequencer – ADC module uses burst requests for DMA 66 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 1.1.6.2 Analog Comparators (see page 1002) An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The LM3S9L71 microcontroller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. The LM3S9L71 microcontroller provides two independent integrated analog comparators with the following functions: ■ Compare external pin input to external pin input or to internal programmable voltage reference ■ Compare a test voltage against any one of the following voltages: – An individual external reference voltage – A shared single external reference voltage – A shared internal reference voltage 1.1.7 JTAG and ARM Serial Wire Debug (see page 180) The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module providing all the normal JTAG debug and test functionality plus real-time access to system memory without halting the core or requiring any target resident code. The SWJ-DP interface has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling July 22, 2011 67 Texas Instruments-Production Data Architectural Overview – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer 1.1.8 Packaging and Temperature ■ Industrial-range 100-pin RoHS-compliant LQFP package ■ Industrial-range 108-ball RoHS-compliant BGA package 1.2 Target Applications The Stellaris family is positioned for cost-conscious applications requiring significant control processing and connectivity capabilities such as: ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 69 depicts the features on the Stellaris LM3S9L71 microcontroller. Note that there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back access performance than the APB bus. 68 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 1-1. Stellaris LM3S9L71 Microcontroller High-Level Block Diagram JTAG/SWD ARM® Cortex™-M3 ROM (80 MHz) System Control and Clocks (w/ Precis. Osc.) DCode bus NVIC Boot Loader DriverLib AES & CRC Flash (128 KB) MPU ICode bus System Bus LM3S9L71 Bus Matrix SRAM (48 KB) SYSTEM PERIPHERALS DMA Watchdog Timers (2) GPIOs (72) GeneralPurpose Timers (4) SSI (2) CAN Controllers (2) UARTs (3) Advanced Peripheral Bus (APB) USB OTG (FS PHY) Advanced High-Performance Bus (AHB) SERIAL PERIPHERALS I2C (2) Ethernet MAC I2S ANALOG PERIPHERALS Analog Comparators (2) 10-Bit ADC Channels (16) MOTION CONTROL PERIPHERALS PWM (6) QEI (2) July 22, 2011 69 Texas Instruments-Production Data Architectural Overview 1.4 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 1111 ■ “Signal Tables” on page 1113 ■ “Operating Characteristics” on page 1189 ■ “Electrical Characteristics” on page 1190 ■ “Package Information” on page 1261 70 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 2 The Cortex-M3 Processor The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ® ■ 32-bit ARM Cortex™-M3 architecture optimized for small-footprint embedded applications ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast multiplier ■ Deterministic, high-performance interrupt handling for time-critical applications ■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing ■ Migration from the ARM7 processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage ■ Ultra-low power consumption with integrated sleep modes ■ 80-MHz operation ■ 1.25 DMIPS/MHz ® The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. July 22, 2011 71 Texas Instruments-Production Data The Cortex-M3 Processor This chapter provides information on the Stellaris implementation of the Cortex-M3 processor, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the instruction set, see the Cortex™-M3 Instruction Set Technical User's Manual. 2.1 Block Diagram The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. 72 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep ARM Cortex-M3 CM3 Core Debug Instructions Data Trace Port Interface Unit Memory Protection Unit Flash Patch and Breakpoint Instrumentation Data Watchpoint Trace Macrocell and Trace ROM Table Private Peripheral Bus (internal) Adv. Peripheral Bus Bus Matrix Serial Wire JTAG Debug Port Debug Access Port 2.2 Overview 2.2.1 System-Level Interface Serial Wire Output Trace Port (SWO) I-code bus D-code bus System bus The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis. 2.2.2 Integrated Configurable Debug The Cortex-M3 processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification for details on SWJ-DP. For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. July 22, 2011 73 Texas Instruments-Production Data The Cortex-M3 Processor The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored in a read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration. For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5 Architecture Specification. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer, as shown in Figure 2-2 on page 74. Figure 2-2. TPIU Block Diagram 2.2.4 Debug ATB Slave Port ATB Interface APB Slave Port APB Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) Cortex-M3 System Component Details The Cortex-M3 includes the following system components: ■ SysTick A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as a simple counter (see “System Timer (SysTick)” on page 114). ■ Nested Vectored Interrupt Controller (NVIC) An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 115). ■ System Control Block (SCB) 74 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions( see “System Control Block (SCB)” on page 117). ■ Memory Protection Unit (MPU) Improves system reliability by defining the memory attributes for different memory regions. The MPU provides up to eight different regions and an optional predefined background region (see “Memory Protection Unit (MPU)” on page 117). 2.3 Programming Model This section describes the Cortex-M3 programming model. In addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included. 2.3.1 Processor Mode and Privilege Levels for Software Execution The Cortex-M3 has two modes of operation: ■ Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. ■ Handler mode Used to handle exceptions. When the processor has finished exception processing, it returns to Thread mode. In addition, the Cortex-M3 has two privilege levels: ■ Unprivileged In this mode, software has the following restrictions: – Limited access to the MSR and MRS instructions and no use of the CPS instruction – No access to the system timer, NVIC, or system control block – Possibly restricted access to memory or peripherals ■ Privileged In this mode, software can use all the instructions and has access to all resources. In Thread mode, the CONTROL register (see page 89) controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 2.3.2 Stacks The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements July 22, 2011 75 Texas Instruments-Production Data The Cortex-M3 Processor two stacks: the main stack and the process stack, with independent copies of the stack pointer (see the SP register on page 79). In Thread mode, the CONTROL register (see page 89) controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1 on page 76. Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use Processor Mode Use Privilege Level Thread Applications Privileged or unprivileged Stack Used Handler Exception handlers Always privileged a Main stack or process stack a Main stack a. See CONTROL (page 89). 2.3.3 Register Map Figure 2-3 on page 76 shows the Cortex-M3 register set. Table 2-2 on page 77 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. Figure 2-3. Cortex-M3 Register Set R0 R1 R2 Low registers R3 R4 R5 R6 General-purpose registers R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSR PSP‡ MSP‡ ‡ Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL CONTROL register 76 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 2-2. Processor Register Map Offset Type Reset - R0 R/W - Cortex General-Purpose Register 0 78 - R1 R/W - Cortex General-Purpose Register 1 78 - R2 R/W - Cortex General-Purpose Register 2 78 - R3 R/W - Cortex General-Purpose Register 3 78 - R4 R/W - Cortex General-Purpose Register 4 78 - R5 R/W - Cortex General-Purpose Register 5 78 - R6 R/W - Cortex General-Purpose Register 6 78 - R7 R/W - Cortex General-Purpose Register 7 78 - R8 R/W - Cortex General-Purpose Register 8 78 - R9 R/W - Cortex General-Purpose Register 9 78 - R10 R/W - Cortex General-Purpose Register 10 78 - R11 R/W - Cortex General-Purpose Register 11 78 - R12 R/W - Cortex General-Purpose Register 12 78 - SP R/W - Stack Pointer 79 - LR R/W 0xFFFF.FFFF Link Register 80 - PC R/W - Program Counter 81 - PSR R/W 0x0100.0000 Program Status Register 82 - PRIMASK R/W 0x0000.0000 Priority Mask Register 86 - FAULTMASK R/W 0x0000.0000 Fault Mask Register 87 - BASEPRI R/W 0x0000.0000 Base Priority Mask Register 88 - CONTROL R/W 0x0000.0000 Control Register 89 2.3.4 Description See page Name Register Descriptions This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 76. The core registers are not memory mapped and are accessed by register name rather than offset. Note: The register type shown in the register descriptions refers to type during program execution in Thread mode and Handler mode. Debug access can differ. July 22, 2011 77 Texas Instruments-Production Data The Cortex-M3 Processor Register 1: Cortex General-Purpose Register 0 (R0) Register 2: Cortex General-Purpose Register 1 (R1) Register 3: Cortex General-Purpose Register 2 (R2) Register 4: Cortex General-Purpose Register 3 (R3) Register 5: Cortex General-Purpose Register 4 (R4) Register 6: Cortex General-Purpose Register 5 (R5) Register 7: Cortex General-Purpose Register 6 (R6) Register 8: Cortex General-Purpose Register 7 (R7) Register 9: Cortex General-Purpose Register 8 (R8) Register 10: Cortex General-Purpose Register 9 (R9) Register 11: Cortex General-Purpose Register 10 (R10) Register 12: Cortex General-Purpose Register 11 (R11) Register 13: Cortex General-Purpose Register 12 (R12) The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Cortex General-Purpose Register 0 (R0) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - DATA Type Reset DATA Type Reset Bit/Field Name Type Reset 31:0 DATA R/W - Description Register data. 78 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 14: Stack Pointer (SP) The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode. Stack Pointer (SP) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - SP Type Reset SP Type Reset Bit/Field Name Type Reset 31:0 SP R/W - Description This field is the address of the stack pointer. July 22, 2011 79 Texas Instruments-Production Data The Cortex-M3 Processor Register 15: Link Register (LR) The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. LR can be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 107 for the values and description. Link Register (LR) Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 LINK Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 LINK Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 LINK R/W R/W 1 Reset R/W 1 Description 0xFFFF.FFFF This field is the return address. 80 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 16: Program Counter (PC) The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode. Program Counter (PC) Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - PC Type Reset PC Type Reset Bit/Field Name Type Reset 31:0 PC R/W - Description This field is the current program address. July 22, 2011 81 Texas Instruments-Production Data The Cortex-M3 Processor Register 17: Program Status Register (PSR) Note: This register is also referred to as xPSR. The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions: ■ Application Program Status Register (APSR), bits 31:27, ■ Execution Program Status Register (EPSR), bits 26:24, 15:10 ■ Interrupt Program Status Register (IPSR), bits 6:0 The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be accessed in either privileged or unprivileged mode. APSR contains the current state of the condition flags from previous instruction executions. EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see “Exception Entry and Return” on page 105). IPSR contains the exception type number of the current Interrupt Service Routine (ISR). These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. page 82 shows the possible register combinations for the PSR. See the MRS and MSR instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual for more information about how to access the program status registers. Table 2-3. PSR Register Combinations Register Type PSR R/W Combination APSR, EPSR, and IPSR IEPSR RO EPSR and IPSR a, b a APSR and IPSR b APSR and EPSR IAPSR R/W EAPSR R/W a. The processor ignores writes to the IPSR bits. b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. Program Status Register (PSR) Type R/W, reset 0x0100.0000 Type Reset 31 30 29 28 27 N Z C V Q 26 25 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 15 14 13 12 11 10 9 ICI / IT ICI / IT Type Reset RO 0 RO 0 RO 0 24 23 22 21 20 THUMB RO 1 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 reserved RO 0 RO 0 RO 0 RO 0 RO 0 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 reserved ISRNUM RO 0 RO 0 82 RO 0 RO 0 RO 0 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 31 N R/W 0 Description APSR Negative or Less Flag Value Description 1 The previous operation result was negative or less than. 0 The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessing PSR or APSR. 30 Z R/W 0 APSR Zero Flag Value Description 1 The previous operation result was zero. 0 The previous operation result was non-zero. The value of this bit is only meaningful when accessing PSR or APSR. 29 C R/W 0 APSR Carry or Borrow Flag Value Description 1 The previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. 0 The previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. The value of this bit is only meaningful when accessing PSR or APSR. 28 V R/W 0 APSR Overflow Flag Value Description 1 The previous operation resulted in an overflow. 0 The previous operation did not result in an overflow. The value of this bit is only meaningful when accessing PSR or APSR. 27 Q R/W 0 APSR DSP Overflow and Saturation Flag Value Description 1 DSP Overflow or saturation has occurred. 0 DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. July 22, 2011 83 Texas Instruments-Production Data The Cortex-M3 Processor Bit/Field Name Type Reset 26:25 ICI / IT RO 0x0 Description EPSR ICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 24 THUMB RO 1 EPSR Thumb State This bit indicates the Thumb state and should always be set. The following can clear the THUMB bit: ■ The BLX, BX and POP{PC} instructions ■ Restoration from the stacked xPSR value on an exception return ■ Bit 0 of the vector value on an exception entry Attempting to execute instructions when this bit is clear results in a fault or lockup. See “Lockup” on page 109 for more information. The value of this bit is only meaningful when accessing PSR or EPSR. 23:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:10 ICI / IT RO 0x0 EPSR ICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When an interrupt occurs during the execution of an LDM, STM, PUSH or POP instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. When EPSR holds the ICI execution state, bits 11:10 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 9:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 84 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 6:0 ISRNUM RO 0x00 IPSR ISR Number This field contains the exception type number of the current Interrupt Service Routine (ISR). Value Description 0x00 Thread mode 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x46 Interrupt Vector 54 0x47-0x7F Reserved See “Exception Types” on page 100 for more information. The value of this field is only meaningful when accessing PSR or IPSR. July 22, 2011 85 Texas Instruments-Production Data The Cortex-M3 Processor Register 18: Priority Mask Register (PRIMASK) The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M3 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 100. Priority Mask Register (PRIMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PRIMASK R/W 0 RO 0 PRIMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Priority Mask Value Description 1 Prevents the activation of all exceptions with configurable priority. 0 No effect. 86 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 19: Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the Cortex™-M3 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 100. Fault Mask Register (FAULTMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 FAULTMASK R/W 0 RO 0 FAULTMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI. 0 No effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. July 22, 2011 87 Texas Instruments-Production Data The Cortex-M3 Processor Register 20: Base Priority Mask Register (BASEPRI) The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. For more information on exception priority levels, see “Exception Types” on page 100. Base Priority Mask Register (BASEPRI) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset BASEPRI RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:5 BASEPRI R/W 0x0 R/W 0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Base Priority Any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. The PRIMASK register can be used to mask all exceptions with programmable priority levels. Higher priority exceptions have lower priority levels. Value Description 4:0 reserved RO 0x0 0x0 All exceptions are unmasked. 0x1 All exceptions with priority level 1-7 are masked. 0x2 All exceptions with priority level 2-7 are masked. 0x3 All exceptions with priority level 3-7 are masked. 0x4 All exceptions with priority level 4-7 are masked. 0x5 All exceptions with priority level 5-7 are masked. 0x6 All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 88 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 21: Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. This register is only accessible in privileged mode. Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 107). In an OS environment, threads running in Thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex™-M3 Instruction Set Technical User's Manual, or perform an exception return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 107. Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the Cortex™-M3 Instruction Set Technical User's Manual. Control Register (CONTROL) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 ASP TMPL RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 ASP R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Active Stack Pointer Value Description 1 PSP is the current stack pointer. 0 MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. 0 TMPL R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. July 22, 2011 89 Texas Instruments-Production Data The Cortex-M3 Processor 2.3.5 Exceptions and Interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See “Exception Entry and Return” on page 105 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” on page 115 for more information. 2.3.6 Data Types The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. See “Memory Regions, Types and Attributes” on page 92 for more information. 2.4 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map for the LM3S9L71 controller is provided in Table 2-4 on page 90. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see “Bit-Banding” on page 95). The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers (see “Cortex-M3 Peripherals” on page 114). Note: Within the memory map, all reserved space returns a bus fault when read or written. Table 2-4. Memory Map Start End Description For details, see page ... 0x0000.0000 0x0001.FFFF On-chip Flash 300 0x0002.0000 0x00FF.FFFF Reserved - 0x0100.0000 0x1FFF.FFFF Reserved for ROM 298 0x2000.0000 0x2000.BFFF Bit-banded on-chip SRAM 298 0x2000.C000 0x21FF.FFFF Reserved - 0x2200.0000 0x2217.FFFF Bit-band alias of bit-banded on-chip SRAM starting at 0x2000.0000 298 0x2218.0000 0x3FFF.FFFF Reserved - 0x4000.0000 0x4000.0FFF Watchdog timer 0 498 0x4000.1000 0x4000.1FFF Watchdog timer 1 498 0x4000.2000 0x4000.3FFF Reserved - 0x4000.4000 0x4000.4FFF GPIO Port A 405 0x4000.5000 0x4000.5FFF GPIO Port B 405 0x4000.6000 0x4000.6FFF GPIO Port C 405 Memory FiRM Peripherals 90 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x4000.7000 0x4000.7FFF GPIO Port D 405 0x4000.8000 0x4000.8FFF SSI0 674 0x4000.9000 0x4000.9FFF SSI1 674 0x4000.A000 0x4000.BFFF Reserved - 0x4000.C000 0x4000.CFFF UART0 612 0x4000.D000 0x4000.DFFF UART1 612 0x4000.E000 0x4000.EFFF UART2 612 0x4000.F000 0x4001.FFFF Reserved - 0x4002.0FFF I2C 0 718 0x4002.1000 0x4002.1FFF I2C 718 0x4002.2000 0x4002.3FFF Reserved - 0x4002.4000 0x4002.4FFF GPIO Port E 405 0x4002.5000 0x4002.5FFF GPIO Port F 405 0x4002.6000 0x4002.6FFF GPIO Port G 405 0x4002.7000 0x4002.7FFF GPIO Port H 405 0x4002.8000 0x4002.8FFF PWM 1029 0x4002.9000 0x4002.BFFF Reserved - 0x4002.C000 0x4002.CFFF QEI0 1094 0x4002.D000 0x4002.DFFF QEI1 1094 0x4002.E000 0x4002.FFFF Reserved - 0x4003.0000 0x4003.0FFF Timer 0 464 0x4003.1000 0x4003.1FFF Timer 1 464 0x4003.2000 0x4003.2FFF Timer 2 464 0x4003.3000 0x4003.3FFF Timer 3 464 0x4003.4000 0x4003.7FFF Reserved - 0x4003.8000 0x4003.8FFF ADC0 541 0x4003.9000 0x4003.9FFF ADC1 541 0x4003.A000 0x4003.BFFF Reserved - 0x4003.C000 0x4003.CFFF Analog Comparators 1002 0x4003.D000 0x4003.DFFF GPIO Port J 405 0x4003.E000 0x4003.FFFF Reserved - 0x4004.0000 0x4004.0FFF CAN0 Controller 796 0x4004.1000 0x4004.1FFF CAN1 Controller 796 0x4004.2000 0x4004.7FFF Reserved - 0x4004.8000 0x4004.8FFF Ethernet Controller 839 0x4004.9000 0x4004.FFFF Reserved - 0x4005.0000 0x4005.0FFF USB 890 0x4005.1000 0x4005.3FFF Reserved - 0x4005.4000 0x4005.4FFF I2S0 751 0x4005.5000 0x4005.7FFF Reserved - Peripherals 0x4002.0000 1 July 22, 2011 91 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x4005.8000 0x4005.8FFF GPIO Port A (AHB aperture) 405 0x4005.9000 0x4005.9FFF GPIO Port B (AHB aperture) 405 0x4005.A000 0x4005.AFFF GPIO Port C (AHB aperture) 405 0x4005.B000 0x4005.BFFF GPIO Port D (AHB aperture) 405 0x4005.C000 0x4005.CFFF GPIO Port E (AHB aperture) 405 0x4005.D000 0x4005.DFFF GPIO Port F (AHB aperture) 405 0x4005.E000 0x4005.EFFF GPIO Port G (AHB aperture) 405 0x4005.F000 0x4005.FFFF GPIO Port H (AHB aperture) 405 0x4006.0000 0x4006.0FFF GPIO Port J (AHB aperture) 405 0x4006.1000 0x400F.CFFF Reserved - 0x400F.D000 0x400F.DFFF Flash memory control 305 0x400F.E000 0x400F.EFFF System control 209 0x400F.F000 0x400F.FFFF µDMA 354 0x4010.0000 0x41FF.FFFF Reserved - 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - 0x4400.0000 0xDFFF.FFFF Reserved - 0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 73 0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 73 0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 73 0xE000.3000 0xE000.DFFF Reserved - 0xE000.E000 0xE000.EFFF Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU) 99 0xE000.F000 0xE003.FFFF Reserved - 0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 74 0xE004.1000 0xFFFF.FFFF Reserved - Private Peripheral Bus 2.4.1 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: ■ Normal: The processor can re-order transactions for efficiency and perform speculative reads. ■ Device: The processor preserves transaction order relative to other transactions to Device or Strongly Ordered memory. ■ Strongly Ordered: The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. 92 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region. 2.4.2 Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions (see “Software Ordering of Memory Accesses” on page 94). However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always observed before A2. 2.4.3 Behavior of Memory Accesses Table 2-5 on page 93 shows the behavior of accesses to each region in the memory map. See “Memory Regions, Types and Attributes” on page 92 for more information on memory types and the XN attribute. Stellaris devices may have reserved memory areas within the address ranges shown below (refer to Table 2-4 on page 90 for more information). Table 2-5. Memory Access Behavior Address Range Memory Region Memory Type Execute Never (XN) Description 0x0000.0000 - 0x1FFF.FFFF Code Normal - This executable region is for program code. Data can also be stored here. 0x2000.0000 - 0x3FFF.FFFF SRAM Normal - This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 95). 0x4000.0000 - 0x5FFF.FFFF Peripheral Device XN This region includes bit band and bit band alias areas (see Table 2-7 on page 95). 0x6000.0000 - 0x9FFF.FFFF External RAM Normal - This executable region is for data. 0xA000.0000 - 0xDFFF.FFFF External device Device XN This region is for external device memory. 0xE000.0000- 0xE00F.FFFF Private peripheral bus Strongly Ordered XN This region includes the NVIC, system timer, and system control block. 0xE010.0000- 0xFFFF.FFFF Reserved - - - The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region because the Cortex-M3 has separate buses that can perform instruction fetches and data accesses simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit (MPU)” on page 117. The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. July 22, 2011 93 Texas Instruments-Production Data The Cortex-M3 Processor 2.4.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: ■ The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. ■ The processor has multiple bus interfaces. ■ Memory or devices in the memory map have different wait states. ■ Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” on page 93 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The Cortex-M3 has the following memory barrier instructions: ■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. ■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. ■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. Memory barrier instructions can be used in the following situations: ■ MPU programming – If the MPU settings are changed and the change must be effective on the very next instruction, use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. – Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not required. ■ Vector table If the program changes an entry in the vector table and then enables the corresponding exception, use a DMB instruction between the operations. The DMB instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. ■ Self-modifying code If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching 94 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. The change then takes effect on completion of the DSB instruction. Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use of DMB instructions. For more information on the memory barrier instructions, see the Cortex™-M3 Instruction Set Technical User's Manual. 2.4.5 Bit-Banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-6 on page 95. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region, as shown in Table 2-7 on page 95. For the specific address range of the bit-band regions, see Table 2-4 on page 90. Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region. A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. Table 2-6. SRAM Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses 0x2000.0000 - 0x200F.FFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. 0x2200.0000 - 0x23FF.FFFF SRAM bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. Table 2-7. Peripheral Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses 0x4000.0000 - 0x400F.FFFF Peripheral bit-band region Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. 0x4200.0000 - 0x43FF.FFFF Peripheral bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset July 22, 2011 95 Texas Instruments-Production Data The Cortex-M3 Processor where: bit_word_offset The position of the target bit in the bit-band memory region. bit_word_addr The address of the word in the alias memory region that maps to the targeted bit. bit_band_base The starting address of the alias region. byte_offset The number of the byte in the bit-band region that contains the targeted bit. bit_number The bit position, 0-7, of the targeted bit. Figure 2-4 on page 97 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: ■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4) ■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4) ■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) 96 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 2-4. Bit-Band Mapping 32-MB Alias Region 0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0 0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0004 0x2200.0000 7 3 1-MB SRAM Bit-Band Region 7 6 5 4 3 2 1 0 7 6 0x200F.FFFF 7 6 5 4 3 2 0x2000.0003 2.4.5.1 5 4 3 2 1 0 7 6 0x200F.FFFE 1 0 7 6 5 4 3 2 5 4 3 2 1 0 6 0x200F.FFFD 1 0 0x2000.0002 7 6 5 4 3 2 0x2000.0001 5 4 2 1 0 1 0 0x200F.FFFC 1 0 7 6 5 4 3 2 0x2000.0000 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set. 2.4.5.2 Directly Accessing a Bit-Band Region “Behavior of Memory Accesses” on page 93 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 2.4.6 Data Storage The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-5 on page 98 illustrates how data is stored. July 22, 2011 97 Texas Instruments-Production Data The Cortex-M3 Processor Figure 2-5. Data Storage Memory 7 Register 0 31 2.4.7 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte Synchronization Primitives The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. A pair of synchronization primitives consists of: ■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. ■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write is performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: ■ The word instructions LDREX and STREX ■ The halfword instructions LDREXH and STREXH ■ The byte instructions LDREXB and STREXB Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and test the returned status bit. If the status bit is clear, the read-modify-write completed successfully; if the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 98 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1. The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has executed a Load-Exclusive instruction. The processor removes its exclusive access tag if: ■ It executes a CLREX instruction. ■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds. ■ An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see the Cortex™-M3 Instruction Set Technical User's Manual. 2.5 Exception Model The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 2-8 on page 101 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 50 interrupts (listed in Table 2-9 on page 102). Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in “Nested Vectored Interrupt Controller (NVIC)” on page 115. Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the programmable priorities. Important: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC)” on page 115 for more information on exceptions and interrupts. 2.5.1 Exception States Each exception is in one of the following states: July 22, 2011 99 Texas Instruments-Production Data The Cortex-M3 Processor ■ Inactive. The exception is not active and not pending. ■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. ■ Active. An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. ■ Active and Pending. The exception is being serviced by the processor, and there is a pending exception from the same source. 2.5.2 Exception Types The exception types are: ■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. ■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. ■ Hard Fault. A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. ■ Memory Management Fault. A memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. The MPU or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. ■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. ■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return 100 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. ■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. ■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception is only active when enabled. This exception does not activate if it is a lower priority than the current activation. ■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using the Interrupt Control and State (INTCTRL) register. ■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor can use this exception as system tick. ■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 102 lists the interrupts on the LM3S9L71 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 2-8 on page 101 shows as having configurable priority (see the SYSHNDCTRL register on page 158 and the DIS0 register on page 131). For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” on page 107. Table 2-8. Exception Types Exception Type a Vector Number Priority Vector Address or b Offset - 0 - 0x0000.0000 Stack top is loaded from the first entry of the vector table on reset. Reset 1 -3 (highest) 0x0000.0004 Asynchronous Non-Maskable Interrupt (NMI) 2 -2 0x0000.0008 Asynchronous Hard Fault 3 -1 0x0000.000C - c 0x0000.0010 Synchronous c 0x0000.0014 Synchronous when precise and asynchronous when imprecise c Synchronous Memory Management 4 programmable Bus Fault 5 programmable Usage Fault 6 programmable 0x0000.0018 7-10 - - - Activation Reserved c 0x0000.002C Synchronous c 0x0000.0030 Synchronous c 0x0000.0038 SVCall 11 programmable Debug Monitor 12 programmable - 13 - PendSV 14 programmable - July 22, 2011 Reserved Asynchronous 101 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-8. Exception Types (continued) Exception Type SysTick Interrupts a Vector Number Priority Vector Address or b Offset 15 programmable c 16 and above 0x0000.003C d programmable Activation Asynchronous 0x0000.0040 and above Asynchronous a. 0 is the default priority for all the programmable priorities. b. See “Vector Table” on page 103. c. See SYSPRI1 on page 155. d. See PRIn registers on page 139. Table 2-9. Interrupts Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 0-15 - 0x0000.0000 0x0000.003C 16 0 0x0000.0040 GPIO Port A 17 1 0x0000.0044 GPIO Port B 18 2 0x0000.0048 GPIO Port C 19 3 0x0000.004C GPIO Port D 20 4 0x0000.0050 GPIO Port E 21 5 0x0000.0054 UART0 22 6 0x0000.0058 UART1 23 7 0x0000.005C SSI0 24 8 0x0000.0060 I2C0 25 9 0x0000.0064 PWM Fault 26 10 0x0000.0068 PWM Generator 0 27 11 0x0000.006C PWM Generator 1 28 12 0x0000.0070 PWM Generator 2 29 13 0x0000.0074 QEI0 30 14 0x0000.0078 ADC0 Sequence 0 31 15 0x0000.007C ADC0 Sequence 1 32 16 0x0000.0080 ADC0 Sequence 2 33 17 0x0000.0084 ADC0 Sequence 3 34 18 0x0000.0088 Watchdog Timers 0 and 1 35 19 0x0000.008C Timer 0A 36 20 0x0000.0090 Timer 0B 37 21 0x0000.0094 Timer 1A 38 22 0x0000.0098 Timer 1B 39 23 0x0000.009C Timer 2A 40 24 0x0000.00A0 Timer 2B 41 25 0x0000.00A4 Analog Comparator 0 42 26 0x0000.00A8 Analog Comparator 1 43 27 - 44 28 0x0000.00B0 System Control 45 29 0x0000.00B4 Flash Memory Control Processor exceptions Reserved 102 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 2-9. Interrupts (continued) 2.5.3 Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 46 30 0x0000.00B8 GPIO Port F 47 31 0x0000.00BC GPIO Port G 48 32 0x0000.00C0 GPIO Port H 49 33 0x0000.00C4 UART2 50 34 0x0000.00C8 SSI1 51 35 0x0000.00CC Timer 3A 52 36 0x0000.00D0 Timer 3B 53 37 0x0000.00D4 I2C1 54 38 0x0000.00D8 QEI1 55 39 0x0000.00DC CAN0 56 40 0x0000.00E0 CAN1 57 41 - 58 42 0x0000.00E8 59 43 - 60 44 0x0000.00F0 61 45 - 62 46 0x0000.00F8 µDMA Software 63 47 0x0000.00FC µDMA Error 64 48 0x0000.0100 ADC1 Sequence 0 65 49 0x0000.0104 ADC1 Sequence 1 66 50 0x0000.0108 ADC1 Sequence 2 67 51 0x0000.010C ADC1 Sequence 3 68 52 0x0000.0110 I2S0 69 53 - 70 54 0x0000.0118 Reserved Ethernet Controller Reserved USB Reserved Reserved GPIO Port J Exception Handlers The processor handles exceptions using: ■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. ■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. ■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. 2.5.4 Vector Table The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in Table 2-8 on page 101. Figure 2-6 on page 104 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code July 22, 2011 103 Texas Instruments-Production Data The Cortex-M3 Processor Figure 2-6. Vector Table Exception number IRQ number 70 54 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Offset 0x0118 . . . 0x004C 0x0048 0x0044 0x0040 0x003C 0x0038 12 11 Vector IRQ54 . . . IRQ2 IRQ1 IRQ0 Systick PendSV Reserved Reserved for Debug -5 10 0x002C 9 SVCall Reserved 8 7 6 -10 5 -11 4 -12 3 -13 2 -14 1 0x0018 0x0014 0x0010 0x000C 0x0008 0x0004 0x0000 Usage fault Bus fault Memory management fault Hard fault NMI Reset Initial SP value On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000.0200 to 0x3FFF.FE00 (see “Vector Table” on page 103). Note that when configuring the VTABLE register, the offset must be aligned on a 512-byte boundary. 2.5.5 Exception Priorities As Table 2-8 on page 101 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see page 155 and page 139. Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. 104 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 2.5.6 Interrupt Priority Grouping To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields: ■ An upper field that defines the group priority ■ A lower field that defines a subpriority within the group Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see page 149. 2.5.7 Exception Entry and Return Descriptions of exception handling use the following terms: ■ Preemption. When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” on page 105 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” on page 106 more information. ■ Return. Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” on page 106 for more information. ■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. ■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On July 22, 2011 105 Texas Instruments-Production Data The Cortex-M3 Processor return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.5.7.1 Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers (see PRIMASK on page 86, FAULTMASK on page 87, and BASEPRI on page 88). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to as stack frame. Figure 2-7. Exception Stack Frame ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack IRQ top of stack Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The stack frame includes the return address, which is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. 2.5.7.2 Exception Return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: ■ An LDM or POP instruction that loads the PC 106 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ A BX instruction using any register ■ An LDR instruction with the PC as the destination EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest four bits of this value provide information on the return stack and processor mode. Table 2-10 on page 107 shows the EXC_RETURN values with a description of the exception return behavior. EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table 2-10. Exception Return Behavior EXC_RETURN[31:0] Description 0xFFFF.FFF0 Reserved 0xFFFF.FFF1 Return to Handler mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFF2 - 0xFFFF.FFF8 Reserved 0xFFFF.FFF9 Return to Thread mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFFA - 0xFFFF.FFFC Reserved 0xFFFF.FFFD Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. 0xFFFF.FFFE - 0xFFFF.FFFF 2.6 Reserved Fault Handling Faults are a subset of the exceptions (see “Exception Model” on page 99). The following conditions generate a fault: ■ A bus error on an instruction fetch or vector table load or a data access. ■ An internally detected error such as an undefined instruction or an attempt to change state with a BX instruction. ■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN). ■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region. 2.6.1 Fault Types Table 2-11 on page 107 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. See page 162 for more information about the fault status registers. Table 2-11. Faults Fault Handler Fault Status Register Bit Name Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT July 22, 2011 107 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-11. Faults (continued) Fault Handler Fault Status Register Bit Name Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) FORCED MPU or default memory mismatch on Memory management instruction access fault Memory Management Fault Status (MFAULTSTAT) IERR MPU or default memory mismatch on Memory management data access fault Memory Management Fault Status (MFAULTSTAT) DERR MPU or default memory mismatch on Memory management exception stacking fault Memory Management Fault Status (MFAULTSTAT) MSTKE MPU or default memory mismatch on Memory management exception unstacking fault Memory Management Fault Status (MFAULTSTAT) MUSTKE Bus error during exception stacking a Bus fault Bus Fault Status (BFAULTSTAT) BSTKE Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF Attempt to enter an invalid instruction Usage fault b set state Usage Fault Status (UFAULTSTAT) INVSTAT Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0 a. Occurs on an access to an XN region even if the MPU is disabled. b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation. 2.6.2 Fault Escalation and Hard Faults All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on page 155). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on page 158). Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in “Exception Model” on page 99. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when: ■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. ■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. ■ An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. 108 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: 2.6.3 Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-12 on page 109. Table 2-12. Fault Status and Fault Address Registers 2.6.4 Handler Status Register Name Address Register Name Register Description Hard fault Hard Fault Status (HFAULTSTAT) - page 168 Memory management Memory Management Fault Status fault (MFAULTSTAT) Memory Management Fault Address (MMADDR) page 162 Bus fault Bus Fault Status (BFAULTSTAT) Bus Fault Address (FAULTADDR) page 162 Usage fault Usage Fault Status (UFAULTSTAT) - page 162 page 169 page 170 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset or an NMI occurs. Note: 2.7 If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state. Power Management The Cortex-M3 processor sleep modes reduce power consumption: ■ Sleep mode stops the processor clock. ■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory. The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used (see page 151). For more information about the behavior of the sleep modes, see “System Control” on page 206. This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to Sleep mode and Deep-sleep mode. 2.7.1 Entering Sleep Modes This section describes the mechanisms software can use to put the processor into one of the sleep modes. July 22, 2011 109 Texas Instruments-Production Data The Cortex-M3 Processor The system can generate spurious wake-up events, for example a debug operation wakes up the processor. Therefore, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. 2.7.1.1 Wait for Interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 110). When the processor executes a WFI instruction, it stops executing instructions and enters sleep mode. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. 2.7.1.2 Wait for Event The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes a WFE instruction, it checks the event register. If the register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction. Typically, this situation occurs if an SEV instruction has been executed. Software cannot access this register directly. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. 2.7.1.3 Sleep-on-Exit If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution of an exception handler, it returns to Thread mode and immediately enters sleep mode. This mechanism can be used in applications that only require the processor to run when an exception occurs. 2.7.2 Wake Up from Sleep Mode The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode. 2.7.2.1 Wake Up from WFI or Sleep-on-Exit Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor clears PRIMASK. For more information about PRIMASK and FAULTMASK, see page 86 and page 87. 2.7.2.2 Wake Up from WFE The processor wakes up if it detects an exception with sufficient priority to cause exception entry. In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about SYSCTRL, see page 151. 110 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 2.8 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 111 lists the supported instructions. Note: In Table 2-13 on page 111: ■ ■ ■ ■ ■ Angle brackets, , enclose alternative forms of the operand Braces, {}, enclose optional operands The Operands column is not exhaustive Op2 is a flexible second operand that can be either a register or a constant Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual. Table 2-13. Cortex-M3 Instruction Summary Mnemonic Operands Brief Description Flags ADC, ADCS {Rd,} Rn, Op2 Add with carry N,Z,C,V ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V ADD, ADDW {Rd,} Rn , #imm12 Add N,Z,C,V ADR Rd, label Load PC-relative address - AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C ASR, ASRS Rd, Rm, Arithmetic shift right N,Z,C B label Branch - BFC Rd, #lsb, #width Bit field clear - BFI Rd, Rn, #lsb, #width Bit field insert - BIC, BICS {Rd,} Rn, Op2 Bit clear N,Z,C BKPT #imm Breakpoint - BL label Branch with link - BLX Rm Branch indirect with link - BX Rm Branch indirect - CBNZ Rn, label Compare and branch if non-zero - CBZ Rn, label Compare and branch if zero - CLREX - Clear exclusive - CLZ Rd, Rm Count leading zeros - CMN Rn, Op2 Compare negative N,Z,C,V CMP Rn, Op2 Compare N,Z,C,V CPSID i Change processor state, disable interrupts - CPSIE i Change processor state, enable interrupts - DMB - Data memory barrier - DSB - Data synchronization barrier - EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C ISB - Instruction synchronization barrier - IT - If-Then condition block - July 22, 2011 111 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description LDM Rn{!}, reglist Load multiple registers, increment after - LDMDB, LDMEA Rn{!}, reglist Load multiple registers, decrement before LDMFD, LDMIA Rn{!}, reglist Load multiple registers, increment after - LDR Rt, [Rn, #offset] Load register with word - LDRB, LDRBT Rt, [Rn, #offset] Load register with byte - LDRD Rt, Rt2, [Rn, #offset] Load register with two bytes - LDREX Rt, [Rn, #offset] Load register exclusive - LDREXB Rt, [Rn] Load register exclusive with byte - LDREXH Rt, [Rn] Load register exclusive with halfword - LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword - LDRSB, LDRSBT Rt, [Rn, #offset] Load register with signed byte - LDRSH, LDRSHT Rt, [Rn, #offset] Load register with signed halfword - LDRT Rt, [Rn, #offset] Load register with word - LSL, LSLS Rd, Rm, Logical shift left N,Z,C LSR, LSRS Rd, Rm, Logical shift right N,Z,C MLA Rd, Rn, Rm, Ra Multiply with accumulate, 32-bit result - MLS Rd, Rn, Rm, Ra Multiply and subtract, 32-bit result - MOV, MOVS Rd, Op2 Move N,Z,C MOV, MOVW Rd, #imm16 Move 16-bit constant N,Z,C MOVT Rd, #imm16 Move top - MRS Rd, spec_reg Move from special register to general register - MSR spec_reg, Rm Move from general register to special register N,Z,C,V MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z MVN, MVNS Rd, Op2 Move NOT N,Z,C NOP - No operation - ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C POP reglist Pop registers from stack - PUSH reglist Push registers onto stack - RBIT Rd, Rn Reverse bits - REV Rd, Rn Reverse byte order in a word - REV16 Rd, Rn Reverse byte order in each halfword - REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend - ROR, RORS Rd, Rm, Rotate right N,Z,C RRX, RRXS Rd, Rm Rotate right with extend N,Z,C RSB, RSBS {Rd,} Rn, Op2 Reverse subtract N,Z,C,V SBC, SBCS {Rd,} Rn, Op2 Subtract with carry N,Z,C,V SBFX Rd, Rn, #lsb, #width Signed bit field extract - 112 Flags - July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags SDIV {Rd,} Rn, Rm Signed divide - SEV - Send event - SMLAL RdLo, RdHi, Rn, Rm Signed multiply with accumulate (32x32+64), 64-bit result - SMULL RdLo, RdHi, Rn, Rm Signed multiply (32x32), 64-bit result - SSAT Rd, #n, Rm {,shift #s} Signed saturate Q STM Rn{!}, reglist Store multiple registers, increment after - STMDB, STMEA Rn{!}, reglist Store multiple registers, decrement before STMFD, STMIA Rn{!}, reglist Store multiple registers, increment after - STR Rt, [Rn {, #offset}] Store register word - STRB, STRBT Rt, [Rn {, #offset}] Store register byte - STRD Rt, Rt2, [Rn {, #offset}] Store register two words - STREX Rt, Rt, [Rn {, #offset}] Store register exclusive - STREXB Rd, Rt, [Rn] Store register exclusive byte - STREXH Rd, Rt, [Rn] Store register exclusive halfword - STRH, STRHT Rt, [Rn {, #offset}] Store register halfword - STRSB, STRSBT Rt, [Rn {, #offset}] Store register signed byte - STRSH, STRSHT Rt, [Rn {, #offset}] Store register signed halfword - STRT Rt, [Rn {, #offset}] Store register word - SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V SUB, SUBW {Rd,} Rn, #imm12 Subtract 12-bit constant N,Z,C,V SVC #imm Supervisor call - SXTB {Rd,} Rm {,ROR #n} Sign extend a byte - SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword - TBB [Rn, Rm] Table branch byte - TBH [Rn, Rm, LSL #1] Table branch halfword - TEQ Rn, Op2 Test equivalence N,Z,C TST Rn, Op2 Test N,Z,C UBFX Rd, Rn, #lsb, #width Unsigned bit field extract - UDIV {Rd,} Rn, Rm Unsigned divide - UMLAL RdLo, RdHi, Rn, Rm Unsigned multiply with accumulate (32x32+32+32), 64-bit result - UMULL RdLo, RdHi, Rn, Rm Unsigned multiply (32x 2), 64-bit result - USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q UXTB {Rd,} Rm, {,ROR #n} Zero extend a Byte - UXTH {Rd,} Rm, {,ROR #n} Zero extend a Halfword - USAT Rd, #n, Rm {,shift #s} Unsigned saturate Q UXTB {Rd,} Rm {,ROR #n} Zero extend a byte - UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword - WFE - Wait for event - WFI - Wait for interrupt - July 22, 2011 - 113 Texas Instruments-Production Data Cortex-M3 Peripherals 3 Cortex-M3 Peripherals ® This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals, including: ■ SysTick (see page 114) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. ■ Nested Vectored Interrupt Controller (NVIC) (see page 115) – Facilitates low-latency exception and interrupt handling – Controls power management – Implements system control registers ■ System Control Block (SCB) (see page 117) Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. ■ Memory Protection Unit (MPU) (see page 117) Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. Table 3-1 on page 114 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed. Table 3-1. Core Peripheral Register Regions Address Core Peripheral Description (see page ...) 0xE000.E010-0xE000.E01F System Timer 114 0xE000.E100-0xE000.E4EF Nested Vectored Interrupt Controller 115 System Control Block 117 Memory Protection Unit 117 0xE000.EF00-0xE000.EF03 0xE000.E008-0xE000.E00F 0xE000.ED00-0xE000.ED3F 0xE000.ED90-0xE000.EDB8 3.1 Functional Description This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals: SysTick, NVIC, SCB and MPU. 3.1.1 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. 114 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter used to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNT bit in the STCTRL control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. The timer consists of three registers: ■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the counter's wrap value. ■ SysTick Current Value (STCURRENT): The current value of the counter. When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter reaches zero, the COUNT status bit is set. The COUNT bit clears on reads. Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. The SysTick counter runs on the system clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers. Note: 3.1.2 When the processor is halted for debugging, the counter does not decrement. Nested Vectored Interrupt Controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ■ 50 interrupts. ■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ■ Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). July 22, 2011 115 Texas Instruments-Production Data Cortex-M3 Peripherals The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. 3.1.2.1 Level-Sensitive and Pulse Interrupts The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts” on page 116 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 3.1.2.2 Hardware and Software Control of Interrupts The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: ■ The NVIC detects that the interrupt signal is High and the interrupt is not active. ■ The NVIC detects a rising edge on the interrupt signal. ■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit in the PEND0 register on page 133 or SWTRIG on page 141. A pending interrupt remains pending until one of the following: ■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. ■ Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. 116 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller – For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. 3.1.3 System Control Block (SCB) The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. 3.1.4 Memory Protection Unit (MPU) This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines eight separate memory regions, 0-7, and a background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” on page 92 for more information). Table 3-2 on page 117 shows the possible MPU region attributes. See the section called “MPU Configuration for a Stellaris Microcontroller” on page 121 for guidelines for programming a microcontroller implementation. Table 3-2. Memory Attributes Summary Memory Type Description Strongly Ordered All accesses to Strongly Ordered memory occur in program order. Device Memory-mapped peripherals Normal Normal memory To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: ■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. July 22, 2011 117 Texas Instruments-Production Data Cortex-M3 Peripherals The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. 3.1.4.1 Updating an MPU Region To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can be programmed separately or with a multiple-word write to program all of these registers. You can use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using an STM instruction. Updating an MPU Region Using Separate Words This example simple code configures one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER STR R1, [R0, #0x0] STR R4, [R0, #0x4] STRH R2, [R0, #0x8] STRH R3, [R0, #0xA] ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Region Base Address Region Size and Enable Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER STR R1, [R0, #0x0] BIC R2, R2, #1 STRH R2, [R0, #0x8] STR R4, [R0, #0x4] STRH R3, [R0, #0xA] ORR R2, #1 STRH R2, [R0, #0x8] ; ; ; ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Disable Region Size and Enable Region Base Address Region Attribute Enable Region Size and Enable Software must use memory barrier instructions: ■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings. ■ After MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region. 118 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is required after changing MPU settings, such as at the end of context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISB is not required. Updating an MPU Region Using Multi-Word Writes The MPU can be programmed directly using multi-word writes, depending how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region number, address, attribute, size and enable This operation can be done in two words for pre-packed information, meaning that the MPU Region Base Address (MPUBASE) register (see page 175) contains the required region number and has the VALID bit set. This method can be used when the data is statically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and region number combined ; with VALID (bit 4) set STR R2, [R0, #0x4] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0,=MPUBASE ; 0xE000ED9C, MPU Region Base register STM R0, {R1-R2} ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 177) to disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the most-significant bit controls the last subregion. Disabling a subregion means another region July 22, 2011 119 Texas Instruments-Production Data Cortex-M3 Peripherals overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be configured to 0x00, otherwise the MPU behavior is unpredictable. Example of SRD Use Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 120 shows. Figure 3-1. SRD Use Example Region 2, with subregions Region 1 Base address of both regions 3.1.4.2 Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB Disabled subregion 64KB Disabled subregion 0 MPU Access Permission Attributes The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 3-3 on page 120 shows the encodings for the TEX, C, B, and S access permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M3 does not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration for a Stellaris Microcontroller” on page 121 for information on programming the MPU for Stellaris implementations. Table 3-3. TEX, S, C, and B Bit Field Encoding TEX S 000b x C B Memory Type Shareability Other Attributes a 0 0 Strongly Ordered Shareable - a - 000 x 0 1 Device Shareable 000 0 1 0 Normal Not shareable 000 1 1 0 Normal Shareable 000 0 1 1 Normal Not shareable 000 1 1 1 Normal Shareable 001 0 0 0 Normal Not shareable 001 1 001 x Outer and inner write-through. No write allocate. 0 0 Normal Shareable Outer and inner noncacheable. a 0 1 Reserved encoding - - a 001 x 1 0 Reserved encoding - - 001 0 1 1 Normal Not shareable 001 1 1 1 Normal Shareable Outer and inner write-back. Write and read allocate. 120 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 3-3. TEX, S, C, and B Bit Field Encoding (continued) TEX S Other Attributes 0 0 Device Not shareable Nonshared Device. a 0 1 Reserved encoding - - x Shareability x Memory Type 010 B 010 C a a a 010 x 1 x Reserved encoding - - 1BB 0 A A Normal Not shareable 1BB 1 A A Normal Shareable Cached memory (BB = outer policy, AA = inner policy). See Table 3-4 for the encoding of the AA and BB bits. a. The MPU ignores the value of this bit. Table 3-4 on page 121 shows the cache policy for memory attribute encodings with a TEX value in the range of 0x4-0x7. Table 3-4. Cache Policy for Memory Attribute Encoding Encoding, AA or BB Corresponding Cache Policy 00 Non-cacheable 01 Write back, write and read allocate 10 Write through, no write allocate 11 Write back, no write allocate Table 3-5 on page 121 shows the AP encodings in the MPUATTR register that define the access permissions for privileged and unprivileged software. Table 3-5. AP Bit Field Encoding AP Bit Field Privileged Permissions Unprivileged Permissions Description 000 No access No access All accesses generate a permission fault. 001 R/W No access Access from privileged software only. 010 R/W RO Writes by unprivileged software generate a permission fault. 011 R/W R/W Full access. 100 Unpredictable Unpredictable Reserved. 101 RO No access Reads by privileged software only. 110 RO RO Read-only, by privileged or unprivileged software. 111 RO RO Read-only, by privileged or unprivileged software. MPU Configuration for a Stellaris Microcontroller Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 121. Table 3-6. Memory Region Attributes for Stellaris Microcontrollers Memory Region TEX S C B Memory Type and Attributes Flash memory 000b 0 1 0 Normal memory, non-shareable, write-through Internal SRAM 000b 1 1 0 Normal memory, shareable, write-through July 22, 2011 121 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-6. Memory Region Attributes for Stellaris Microcontrollers (continued) Memory Region TEX S C B Memory Type and Attributes External SRAM 000b 1 1 1 Normal memory, shareable, write-back, write-allocate Peripherals 000b 1 0 1 Device memory, shareable In current Stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. 3.1.4.3 MPU Mismatch When an access violates the MPU permissions, the processor generates a memory management fault (see “Exceptions and Interrupts” on page 90 for more information). The MFAULTSTAT register indicates the cause of the fault. See page 162 for more information. 3.2 Register Map Table 3-7 on page 122 lists the Cortex-M3 Peripheral SysTick, NVIC, SCB, and MPU registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note: Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table 3-7. Peripherals Register Map Offset Name Type Reset Description See page System Timer (SysTick) Registers 0x010 STCTRL R/W 0x0000.0004 SysTick Control and Status Register 125 0x014 STRELOAD R/W 0x0000.0000 SysTick Reload Value Register 127 0x018 STCURRENT R/WC 0x0000.0000 SysTick Current Value Register 128 Nested Vectored Interrupt Controller (NVIC) Registers 0x100 EN0 R/W 0x0000.0000 Interrupt 0-31 Set Enable 129 0x104 EN1 R/W 0x0000.0000 Interrupt 32-54 Set Enable 130 0x180 DIS0 R/W 0x0000.0000 Interrupt 0-31 Clear Enable 131 0x184 DIS1 R/W 0x0000.0000 Interrupt 32-54 Clear Enable 132 0x200 PEND0 R/W 0x0000.0000 Interrupt 0-31 Set Pending 133 0x204 PEND1 R/W 0x0000.0000 Interrupt 32-54 Set Pending 134 0x280 UNPEND0 R/W 0x0000.0000 Interrupt 0-31 Clear Pending 135 0x284 UNPEND1 R/W 0x0000.0000 Interrupt 32-54 Clear Pending 136 0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0-31 Active Bit 137 0x304 ACTIVE1 RO 0x0000.0000 Interrupt 32-54 Active Bit 138 0x400 PRI0 R/W 0x0000.0000 Interrupt 0-3 Priority 139 122 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 3-7. Peripherals Register Map (continued) Description See page Offset Name Type Reset 0x404 PRI1 R/W 0x0000.0000 Interrupt 4-7 Priority 139 0x408 PRI2 R/W 0x0000.0000 Interrupt 8-11 Priority 139 0x40C PRI3 R/W 0x0000.0000 Interrupt 12-15 Priority 139 0x410 PRI4 R/W 0x0000.0000 Interrupt 16-19 Priority 139 0x414 PRI5 R/W 0x0000.0000 Interrupt 20-23 Priority 139 0x418 PRI6 R/W 0x0000.0000 Interrupt 24-27 Priority 139 0x41C PRI7 R/W 0x0000.0000 Interrupt 28-31 Priority 139 0x420 PRI8 R/W 0x0000.0000 Interrupt 32-35 Priority 139 0x424 PRI9 R/W 0x0000.0000 Interrupt 36-39 Priority 139 0x428 PRI10 R/W 0x0000.0000 Interrupt 40-43 Priority 139 0x42C PRI11 R/W 0x0000.0000 Interrupt 44-47 Priority 139 0x430 PRI12 R/W 0x0000.0000 Interrupt 48-51 Priority 139 0x434 PRI13 R/W 0x0000.0000 Interrupt 52-54 Priority 139 0xF00 SWTRIG WO 0x0000.0000 Software Trigger Interrupt 141 System Control Block (SCB) Registers 0x008 ACTLR R/W 0x0000.0000 Auxiliary Control 142 0xD00 CPUID RO 0x412F.C230 CPU ID Base 144 0xD04 INTCTRL R/W 0x0000.0000 Interrupt Control and State 145 0xD08 VTABLE R/W 0x0000.0000 Vector Table Offset 148 0xD0C APINT R/W 0xFA05.0000 Application Interrupt and Reset Control 149 0xD10 SYSCTRL R/W 0x0000.0000 System Control 151 0xD14 CFGCTRL R/W 0x0000.0200 Configuration and Control 153 0xD18 SYSPRI1 R/W 0x0000.0000 System Handler Priority 1 155 0xD1C SYSPRI2 R/W 0x0000.0000 System Handler Priority 2 156 0xD20 SYSPRI3 R/W 0x0000.0000 System Handler Priority 3 157 0xD24 SYSHNDCTRL R/W 0x0000.0000 System Handler Control and State 158 0xD28 FAULTSTAT R/W1C 0x0000.0000 Configurable Fault Status 162 0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 168 0xD34 MMADDR R/W - Memory Management Fault Address 169 0xD38 FAULTADDR R/W - Bus Fault Address 170 MPU Type 171 Memory Protection Unit (MPU) Registers 0xD90 MPUTYPE RO 0x0000.0800 July 22, 2011 123 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-7. Peripherals Register Map (continued) Offset Name Type Reset Description See page 0xD94 MPUCTRL R/W 0x0000.0000 MPU Control 172 0xD98 MPUNUMBER R/W 0x0000.0000 MPU Region Number 174 0xD9C MPUBASE R/W 0x0000.0000 MPU Region Base Address 175 0xDA0 MPUATTR R/W 0x0000.0000 MPU Region Attribute and Size 177 0xDA4 MPUBASE1 R/W 0x0000.0000 MPU Region Base Address Alias 1 175 0xDA8 MPUATTR1 R/W 0x0000.0000 MPU Region Attribute and Size Alias 1 177 0xDAC MPUBASE2 R/W 0x0000.0000 MPU Region Base Address Alias 2 175 0xDB0 MPUATTR2 R/W 0x0000.0000 MPU Region Attribute and Size Alias 2 177 0xDB4 MPUBASE3 R/W 0x0000.0000 MPU Region Base Address Alias 3 175 0xDB8 MPUATTR3 R/W 0x0000.0000 MPU Region Attribute and Size Alias 3 177 3.3 System Timer (SysTick) Register Descriptions This section lists and describes the System Timer registers, in numerical order by address offset. 124 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 Note: This register can only be accessed from privileged mode. The SysTick STCTRL register enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type R/W, reset 0x0000.0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 16 COUNT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 CLK_SRC INTEN ENABLE R/W 1 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 COUNT RO 0 Count Flag Value Description 0 The SysTick timer has not counted to 0 since the last time this bit was read. 1 The SysTick timer has counted to 0 since the last time this bit was read. This bit is cleared by a read of the register or if the STCURRENT register is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in the AHB-AP Control Register is clear. Otherwise, the COUNT bit is not changed by the debugger read. See the ARM® Debug Interface V5 Architecture Specification for more information on MasterType. 15:3 reserved RO 0x000 2 CLK_SRC R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Source Value Description 0 External reference clock. (Not implemented for Stellaris microcontrollers.) 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. July 22, 2011 125 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 1 INTEN R/W 0 0 ENABLE R/W 0 Description Interrupt Enable Value Description 0 Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. 1 An interrupt is generated to the NVIC when SysTick counts to 0. Enable Value Description 0 The counter is disabled. 1 Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. 126 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 Note: This register can only be accessed from privileged mode. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD field. SysTick Reload Value Register (STRELOAD) Base 0xE000.E000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 RO 0 RO 0 RO 0 RO 0 15 14 13 R/W 0 R/W 0 R/W 0 27 26 25 24 23 22 21 20 18 17 16 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 19 RELOAD RELOAD Type Reset Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 RELOAD R/W 0x00.0000 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. July 22, 2011 127 Texas Instruments-Production Data Cortex-M3 Peripherals Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 Note: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000 Offset 0x018 Type R/WC, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 reserved Type Reset 20 19 18 17 16 CURRENT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 CURRENT Type Reset R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 R/WC 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:0 CURRENT R/WC 0x00.0000 Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. 3.4 NVIC Register Descriptions This section lists and describes the NVIC registers, in numerical order by address offset. The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any other unprivileged mode access causes a bus fault. Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An interrupt can enter the pending state even if it is disabled. Before programming the VTABLE register to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For more information, see page 148. 128 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 Note: This register can only be accessed from privileged mode. The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 102 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 0-31 Set Enable (EN0) Base 0xE000.E000 Offset 0x100 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 INT R/W R/W 0 Reset R/W 0 Description 0x0000.0000 Interrupt Enable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. July 22, 2011 129 Texas Instruments-Production Data Cortex-M3 Peripherals Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104 Note: This register can only be accessed from privileged mode. The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 102 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 32-54 Set Enable (EN1) Base 0xE000.E000 Offset 0x104 Type R/W, reset 0x0000.0000 31 30 29 28 RO 0 RO 0 RO 0 RO 0 15 14 13 R/W 0 R/W 0 R/W 0 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset INT INT Type Reset Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT R/W 0x00.0000 Interrupt Enable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. 130 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 Note: This register can only be accessed from privileged mode. The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 102 for interrupt assignments. Interrupt 0-31 Clear Enable (DIS0) Base 0xE000.E000 Offset 0x180 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. July 22, 2011 131 Texas Instruments-Production Data Cortex-M3 Peripherals Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184 Note: This register can only be accessed from privileged mode. The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 102 for interrupt assignments. Interrupt 32-54 Clear Enable (DIS1) Base 0xE000.E000 Offset 0x184 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset 19 18 17 16 INT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT R/W 0x00.0000 Interrupt Disable Value Description 0 On a read, indicates the interrupt is disabled. On a write, no effect. 1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. 132 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 Note: This register can only be accessed from privileged mode. The PEND0 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 102 for interrupt assignments. Interrupt 0-31 Set Pending (PEND0) Base 0xE000.E000 Offset 0x200 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Set Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. July 22, 2011 133 Texas Instruments-Production Data Cortex-M3 Peripherals Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204 Note: This register can only be accessed from privileged mode. The PEND1 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 102 for interrupt assignments. Interrupt 32-54 Set Pending (PEND1) Base 0xE000.E000 Offset 0x204 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset 19 18 17 16 INT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT R/W 0x00.0000 Interrupt Set Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. 134 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 Note: This register can only be accessed from privileged mode. The UNPEND0 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 102 for interrupt assignments. Interrupt 0-31 Clear Pending (UNPEND0) Base 0xE000.E000 Offset 0x280 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT R/W Reset Description 0x0000.0000 Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. July 22, 2011 135 Texas Instruments-Production Data Cortex-M3 Peripherals Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 Note: This register can only be accessed from privileged mode. The UNPEND1 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 102 for interrupt assignments. Interrupt 32-54 Clear Pending (UNPEND1) Base 0xE000.E000 Offset 0x284 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset 19 18 17 16 INT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 INT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT R/W 0x00.0000 Interrupt Clear Pending Value Description 0 On a read, indicates that the interrupt is not pending. On a write, no effect. 1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 136 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 Note: This register can only be accessed from privileged mode. The ACTIVE0 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 102 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 0-31 Active Bit (ACTIVE0) Base 0xE000.E000 Offset 0x300 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 INT Type Reset INT Type Reset Bit/Field Name Type 31:0 INT RO Reset Description 0x0000.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. July 22, 2011 137 Texas Instruments-Production Data Cortex-M3 Peripherals Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 Note: This register can only be accessed from privileged mode. The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit 22 corresponds to Interrupt 54. See Table 2-9 on page 102 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 32-54 Active Bit (ACTIVE1) Base 0xE000.E000 Offset 0x304 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset 19 18 17 16 INT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 INT Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:23 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:0 INT RO 0x00.0000 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. 138 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 Register 25: Interrupt 44-47 Priority (PRI11), offset 0x42C Register 26: Interrupt 48-51 Priority (PRI12), offset 0x430 Register 27: Interrupt 52-54 Priority (PRI13), offset 0x434 Note: This register can only be accessed from privileged mode. The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: PRIn Register Bit Field Interrupt Bits 31:29 Interrupt [4n+3] Bits 23:21 Interrupt [4n+2] Bits 15:13 Interrupt [4n+1] Bits 7:5 Interrupt [4n] See Table 2-9 on page 102 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register (see page 149) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. July 22, 2011 139 Texas Instruments-Production Data Cortex-M3 Peripherals Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 INTD Type Reset 25 24 23 reserved 22 21 20 19 INTC 18 17 16 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 INTB Type Reset 26 R/W 0 R/W 0 reserved RO 0 INTA Bit/Field Name Type Reset 31:29 INTD R/W 0x0 R/W 0 reserved RO 0 Description Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 INTC R/W 0x0 Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 INTB R/W 0x0 Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 INTA R/W 0x0 Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 140 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 28: Software Trigger Interrupt (SWTRIG), offset 0xF00 Note: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). See Table 2-9 on page 102 for interrupt assignments. When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 153) is set, unprivileged software can access the SWTRIG register. Software Trigger Interrupt (SWTRIG) Base 0xE000.E000 Offset 0xF00 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 INTID Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:0 INTID WO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. 3.5 System Control Block (SCB) Register Descriptions This section lists and describes the System Control Block (SCB) registers, in numerical order by address offset. The SCB registers can only be accessed from privileged mode. All registers must be accessed with aligned word accesses except for the FAULTSTAT and SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. July 22, 2011 141 Texas Instruments-Production Data Cortex-M3 Peripherals Register 29: Auxiliary Control (ACTLR), offset 0x008 Note: This register can only be accessed from privileged mode. The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M3 processor and does not normally require modification. Auxiliary Control (ACTLR) Base 0xE000.E000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2 DISFOLD R/W 0 DISFOLD DISWBUF DISMCYC RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Disable IT Folding Value Description 0 No effect. 1 Disables IT folding. In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit before executing the task, to disable IT folding. 1 DISWBUF R/W 0 Disable Write Buffer Value Description 0 No effect. 1 Disables write buffer use during default memory map accesses. In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. Note: This bit only affects write buffers implemented in the Cortex-M3 processor. 142 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 DISMCYC R/W 0 Description Disable Interrupts of Multiple Cycle Instructions Value Description 0 No effect. 1 Disables interruption of load multiple and store multiple instructions. In this situation, the interrupt latency of the processor is increased because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. July 22, 2011 143 Texas Instruments-Production Data Cortex-M3 Peripherals Register 30: CPU ID Base (CPUID), offset 0xD00 Note: This register can only be accessed from privileged mode. The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x412F.C230 31 30 29 28 27 26 25 24 23 22 IMP Type Reset 21 20 19 18 VAR R0 0 R0 1 R0 0 R0 0 R0 0 R0 0 R0 0 R0 1 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PARTNO Type Reset RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 17 16 RO 1 RO 1 1 0 RO 0 RO 0 CON REV RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 IMP R0 0x41 Implementer Code RO 1 RO 1 RO 0 RO 0 Value Description 0x41 ARM 23:20 VAR RO 0x2 Variant Number Value Description 0x2 19:16 CON RO 0xF The rn value in the rnpn product revision identifier, for example, the 2 in r2p0. Constant Value Description 0xF 15:4 PARTNO RO 0xC23 Always reads as 0xF. Part Number Value Description 0xC23 Cortex-M3 processor. 3:0 REV RO 0x0 Revision Number Value Description 0x0 The pn value in the rnpn product revision identifier, for example, the 0 in r2p0. 144 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 31: Interrupt Control and State (INTCTRL), offset 0xD04 Note: This register can only be accessed from privileged mode. The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits. Interrupt Control and State (INTCTRL) Base 0xE000.E000 Offset 0xD04 Type R/W, reset 0x0000.0000 31 NMISET Type Reset 30 29 reserved 28 26 25 24 PENDSV UNPENDSV PENDSTSET PENDSTCLR reserved 23 22 21 ISRPRE ISRPEND 20 19 18 reserved 17 16 VECPEND R/W 0 RO 0 RO 0 R/W 0 WO 0 R/W 0 WO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 VECPEND Type Reset 27 RO 0 RETBASE RO 0 reserved RO 0 Bit/Field Name Type Reset 31 NMISET R/W 0 VECACT RO 0 Description NMI Set Pending Value Description 0 On a read, indicates an NMI exception is not pending. On a write, no effect. 1 On a read, indicates an NMI exception is pending. On a write, changes the NMI exception state to pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 30:29 reserved RO 0x0 28 PENDSV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PendSV Set Pending Value Description 0 On a read, indicates a PendSV exception is not pending. On a write, no effect. 1 On a read, indicates a PendSV exception is pending. On a write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to the UNPENDSV bit. July 22, 2011 145 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 27 UNPENDSV WO 0 Description PendSV Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the PendSV exception. This bit is write only; on a register read, its value is unknown. 26 PENDSTSET R/W 0 SysTick Set Pending Value Description 0 On a read, indicates a SysTick exception is not pending. On a write, no effect. 1 On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception state to pending. This bit is cleared by writing a 1 to the PENDSTCLR bit. 25 PENDSTCLR WO 0 SysTick Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the SysTick exception. This bit is write only; on a register read, its value is unknown. 24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23 ISRPRE RO 0 Debug Interrupt Handling Value Description 0 The release from halt does not take an interrupt. 1 The release from halt takes an interrupt. This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. 22 ISRPEND RO 0 Interrupt Pending Value Description 0 No interrupt is pending. 1 An interrupt is pending. This bit provides status for all interrupts excluding NMI and Faults. 21:19 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 146 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 18:12 VECPEND RO 0x00 Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. Value Description 0x00 No exceptions are pending 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x46 Interrupt Vector 54 0x47-0x7F Reserved 11 RETBASE RO 0 Return to Base Value Description 0 There are preempted active exceptions to execute. 1 There are no active exceptions, or the currently executing exception is the only active exception. This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero). 10:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:0 VECACT RO 0x00 Interrupt Pending Vector Number This field contains the active exception number. The exception numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 82). July 22, 2011 147 Texas Instruments-Production Data Cortex-M3 Peripherals Register 32: Vector Table Offset (VTABLE), offset 0xD08 Note: This register can only be accessed from privileged mode. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type R/W, reset 0x0000.0000 31 30 reserved Type Reset 29 28 27 26 25 24 23 BASE RO 0 RO 0 R/W 0 15 14 13 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 OFFSET R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 OFFSET Type Reset R/W 0 R/W 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:30 reserved RO 0x0 29 BASE R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Vector Table Base Value Description 28:9 OFFSET R/W 0x000.00 0 The vector table is in the code memory region. 1 The vector table is in the SRAM memory region. Vector Table Offset When configuring the OFFSET field, the offset must be aligned to the number of exception entries in the vector table. Because there are 54 interrupts, the minimum alignment is 128 words. 8:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 148 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 33: Application Interrupt and Reset Control (APINT), offset 0xD0C Note: This register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored. The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table 3-8 on page 149 shows how the PRIGROUP value controls this split. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29. Note: Determining preemption of an exception uses only the group priority field. Table 3-8. Interrupt Priority Levels a PRIGROUP Bit Field Binary Point Group Priority Field Subpriority Field Group Priorities Subpriorities 0x0 - 0x4 bxxx. [7:5] None 8 1 0x5 bxx.y [7:6] [5] 4 2 0x6 bx.yy [7] [6:5] 2 4 0x7 b.yyy None [7:5] 1 8 a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. Application Interrupt and Reset Control (APINT) Base 0xE000.E000 Offset 0xD0C Type R/W, reset 0xFA05.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 5 4 3 2 1 0 VECTKEY Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 15 14 13 12 11 10 reserved ENDIANESS Type Reset RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 0 R/W 0 R/W 0 9 8 7 6 PRIGROUP RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 VECTKEY R/W 0xFA05 reserved R/W 0 RO 0 RO 0 RO 0 SYSRESREQ VECTCLRACT VECTRESET RO 0 RO 0 WO 0 WO 0 WO 0 Description Register Key This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. 15 ENDIANESS RO 0 Data Endianess The Stellaris implementation uses only little-endian mode so this is cleared to 0. 14:11 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 149 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 10:8 PRIGROUP R/W 0x0 Description Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-8 on page 149 for more information). 7:3 reserved RO 0x0 2 SYSRESREQ WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Reset Request Value Description 0 No effect. 1 Resets the core and all on-chip peripherals except the Debug interface. This bit is automatically cleared during the reset of the core and reads as 0. 1 VECTCLRACT WO 0 Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 0 VECTRESET WO 0 System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 150 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 34: System Control (SYSCTRL), offset 0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.00 4 SEVONPEND R/W 0 RO 0 RO 0 RO 0 RO 0 4 3 SEVONPEND reserved R/W 0 RO 0 SLEEPDEEP SLEEPEXIT R/W 0 R/W 0 0 reserved RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Wake Up on Pending Value Description 0 Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor. When an event or interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of a SEV instruction or an external event. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 SLEEPDEEP R/W 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. July 22, 2011 151 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 1 SLEEPEXIT R/W 0 Description Sleep on ISR Exit Value Description 0 When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. 1 When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 152 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 35: Configuration and Control (CFGCTRL), offset 0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 141). Configuration and Control (CFGCTRL) Base 0xE000.E000 Offset 0xD14 Type R/W, reset 0x0000.0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 reserved STKALIGN BFHFNMIGN RO 0 RO 0 R/W 1 Bit/Field Name Type Reset 31:10 reserved RO 0x0000.00 9 STKALIGN R/W 1 R/W 0 RO 0 RO 0 RO 0 4 3 2 1 0 DIV0 UNALIGNED reserved MAINPEND BASETHR R/W 0 R/W 0 RO 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Stack Alignment on Exception Entry Value Description 0 The stack is 4-byte aligned. 1 The stack is 8-byte aligned. On exception entry, the processor uses bit 9 of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 8 BFHFNMIGN R/W 0 Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK escalated handlers. Value Description 0 Data bus faults caused by load and store instructions cause a lock-up. 1 Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 153 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 4 DIV0 R/W 0 Description Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. Value Description 3 UNALIGNED R/W 0 0 Do not trap on divide by 0. A divide by zero returns a quotient of 0. 1 Trap on divide by 0. Trap on Unaligned Access Value Description 0 Do not trap on unaligned halfword and word accesses. 1 Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 MAINPEND R/W 0 Allow Main Interrupt Trigger Value Description 0 BASETHR R/W 0 0 Disables unprivileged software access to the SWTRIG register. 1 Enables unprivileged software access to the SWTRIG register (see page 141). Thread State Control Value Description 0 The processor can enter Thread mode only when no exception is active. 1 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 106 for more information). 154 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 36: System Handler Priority 1 (SYSPRI1), offset 0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 reserved Type Reset RO 0 15 RO 0 RO 0 RO 0 RO 0 14 13 12 11 BUS Type Reset R/W 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 10 9 8 7 reserved R/W 0 RO 0 22 21 20 19 USAGE RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 MEM RO 0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 USAGE R/W 0x0 Usage Fault Priority This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 20:16 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 BUS R/W 0x0 Bus Fault Priority This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 12:8 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 MEM R/W 0x0 Memory Management Fault Priority This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 4:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 155 Texas Instruments-Production Data Cortex-M3 Peripherals Register 37: System Handler Priority 2 (SYSPRI2), offset 0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 SVC Type Reset 22 21 20 19 18 17 16 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:29 SVC R/W 0x0 RO 0 Description SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 28:0 reserved RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 156 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 38: System Handler Priority 3 (SYSPRI3), offset 0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type R/W, reset 0x0000.0000 31 30 29 28 27 TICK Type Reset 26 25 24 23 reserved R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 22 21 20 19 PENDSV R/W 0 R/W 0 RO 0 RO 0 6 5 4 3 DEBUG RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:29 TICK R/W 0x0 RO 0 R/W 0 R/W 0 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 reserved reserved R/W 0 RO 0 RO 0 RO 0 Description SysTick Exception Priority This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority. 28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 PENDSV R/W 0x0 PendSV Priority This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority. 20:8 reserved RO 0x000 7:5 DEBUG R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. 4:0 reserved RO 0x0.0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 157 Texas Instruments-Production Data Cortex-M3 Peripherals Register 39: System Handler Control and State (SYSHNDCTRL), offset 0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. Caution – Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified. System Handler Control and State (SYSHNDCTRL) Base 0xE000.E000 Offset 0xD24 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 SVC BUSP MEMP USAGEP R/W 0 R/W 0 R/W 0 R/W 0 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 USAGE BUS MEM R/W 0 R/W 0 R/W 0 10 9 8 7 6 5 4 3 2 1 0 TICK PNDSV reserved MON SVCA R/W 0 R/W 0 RO 0 R/W 0 R/W 0 USGA reserved BUSA MEMA R/W 0 RO 0 R/W 0 R/W 0 reserved Type Reset Type Reset reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 USAGE R/W 0 Usage Fault Enable Value Description 17 BUS R/W 0 0 Disables the usage fault exception. 1 Enables the usage fault exception. Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. 158 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 16 MEM R/W 0 Description Memory Management Fault Enable Value Description 15 SVC R/W 0 0 Disables the memory management fault exception. 1 Enables the memory management fault exception. SVC Call Pending Value Description 0 An SVC call exception is not pending. 1 An SVC call exception is pending. This bit can be modified to change the pending status of the SVC call exception. 14 BUSP R/W 0 Bus Fault Pending Value Description 0 A bus fault exception is not pending. 1 A bus fault exception is pending. This bit can be modified to change the pending status of the bus fault exception. 13 MEMP R/W 0 Memory Management Fault Pending Value Description 0 A memory management fault exception is not pending. 1 A memory management fault exception is pending. This bit can be modified to change the pending status of the memory management fault exception. 12 USAGEP R/W 0 Usage Fault Pending Value Description 0 A usage fault exception is not pending. 1 A usage fault exception is pending. This bit can be modified to change the pending status of the usage fault exception. 11 TICK R/W 0 SysTick Exception Active Value Description 0 A SysTick exception is not active. 1 A SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. July 22, 2011 159 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 10 PNDSV R/W 0 Description PendSV Exception Active Value Description 0 A PendSV exception is not active. 1 A PendSV exception is active. This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 MON R/W 0 Debug Monitor Active Value Description 7 SVCA R/W 0 0 The Debug monitor is not active. 1 The Debug monitor is active. SVC Call Active Value Description 0 SVC call is not active. 1 SVC call is active. This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit. 6:4 reserved RO 0x0 3 USGA R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Usage Fault Active Value Description 0 Usage fault is not active. 1 Usage fault is active. This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BUSA R/W 0 Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. 160 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 MEMA R/W 0 Description Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. July 22, 2011 161 Texas Instruments-Production Data Cortex-M3 Peripherals Register 40: Configurable Fault Status (FAULTSTAT), offset 0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: ■ Usage Fault Status (UFAULTSTAT), bits 31:16 ■ Bus Fault Status (BFAULTSTAT), bits 15:8 ■ Memory Management Fault Status (MFAULTSTAT), bits 7:0 FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows: ■ ■ ■ ■ ■ The complete FAULTSTAT register, with a word access to offset 0xD28 The MFAULTSTAT, with a byte access to offset 0xD28 The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28 The BFAULTSTAT, with a byte access to offset 0xD29 The UFAULTSTAT, with a halfword access to offset 0xD2A Bits are cleared by writing a 1 to them. In a fault handler, the true faulting address can be determined by: 1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address (FAULTADDR) value. 2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the MMADDR or FAULTADDR contents are valid. Software must follow this sequence because another higher priority exception might change the MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the MMADDR or FAULTADDR value. Configurable Fault Status (FAULTSTAT) Base 0xE000.E000 Offset 0xD28 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 reserved Type Reset RO 0 RO 0 RO 0 15 14 13 BFARV Type Reset R/W1C 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 25 24 DIV0 UNALIGN R/W1C 0 R/W1C 0 23 22 21 20 reserved RO 0 RO 0 RO 0 6 5 12 11 10 9 8 7 BSTKE BUSTKE IMPRE PRECISE IBUS MMARV R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved RO 0 RO 0 RO 0 19 18 17 16 NOCP INVPC INVSTAT UNDEF R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 4 3 2 1 0 MSTKE MUSTKE reserved DERR IERR R/W1C 0 R/W1C 0 RO 0 R/W1C 0 R/W1C 0 Bit/Field Name Type Reset Description 31:26 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 162 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 25 DIV0 R/W1C 0 Description Divide-by-Zero Usage Fault Value Description 0 No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 1 The processor has executed an SDIV or UDIV instruction with a divisor of 0. When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the Configuration and Control (CFGCTRL) register (see page 153). This bit is cleared by writing a 1 to it. 24 UNALIGN R/W1C 0 Unaligned Access Usage Fault Value Description 0 No unaligned access fault has occurred, or unaligned access trapping is not enabled. 1 The processor has made an unaligned memory access. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting the UNALIGNED bit in the CFGCTRL register (see page 153). This bit is cleared by writing a 1 to it. 23:20 reserved RO 0x00 19 NOCP R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. No Coprocessor Usage Fault Value Description 0 A usage fault has not been caused by attempting to access a coprocessor. 1 The processor has attempted to access a coprocessor. This bit is cleared by writing a 1 to it. 18 INVPC R/W1C 0 Invalid PC Load Usage Fault Value Description 0 A usage fault has not been caused by attempting to load an invalid PC value. 1 The processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing a 1 to it. July 22, 2011 163 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 17 INVSTAT R/W1C 0 Description Invalid State Usage Fault Value Description 0 A usage fault has not been caused by an invalid state. 1 The processor has attempted to execute an instruction that makes illegal use of the EPSR register. When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register. This bit is not set if an undefined instruction uses the EPSR register. This bit is cleared by writing a 1 to it. 16 UNDEF R/W1C 0 Undefined Instruction Usage Fault Value Description 0 A usage fault has not been caused by an undefined instruction. 1 The processor has attempted to execute an undefined instruction. When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it. 15 BFARV R/W1C 0 Bus Fault Address Register Valid Value Description 0 The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address. 1 The FAULTADDR register is holding a valid fault address. This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 14:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 164 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 12 BSTKE R/W1C 0 Description Stack Bus Fault Value Description 0 No bus fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 11 BUSTKE R/W1C 0 Unstack Bus Fault Value Description 0 No bus fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more bus faults. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 10 IMPRE R/W1C 0 Imprecise Data Bus Error Value Description 0 An imprecise data bus error has not occurred. 1 A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When this bit is set, a fault address is not written to the FAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the IMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it. 9 PRECISE R/W1C 0 Precise Data Bus Error Value Description 0 A precise data bus error has not occurred. 1 A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When this bit is set, the fault address is written to the FAULTADDR register. This bit is cleared by writing a 1 to it. July 22, 2011 165 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 8 IBUS R/W1C 0 Description Instruction Bus Error Value Description 0 An instruction bus error has not occurred. 1 An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 7 MMARV R/W1C 0 Memory Management Fault Address Register Valid Value Description 0 The value in the Memory Management Fault Address (MMADDR) register is not a valid fault address. 1 The MMADDR register is holding a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 6:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 MSTKE R/W1C 0 Stack Access Violation Value Description 0 No memory management fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more access violations. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 166 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 3 MUSTKE R/W1C 0 Description Unstack Access Violation Value Description 0 No memory management fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more access violations. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 DERR R/W1C 0 Data Access Violation Value Description 0 A data access violation has not occurred. 1 The processor attempted a load or store at a location that does not permit the operation. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register. This bit is cleared by writing a 1 to it. 0 IERR R/W1C 0 Instruction Access Violation Value Description 0 An instruction access violation has not occurred. 1 The processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing a 1 to it. July 22, 2011 167 Texas Instruments-Production Data Cortex-M3 Peripherals Register 41: Hard Fault Status (HFAULTSTAT), offset 0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type R/W1C, reset 0x0000.0000 Type Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBG FORCED R/W1C 0 R/W1C 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VECT reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 RO 0 reserved Type Reset Bit/Field Name Type Reset 31 DBG R/W1C 0 Description Debug Event This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable. 30 FORCED R/W1C 0 Forced Hard Fault Value Description 0 No forced hard fault has occurred. 1 A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it. 29:2 reserved RO 0x00 1 VECT R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Vector Table Read Fault Value Description 0 No bus fault has occurred on a vector table read. 1 A bus fault occurred on a vector table read. This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 168 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 42: Memory Management Fault Address (MMADDR), offset 0xD34 Note: This register can only be accessed from privileged mode. The MMADDR register contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in the MMADDR register is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Bits in the Memory Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether the value in the MMADDR register is valid (see page 162). Memory Management Fault Address (MMADDR) Base 0xE000.E000 Offset 0xD34 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. July 22, 2011 169 Texas Instruments-Production Data Cortex-M3 Peripherals Register 43: Bus Fault Address (FAULTADDR), offset 0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDR register contains the address of the location that generated a bus fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT) register indicate the cause of the fault and whether the value in the FAULTADDR register is valid (see page 162). Bus Fault Address (FAULTADDR) Base 0xE000.E000 Offset 0xD38 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. 3.6 Memory Protection Unit (MPU) Register Descriptions This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset. The MPU registers can only be accessed from privileged mode. 170 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 44: MPU Type (MPUTYPE), offset 0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.0800 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 DREGION Type Reset RO 0 RO 0 RO 0 RO 0 19 18 17 16 RO 0 IREGION RO 0 RO 0 RO 0 RO 0 4 3 2 1 reserved RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 0 SEPARATE RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 IREGION RO 0x00 Number of I Regions This field indicates the number of supported MPU instruction regions. This field always contains 0x00. The MPU memory map is unified and is described by the DREGION field. 15:8 DREGION RO 0x08 Number of D Regions Value Description 0x08 Indicates there are eight supported MPU data regions. 7:1 reserved RO 0x00 0 SEPARATE RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Separate or Unified MPU Value Description 0 Indicates the MPU is unified. July 22, 2011 171 Texas Instruments-Production Data Cortex-M3 Peripherals Register 45: MPU Control (MPUCTRL), offset 0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRL register enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask Register (FAULTMASK) escalated handlers. When the ENABLE and PRIVDEFEN bits are both set: ■ For privileged accesses, the default memory map is as described in “Memory Model” on page 90. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. ■ Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled, then only privileged software can operate. When the ENABLE bit is clear, the system uses the default memory map, which has the same memory attributes as if the MPU is not implemented (see Table 2-5 on page 93 for more information). The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set. Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when operating with these two priorities. MPU Control (MPUCTRL) Base 0xE000.E000 Offset 0xD94 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 PRIVDEFEN HFNMIENA R/W 0 R/W 0 ENABLE R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 172 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 2 PRIVDEFEN R/W 0 Description MPU Default Region This bit enables privileged software access to the default memory map. Value Description 0 If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 If the MPU is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. When this bit is set, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. 1 HFNMIENA R/W 0 MPU Enabled During Faults This bit controls the operation of the MPU during hard fault, NMI, and FAULTMASK handlers. Value Description 0 The MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit. 1 The MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. 0 ENABLE R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. July 22, 2011 173 Texas Instruments-Production Data Cortex-M3 Peripherals Register 46: MPU Region Number (MPUNUMBER), offset 0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBER register selects which memory region is referenced by the MPU Region Base Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the required region number should be written to this register before accessing the MPUBASE or the MPUATTR register. However, the region number can be changed by writing to the MPUBASE register with the VALID bit set (see page 175). This write updates the value of the REGION field. MPU Region Number (MPUNUMBER) Base 0xE000.E000 Offset 0xD98 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 NUMBER R/W 0x0 NUMBER RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. 174 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 47: MPU Region Base Address (MPUBASE), offset 0xD9C Register 48: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 Register 49: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC Register 50: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 Note: This register can only be accessed from privileged mode. The MPUBASE register defines the base address of the MPU region selected by the MPU Region Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To change the current region number and update the MPUNUMBER register, write the MPUBASE register with the VALID bit set. The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size, as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines the value of N where: N = Log2(Region size in bytes) If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x0000.0000. The base address is aligned to the size of the region. For example, a 64-KB region must be aligned on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000. MPU Region Base Address (MPUBASE) Base 0xE000.E000 Offset 0xD9C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALID reserved WO 0 RO 0 ADDR Type Reset ADDR Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:5 ADDR R/W 0x0000.000 R/W 0 R/W 0 R/W 0 R/W 0 REGION R/W 0 R/W 0 R/W 0 Description Base Address Mask Bits 31:N in this field contain the region base address. The value of N depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 175 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset 4 VALID WO 0 Description Region Number Valid Value Description 0 The MPUNUMBER register is not changed and the processor updates the base address for the region specified in the MPUNUMBER register and ignores the value of the REGION field. 1 The MPUNUMBER register is updated with the value of the REGION field and the base address is updated for the region specified in the REGION field. This bit is always read as 0. 3 reserved RO 0 2:0 REGION R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Region Number On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the current region number in the MPUNUMBER register. 176 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 51: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 Register 52: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 Register 53: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 Register 54: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 Note: This register can only be accessed from privileged mode. The MPUATTR register defines the region size and memory attributes of the MPU region specified by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions. The MPUATTR register is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table 3-9 on page 177 gives example SIZE values with the corresponding region size and value of N in the MPU Region Base Address (MPUBASE) register. Table 3-9. Example SIZE Field Values a SIZE Encoding Region Size Value of N Note 00100b (0x4) 32 B 5 Minimum permitted size 01001b (0x9) 1 KB 10 - 10011b (0x13) 1 MB 20 - 11101b (0x1D) 1 GB 30 - 11111b (0x1F) 4 GB No valid ADDR field in MPUBASE; the Maximum possible size region occupies the complete memory map. a. Refers to the N parameter in the MPUBASE register (see page 175). MPU Region Attribute and Size (MPUATTR) Base 0xE000.E000 Offset 0xDA0 Type R/W, reset 0x0000.0000 31 30 29 28 27 reserved Type Reset 26 25 24 23 AP 21 reserved 20 19 18 TEX 17 16 XN reserved S C B RO 0 RO 0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 SRD Type Reset 22 reserved SIZE July 22, 2011 R/W 0 ENABLE R/W 0 177 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description 31:29 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 XN R/W 0 Instruction Access Disable Value Description 0 Instruction fetches are enabled. 1 Instruction fetches are disabled. 27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 26:24 AP R/W 0 Access Privilege For information on using this bit field, see Table 3-5 on page 121. 23:22 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21:19 TEX R/W 0x0 Type Extension Mask For information on using this bit field, see Table 3-3 on page 120. 18 S R/W 0 Shareable For information on using this bit, see Table 3-3 on page 120. 17 C R/W 0 Cacheable For information on using this bit, see Table 3-3 on page 120. 16 B R/W 0 Bufferable For information on using this bit, see Table 3-3 on page 120. 15:8 SRD R/W 0x00 Subregion Disable Bits Value Description 0 The corresponding subregion is enabled. 1 The corresponding subregion is disabled. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, configure the SRD field as 0x00. See the section called “Subregions” on page 119 for more information. 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:1 SIZE R/W 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 177 for more information. 178 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 ENABLE R/W 0 Description Region Enable Value Description 0 The region is disabled. 1 The region is enabled. July 22, 2011 179 Texas Instruments-Production Data JTAG Interface 4 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. ® The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO output. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM, Stellaris, and unimplemented JTAG instructions. The Stellaris JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. 180 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 4.1 Block Diagram Figure 4-1. JTAG Module Block Diagram TCK TMS TAP Controller TDI Instruction Register (IR) BYPASS Data Register TDO Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register Cortex-M3 Debug Port 4.2 Signal Description The following table lists the external signals of the JTAG/SWD controller and describes the function of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals are under commit protection and require a special process to be configured as GPIOs, see “Commit Control” on page 400. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) is set to choose the JTAG/SWD function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the JTAG/SWD controller signals to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. Table 4-1. Signals for JTAG_SWD_SWO (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description SWCLK 80 PC0 (3) I TTL JTAG/SWD CLK. SWDIO 79 PC1 (3) I/O TTL JTAG TMS and SWDIO. SWO 77 PC3 (3) O TTL JTAG TDO and SWO. TCK 80 PC0 (3) I TTL JTAG/SWD CLK. TDI 78 PC2 (3) I TTL JTAG TDI. TDO 77 PC3 (3) O TTL JTAG TDO and SWO. July 22, 2011 181 Texas Instruments-Production Data JTAG Interface Table 4-1. Signals for JTAG_SWD_SWO (100LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment 79 TMS PC1 (3) a Pin Type Buffer Type I TTL Description JTAG TMS and SWDIO. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 4-2. Signals for JTAG_SWD_SWO (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description A9 PC0 (3) I TTL JTAG/SWD CLK. SWDIO B9 PC1 (3) I/O TTL JTAG TMS and SWDIO. SWO A10 PC3 (3) O TTL JTAG TDO and SWO. TCK A9 PC0 (3) I TTL JTAG/SWD CLK. SWCLK TDI B8 PC2 (3) I TTL JTAG TDI. TDO A10 PC3 (3) O TTL JTAG TDO and SWO. TMS B9 PC1 (3) I TTL JTAG TMS and SWDIO. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 4.3 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 181. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 4-4 on page 188 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 1191 for JTAG timing diagrams. Note: 4.3.1 Of all the possible reset sources, only Power-On reset (POR) and the assertion of the RST input have any effect on the JTAG module. The pin configurations are reset by both the RST input and POR, whereas the internal JTAG logic is only reset with POR. See “Reset Sources” on page 193 for more information on reset. JTAG Interface Pins The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their associated state after a power-on reset or reset caused by the RST input are given in Table 4-3. Detailed information on each pin follows. Refer to “General-Purpose Input/Outputs (GPIOs)” on page 391 for information on how to reprogram the configuration of these pins. 182 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 4-3. JTAG Port Pins State after Power-On Reset or RST assertion 4.3.1.1 Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value TCK Input Enabled Disabled N/A N/A TMS Input Enabled Disabled N/A N/A TDI Input Enabled Disabled N/A N/A TDO Output Enabled Disabled 2-mA driver High-Z Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks and to ensure that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset, assuring that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source (see page 422 and page 424). 4.3.1.2 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG module and associated registers are reset to their default values. This procedure should be performed to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety in Figure 4-2 on page 184. By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost (see page 422). 4.3.1.3 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, may present this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost (see page 422). 4.3.1.4 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the July 22, 2011 183 Texas Instruments-Production Data JTAG Interface chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset, assuring that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states (see page 422 and page 424). 4.3.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 4-2. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset the JTAG module after the microcontroller has been powered on, the TMS input must be held HIGH for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. Figure 4-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 0 Select DR Scan 1 Select IR Scan 1 0 1 Capture DR 1 Capture IR 0 0 Shift DR Shift IR 0 1 Exit 1 DR Exit 1 IR 1 Pause IR 0 1 Exit 2 DR 0 1 0 Exit 2 IR 1 1 Update DR 4.3.3 1 0 Pause DR 1 0 1 0 0 1 0 0 Update IR 1 0 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows 184 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller this information to be shifted out on TDO during the TAP controller’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 188. 4.3.4 Operational Considerations Certain operational parameters must be considered when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. 4.3.4.1 GPIO Functionality When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0] set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0] set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors (PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select (GPIOAFSEL) register) on the JTAG/SWD pins. See page 416, page 422, page 424, and page 427. It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides four more GPIOs for use in the design. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 416), GPIO Pull Up Select (GPIOPUR) register (see page 422), GPIO Pull-Down Select (GPIOPDR) register (see page 424), and GPIO Digital Enable (GPIODEN) register (see page 427) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 429) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 430) have been set. 4.3.4.2 Communication with JTAG/SWD Because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software should check the ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. July 22, 2011 185 Texas Instruments-Production Data JTAG Interface 4.3.4.3 Recovering a "Locked" Microcontroller Note: Performing the sequence below restores the nonvolatile registers discussed in “Nonvolatile Register Programming” on page 304 to their factory default values. The mass erase of the Flash memory caused by the sequence below occurs prior to the nonvolatile registers being restored. If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug port unlock sequence that can be used to recover the microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence is: 1. Assert and hold the RST signal. 2. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD Switching” on page 187. 3. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG Switching” on page 187. 4. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 5. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 6. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 7. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 8. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 9. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 10. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 11. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 12. Release the RST signal. 13. Wait 400 ms. 14. Power-cycle the microcontroller. 4.3.4.4 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued before the SWD session begins. The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. 186 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Stepping through this sequence of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Debug Interface V5 Architecture Specification. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This instance is the only one where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send the switching preamble to the microcontroller. The 16-bit TMS command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already in SWD mode, the SWD goes into the line reset state before sending the switch sequence. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch command to the microcontroller. The 16-bit TMS command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first. This command can also be represented as 0xE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already in JTAG mode, the JTAG goes into the Test Logic Reset state before sending the switch sequence. 4.4 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. To return the pins to their JTAG functions, enable the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the four JTAG pins (PC[3:0]) should be returned to their default settings. July 22, 2011 187 Texas Instruments-Production Data JTAG Interface 4.5 Register Descriptions The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within the JTAG controller are all accessed serially through the TAP Controller. These registers include the Instruction Register and the six Data Registers. 4.5.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-4. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 4-4. JTAG Instruction Register Commands 4.5.1.1 IR[3:0] Instruction Description 0x0 EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0x1 INTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. 0x2 SAMPLE / PRELOAD 0x8 ABORT Shifts data into the ARM Debug Port Abort Register. 0xA DPACC Shifts data into and out of the ARM DP Access Register. 0xB APACC Shifts data into and out of the ARM AC Access Register. 0xE IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. 0xF BYPASS Connects TDI to TDO through a single Shift Register chain. All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. EXTEST Instruction The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. With tests that drive known values out of the controller, this instruction can be used to verify connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 4.5.1.2 INTEST Instruction The INTEST instruction is not associated with its own Data Register chain. Instead, the INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. With tests that drive known values into the controller, this instruction can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. 188 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller While the INTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 4.5.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. See “Boundary Scan Data Register” on page 190 for more information. 4.5.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. See the “ABORT Data Register” on page 191 for more information. 4.5.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. See “DPACC Data Register” on page 191 for more information. 4.5.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. See “APACC Data Register” on page 191 for more information. 4.5.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure input and output data streams. IDCODE is the default instruction loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. See “IDCODE Data Register” on page 190 for more information. July 22, 2011 189 Texas Instruments-Production Data JTAG Interface 4.5.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 190 for more information. 4.5.2 Data Registers The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections. 4.5.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-3. The standard requires that every JTAG-compliant microcontroller implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This definition allows auto-configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 4-3. IDCODE Register Format 31 TDI 4.5.2.2 28 27 12 11 Version Part Number 1 0 Manufacturer ID 1 TDO BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-4. The standard requires that every JTAG-compliant microcontroller implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This definition allows auto-configuration test tools to determine which instruction is the default instruction. Figure 4-4. BYPASS Register Format 0 TDI 4.5.2.3 0 TDO Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each 190 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as shown in the figure. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. The EXTEST instruction forces data out of the controller, and the INTEST instruction forces data into the controller. Figure 4-5. Boundary Scan Register Format TDI I N O U T O E ... 1st GPIO 4.5.2.4 I N O U T mth GPIO O E I N O U T (m+1)th GPIO O E ... I N O U T O E TDO GPIO nth APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.5.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. July 22, 2011 191 Texas Instruments-Production Data System Control 5 System Control System control configures the overall operation of the device and provides information about the device. Configurable features include reset control, NMI operation, power control, clock control, and low-power modes. 5.1 Signal Description The following table lists the external signals of the System Control module and describes the function of each. The NMI signal is the alternate function for the GPIO PB7 signal and functions as a GPIO after reset. PB7 is under commit protection and requires a special process to be configured as any alternate function or to subsequently return to the GPIO function, see “Commit Control” on page 400. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the NMI function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the NMI signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. The remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment and function. Table 5-1. Signals for System Control & Clocks (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description NMI 89 PB7 (4) I TTL Non-maskable interrupt. OSC0 48 fixed I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 64 fixed I TTL System reset input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 5-2. Signals for System Control & Clocks (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description NMI A8 PB7 (4) I TTL Non-maskable interrupt. OSC0 L11 fixed I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST H11 fixed I TTL System reset input. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 5.2 Functional Description The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 193 ■ Local control, such as reset (see “Reset Control” on page 193), power (see “Power Control” on page 198) and clock control (see “Clock Control” on page 199) 192 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 206 5.2.1 Device Identification Several read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, Flash memory size, and other features. See the DID0 (page 210), DID1 (page 238), DC0-DC9 (page 240) and NVMSTAT (page 263) registers. 5.2.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 Reset Sources The LM3S9L71 microcontroller has six sources of reset: 1. Power-on reset (POR) (see page 194). 2. External reset input pin (RST) assertion (see page 194). 3. Internal brown-out (BOR) detector (see page 196). 4. Software-initiated reset (with the software reset registers) (see page 196). 5. A watchdog timer reset condition violation (see page 197). 6. MOSC failure (see page 198). Table 5-3 provides a summary of results of the various reset operations. Table 5-3. Reset Sources Core Reset? JTAG Reset? On-Chip Peripherals Reset? Power-On Reset Reset Source Yes Yes Yes RST Yes Yes Yes Brown-Out Reset Yes Yes Yes Software System Request Reset using the SYSRESREQ bit in the APINT register. Yes Yes Yes Software System Request Reset using the VECTRESET bit in the APINT register. Yes No No Software Peripheral Reset No Yes Yes Watchdog Reset Yes Yes Yes MOSC Failure Reset Yes Yes Yes a a. Programmable on a module-by-module basis using the Software Reset Control Registers. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, in which case, all the bits in the RESC register are cleared except for the POR indicator. A bit in the RESC register can be cleared by writing a 0. July 22, 2011 193 Texas Instruments-Production Data System Control At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal as configured in the Boot Configuration (BOOTCFG) register. At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always executed. The boot sequence executed from ROM is as follows: 1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is mapped to address 0x0. 2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is valid data at address 0x0000.0004, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. For example, if the BOOTCFG register is written and committed with the value of 0x0000.3C01, then PB7 is examined at reset to determine if the ROM Boot Loader should be executed. If PB7 is Low, the core unconditionally begins executing the ROM boot loader. If PB7 is High, then the application in Flash memory is executed if the reset vector at location 0x0000.0004 is not 0xFFFF.FFFF. Otherwise, the ROM boot loader is executed. 5.2.2.2 Power-On Reset (POR) The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VTH). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete (see “Power and Brown-out” on page 1192). For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input may be used as discussed in “External RST Pin” on page 194. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset timing is shown in Figure 25-4 on page 1193. 5.2.2.3 External RST Pin Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be sure to place any components connected to the RST signal as close to the microcontroller as possible. If the application only uses the internal POR circuit, the RST input must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 195. 194 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 5-1. Basic RST Configuration VDD Stellaris® RPU RST RPU = 0 to 100 kΩ The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals except the JTAG TAP controller (see “JTAG Interface” on page 180). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted (see “Reset” on page 1194). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. To improve noise immunity and/or to delay reset at power up, the RST input may be connected to an RC network as shown in Figure 5-2 on page 195. Figure 5-2. External Circuitry to Extend Power-On Reset VDD Stellaris® RPU RST C1 RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 µF If the application requires the use of an external reset switch, Figure 5-3 on page 196 shows the proper circuitry to use. July 22, 2011 195 Texas Instruments-Production Data System Control Figure 5-3. Reset Circuit Controlled by Switch VDD Stellaris® RPU RST C1 RS Typical RPU = 10 kΩ Typical RS = 470 Ω C1 = 10 nF The RPU and C1 components define the power-on delay. The external reset timing is shown in Figure 25-7 on page 1194. 5.2.2.4 Brown-Out Reset (BOR) The microcontroller provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate an interrupt or a system reset. The default condition is to generate an interrupt, so BOR must be enabled. Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset; if BORIOR is clear, an interrupt is generated. When a Brown-out condition occurs during a Flash PROGRAM or ERASE operation, a full system reset is always triggered without regard to the setting in the PBORCTL register. The brown-out reset sequence is as follows: 1. When VDD drops below VBTH, an internal BOR condition is set. 2. If the BOR condition exists, an internal reset is asserted. 3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. 4. The internal BOR condition is reset after 500 µs to prevent another BOR condition from being set before software has a chance to investigate the original cause. The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 25-5 on page 1193. 5.2.2.5 Software Reset Software can reset a specific peripheral or generate a reset to the entire microcontroller. 196 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Peripherals can be individually reset by software via three registers that control reset signals to each on-chip peripheral (see the SRCRn registers, page 290). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 206). The entire microcontroller, including the core, can be reset by software by setting the SYSRESREQ bit in the Application Interrupt and Reset Control (APINT) register. The software-initiated system reset sequence is as follows: 1. A software microcontroller reset is initiated by setting the SYSRESREQ bit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The core only can be reset by software by setting the VECTRESET bit in the APINT register. The software-initiated core reset sequence is as follows: 1. A core reset is initiated by setting the VECTRESET bit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 25-8 on page 1194. 5.2.2.6 Watchdog Timer Reset The Watchdog Timer module's function is to prevent system hangs. The LM3S9L71 microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module operates in the same manner except that because the PIOSC watchdog timer module is in a different clock domain, register accesses must have a time delay between them. The watchdog timer can be configured to generate an interrupt to the microcontroller on its first time-out and to generate a reset on its second time-out. After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. For more information on the Watchdog Timer module, see “Watchdog Timers” on page 495. July 22, 2011 197 Texas Instruments-Production Data System Control The watchdog reset timing is shown in Figure 25-9 on page 1195. 5.2.3 Non-Maskable Interrupt The microcontroller has three sources of non-maskable interrupt (NMI): ■ The assertion of the NMI signal ■ A main oscillator verification error ■ The NMISET bit in the Interrupt Control and State (INTCTRL) register in the Cortex™-M3 (see page 145). Software must check the cause of the interrupt in order to distinguish among the sources. 5.2.3.1 NMI Pin The NMI signal is the alternate function for GPIO port pin PB7. The alternate function must be enabled in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs (GPIOs)” on page 391. Note that enabling the NMI alternate function requires the use of the GPIO lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality, see page 430. The active sense of the NMI signal is High; asserting the enabled NMI signal above VIH initiates the NMI interrupt sequence. 5.2.3.2 Main Oscillator Verification Failure The LM3S9L71 microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is enabled and a failure occurs, a power-on reset is generated and control is transferred to the NMI handler. The NMI handler is used to address the main oscillator verification failure because the necessary code can be removed from the general reset handler, speeding up reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator fail status (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit action is described in more detail in “Main Oscillator Verification Circuit” on page 205. 5.2.4 Power Control ® The Stellaris microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture. An external regulator may be used instead of the on-chip LDO, but must meet the requirements in Table 25-4 on page 1192. Regardless of the LDO implementation, the internal LDO requires decoupling capacitors as specified in “On-Chip Low Drop-Out (LDO) Regulator” on page 1195. Note: VDDA must be supplied with 3.3 V, or the microcontroller does not function properly. VDDA is the supply for all of the analog circuitry on the device, including the clock circuitry. 198 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 5-4. Power Architecture VDDC Internal Logic and PLL VDDC GND GND LDO Low-Noise LDO +3.3V VDD GND I/O Buffers VDD GND VDDA GNDA Analog Circuits VDDA 5.2.5 GNDA Clock Control System control determines the control of clocks in this part. 5.2.5.1 Fundamental Clock Sources There are multiple clock sources for use in the microcontroller: ■ Precision Internal Oscillator (PIOSC). The precision internal oscillator is an on-chip clock source that is the clock source the microcontroller uses during and following POR. It does not require the use of any external components and provides a clock that is 16 MHz ±1% at room temperature and ±3% across temperature. The PIOSC allows for a reduced system cost in applications that require an accurate clock source. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being used, the crystal value must be one of the supported frequencies between 3.579545 MHz to 16.384 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz to 16.384 MHz. The single-ended clock source range is from DC July 22, 2011 199 Texas Instruments-Production Data System Control through the specified speed of the microcontroller. The supported crystals are listed in the XTAL bit field in the RCC register (see page 221). Note that the MOSC provides the clock source for the USB PLL and must be connected to a crystal or an oscillator. ■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator provides an operational frequency of 30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the MOSC to be powered down. The internal system clock (SysClk), is derived from any of the above sources plus two others: the output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz (inclusive). Table 5-4 on page 200 shows how the various clock sources can be used in a system. Table 5-4. Clock Source Options 5.2.5.2 Clock Source Drive PLL? Used as SysClk? Precision Internal Oscillator Yes BYPASS = 0, OSCSRC = 0x1 Yes BYPASS = 1, OSCSRC = 0x1 Precision Internal Oscillator divide by 4 (4 MHz ± 1%) No - Yes BYPASS = 1, OSCSRC = 0x2 Main Oscillator Yes BYPASS = 0, OSCSRC = 0x0 Yes BYPASS = 1, OSCSRC = 0x0 Internal 30-kHz Oscillator No - Yes BYPASS = 1, OSCSRC = 0x3 Clock Configuration The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. These registers control the following clock functionality: ■ Source of clocks in sleep and deep-sleep modes ■ System clock derived from PLL or other clock source ■ Enabling/disabling of oscillators and PLL ■ Clock divisors ■ Crystal input selection Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the RCC register is required, include another register access after writing the RCC register and before writing the RCC2 register. Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. When the PLL is enabled, the ADC clock signal is automatically divided down to 16 MHz from the PLL output for proper ADC operation. The PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV in RCC). 200 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Note: When the ADC module is in operation, the system clock must be at least 16 MHz. When the USB module is in operation, MOSC must be provided with a clock source, and the system clock must be at least 20 MHz. Figure 5-5. Main Clock Tree XTALa USBPWRDN c USB PLL (480 MHz) ÷4 USB Clock RXINT RXFRAC I2S Receive MCLK TXINT TXFRAC I2S Transmit MCLK USEPWMDIV a PWMDW a PWM Clock XTALa PWRDN b MOSCDIS a PLL (400 MHz) Main OSC USESYSDIV a,d DIV400 c ÷2 IOSCDIS a System Clock Precision Internal OSC (16 MHz) SYSDIV e ÷4 BYPASS b,d Internal OSC (30 kHz) Hibernation OSC (32.768 kHz) PWRDN ADC Clock OSCSRC b,d ÷ 25 a. Control provided by RCC register bit/field. b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2. c. Control provided by RCC2 register bit/field. d. Also may be controlled by DSLPCLKCFG when in deep sleep mode. e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2 bit, or [SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set. Note: The figure above shows all features available on all Stellaris® Tempest-class microcontrollers. Not all peripherals may be available on this device. July 22, 2011 201 Texas Instruments-Production Data System Control Using the SYSDIV and SYSDIV2 Fields In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1). The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see Table 5-4 on page 200. Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field SYSDIV Divisor a ® Frequency (BYPASS=0) Frequency (BYPASS=1) StellarisWare Parameter b 0x0 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1 0x1 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x2 /3 66.67 MHz Clock source frequency/3 SYSCTL_SYSDIV_3 0x3 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x4 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 0x5 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x6 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 0x7 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x8 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9 0x9 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 0xA /11 18.18 MHz Clock source frequency/11 SYSCTL_SYSDIV_11 0xB /12 16.67 MHz Clock source frequency/12 SYSCTL_SYSDIV_12 0xC /13 15.38 MHz Clock source frequency/13 SYSCTL_SYSDIV_13 0xD /14 14.29 MHz Clock source frequency/14 SYSCTL_SYSDIV_14 0xE /15 13.33 MHz Clock source frequency/15 SYSCTL_SYSDIV_15 0xF /16 12.5 MHz (default) Clock source frequency/16 SYSCTL_SYSDIV_16 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding plus 1. Table 5-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list of possible clock sources, see Table 5-4 on page 200. Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field SYSDIV2 Divisor a Frequency (BYPASS2=0) Frequency (BYPASS2=1) StellarisWare Parameter b 0x00 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1 0x01 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x02 /3 66.67 MHz Clock source frequency/3 SYSCTL_SYSDIV_3 0x03 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x04 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 202 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field (continued) Divisor SYSDIV2 a Frequency (BYPASS2=0) Frequency (BYPASS2=1) StellarisWare Parameter ... ... ... ... ... 0x09 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 ... ... ... ... ... 0x3F /64 3.125 MHz Clock source frequency/64 SYSCTL_SYSDIV_64 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In this situation, the divisor is equivalent to the (SYSDIV2 encoding with SYSDIV2LSB appended) plus one. Table 5-7 shows the frequency choices when DIV400 is set. When the DIV400 bit is clear, SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table 5-6 on page 202. Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1 /2 reserved - /3 reserved - 1 /4 reserved - 0 /5 80 MHz SYSCTL_SYSDIV_2_5 1 /6 66.67 MHz SYSCTL_SYSDIV_3 0 /7 reserved - 1 /8 50 MHz SYSCTL_SYSDIV_4 0 /9 44.44 MHz SYSCTL_SYSDIV_4_5 1 /10 40 MHz SYSCTL_SYSDIV_5 ... ... ... ... 0 /127 3.15 MHz SYSCTL_SYSDIV_63_5 1 /128 3.125 MHz SYSCTL_SYSDIV_64 0x00 reserved 0 0x01 0x02 0x03 0x04 ... 0x3F b StellarisWare Parameter SYSDIV2LSB Divisor a Frequency (BYPASS2=0) SYSDIV2 a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0. b. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. 5.2.5.3 Precision Internal Oscillator Operation (PIOSC) The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC must remain enabled as it is used for internal functions. The PIOSC can only be disabled during Deep-Sleep mode. It can be powered down by setting the IOSCDIS bit in the RCC register. The PIOSC generates a 16-MHz clock with a ±1% accuracy at room temperatures. Across the extended temperature range, the accuracy is ±3%. At the factory, the PIOSC is set to 16 MHz at room temperature, however, the frequency can be trimmed for other voltage or temperature conditions using software in one of two ways: ■ Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator Calibration (PIOSCCAL) register. July 22, 2011 203 Texas Instruments-Production Data System Control ■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As the UT value increases, the generated period increases. To commit a new UT value, first set the UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within a few clock periods and is glitch free. 5.2.5.4 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 16.384 MHz, otherwise, the range of supported crystals is 1 to 16.384 MHz. The XTAL bit in the RCC register (see page 221) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 5.2.5.5 Main PLL Frequency Configuration The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor, unless the DIV400 bit in the RCC2 register is set. To configure the PIOSC to be the clock source for the main PLL, program the OSCRC2 field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x1. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 226). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 25-8 on page 1196 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 221) describes the available crystal choices and default programming of the PLLCFG register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. 5.2.5.6 USB PLL Frequency Configuration The USB PLL is disabled by default during power-on reset and is enabled later by software. The USB PLL must be enabled and running for proper USB function. The main oscillator is the only clock reference for the USB PLL. The USB PLL is enabled by clearing the USBPWRDN bit of the RCC2 register. The XTAL bit field (Crystal Value) of the RCC register describes the available crystal choices. The main oscillator must be connected to one of the following crystal values in order to correctly generate the USB clock: 4, 5, 6, 8, 10, 12, or 16 MHz. Only these crystals provide the necessary USB PLL VCO frequency to conform with the USB timing specifications. 5.2.5.7 PLL Modes Both PLLs have two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 221 and page 229). 204 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 5.2.5.8 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 25-7 on page 1195). During the relock time, the affected PLL is not usable as a clock reference. Either PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter clocked by the system clock is used to measure the TREADY requirement. If the system clock is the main oscillator and it is running off an 8.192 MHz or slower external oscillator clock, the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz). If the system clock is running off the PIOSC or an external oscillator clock that is faster than 8.192 MHz, the down counter is set to 0x2400. Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the microcontroller from the oscillator selected by the RCC/RCC2 register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt. The USB PLL is not protected during the lock time (TREADY), and software should ensure that the USB PLL has locked before using the interface. Software can use many methods to ensure the TREADY period has passed, including periodically polling the USBPLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the USB PLL Lock interrupt. 5.2.5.9 Main Oscillator Verification Circuit The clock control includes circuitry to ensure that the main oscillator is running at the appropriate frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable band of attached crystals. The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL) register. If this circuit is enabled and detects an error, the following sequence is performed by the hardware: 1. The MOSCFAIL bit in the Reset Cause (RESC) register is set. 2. If the internal oscillator (PIOSC) is disabled, it is enabled. 3. The system clock is switched from the main oscillator to the PIOSC. 4. An internal power-on reset is initiated that lasts for 32 PIOSC periods. 5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence. if the MOSCIM bit in the MOSCCTL register is set, then the following sequence is performed by the hardware: 1. The system clock is switched from the main oscillator to the PIOSC. July 22, 2011 205 Texas Instruments-Production Data System Control 2. The MOFRIS bit in the RIS register is set to indicate a MOSC failure. 5.2.6 System Control For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating logic for each peripheral or block in the system while the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. These registers are located in the System Control register map starting at offsets 0x600, 0x700, and 0x800, respectively. There must be a delay of 3 system clocks after a peripheral module clock is enabled in the RCGC register before any module registers are accessed. There are three levels of operation for the microcontroller defined as: ■ Run mode ■ Sleep mode ■ Deep-Sleep mode The following sections describe the different modes in detail. Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their Run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock. A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface. 5.2.6.1 Run Mode In Run mode, the microcontroller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. 5.2.6.2 Sleep Mode In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 109 for more details. Peripherals are clocked that are enabled in the SCGCn registers when auto-clock gating is enabled (see the RCC register) or the RCGCn registers when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. 5.2.6.3 Deep-Sleep Mode In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns 206 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-Sleep mode is entered by first setting the SLEEPDEEP bit in the System Control (SYSCTRL) register (see page 151) and then executing a WFI instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 109 for more details. The Cortex-M3 processor core and the memory subsystem are not clocked in Deep-Sleep mode. Peripherals are clocked that are enabled in the DCGCn registers when auto-clock gating is enabled (see the RCC register) or the RCGCn registers when auto-clock gating is disabled. The system clock source is specified in the DSLPCLKCFG register. When the DSLPCLKCFG register is used, the internal oscillator source is powered up, if necessary, and other clocks are powered down. If the PLL is running at the time of the WFI instruction, hardware powers the PLL down and overrides the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the PIOSC is used as the PLL reference clock source, it may continue to provide the clock during Deep-Sleep. See page 233. 5.3 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register, thereby configuring the microcontroller to run off a “raw” clock source and allowing for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 5.4 Register Map Table 5-8 on page 208 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Additional Flash and ROM registers defined in the System Control register space are described in the “Internal Memory” on page 297. July 22, 2011 207 Texas Instruments-Production Data System Control Table 5-8. System Control Register Map Description See page Offset Name Type Reset 0x000 DID0 RO - Device Identification 0 210 0x004 DID1 RO - Device Identification 1 238 0x008 DC0 RO 0x00BF.003F Device Capabilities 0 240 0x010 DC1 RO - Device Capabilities 1 241 0x014 DC2 RO 0x130F.5337 Device Capabilities 2 244 0x018 DC3 RO 0xBFFF.8FFF Device Capabilities 3 246 0x01C DC4 RO 0x1104.F1FF Device Capabilities 4 249 0x020 DC5 RO 0x0F30.003F Device Capabilities 5 251 0x024 DC6 RO 0x0000.0013 Device Capabilities 6 253 0x028 DC7 RO 0xFFFF.FFFF Device Capabilities 7 254 0x02C DC8 RO 0xFFFF.FFFF Device Capabilities 8 ADC Channels 258 0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 212 0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 290 0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 292 0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 295 0x050 RIS RO 0x0000.0000 Raw Interrupt Status 213 0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 215 0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 217 0x05C RESC R/W - Reset Cause 219 0x060 RCC R/W 0x078E.3AD1 Run-Mode Clock Configuration 221 0x064 PLLCFG RO - XTAL to PLL Translation 226 0x06C GPIOHBCTL R/W 0x0000.0000 GPIO High-Performance Bus Control 227 0x070 RCC2 R/W 0x07C0.6810 Run-Mode Clock Configuration 2 229 0x07C MOSCCTL R/W 0x0000.0000 Main Oscillator Control 232 0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 264 0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 272 0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 281 0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 267 0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 275 0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 284 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 270 0x124 DCGC1 R/W 0x00000000 Deep-Sleep Mode Clock Gating Control Register 1 278 208 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 5-8. System Control Register Map (continued) Name Type Reset 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 287 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 233 0x150 PIOSCCAL R/W 0x0000.0000 Precision Internal Oscillator Calibration 235 0x170 I2SMCLKCFG R/W 0x0000.0000 I2S MCLK Configuration 236 0x190 DC9 RO 0x00FF.00FF Device Capabilities 9 ADC Digital Comparators 261 0x1A0 NVMSTAT RO 0x0000.0001 Non-Volatile Memory Information 263 5.5 Description See page Offset Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. July 22, 2011 209 Texas Instruments-Production Data System Control Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset 31 30 28 27 26 VER reserved Type Reset 29 25 24 23 22 21 20 reserved 18 17 16 CLASS RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - MAJOR Type Reset 19 MINOR Bit/Field Name Type Reset 31 reserved RO 0 30:28 VER RO 0x1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 Second version of the DID0 register format. 27:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 CLASS RO 0x04 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all microcontrollers in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior microcontrollers. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x04 Stellaris® Tempest-class microcontrollers 210 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 15:8 MAJOR RO - Description Major Revision This field specifies the major revision number of the microcontroller. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. 7:0 MINOR RO - Minor Revision This field specifies the minor revision number of the microcontroller. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. July 22, 2011 211 Texas Instruments-Production Data System Control Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BORIOR reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 BORIOR R/W 0 BOR Interrupt or Reset Value Description 0 reserved RO 0 0 A Brown Out Event causes an interrupt to be generated to the interrupt controller. 1 A Brown Out Event causes a reset of the microcontroller. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 212 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 3: Raw Interrupt Status (RIS), offset 0x050 This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1 to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt status bit. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 BORRIS reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MOSCPUPRIS USBPLLLRIS Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 MOSCPUPRIS RO 0 RO 0 RO 0 PLLLRIS RO 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MOSC Power Up Raw Interrupt Status Value Description 1 Sufficient time has passed for the MOSC to reach the expected frequency. The value for this power-up time is indicated by TMOSC_START. 0 Sufficient time has not passed for the MOSC to reach the expected frequency. This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC register. 7 USBPLLLRIS RO 0 USB PLL Lock Raw Interrupt Status Value Description 1 The USB PLL timer has reached TREADY indicating that sufficient time has passed for the USB PLL to lock. 0 The USB PLL timer has not reached TREADY. This bit is cleared by writing a 1 to the USBPLLLMIS bit in the MISC register. 6 PLLLRIS RO 0 PLL Lock Raw Interrupt Status Value Description 1 The PLL timer has reached TREADY indicating that sufficient time has passed for the PLL to lock. 0 The PLL timer has not reached TREADY. This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register. July 22, 2011 213 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 5:2 reserved RO 0x0 1 BORRIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Brown-Out Reset Raw Interrupt Status Value Description 1 A brown-out condition is currently active. 0 A brown-out condition is not currently active. Note the BORIOR bit in the PBORCTL register must be cleared to cause an interrupt due to a Brown Out Event. This bit is cleared by writing a 1 to the BORMIS bit in the MISC register. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 214 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: Interrupt Mask Control (IMC), offset 0x054 This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the corresponding bit in this register is set. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 BORIM reserved RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MOSCPUPIM USBPLLLIM Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 MOSCPUPIM R/W 0 R/W 0 R/W 0 PLLLIM R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MOSC Power Up Interrupt Mask Value Description 7 USBPLLLIM R/W 0 1 An interrupt is sent to the interrupt controller when the MOSCPUPRIS bit in the RIS register is set. 0 The MOSCPUPRIS interrupt is suppressed and not sent to the interrupt controller. USB PLL Lock Interrupt Mask Value Description 6 PLLLIM R/W 0 1 An interrupt is sent to the interrupt controller when the USBPLLLRIS bit in the RIS register is set. 0 The USBPLLLRIS interrupt is suppressed and not sent to the interrupt controller. PLL Lock Interrupt Mask Value Description 5:2 reserved RO 0x0 1 An interrupt is sent to the interrupt controller when the PLLLRIS bit in the RIS register is set. 0 The PLLLRIS interrupt is suppressed and not sent to the interrupt controller. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 215 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 1 BORIM R/W 0 Description Brown-Out Reset Interrupt Mask Value Description 0 reserved RO 0 1 An interrupt is sent to the interrupt controller when the BORRIS bit in the RIS register is set. 0 The BORRIS interrupt is suppressed and not sent to the interrupt controller. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 216 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt in the Raw Interrupt Status (RIS) register. All of the bits are R/W1C, thus writing a 1 to a bit clears the corresponding raw interrupt bit in the RIS register (see page 213). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 BORMIS reserved RO 0 RO 0 RO 0 RO 0 R/W1C 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MOSCPUPMIS USBPLLLMIS Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 MOSCPUPMIS R/W1C 0 R/W1C 0 R/W1C 0 PLLLMIS R/W1C 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MOSC Power Up Masked Interrupt Status Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the MOSC PLL to lock. Writing a 1 to this bit clears it and also the MOSCPUPRIS bit in the RIS register. 0 When read, a 0 indicates that sufficient time has not passed for the MOSC PLL to lock. A write of 0 has no effect on the state of this bit. 7 USBPLLLMIS R/W1C 0 USB PLL Lock Masked Interrupt Status Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the USB PLL to lock. Writing a 1 to this bit clears it and also the USBPLLLRIS bit in the RIS register. 0 When read, a 0 indicates that sufficient time has not passed for the USB PLL to lock. A write of 0 has no effect on the state of this bit. July 22, 2011 217 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 6 PLLLMIS R/W1C 0 Description PLL Lock Masked Interrupt Status Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the PLL to lock. Writing a 1 to this bit clears it and also the PLLLRIS bit in the RIS register. 0 When read, a 0 indicates that sufficient time has not passed for the PLL to lock. A write of 0 has no effect on the state of this bit. 5:2 reserved RO 0x0 1 BORMIS R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. BOR Masked Interrupt Status Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because of a brown-out condition. Writing a 1 to this bit clears it and also the BORRIS bit in the RIS register. 0 When read, a 0 indicates that a brown-out condition has not occurred. A write of 0 has no effect on the state of this bit. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 218 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other than POR in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W - 9 8 7 6 5 4 3 2 1 0 WDT1 SW WDT0 BOR POR EXT RO 0 RO 0 RO 0 RO 0 R/W - R/W - R/W - R/W - R/W - R/W - reserved Type Reset MOSCFAIL reserved Type Reset RO 0 16 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 MOSCFAIL R/W - MOSC Failure Reset Value Description 1 When read, this bit indicates that the MOSC circuit was enabled for clock validation and failed, generating a reset event. 0 When read, this bit indicates that a MOSC failure has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 15:6 reserved RO 0x00 5 WDT1 R/W - Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Timer 1 Reset Value Description 1 When read, this bit indicates that Watchdog Timer 1 timed out and generated a reset. 0 When read, this bit indicates that Watchdog Timer 1 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. July 22, 2011 219 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 4 SW R/W - Description Software Reset Value Description 1 When read, this bit indicates that a software reset has caused a reset event. 0 When read, this bit indicates that a software reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 3 WDT0 R/W - Watchdog Timer 0 Reset Value Description 1 When read, this bit indicates that Watchdog Timer 0 timed out and generated a reset. 0 When read, this bit indicates that Watchdog Timer 0 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 2 BOR R/W - Brown-Out Reset Value Description 1 When read, this bit indicates that a brown-out reset has caused a reset event. 0 When read, this bit indicates that a brown-out reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. 1 POR R/W - Power-On Reset Value Description 1 When read, this bit indicates that a power-on reset has caused a reset event. 0 When read, this bit indicates that a power-on reset has not generated a reset. Writing a 0 to this bit clears it. 0 EXT R/W - External Reset Value Description 1 When read, this bit indicates that an external reset (RST assertion) has caused a reset event. 0 When read, this bit indicates that an external reset (RST assertion) has not caused a reset event since the previous power-on reset. Writing a 0 to this bit clears it. 220 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 The bits in this register configure the system clock and oscillators. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x078E.3AD1 31 30 29 28 26 25 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 15 14 13 12 11 PWRDN reserved BYPASS R/W 1 RO 1 R/W 1 reserved Type Reset reserved Type Reset RO 0 RO 0 27 24 23 R/W 1 R/W 1 R/W 1 10 9 8 R/W 0 R/W 1 ACG 22 21 20 USESYSDIV reserved USEPWMDIV R/W 0 RO 0 R/W 0 R/W 1 R/W 1 R/W 1 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 0 R/W 1 RO 0 SYSDIV XTAL Bit/Field Name Type Reset 31:28 reserved RO 0x0 27 ACG R/W 0 R/W 0 OSCSRC 19 18 17 PWMDIV reserved RO 0 16 reserved IOSCDIS MOSCDIS R/W 0 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the microcontroller enters a Sleep or Deep-Sleep mode (respectively). Value Description 1 The SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the microcontroller is in a sleep mode. The SCGCn and DCGCn registers allow unused peripherals to consume less power when the microcontroller is in a sleep mode. 0 The Run-Mode Clock Gating Control (RCGCn) registers are used when the microcontroller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. 26:23 SYSDIV R/W 0xF System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). See Table 5-5 on page 202 for bit encodings. If the SYSDIV value is less than MINSYSDIV (see page 241), and the PLL is being used, then the MINSYSDIV value is used as the divisor. If the PLL is not being used, the SYSDIV value can be less than MINSYSDIV. July 22, 2011 221 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 22 USESYSDIV R/W 0 Description Enable System Clock Divider Value Description 1 The system clock divider is the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field in the RCC2 register is used as the system clock divider rather than the SYSDIV field in this register. 0 The system clock is used undivided. 21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 USEPWMDIV R/W 0 Enable PWM Clock Divisor Value Description 1 The PWM clock divider is the source for the PWM clock. 0 The system clock is the source for the PWM clock. Note that when the PWM divisor is used, it is applied to the clock for both PWM modules. 19:17 PWMDIV R/W 0x7 PWM Unit Clock Divisor This field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. The rising edge of this clock is synchronous with the system clock. Value Divisor 16:14 reserved RO 0x0 13 PWRDN R/W 1 0x0 /2 0x1 /4 0x2 /8 0x3 /16 0x4 /32 0x5 /64 0x6 /64 0x7 /64 (default) Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Power Down Value Description 1 The PLL is powered down. Care must be taken to ensure that another clock source is functioning and that the BYPASS bit is set before setting this bit. 0 The PLL is operating normally. 222 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 12 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 BYPASS R/W 1 PLL Bypass Value Description 1 The system clock is derived from the OSC source and divided by the divisor specified by SYSDIV. 0 The system clock is the PLL output clock divided by the divisor specified by SYSDIV. See Table 5-5 on page 202 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. July 22, 2011 223 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 10:6 XTAL R/W 0x0B Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Depending on the crystal used, the PLL frequency may not be exactly 400 MHz, see Table 25-8 on page 1196 for more information. Frequencies that may be used with the USB interface are indicated in the table. To function within the clocking requirements of the USB specification, a crystal of 4, 5, 6, 8, 10, 12, or 16 MHz must be used. Value Crystal Frequency (MHz) Not Crystal Frequency (MHz) Using Using the PLL the PLL 0x00 1.000 MHz reserved 0x01 1.8432 MHz reserved 0x02 2.000 MHz reserved 0x03 2.4576 MHz 0x04 reserved 3.579545 MHz 0x05 3.6864 MHz 0x06 4 MHz (USB) 0x07 4.096 MHz 0x08 4.9152 MHz 0x09 5 MHz (USB) 0x0A 5.12 MHz 0x0B 6 MHz (reset value)(USB) 0x0C 6.144 MHz 0x0D 7.3728 MHz 0x0E 8 MHz (USB) 0x0F 8.192 MHz 0x10 10.0 MHz (USB) 0x11 12.0 MHz (USB) 0x12 12.288 MHz 0x13 13.56 MHz 0x14 14.31818 MHz 0x15 16.0 MHz (USB) 0x16 16.384 MHz 224 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 5:4 OSCSRC R/W 0x1 Description Oscillator Source Selects the input source for the OSC. The values are: Value Input Source 0x0 MOSC Main oscillator 0x1 PIOSC Precision internal oscillator (default) 0x2 PIOSC/4 Precision internal oscillator / 4 0x3 30 kHz 30-kHz internal oscillator For additional oscillator sources, see the RCC2 register. 3:2 reserved RO 0x0 1 IOSCDIS R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Precision Internal Oscillator Disable Value Description 0 MOSCDIS R/W 1 1 The precision internal oscillator (PIOSC) is disabled. 0 The precision internal oscillator is enabled. Main Oscillator Disable Value Description 1 The main oscillator is disabled (default). 0 The main oscillator is enabled. July 22, 2011 225 Texas Instruments-Production Data System Control Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 221). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO - RO - RO - RO - RO - 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO - RO - RO - RO - RO - RO - RO - RO - RO - reserved Type Reset reserved Type Reset RO 0 RO 0 F Bit/Field Name Type Reset 31:14 reserved RO 0x0000.0 13:5 F RO - R Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL F Value This field specifies the value supplied to the PLL’s F input. 4:0 R RO - PLL R Value This field specifies the value supplied to the PLL’s R input. 226 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C This register controls which internal bus is used to access each GPIO port. When a bit is clear, the corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and through the APB memory aperture. When a bit is set, the corresponding port is accessed across the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each GPIO port can be individually configured to use AHB or APB, but may be accessed only through one aperture. The AHB bus provides better back-to-back access performance than the APB bus. The address aperture in the memory map changes for the ports that are enabled for AHB access (see Table 8-7 on page 403). GPIO High-Performance Bus Control (GPIOHBCTL) Base 0x400F.E000 Offset 0x06C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PORTJ PORTH PORTG PORTF PORTE PORTD PORTC PORTB PORTA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:9 reserved RO 0x0000.0 8 PORTJ R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Port J Advanced High-Performance Bus This bit defines the memory aperture for Port J. Value Description 7 PORTH R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port H Advanced High-Performance Bus This bit defines the memory aperture for Port H. Value Description 6 PORTG R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port G Advanced High-Performance Bus This bit defines the memory aperture for Port G. Value Description 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. July 22, 2011 227 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 5 PORTF R/W 0 Description Port F Advanced High-Performance Bus This bit defines the memory aperture for Port F. Value Description 4 PORTE R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port E Advanced High-Performance Bus This bit defines the memory aperture for Port E. Value Description 3 PORTD R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port D Advanced High-Performance Bus This bit defines the memory aperture for Port D. Value Description 2 PORTC R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port C Advanced High-Performance Bus This bit defines the memory aperture for Port C. Value Description 1 PORTB R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port B Advanced High-Performance Bus This bit defines the memory aperture for Port B. Value Description 0 PORTA R/W 0 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. Port A Advanced High-Performance Bus This bit defines the memory aperture for Port A. Value Description 1 Advanced High-Performance Bus (AHB) 0 Advanced Peripheral Bus (APB). This bus is the legacy bus. 228 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields, as shown in Table 5-9, when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC field is located at the same LSB bit position; however, some RCC2 fields are larger than the corresponding RCC field. Table 5-9. RCC2 Fields that Override RCC Fields RCC2 Field... Overrides RCC Field SYSDIV2, bits[28:23] SYSDIV, bits[26:23] PWRDN2, bit[13] PWRDN, bit[13] BYPASS2, bit[11] BYPASS, bit[11] OSCSRC2, bits[6:4] OSCSRC, bits[5:4] Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x07C0.6810 31 30 USERCC2 DIV400 Type Reset Type Reset R/W 0 R/W 0 29 28 27 26 25 24 23 SYSDIV2 reserved RO 0 R/W 0 22 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 10 9 8 7 6 15 14 13 12 11 reserved USBPWRDN PWRDN2 reserved BYPASS2 RO 0 R/W 1 R/W 1 RO 0 R/W 1 reserved RO 0 21 20 19 RO 0 RO 0 Bit/Field Name Type Reset Description 31 USERCC2 R/W 0 Use RCC2 R/W 0 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 RO 0 RO 0 OSCSRC2 RO 0 18 reserved SYSDIV2LSB R/W 0 reserved R/W 1 RO 0 RO 0 Value Description 30 DIV400 R/W 0 1 The RCC2 register fields override the RCC register fields. 0 The RCC register fields are used, and the fields in RCC2 are ignored. Divide PLL as 400 MHz vs. 200 MHz This bit, along with the SYSDIV2LSB bit, allows additional frequency choices. Value Description 29 reserved RO 0x0 1 Append the SYSDIV2LSB bit to the SYSDIV2 field to create a 7 bit divisor using the 400 MHz PLL output, see Table 5-7 on page 203. 0 Use SYSDIV2 as is and apply to 200 MHz predivided PLL output. See Table 5-6 on page 202 for programming guidelines. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 229 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 28:23 SYSDIV2 R/W 0x0F System Clock Divisor 2 Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS2 bit is configured). SYSDIV2 is used for the divisor when both the USESYSDIV bit in the RCC register and the USERCC2 bit in this register are set. See Table 5-6 on page 202 for programming guidelines. 22 SYSDIV2LSB R/W 1 Additional LSB for SYSDIV2 When DIV400 is set, this bit becomes the LSB of SYSDIV2. If DIV400 is clear, this bit is not used. See Table 5-6 on page 202 for programming guidelines. This bit can only be set or cleared when DIV400 is set. 21:15 reserved RO 0x0 14 USBPWRDN R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power-Down USB PLL Value Description 13 PWRDN2 R/W 1 1 The USB PLL is powered down. 0 The USB PLL operates normally. Power-Down PLL 2 Value Description 1 The PLL is powered down. 0 The PLL operates normally. 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 BYPASS2 R/W 1 PLL Bypass 2 Value Description 1 The system clock is derived from the OSC source and divided by the divisor specified by SYSDIV2. 0 The system clock is the PLL output clock divided by the divisor specified by SYSDIV2. See Table 5-6 on page 202 for programming guidelines. Note: 10:7 reserved RO 0x0 The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 230 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 6:4 OSCSRC2 R/W 0x1 Description Oscillator Source 2 Selects the input source for the OSC. The values are: Value Description 0x0 MOSC Main oscillator 0x1 PIOSC Precision internal oscillator 0x2 PIOSC/4 Precision internal oscillator / 4 0x3 30 kHz 30-kHz internal oscillator 0x4-0x7 Reserved 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 231 Texas Instruments-Production Data System Control Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C This register provides the ability to enable the MOSC clock verification circuit. When enabled, this circuit monitors the frequency of the MOSC to verify that the oscillator is operating within specified limits. If the clock goes invalid after being enabled, the microcontroller issues a power-on reset and reboots to the NMI handler. Main Oscillator Control (MOSCCTL) Base 0x400F.E000 Offset 0x07C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 CVAL R/W 0 RO 0 CVAL R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Validation for MOSC Value Description 1 The MOSC monitor circuit is enabled. 0 The MOSC monitor circuit is disabled. 232 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 29 28 27 26 reserved Type Reset 25 24 23 22 21 20 DSDIVORIDE 18 17 16 reserved RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 19 DSOSCSRC RO 0 Bit/Field Name Type Reset 31:29 reserved RO 0x0 28:23 DSDIVORIDE R/W 0x0F R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Divider Field Override If Deep-Sleep mode is enabled when the PLL is running, the PLL is disabled. This 6-bit field contains a system divider field that overrides the SYSDIV field in the RCC register or the SYSDIV2 field in the RCC2 register during Deep Sleep. This divider is applied to the source selected by the DSOSCSRC field. Value Description 0x0 /1 0x1 /2 0x2 /3 0x3 /4 ... ... 0x3F /64 22:7 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 233 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 6:4 DSOSCSRC R/W 0x0 Description Clock Source Specifies the clock source during Deep-Sleep mode. Value Description 0x0 MOSC Use the main oscillator as the source. Note: 0x1 If the PIOSC is being used as the clock reference for the PLL, the PIOSC is the clock source instead of MOSC in Deep-Sleep mode. PIOSC Use the precision internal 16-MHz oscillator as the source. 0x2 Reserved 0x3 30 kHz Use the 30-kHz internal oscillator as the source. 0x4-0x7 Reserved 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 234 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 This register provides the ability to update or recalibrate the precision internal oscillator. Precision Internal Oscillator Calibration (PIOSCCAL) Base 0x400F.E000 Offset 0x150 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 22 21 20 19 18 17 16 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 UPDATE reserved R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 UTEN Type Reset reserved reserved Type Reset 23 RO 0 Bit/Field Name Type Reset 31 UTEN R/W 0 UT Description Use User Trim Value Value Description 30:9 reserved RO 0x0000 8 UPDATE R/W 0 1 The trim value in bits[6:0] of this register are used for any update trim operation. 0 The factory calibration value is used for an update trim operation. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Update Trim Value Description 1 Updates the PIOSC trim value with the UT bit. Used with UTEN. 0 No action. This bit is auto-cleared after the update. 7 reserved RO 0 6:0 UT R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. User Trim Value User trim value that can be loaded into the PIOSC. Refer to “Main PLL Frequency Configuration” on page 204 for more information on calibrating the PIOSC. July 22, 2011 235 Texas Instruments-Production Data System Control Register 14: I2S MCLK Configuration (I2SMCLKCFG), offset 0x170 This register configures the receive and transmit fractional clock dividers for the for the I2S master transmit and receive clocks (I2S0TXMCLK and I2S0RXMCLK). Varying the integer and fractional inputs for the clocks allows greater accuracy in hitting the target I2S clock frequencies. Refer to “Clock Control” on page 744 for combinations of the TXI and TXF bits and the RXI and RXF bits that provide MCLK frequencies within acceptable error limits. I2S MCLK Configuration (I2SMCLKCFG) Base 0x400F.E000 Offset 0x170 Type R/W, reset 0x0000.0000 Type Reset Type Reset 31 30 RXEN reserved R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 13 12 11 10 9 15 14 TXEN reserved R/W 0 RO 0 29 28 27 26 25 24 23 22 21 20 19 18 RXI R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 TXI R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31 RXEN R/W 0 17 16 R/W 0 R/W 0 1 0 R/W 0 R/W 0 RXF TXF R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description RX Clock Enable Value Description 1 The I2S receive clock generator is enabled. 0 The I2S receive clock generator is disabled. If the RXSLV bit in the I2S Module Configuration (I2SCFG) register is set, then the I2S0RXMCLK must be externally generated. 30 reserved RO 0 29:20 RXI R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RX Clock Integer Input This field contains the integer input for the receive clock generator. 19:16 RXF R/W 0x0 RX Clock Fractional Input This field contains the fractional input for the receive clock generator. 15 TXEN R/W 0 TX Clock Enable Value Description 1 The I2S transmit clock generator is enabled. 0 The I2S transmit clock generator is disabled. If the TXSLV bit in the I2S Module Configuration (I2SCFG) register is set, then the I2S0TXMCLK must be externally generated. 236 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 14 reserved RO 0 13:4 TXI R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. TX Clock Integer Input This field contains the integer input for the transmit clock generator. 3:0 TXF R/W 0x0 TX Clock Fractional Input This field contains the fractional input for the transmit clock generator. July 22, 2011 237 Texas Instruments-Production Data System Control Register 15: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 31 30 29 28 27 26 RO 0 15 25 24 23 22 21 20 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 14 13 12 11 10 9 8 7 6 5 4 RO 0 RO 0 RO 0 RO 0 RO 0 RO - RO - RO - VER Type Reset FAM PINCOUNT Type Reset RO 0 RO 1 18 17 16 RO 1 RO 0 RO 1 RO 1 3 2 1 0 PARTNO reserved RO 0 19 TEMP Bit/Field Name Type Reset 31:28 VER RO 0x1 RO - PKG ROHS RO - RO 1 QUAL RO - RO - Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 27:24 FAM RO 0x0 Second version of the DID1 register format. Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 23:16 PARTNO RO 0x1B Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0x1B LM3S9L71 15:13 PINCOUNT RO 0x2 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin package 238 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 12:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 TEMP RO - Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 4:3 PKG RO - 0x0 Commercial temperature range (0°C to 70°C) 0x1 Industrial temperature range (-40°C to 85°C) 0x2 Extended temperature range (-40°C to 105°C) Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 2 ROHS RO 1 0x0 SOIC package 0x1 LQFP package 0x2 BGA package RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 1:0 QUAL RO - Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified July 22, 2011 239 Texas Instruments-Production Data System Control Register 16: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00BF.003F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 1 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 SRAMSZ Type Reset FLASHSZ Type Reset RO 0 Bit/Field Name Type Reset Description 31:16 SRAMSZ RO 0x00BF SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x00BF 48 KB of SRAM 15:0 FLASHSZ RO 0x003F Flash Size Indicates the size of the on-chip flash memory. Value Description 0x003F 128 KB of Flash 240 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 17: Device Capabilities 1 (DC1), offset 0x010 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 31 30 29 reserved Type Reset 28 WDT1 26 24 23 22 21 19 16 CAN1 CAN0 ADC1 ADC0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MPU reserved TEMPSNS PLL WDT0 SWO SWD JTAG RO - RO - RO 1 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 MAXADC0SPD RO 1 RO 1 RO 1 RO 1 reserved 17 RO 1 MAXADC1SPD PWM 18 RO 0 RO - reserved 20 RO 0 RO - reserved 25 RO 0 MINSYSDIV Type Reset 27 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 RO 1 Watchdog Timer 1 Present When set, indicates that watchdog timer 1 is present. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 CAN1 RO 1 CAN Module 1 Present When set, indicates that CAN unit 1 is present. 24 CAN0 RO 1 CAN Module 0 Present When set, indicates that CAN unit 0 is present. 23:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM RO 1 PWM Module Present When set, indicates that the PWM module is present. 19:18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 17 ADC1 RO 1 ADC Module 1 Present When set, indicates that ADC module 1 is present. 16 ADC0 RO 1 ADC Module 0 Present When set, indicates that ADC module 0 is present July 22, 2011 241 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 15:12 MINSYSDIV RO - Description System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 11:10 MAXADC1SPD RO 0x3 0x1 Specifies an 80-MHz CPU clock with a PLL divider of 2.5. 0x2 Specifies a 66.67-MHz CPU clock with a PLL divider of 3. 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 0x7 Specifies a 25-MHz clock with a PLL divider of 8. 0x9 Specifies a 20-MHz clock with a PLL divider of 10. Max ADC1 Speed This field indicates the maximum rate at which the ADC samples data. Value Description 0x3 9:8 MAXADC0SPD RO 0x3 1M samples/second Max ADC0 Speed This field indicates the maximum rate at which the ADC samples data. Value Description 0x3 7 MPU RO 1 1M samples/second MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the "Cortex-M3 Peripherals" chapter for details on the MPU. 6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 TEMPSNS RO 1 Temp Sensor Present When set, indicates that the on-chip temperature sensor is present. 4 PLL RO 1 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 3 WDT0 RO 1 Watchdog Timer 0 Present When set, indicates that watchdog timer 0 is present. 2 SWO RO 1 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 1 SWD RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 242 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 JTAG RO 1 Description JTAG Present When set, indicates that the JTAG debugger interface is present. July 22, 2011 243 Texas Instruments-Production Data System Control Register 18: Device Capabilities 2 (DC2), offset 0x014 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x130F.5337 31 30 29 reserved Type Reset Type Reset 28 I2S0 27 26 reserved 25 24 23 22 21 20 18 17 16 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C1 reserved I2C0 QEI1 QEI0 SSI1 SSI0 reserved UART2 UART1 UART0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 0 RO 1 RO 1 RO 1 reserved RO 0 RO 0 reserved 19 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 I2S0 RO 1 I2S Module 0 Present When set, indicates that I2S module 0 is present. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 RO 1 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 24 COMP0 RO 1 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 RO 1 Timer Module 3 Present When set, indicates that General-Purpose Timer module 3 is present. 18 TIMER2 RO 1 Timer Module 2 Present When set, indicates that General-Purpose Timer module 2 is present. 17 TIMER1 RO 1 Timer Module 1 Present When set, indicates that General-Purpose Timer module 1 is present. 16 TIMER0 RO 1 Timer Module 0 Present When set, indicates that General-Purpose Timer module 0 is present. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 244 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 14 I2C1 RO 1 Description I2C Module 1 Present When set, indicates that I2C module 1 is present. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 RO 1 I2C Module 0 Present When set, indicates that I2C module 0 is present. 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 QEI1 RO 1 QEI Module 1 Present When set, indicates that QEI module 1 is present. 8 QEI0 RO 1 QEI Module 0 Present When set, indicates that QEI module 0 is present. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 RO 1 SSI Module 1 Present When set, indicates that SSI module 1 is present. 4 SSI0 RO 1 SSI Module 0 Present When set, indicates that SSI module 0 is present. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 RO 1 UART Module 2 Present When set, indicates that UART module 2 is present. 1 UART1 RO 1 UART Module 1 Present When set, indicates that UART module 1 is present. 0 UART0 RO 1 UART Module 0 Present When set, indicates that UART module 0 is present. July 22, 2011 245 Texas Instruments-Production Data System Control Register 19: Device Capabilities 3 (DC3), offset 0x018 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0xBFFF.8FFF Type Reset 31 30 29 28 27 26 25 24 32KHZ reserved CCP5 CCP4 CCP3 CCP2 CCP1 CCP0 RO 1 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 reserved PWMFAULT Type Reset RO 1 RO 0 RO 0 C1O RO 0 C1PLUS C1MINUS RO 1 RO 1 RO 1 Bit/Field Name Type Reset 31 32KHZ RO 1 C0O RO 1 23 22 21 20 19 18 17 16 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 C0PLUS C0MINUS RO 1 RO 1 Description 32KHz Input Clock Available When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock. 30 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 CCP5 RO 1 CCP5 Pin Present When set, indicates that Capture/Compare/PWM pin 5 is present. 28 CCP4 RO 1 CCP4 Pin Present When set, indicates that Capture/Compare/PWM pin 4 is present. 27 CCP3 RO 1 CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 26 CCP2 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 25 CCP1 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 24 CCP0 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 23 ADC0AIN7 RO 1 ADC Module 0 AIN7 Pin Present When set, indicates that ADC module 0 input pin 7 is present. 22 ADC0AIN6 RO 1 ADC Module 0 AIN6 Pin Present When set, indicates that ADC module 0 input pin 6 is present. 21 ADC0AIN5 RO 1 ADC Module 0 AIN5 Pin Present When set, indicates that ADC module 0 input pin 5 is present. 246 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 20 ADC0AIN4 RO 1 Description ADC Module 0 AIN4 Pin Present When set, indicates that ADC module 0 input pin 4 is present. 19 ADC0AIN3 RO 1 ADC Module 0 AIN3 Pin Present When set, indicates that ADC module 0 input pin 3 is present. 18 ADC0AIN2 RO 1 ADC Module 0 AIN2 Pin Present When set, indicates that ADC module 0 input pin 2 is present. 17 ADC0AIN1 RO 1 ADC Module 0 AIN1 Pin Present When set, indicates that ADC module 0 input pin 1 is present. 16 ADC0AIN0 RO 1 ADC Module 0 AIN0 Pin Present When set, indicates that ADC module 0 input pin 0 is present. 15 PWMFAULT RO 1 PWM Fault Pin Present When set, indicates that a PWM Fault pin is present. See DC5 for specific Fault pins on this device. 14:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 C1O RO 1 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present. 10 C1PLUS RO 1 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 9 C1MINUS RO 1 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. 8 C0O RO 1 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 7 C0PLUS RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 6 C0MINUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 5 PWM5 RO 1 PWM5 Pin Present When set, indicates that the PWM pin 5 is present. 4 PWM4 RO 1 PWM4 Pin Present When set, indicates that the PWM pin 4 is present. 3 PWM3 RO 1 PWM3 Pin Present When set, indicates that the PWM pin 3 is present. 2 PWM2 RO 1 PWM2 Pin Present When set, indicates that the PWM pin 2 is present. 1 PWM1 RO 1 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. July 22, 2011 247 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 0 PWM0 RO 1 Description PWM0 Pin Present When set, indicates that the PWM pin 0 is present. 248 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 20: Device Capabilities 4 (DC4), offset 0x01C This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x1104.F1FF 31 30 29 reserved Type Reset Type Reset 28 27 EMAC0 26 25 reserved 24 23 22 E1588 21 20 19 reserved 18 17 PICAL 16 reserved RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCP7 CCP6 UDMA ROM GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 RO 1 Ethernet MAC Layer 0 Present When set, indicates that Ethernet MAC layer 0 is present. 27:25 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24 E1588 RO 1 1588 Capable When set, indicates that that Ethernet MAC layer 0 is 1588 capable. 23:19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 PICAL RO 1 PIOSC Calibrate When set, indicates that the PIOSC can be calibrated. 17:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 CCP7 RO 1 CCP7 Pin Present When set, indicates that Capture/Compare/PWM pin 7 is present. 14 CCP6 RO 1 CCP6 Pin Present When set, indicates that Capture/Compare/PWM pin 6 is present. 13 UDMA RO 1 Micro-DMA Module Present When set, indicates that the micro-DMA module present. 12 ROM RO 1 Internal Code ROM Present When set, indicates that internal code ROM is present. July 22, 2011 249 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 11:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ RO 1 GPIO Port J Present When set, indicates that GPIO Port J is present. 7 GPIOH RO 1 GPIO Port H Present When set, indicates that GPIO Port H is present. 6 GPIOG RO 1 GPIO Port G Present When set, indicates that GPIO Port G is present. 5 GPIOF RO 1 GPIO Port F Present When set, indicates that GPIO Port F is present. 4 GPIOE RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 3 GPIOD RO 1 GPIO Port D Present When set, indicates that GPIO Port D is present. 2 GPIOC RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 1 GPIOB RO 1 GPIO Port B Present When set, indicates that GPIO Port B is present. 0 GPIOA RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. 250 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 21: Device Capabilities 5 (DC5), offset 0x020 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 5 (DC5) Base 0x400F.E000 Offset 0x020 Type RO, reset 0x0F30.003F 31 30 29 28 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 1 15 14 13 12 11 10 9 8 7 6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 27 26 25 24 23 22 reserved PWMFAULT3 PWMFAULT2 PWMFAULT1 PWMFAULT0 RO 0 20 19 18 RO 1 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 PWMEFLT PWMESYNC reserved Type Reset 21 17 16 reserved Bit/Field Name Type Reset Description 31:28 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27 PWMFAULT3 RO 1 PWM Fault 3 Pin Present When set, indicates that the PWM Fault 3 pin is present. 26 PWMFAULT2 RO 1 PWM Fault 2 Pin Present When set, indicates that the PWM Fault 2 pin is present. 25 PWMFAULT1 RO 1 PWM Fault 1 Pin Present When set, indicates that the PWM Fault 1 pin is present. 24 PWMFAULT0 RO 1 PWM Fault 0 Pin Present When set, indicates that the PWM Fault 0 pin is present. 23:22 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21 PWMEFLT RO 1 PWM Extended Fault Active When set, indicates that the PWM Extended Fault feature is active. 20 PWMESYNC RO 1 PWM Extended SYNC Active When set, indicates that the PWM Extended SYNC feature is active. 19:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 PWM5 RO 1 PWM5 Pin Present When set, indicates that the PWM pin 5 is present. 4 PWM4 RO 1 PWM4 Pin Present When set, indicates that the PWM pin 4 is present. July 22, 2011 251 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 3 PWM3 RO 1 Description PWM3 Pin Present When set, indicates that the PWM pin 3 is present. 2 PWM2 RO 1 PWM2 Pin Present When set, indicates that the PWM pin 2 is present. 1 PWM1 RO 1 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. 0 PWM0 RO 1 PWM0 Pin Present When set, indicates that the PWM pin 0 is present. 252 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 22: Device Capabilities 6 (DC6), offset 0x024 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0 registers cannot be set. Device Capabilities 6 (DC6) Base 0x400F.E000 Offset 0x024 Type RO, reset 0x0000.0013 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset RO 0 USB0PHY RO 1 reserved RO 0 USB0 RO 1 Bit/Field Name Type Reset Description 31:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 USB0PHY RO 1 USB Module 0 PHY Present When set, indicates that the USB module 0 PHY is present. 3:2 reserved RO 0 1:0 USB0 RO 0x3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Module 0 Present Thie field indicates that USB module 0 is present and specifies its capability. Value Description 0x3 USB0 is OTG. July 22, 2011 253 Texas Instruments-Production Data System Control Register 23: Device Capabilities 7 (DC7), offset 0x028 This register is predefined by the part and can be used to verify uDMA channel features. A 1 indicates the channel is available on this device; a 0 that the channel is only available on other devices in the family. Most channels have primary and secondary assignments. If the primary function is not available on this microcontroller, the secondary function becomes the primary function. If the secondary function is not available, the primary function is the only option. Device Capabilities 7 (DC7) Base 0x400F.E000 Offset 0x028 Type RO, reset 0xFFFF.FFFF 31 reserved Type Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 DMACH3 DMACH2 DMACH1 DMACH0 Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset 31 reserved RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Description Reserved Reserved for uDMA channel 31. 30 DMACH30 RO 1 SW When set, indicates uDMA channel 30 is available for software transfers. 29 DMACH29 RO 1 I2S0_TX / CAN1_TX When set, indicates uDMA channel 29 is available and connected to the transmit path of I2S module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of CAN module 1 transmit. 28 DMACH28 RO 1 I2S0_RX / CAN1_RX When set, indicates uDMA channel 28 is available and connected to the receive path of I2S module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of CAN module 1 receive. 27 DMACH27 RO 1 CAN1_TX / ADC1_SS3 When set, indicates uDMA channel 27 is available and connected to the transmit path of CAN module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 3. 26 DMACH26 RO 1 CAN1_RX / ADC1_SS2 When set, indicates uDMA channel 26 is available and connected to the receive path of CAN module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 2. 254 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 25 DMACH25 RO 1 Description SSI1_TX / ADC1_SS1 When set, indicates uDMA channel 25 is available and connected to the transmit path of SSI module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 1. 24 DMACH24 RO 1 SSI1_RX / ADC1_SS0 When set, indicates uDMA channel 24 is available and connected to the receive path of SSI module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of ADC module 1 Sample Sequencer 0. 23 DMACH23 RO 1 UART1_TX / CAN2_TX When set, indicates uDMA channel 23 is available and connected to the transmit path of UART module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of CAN module 2 transmit. 22 DMACH22 RO 1 UART1_RX / CAN2_RX When set, indicates uDMA channel 22 is available and connected to the receive path of UART module 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of CAN module 2 receive. 21 DMACH21 RO 1 Timer1B / EPI0_WFIFO When set, indicates uDMA channel 21 is available and connected to Timer 1B. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of EPI module 0 write FIFO (WRIFO). 20 DMACH20 RO 1 Timer1A / EPI0_NBRFIFO When set, indicates uDMA channel 20 is available and connected to Timer 1A. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of EPI module 0 non-blocking read FIFO (NBRFIFO). 19 DMACH19 RO 1 Timer0B / Timer1B When set, indicates uDMA channel 19 is available and connected to Timer 0B. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 1B. 18 DMACH18 RO 1 Timer0A / Timer1A When set, indicates uDMA channel 18 is available and connected to Timer 0A. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 1A. 17 DMACH17 RO 1 ADC0_SS3 When set, indicates uDMA channel 17 is available and connected to ADC module 0 Sample Sequencer 3. 16 DMACH16 RO 1 ADC0_SS2 When set, indicates uDMA channel 16 is available and connected to ADC module 0 Sample Sequencer 2. July 22, 2011 255 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 15 DMACH15 RO 1 Description ADC0_SS1 / Timer2B When set, indicates uDMA channel 15 is available and connected to ADC module 0 Sample Sequencer 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2B. 14 DMACH14 RO 1 ADC0_SS0 / Timer2A When set, indicates uDMA channel 14 is available and connected to ADC module 0 Sample Sequencer 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2A. 13 DMACH13 RO 1 CAN0_TX / UART2_TX When set, indicates uDMA channel 13 is available and connected to the transmit path of CAN module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 2 transmit. 12 DMACH12 RO 1 CAN0_RX / UART2_RX When set, indicates uDMA channel 12 is available and connected to the receive path of CAN module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 2 receive. 11 DMACH11 RO 1 SSI0_TX / SSI1_TX When set, indicates uDMA channel 11 is available and connected to the transmit path of SSI module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of SSI module 1 transmit. 10 DMACH10 RO 1 SSI0_RX / SSI1_RX When set, indicates uDMA channel 10 is available and connected to the receive path of SSI module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of SSI module 1 receive. 9 DMACH9 RO 1 UART0_TX / UART1_TX When set, indicates uDMA channel 9 is available and connected to the transmit path of UART module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 1 transmit. 8 DMACH8 RO 1 UART0_RX / UART1_RX When set, indicates uDMA channel 8 is available and connected to the receive path of UART module 0. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 1 receive. 7 DMACH7 RO 1 ETH_TX / Timer2B When set, indicates uDMA channel 7 is available and connected to the transmit path of the Ethernet module. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2B. 256 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 6 DMACH6 RO 1 Description ETH_RX / Timer2A When set, indicates uDMA channel 6 is available and connected to the receive path of the Ethernet module. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2A. 5 DMACH5 RO 1 USB_EP3_TX / Timer2B When set, indicates uDMA channel 5 is available and connected to the transmit path of USB endpoint 3. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2B. 4 DMACH4 RO 1 USB_EP3_RX / Timer2A When set, indicates uDMA channel 4 is available and connected to the receive path of USB endpoint 3. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 2A. 3 DMACH3 RO 1 USB_EP2_TX / Timer3B When set, indicates uDMA channel 3 is available and connected to the transmit path of USB endpoint 2. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 3B. 2 DMACH2 RO 1 USB_EP2_RX / Timer3A When set, indicates uDMA channel 2 is available and connected to the receive path of USB endpoint 2. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of Timer 3A. 1 DMACH1 RO 1 USB_EP1_TX / UART2_TX When set, indicates uDMA channel 1 is available and connected to the transmit path of USB endpoint 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 2 transmit. 0 DMACH0 RO 1 USB_EP1_RX / UART2_RX When set, indicates uDMA channel 0 is available and connected to the receive path of USB endpoint 1. If the corresponding bit in the DMACHASGN register is set, the channel is connected instead to the secondary channel assignment of UART module 2 receive. July 22, 2011 257 Texas Instruments-Production Data System Control Register 24: Device Capabilities 8 ADC Channels (DC8), offset 0x02C This register is predefined by the part and can be used to verify features. Device Capabilities 8 ADC Channels (DC8) Base 0x400F.E000 Offset 0x02C Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC1AIN15 ADC1AIN14 ADC1AIN13 ADC1AIN12 ADC1AIN11 ADC1AIN10 ADC1AIN9 ADC1AIN8 ADC1AIN7 ADC1AIN6 ADC1AIN5 ADC1AIN4 ADC1AIN3 ADC1AIN2 ADC1AIN1 ADC1AIN0 Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC0AIN15 ADC0AIN14 ADC0AIN13 ADC0AIN12 ADC0AIN11 ADC0AIN10 ADC0AIN9 ADC0AIN8 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset 31 ADC1AIN15 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Description ADC Module 1 AIN15 Pin Present When set, indicates that ADC module 1 input pin 15 is present. 30 ADC1AIN14 RO 1 ADC Module 1 AIN14 Pin Present When set, indicates that ADC module 1 input pin 14 is present. 29 ADC1AIN13 RO 1 ADC Module 1 AIN13 Pin Present When set, indicates that ADC module 1 input pin 13 is present. 28 ADC1AIN12 RO 1 ADC Module 1 AIN12 Pin Present When set, indicates that ADC module 1 input pin 12 is present. 27 ADC1AIN11 RO 1 ADC Module 1 AIN11 Pin Present When set, indicates that ADC module 1 input pin 11 is present. 26 ADC1AIN10 RO 1 ADC Module 1 AIN10 Pin Present When set, indicates that ADC module 1 input pin 10 is present. 25 ADC1AIN9 RO 1 ADC Module 1 AIN9 Pin Present When set, indicates that ADC module 1 input pin 9 is present. 24 ADC1AIN8 RO 1 ADC Module 1 AIN8 Pin Present When set, indicates that ADC module 1 input pin 8 is present. 23 ADC1AIN7 RO 1 ADC Module 1 AIN7 Pin Present When set, indicates that ADC module 1 input pin 7 is present. 22 ADC1AIN6 RO 1 ADC Module 1 AIN6 Pin Present When set, indicates that ADC module 1 input pin 6 is present. 21 ADC1AIN5 RO 1 ADC Module 1 AIN5 Pin Present When set, indicates that ADC module 1 input pin 5 is present. 20 ADC1AIN4 RO 1 ADC Module 1 AIN4 Pin Present When set, indicates that ADC module 1 input pin 4 is present. 258 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 19 ADC1AIN3 RO 1 Description ADC Module 1 AIN3 Pin Present When set, indicates that ADC module 1 input pin 3 is present. 18 ADC1AIN2 RO 1 ADC Module 1 AIN2 Pin Present When set, indicates that ADC module 1 input pin 2 is present. 17 ADC1AIN1 RO 1 ADC Module 1 AIN1 Pin Present When set, indicates that ADC module 1 input pin 1 is present. 16 ADC1AIN0 RO 1 ADC Module 1 AIN0 Pin Present When set, indicates that ADC module 1 input pin 0 is present. 15 ADC0AIN15 RO 1 ADC Module 0 AIN15 Pin Present When set, indicates that ADC module 0 input pin 15 is present. 14 ADC0AIN14 RO 1 ADC Module 0 AIN14 Pin Present When set, indicates that ADC module 0 input pin 14 is present. 13 ADC0AIN13 RO 1 ADC Module 0 AIN13 Pin Present When set, indicates that ADC module 0 input pin 13 is present. 12 ADC0AIN12 RO 1 ADC Module 0 AIN12 Pin Present When set, indicates that ADC module 0 input pin 12 is present. 11 ADC0AIN11 RO 1 ADC Module 0 AIN11 Pin Present When set, indicates that ADC module 0 input pin 11 is present. 10 ADC0AIN10 RO 1 ADC Module 0 AIN10 Pin Present When set, indicates that ADC module 0 input pin 10 is present. 9 ADC0AIN9 RO 1 ADC Module 0 AIN9 Pin Present When set, indicates that ADC module 0 input pin 9 is present. 8 ADC0AIN8 RO 1 ADC Module 0 AIN8 Pin Present When set, indicates that ADC module 0 input pin 8 is present. 7 ADC0AIN7 RO 1 ADC Module 0 AIN7 Pin Present When set, indicates that ADC module 0 input pin 7 is present. 6 ADC0AIN6 RO 1 ADC Module 0 AIN6 Pin Present When set, indicates that ADC module 0 input pin 6 is present. 5 ADC0AIN5 RO 1 ADC Module 0 AIN5 Pin Present When set, indicates that ADC module 0 input pin 5 is present. 4 ADC0AIN4 RO 1 ADC Module 0 AIN4 Pin Present When set, indicates that ADC module 0 input pin 4 is present. 3 ADC0AIN3 RO 1 ADC Module 0 AIN3 Pin Present When set, indicates that ADC module 0 input pin 3 is present. 2 ADC0AIN2 RO 1 ADC Module 0 AIN2 Pin Present When set, indicates that ADC module 0 input pin 2 is present. July 22, 2011 259 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 1 ADC0AIN1 RO 1 Description ADC Module 0 AIN1 Pin Present When set, indicates that ADC module 0 input pin 1 is present. 0 ADC0AIN0 RO 1 ADC Module 0 AIN0 Pin Present When set, indicates that ADC module 0 input pin 0 is present. 260 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 25: Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 This register is predefined by the part and can be used to verify features. Device Capabilities 9 ADC Digital Comparators (DC9) Base 0x400F.E000 Offset 0x190 Type RO, reset 0x00FF.00FF 31 30 29 28 27 26 25 24 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 ADC1DC7 ADC1DC6 ADC1DC5 ADC1DC4 ADC1DC3 ADC1DC2 ADC1DC1 ADC1DC0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 ADC0DC7 ADC0DC6 ADC0DC5 ADC0DC4 ADC0DC3 ADC0DC2 ADC0DC1 ADC0DC0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type Reset Description 31:24 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23 ADC1DC7 RO 1 ADC1 DC7 Present When set, indicates that ADC module 1 Digital Comparator 7 is present. 22 ADC1DC6 RO 1 ADC1 DC6 Present When set, indicates that ADC module 1 Digital Comparator 6 is present. 21 ADC1DC5 RO 1 ADC1 DC5 Present When set, indicates that ADC module 1 Digital Comparator 5 is present. 20 ADC1DC4 RO 1 ADC1 DC4 Present When set, indicates that ADC module 1 Digital Comparator 4 is present. 19 ADC1DC3 RO 1 ADC1 DC3 Present When set, indicates that ADC module 1 Digital Comparator 3 is present. 18 ADC1DC2 RO 1 ADC1 DC2 Present When set, indicates that ADC module 1 Digital Comparator 2 is present. 17 ADC1DC1 RO 1 ADC1 DC1 Present When set, indicates that ADC module 1 Digital Comparator 1 is present. 16 ADC1DC0 RO 1 ADC1 DC0 Present When set, indicates that ADC module 1 Digital Comparator 0 is present. 15:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 ADC0DC7 RO 1 ADC0 DC7 Present When set, indicates that ADC module 0 Digital Comparator 7 is present. July 22, 2011 261 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 6 ADC0DC6 RO 1 Description ADC0 DC6 Present When set, indicates that ADC module 0 Digital Comparator 6 is present. 5 ADC0DC5 RO 1 ADC0 DC5 Present When set, indicates that ADC module 0 Digital Comparator 5 is present. 4 ADC0DC4 RO 1 ADC0 DC4 Present When set, indicates that ADC module 0 Digital Comparator 4 is present. 3 ADC0DC3 RO 1 ADC0 DC3 Present When set, indicates that ADC module 0 Digital Comparator 3 is present. 2 ADC0DC2 RO 1 ADC0 DC2 Present When set, indicates that ADC module 0 Digital Comparator 2 is present. 1 ADC0DC1 RO 1 ADC0 DC1 Present When set, indicates that ADC module 0 Digital Comparator 1 is present. 0 ADC0DC0 RO 1 ADC0 DC0 Present When set, indicates that ADC module 0 Digital Comparator 0 is present. 262 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 26: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 This register is predefined by the part and can be used to verify features. Non-Volatile Memory Information (NVMSTAT) Base 0x400F.E000 Offset 0x1A0 Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 FWB RO 1 Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 FWB RO 1 32 Word Flash Write Buffer Active When set, indicates that the 32 word Flash memory write buffer feature is active. July 22, 2011 263 Texas Instruments-Production Data System Control Register 27: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 reserved Type Reset 28 WDT1 26 24 23 22 21 19 16 CAN1 CAN0 ADC1 ADC0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved RO 0 RO 0 RO 0 RO 1 MAXADC0SPD R/W 0 R/W 0 R/W 0 R/W 0 reserved RO 0 RO 0 reserved 17 R/W 0 MAXADC1SPD PWM 18 RO 0 RO 0 reserved 20 RO 0 RO 0 reserved 25 RO 0 reserved Type Reset 27 WDT0 R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 R/W 0 WDT1 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 CAN1 R/W 0 CAN1 Clock Gating Control This bit controls the clock gating for CAN module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 24 CAN0 R/W 0 CAN0 Clock Gating Control This bit controls the clock gating for CAN module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 264 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 23:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM R/W 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 19:18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 17 ADC1 R/W 0 ADC1 Clock Gating Control This bit controls the clock gating for SAR ADC module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 16 ADC0 R/W 0 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 MAXADC1SPD R/W 0 ADC1 Sample Speed This field sets the rate at which ADC module 1 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADC1SPD bit as follows (all other encodings are reserved): Value Description 9:8 MAXADC0SPD R/W 0 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second ADC0 Sample Speed This field sets the rate at which ADC0 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADC0SPD bit as follows (all other encodings are reserved): Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second July 22, 2011 265 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT0 R/W 0 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 266 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 28: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 reserved Type Reset 28 WDT1 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 reserved Type Reset RO 0 RO 0 RO 0 RO 0 27 26 reserved RO 0 RO 0 11 10 25 24 CAN1 CAN0 R/W 0 R/W 0 9 8 MAXADC1SPD MAXADC0SPD R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 reserved RO 0 20 RO 0 RO 0 R/W 0 5 4 7 6 reserved reserved RO 0 RO 1 19 PWM reserved RO 0 RO 0 18 reserved RO 0 RO 0 3 2 WDT0 R/W 0 17 16 ADC1 ADC0 R/W 0 R/W 0 1 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 R/W 0 WDT1 Clock Gating Control This bit controls the clock gating for Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 CAN1 R/W 0 CAN1 Clock Gating Control This bit controls the clock gating for CAN module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 24 CAN0 R/W 0 CAN0 Clock Gating Control This bit controls the clock gating for CAN module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 22, 2011 267 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 23:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM R/W 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 19:18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 17 ADC1 R/W 0 ADC1 Clock Gating Control This bit controls the clock gating for ADC module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 16 ADC0 R/W 0 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 MAXADC1SPD R/W 0 ADC1 Sample Speed This field sets the rate at which ADC module 1 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADC1SPD bit as follows (all other encodings are reserved): Value Description 9:8 MAXADC0SPD R/W 0 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second ADC0 Sample Speed This field sets the rate at which ADC module 0 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADC0SPD bit as follows (all other encodings are reserved): Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 268 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT0 R/W 0 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 269 Texas Instruments-Production Data System Control Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 reserved Type Reset 28 WDT1 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 27 26 reserved 25 24 CAN1 CAN0 23 RO 0 RO 0 R/W 0 R/W 0 RO 0 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 22 RO 0 RO 0 RO 0 RO 0 20 RO 0 R/W 0 6 5 4 RO 1 19 PWM RO 0 reserved RO 0 21 reserved reserved RO 0 RO 0 18 reserved RO 0 RO 0 3 2 WDT0 R/W 0 17 16 ADC1 ADC0 R/W 0 R/W 0 1 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 R/W 0 WDT1 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 CAN1 R/W 0 CAN1 Clock Gating Control This bit controls the clock gating for CAN module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 24 CAN0 R/W 0 CAN0 Clock Gating Control This bit controls the clock gating for CAN module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 270 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 23:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM R/W 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 19:18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 17 ADC1 R/W 0 ADC1 Clock Gating Control This bit controls the clock gating for ADC module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 16 ADC0 R/W 0 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT0 R/W 0 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 271 Texas Instruments-Production Data System Control Register 30: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 29 reserved Type Reset Type Reset 28 I2S0 27 26 reserved 25 24 23 22 21 20 18 17 16 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C1 reserved I2C0 QEI1 QEI0 SSI1 SSI0 reserved UART2 UART1 UART0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved RO 0 RO 0 reserved 19 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 I2S0 R/W 0 I2S0 Clock Gating This bit controls the clock gating for I2S module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 272 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 R/W 0 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 QEI1 R/W 0 QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 22, 2011 273 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 8 QEI0 R/W 0 Description QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 4 SSI0 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 274 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 31: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 reserved Type Reset Type Reset RO 0 RO 0 28 I2S0 RO 0 27 26 reserved R/W 0 RO 0 RO 0 11 10 15 14 13 12 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 reserved RO 0 RO 0 25 24 COMP1 COMP0 R/W 0 R/W 0 RO 0 RO 0 7 6 9 8 QEI1 QEI0 R/W 0 R/W 0 23 22 21 20 reserved reserved RO 0 RO 0 RO 0 RO 0 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 5 4 3 2 1 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 I2S0 R/W 0 I2S0 Clock Gating This bit controls the clock gating for I2S module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 22, 2011 275 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 R/W 0 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 QEI1 R/W 0 QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 276 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 8 QEI0 R/W 0 Description QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 4 SSI0 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 22, 2011 277 Texas Instruments-Production Data System Control Register 32: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 reserved Type Reset RO 0 Type Reset RO 0 28 I2S0 RO 0 27 26 reserved R/W 0 RO 0 RO 0 11 10 15 14 13 12 reserved I2C1 reserved I2C0 RO 0 R/W 0 RO 0 R/W 0 reserved RO 0 RO 0 25 24 COMP1 COMP0 R/W 0 R/W 0 RO 0 RO 0 7 6 9 8 QEI1 QEI0 R/W 0 R/W 0 23 22 21 20 reserved reserved RO 0 RO 0 RO 0 RO 0 19 18 17 16 TIMER3 TIMER2 TIMER1 TIMER0 R/W 0 R/W 0 R/W 0 R/W 0 5 4 3 2 1 0 SSI1 SSI0 reserved UART2 UART1 UART0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 I2S0 R/W 0 I2S0 Clock Gating This bit controls the clock gating for I2S module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 278 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 R/W 0 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 QEI1 R/W 0 QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 22, 2011 279 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 8 QEI0 R/W 0 Description QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 4 SSI0 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 280 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 33: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 31 30 29 reserved Type Reset 27 26 25 24 23 EMAC0 22 21 20 19 18 17 reserved 16 USB0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 28 RO 0 RO 0 UDMA R/W 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC layer 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 USB0 R/W 0 USB0 Clock Gating Control This bit controls the clock gating for USB module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 281 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 13 UDMA R/W 0 Description Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 12:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ R/W 0 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 7 GPIOH R/W 0 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 282 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 GPIOA R/W 0 Description Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 22, 2011 283 Texas Instruments-Production Data System Control Register 34: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 31 30 29 reserved Type Reset RO 0 RO 0 15 14 reserved Type Reset RO 0 RO 0 28 27 26 25 24 23 EMAC0 RO 0 R/W 0 RO 0 RO 0 RO 0 13 12 11 10 9 UDMA R/W 0 reserved RO 0 22 21 20 19 18 17 reserved RO 0 RO 0 RO 0 RO 0 RO 0 16 USB0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 8 7 6 5 4 3 2 1 0 GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC layer 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 USB0 R/W 0 USB0 Clock Gating Control This bit controls the clock gating for USB module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 284 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 13 UDMA R/W 0 Description Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 12:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ R/W 0 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 7 GPIOH R/W 0 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 22, 2011 285 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 0 GPIOA R/W 0 Description Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 286 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 35: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 31 30 29 reserved Type Reset RO 0 RO 0 15 14 reserved Type Reset RO 0 RO 0 28 27 26 25 24 23 EMAC0 RO 0 R/W 0 RO 0 RO 0 RO 0 13 12 11 10 9 UDMA R/W 0 reserved RO 0 22 21 20 19 18 17 reserved RO 0 RO 0 RO 0 RO 0 RO 0 16 USB0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 8 7 6 5 4 3 2 1 0 GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC layer 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 27:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 USB0 R/W 0 USB0 Clock Gating Control This bit controls the clock gating for USB module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 287 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 13 UDMA R/W 0 Description Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 12:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ R/W 0 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 7 GPIOH R/W 0 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 288 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 GPIOA R/W 0 Description Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. July 22, 2011 289 Texas Instruments-Production Data System Control Register 36: Software Reset Control 0 (SRCR0), offset 0x040 This register allows individual modules to be reset. Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 reserved Type Reset 28 WDT1 27 26 reserved 25 24 23 22 21 reserved 20 PWM 18 reserved 17 16 CAN1 CAN0 ADC1 ADC0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 19 WDT0 R/W 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 WDT1 R/W 0 WDT1 Reset Control When this bit is set, Watchdog Timer module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 CAN1 R/W 0 CAN1 Reset Control When this bit is set, CAN module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 24 CAN0 R/W 0 CAN0 Reset Control When this bit is set, CAN module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 23:21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 PWM R/W 0 PWM Reset Control When this bit is set, PWM module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 19:18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 290 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 17 ADC1 R/W 0 Description ADC1 Reset Control When this bit is set, ADC module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 16 ADC0 R/W 0 ADC0 Reset Control When this bit is set, ADC module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 15:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 WDT0 R/W 0 WDT0 Reset Control When this bit is set, Watchdog Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 291 Texas Instruments-Production Data System Control Register 37: Software Reset Control 1 (SRCR1), offset 0x044 This register allows individual modules to be reset. Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 29 reserved Type Reset Type Reset 28 I2S0 27 26 reserved 25 24 23 22 21 20 18 17 16 COMP1 COMP0 TIMER3 TIMER2 TIMER1 TIMER0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C1 reserved I2C0 QEI1 QEI0 SSI1 SSI0 reserved UART2 UART1 UART0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved RO 0 RO 0 reserved 19 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 I2S0 R/W 0 I2S0 Reset Control When this bit is set, I2S module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 25 COMP1 R/W 0 Analog Comp 1 Reset Control When this bit is set, Analog Comparator module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 24 COMP0 R/W 0 Analog Comp 0 Reset Control When this bit is set, Analog Comparator module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 TIMER3 R/W 0 Timer 3 Reset Control Timer 3 Reset Control. When this bit is set, General-Purpose Timer module 3 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 18 TIMER2 R/W 0 Timer 2 Reset Control When this bit is set, General-Purpose Timer module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 292 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 17 TIMER1 R/W 0 Description Timer 1 Reset Control When this bit is set, General-Purpose Timer module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 16 TIMER0 R/W 0 Timer 0 Reset Control When this bit is set, General-Purpose Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 I2C1 R/W 0 I2C1 Reset Control When this bit is set, I2C module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 I2C0 R/W 0 I2C0 Reset Control When this bit is set, I2C module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 QEI1 R/W 0 QEI1 Reset Control When this bit is set, QEI module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 8 QEI0 R/W 0 QEI0 Reset Control When this bit is set, QEI module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 SSI1 R/W 0 SSI1 Reset Control When this bit is set, SSI module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 4 SSI0 R/W 0 SSI0 Reset Control When this bit is set, SSI module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. July 22, 2011 293 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 UART2 R/W 0 UART2 Reset Control When this bit is set, UART module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 1 UART1 R/W 0 UART1 Reset Control When this bit is set, UART module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0 UART0 R/W 0 UART0 Reset Control When this bit is set, UART module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 294 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 38: Software Reset Control 2 (SRCR2), offset 0x048 This register allows individual modules to be reset. Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 31 30 29 reserved Type Reset 27 26 25 24 23 EMAC0 22 21 20 19 18 17 reserved 16 USB0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 28 RO 0 RO 0 UDMA R/W 0 reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 EMAC0 R/W 0 MAC0 Reset Control When this bit is set, Ethernet MAC layer 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 27:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 USB0 R/W 0 USB0 Reset Control When this bit is set, USB module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 UDMA R/W 0 Micro-DMA Reset Control When this bit is set, uDMA module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 12:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8 GPIOJ R/W 0 Port J Reset Control When this bit is set, Port J module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. July 22, 2011 295 Texas Instruments-Production Data System Control Bit/Field Name Type Reset 7 GPIOH R/W 0 Description Port H Reset Control When this bit is set, Port H module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 6 GPIOG R/W 0 Port G Reset Control When this bit is set, Port G module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 5 GPIOF R/W 0 Port F Reset Control When this bit is set, Port F module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 4 GPIOE R/W 0 Port E Reset Control When this bit is set, Port E module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 3 GPIOD R/W 0 Port D Reset Control When this bit is set, Port D module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 2 GPIOC R/W 0 Port C Reset Control When this bit is set, Port C module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 1 GPIOB R/W 0 Port B Reset Control When this bit is set, Port B module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0 GPIOA R/W 0 Port A Reset Control When this bit is set, Port A module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 296 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 6 Internal Memory The LM3S9L71 microcontroller comes with 48 KB of bit-banded SRAM, internal ROM,and 128 KB of Flash memory. The Flash memory controller provides a user-friendly interface, making Flash memory programming a simple task. Flash memory protection can be applied to the Flash memory on a 2-KB block basis. 6.1 Block Diagram Figure 6-1 on page 297 illustrates the internal memory blocks and control logic. The dashed boxes in the figure indicate registers residing in the System Control module. Figure 6-1. Internal Memory Block Diagram ROM Control ROM Array RMCTL Flash Control Icode Bus Cortex-M3 FMA FMD FMC FCRIS FCIM FCMISC Dcode Bus Flash Array System Bus Flash Write Buffer FMC2 FWBVAL FWBn 32 words Flash Protection Bridge FMPREn FMPRE FMPPEn FMPPE User Registers Flash Timing BOOTCFG USECRL USER_REG0 USER_REG1 USER_REG2 USER_REG3 SRAM Array 6.2 Functional Description This section describes the functionality of the SRAM, ROM, and Flash memories. Note: The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. July 22, 2011 297 Texas Instruments-Production Data Internal Memory 6.2.1 SRAM ® The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM provides bit-banding technology in the processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band base is located at address 0x2200.0000. The bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, see “Bit-Banding” on page 95. Note: 6.2.2 The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays). The banks are partitioned such that one bank contains all even words (the even bank) and the other contains all odd words (the odd bank). A write access that is followed immediately by a read access to the same bank incurs a stall of a single clock cycle. However, a write to one bank followed by a read of the other bank can occur in successive clock cycles without incurring any delay. ROM The internal ROM of the Stellaris device is located at address 0x0100.0000 of the device memory map. Detailed information on the ROM contents can be found in the Stellaris® ROM User’s Guide. The ROM contains the following components: ■ Stellaris Boot Loader and vector table ■ Stellaris Peripheral Driver Library (DriverLib) release for product-specific peripherals and interfaces ■ Advanced Encryption Standard (AES) cryptography tables ■ Cyclic Redundancy Check (CRC) error detection functionality The boot loader is used as an initial program loader (when the Flash memory is empty) as well as an application-initiated firmware upgrade mechanism (by calling back to the boot loader). The Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory requirements and freeing the Flash memory to be used for other purposes (such as additional features in the application). Advance Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government and Cyclic Redundancy Check (CRC) is a technique to validate a span of data has the same contents as when previously checked. 6.2.2.1 Boot Loader Overview The Stellaris Boot Loader is used to download code to the Flash memory of a device without the use of a debug interface. When the core is reset, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal in Ports A-H as configured in the Boot Configuration (BOOTCFG) register. 298 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always executed. The boot sequence executed from ROM is as follows: 1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is mapped to address 0x0. 2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. The boot loader uses a simple packet interface to provide synchronous communication with the device. The speed of the boot loader is determined by the internal oscillator (PIOSC) frequency as it does not enable the PLL. The following serial interfaces can be used: ■ UART0 ■ SSI0 ■ I2C0 ■ Ethernet For simplicity, both the data format and communication protocol are identical for all serial interfaces. Note: The Flash-memory-resident version of the Boot Loader also supports CAN and USB. See the Stellaris® Boot Loader User's Guide for information on the boot loader software. 6.2.2.2 Stellaris Peripheral Driver Library The Stellaris Peripheral Driver Library contains a file called driverlib/rom.h that assists with calling the peripheral driver library functions in the ROM. The detailed description of each function is available in the Stellaris® ROM User’s Guide. See the "Using the ROM" chapter of the Stellaris® Peripheral Driver Library User's Guide for more details on calling the ROM functions and using driverlib/rom.h. A table at the beginning of the ROM points to the entry points for the APIs that are provided in the ROM. Accessing the API through these tables provides scalability; while the API locations may change in future versions of the ROM, the API tables will not. The tables are split into two levels; the main table contains one pointer per peripheral which points to a secondary table that contains one pointer per API that is associated with that peripheral. The main table is located at 0x0100.0010, right after the Cortex-M3 vector table in the ROM. DriverLib functions are described in detail in the Stellaris® Peripheral Driver Library User's Guide. Additional APIs are available for graphics and USB functions, but are not preloaded into ROM. The Stellaris Graphics Library provides a set of graphics primitives and a widget set for creating graphical user interfaces on Stellaris microcontroller-based boards that have a graphical display (for more information, see the Stellaris® Graphics Library User's Guide). The Stellaris USB Library is a set July 22, 2011 299 Texas Instruments-Production Data Internal Memory of data types and functions for creating USB Device, Host or On-The-Go (OTG) applications on Stellaris microcontroller-based boards (for more information, see the Stellaris® USB Library User's Guide). 6.2.2.3 Advanced Encryption Standard (AES) Cryptography Tables AES is a strong encryption method with reasonable performance and size. AES is fast in both hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for applications that can use pre-arranged keys, such as setup during manufacturing or configuration. Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the forward S-box substitution table, the second is the reverse S-box substitution table, the third is the forward polynomial table, and the final is the reverse polynomial table. See the Stellaris® ROM User’s Guide for more information on AES. 6.2.2.4 Cyclic Redundancy Check (CRC) Error Detection The CRC technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that Flash memory contents have not been changed, and for other cases where the data needs to be validated. A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more readily. See the Stellaris® ROM User’s Guide for more information on CRC. 6.2.3 Flash Memory At system clock speeds of 50 MHz and below, the Flash memory is read in a single cycle. The Flash memory is organized as a set of 1-KB blocks that can be individually erased. An individual 32-bit word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability to concurrently program 32 continuous words in Flash memory. Erasing a block causes the entire contents of the block to be reset to all 1s. The 1-KB blocks are paired into sets of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. Caution – The Stellaris Flash memory array has ECC which uses a test port into the Flash memory to continually scan the array for ECC errors and to correct any that are detected. This operation is transparent to the microcontroller. The BIST must scan the entire memory array occasionally to ensure integrity, taking about five minutes to do so. In systems where the microcontroller is frequently powered for less than five minutes, power should be removed from the microcontroller in a controlled manner to ensure proper operation. Software can request permission to power down the part using the USDREQ bit in the Flash Control (FCTL) register and wait to receive an acknowledge from the USDACK bit prior to removing power. If the microcontroller is powered down using this controlled method, the BIST engine keeps track of where it was in the memory array and it always scans the complete array after any aggregate of five minutes powered-on, regardless of the number of intervening power cycles. If the microcontroller is powered down before five minutes of being powered up, BIST starts again from wherever it left off before the last controlled power-down or from 0 if there never was a controlled power down. An occasional short power down is not a concern, but the microcontroller should not always be powered down frequently in an uncontrolled manner. The microcontroller can be power-cycled as frequently as necessary if it is powered-down in a controlled manner. 300 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 6.2.3.1 Prefetch Buffer The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency is greater than 50 MHz. In this mode, the Flash memory operates at half of the system clock. The prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait states while code is executing linearly. The fetch buffer includes a branch speculation mechanism that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short loop branches often stay in the buffer. As a result, some branches can be executed with no wait states. Other branches incur a single wait state. 6.2.3.2 Flash Memory Protection The user is provided two forms of Flash memory protection per 2-KB Flash memory block in two pairs of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If a bit is set, the corresponding block may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may be executed or read by software or debuggers. If a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. The policies may be combined as shown in Table 6-1 on page 301. Table 6-1. Flash Memory Protection Policy Combinations FMPPEn FMPREn 0 0 Protection Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. 1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. 0 1 Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 1 1 No protection. The block may be written, erased, executed or read. A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited and generates a bus fault. A Flash memory access that attempts to program or erase a program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt (by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. These settings create a policy of open access and programmability. The register bits may be changed by clearing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The changes are committed using the Flash Memory Control (FMC) register. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 304. 6.2.3.3 Interrupts The Flash memory controller can generate interrupts when the following conditions are observed: July 22, 2011 301 Texas Instruments-Production Data Internal Memory ■ Programming Interrupt - signals when a program or erase action is complete. ■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block of memory that is protected by its corresponding FMPPEn bit. The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller Masked Interrupt Status (FCMIS) register (see page 312) by setting the corresponding MASK bits. If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw Interrupt Status (FCRIS) register (see page 311). Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register (see page 313). 6.2.3.4 Flash Memory Programming The Stellaris devices provide a user-friendly interface for Flash memory programming. All erase/program operations are handled via three registers: Flash Memory Address (FMA), Flash Memory Data (FMD), and Flash Memory Control (FMC). Note that if the debug capabilities of the microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be performed in order to reactivate the debug module. See “Recovering a "Locked" Microcontroller” on page 186. During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation is complete. If instruction execution is required during a Flash memory operation, the code that is executing must be placed in SRAM and executed from there while the flash operation is in progress. Caution – The Flash memory is divided into sectors of electrically separated address ranges of 4 KB each, aligned on 4 KB boundaries. Erase/program operations on a 1-KB page have an electrical effect on the other three 1-KB pages within the sector. A specific 1-KB page must be erased after 6 total erase/program cycles occur to the other pages within its 4-KB sector. The following sequence of operations on a 4-KB sector of Flash memory (Page 0..3) provides an example: ■ Page 3 is erase and programmed with values. ■ Page 0, Page 1, and Page 2 are erased and then programmed with values. At this point Page 3 has been affected by 3 erase/program cycles. ■ Page 0, Page 1, and Page 2 are again erased and then programmed with values. At this point Page 3 has been affected by 6 erase/program cycles. ■ If the contents of Page 3 must continue to be valid, Page 3 must be erased and reprogrammed before any other page in this sector has another erase or program operation. To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the Flash memory write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 302 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Important: To ensure proper operation, two writes to the same word must be separated by an ERASE. The following two sequences are allowed: ■ ERASE -> PROGRAM value -> PROGRAM 0x0000.0000 ■ ERASE -> PROGRAM value -> ERASE The following sequence is NOT allowed: ■ ERASE -> PROGRAM value -> PROGRAM value To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the Flash memory write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared or, alternatively, enable the programming interrupt using the PMASK bit in the FCIM register. To perform a mass erase of the Flash memory 1. Write the Flash memory write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared or, alternatively, enable the programming interrupt using the PMASK bit in the FCIM register. 6.2.3.5 32-Word Flash Memory Write Buffer A 32-word write buffer provides the capability to perform faster write accesses to the Flash memory by concurrently programing 32 words with a single buffered Flash memory write operation. The buffered Flash memory write operation takes the same amount of time as the single word write operation controlled by bit 0 in the FMC register. The data for the buffered write is written to the Flash Write Buffer (FWBn) registers. The registers are 32-word aligned with Flash memory, and therefore the register FWB0 corresponds with the address in FMA where bits [6:0] of FMA are all 0. FWB1 corresponds with the address in FMA + 0x4 and so on. Only the FWBn registers that have been updated since the previous buffered Flash memory write operation are written. The Flash Write Buffer Valid (FWBVAL) register shows which registers have been written since the last buffered Flash memory write operation. This register contains a bit for each of the 32 FWBn registers, where bit[n] of FWBVAL corresponds to FWBn. The FWBn register has been updated if the corresponding bit in the FWBVAL register is set. To program 32 words with a single buffered Flash memory write operation 1. Write the source data to the FWBn registers. 2. Write the target address to the FMA register. This must be a 32-word aligned address (that is, bits [6:0] in FMA must be 0s). 3. Write the Flash memory write key and the WRBUF bit (a value of 0xA442.0001) to the FMC2 register. July 22, 2011 303 Texas Instruments-Production Data Internal Memory 4. Poll the FMC2 register until the WRBUF bit is cleared or wait for the PMIS interrupt to be signaled. 6.2.3.6 Nonvolatile Register Programming This section discusses how to update registers that are resident within the Flash memory itself. These registers exist in a separate space from the main Flash memory array and are not affected by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0 with a write operation. The register contents are unaffected by any reset condition except power-on reset, which returns the register contents to 0xFFFF.FFFF. By committing the register values using the COMT bit in the FMC register, the register contents become nonvolatile and are therefore retained following power cycling. Once the register contents are committed, the only way to restore the factory default values is to perform the sequence described in “Recovering a "Locked" Microcontroller” on page 186. With the exception of the Boot Configuration (BOOTCFG) register, the settings in these registers can be tested before committing them to Flash memory. For the BOOTCFG register, the data to be written is loaded into the FMD register before it is committed. The FMD register is read only and does not allow the BOOTCFG operation to be tried before committing it to nonvolatile memory. Important: The Flash memory resident registers can only have bits changed from 1 to 0 by user programming and can only be committed once. After being committed, these registers can only be restored to their factory default values only by performing the sequence described in “Recovering a "Locked" Microcontroller” on page 186. The mass erase of the main Flash memory array caused by the sequence is performed prior to restoring these registers. In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and BOOTCFG registers each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be changed from 1 to 0. Table 6-2 on page 304 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 6-2. User-Programmable Flash Memory Resident Registers Register to be Committed FMPRE0 6.3 FMA Value Data Source 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.0001 USER_REG1 USER_REG2 0x8000.0002 USER_REG2 USER_REG3 0x8000.0003 USER_REG3 BOOTCFG 0x7510.0000 FMD Register Map Table 6-3 on page 305 lists the ROM Controller register and the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, FCMISC, FMC2, FWBVAL, and FWBn register offsets are relative to the Flash memory control base address of 0x400F.D000. The ROM and Flash memory protection register offsets are relative to the System Control base address of 0x400F.E000. 304 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 6-3. Flash Register Map Offset Name Type Reset Description See page Flash Memory Registers (Flash Control Offset) 0x000 FMA R/W 0x0000.0000 Flash Memory Address 306 0x004 FMD R/W 0x0000.0000 Flash Memory Data 307 0x008 FMC R/W 0x0000.0000 Flash Memory Control 308 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 311 0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 312 0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 313 0x020 FMC2 R/W 0x0000.0000 Flash Memory Control 2 314 0x030 FWBVAL R/W 0x0000.0000 Flash Write Buffer Valid 315 0x0F8 FCTL R/W 0x0000.0000 Flash Control 316 0x100 0x17C FWBn R/W 0x0000.0000 Flash Write Buffer n 317 ROM Control 318 Memory Registers (System Control Offset) 0x0F0 RMCTL R/W1C - 0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 319 0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 319 0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 320 0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 320 0x1D0 BOOTCFG R/W 0xFFFF.FFFE Boot Configuration 321 0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 323 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 324 0x1E8 USER_REG2 R/W 0xFFFF.FFFF User Register 2 325 0x1EC USER_REG3 R/W 0xFFFF.FFFF User Register 3 326 0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 327 0x208 FMPRE2 R/W 0x0000.0000 Flash Memory Protection Read Enable 2 328 0x20C FMPRE3 R/W 0x0000.0000 Flash Memory Protection Read Enable 3 329 0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 330 0x408 FMPPE2 R/W 0x0000.0000 Flash Memory Protection Program Enable 2 331 0x40C FMPPE3 R/W 0x0000.0000 Flash Memory Protection Program Enable 3 332 6.4 Flash Memory Register Descriptions (Flash Control Offset) This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. July 22, 2011 305 Texas Instruments-Production Data Internal Memory Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned CPU byte address and specifies which block is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 16 OFFSET OFFSET Type Reset Bit/Field Name Type Reset Description 31:17 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16:0 OFFSET R/W 0x0 Address Offset Address offset in Flash memory where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 304 for details on values for this field). 306 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DATA Type Reset DATA Type Reset Bit/Field Name Type 31:0 DATA R/W Reset Description 0x0000.0000 Data Value Data value for write operation. July 22, 2011 307 Texas Instruments-Production Data Internal Memory Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 306). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 307) is written to the specified address. This register must be the final register written and initiates the memory operation. The four control bits in the lower byte of this register are used to initiate memory operations. Care must be taken not to set multiple control bits as the results of such an operation are unpredictable. Caution – If any of bits [15:4] are written to 1, the device may become inoperable. These bits should always be written to 0. In all registers, the value of a reserved bit should be preserved across a read-modify-write operation. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 COMT MERASE ERASE WRITE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 WRKEY Type Reset reserved Type Reset Bit/Field Name Type Reset 31:16 WRKEY WO 0x0000 Description Flash Memory Write Key This field contains a write key, which is used to minimize the incidence of accidental Flash memory writes. The value 0xA442 must be written into this field for a Flash memory write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 15:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 308 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 3 COMT R/W 0 Description Commit Register Value This bit is used to commit writes to Flash-memory-resident registers and to monitor the progress of that process. Value Description 1 Set this bit to commit (write) the register value to a Flash-memory-resident register. When read, a 1 indicates that the previous commit access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous commit access is complete. See “Nonvolatile Register Programming” on page 304 for more information on programming Flash-memory-resident registers. 2 MERASE R/W 0 Mass Erase Flash Memory This bit is used to mass erase the Flash main memory and to monitor the progress of that process. Value Description 1 Set this bit to erase the Flash main memory. When read, a 1 indicates that the previous mass erase access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous mass erase access is complete. For information on erase time, see “Flash Memory ” on page 1198. 1 ERASE R/W 0 Erase a Page of Flash Memory This bit is used to erase a page of Flash memory and to monitor the progress of that process. Value Description 1 Set this bit to erase the Flash memory page specified by the contents of the FMA register. When read, a 1 indicates that the previous page erase access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous page erase access is complete. For information on erase time, see “Flash Memory ” on page 1198. July 22, 2011 309 Texas Instruments-Production Data Internal Memory Bit/Field Name Type Reset 0 WRITE R/W 0 Description Write a Word into Flash Memory This bit is used to write a word into Flash memory and to monitor the progress of that process. Value Description 1 Set this bit to write the data stored in the FMD register into the Flash memory location specified by the contents of the FMA register. When read, a 1 indicates that the write update access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous write update access is complete. For information on programming time, see “Flash Memory ” on page 1198. 310 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the Flash memory controller has an interrupt condition. An interrupt is sent to the interrupt controller only if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PRIS ARIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 PRIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Raw Interrupt Status This bit provides status on programming cycles which are write or erase actions generated through the FMC or FMC2 register bits (see page 308 and page 314). Value Description 1 The programming or erase cycle has completed. 0 The programming or erase cycle has not completed. This status is sent to the interrupt controller when the PMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register. 0 ARIS RO 0 Access Raw Interrupt Status Value Description 1 A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. 0 No access has tried to improperly program or erase the Flash memory. This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register. July 22, 2011 311 Texas Instruments-Production Data Internal Memory Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the Flash memory controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PMASK AMASK RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 PMASK R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the interrupt controller. Value Description 0 AMASK R/W 0 1 An interrupt is sent to the interrupt controller when the PRIS bit is set. 0 The PRIS interrupt is suppressed and not sent to the interrupt controller. Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the interrupt controller. Value Description 1 An interrupt is sent to the interrupt controller when the ARIS bit is set. 0 The ARIS interrupt is suppressed and not sent to the interrupt controller. 312 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 PMISC R/W1C 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 1 0 PMISC AMISC R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. Writing a 1 to this bit clears PMISC and also the PRIS bit in the FCRIS register (see page 311). 0 When read, a 0 indicates that a programming cycle complete interrupt has not occurred. A write of 0 has no effect on the state of this bit. 0 AMISC R/W1C 0 Access Masked Interrupt Status and Clear Value Description 1 When read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. Writing a 1 to this bit clears AMISC and also the ARIS bit in the FCRIS register (see page 311). 0 When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit. July 22, 2011 313 Texas Instruments-Production Data Internal Memory Register 7: Flash Memory Control 2 (FMC2), offset 0x020 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 306). If the access is a write access, the data contained in the Flash Write Buffer (FWB) registers is written. This register must be the final register written as it initiates the memory operation. Flash Memory Control 2 (FMC2) Base 0x400F.D000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 WRKEY Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:16 WRKEY WO 0x0000 RO 0 0 WRBUF RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 Description Flash Memory Write Key This field contains a write key, which is used to minimize the incidence of accidental Flash memory writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC2 register without this WRKEY value are ignored. A read of this field returns the value 0. 15:1 reserved RO 0x000 0 WRBUF R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Buffered Flash Memory Write This bit is used to start a buffered write to Flash memory. Value Description 1 Set this bit to write the data stored in the FWBn registers to the location specified by the contents of the FMA register. When read, a 1 indicates that the previous buffered Flash memory write access is not complete. 0 A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous buffered Flash memory write access is complete. For information on programming time, see “Flash Memory ” on page 1198. 314 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 This register provides a bitwise status of which FWBn registers have been written by the processor since the last write of the Flash memory write buffer. The entries with a 1 are written on the next write of the Flash memory write buffer. This register is cleared after the write operation by hardware. A protection violation on the write operation also clears this status. Software can program the same 32 words to various Flash memory locations by setting the FWB[n] bits after they are cleared by the write operation. The next write operation then uses the same data as the previous one. In addition, if a FWBn register change should not be written to Flash memory, software can clear the corresponding FWB[n] bit to preserve the existing data when the next write operation occurs. Flash Write Buffer Valid (FWBVAL) Base 0x400F.D000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FWB[n] Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 FWB[n] Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:0 FWB[n] R/W 0x0 R/W 0 Description Flash Memory Write Buffer Value Description 1 The corresponding FWBn register has been updated since the last buffer write operation and is ready to be written to Flash memory. 0 The corresponding FWBn register has no new data to be written. Bit 0 corresponds to FWB0, offset 0x100, and bit 31 corresponds to FWB31, offset 0x13C. July 22, 2011 315 Texas Instruments-Production Data Internal Memory Register 9: Flash Control (FCTL), offset 0x0F8 This register is used to ensure that the microcontroller is powered down in a controlled fashion in systems where power is cycled more frequently than once every five minutes. The USDREQ bit should be set to indicate that power is going to be turned off. Software should poll the USDACK bit to determine when it is acceptable to power down. Flash Control (FCTL) Base 0x400F.D000 Offset 0x0F8 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 USDACK RO 0 USDACK USDREQ RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. User Shut Down Acknowledge Value Description 1 The microcontroller can be powered down. 0 The microcontroller cannot yet be powered down. This bit should be set within 50 ms of setting the USDREQ bit. 0 USDREQ R/W 0 User Shut Down Request Value Description 1 Requests permission to power down the microcontroller. 0 No effect. 316 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C These 32 registers hold the contents of the data to be written into the Flash memory on a buffered Flash memory write operation. The offset selects one of the 32-bit registers. Only FWBn registers that have been updated since the preceding buffered Flash memory write operation are written into the Flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or 2 words. The FWBn registers are written into the Flash memory with the FWB0 register corresponding to the address contained in FMA. FWB1 is written to the address FMA+0x4 etc. Note that only data bits that are 0 result in the Flash memory being modified. A data bit that is 1 leaves the content of the Flash memory bit at its previous value. Flash Write Buffer n (FWBn) Base 0x400F.D000 Offset 0x100 - 0x17C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DATA Type Reset DATA Type Reset Bit/Field Name Type 31:0 DATA R/W Reset Description 0x0000.0000 Data Data to be written into the Flash memory. 6.5 Memory Register Descriptions (System Control Offset) The remainder of this section lists and describes the registers that reside in the System Control address space, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. July 22, 2011 317 Texas Instruments-Production Data Internal Memory Register 11: ROM Control (RMCTL), offset 0x0F0 This register provides control of the ROM controller state. This register offset is relative to the System Control base address of 0x400F.E000. At reset, the ROM is mapped over the Flash memory so that the ROM boot sequence is always executed. The boot sequence executed from ROM is as follows: 1. The BA bit (below) is cleared such that ROM is mapped to 0x01xx.xxxx and Flash memory is mapped to address 0x0. 2. The BOOTCFG register is read. If the EN bit is clear, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. ROM Control (RMCTL) Base 0x400F.E000 Offset 0x0F0 Type R/W1C, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 BA R/W1C 1 RO 0 0 BA RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Boot Alias Value Description 1 The microcontroller's ROM appears at address 0x0. 0 The Flash memory is at address 0x0. This bit is cleared by writing a 1 to this bit position. 318 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.E000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. July 22, 2011 319 Texas Instruments-Production Data Internal Memory Register 13: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.E000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 PROG_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. 320 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 14: Boot Configuration (BOOTCFG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides configuration of a GPIO pin to enable the ROM Boot Loader as well as a write-once mechanism to disable external debugger access to the device. Upon reset, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal from Ports A-H as configured by the bits in this register. If the EN bit is set or the specified pin does not have the required polarity, the system control module checks address 0x000.0004 to see if the Flash memory has a valid reset vector. If the data at address 0x0000.0004 is 0xFFFF.FFFF, then it is assumed that the Flash memory has not yet been programmed, and the core executes the ROM Boot Loader. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Clearing the DBG1 bit disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. Boot Configuration (BOOTCFG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 30 29 28 27 26 25 24 NW Type Reset R/W 1 15 RO 1 RO 1 RO 1 14 13 12 PORT Type Reset R/W 1 23 22 21 20 19 18 17 16 RO 1 RO 1 reserved R/W 1 RO 1 RO 1 11 10 PIN R/W 1 R/W 1 R/W 1 R/W 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 9 8 POL EN R/W 1 R/W 1 reserved RO 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written RO 1 RO 1 RO 1 RO 1 RO 1 1 0 DBG1 DBG0 R/W 1 R/W 0 When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:16 reserved RO 0x7FFF Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 321 Texas Instruments-Production Data Internal Memory Bit/Field Name Type Reset 15:13 PORT R/W 0x7 Description Boot GPIO Port This field selects the port of the GPIO port pin that enables the ROM boot loader at reset. Value Description 12:10 PIN R/W 0x7 0x0 Port A 0x1 Port B 0x2 Port C 0x3 Port D 0x4 Port E 0x5 Port F 0x6 Port G 0x7 Port H Boot GPIO Pin This field selects the pin number of the GPIO port pin that enables the ROM boot loader at reset. Value Description 9 POL R/W 0x1 0x0 Pin 0 0x1 Pin 1 0x2 Pin 2 0x3 Pin 3 0x4 Pin 4 0x5 Pin 5 0x6 Pin 6 0x7 Pin 7 Boot GPIO Polarity When set, this bit selects a high level for the GPIO port pin to enable the ROM boot loader at reset. When clear, this bit selects a low level for the GPIO port pin. 8 EN R/W 0x1 Boot GPIO Enable Clearing this bit enables the use of a GPIO pin to enable the ROM Boot Loader at reset. When this bit is set, the contents of address 0x0000.0004 are checked to see if the Flash memory has been programmed. If the contents are not 0xFFFF.FFFF, the core executes out of Flash memory. If the Flash has not been programmed, the core executes out of ROM. 7:2 reserved RO 0x3F 1 DBG1 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0x0 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 322 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 15: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. The only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG section. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. July 22, 2011 323 Texas Instruments-Production Data Internal Memory Register 16: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 324 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 17: User Register 2 (USER_REG2), offset 0x1E8 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 2 (USER_REG2) Base 0x400F.E000 Offset 0x1E8 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. July 22, 2011 325 Texas Instruments-Production Data Internal Memory Register 18: User Register 3 (USER_REG3), offset 0x1EC Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 3 (USER_REG3) Base 0x400F.E000 Offset 0x1EC Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 NW Type Reset 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 DATA R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31 NW R/W 1 Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 326 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 19: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 1 Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. July 22, 2011 327 Texas Instruments-Production Data Internal Memory Register 20: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 0 Reset R/W 0 R/W 0 Description 0x00000000 Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 129 to 192 KB. 328 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 21: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 READ_ENABLE R/W R/W 0 Reset R/W 0 R/W 0 Description 0x00000000 Flash Read Enable Configures 2-KB flash blocks to be read or executed only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 193 to 256 KB. July 22, 2011 329 Texas Instruments-Production Data Internal Memory Register 22: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 1 R/W 1 Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. 330 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 23: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 0 R/W 0 Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 129 to 192 KB. July 22, 2011 331 Texas Instruments-Production Data Internal Memory Register 24: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PROG_ENABLE Type Reset PROG_ENABLE Type Reset Bit/Field Name Type 31:0 PROG_ENABLE R/W Reset R/W 0 R/W 0 Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Bits [31:0] each enable protection on a 2-KB block of Flash memory in the range from 193 to 256 KB. 332 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 7 Micro Direct Memory Access (μDMA) The LM3S9L71 microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex™-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: ® ® ■ ARM PrimeCell 32-channel configurable µDMA controller ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Primary and secondary channel assignments – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable priority scheme – Optional software-initiated requests for any channel ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping – Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Transfer size is programmable in binary steps from 1 to 1024 ■ Source and destination address increment size of byte, half-word, word, or no increment ■ Maskable peripheral requests July 22, 2011 333 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 7.1 Block Diagram Figure 7-1. μDMA Block Diagram uDMA Controller DMA error System Memory CH Control Table Peripheral DMA Channel 0 • • • Peripheral DMA Channel N-1 Nested Vectored Interrupt Controller (NVIC) IRQ General Peripheral N Registers request done request done request done DMASTAT DMACFG DMACTLBASE DMAALTBASE DMAWAITSTAT DMASWREQ DMAUSEBURSTSET DMAUSEBURSTCLR DMAREQMASKSET DMAREQMASKCLR DMAENASET DMAENACLR DMAALTSET DMAALTCLR DMAPRIOSET DMAPRIOCLR DMAERRCLR DMACHASGN DMASRCENDP DMADSTENDP DMACHCTRL • • • DMASRCENDP DMADSTENDP DMACHCTRL Transfer Buffers Used by µDMA ARM Cortex-M3 7.2 Functional Description The μDMA controller is a flexible and highly configurable DMA controller designed to work efficiently with the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow for sophisticated programmed data transfers. The μDMA controller's usage of the bus is always subordinate to the processor core, so it never holds up a bus transaction by the processor. Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth it provides is essentially free, with no impact on the rest of the system. The bus architecture has been optimized to greatly enhance the ability of the processor core and the μDMA controller to efficiently share the on-chip bus, thus improving performance. The optimizations include RAM striping and peripheral bus segmentation, which in many cases allow both the processor core and the μDMA controller to access the bus and perform simultaneous data transfers. The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. Each peripheral function that is supported has a dedicated channel on the μDMA controller that can be configured independently. The μDMA controller implements a unique configuration method using channel control structures that are maintained in system memory by the processor. While simple transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that allow the μDMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The μDMA controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or from a peripheral. Each channel also has a configurable arbitration size. The arbitration size is the number of items that are transferred in a burst before the μDMA controller rearbitrates for channel priority. Using the 334 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time it makes a μDMA service request. 7.2.1 Channel Assignments μDMA channels 0-31 are assigned to peripherals according to the following table. The DMA Channel Assignment (DMACHASGN) register (see page 381) can be used to specify the primary or secondary assignment. If the primary function is not available on this microcontroller, the secondary function becomes the primary function. If the secondary function is not available, the primary function is the only option. Note: Channels noted in the table as "Available for software" may be assigned to peripherals in the future. However, they are currently available for software use. Channel 30 is dedicated for software use. The USB endpoints mapped to μDMA channels 0-3 can be changed with the USBDMASEL register (see page 1000). Because of the way the μDMA controller interacts with peripherals, the μDMA channel for the peripheral must be enabled in order for the μDMA controller to be able to read and write the peripheral registers, even if a different μDMA channel is used to perform the μDMA transfer. To minimize confusion and chance of software errors, it is best practice to use a peripheral's μDMA channel for performing all μDMA transfers for that peripheral, even if it is processor-triggered and using AUTO mode, which could be considered a software transfer. Note that if the software channel is used, interrupts occur on the dedicated μDMA interrupt vector. If the peripheral channel is used, then the interrupt occurs on the interrupt vector for the peripheral. Table 7-1. μDMA Channel Assignments μDMA Channel Primary Assignment Secondary Assignment 0 USB Endpoint 1 Receive UART2 Receive 1 USB Endpoint 1 Transmit UART2 Transmit 2 USB Endpoint 2 Receive General-Purpose Timer 3A 3 USB Endpoint 2 Transmit General-Purpose Timer 3B 4 USB Endpoint 3 Receive General-Purpose Timer 2A 5 USB Endpoint 3 Transmit General-Purpose Timer 2B 6 Ethernet Receive General-Purpose Timer 2A 7 Ethernet Transmit General-Purpose Timer 2B 8 UART0 Receive UART1 Receive 9 UART0 Transmit UART1 Transmit 10 SSI0 Receive SSI1 Receive 11 SSI0 Transmit SSI1 Transmit 12 Available for software UART2 Receive 13 Available for software UART2 Transmit 14 ADC0 Sample Sequencer 0 General-Purpose Timer 2A 15 ADC0 Sample Sequencer 1 General-Purpose Timer 2B 16 ADC0 Sample Sequencer 2 Available for software 17 ADC0 Sample Sequencer 3 Available for software 18 General-Purpose Timer 0A General-Purpose Timer 1A 19 General-Purpose Timer 0B General-Purpose Timer 1B July 22, 2011 335 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Table 7-1. μDMA Channel Assignments (continued) μDMA Channel 7.2.2 Primary Assignment Secondary Assignment 20 General-Purpose Timer 1A Available for software 21 General-Purpose Timer 1B Available for software 22 UART1 Receive Available for software 23 UART1 Transmit Available for software 24 SSI1 Receive ADC1 Sample Sequencer 0 25 SSI1 Transmit ADC1 Sample Sequencer 1 26 Available for software ADC1 Sample Sequencer 2 27 Available for software ADC1 Sample Sequencer 3 28 I2S0 Receive Available for software 29 I2S0 Available for software 30 Dedicated for software use 31 Reserved Transmit Priority The μDMA controller assigns priority to each channel based on the channel number and the priority level bit for the channel. Channel number 0 has the highest priority and as the channel number increases, the priority of a channel decreases. Each channel has a priority level bit to provide two levels of priority: default priority and high priority. If the priority level bit is set, then that channel has higher priority than all other channels at default priority. If multiple channels are set for high priority, then the channel number is used to determine relative priority among all the high priority channels. The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET) register and cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register. 7.2.3 Arbitration Size When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels making a request and services the μDMA channel with the highest priority. Once a transfer begins, it continues for a selectable number of transfers before rearbitrating among the requesting channels again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers. After the μDMA controller transfers the number of items specified by the arbitration size, it then checks among all the channels making a request and services the channel with the highest priority. If a lower priority μDMA channel uses a large arbitration size, the latency for higher priority channels is increased because the μDMA controller completes the lower priority burst before checking for higher priority requests. Therefore, lower priority channels should not use a large arbitration size for best response on high priority channels. The arbitration size can also be thought of as a burst size. It is the maximum number of items that are transferred at any one time in a burst. Here, the term arbitration refers to determination of μDMA channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the processor always takes priority. Furthermore, the μDMA controller is held off whenever the processor must perform a bus transaction on the same bus, even in the middle of a burst transfer. 7.2.4 Request Types The μDMA controller responds to two types of requests from a peripheral: single or burst. Each peripheral may support either or both types of requests. A single request means that the peripheral 336 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple items. The μDMA controller responds differently depending on whether the peripheral is making a single request or a burst request. If both are asserted, and the μDMA channel has been set up for a burst transfer, then the burst request takes precedence. See Table 7-2 on page 337, which shows how each peripheral supports the two request types. Table 7-2. Request Type Support 7.2.4.1 Peripheral Single Request Signal Burst Request Signal ADC None Sequencer IE bit Ethernet TX TX FIFO empty None Ethernet RX RX packet received None General-Purpose Timer Raw interrupt pulse None I2S TX None FIFO service request I2S None FIFO service request SSI TX TX FIFO Not Full TX FIFO Level (fixed at 4) SSI RX RX FIFO Not Empty RX FIFO Level (fixed at 4) UART TX TX FIFO Not Full TX FIFO Level (configurable) UART RX RX FIFO Not Empty RX FIFO Level (configurable) USB TX None FIFO TXRDY USB RX None FIFO RXRDY RX Single Request When a single request is detected, and not a burst request, the μDMA controller transfers one item and then stops to wait for another request. 7.2.4.2 Burst Request When a burst request is detected, the μDMA controller transfers the number of items that is the lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration size should be the same as the number of data items that the peripheral can accommodate when making a burst request. For example, the UART generates a burst request based on the FIFO trigger level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer when the trigger level is reached. A burst transfer runs to completion once it is started, and cannot be interrupted, even by a higher priority channel. Burst transfers complete in a shorter time than the same number of non-burst transfers. It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps the nature of the data is such that it only makes sense when transferred together as a single unit rather than one piece at a time. The single request can be disabled by using the DMA Channel Useburst Set (DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the μDMA controller only responds to burst requests for that channel. 7.2.5 Channel Configuration The μDMA controller uses an area of system memory to store a set of channel control structures in a table. The control table may have one or two entries for each μDMA channel. Each entry in the table structure contains source and destination pointers, transfer size, and transfer mode. The control table can be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary. July 22, 2011 337 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Table 7-3 on page 338 shows the layout in memory of the channel control table. Each channel may have one or two control structures in the control table: a primary control structure and an optional alternate control structure. The table is organized so that all of the primary entries are in the first half of the table, and all the alternate structures are in the second half of the table. The primary entry is used for simple transfer modes where transfers can be reconfigured and restarted after each transfer is complete. In this case, the alternate control structures are not used and therefore only the first half of the table must be allocated in memory; the second half of the control table is not necessary, and that memory can be used for something else. If a more complex transfer mode is used such as ping-pong or scatter-gather, then the alternate control structure is also used and memory space should be allocated for the entire table. Any unused memory in the control table may be used by the application. This includes the control structures for any channels that are unused by the application as well as the unused control word for each channel. Table 7-3. Control Structure Memory Map Offset Channel 0x0 0, Primary 0x10 1, Primary ... ... 0x1F0 31, Primary 0x200 0, Alternate 0x210 1, Alternate ... 0x3F0 ... 31, Alternate Table 7-4 shows an individual control structure entry in the control table. Each entry is aligned on a 16-byte boundary. The entry contains four long words: the source end pointer, the destination end pointer, the control word, and an unused entry. The end pointers point to the ending address of the transfer and are inclusive. If the source or destination is non-incrementing (as for a peripheral register), then the pointer should point to the transfer address. Table 7-4. Channel Control Structure Offset Description 0x000 Source End Pointer 0x004 Destination End Pointer 0x008 Control Word 0x00C Unused The control word contains the following fields: ■ Source and destination data sizes ■ Source and destination address increment size ■ Number of transfers before bus arbitration ■ Total number of items to transfer ■ Useburst flag 338 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ Transfer mode The control word and each field are described in detail in “μDMA Channel Control Structure” on page 355. The μDMA controller updates the transfer size and transfer mode fields as the transfer is performed. At the end of a transfer, the transfer size indicates 0, and the transfer mode indicates "stopped." Because the control word is modified by the μDMA controller, it must be reconfigured before each new transfer. The source and destination end pointers are not modified, so they can be left unchanged if the source or destination addresses remain the same. Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the DMA Channel Enable Set (DMAENASET) register. A channel can be disabled by setting the channel bit in the DMA Channel Enable Clear (DMAENACLR) register. At the end of a complete μDMA transfer, the controller automatically disables the channel. 7.2.6 Transfer Modes The μDMA controller supports several transfer modes. Two of the modes support simple one-time transfers. Several complex modes support a continuous flow of data. 7.2.6.1 Stop Mode While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word. When the mode field has this value, the μDMA controller does not perform any transfers and disables the channel if it is enabled. At the end of a transfer, the μDMA controller updates the control word to set the mode to Stop. 7.2.6.2 Basic Mode In Basic mode, the μDMA controller performs transfers as long as there are more items to transfer, and a transfer request is present. This mode is used with peripherals that assert a μDMA request signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any situation where the request is momentary even though the entire transfer should be completed. For example, a software-initiated transfer creates a momentary request, and in Basic mode, only the number of transfers specified by the ARBSIZE field in the DMA Channel Control Word (DMACHCTL) register is transferred on a software request, even if there is more data to transfer. When all of the items have been transferred using Basic mode, the μDMA controller sets the mode for that channel to Stop. 7.2.6.3 Auto Mode Auto mode is similar to Basic mode, except that once a transfer request is received, the transfer runs to completion, even if the μDMA request is removed. This mode is suitable for software-triggered transfers. Generally, Auto mode is not used with a peripheral. When all the items have been transferred using Auto mode, the μDMA controller sets the mode for that channel to Stop. 7.2.6.4 Ping-Pong Ping-Pong mode is used to support a continuous data flow to or from a peripheral. To use Ping-Pong mode, both the primary and alternate data structures must be implemented. Both structures are set up by the processor for data transfer between memory and a peripheral. The transfer is started using the primary control structure. When the transfer using the primary control structure is complete, the μDMA controller reads the alternate control structure for that channel to continue the transfer. Each time this happens, an interrupt is generated, and the processor can reload the control structure for the just-completed transfer. Data flow can continue indefinitely this way, using the primary and July 22, 2011 339 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. Refer to Figure 7-2 on page 340 for an example showing operation in Ping-Pong mode. Figure 7-2. Example of Ping-Pong μDMA Transaction µDMA Controller SOURCE DEST CONTROL Unused transfers using BUFFER A transfer continues using alternate Primary Structure Cortex-M3 Processor SOURCE DEST CONTROL Unused Pe rip he ral /µD M AI nte Time transfers using BUFFER B SOURCE DEST CONTROL Unused Alternate Structure SOURCE DEST CONTROL Unused BUFFER B · Process data in BUFFER A · Reload primary structure Pe rip he ral /µD M AI nte r transfers using BUFFER A rup t BUFFER A · Process data in BUFFER B · Reload alternate structure transfer continues using alternate Primary Structure rru p t transfer continues using primary Alternate Structure BUFFER A Pe rip he ral /µD M AI nte transfers using BUFFER B rru pt BUFFER B · Process data in BUFFER B · Reload alternate structure 340 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 7.2.6.5 Memory Scatter-Gather Memory Scatter-Gather mode is a complex mode used when data must be transferred to or from varied locations in memory instead of a set of contiguous locations in a memory buffer. For example, a gather μDMA operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer. In Memory Scatter-Gather mode, the primary control structure is used to program the alternate control structure from a table in memory. The table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode. Each entry in the table is copied in turn to the alternate structure where it is then executed. The μDMA controller alternates between using the primary control structure to copy the next transfer instruction from the list and then executing the new transfer instruction. The end of the list is marked by programming the control word for the last entry to use Auto transfer mode. Once the last transfer is performed using Auto mode, the μDMA controller stops. A completion interrupt is generated only after the last transfer. It is possible to loop the list by having the last entry copy the primary control structure to point back to the beginning of the list (or to a new list). It is also possible to trigger a set of other channels to perform a transfer, either directly, by programming a write to the software trigger for another channel, or indirectly, by causing a peripheral action that results in a μDMA request. By programming the μDMA controller using this method, a set of arbitrary transfers can be performed based on a single μDMA request. Refer to Figure 7-3 on page 342 and Figure 7-4 on page 343, which show an example of operation in Memory Scatter-Gather mode. This example shows a gather operation, where data in three separate buffers in memory is copied together into one buffer. Figure 7-3 on page 342 shows how the application sets up a μDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. Figure 7-4 on page 343 shows the sequence as the μDMA controller performs the three sets of copy operations. First, using the primary control structure, the μDMA controller loads the alternate control structure with task A. It then performs the copy operation specified by task A, copying the data from the source buffer A to the destination buffer. Next, the μDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. July 22, 2011 341 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Figure 7-3. Memory Scatter-Gather, Setup and Configuration 1 2 3 Source and Destination Buffer in Memory Task List in Memory Channel Control Table in Memory 4 WORDS (SRC A) SRC A DST ITEMS=4 16 WORDS (SRC B) SRC Unused DST SRC ITEMS=12 DST B “TASK” A ITEMS=16 Channel Primary Control Structure “TASK” B Unused SRC DST ITEMS=1 “TASK” C Unused SRC DST Channel Alternate Control Structure ITEMS=n 1 WORD (SRC C) C 4 (DEST A) 16 (DEST B) 1 (DEST C) NOTES: 1. Application has a need to copy data items from three separate locations in memory into one combined buffer. 2. Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three µDMA copy “tasks.” 3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller. 342 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 7-4. Memory Scatter-Gather, μDMA Copy Sequence Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI COPIED DST TASK A TASK B SRC SRC C ALT COPIED DST TASK C DEST A DEST B DEST C Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer A to the destination buffer. Using the channel’s primary control structure, the µDMA controller copies task A configuration to the channel’s alternate control structure. Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC B SRC PRI DST TASK A SRC TASK B TASK C SRC C COPIED ALT COPIED DST DEST A DEST B DEST C Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer B to the destination buffer. Using the channel’s primary control structure, the µDMA controller copies task B configuration to the channel’s alternate control structure. Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI DST TASK A SRC TASK B TASK C SRC C ALT DST DEST A COPIED COPIED DEST B DEST C Using the channel’s primary control structure, the µDMA controller copies task C configuration to the channel’s alternate control structure. Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer C to the destination buffer. July 22, 2011 343 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 7.2.6.6 Peripheral Scatter-Gather Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers are controlled by a peripheral making a μDMA request. Upon detecting a request from the peripheral, the μDMA controller uses the primary control structure to copy one entry from the list to the alternate control structure and then performs the transfer. At the end of this transfer, the next transfer is started only if the peripheral again asserts a μDMA request. The μDMA controller continues to perform transfers from the list only when the peripheral is making a request, until the last transfer is complete. A completion interrupt is generated only after the last transfer. By using this method, the μDMA controller can transfer data to or from a peripheral from a set of arbitrary locations whenever the peripheral is ready to transfer data. Refer to Figure 7-5 on page 345 and Figure 7-6 on page 346, which show an example of operation in Peripheral Scatter-Gather mode. This example shows a gather operation, where data from three separate buffers in memory is copied to a single peripheral data register. Figure 7-5 on page 345 shows how the application sets up a µDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. Figure 7-6 on page 346 shows the sequence as the µDMA controller performs the three sets of copy operations. First, using the primary control structure, the µDMA controller loads the alternate control structure with task A. It then performs the copy operation specified by task A, copying the data from the source buffer A to the peripheral data register. Next, the µDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. 344 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 7-5. Peripheral Scatter-Gather, Setup and Configuration 1 2 3 Source Buffer in Memory Task List in Memory Channel Control Table in Memory 4 WORDS (SRC A) SRC A DST ITEMS=4 16 WORDS (SRC B) SRC DST SRC ITEMS=12 DST B “TASK” A Unused ITEMS=16 Channel Primary Control Structure “TASK” B Unused SRC DST ITEMS=1 “TASK” C Unused SRC DST Channel Alternate Control Structure ITEMS=n 1 WORD (SRC C) C Peripheral Data Register DEST NOTES: 1. Application has a need to copy data items from three separate locations in memory into a peripheral data register. 2. Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three µDMA copy “tasks.” 3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller. July 22, 2011 345 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Figure 7-6. Peripheral Scatter-Gather, μDMA Copy Sequence Task List in Memory Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI COPIED DST TASK A TASK B SRC SRC C ALT COPIED DST TASK C Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer A to the peripheral data register. Using the channel’s primary control structure, the µDMA controller copies task A configuration to the channel’s alternate control structure. Task List in Memory Peripheral Data Register Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI DST TASK A SRC TASK B TASK C SRC C COPIED ALT COPIED DST Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer B to the peripheral data register. Using the channel’s primary control structure, the µDMA controller copies task B configuration to the channel’s alternate control structure. Task List in Memory Peripheral Data Register Buffers in Memory µDMA Control Table in Memory SRC A SRC SRC B PRI DST TASK A SRC TASK B TASK C SRC C ALT DST COPIED COPIED Peripheral Data Register Using the channel’s primary control structure, the µDMA controller copies task C configuration to the channel’s alternate control structure. Then, using the channel’s alternate control structure, the µDMA controller copies data from the source buffer C to the peripheral data register. 346 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 7.2.7 Transfer Size and Increment The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size must be the same for any given transfer. The source and destination address can be auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and destination address increment values can be set independently, and it is not necessary for the address increment to match the data size as long as the increment is the same or larger than the data size. For example, it is possible to perform a transfer using 8-bit data size, but using an address increment of full words (4 bytes). The data to be transferred must be aligned in memory according to the data size (8, 16, or 32 bits). Table 7-5 shows the configuration to read from a peripheral that supplies 8-bit data. Table 7-5. μDMA Read Example: 8-Bit Peripheral 7.2.8 Field Configuration Source data size 8 bits Destination data size 8 bits Source address increment No increment Destination address increment Byte Source end pointer Peripheral read FIFO register Destination end pointer End of the data buffer in memory Peripheral Interface Each peripheral that supports μDMA has a single request and/or burst request signal that is asserted when the peripheral is ready to transfer data (see Table 7-2 on page 337). The request signal can be disabled or enabled using the DMA Channel Request Mask Set (DMAREQMASKSET) and DMA Channel Request Mask Clear (DMAREQMASKCLR) registers. The μDMA request signal is disabled, or masked, when the channel request mask bit is set. When the request is not masked, the μDMA channel is configured correctly and enabled, and the peripheral asserts the request signal, the μDMA controller begins the transfer. Note: When using μDMA to transfer data to and from a peripheral, the peripheral must disable all interrupts to the NVIC. When a μDMA transfer is complete, the μDMA controller generates an interrupt, see “Interrupts and Errors” on page 348 for more information. For more information on how a specific peripheral interacts with the μDMA controller, refer to the DMA Operation section in the chapter that discusses that peripheral. 7.2.9 Software Request One μDMA channel is dedicated to software-initiated transfers. This channel also has a dedicated interrupt to signal completion of a μDMA transfer. A transfer is initiated by software by first configuring and enabling the transfer, and then issuing a software request using the DMA Channel Software Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should be used. It is possible to initiate a transfer on any channel using the DMASWREQ register. If a request is initiated by software using a peripheral μDMA channel, then the completion interrupt occurs on the interrupt vector for the peripheral instead of the software interrupt vector. Any channel may be used for software requests as long as the corresponding peripheral is not using μDMA for data transfer. July 22, 2011 347 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 7.2.10 Interrupts and Errors When a μDMA transfer is complete, the μDMA controller generates a completion interrupt on the interrupt vector of the peripheral. Therefore, if μDMA is used to transfer data for a peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed to handle the μDMA transfer completion interrupt. If the transfer uses the software μDMA channel, then the completion interrupt occurs on the dedicated software μDMA interrupt vector (see Table 7-6 on page 348). When μDMA is enabled for a peripheral, the μDMA controller stops the normal transfer interrupts for a peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's interrupt registers). Thus, when a large amount of data is transferred using μDMA, instead of receiving multiple interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt when the transfer is complete. Unmasked peripheral error interrupts continue to be sent to the interrupt controller. If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data transfer, it disables the μDMA channel that caused the error and generates an interrupt on the μDMA error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be cleared by writing a 1 to the ERRCLR bit. Table 7-6 shows the dedicated interrupt assignments for the μDMA controller. Table 7-6. μDMA Interrupt Assignments Interrupt Assignment 46 μDMA Software Channel Transfer 47 μDMA Error 7.3 Initialization and Configuration 7.3.1 Module Initialization Before the μDMA controller can be used, it must be enabled in the System Control block and in the peripheral. The location of the channel control structure must also be programmed. The following steps should be performed one time during system initialization: 1. The μDMA peripheral must be enabled in the System Control block. To do this, set the UDMA bit of the System Control RCGC2 register (see page 281). 2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG) register. 3. Program the location of the channel control table by writing the base address of the table to the DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be aligned on a 1024-byte boundary. 7.3.2 Configuring a Memory-to-Memory Transfer μDMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used for software-initiated, memory-to-memory transfer if the associated peripheral is not being used. 348 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 7.3.2.1 Configure the Channel Attributes First, configure the channel attributes: 1. Program bit 30 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 30 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 30 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 30 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 7.3.2.2 Configure the Channel Control Structure Now the channel control structure must be configured. This example transfers 256 words from one memory buffer to another. Channel 30 is used for a software transfer, and the control structure for channel 30 is at offset 0x1E0 of the channel control table. The channel control structure for channel 30 is located at the offsets shown in Table 7-7. Table 7-7. Channel Control Structure Offsets for Channel 30 Offset Description Control Table Base + 0x1E0 Channel 30 Source End Pointer Control Table Base + 0x1E4 Channel 30 Destination End Pointer Control Table Base + 0x1E8 Channel 30 Control Word Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). 1. Program the source end pointer at offset 0x1E0 to the address of the source buffer + 0x3FC. 2. Program the destination end pointer at offset 0x1E4 to the address of the destination buffer + 0x3FC. The control word at offset 0x1E8 must be programmed according to Table 7-8. Table 7-8. Channel Control Word Configuration for Memory Transfer Example Field in DMACHCTL Bits Value DSTINC 31:30 2 32-bit destination address increment DSTSIZE 29:28 2 32-bit destination data size SRCINC 27:26 2 32-bit source address increment SRCSIZE 25:24 2 32-bit source data size reserved 23:18 0 Reserved ARBSIZE 17:14 3 Arbitrates after 8 transfers XFERSIZE 13:4 255 3 0 N/A for this transfer type 2:0 2 Use Auto-request transfer mode NXTUSEBURST XFERMODE July 22, 2011 Description Transfer 256 items 349 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 7.3.2.3 Start the Transfer Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 30 of the DMA Channel Enable Set (DMAENASET) register. 2. Issue a transfer request by setting bit 30 of the DMA Channel Software Request (DMASWREQ) register. The μDMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt when the transfer is complete. If needed, the status can be checked by reading bit 30 of the DMAENASET register. This bit is automatically cleared when the transfer is complete. The status can also be checked by reading the XFERMODE field of the channel control word at offset 0x1E8. This field is automatically cleared at the end of the transfer. 7.3.3 Configuring a Peripheral for Simple Transmit This example configures the μDMA controller to transmit a buffer of data to a peripheral. The peripheral has a transmit FIFO with a trigger level of 4. The example peripheral uses μDMA channel 7. 7.3.3.1 Configure the Channel Attributes First, configure the channel attributes: 1. Configure bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 7.3.3.2 Configure the Channel Control Structure This example transfers 64 bytes from a memory buffer to the peripheral's transmit FIFO register using μDMA channel 7. The control structure for channel 7 is at offset 0x070 of the channel control table. The channel control structure for channel 7 is located at the offsets shown in Table 7-9. Table 7-9. Channel Control Structure Offsets for Channel 7 Offset Description Control Table Base + 0x070 Channel 7 Source End Pointer Control Table Base + 0x074 Channel 7 Destination End Pointer Control Table Base + 0x078 Channel 7 Control Word Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). Because the peripheral pointer does not change, it simply points to the peripheral's data register. 1. Program the source end pointer at offset 0x070 to the address of the source buffer + 0x3F. 350 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 2. Program the destination end pointer at offset 0x074 to the address of the peripheral's transmit FIFO register. The control word at offset 0x078 must be programmed according to Table 7-10. Table 7-10. Channel Control Word Configuration for Peripheral Transmit Example Field in DMACHCTL Bits Value DSTINC 31:30 3 Destination address does not increment DSTSIZE 29:28 0 8-bit destination data size SRCINC 27:26 0 8-bit source address increment SRCSIZE 25:24 0 8-bit source data size reserved 23:18 0 Reserved ARBSIZE 17:14 2 Arbitrates after 4 transfers XFERSIZE 13:4 63 Transfer 64 items 3 0 N/A for this transfer type 2:0 1 Use Basic transfer mode NXTUSEBURST XFERMODE Note: 7.3.3.3 Description In this example, it is not important if the peripheral makes a single request or a burst request. Because the peripheral has a FIFO that triggers at a level of 4, the arbitration size is set to 4. If the peripheral does make a burst request, then 4 bytes are transferred, which is what the FIFO can accommodate. If the peripheral makes a single request (if there is any space in the FIFO), then one byte is transferred at a time. If it is important to the application that transfers only be made in bursts, then the Channel Useburst SET[7] bit should be set in the DMA Channel Useburst Set (DMAUSEBURSTSET) register. Start the Transfer Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 7 of the DMA Channel Enable Set (DMAENASET) register. The μDMA controller is now configured for transfer on channel 7. The controller makes transfers to the peripheral whenever the peripheral asserts a μDMA request. The transfers continue until the entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller disables the channel and sets the XFERMODE field of the channel control word to 0 (Stopped). The status of the transfer can be checked by reading bit 7 of the DMA Channel Enable Set (DMAENASET) register. This bit is automatically cleared when the transfer is complete. The status can also be checked by reading the XFERMODE field of the channel control word at offset 0x078. This field is automatically cleared at the end of the transfer. If peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when the entire transfer is complete. 7.3.4 Configuring a Peripheral for Ping-Pong Receive This example configures the μDMA controller to continuously receive 8-bit data from a peripheral into a pair of 64-byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example peripheral uses μDMA channel 8. 7.3.4.1 Configure the Channel Attributes First, configure the channel attributes: July 22, 2011 351 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) 1. Configure bit 8 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority. 2. Set bit 8 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary channel control structure for this transfer. 3. Set bit 8 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the μDMA controller to respond to single and burst requests. 4. Set bit 8 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the μDMA controller to recognize requests for this channel. 7.3.4.2 Configure the Channel Control Structure This example transfers bytes from the peripheral's receive FIFO register into two memory buffers of 64 bytes each. As data is received, when one buffer is full, the μDMA controller switches to use the other. To use Ping-Pong buffering, both primary and alternate channel control structures must be used. The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the alternate channel control structure is at offset 0x280. The channel control structures for channel 8 are located at the offsets shown in Table 7-11. Table 7-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 Offset Description Control Table Base + 0x080 Channel 8 Primary Source End Pointer Control Table Base + 0x084 Channel 8 Primary Destination End Pointer Control Table Base + 0x088 Channel 8 Primary Control Word Control Table Base + 0x280 Channel 8 Alternate Source End Pointer Control Table Base + 0x284 Channel 8 Alternate Destination End Pointer Control Table Base + 0x288 Channel 8 Alternate Control Word Configure the Source and Destination The source and destination end pointers must be set to the last address for the transfer (inclusive). Because the peripheral pointer does not change, it simply points to the peripheral's data register. Both the primary and alternate sets of pointers must be configured. 1. Program the primary source end pointer at offset 0x080 to the address of the peripheral's receive buffer. 2. Program the primary destination end pointer at offset 0x084 to the address of ping-pong buffer A + 0x3F. 3. Program the alternate source end pointer at offset 0x280 to the address of the peripheral's receive buffer. 4. Program the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer B + 0x3F. The primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially programmed the same way. 1. Program the primary channel control word at offset 0x088 according to Table 7-12. 352 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 2. Program the alternate channel control word at offset 0x288 according to Table 7-12. Table 7-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example Field in DMACHCTL Bits Value DSTINC 31:30 0 8-bit destination address increment DSTSIZE 29:28 0 8-bit destination data size SRCINC 27:26 3 Source address does not increment SRCSIZE 25:24 0 8-bit source data size reserved 23:18 0 Reserved ARBSIZE 17:14 3 Arbitrates after 8 transfers XFERSIZE 13:4 63 Transfer 64 items 3 0 N/A for this transfer type 2:0 3 Use Ping-Pong transfer mode NXTUSEBURST XFERMODE Note: 7.3.4.3 Description In this example, it is not important if the peripheral makes a single request or a burst request. Because the peripheral has a FIFO that triggers at a level of 8, the arbitration size is set to 8. If the peripheral does make a burst request, then 8 bytes are transferred, which is what the FIFO can accommodate. If the peripheral makes a single request (if there is any data in the FIFO), then one byte is transferred at a time. If it is important to the application that transfers only be made in bursts, then the Channel Useburst SET[8] bit should be set in the DMA Channel Useburst Set (DMAUSEBURSTSET) register. Configure the Peripheral Interrupt An interrupt handler should be configured when using μDMA Ping-Pong mode, it is best to use an interrupt handler. However, the Ping-Pong mode can be configured without interrupts by polling. The interrupt handler is triggered after each buffer is complete. 1. Configure and enable an interrupt handler for the peripheral. 7.3.4.4 Enable the μDMA Channel Now the channel is configured and is ready to start. 1. Enable the channel by setting bit 8 of the DMA Channel Enable Set (DMAENASET) register. 7.3.4.5 Process Interrupts The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral asserts the μDMA request signal, the μDMA controller makes transfers into buffer A using the primary channel control structure. When the primary transfer to buffer A is complete, it switches to the alternate channel control structure and makes transfers into buffer B. At the same time, the primary channel control word mode field is configured to indicate Stopped, and an interrupt is When an interrupt is triggered, the interrupt handler must determine which buffer is complete and process the data or set a flag that the data must be processed by non-interrupt buffer processing code. Then the next buffer transfer must be set up. In the interrupt handler: 1. Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the field is 0, this means buffer A is complete. If buffer A is complete, then: July 22, 2011 353 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) a. Process the newly received data in buffer A or signal the buffer processing code that buffer A has data available. b. Reprogram the primary channel control word at offset 0x88 according to Table 7-12 on page 353. 2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the field is 0, this means buffer B is complete. If buffer B is complete, then: a. Process the newly received data in buffer B or signal the buffer processing code that buffer B has data available. b. Reprogram the alternate channel control word at offset 0x288 according to Table 7-12 on page 353. 7.3.5 Configuring Channel Assignments Channel assignments for each μDMA channel can be changed using the DMACHASGN register. Each bit represents a μDMA channel. If the bit is set, then the secondary function is used for the channel. Refer to Table 7-1 on page 335 for channel assignments. For example, to use SSI1 Receive on channel 8 instead of UART0, set bit 8 of the DMACHASGN register. 7.4 Register Map Table 7-13 on page 354 lists the μDMA channel control structures and registers. The channel control structure shows the layout of one entry in the channel control table. The channel control table is located in system memory, and the location is determined by the application, that is, the base address is n/a (not applicable). In the table below, the offset for the channel control structures is the offset from the entry in the channel control table. See “Channel Configuration” on page 337 and Table 7-3 on page 338 for a description of how the entries in the channel control table are located in memory. The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers can be programmed (see page 281). There must be a delay of 3 system clocks after the μDMA module clock is enabled before any μDMA module registers are accessed. Table 7-13. μDMA Register Map Offset Name Type Reset Description See page μDMA Channel Control Structure (Offset from Channel Control Table Base) 0x000 DMASRCENDP R/W - DMA Channel Source Address End Pointer 356 0x004 DMADSTENDP R/W - DMA Channel Destination Address End Pointer 357 0x008 DMACHCTL R/W - DMA Channel Control Word 358 DMA Status 363 DMA Configuration 365 DMA Channel Control Base Pointer 366 μDMA Registers (Offset from μDMA Base Address) 0x000 DMASTAT RO 0x001F.0000 0x004 DMACFG WO - 0x008 DMACTLBASE R/W 0x0000.0000 354 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 7-13. μDMA Register Map (continued) Offset Name 0x00C Reset DMAALTBASE RO 0x0000.0200 DMA Alternate Channel Control Base Pointer 367 0x010 DMAWAITSTAT RO 0xFFFF.FFC0 DMA Channel Wait-on-Request Status 368 0x014 DMASWREQ WO - DMA Channel Software Request 369 0x018 DMAUSEBURSTSET R/W 0x0000.0000 DMA Channel Useburst Set 370 0x01C DMAUSEBURSTCLR WO - DMA Channel Useburst Clear 371 0x020 DMAREQMASKSET R/W 0x0000.0000 DMA Channel Request Mask Set 372 0x024 DMAREQMASKCLR WO - DMA Channel Request Mask Clear 373 0x028 DMAENASET R/W 0x0000.0000 DMA Channel Enable Set 374 0x02C DMAENACLR WO - DMA Channel Enable Clear 375 0x030 DMAALTSET R/W 0x0000.0000 DMA Channel Primary Alternate Set 376 0x034 DMAALTCLR WO - DMA Channel Primary Alternate Clear 377 0x038 DMAPRIOSET R/W 0x0000.0000 DMA Channel Priority Set 378 0x03C DMAPRIOCLR WO - DMA Channel Priority Clear 379 0x04C DMAERRCLR R/W 0x0000.0000 DMA Bus Error Clear 380 0x500 DMACHASGN R/W 0x0000.0000 DMA Channel Assignment 381 0xFD0 DMAPeriphID4 RO 0x0000.0004 DMA Peripheral Identification 4 386 0xFE0 DMAPeriphID0 RO 0x0000.0030 DMA Peripheral Identification 0 382 0xFE4 DMAPeriphID1 RO 0x0000.00B2 DMA Peripheral Identification 1 383 0xFE8 DMAPeriphID2 RO 0x0000.000B DMA Peripheral Identification 2 384 0xFEC DMAPeriphID3 RO 0x0000.0000 DMA Peripheral Identification 3 385 0xFF0 DMAPCellID0 RO 0x0000.000D DMA PrimeCell Identification 0 387 0xFF4 DMAPCellID1 RO 0x0000.00F0 DMA PrimeCell Identification 1 388 0xFF8 DMAPCellID2 RO 0x0000.0005 DMA PrimeCell Identification 2 389 0xFFC DMAPCellID3 RO 0x0000.00B1 DMA PrimeCell Identification 3 390 7.5 Description See page Type μDMA Channel Control Structure The μDMA Channel Control Structure holds the transfer settings for a μDMA channel. Each channel has two control structures, which are located in a table in system memory. Refer to “Channel Configuration” on page 337 for an explanation of the Channel Control Table and the Channel Control Structure. The channel control structure is one entry in the channel control table. Each channel has a primary and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. July 22, 2011 355 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 DMA Channel Source Address End Pointer (DMASRCENDP) is part of the Channel Control Structure and is used to specify the source address for a μDMA transfer. The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address. DMA Channel Source Address End Pointer (DMASRCENDP) Base n/a Offset 0x000 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 ADDR Type Reset R/W - R/W - R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:0 ADDR R/W - R/W - Description Source Address End Pointer This field points to the last address of the μDMA transfer source (inclusive). If the source address is not incrementing (the SRCINC field in the DMACHCTL register is 0x3), then this field points at the source location itself (such as a peripheral data register). 356 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 DMA Channel Destination Address End Pointer (DMADSTENDP) is part of the Channel Control Structure and is used to specify the destination address for a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address. DMA Channel Destination Address End Pointer (DMADSTENDP) Base n/a Offset 0x004 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - ADDR Type Reset ADDR Type Reset Bit/Field Name Type Reset 31:0 ADDR R/W - Description Destination Address End Pointer This field points to the last address of the μDMA transfer destination (inclusive). If the destination address is not incrementing (the DSTINC field in the DMACHCTL register is 0x3), then this field points at the destination location itself (such as a peripheral data register). July 22, 2011 357 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used to specify parameters of a μDMA transfer. Note: The offset specified is from the base address of the control structure in system memory, not the μDMA module base address. DMA Channel Control Word (DMACHCTL) Base n/a Offset 0x008 Type R/W, reset 31 30 DSTINC Type Reset 29 28 27 DSTSIZE 26 24 23 22 21 SRCSIZE 20 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 7 6 5 4 R/W - XFERSIZE R/W - R/W - R/W - R/W - R/W - Bit/Field Name Type Reset 31:30 DSTINC R/W - 18 17 R/W - R/W - 3 2 R/W - R/W - R/W - R/W - R/W - R/W - R/W - 1 0 XFERMODE NXTUSEBURST R/W - 16 ARBSIZE R/W - R/W - 19 reserved R/W - ARBSIZE Type Reset 25 SRCINC R/W - R/W - R/W - Description Destination Address Increment This field configures the destination address increment. The address increment value must be equal or greater than the value of the destination size (DSTSIZE). Value Description 0x0 Byte Increment by 8-bit locations 0x1 Half-word Increment by 16-bit locations 0x2 Word Increment by 32-bit locations 0x3 No increment Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel 29:28 DSTSIZE R/W - Destination Data Size This field configures the destination item data size. Note: DSTSIZE must be the same as SRCSIZE. Value Description 0x0 Byte 8-bit data size 0x1 Half-word 16-bit data size 0x2 Word 32-bit data size 0x3 Reserved 358 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 27:26 SRCINC R/W - Description Source Address Increment This field configures the source address increment. The address increment value must be equal or greater than the value of the source size (SRCSIZE). Value Description 0x0 Byte Increment by 8-bit locations 0x1 Half-word Increment by 16-bit locations 0x2 Word Increment by 32-bit locations 0x3 No increment Address remains set to the value of the Source Address End Pointer (DMASRCENDP) for the channel 25:24 SRCSIZE R/W - Source Data Size This field configures the source item data size. Note: DSTSIZE must be the same as SRCSIZE. Value Description 0x0 Byte 8-bit data size. 0x1 Half-word 16-bit data size. 0x2 Word 32-bit data size. 0x3 23:18 reserved R/W - Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 359 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset 17:14 ARBSIZE R/W - Description Arbitration Size This field configures the number of transfers that can occur before the μDMA controller re-arbitrates. The possible arbitration rate configurations represent powers of 2 and are shown below. Value Description 0x0 1 Transfer Arbitrates after each μDMA transfer 0x1 2 Transfers 0x2 4 Transfers 0x3 8 Transfers 0x4 16 Transfers 0x5 32 Transfers 0x6 64 Transfers 0x7 128 Transfers 0x8 256 Transfers 0x9 512 Transfers 0xA-0xF 1024 Transfers In this configuration, no arbitration occurs during the μDMA transfer because the maximum transfer size is 1024. 13:4 XFERSIZE R/W - Transfer Size (minus 1) This field configures the total number of items to transfer. The value of this field is 1 less than the number to transfer (value 0 means transfer 1 item). The maximum value for this 10-bit field is 1023 which represents a transfer size of 1024 items. The transfer size is the number of items, not the number of bytes. If the data size is 32 bits, then this value is the number of 32-bit words to transfer. The μDMA controller updates this field immediately prior to entering the arbitration process, so it contains the number of outstanding items that is necessary to complete the μDMA cycle. 3 NXTUSEBURST R/W - Next Useburst This field controls whether the Useburst SET[n] bit is automatically set for the last transfer of a peripheral scatter-gather operation. Normally, for the last transfer, if the number of remaining items to transfer is less than the arbitration size, the μDMA controller uses single transfers to complete the transaction. If this bit is set, then the controller uses a burst transfer to complete the last transfer. 360 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 2:0 XFERMODE R/W - Description μDMA Transfer Mode This field configures the operating mode of the μDMA cycle. Refer to “Transfer Modes” on page 339 for a detailed explanation of transfer modes. Because this register is in system RAM, it has no reset value. Therefore, this field should be initialized to 0 before the channel is enabled. Value Description 0x0 Stop 0x1 Basic 0x2 Auto-Request 0x3 Ping-Pong 0x4 Memory Scatter-Gather 0x5 Alternate Memory Scatter-Gather 0x6 Peripheral Scatter-Gather 0x7 Alternate Peripheral Scatter-Gather XFERMODE Bit Field Values. Stop Channel is stopped or configuration data is invalid. No more transfers can occur. Basic For each trigger (whether from a peripheral or a software request), the μDMA controller performs the number of transfers specified by the ARBSIZE field. Auto-Request The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer of XFERSIZE items without any further requests. Ping-Pong This mode uses both the primary and alternate control structures for this channel. When the number of transfers specified by the XFERSIZE field have completed for the current control structure (primary or alternate), the µDMA controller switches to the other one. These switches continue until one of the control structures is not set to ping-pong mode. At that point, the µDMA controller stops. An interrupt is generated on completion of the transfers configured by each control structure. See “Ping-Pong” on page 339. Memory Scatter-Gather When using this mode, the primary control structure for the channel is configured to allow a list of operations (tasks) to be performed. The source address pointer specifies the start of a table of tasks to be copied to the alternate control structure for this channel. The XFERMODE field for the alternate control structure should be configured to 0x5 (Alternate memory scatter-gather) to perform the task. When the task completes, the µDMA switches back to the primary channel control structure, which then copies the next task to the alternate control structure. This process continues until the table of tasks is empty. The last task must have an XFERMODE value other than 0x5. Note that for continuous operation, the last task can update the primary channel control structure back to the start of the list or to another list. See “Memory Scatter-Gather” on page 341. July 22, 2011 361 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Alternate Memory Scatter-Gather This value must be used in the alternate channel control data structure when the μDMA controller operates in Memory Scatter-Gather mode. Peripheral Scatter-Gather This value must be used in the primary channel control data structure when the μDMA controller operates in Peripheral Scatter-Gather mode. In this mode, the μDMA controller operates exactly the same as in Memory Scatter-Gather mode, except that instead of performing the number of transfers specified by the XFERSIZE field in the alternate control structure at one time, the μDMA controller only performs the number of transfers specified by the ARBSIZE field per trigger; see Basic mode for details. See “Peripheral Scatter-Gather” on page 344. Alternate Peripheral Scatter-Gather This value must be used in the alternate channel control data structure when the μDMA controller operates in Peripheral Scatter-Gather mode. 7.6 μDMA Register Descriptions The register addresses given are relative to the μDMA base address of 0x400F.F000. 362 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: DMA Status (DMASTAT), offset 0x000 The DMA Status (DMASTAT) register returns the status of the μDMA controller. You cannot read this register when the μDMA controller is in the reset state. DMA Status (DMASTAT) Base 0x400F.F000 Offset 0x000 Type RO, reset 0x001F.0000 31 30 29 28 27 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 26 25 24 23 22 21 20 19 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 10 9 8 7 6 5 4 3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset STATE RO 0 17 16 RO 1 RO 1 RO 1 2 1 0 DMACHANS reserved Type Reset 18 reserved RO 0 MASTEN RO 0 RO 0 Bit/Field Name Type Reset Description 31:21 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20:16 DMACHANS RO 0x1F Available μDMA Channels Minus 1 This field contains a value equal to the number of μDMA channels the μDMA controller is configured to use, minus one. The value of 0x1F corresponds to 32 μDMA channels. 15:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 STATE RO 0x0 Control State Machine Status This field shows the current status of the control state machine. Status can be one of the following. Value Description 0x0 Idle 0x1 Reading channel controller data. 0x2 Reading source end pointer. 0x3 Reading destination end pointer. 0x4 Reading source data. 0x5 Writing destination data. 0x6 Waiting for µDMA request to clear. 0x7 Writing channel controller data. 0x8 Stalled 0x9 Done 0xA-0xF Undefined 3:1 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 363 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Bit/Field Name Type Reset 0 MASTEN RO 0 Description Master Enable Status Value Description 0 The μDMA controller is disabled. 1 The μDMA controller is enabled. 364 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 5: DMA Configuration (DMACFG), offset 0x004 The DMACFG register controls the configuration of the μDMA controller. DMA Configuration (DMACFG) Base 0x400F.F000 Offset 0x004 Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - reserved Type Reset reserved Type Reset WO - MASTEN WO - Bit/Field Name Type Reset Description 31:1 reserved WO - Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 MASTEN WO - Controller Master Enable Value Description 0 Disables the μDMA controller. 1 Enables μDMA controller. July 22, 2011 365 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 The DMACTLBASE register must be configured so that the base pointer points to a location in system memory. The amount of system memory that must be assigned to the μDMA controller depends on the number of μDMA channels used and whether the alternate channel control data structure is used. See “Channel Configuration” on page 337 for details about the Channel Control Table. The base address must be aligned on a 1024-byte boundary. This register cannot be read when the μDMA controller is in the reset state. DMA Channel Control Base Pointer (DMACTLBASE) Base 0x400F.F000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR Type Reset R/W 0 R/W 0 R/W 0 15 14 13 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 ADDR Type Reset R/W 0 R/W 0 R/W 0 reserved R/W 0 R/W 0 R/W 0 RO 0 Bit/Field Name Type Reset 31:10 ADDR R/W 0x0000.00 RO 0 RO 0 RO 0 RO 0 Description Channel Control Base Address This field contains the pointer to the base address of the channel control table. The base address must be 1024-byte aligned. 9:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 366 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C The DMAALTBASE register returns the base address of the alternate channel control data. This register removes the necessity for application software to calculate the base address of the alternate channel control structures. This register cannot be read when the μDMA controller is in the reset state. DMA Alternate Channel Control Base Pointer (DMAALTBASE) Base 0x400F.F000 Offset 0x00C Type RO, reset 0x0000.0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 ADDR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 ADDR Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type 31:0 ADDR RO RO 1 Reset RO 0 Description 0x0000.0200 Alternate Channel Address Pointer This field provides the base address of the alternate channel control structures. July 22, 2011 367 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can hold off the μDMA from performing a single request until the peripheral is ready for a burst request to enhance the μDMA performance. The use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. This register cannot be read when the μDMA controller is in the reset state. DMA Channel Wait-on-Request Status (DMAWAITSTAT) Base 0x400F.F000 Offset 0x010 Type RO, reset 0xFFFF.FFC0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WAITREQ[n] Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 8 7 6 5 4 3 2 1 0 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WAITREQ[n] Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field Name Type 31:0 WAITREQ[n] RO RO 1 Reset RO 1 RO 1 Description 0xFFFF.FFC0 Channel [n] Wait Status These bits provide the channel wait-on-request status. Bit 0 corresponds to channel 0. Value Description 1 The corresponding channel is waiting on a request. 0 The corresponding channel is not waiting on a request. 368 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 Each bit of the DMASWREQ register represents the corresponding μDMA channel. Setting a bit generates a request for the specified μDMA channel. DMA Channel Software Request (DMASWREQ) Base 0x400F.F000 Offset 0x014 Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - SWREQ[n] Type Reset SWREQ[n] Type Reset Bit/Field Name Type Reset 31:0 SWREQ[n] WO - WO - Description Channel [n] Software Request These bits generate software requests. Bit 0 corresponds to channel 0. Value Description 1 Generate a software request for the corresponding channel. 0 No request generated. These bits are automatically cleared when the software request has been completed. July 22, 2011 369 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 Each bit of the DMAUSEBURSTSET register represents the corresponding μDMA channel. Setting a bit disables the channel's single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST. If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET[n] bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than the arbitration (burst) size, the μDMA controller automatically clears the corresponding SET[n] bit, allowing the remaining items to transfer using single requests. In order to resume transfers using burst requests, the corresponding bit must be set again. A bit should not be set if the corresponding peripheral does not support the burst request model. Refer to “Request Types” on page 336 for more details about request types. DMA Channel Useburst Set (DMAUSEBURSTSET) Base 0x400F.F000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset SET[n] Type Reset Bit/Field Name Type 31:0 SET[n] R/W Reset Description 0x0000.0000 Channel [n] Useburst Set Value Description 0 μDMA channel [n] responds to single or burst requests. 1 μDMA channel [n] responds only to burst requests. Bit 0 corresponds to channel 0. This bit is automatically cleared as described above. A bit can also be manually cleared by setting the corresponding CLR[n] bit in the DMAUSEBURSTCLR register. 370 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C Each bit of the DMAUSEBURSTCLR register represents the corresponding μDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register. DMA Channel Useburst Clear (DMAUSEBURSTCLR) Base 0x400F.F000 Offset 0x01C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset CLR[n] Type Reset Bit/Field Name Type Reset 31:0 CLR[n] WO - Description Channel [n] Useburst Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register meaning that µDMA channel [n] responds to single and burst requests. July 22, 2011 371 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 Each bit of the DMAREQMASKSET register represents the corresponding μDMA channel. Setting a bit disables μDMA requests for the channel. Reading the register returns the request mask status. When a μDMA channel's request is masked, that means the peripheral can no longer request μDMA transfers. The channel can then be used for software-initiated transfers. DMA Channel Request Mask Set (DMAREQMASKSET) Base 0x400F.F000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SET[n] Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 SET[n] R/W R/W 0 Reset R/W 0 Description 0x0000.0000 Channel [n] Request Mask Set Value Description 0 The peripheral associated with channel [n] is enabled to request μDMA transfers. 1 The peripheral associated with channel [n] is not able to request μDMA transfers. Channel [n] may be used for software-initiated transfers. Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAREQMASKCLR register. 372 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 Each bit of the DMAREQMASKCLR register represents the corresponding μDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register. DMA Channel Request Mask Clear (DMAREQMASKCLR) Base 0x400F.F000 Offset 0x024 Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - Bit/Field Name Type Reset 31:0 CLR[n] WO - WO - Description Channel [n] Request Mask Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register meaning that the peripheral associated with channel [n] is enabled to request μDMA transfers. July 22, 2011 373 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit enables the corresponding µDMA channel. Reading the register returns the enable status of the channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be used for software-initiated transfers. DMA Channel Enable Set (DMAENASET) Base 0x400F.F000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset SET[n] Type Reset Bit/Field Name Type 31:0 SET[n] R/W Reset Description 0x0000.0000 Channel [n] Enable Set Value Description 0 µDMA Channel [n] is disabled. 1 µDMA Channel [n] is enabled. Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAENACLR register. 374 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAENASET register. DMA Channel Enable Clear (DMAENACLR) Base 0x400F.F000 Offset 0x02C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset CLR[n] Type Reset Bit/Field Name Type Reset 31:0 CLR[n] WO - Description Clear Channel [n] Enable Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAENASET register meaning that channel [n] is disabled for μDMA transfers. Note: The controller disables a channel when it completes the μDMA cycle. July 22, 2011 375 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 Each bit of the DMAALTSET register represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding µDMA channel. DMA Channel Primary Alternate Set (DMAALTSET) Base 0x400F.F000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset SET[n] Type Reset Bit/Field Name Type 31:0 SET[n] R/W Reset Description 0x0000.0000 Channel [n] Alternate Set Value Description 0 µDMA channel [n] is using the primary control structure. 1 µDMA channel [n] is using the alternate control structure. Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAALTCLR register. Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these bits to select the alternate channel control data structure. 376 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 Each bit of the DMAALTCLR register represents the corresponding μDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register. DMA Channel Primary Alternate Clear (DMAALTCLR) Base 0x400F.F000 Offset 0x034 Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 CLR[n] Type Reset WO - WO - WO - WO - WO - WO - WO - Bit/Field Name Type Reset 31:0 CLR[n] WO - WO - Description Channel [n] Alternate Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register meaning that channel [n] is using the primary control structure. Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these bits to select the alternate channel control data structure. July 22, 2011 377 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 Each bit of the DMAPRIOSET register represents the corresponding µDMA channel. Setting a bit configures the µDMA channel to have a high priority level. Reading the register returns the status of the channel priority mask. DMA Channel Priority Set (DMAPRIOSET) Base 0x400F.F000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SET[n] Type Reset SET[n] Type Reset Bit/Field Name Type 31:0 SET[n] R/W Reset Description 0x0000.0000 Channel [n] Priority Set Value Description 0 µDMA channel [n] is using the default priority level. 1 µDMA channel [n] is using a high priority level. Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAPRIOCLR register. 378 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C Each bit of the DMAPRIOCLR register represents the corresponding µDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register. DMA Channel Priority Clear (DMAPRIOCLR) Base 0x400F.F000 Offset 0x03C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - WO - CLR[n] Type Reset CLR[n] Type Reset Bit/Field Name Type Reset 31:0 CLR[n] WO - Description Channel [n] Priority Clear Value Description 0 No effect. 1 Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register meaning that channel [n] is using the default priority level. July 22, 2011 379 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C The DMAERRCLR register is used to read and clear the µDMA bus error status. The error status is set if the μDMA controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that channel is automatically disabled by the μDMA controller. The other channels are unaffected. DMA Bus Error Clear (DMAERRCLR) Base 0x400F.F000 Offset 0x04C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 ERRCLR R/W1C 0 RO 0 ERRCLR R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Bus Error Status Value Description 0 No bus error is pending. 1 A bus error is pending. This bit is cleared by writing a 1 to it. 380 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 Each bit of the DMACHASGN register represents the corresponding µDMA channel. Setting a bit selects the secondary channel assignment as specified in Table 7-1 on page 335. DMA Channel Assignment (DMACHASGN) Base 0x400F.F000 Offset 0x500 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 15 14 13 12 11 10 9 8 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 23 22 21 20 19 18 17 16 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - 7 6 5 4 3 2 1 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - CHASGN[n] Type Reset CHASGN[n] Type Reset Bit/Field Name Type Reset 31:0 CHASGN[n] R/W - R/W - Description Channel [n] Assignment Select Value Description 0 Use the primary channel assignment. 1 Use the secondary channel assignment. July 22, 2011 381 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 22: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 0 (DMAPeriphID0) Base 0x400F.F000 Offset 0xFE0 Type RO, reset 0x0000.0030 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x30 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 382 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 23: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 1 (DMAPeriphID1) Base 0x400F.F000 Offset 0xFE4 Type RO, reset 0x0000.00B2 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0xB2 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 22, 2011 383 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 24: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 2 (DMAPeriphID2) Base 0x400F.F000 Offset 0xFE8 Type RO, reset 0x0000.000B 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x0B Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 384 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 25: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. DMA Peripheral Identification 3 (DMAPeriphID3) Base 0x400F.F000 Offset 0xFEC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 22, 2011 385 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 26: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA Peripheral Identification 4 (DMAPeriphID4) Base 0x400F.F000 Offset 0xFD0 Type RO, reset 0x0000.0004 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x04 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA Peripheral ID Register Can be used by software to identify the presence of this peripheral. 386 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 27: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 0 (DMAPCellID0) Base 0x400F.F000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. July 22, 2011 387 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 28: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 1 (DMAPCellID1) Base 0x400F.F000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. μDMA PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. 388 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 29: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 2 (DMAPCellID2) Base 0x400F.F000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID2 RO 0x05 μDMA PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. July 22, 2011 389 Texas Instruments-Production Data Micro Direct Memory Access (μDMA) Register 30: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset values. DMA PrimeCell Identification 3 (DMAPCellID3) Base 0x400F.F000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CID3 RO 0xB1 μDMA PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. 390 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of nine physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H, Port J). The GPIO module supports up to 72 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ Up to 72 GPIOs, depending on configuration ■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions ■ 5-V-tolerant in input configuration ■ Fast toggle capable of a change every two clock cycles ■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility with existing code ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can be used to initiate an ADC sample sequence ■ Pins configured as digital inputs are Schmitt-triggered ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 8.1 Signal Description GPIO signals have alternate hardware functions. The following table lists the GPIO pins and their analog and digital alternate functions. The AINx and VREFA analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to their circuitry (C0-, C0+, C1-, C1+, USB0VBUS, July 22, 2011 391 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) USB0ID). These signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. All GPIO signals are 5-V tolerant when configured as inputs except for PB0 and PB1, which are limited to 3.6 V. The digital alternate hardware functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric encoding shown in the table below. Note that each pin must be programmed individually; no type of grouping is implied by the columns in the table. Table entries that are shaded gray are the default values for the corresponding GPIO pin. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 8-1. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 GPIOPCTL 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 Table 8-2. GPIO Pins and Alternate Functions (100LQFP) IO Pin Analog Function a Digital Function (GPIOPCTL PMCx Bit Field Encoding) 1 2 3 4 5 6 7 8 9 10 11 PA0 26 - U0Rx - - - - - - I2C1SCL U1Rx - - PA1 27 - U0Tx - - - - - - I2C1SDA U1Tx - - PA2 28 - SSI0Clk - TXD2 PWM4 - - - - I2S0RXSD - - PA3 29 - SSI0Fss - TXD1 PWM5 - - - - I2S0RXMCLK - - PA4 30 - SSI0Rx - TXD0 - CAN0Rx - - - I2S0TXSCK - - PA5 31 - SSI0Tx - RXDV - CAN0Tx - - - I2S0TXWS - - PA6 34 - I2C1SCL CCP1 RXCK PWM0 PWM4 CAN0Rx - USB0EPEN U1CTS - - USB0PFLT U1DCD PA7 35 - I2C1SDA CCP4 RXER PWM1 PWM5 CAN0Tx CCP3 - - PB0 66 USB0ID CCP0 PWM2 - - U1Rx - - - - - - PB1 67 USB0VBUS CCP2 PWM3 - CCP1 U1Tx - - - - - - IDX0 PB2 72 - I2C0SCL PB3 65 - I2C0SDA Fault0 - CCP3 CCP0 - - USB0EPEN - - - - Fault3 - - - USB0PFLT - - - PB4 92 AIN10 C0- - - - U2Rx CAN0Rx IDX0 U1Rx - - - - PB5 91 AIN11 C1- C0o CCP5 CCP6 CCP0 CAN0Tx CCP2 U1Tx - - - - PB6 90 VREFA C0+ CCP1 CCP7 C0o Fault1 IDX0 CCP5 - - I2S0TXSCK - - PB7 89 - - - - NMI - - RXD1 - - - - PC0 80 - - - TCK SWCLK - - - - - - - - 392 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 8-2. GPIO Pins and Alternate Functions (100LQFP) (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PC1 79 - - - TMS SWDIO - - - - - - - - PC2 78 - - - TDI - - - - - - - - PC3 77 - - - TDO SWO - - - - - - - - PC4 25 - CCP5 PhA0 TXD3 - CCP2 CCP4 - - CCP1 - - PC5 24 C1+ CCP1 C1o C0o Fault2 CCP3 USB0EPEN - - - - - PC6 23 - CCP3 PhB0 - - U1Rx CCP0 USB0PFLT - - - - PC7 22 - CCP4 PhB0 - CCP0 U1Tx USB0PFLT C1o - - - - PD0 10 AIN15 PWM0 CAN0Rx IDX0 U2Rx U1Rx CCP6 RXDV I2S0RXSCK U1CTS - - PD1 11 AIN14 PWM1 CAN0Tx PhA0 U2Tx U1Tx CCP7 TXER I2S0RXWS U1DCD CCP2 PhB1 PD2 12 AIN13 U1Rx CCP6 PWM2 CCP5 - - - - - - PD3 13 AIN12 U1Tx CCP7 PWM3 CCP0 - - - - - - - PD4 97 AIN7 CCP0 CCP3 - TXD3 - - - I2S0RXSD U1RI - - - PD5 98 AIN6 CCP2 CCP4 - TXD2 - - - I2S0RXMCLK U2Rx - - PD6 99 AIN5 Fault0 - - TXD1 - - - I2S0TXSCK U2Tx - - PD7 100 AIN4 IDX0 C0o CCP1 TXD0 - - - I2S0TXWS U1DTR - - PE0 74 - PWM4 SSI1Clk CCP3 - - - - - USB0PFLT - - PE1 75 - PWM5 SSI1Fss Fault0 CCP2 CCP6 - - - - - - PE2 95 AIN9 CCP4 SSI1Rx PhB1 PhA0 CCP2 - - - - - - PE3 96 AIN8 CCP1 SSI1Tx PhA1 PhB0 CCP7 - - - - - - PE4 6 AIN3 CCP3 - - Fault0 U2Tx CCP2 RXD0 - I2S0TXWS - - PE5 5 AIN2 CCP5 - - - - - - - I2S0TXSD - - PE6 2 AIN1 PWM4 C1o - - - - - - U1CTS - - - PE7 1 AIN0 PWM5 - - - - - - U1DCD - - PF0 47 - CAN1Rx PhB0 PWM0 RXCK - - - I2S0TXSD U1DSR - - PF1 61 - CAN1Tx IDX1 PWM1 RXER - - - I2S0TXMCLK U1RTS CCP3 - PF2 60 - - PWM4 PHYINT PWM2 - - - - SSI1Clk - - PF3 59 - - PWM5 MDC PWM3 - - - - SSI1Fss - - PF4 58 - CCP0 C0o MDIO Fault0 - - - - SSI1Rx - - PF5 46 - CCP2 C1o RXD3 - - - - - SSI1Tx - - PF6 43 - CCP1 - RXD2 PhA0 - - - - I2S0TXMCLK U1RTS - PF7 42 - CCP4 - RXD1 PhB0 - - - - Fault1 - - PG0 19 - U2Rx PWM0 I2C1SCL PWM4 - - USB0EPEN - - - - PG1 18 - U2Tx PWM1 I2C1SDA PWM5 - - - - - - - PG2 17 - PWM0 - COL Fault0 - - - IDX1 I2S0RXSD - - PG3 16 - PWM1 - CRS Fault2 - - - Fault0 I2S0RXMCLK - - PG4 41 - CCP3 - RXD0 Fault1 - - - - U1RI - PG5 40 - CCP5 - TXEN IDX0 Fault1 - - - PG6 37 - PhA1 - TXCK - - - - PG7 36 - PhB1 - TXER - - - - July 22, 2011 - I2S0RXSCK U1DTR Fault1 I2S0RXWS CCP5 - - U1RI - - - 393 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-2. GPIO Pins and Alternate Functions (100LQFP) (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PH0 86 - CCP6 PWM2 - - - - - - PWM4 - - PH1 85 - CCP7 PWM3 - - - - - - PWM5 - - PH2 84 - IDX1 C1o - Fault3 - - - - TXD3 - - PH3 83 - PhB0 Fault0 - USB0EPEN - - - - TXD2 - - PH4 76 - - - - USB0PFLT - - - - TXD1 - SSI1Clk PH5 63 - - - - - - - - - TXD0 PH6 62 - - - - - - - - - RXDV Fault2 SSI1Fss PWM4 SSI1Rx PH7 15 - - - RXCK - - - - - - PWM5 SSI1Tx PJ0 14 - - - RXER - - - - - - PWM0 I2C1SCL PJ1 87 - - - - - - - - - USB0PFLT PWM1 I2C1SDA PJ2 39 - - - - - - - - - CCP0 Fault0 - PJ3 50 - - - - - - - - - U1CTS CCP6 - PJ4 52 - - - - - - - - - U1DCD CCP4 - PJ5 53 - - - - - - - - - U1DSR CCP2 - PJ6 54 - - - - - - - - - U1RTS CCP1 - PJ7 55 - - - - - - - - - U1DTR CCP0 - 10 11 a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. Table 8-3. GPIO Pins and Alternate Functions (108BGA) IO Pin Analog Function a Digital Function (GPIOPCTL PMCx Bit Field Encoding) 1 2 3 4 5 6 7 8 9 PA0 L3 - U0Rx - - - - - - I2C1SCL U1Rx - - PA1 M3 - U0Tx - - - - - - I2C1SDA U1Tx - - PA2 M4 - SSI0Clk - TXD2 PWM4 - - - - I2S0RXSD - - PA3 L4 - SSI0Fss - TXD1 PWM5 - - - - I2S0RXMCLK - - PA4 L5 - SSI0Rx - TXD0 - CAN0Rx - - - I2S0TXSCK - - PA5 M5 - SSI0Tx - RXDV - CAN0Tx - - - I2S0TXWS - - PA6 L6 - I2C1SCL CCP1 RXCK PWM0 PWM4 CAN0Rx - USB0EPEN U1CTS - - USB0PFLT U1DCD PA7 M6 - I2C1SDA CCP4 RXER PWM1 PWM5 CAN0Tx CCP3 - - PB0 E12 USB0ID CCP0 PWM2 - - U1Rx - - - - - - PB1 D12 USB0VBUS CCP2 PWM3 - CCP1 U1Tx - - - - - - IDX0 PB2 A11 - I2C0SCL PB3 E11 - I2C0SDA Fault0 - CCP3 CCP0 - - USB0EPEN - - - - Fault3 - - - USB0PFLT - - - PB4 A6 AIN10 C0- - - - U2Rx CAN0Rx IDX0 U1Rx - - - - PB5 B7 AIN11 C1- C0o CCP5 CCP6 CCP0 CAN0Tx CCP2 U1Tx - - - - PB6 A7 VREFA C0+ CCP1 CCP7 C0o Fault1 IDX0 CCP5 - - I2S0TXSCK - - PB7 A8 - - - - NMI - - RXD1 - - - - 394 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 8-3. GPIO Pins and Alternate Functions (108BGA) (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PC0 A9 - - - TCK SWCLK - - - - - - - - PC1 B9 - - - TMS SWDIO - - - - - - - - PC2 B8 - - - TDI - - - - - - - - PC3 A10 - - - TDO SWO - - - - - - - - PC4 L1 - CCP5 PhA0 TXD3 - CCP2 CCP4 - - CCP1 - - PC5 M1 C1+ CCP1 C1o C0o Fault2 CCP3 USB0EPEN - - - - - PC6 M2 - CCP3 PhB0 - - U1Rx CCP0 USB0PFLT - - - - PC7 L2 - CCP4 PhB0 - CCP0 U1Tx USB0PFLT C1o - - - - PD0 G1 AIN15 PWM0 CAN0Rx IDX0 U2Rx U1Rx CCP6 RXDV I2S0RXSCK U1CTS - - PD1 G2 AIN14 PWM1 CAN0Tx PhA0 U2Tx U1Tx CCP7 TXER I2S0RXWS U1DCD CCP2 PhB1 PD2 H2 AIN13 U1Rx CCP6 PWM2 CCP5 - - - - - - - PD3 H1 AIN12 U1Tx CCP7 PWM3 CCP0 - - - - - - - PD4 B5 AIN7 CCP0 CCP3 - TXD3 - - - I2S0RXSD U1RI - - PD5 C6 AIN6 CCP2 CCP4 - TXD2 - - - I2S0RXMCLK U2Rx - - PD6 A3 AIN5 Fault0 - - TXD1 - - - I2S0TXSCK U2Tx - - PD7 A2 AIN4 IDX0 C0o CCP1 TXD0 - - - I2S0TXWS U1DTR - - PE0 B11 - PWM4 SSI1Clk CCP3 - - - - - USB0PFLT - - PE1 A12 - PWM5 SSI1Fss Fault0 CCP2 CCP6 - - - - - - PE2 A4 AIN9 CCP4 SSI1Rx PhB1 PhA0 CCP2 - - - - - - PE3 B4 AIN8 CCP1 SSI1Tx PhA1 PhB0 CCP7 - - - - - - PE4 B2 AIN3 CCP3 - - Fault0 U2Tx CCP2 RXD0 - I2S0TXWS - - PE5 B3 AIN2 CCP5 - - - - - - - I2S0TXSD - - PE6 A1 AIN1 PWM4 C1o - - - - - - U1CTS - - PE7 B1 AIN0 PWM5 - - - - - - - U1DCD - - PF0 M9 - CAN1Rx PhB0 PWM0 RXCK - - - I2S0TXSD U1DSR - - PF1 H12 - CAN1Tx IDX1 PWM1 RXER - - - I2S0TXMCLK U1RTS CCP3 - PF2 J11 - - PWM4 PHYINT PWM2 - - - - SSI1Clk - - PF3 J12 - - PWM5 MDC PWM3 - - - - SSI1Fss - - PF4 L9 - CCP0 C0o MDIO Fault0 - - - - SSI1Rx - - PF5 L8 - CCP2 C1o RXD3 - - - - - SSI1Tx - - PF6 M8 - CCP1 - RXD2 PhA0 - - - - I2S0TXMCLK U1RTS - PF7 K4 - CCP4 - RXD1 PhB0 - - - - Fault1 - - PG0 K1 - U2Rx PWM0 I2C1SCL PWM4 - - USB0EPEN - - - - PG1 K2 - U2Tx PWM1 I2C1SDA PWM5 - - - - - - - PG2 J1 - PWM0 - COL Fault0 - - - IDX1 I2S0RXSD - - PG3 J2 - PWM1 - CRS Fault2 - - - Fault0 I2S0RXMCLK - - PG4 K3 - CCP3 - RXD0 Fault1 - - - - U1RI - PG5 M7 - CCP5 - TXEN IDX0 Fault1 - - - July 22, 2011 - I2S0RXSCK U1DTR - 395 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-3. GPIO Pins and Alternate Functions (108BGA) (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 PG6 L7 - PhA1 - TXCK - - - - PG7 C10 - PhB1 - TXER - - - - 8 9 Fault1 I2S0RXWS CCP5 - 10 11 U1RI - - - PH0 C9 - CCP6 PWM2 - - - - - - PWM4 - - PH1 C8 - CCP7 PWM3 - - - - - - PWM5 - - PH2 D11 - IDX1 C1o - Fault3 - - - - TXD3 - - PH3 D10 - PhB0 Fault0 - USB0EPEN - - - - TXD2 - - PH4 B10 - - - - USB0PFLT - - - - TXD1 - SSI1Clk PH5 F10 - - - - - - - - - TXD0 PH6 G3 - - - - - - - - - RXDV Fault2 SSI1Fss PWM4 SSI1Rx PH7 H3 - - - RXCK - - - - - - PWM5 SSI1Tx PJ0 F3 - - - RXER - - - - - - PWM0 I2C1SCL PJ1 B6 - - - - - - - - - USB0PFLT PWM1 I2C1SDA PJ2 K6 - - - - - - - - - CCP0 Fault0 - PJ3 M10 - - - - - - - - - U1CTS CCP6 - PJ4 K11 - - - - - - - - - U1DCD CCP4 - PJ5 K12 - - - - - - - - - U1DSR CCP2 - PJ6 L10 - - - - - - - - - U1RTS CCP1 - PJ7 L12 - - - - - - - - - U1DTR CCP0 - a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. 8.2 Functional Description Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-1 on page 397 and Figure 8-2 on page 398). The LM3S9L71 microcontroller contains nineports and thus nine of these physical GPIO blocks. Note that not all pins may be implemented on every block. Some GPIO pins can function as I/O signals for the on-chip peripheral modules. For information on which GPIO pins are used for alternate hardware functions, refer to Table 23-5 on page 1145. 396 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 8-1. Digital I/O Pads Commit Control GPIOLOCK GPIOCR Port Control GPIOPCTL Mode Control GPIOAFSEL Periph 1 DEMUX Alternate Input Alternate Output Alternate Output Enable MUX Periph 0 Pad Input Periph n GPIO Output GPIO Output Enable Interrupt Control Pad Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN MUX GPIODATA GPIODIR Interrupt MUX GPIO Input Data Control Pad Output Digital I/O Pad Package I/O Pin Pad Output Enable Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 July 22, 2011 397 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Figure 8-2. Analog/Digital I/O Pads Commit Control GPIOLOCK GPIOCR Port Control GPIOPCTL Mode Control GPIOAFSEL Periph 1 DEMUX Alternate Input Alternate Output Alternate Output Enable MUX Periph 0 Pad Input Periph n MUX MUX Data Control Pad Output Pad Output Enable Analog/Digital I/O Pad Package I/O Pin GPIO Input GPIO Output GPIODATA GPIODIR Interrupt GPIO Output Enable Interrupt Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Pad Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN GPIOAMSEL Analog Circuitry Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 8.2.1 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 ADC (for GPIO pins that connect to the ADC input MUX) Isolation Circuit Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. 8.2.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 407) is used to configure each individual pin as an input or output. When the data direction bit is cleared, the GPIO is configured as an input, and the corresponding data register bit captures and stores the value on the GPIO port. When the data direction bit is set, the GPIO is configured as an output, and the corresponding data register bit is driven out on the GPIO port. 398 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 8.2.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 406) by using bits [9:2] of the address bus as a mask. In this manner, software drivers can modify individual GPIO pins in a single instruction without affecting the state of the other pins. This method is more efficient than the conventional method of performing a read-modify-write operation to set or clear an individual GPIO pin. To implement this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set, the value of the GPIODATA register is altered. If the address bit is cleared, the data bit is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 has the results shown in Figure 8-3, where u indicates that data is unchanged by the write. Figure 8-3. GPIODATA Write Example ADDR[9:2] 0x098 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 0 0 0 0xEB 1 1 1 0 1 0 1 1 GPIODATA u u 1 u u 0 1 u 7 6 5 4 3 2 1 0 During a read, if the address bit associated with the data bit is set, the value is read. If the address bit associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-4. Figure 8-4. GPIODATA Read Example 8.2.2 ADDR[9:2] 0x0C4 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 1 0 0 GPIODATA 1 0 1 1 1 1 1 0 Returned Value 0 0 1 1 0 0 0 0 7 6 5 4 3 2 1 0 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. These registers are used to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, the external source must hold the level constant for the interrupt to be recognized by the controller. Three registers define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 408) July 22, 2011 399 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 409) ■ GPIO Interrupt Event (GPIOIEV) register (see page 410) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 411). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 412 and page 413). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the interrupt controller. Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR) register (see page 415). When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts should be masked (GPIOIM cleared). Writing any value to an interrupt control register can generate a spurious interrupt if the corresponding bits are enabled. 8.2.2.1 ADC Trigger Source In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set), an interrupt for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. See page 552. If no other Port B pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0) register can disable the Port B interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts on PB4 and wait for the ADC interrupt, or the ADC interrupt must be disabled in the EN0 register and the Port B interrupt handler must poll the ADC registers until the conversion is completed. See page 129 for more information. 8.2.3 Mode Control The GPIO pins can be controlled by either software or hardware. Software control is the default for most signals and corresponds to the GPIO mode, where the GPIODATA register is used to read or write the corresponding pins. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 416), the pin state is controlled by its alternate function (that is, the peripheral). Further pin muxing options are provided through the GPIO Port Control (GPIOPCTL) register which selects one of several peripheral functions for each GPIO. For information on the configuration options, refer to Table 23-5 on page 1145. Note: 8.2.4 If any pin is to be used as an ADC input, the appropriate bit in the GPIOAMSEL register must be set to disable the analog isolation circuit. Commit Control The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 416), GPIO Pull Up Select (GPIOPUR) register (see page 422), GPIO Pull-Down Select (GPIOPDR) register (see page 424), and GPIO Digital Enable (GPIODEN) register (see 400 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller page 427) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 429) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 430) have been set. 8.2.5 Pad Control The pad control registers allow software to configure the GPIO pads based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable for each GPIO. For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. 8.2.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 8.3 Initialization and Configuration The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides better back-to-back access performance than the APB bus. These apertures are mutually exclusive. The aperture enabled for a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL register (see page 227). To use the pins in a particular GPIO port, the clock for the port must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register (see page 281). When the internal POR signal is asserted and until otherwise configured, all GPIO pins are configured to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0, except for the pins shown in Table 8-1 on page 392. Table 8-4 on page 401 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 8-5 on page 402 shows how a rising edge interrupt is configured for pin 2 of a GPIO port. Table 8-4. GPIO Pad Configuration Examples a Configuration Digital Input (GPIO) GPIO Register Bit Value AFSEL 0 DIR ODR 0 0 DEN 1 PUR ? PDR ? DR2R DR4R DR8R X X X SLR X Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ? Open Drain Output (GPIO) 0 1 1 1 X X ? ? ? ? Open Drain Input/Output (I2C) 1 X 1 1 X X ? ? ? ? Digital Input (Timer CCP) 1 X 0 1 ? ? X X X X July 22, 2011 401 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-4. GPIO Pad Configuration Examples (continued) a Configuration Digital Input (QEI) GPIO Register Bit Value AFSEL DIR 1 ODR X DEN 0 PUR 1 PDR ? DR2R DR4R DR8R X X X ? SLR X Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ? Digital Output (Timer PWM) 1 X 0 1 ? ? ? ? ? ? Digital Input/Output (SSI) 1 X 0 1 ? ? ? ? ? ? Digital Input/Output (UART) 1 X 0 1 ? ? ? ? ? ? Analog Input (Comparator) 0 0 0 0 0 0 X X X X Digital Output (Comparator) 1 X 0 1 ? ? ? ? ? ? a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 8-5. GPIO Interrupt Configuration Example Register Desired Interrupt Event Trigger GPIOIS 0=edge a Pin 2 Bit Value 7 6 5 4 3 2 1 0 X X X X X 0 X X X X X X X 0 X X X X X X X 1 X X 0 0 0 0 0 1 0 0 1=level GPIOIBE 0=single edge 1=both edges GPIOIEV 0=Low level, or falling edge 1=High level, or rising edge GPIOIM 0=masked 1=not masked a. X=Ignored (don’t care bit) 8.4 Register Map Table 8-7 on page 403 lists the GPIO registers. Each GPIO port can be accessed through one of two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides better back-to-back access performance than the APB bus. Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to unconnected bits has no effect, and reading unconnected bits returns no meaningful data. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: ■ GPIO Port A (APB): 0x4000.4000 ■ GPIO Port A (AHB): 0x4005.8000 402 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ GPIO Port B (APB): 0x4000.5000 GPIO Port B (AHB): 0x4005.9000 GPIO Port C (APB): 0x4000.6000 GPIO Port C (AHB): 0x4005.A000 GPIO Port D (APB): 0x4000.7000 GPIO Port D (AHB): 0x4005.B000 GPIO Port E (APB): 0x4002.4000 GPIO Port E (AHB): 0x4005.C000 GPIO Port F (APB): 0x4002.5000 GPIO Port F (AHB): 0x4005.D000 GPIO Port G (APB): 0x4002.6000 GPIO Port G (AHB): 0x4005.E000 GPIO Port H (APB): 0x4002.7000 GPIO Port H (AHB): 0x4005.F000 GPIO Port J (APB): 0x4003.D000 GPIO Port J (AHB): 0x4006.0000 Note that each GPIO module clock must be enabled before the registers can be programmed (see page 281). There must be a delay of 3 system clocks after the GPIO module clock is enabled before any GPIO module registers are accessed. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 8-6. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL PA[1:0] UART0 0 1 0 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as GPIO pins, the PC[3:0] pins default to non-committable. Similarly, to ensure that the NMI pin is not accidentally programmed as a GPIO pin, the PB7 pin defaults to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 8-7. GPIO Register Map Offset Name Type Reset 0x000 GPIODATA R/W 0x0000.0000 Description GPIO Data July 22, 2011 See page 406 403 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-7. GPIO Register Map (continued) Description See page Offset Name Type Reset 0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 407 0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 408 0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 409 0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 410 0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 411 0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 412 0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 413 0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 415 0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 416 0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 418 0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 419 0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 420 0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 421 0x510 GPIOPUR R/W - GPIO Pull-Up Select 422 0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 424 0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 426 0x51C GPIODEN R/W - GPIO Digital Enable 427 0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 429 0x524 GPIOCR - - GPIO Commit 430 0x528 GPIOAMSEL R/W 0x0000.0000 GPIO Analog Mode Select 432 0x52C GPIOPCTL R/W - GPIO Port Control 434 0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 436 0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 437 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 438 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 439 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 440 0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 441 0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 442 0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 443 0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 444 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 445 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 446 404 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 8-7. GPIO Register Map (continued) Offset Name 0xFFC GPIOPCellID3 8.5 Type Reset RO 0x0000.00B1 Description GPIO PrimeCell Identification 3 See page 447 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. July 22, 2011 405 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 407). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be set. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are set in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are clear in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DATA R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and written to the registers are masked by the eight address lines [9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ADDR[9:2] and are configured as outputs. See “Data Register Operation” on page 399 for examples of reads and writes. 406 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be an input. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DIR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DIR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Data Direction Value Description 0 Corresponding pin is an input. 1 Corresponding pins is an output. July 22, 2011 407 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 IS R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Sense Value Description 0 The edge on the corresponding pin is detected (edge-sensitive). 1 The level on the corresponding pin is detected (level-sensitive). 408 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 408) is set to detect edges, setting a bit in the GPIOIBE register configures the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 410). Clearing a bit configures the pin to be controlled by the GPIOIEV register. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IBE RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 IBE R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Both Edges Value Description 0 Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 410). 1 Both edges on the corresponding pin trigger an interrupt. July 22, 2011 409 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 408). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in the GPIOIS register. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IEV RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 IEV R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Event Value Description 0 A falling edge or a Low level on the corresponding pin triggers an interrupt. 1 A rising edge or a High level on the corresponding pin triggers an interrupt. 410 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IME RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 IME R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Mask Enable Value Description 0 The interrupt from the corresponding pin is masked. 1 The interrupt from the corresponding pin is sent to the interrupt controller. July 22, 2011 411 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin. If the corresponding bit in the GPIO Interrupt Mask (GPIOIM) register (see page 411) is set, the interrupt is sent to the interrupt controller. Bits read as zero indicate that corresponding input pins have not initiated an interrupt. A bit in this register can be cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 RIS RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Raw Status Value Description 1 An interrupt condition has occurred on the corresponding pin. 0 An interrupt condition has not occurred on the corresponding pin. A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register. 412 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set), an interrupt for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. See page 552. If no other Port B pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0) register can disable the Port B interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the Port B interrupt handler must ignore and clear interrupts on PB4 and wait for the ADC interrupt, or the ADC interrupt must be disabled in the EN0 register and the Port B interrupt handler must poll the ADC registers until the conversion is completed. See page 129 for more information. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 MIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 413 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset Description 7:0 MIS RO 0x00 GPIO Masked Interrupt Status Value Description 1 An interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller. 0 An interrupt condition on the corresponding pin is masked or has not occurred. A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register. 414 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt bit in the GPIORIS and GPIOMIS registers. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 W1C 0 W1C 0 W1C 0 W1C 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 IC RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0 7:0 IC W1C 0x00 RO 0 W1C 0 W1C 0 W1C 0 W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Clear Value Description 1 The corresponding interrupt is cleared. 0 The corresponding interrupt is unaffected. July 22, 2011 415 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. If a bit is clear, the pin is used as a GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral functions are multiplexed on each GPIO. The GPIO Port Control (GPIOPCTL) register is used to select one of the possible functions. Table 23-5 on page 1145 details which functions are muxed on each GPIO pin. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in the table below. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 8-8. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 0 GPIOPCTL 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 416), GPIO Pull Up Select (GPIOPUR) register (see page 422), GPIO Pull-Down Select (GPIOPDR) register (see page 424), and GPIO Digital Enable (GPIODEN) register (see page 427) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 429) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 430) have been set. When using the I2C module, in addition to setting the GPIOAFSEL register bits for the I2C clock and data pins, the data pins should be set to open drain using the GPIO Open Drain Select (GPIOODR) register (see examples in “Initialization and Configuration” on page 401). 416 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x420 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 AFSEL RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 AFSEL R/W - RO 0 R/W - R/W - R/W - R/W - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Alternate Function Select Value Description 0 The associated pin functions as a GPIO and is controlled by the GPIO registers. 1 The associated pin functions as a peripheral signal and is controlled by the alternate hardware function. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 8-1 on page 392. July 22, 2011 417 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default, all GPIO pins have 2-mA drive. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV2 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DRV2 R/W 0xFF RO 0 R/W 1 R/W 1 R/W 1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 2-mA Drive Enable Value Description 1 The corresponding GPIO pin has 2-mA drive. 0 The drive for the corresponding GPIO pin is controlled by the GPIODR4R or GPIODR8R register. Setting a bit in either the GPIODR4 register or the GPIODR8 register clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. 418 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV4 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DRV4 R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 4-mA Drive Enable Value Description 1 The corresponding GPIO pin has 4-mA drive. 0 The drive for the corresponding GPIO pin is controlled by the GPIODR2R or GPIODR8R register. Setting a bit in either the GPIODR2 register or the GPIODR8 register clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. July 22, 2011 419 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and DRV4 bit in the GPIODR4R register are automatically cleared by hardware. The 8-mA setting is also used for high-current operation. Note: There is no configuration difference between 8-mA and high-current operation. The additional current capacity results from a shift in the VOH/VOL levels. See “Recommended Operating Conditions” on page 1190 for further information. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DRV8 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DRV8 R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 8-mA Drive Enable Value Description 1 The corresponding GPIO pin has 8-mA drive. 0 The drive for the corresponding GPIO pin is controlled by the GPIODR2R or GPIODR4R register. Setting a bit in either the GPIODR2 register or the GPIODR4 register clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. 420 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 427). Corresponding bits in the drive strength and slew rate control registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts as an input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no effect until the GPIO is changed to an output. When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set (see examples in “Initialization and Configuration” on page 401). GPIO Open Drain Select (GPIOODR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 ODE RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 ODE R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad Open Drain Enable Value Description 1 The corresponding pin is configured as open drain. 0 The corresponding pin is not configured as open drain. July 22, 2011 421 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 424). Write access to this register is protected with the GPIOCR register. Bits in GPIOCR that are cleared prevent writes to the equivalent bit in this register. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 8-9. GPIO Pins With Non-Zero Reset Values Note: GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 GPIOPCTL 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 416), GPIO Pull Up Select (GPIOPUR) register (see page 422), GPIO Pull-Down Select (GPIOPDR) register (see page 424), and GPIO Digital Enable (GPIODEN) register (see page 427) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 429) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 430) have been set. GPIO Pull-Up Select (GPIOPUR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x510 Type R/W, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - reserved Type Reset reserved Type Reset RO 0 PUE 422 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PUE R/W - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Pad Weak Pull-Up Enable Value Description 1 The corresponding pin has a weak pull-up resistor. 0 The corresponding pin is not affected. Setting a bit in the GPIOPDR register clears the corresponding bit in the GPIOPUR register. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 8-1 on page 392. July 22, 2011 423 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set, a weak pull-down resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 422). Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 8-10. GPIO Pins With Non-Zero Reset Values Note: GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 GPIOPCTL 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 416), GPIO Pull Up Select (GPIOPUR) register (see page 422), GPIO Pull-Down Select (GPIOPDR) register (see page 424), and GPIO Digital Enable (GPIODEN) register (see page 427) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 429) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 430) have been set. GPIO Pull-Down Select (GPIOPDR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 PDE 424 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PDE R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Pad Weak Pull-Down Enable Value Description 1 The corresponding pin has a weak pull-down resistor. 0 The corresponding pin is not affected. Setting a bit in the GPIOPUR register clears the corresponding bit in the GPIOPDR register. The change is effective on the second clock cycle after the write if accessing GPIO via the APB memory aperture. If using AHB access, the change is effective on the next clock cycle. July 22, 2011 425 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 420). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 SRL RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 SRL R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Slew Rate Limit Enable (8-mA drive only) Value Description 1 Slew rate control is enabled for the corresponding pin. 0 Slew rate control is disabled for the corresponding pin. 426 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin as a digital input or output (either GPIO or alternate function), the corresponding GPIODEN bit must be set. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 8-11. GPIO Pins With Non-Zero Reset Values Note: GPIO Pins Default State GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL PA[1:0] UART0 0 1 0 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 416), GPIO Pull Up Select (GPIOPUR) register (see page 422), GPIO Pull-Down Select (GPIOPDR) register (see page 424), and GPIO Digital Enable (GPIODEN) register (see page 427) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 429) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 430) have been set. July 22, 2011 427 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) GPIO Digital Enable (GPIODEN) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x51C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W - R/W - R/W - R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DEN RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DEN R/W - RO 0 R/W - R/W - R/W - R/W - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Enable Value Description 0 The digital functions for the corresponding pin are disabled. 1 The digital functions for the corresponding pin are enabled. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in Table 8-1 on page 392. 428 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 430). Writing 0x4C4F.434B to the GPIOLOCK register unlocks the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x0000.0001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x0000.0000. GPIO Lock (GPIOLOCK) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type 31:0 LOCK R/W R/W 0 Reset R/W 0 Description 0x0000.0001 GPIO Lock A write of the value 0x4C4F.434B unlocks the GPIO Commit (GPIOCR) register for write access.A write of any other value or a write to the GPIOCR register reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x1 The GPIOCR register is locked and may not be modified. 0x0 The GPIOCR register is unlocked and may be modified. July 22, 2011 429 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN registers are committed when a write to these registers is performed. If a bit in the GPIOCR register is cleared, the data being written to the corresponding bit in the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers cannot be committed and retains its previous value. If a bit in the GPIOCR register is set, the data being written to the corresponding bit of the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers is committed to the register and reflects the new value. The contents of the GPIOCR register can only be modified if the status in the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the status in the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the registers that control connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the NMI and JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the corresponding registers. Because this protection is currently only implemented on the NMI and JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN register bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x524 Type -, reset 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 - - - - - - - - reserved Type Reset reserved Type Reset RO 0 CR 430 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CR - - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Commit Value Description 1 The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits can be written. 0 The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits cannot be written. Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as GPIO pins, the PC[3:0] pins default to non-committable. Similarly, to ensure that the NMI pin is not accidentally programmed as a GPIO pin, the PB7 pin defaults to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. July 22, 2011 431 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 Important: This register is only valid for ports D and E; the corresponding base addresses for the remaining ports are not valid. If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be set to disable the analog isolation circuit. The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because the GPIOs may be driven by a 5-V source and affect analog operation, analog circuitry requires isolation from the pins when they are not used in their analog function. Each bit of this register controls the isolation circuitry for the corresponding GPIO signal. For information on which GPIO pins can be used for ADC functions, refer to Table 23-5 on page 1145. GPIO Analog Mode Select (GPIOAMSEL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x528 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset GPIOAMSEL RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 432 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 7:0 GPIOAMSEL R/W 0x00 GPIO Analog Mode Select Value Description 1 The analog function of the pin is enabled, the isolation is disabled, and the pin is capable of analog functions. 0 The analog function of the pin is disabled, the isolation is enabled, and the pin is capable of digital functions as specified by the other GPIO configuration registers. Note: This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. The reset state of this register is 0 for all signals. July 22, 2011 433 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the GPIOAFSEL register are cleared on reset, therefore most GPIO pins are configured as GPIOs by default. When a bit is set in the GPIOAFSEL register, the corresponding GPIO signal is controlled by an associated peripheral. The GPIOPCTL register selects one out of a set of peripheral functions for each GPIO, providing additional flexibility in signal definition. For information on the defined encodings for the bit fields in this register, refer to Table 23-5 on page 1145. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed in the table below. Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 8-12. GPIO Pins With Non-Zero Reset Values GPIO Pins Default State PA[1:0] UART0 GPIOAFSEL GPIODEN GPIOPDR GPIOPUR 0 1 0 GPIOPCTL 0 0x1 PA[5:2] SSI0 0 1 0 0 0x1 PB[3:2] I2C0 0 1 0 0 0x3 PC[3:0] JTAG/SWD 1 1 0 1 0x1 GPIO Port Control (GPIOPCTL) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0x52C Type R/W, reset 31 30 29 28 27 26 PMC7 Type Reset R/W - R/W - 15 14 R/W - R/W - R/W - R/W - 13 12 11 10 PMC3 Type Reset R/W - R/W - 25 24 23 22 PMC6 R/W - R/W - R/W - R/W - 9 8 7 6 PMC2 R/W - R/W - R/W - R/W - 21 20 19 18 PMC5 R/W - R/W - R/W - R/W - 5 4 3 2 PMC1 R/W - Bit/Field Name Type Reset 31:28 PMC7 R/W - R/W - R/W - R/W - 17 16 R/W - R/W - 1 0 R/W - R/W - PMC4 PMC0 R/W - R/W - R/W - R/W - Description Port Mux Control 7 This field controls the configuration for GPIO pin 7. 434 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 27:24 PMC6 R/W - Description Port Mux Control 6 This field controls the configuration for GPIO pin 6. 23:20 PMC5 R/W - Port Mux Control 5 This field controls the configuration for GPIO pin 5. 19:16 PMC4 R/W - Port Mux Control 4 This field controls the configuration for GPIO pin 4. 15:12 PMC3 R/W - Port Mux Control 3 This field controls the configuration for GPIO pin 3. 11:8 PMC2 R/W - Port Mux Control 2 This field controls the configuration for GPIO pin 2. 7:4 PMC1 R/W - Port Mux Control 1 This field controls the configuration for GPIO pin 1. 3:0 PMC0 R/W - Port Mux Control 0 This field controls the configuration for GPIO pin 0. July 22, 2011 435 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 23: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID4 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [7:0] 436 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 24: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID5 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [15:8] July 22, 2011 437 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 25: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID6 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [23:16] 438 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 26: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID7 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [31:24] July 22, 2011 439 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 27: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x61 RO 0 RO 0 RO 1 RO 1 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 440 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 28: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 22, 2011 441 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 29: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID2 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x18 RO 0 RO 0 RO 0 RO 0 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 442 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 30: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x01 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 22, 2011 443 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 31: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 444 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 32: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID1 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 RO 0 RO 1 RO 1 RO 1 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. July 22, 2011 445 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 33: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID2 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID2 RO 0x05 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 446 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 34: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 CID3 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID3 RO 0xB1 RO 0 RO 1 RO 0 RO 1 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. July 22, 2011 447 Texas Instruments-Production Data General-Purpose Timers 9 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. ® The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM block provides two 16-bit timers/counters (referred to as Timer A and Timer B) that can be configured to operate independently as timers or event counters, or concatenated to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger μDMA transfers. In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events. The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer resources include the System Timer (SysTick) (see 114) and the PWM timer in the PWM module (see “PWM Timer” on page 1020). The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional options: ■ Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 16-bit input-edge count- or time-capture modes – 16-bit PWM mode with software-programmable output inversion of the PWM signal ■ Count up or down ■ Eight Capture Compare PWM pins (CCP) ■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events ■ ADC event trigger ■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding RTC mode) ■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each timer – Burst request generated on timer interrupt 448 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 9.1 Block Diagram In the block diagram, the specific Capture Compare PWM (CCP) pins available depend on the Stellaris device. See Table 9-1 on page 449 for the available CCP pins and their timer assignments. Figure 9-1. GPTM Module Block Diagram 0x0000 (Down Counter Modes) 0xFFFF (Up Counter Modes) Timer A Free-Running Value Timer A Control GPTMTAPMR GPTMTAPR TA Comparator GPTMTAMATCHR Clock / Edge Detect GPTMTAILR Interrupt / Config Timer A Interrupt GPTMTAMR GPTMTAR En GPTMCFG GPTMCTL GPTMTAV GPTMIMR Timer B Interrupt 32 KHz or Even CCP Pin RTC Divider GPTMRIS GPTMTBV GPTMMIS GPTMICR GPTMTBR En Clock / Edge Detect Timer B Control GPTMTBMR GPTMTBILR Timer B Free-Running Value Odd CCP Pin TB Comparator GPTMTBMATCHR GPTMTBPR GPTMTBPMR 0x0000 (Down Counter Modes) 0xFFFF (Up Counter Modes) System Clock Table 9-1. Available CCP Pins Timer Timer 0 Timer 1 Timer 2 Timer 3 9.2 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin TimerA CCP0 - TimerB - CCP1 TimerA CCP2 - TimerB - CCP3 TimerA CCP4 - TimerB - CCP5 TimerA CCP6 - TimerB - CCP7 Signal Description The following table lists the external signals of the GP Timer module and describes the function of each. The GP Timer signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these GP Timer signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the GP Timer function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port July 22, 2011 449 Texas Instruments-Production Data General-Purpose Timers Control (GPIOPCTL) register (page 434) to assign the GP Timer signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. Table 9-2. Signals for General-Purpose Timers (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP0 13 22 23 39 55 58 66 72 91 97 PD3 (4) PC7 (4) PC6 (6) PJ2 (9) PJ7 (10) PF4 (1) PB0 (1) PB2 (5) PB5 (4) PD4 (1) I/O TTL Capture/Compare/PWM 0. CCP1 24 25 34 43 54 67 90 96 100 PC5 (1) PC4 (9) PA6 (2) PF6 (1) PJ6 (10) PB1 (4) PB6 (1) PE3 (1) PD7 (3) I/O TTL Capture/Compare/PWM 1. CCP2 6 11 25 46 53 67 75 91 95 98 PE4 (6) PD1 (10) PC4 (5) PF5 (1) PJ5 (10) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) I/O TTL Capture/Compare/PWM 2. CCP3 6 23 24 35 41 61 72 74 97 PE4 (1) PC6 (1) PC5 (5) PA7 (7) PG4 (1) PF1 (10) PB2 (4) PE0 (3) PD4 (2) I/O TTL Capture/Compare/PWM 3. CCP4 22 25 35 42 52 95 98 PC7 (1) PC4 (6) PA7 (2) PF7 (1) PJ4 (10) PE2 (1) PD5 (2) I/O TTL Capture/Compare/PWM 4. 450 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 9-2. Signals for General-Purpose Timers (100LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP5 5 12 25 36 40 90 91 PE5 (1) PD2 (4) PC4 (1) PG7 (8) PG5 (1) PB6 (6) PB5 (2) I/O TTL Capture/Compare/PWM 5. CCP6 10 12 50 75 86 91 PD0 (6) PD2 (2) PJ3 (10) PE1 (5) PH0 (1) PB5 (3) I/O TTL Capture/Compare/PWM 6. CCP7 11 13 85 90 96 PD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) I/O TTL Capture/Compare/PWM 7. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 9-3. Signals for General-Purpose Timers (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP0 H1 L2 M2 K6 L12 L9 E12 A11 B7 B5 PD3 (4) PC7 (4) PC6 (6) PJ2 (9) PJ7 (10) PF4 (1) PB0 (1) PB2 (5) PB5 (4) PD4 (1) I/O TTL Capture/Compare/PWM 0. CCP1 M1 L1 L6 M8 L10 D12 A7 B4 A2 PC5 (1) PC4 (9) PA6 (2) PF6 (1) PJ6 (10) PB1 (4) PB6 (1) PE3 (1) PD7 (3) I/O TTL Capture/Compare/PWM 1. CCP2 B2 G2 L1 L8 K12 D12 A12 B7 A4 C6 PE4 (6) PD1 (10) PC4 (5) PF5 (1) PJ5 (10) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) I/O TTL Capture/Compare/PWM 2. July 22, 2011 451 Texas Instruments-Production Data General-Purpose Timers Table 9-3. Signals for General-Purpose Timers (108BGA) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP3 B2 M2 M1 M6 K3 H12 A11 B11 B5 PE4 (1) PC6 (1) PC5 (5) PA7 (7) PG4 (1) PF1 (10) PB2 (4) PE0 (3) PD4 (2) I/O TTL Capture/Compare/PWM 3. CCP4 L2 L1 M6 K4 K11 A4 C6 PC7 (1) PC4 (6) PA7 (2) PF7 (1) PJ4 (10) PE2 (1) PD5 (2) I/O TTL Capture/Compare/PWM 4. CCP5 B3 H2 L1 C10 M7 A7 B7 PE5 (1) PD2 (4) PC4 (1) PG7 (8) PG5 (1) PB6 (6) PB5 (2) I/O TTL Capture/Compare/PWM 5. CCP6 G1 H2 M10 A12 C9 B7 PD0 (6) PD2 (2) PJ3 (10) PE1 (5) PH0 (1) PB5 (3) I/O TTL Capture/Compare/PWM 6. CCP7 G2 H1 C8 A7 B4 PD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) I/O TTL Capture/Compare/PWM 7. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 9.3 Functional Description The main components of each GPTM block are two free-running up/down counters (referred to as Timer A and Timer B), two match registers, two prescaler match registers, two shadow registers, and two load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Timer A and Timer B can be used individually, in which case they have a 16-bit counting range. In addition, Timer A and Timer B can be concatenated to provide a 32-bit counting range. Note that the prescaler can only be used when the timers are used individually. The available modes for each GPTM block are shown in Table 9-4 on page 453. Note that when counting down, the prescaler acts as a true prescaler and contains the least-significant bits of the count. When counting up, the prescaler acts as a timer extension and holds the most-significant bits of the count. 452 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 9-4. General-Purpose Timer Capabilities Mode a Timer Use Count Direction Counter Size Prescaler Size Individual Up or Down 16-bit 8-bit Concatenated Up or Down 32-bit - Individual Up or Down 16-bit 8-bit Concatenated Up or Down 32-bit - RTC Concatenated Up 32-bit - Edge Count Individual Down 16-bit 8-bit Edge Time Individual Down 16-bit - PWM Individual Down 16-bit - One-shot Periodic a. The prescaler is only available when the timers are used individually Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 465), the GPTM Timer A Mode (GPTMTAMR) register (see page 466), and the GPTM Timer B Mode (GPTMTBMR) register (see page 468). When in one of the concatentated modes, Timer A and Timer B can only operate in one mode. However, when configured in an individual mode, Timer A and Timer B can be independently configured in any combination of the individual modes. 9.3.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all 1s, along with their corresponding load registers: the GPTM Timer A Interval Load (GPTMTAILR) register (see page 483) and the GPTM Timer B Interval Load (GPTMTBILR) register (see page 484) and shadow registers: the GPTM Timer A Value (GPTMTAV) register (see page 493) and the GPTM Timer B Value (GPTMTBV) register (see page 494). The prescale counters are initialized to 0x00: the GPTM Timer A Prescale (GPTMTAPR) register (see page 487) and the GPTM Timer B Prescale (GPTMTBPR) register (see page 488). 9.3.2 Timer Modes This section describes the operation of the various timer modes. When using Timer A and Timer B in concatenated mode, only the Timer A control and status bits must be used; there is no need to use Timer B control and status bits. The GPTM is placed into individual mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 465). In the following sections, the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer B function. The prescaler is only available in the 16-bit one-shot, periodic, and input edge count timer mode. Note that when counting down, the prescaler acts as a true prescaler and contains the least-significant bits of the count. When counting up, the prescaler acts as a timer extension and holds the most-significant bits of the count. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count mode is the value in the GPTM Timer n Match (GPTMTnMATCH) and the optional GPTM Timer n Prescale Match (GPTMTnPMR) registers. 9.3.2.1 One-Shot/Periodic Timer Mode The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTM Timer n Mode (GPTMTnMR) register (see page 466). The timer is configured to count up or down using the TnCDIR bit in the GPTMTnMR register. When software sets the TnEN bit in the GPTM Control (GPTMCTL) register (see page 470), the timer begins counting up from 0x0 or down from its preloaded value. Alternatively, if the TnWOT bit July 22, 2011 453 Texas Instruments-Production Data General-Purpose Timers is set in the GPTMTnMR register, once the TnEN bit is set, the timer waits for a trigger to begin counting (see the section called “Wait-for-Trigger Mode” on page 455). When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start value from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is counting up and it reaches the timeout event (the value in the GPTMTnILR and the GPTMTnPR registers), the timer reloads with 0x0. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, the timer starts counting again on the next cycle. In periodic, snap-shot mode (TnSNAPS bit in the GPTMTnMR register is set), the actual free-running value of the timer at the time-out event is loaded into the GPTMTnR register. In this manner, software can determine the time elapsed from the interrupt assertion to the ISR entry. In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the time-out event. The GPTM sets the TnTORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 475), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 481). If the timeout interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register (see page 473), the GPTM also sets the TnTOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 478). By setting the TnMIE bit in the GPTMTAMR register, an interrupt can also be generated when the Timer value equals the value loaded into the GPTM Timer n Match (GPTMTnMATCH) and GPTM Timer n Prescale Match (GPTMTnPMR) registers. This interrupt has the same status, masking, and clearing functions as the timeout interrupt. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL. The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 337. If software updates the GPTMTnILR register while the counter is counting down, the counter loads the new value on the next clock cycle and continues counting down from the new value. If software updates the GPTMTnILR register while the counter is counting up, the timeout event is changed on the next cycle to the new value. If software updates the GPTM Timer n Value (GPTMTnV) register while the counter is counting up or down, the counter loads the new value on the next clock cycle and continues counting from the new value. If software updates the GPTMTnMATCHR register while the counter is counting, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. The following table shows a variety of configurations for a 16-bit free-running timer while using the prescaler. All values assume an 80-MHz clock with Tc=12.5 ns (clock period). Table 9-5. 16-Bit Timer With Prescaler Configurations a Prescale #Clock (Tc) Max Time Units 00000000 1 0.8192 ms 00000001 2 1.6384 ms 00000010 3 2.4576 ms ------------ -- -- -- 11111101 254 208.0768 ms 11111110 255 208.896 ms 11111111 256 209.7152 ms a. Tc is the clock period. 454 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Wait-for-Trigger Mode The Wait-for-Trigger mode allows daisy chaining of the timer modules such that once configured, a single timer can initiate mulitple timing events using the Timer triggers. Wait-for-Trigger mode is enabled by setting the TnWOT bit in the GPTMTnMR register. When the TnWOT bit is set, Timer N+1 does not begin counting until the timer in the previous position in the daisy chain (Timer N) reaches its time-out event. The daisy chain is configured such that GPTM1 always follows GPTM0, GPTM2 follows GPTM1, and so on. If Timer A is in 32-bit mode (controlled by the GPTMCFG bit in the GPTMCFG register), it triggers Timer A in the next module. If Timer A is in 16-bit mode, it triggers Timer B in the same module, and Timer B triggers Timer A in the next module. Care must be taken that the TAWOT bit is never set in GPTM0. Figure 9-2 on page 455 shows how the GPTMCFG bit affects the daisy chain. This function is valid for both one-shot and periodic modes. Figure 9-2. Timer Daisy Chain GP Timer N+1 1 0 GPTMCFG Timer B ADC Trigger Timer B Timer A Timer A ADC Trigger GP Timer N 1 0 GPTMCFG Timer B ADC Trigger Timer B Timer A 9.3.2.2 Timer A ADC Trigger Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers are configured as an up-counter. When RTC mode is selected for the first time after reset, the counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM Timer A Interval Load (GPTMTAILR) register (see page 483). The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1-Hz rate and is passed along to the input of the counter. When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from its preloaded value of 0x1. When the current count value matches the preloaded value in the GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 337. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 9.3.2.3 Input Edge-Count Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low July 22, 2011 455 Texas Instruments-Production Data General-Purpose Timers for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. In Edge-Count mode, the timer is configured as a 24-bit down-counter including the optional prescaler with the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR) register and the lower bits in the GPTMTnR register. In this mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of the GPTMTnMR register must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL.The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 337. After the match value is reached, the counter is then reloaded using the value in GPTMTnILR and GPTMTnPR registers, and stopped because the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 9-3 on page 456 shows how Input Edge-Count mode works. In this case, the timer start value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted because the timer automatically clears the TnEN bit after the current count matches the value in the GPTMTnMATCHR register. Figure 9-3. Input Edge-Count Mode Example Count Timer stops, flags asserted Timer reload on next cycle Ignored Ignored 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal 456 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 9.3.2.4 Input Edge-Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. The prescaler is not available in 16-Bit Input Edge-Time mode. In Edge-Time mode, the timer is configured as a 16-bit down-counter. In this mode, the timer is initialized to the value loaded in the GPTMTnILRregister. The timer is capable of capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current timer counter value is captured in the GPTMTnR register and is available to be read by the microcontroller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). The GPTMTnV contains the free-running value of the timer and can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR. In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL.The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 337. After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with the value from the GPTMTnILR register. Figure 9-4 on page 458 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into the GPTMTnR register). July 22, 2011 457 Texas Instruments-Production Data General-Purpose Timers Figure 9-4. 16-Bit Input Edge-Time Mode Example Count 0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z Z X Y Time Input Signal 9.3.2.5 PWM Mode Note: The prescaler is not available in 16-Bit PWM mode. The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 16-bit down-counter with a start value (and thus period) defined by the GPTMTnILR register. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x1 or 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0 state. On the next counter cycle in periodic mode, the counter reloads its start value from the GPTMTnILR register and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTMTnMATCHR register. Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 9-5 on page 459 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMTnILR=0xC350 and the match value is GPTMTnMATCHR=0x411A. 458 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 9-5. 16-Bit PWM Mode Example Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 9.3.3 DMA Operation The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs. The arbitration size of the μDMA transfer should be set to the amount of data that should be transferred whenever a timer event occurs. For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of 8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items have been transferred. No other special steps are needed to enable Timers for μDMA operation. Refer to “Micro Direct Memory Access (μDMA)” on page 333 for more details about programming the μDMA controller. 9.3.4 Accessing Concatenated Register Values The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in the GPTM Configuration (GPTMCFG) register. In both configurations, certain registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 483 ■ GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 484 ■ GPTM Timer A (GPTMTAR) register [15:0], see page 491 ■ GPTM Timer B (GPTMTBR) register [15:0], see page 492 ■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 493 July 22, 2011 459 Texas Instruments-Production Data General-Purpose Timers ■ GPTM Timer B Value (GPTMTBV) register [15:0], see page 494 ■ GPTM Timer A Match (GPTMTAMATCHR) register [15:0], see page 485 ■ GPTM Timer B Match (GPTMTBMATCHR) register [15:0], see page 486 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a 32-bit read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] A 32-bit read access to GPTMTAV returns the value: GPTMTBV[15:0]:GPTMTAV[15:0] 9.4 Initialization and Configuration To use a GPTM, the appropriate TIMERn bit must be set in the RCGC1 register (see page 272). If using any CCP pins, the clock to the appropriate GPIO module must be enabled via the RCGC1 register (see page 272). To find out which GPIO port to enable, refer to Table 23-4 on page 1137. Configure the PMCn fields in the GPIOPCTL register to assign the CCP signals to the appropriate pins (see page 434 and Table 23-5 on page 1145). This section shows module initialization and configuration examples for each of the supported timer modes. 9.4.1 One-Shot/Periodic Timer Mode The GPTM is configured for One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000. 3. Configure the TnMR field in the GPTM Timer n Mode Register (GPTMTnMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Optionally configure the TnSNAPS, TnWOT, TnMTE, and TnCDIR bits in the GPTMTnMR register to select whether to capture the value of the free-running timer at time-out, use an external trigger to start counting, configure an additional trigger or interrupt, and count up or down. 5. Load the start value into the GPTM Timer n Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTMCTL register to enable the timer and start counting. 460 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear Register (GPTMICR). If the TnMIE bit in the GPTMTnMR register is set, the RTCRIS bit in the GPTMRIS register is set, and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out event. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode reloads the timer and continues counting after the time-out event. 9.4.2 Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0001. 3. Write the match value to the GPTM Timer n Match Register (GPTMTnMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as needed. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTnMATCHR register, the GPTM asserts the RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register. 9.4.3 Input Edge-Count Mode A timer is configured to Input Edge-Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register (GPTMTnPR). 6. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 7. Load the event count into the GPTM Timer n Match (GPTMTnMATCHR) register. 8. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 9. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. July 22, 2011 461 Texas Instruments-Production Data General-Purpose Timers 10. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. When counting down in Input Edge-Count Mode, the timer stops after the programmed number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 461 through step 9 on page 462. 9.4.4 Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timer n (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 9.4.5 PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 6. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value. 462 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 9.5 Register Map Table 9-6 on page 463 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s address, relative to that timer’s base address: ■ ■ ■ ■ Timer 0: 0x4003.0000 Timer 1: 0x4003.1000 Timer 2: 0x4003.2000 Timer 3: 0x4003.3000 Note that the GP Timer module clock must be enabled before the registers can be programmed (see page 272). There must be a delay of 3 system clocks after the Timer module clock is enabled before any Timer module registers are accessed. Table 9-6. Timers Register Map Description See page Offset Name Type Reset 0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 465 0x004 GPTMTAMR R/W 0x0000.0000 GPTM Timer A Mode 466 0x008 GPTMTBMR R/W 0x0000.0000 GPTM Timer B Mode 468 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 470 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 473 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 475 0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 478 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 481 0x028 GPTMTAILR R/W 0xFFFF.FFFF GPTM Timer A Interval Load 483 0x02C GPTMTBILR R/W 0x0000.FFFF GPTM Timer B Interval Load 484 0x030 GPTMTAMATCHR R/W 0xFFFF.FFFF GPTM Timer A Match 485 0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM Timer B Match 486 0x038 GPTMTAPR R/W 0x0000.0000 GPTM Timer A Prescale 487 0x03C GPTMTBPR R/W 0x0000.0000 GPTM Timer B Prescale 488 0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 489 0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 490 0x048 GPTMTAR RO 0xFFFF.FFFF GPTM Timer A 491 0x04C GPTMTBR RO 0x0000.FFFF GPTM Timer B 492 0x050 GPTMTAV RW 0xFFFF.FFFF GPTM Timer A Value 493 July 22, 2011 463 Texas Instruments-Production Data General-Purpose Timers Table 9-6. Timers Register Map (continued) Offset Name 0x054 GPTMTBV 9.6 Type Reset RW 0x0000.FFFF Description GPTM Timer B Value See page 494 Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. 464 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. Important: Bits in this register should only be changed when the TAEN and TBEN bits in the GPTMCTL register are cleared. GPTM Configuration (GPTMCFG) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 GPTMCFG R/W 0x0 GPTMCFG R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Configuration The GPTMCFG values are defined as follows: Value Description 0x0 32-bit timer configuration. 0x1 32-bit real-time clock (RTC) counter configuration. 0x2-0x3 Reserved 0x4 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 0x5-0x7 Reserved July 22, 2011 465 Texas Instruments-Production Data General-Purpose Timers Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in PWM mode, set the TAAMS bit, clear the TACMR bit, and configure the TAMR field to 0x1 or 0x2. This register controls the modes for Timer A when it is used individually. When Timer A and Timer B are concatenated, this register controls the modes for both Timer A and Timer B, and the contents of GPTMTBMR are ignored. Important: Bits in this register should only be changed when the TAEN bit in the GPTMCTL register is cleared. GPTM Timer A Mode (GPTMTAMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TASNAPS TAWOT RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 TASNAPS R/W 0 RO 0 R/W 0 R/W 0 5 4 3 2 TAMIE TACDIR TAAMS TACMR R/W 0 R/W 0 R/W 0 R/W 0 0 TAMR R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer A Snap-Shot Mode Value Description 6 TAWOT R/W 0 0 Snap-shot mode is disabled. 1 If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPTM Timer A (GPTMTAR) register. GPTM Timer A Wait-on-Trigger Value Description 0 Timer A begins counting as soon as it is enabled. 1 If Timer A is enabled (TAEN is set in the GPTMCTL register), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain, see Figure 9-2 on page 455. This function is valid for both one-shot and periodic modes. This bit must be clear for GP Timer Module 0, Timer A. 466 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 5 TAMIE R/W 0 Description GPTM Timer A Match Interrupt Enable Value Description 4 TACDIR R/W 0 0 The match interrupt is disabled. 1 An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes. GPTM Timer A Count Direction Value Description 0 The timer counts down. 1 When in one-shot or periodic mode, the timer counts up. When counting up, the timer starts from a value of 0x0. When in PWM or RTC mode, the status of this bit is ignored. PWM mode always counts down and RTC mode always counts up. 3 TAAMS R/W 0 GPTM Timer A Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TACMR R/W 0 To enable PWM mode, you must also clear the TACMR bit and configure the TAMR field to 0x1 or 0x2. GPTM Timer A Capture Mode The TACMR values are defined as follows: Value Description 1:0 TAMR R/W 0x0 0 Edge-Count mode 1 Edge-Time mode GPTM Timer A Mode The TAMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. July 22, 2011 467 Texas Instruments-Production Data General-Purpose Timers Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in PWM mode, set the TBAMS bit, clear the TBCMR bit, and configure the TBMR field to 0x1 or 0x2. This register controls the modes for Timer B when it is used individually. When Timer A and Timer B are concatenated, this register is ignored and GPTMTBMR controls the modes for both Timer A and Timer B. Important: Bits in this register should only be changed when the TBEN bit in the GPTMCTL register is cleared. GPTM Timer B Mode (GPTMTBMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TBSNAPS TBWOT RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 TBSNAPS R/W 0 RO 0 R/W 0 R/W 0 5 4 3 2 TBMIE TBCDIR TBAMS TBCMR R/W 0 R/W 0 R/W 0 R/W 0 0 TBMR R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Snap-Shot Mode Value Description 6 TBWOT R/W 0 0 Snap-shot mode is disabled. 1 If Timer B is configured in the periodic mode, the actual free-running value of Timer B is loaded at the time-out event into the GPTM Timer B (GPTMTBR) register. GPTM Timer B Wait-on-Trigger Value Description 0 Timer B begins counting as soon as it is enabled. 1 If Timer B is enabled (TBEN is set in the GPTMCTL register), Timer B does not begin counting until it receives an it receives a trigger from the timer in the previous position in the daisy chain, see Figure 9-2 on page 455. This function is valid for both one-shot and periodic modes. 468 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 5 TBMIE R/W 0 Description GPTM Timer B Match Interrupt Enable Value Description 4 TBCDIR R/W 0 0 The match interrupt is disabled. 1 An interrupt is generated when the match value in the GPTMTBMATCHR register is reached in the one-shot and periodic modes. GPTM Timer B Count Direction Value Description 0 The timer counts down. 1 When in one-shot or periodic mode, the timer counts up. When counting up, the timer starts from a value of 0x0. When in PWM or RTC mode, the status of this bit is ignored. PWM mode always counts down and RTC mode always counts up. 3 TBAMS R/W 0 GPTM Timer B Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: 2 TBCMR R/W 0 To enable PWM mode, you must also clear the TBCMR bit and configure the TBMR field to 0x1 or 0x2. GPTM Timer B Capture Mode The TBCMR values are defined as follows: Value Description 1:0 TBMR R/W 0x0 0 Edge-Count mode 1 Edge-Time mode GPTM Timer B Mode The TBMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. July 22, 2011 469 Texas Instruments-Production Data General-Purpose Timers Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. Important: Bits in this register should only be changed when the TnEN bit for the respective timer is cleared. GPTM Control (GPTMCTL) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 reserved TBPWML TBOTE reserved RO 0 R/W 0 R/W 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TBSTALL TBEN reserved TAPWML TAOTE RTCEN TASTALL TAEN R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset TBEVENT R/W 0 R/W 0 Bit/Field Name Type Reset 31:15 reserved RO 0x0000.0 14 TBPWML R/W 0 TAEVENT R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B PWM Output Level The TBPWML values are defined as follows: Value Description 13 TBOTE R/W 0 0 Output is unaffected. 1 Output is inverted. GPTM Timer B Output Trigger Enable The TBOTE values are defined as follows: Value Description 0 The output Timer B ADC trigger is disabled. 1 The output Timer B ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see page 552). 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 470 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 11:10 TBEVENT R/W 0x0 Description GPTM Timer B Event Mode The TBEVENT values are defined as follows: Value Description 9 TBSTALL R/W 0 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges GPTM Timer B Stall Enable The TBSTALL values are defined as follows: Value Description 0 Timer B continues counting while the processor is halted by the debugger. 1 Timer B freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TBSTALL bit is ignored. 8 TBEN R/W 0 GPTM Timer B Enable The TBEN values are defined as follows: Value Description 0 Timer B is disabled. 1 Timer B is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 TAPWML R/W 0 GPTM Timer A PWM Output Level The TAPWML values are defined as follows: Value Description 5 TAOTE R/W 0 0 Output is unaffected. 1 Output is inverted. GPTM Timer A Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 The output Timer A ADC trigger is disabled. 1 The output Timer A ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see page 552). July 22, 2011 471 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 4 RTCEN R/W 0 Description GPTM RTC Enable The RTCEN values are defined as follows: Value Description 3:2 TAEVENT R/W 0x0 0 RTC counting is disabled. 1 RTC counting is enabled. GPTM Timer A Event Mode The TAEVENT values are defined as follows: Value Description 1 TASTALL R/W 0 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges GPTM Timer A Stall Enable The TASTALL values are defined as follows: Value Description 0 Timer A continues counting while the processor is halted by the debugger. 1 Timer A freezes counting while the processor is halted by the debugger. If the processor is executing normally, the TASTALL bit is ignored. 0 TAEN R/W 0 GPTM Timer A Enable The TAEN values are defined as follows: Value Description 0 Timer A is disabled. 1 Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 472 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables the corresponding interrupt, while clearing a bit disables it. GPTM Interrupt Mask (GPTMIMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 11 10 9 8 TBMIM CBEIM CBMIM TBTOIM R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TBMIM R/W 0 reserved RO 0 RO 0 RO 0 4 3 2 1 0 TAMIM RTCIM CAEIM CAMIM TATOIM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Mode Match Interrupt Mask The TBMIM values are defined as follows: Value Description 10 CBEIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Capture B Event Interrupt Mask The CBEIM values are defined as follows: Value Description 9 CBMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Capture B Match Interrupt Mask The CBMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. July 22, 2011 473 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 8 TBTOIM R/W 0 Description GPTM Timer B Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 TAMIM R/W 0 GPTM Timer A Mode Match Interrupt Mask The TAMIM values are defined as follows: Value Description 3 RTCIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 2 CAEIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Capture A Event Interrupt Mask The CAEIM values are defined as follows: Value Description 1 CAMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Capture A Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 TATOIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM Timer A Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 474 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 TBMRIS CBERIS RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 CBMRIS TBTORIS RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TBMRIS RO 0 RO 0 reserved RO 0 RO 0 RO 0 4 3 2 TAMRIS RTCRIS CAERIS RO 0 RO 0 RO 0 CAMRIS TATORIS RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Mode Match Raw Interrupt Value Description 1 The TBMIE bit is set in the GPTMTBMR register, and the match value in the GPTMTBMATCHR register has been reached when in the one-shot and periodic modes. 0 The match value has not been reached. This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register. 10 CBERIS RO 0 GPTM Capture B Event Raw Interrupt Value Description 1 The Capture B event has occurred. 0 The Capture B event has not occurred. This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register. 9 CBMRIS RO 0 GPTM Capture B Match Raw Interrupt Value Description 1 The Capture B match has occurred. 0 The Capture B match has not occurred. This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register. July 22, 2011 475 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 8 TBTORIS RO 0 Description GPTM Timer B Time-Out Raw Interrupt Value Description 1 Timer B has timed out. 0 Timer B has not timed out. This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 TAMRIS RO 0 GPTM Timer A Mode Match Raw Interrupt Value Description 1 The TAMIE bit is set in the GPTMTAMR register, and the match value in the GPTMTAMATCHR register has been reached when in the one-shot and periodic modes. 0 The match value has not been reached. This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register. 3 RTCRIS RO 0 GPTM RTC Raw Interrupt Value Description 1 The RTC event has occurred. 0 The RTC event has not occurred. This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR register. 2 CAERIS RO 0 GPTM Capture A Event Raw Interrupt Value Description 1 The Capture A event has occurred. 0 The Capture A event has not occurred. This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register. 1 CAMRIS RO 0 GPTM Capture A Match Raw Interrupt Value Description 1 The Capture A match has occurred. 0 The Capture A match has not occurred. This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register. 476 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 TATORIS RO 0 Description GPTM Timer A Time-Out Raw Interrupt Value Description 1 Timer A has timed out. 0 Timer A has not timed out. This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register. July 22, 2011 477 Texas Instruments-Production Data General-Purpose Timers Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 reserved Type Reset RO 0 RO 0 RO 0 11 TBMMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 CBEMIS CBMMIS TBTOMIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TBMMIS RO 0 RO 0 reserved RO 0 RO 0 RO 0 4 3 TAMMIS RTCMIS RO 0 RO 0 CAEMIS CAMMIS TATOMIS RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Mode Match Masked Interrupt Value Description 1 An unmasked Timer B Mode Match interrupt has occurred. 0 A Timer B Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register. 10 CBEMIS RO 0 GPTM Capture B Event Masked Interrupt Value Description 1 An unmasked Capture B event interrupt has occurred. 0 A Capture B event interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register. 478 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 9 CBMMIS RO 0 Description GPTM Capture B Match Masked Interrupt Value Description 1 An unmasked Capture B Match interrupt has occurred. 0 A Capture B Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register. 8 TBTOMIS RO 0 GPTM Timer B Time-Out Masked Interrupt Value Description 1 An unmasked Timer B Time-Out interrupt has occurred. 0 A Timer B Time-Out interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 TAMMIS RO 0 GPTM Timer A Mode Match Masked Interrupt Value Description 1 An unmasked Timer A Mode Match interrupt has occurred. 0 A Timer A Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register. 3 RTCMIS RO 0 GPTM RTC Masked Interrupt Value Description 1 An unmasked RTC event interrupt has occurred. 0 An RTC event interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR register. 2 CAEMIS RO 0 GPTM Capture A Event Masked Interrupt Value Description 1 An unmasked Capture A event interrupt has occurred. 0 A Capture A event interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register. July 22, 2011 479 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 1 CAMMIS RO 0 Description GPTM Capture A Match Masked Interrupt Value Description 1 An unmasked Capture A Match interrupt has occurred. 0 A Capture A Mode Match interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register. 0 TATOMIS RO 0 GPTM Timer A Time-Out Masked Interrupt Value Description 1 An unmasked Timer A Time-Out interrupt has occurred. 0 A Timer A Time-Out interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register. 480 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 TBMCINT CBECINT CBMCINT TBTOCINT RO 0 RO 0 W1C 0 W1C 0 W1C 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TBMCINT W1C 0 W1C 0 reserved RO 0 RO 0 TAMCINT RTCCINT CAECINT CAMCINT TATOCINT RO 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Mode Match Interrupt Clear Writing a 1 to this bit clears the TBMRIS bit in the GPTMRIS register and the TBMMIS bit in the GPTMMIS register. 10 CBECINT W1C 0 GPTM Capture B Event Interrupt Clear Writing a 1 to this bit clears the CBERIS bit in the GPTMRIS register and the CBEMIS bit in the GPTMMIS register. 9 CBMCINT W1C 0 GPTM Capture B Match Interrupt Clear Writing a 1 to this bit clears the CBMRIS bit in the GPTMRIS register and the CBMMIS bit in the GPTMMIS register. 8 TBTOCINT W1C 0 GPTM Timer B Time-Out Interrupt Clear Writing a 1 to this bit clears the TBTORIS bit in the GPTMRIS register and the TBTOMIS bit in the GPTMMIS register. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 TAMCINT W1C 0 GPTM Timer A Mode Match Interrupt Clear Writing a 1 to this bit clears the TAMRIS bit in the GPTMRIS register and the TAMMIS bit in the GPTMMIS register. 3 RTCCINT W1C 0 GPTM RTC Interrupt Clear Writing a 1 to this bit clears the RTCRIS bit in the GPTMRIS register and the RTCMIS bit in the GPTMMIS register. 2 CAECINT W1C 0 GPTM Capture A Event Interrupt Clear Writing a 1 to this bit clears the CAERIS bit in the GPTMRIS register and the CAEMIS bit in the GPTMMIS register. July 22, 2011 481 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset 1 CAMCINT W1C 0 Description GPTM Capture A Match Interrupt Clear Writing a 1 to this bit clears the CAMRIS bit in the GPTMRIS register and the CAMMIS bit in the GPTMMIS register. 0 TATOCINT W1C 0 GPTM Timer A Time-Out Raw Interrupt Writing a 1 to this bit clears the TATORIS bit in the GPTMRIS register and the TATOMIS bit in the GPTMMIS register. 482 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 9: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 When the timer is counting down, this register is used to load the starting count value into the timer. When the timer is counting up, this register sets the upper bound for the timeout event. When a GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Interval Load (GPTMTBILR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM Timer A Interval Load (GPTMTAILR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x028 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAILR Type Reset TAILR Type Reset Bit/Field Name Type 31:0 TAILR R/W Reset Description 0xFFFF.FFFF GPTM Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value of GPTMTAILR. July 22, 2011 483 Texas Instruments-Production Data General-Purpose Timers Register 10: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C When the timer is counting down, this register is used to load the starting count value into the timer. When the timer is counting up, this register sets the upper bound for the timeout event. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAILR register. Reads from this register return the current value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load value. Bits 31:16 are reserved in both cases. GPTM Timer B Interval Load (GPTMTBILR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TBILR Type Reset TBILR Type Reset Bit/Field Name Type 31:0 TBILR R/W Reset Description 0x0000.FFFF GPTM Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value of GPTMTBILR. When a GPTM is in 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 484 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 11: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. In PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When a GPTM is configured to one of the 32-bit modes, GPTMTAMATCHR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Match (GPTMTBMATCHR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBMATCHR. GPTM Timer A Match (GPTMTAMATCHR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x030 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TAMR Type Reset TAMR Type Reset Bit/Field Name Type 31:0 TAMR R/W Reset Description 0xFFFF.FFFF GPTM Timer A Match Register This value is compared to the GPTMTAR register to determine match events. July 22, 2011 485 Texas Instruments-Production Data General-Purpose Timers Register 12: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. In PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAMATCHR register. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. GPTM Timer B Match (GPTMTBMATCHR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TBMR Type Reset TBMR Type Reset Bit/Field Name Type 31:0 TBMR R/W Reset Description 0x0000.FFFF GPTM Timer B Match Register This value is compared to the GPTMTBR register to determine match events. 486 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. In Edge-Count mode, this register is the MSB of the 24-bit count value. GPTM Timer A Prescale (GPTMTAPR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TAPSR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000 7:0 TAPSR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer A Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 9-5 on page 454 for more details and an example. July 22, 2011 487 Texas Instruments-Production Data General-Purpose Timers Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. In Edge-Count mode, this register is the MSB of the 24-bit count value. GPTM Timer B Prescale (GPTMTBPR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TBPSR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000 7:0 TBPSR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Timer B Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 9-5 on page 454 for more details and an example. 488 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TAPSMR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000 7:0 TAPSMR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. July 22, 2011 489 Texas Instruments-Production Data General-Purpose Timers Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 TBPSMR RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000 7:0 TBPSMR R/W 0x00 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 490 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 17: GPTM Timer A (GPTMTAR), offset 0x048 This register shows the current value of the Timer A counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. Also in Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, GPTMTAR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B (GPTMTBR) register). In the16-bit Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the GPTMTAV register. GPTM Timer A (GPTMTAR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x048 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 TAR Type Reset TAR Type Reset Bit/Field Name Type 31:0 TAR RO Reset Description 0xFFFF.FFFF GPTM Timer A Register A read returns the current value of the GPTM Timer A Count Register, in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. July 22, 2011 491 Texas Instruments-Production Data General-Purpose Timers Register 18: GPTM Timer B (GPTMTBR), offset 0x04C This register shows the current value of the Timer B counter in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. Also in Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAR register. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. GPTM Timer B (GPTMTBR) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 TBR Type Reset TBR Type Reset Bit/Field Name Type 31:0 TBR RO Reset Description 0x0000.FFFF GPTM Timer B Register A read returns the current value of the GPTM Timer B Count Register, in all cases except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. 492 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 19: GPTM Timer A Value (GPTMTAV), offset 0x050 When read, this register shows the current, free-running value of Timer A in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. In Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, GPTMTAV appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Value (GPTMTBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. Note: The GPTMTAV register cannot be written in Edge-Count mode. GPTM Timer A Value (GPTMTAV) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x050 Type RW, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 7 6 5 4 3 2 1 0 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 TAV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 15 14 13 12 11 10 9 8 TAV Type Reset RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 Bit/Field Name Type 31:0 TAV RW RW 1 Reset RW 1 Description 0xFFFF.FFFF GPTM Timer A Value A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. July 22, 2011 493 Texas Instruments-Production Data General-Purpose Timers Register 20: GPTM Timer B Value (GPTMTBV), offset 0x054 When read, this register shows the current, free-running value of Timer B in all modes. Software can use this value to determine the time elapsed between an interrupt and the ISR entry. When written, the value written into this register is loaded into the GPTMTBR register on the next clock cycle. In Input Edge-Count mode, bits 23:16 contain the upper 8 bits of the count. When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAV register. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the current, free-running value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. GPTM Timer B Value (GPTMTBV) Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 Offset 0x054 Type RW, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 TBV Type Reset TBV Type Reset Bit/Field Name Type 31:0 TBV RW Reset Description 0x0000.FFFF GPTM Timer B Value A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. 494 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 10 Watchdog Timers A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The LM3S9L71 microcontroller has two Watchdog Timer Modules, one module is clocked by the system clock (Watchdog Timer 0) and the other is clocked by the PIOSC (Watchdog Timer 1). The two modules are identical except that WDT1 is in a different clock domain, and therefore requires synchronizers. As a result, WDT1 has a bit defined in the Watchdog Timer Control (WDTCTL) register to indicate when a write to a WDT1 register is complete. Software can use this bit to ensure that the previous access has completed before starting the next access. ® The Stellaris LM3S9L71 controller has two Watchdog Timer modules with the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. July 22, 2011 495 Texas Instruments-Production Data Watchdog Timers 10.1 Block Diagram Figure 10-1. WDT Module Block Diagram WDTLOAD Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt WDTRIS 32-Bit Down Counter WDTMIS 0x0000.0000 WDTLOCK System Clock/ PIOSC WDTTEST Comparator WDTVALUE Identification Registers 10.2 WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled by setting the RESEN bit in the WDTCTL register, the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. 496 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.2.1 Register Access Timing Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. Software must guarantee that this delay is inserted between back-to-back writes to WDT1 registers or between a write followed by a read to the registers. The timing for back-to-back reads from the WDT1 module has no restrictions. The WRC bit in the Watchdog Control (WDTCTL) register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. Software should poll WDTCTL for WRC=1 prior to accessing another register. Note that WDT0 does not have this restriction as it runs off the system clock. 10.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register, see page 264. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If WDT1, wait for the WRC bit in the WDTCTL register to be set. 3. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 4. If WDT1, wait for the WRC bit in the WDTCTL register to be set. 5. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 10.4 Register Map Table 10-1 on page 498 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address: ■ WDT0: 0x4000.0000 ■ WDT1: 0x4000.1000 Note that the Watchdog Timer module clock must be enabled before the registers can be programmed (see page 264). July 22, 2011 497 Texas Instruments-Production Data Watchdog Timers Table 10-1. Watchdog Timers Register Map Name Type Reset 0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 499 0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 500 0x008 WDTCTL R/W 0x0000.0000 (WDT0) 0x8000.0000 (WDT1) Watchdog Control 501 0x00C WDTICR WO - Watchdog Interrupt Clear 503 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 504 0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 505 0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 506 0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 507 0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 508 0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 509 0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 510 0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 511 0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 512 0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 513 0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 514 0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 515 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 516 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 517 0xFF8 WDTPCellID2 RO 0x0000.0006 Watchdog PrimeCell Identification 2 518 0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 519 10.5 Description See page Offset Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 498 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 WDTLOAD Type Reset WDTLOAD Type Reset Bit/Field Name Type 31:0 WDTLOAD R/W Reset R/W 1 Description 0xFFFF.FFFF Watchdog Load Value July 22, 2011 499 Texas Instruments-Production Data Watchdog Timers Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 15 14 13 12 11 10 9 8 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 23 22 21 20 19 18 17 16 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 WDTVALUE Type Reset WDTVALUE Type Reset Bit/Field Name Type 31:0 WDTVALUE RO Reset RO 1 Description 0xFFFF.FFFF Watchdog Value Current value of the 32-bit down counter. 500 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled by setting the INTEN bit, all subsequent writes to the INTEN bit are ignored. The only mechanism that can re-enable writes to this bit is a hardware reset. Important: Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. Software must guarantee that this delay is inserted between back-to-back writes to WDT1 registers or between a write followed by a read to the registers. The timing for back-to-back reads from the WDT1 module has no restrictions. The WRC bit in the Watchdog Control (WDTCTL) register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. Software should poll WDTCTL for WRC=1 prior to accessing another register. Note that WDT0 does not have this restriction as it runs off the system clock and therefore does not have a WRC bit. Watchdog Control (WDTCTL) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x008 Type R/W, reset 0x0000.0000 (WDT0) and 0x8000.0000 (WDT1) 31 30 29 28 27 26 25 24 22 21 20 19 18 17 16 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RESEN INTEN RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 WRC Type Reset 23 reserved reserved Type Reset Bit/Field Name Type Reset 31 WRC RO 1 Description Write Complete The WRC values are defined as follows: Value Description 0 A write access to one of the WDT1 registers is in progress. 1 A write access is not in progress, and WDT1 registers can be read or written. Note: 30:2 reserved RO 0x000.000 This bit is reserved for WDT0 and has a reset value of 0. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 501 Texas Instruments-Production Data Watchdog Timers Bit/Field Name Type Reset 1 RESEN R/W 0 Description Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 INTEN R/W 0 0 Disabled. 1 Enable the Watchdog module reset output. Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description 0 Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 1 Interrupt event enabled. Once enabled, all writes are ignored. 502 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x00C Type WO, reset 31 30 29 28 27 26 25 24 WO - WO - WO - WO - WO - WO - WO - WO - 15 14 13 12 11 10 9 8 WO - WO - WO - WO - WO - WO - WO - WO - 23 22 21 20 19 18 17 16 WO - WO - WO - WO - WO - WO - WO - WO - 7 6 5 4 3 2 1 0 WO - WO - WO - WO - WO - WO - WO - WDTINTCLR Type Reset WDTINTCLR Type Reset Bit/Field Name Type Reset 31:0 WDTINTCLR WO - WO - Description Watchdog Interrupt Clear July 22, 2011 503 Texas Instruments-Production Data Watchdog Timers Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 WDTRIS RO 0 RO 0 WDTRIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Raw Interrupt Status Value Description 1 A watchdog time-out event has occurred. 0 The watchdog has not timed out. 504 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 WDTMIS RO 0 RO 0 WDTMIS RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Masked Interrupt Status Value Description 1 A watchdog time-out event has been signalled to the interrupt controller. 0 The watchdog has not timed out or the watchdog timer interrupt is masked. July 22, 2011 505 Texas Instruments-Production Data Watchdog Timers Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STALL Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 STALL R/W 0 R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Stall Enable Value Description 7:0 reserved RO 0x00 1 If the microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. 0 The watchdog timer continues counting if the microcontroller is stopped with a debugger. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 506 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 WDTLOCK Type Reset WDTLOCK Type Reset Bit/Field Name Type 31:0 WDTLOCK R/W Reset R/W 0 Description 0x0000.0000 Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked July 22, 2011 507 Texas Instruments-Production Data Watchdog Timers Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register [7:0] 508 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID5 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID5 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register [15:8] July 22, 2011 509 Texas Instruments-Production Data Watchdog Timers Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID6 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID6 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register [23:16] 510 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID7 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID7 RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register [31:24] July 22, 2011 511 Texas Instruments-Production Data Watchdog Timers Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x05 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register [7:0] 512 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID1 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0x18 RO 0 RO 0 RO 0 RO 0 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register [15:8] July 22, 2011 513 Texas Instruments-Production Data Watchdog Timers Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID2 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x18 RO 0 RO 0 RO 0 RO 0 RO 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register [23:16] 514 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 PID3 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x01 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register [31:24] July 22, 2011 515 Texas Instruments-Production Data Watchdog Timers Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register [7:0] 516 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register [15:8] July 22, 2011 517 Texas Instruments-Production Data Watchdog Timers Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFF8 Type RO, reset 0x0000.0006 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID2 RO 0x06 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register [23:16] 518 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID3 RO 0xB1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register [31:24] July 22, 2011 519 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) 11 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. Two identical converter modules are included, which share 16 input channels. ® The Stellaris ADC module features 10-bit conversion resolution and supports 16 input channels, plus an internal temperature sensor. Each ADC module contains four programmable sequencers allowing the sampling of multiple analog input sources without controller intervention. Each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. A digital comparator function is included which allows the conversion value to be diverted to a digital comparator module. Each ADC module provides eight digital comparators. Each digital comparator evaluates the ADC conversion value against its two user-defined values to determine the operational range of the signal. The trigger source for ADC0 and ADC1 may be independent or the two ADC modules may operate from the same trigger source and operate on the same or different inputs. A phase shifter can delay the start of sampling by a specified phase angle. When using both ADC modules, it is possible to configure the converters to start the conversions coincidentally or within a relative phase from each other, see “Sample Phase Control” on page 526. The Stellaris LM3S9L71 microcontroller provides two ADC modules with each having the following features: ■ 16 shared analog input channels ■ Single-ended and differential-input configurations ■ On-chip internal temperature sensor ■ Maximum sample rate of one million samples/second ■ Optional phase shift in sample time programmable from 22.5º to 337.5º ■ Four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – PWM – GPIO ■ Hardware averaging of up to 64 samples ■ Digital comparison unit providing eight digital comparators ■ Converter uses an internal 3-V reference or an external reference ■ Power and ground for the analog circuitry is separate from the digital power and ground 520 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each sample sequencer – ADC module uses burst requests for DMA 11.1 Block Diagram The Stellaris microcontroller contains two identical Analog-to-Digital Converter modules. These two modules, ADC0 and ADC1, share the same 16 analog input channels. Each ADC module operates independently and can therefore execute different sample sequences, sample any of the analog input channels at any time, and generate different interrupts and triggers. Figure 11-1 on page 521 shows how the two modules are connected to analog inputs and the system bus. Figure 11-1. Implementation of Two ADC Blocks Triggers ADC 0 Input Channels Interrupts/ Triggers ADC 1 Interrupts/ Triggers Figure 11-2 on page 522 provides details on the internal configuration of the ADC controls and data registers. July 22, 2011 521 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 11-2. ADC Module Block Diagram External Voltage Ref (VREFA) Internal Voltage Ref Trigger Events Comparator GPIO (PB4) Timer PWM SS3 Comparator GPIO (PB4) Timer PWM Sample Sequencer 0 Control/Status ADCSSMUX0 ADCACTSS ADCSSCTL0 ADCOSTAT ADCSSFSTAT0 Analog-to-Digital Converter Analog Inputs (AINx) ADCUSTAT SS2 Comparator GPIO (PB4) Timer PWM ADCSSPRI ADCCTL Sample Sequencer 1 ADCSPC ADCSSMUX1 ADCSSCTL1 SS1 Hardware Averager ADCSSFSTAT1 ADCSAC Sample Sequencer 2 Comparator GPIO (PB4) Timer PWM SS0 ADCSSMUX2 FIFO Block ADCSSCTL2 ADCSSOPn ADCSSFSTAT2 ADCEMUX ADCPSSI SS0 Interrupt SS1 Interrupt SS2 Interrupt SS3 Interrupt Interrupt Control Sample Sequencer 3 ADCIM ADCSSMUX3 ADCRIS ADCSSCTL3 ADCISC ADCSSFSTAT3 Digital Comparator ADCSSFIFO0 ADCSSDCn ADCSSFIFO1 ADCDCCTLn ADCSSFIFO2 ADCDCCMPn ADCSSFIFO3 ADCDCRIC ADCDCISC DC Interrupts PWM Trigger 11.2 Signal Description The following table lists the external signals of the ADC module and describes the function of each. The ADC signals are analog functions for some GPIO signals. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the ADC signals. The AINx and VREFA analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. Table 11-1. Signals for ADC (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description AIN0 1 PE7 I Analog Analog-to-digital converter input 0. AIN1 2 PE6 I Analog Analog-to-digital converter input 1. AIN2 5 PE5 I Analog Analog-to-digital converter input 2. AIN3 6 PE4 I Analog Analog-to-digital converter input 3. AIN4 100 PD7 I Analog Analog-to-digital converter input 4. AIN5 99 PD6 I Analog Analog-to-digital converter input 5. AIN6 98 PD5 I Analog Analog-to-digital converter input 6. AIN7 97 PD4 I Analog Analog-to-digital converter input 7. AIN8 96 PE3 I Analog Analog-to-digital converter input 8. AIN9 95 PE2 I Analog Analog-to-digital converter input 9. 522 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 11-1. Signals for ADC (100LQFP) (continued) Pin Name AIN10 Pin Number Pin Mux / Pin Assignment 92 a Pin Type Buffer Type Description PB4 I Analog Analog-to-digital converter input 10. AIN11 91 PB5 I Analog Analog-to-digital converter input 11. AIN12 13 PD3 I Analog Analog-to-digital converter input 12. AIN13 12 PD2 I Analog Analog-to-digital converter input 13. AIN14 11 PD1 I Analog Analog-to-digital converter input 14. AIN15 10 PD0 I Analog Analog-to-digital converter input 15. VREFA 90 PB6 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 1023. The VREFA input is limited to the range specified in Table 25-18 on page 1200. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 11-2. Signals for ADC (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description AIN0 B1 PE7 I Analog Analog-to-digital converter input 0. AIN1 A1 PE6 I Analog Analog-to-digital converter input 1. AIN2 B3 PE5 I Analog Analog-to-digital converter input 2. AIN3 B2 PE4 I Analog Analog-to-digital converter input 3. AIN4 A2 PD7 I Analog Analog-to-digital converter input 4. AIN5 A3 PD6 I Analog Analog-to-digital converter input 5. AIN6 C6 PD5 I Analog Analog-to-digital converter input 6. AIN7 B5 PD4 I Analog Analog-to-digital converter input 7. AIN8 B4 PE3 I Analog Analog-to-digital converter input 8. AIN9 A4 PE2 I Analog Analog-to-digital converter input 9. AIN10 A6 PB4 I Analog Analog-to-digital converter input 10. AIN11 B7 PB5 I Analog Analog-to-digital converter input 11. AIN12 H1 PD3 I Analog Analog-to-digital converter input 12. AIN13 H2 PD2 I Analog Analog-to-digital converter input 13. AIN14 G2 PD1 I Analog Analog-to-digital converter input 14. AIN15 G1 PD0 I Analog Analog-to-digital converter input 15. VREFA A7 PB6 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 1023. The VREFA input is limited to the range specified in Table 25-18 on page 1200. a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 22, 2011 523 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) 11.3 Functional Description The Stellaris ADC collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approaches found on many ADC modules. Each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC to collect data from multiple input sources without having to be re-configured or serviced by the processor. The programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. In addition, the μDMA can be used to more efficiently move data from the sample sequencers without CPU intervention. 11.3.1 Sample Sequencers The sampling control and data capture is handled by the sample sequencers. All of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the FIFO. Table 11-3 on page 524 shows the maximum number of samples that each sequencer can capture and its corresponding FIFO depth. Each sample that is captured is stored in the FIFO. In this implementation, each FIFO entry is a 32-bit word, with the lower 10 bits containing the conversion result. Table 11-3. Samples and FIFO Depth of Sequencers Sequencer Number of Samples Depth of FIFO SS3 1 1 SS2 4 4 SS1 4 4 SS0 8 8 For a given sample sequence, each sample is defined by bit fields in the ADC Sample Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn fields select the input pin, while the ADCSSCTLn fields contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. Sample sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register and should be configured before being enabled. Sampling is then initiated by setting the SSn bit in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. In addition, sample sequences may be initiated on multiple ADC modules simultaneously using the GSYNC and SYNCWAIT bits in the ADCPSSI register during the configuration of each ADC module. For more information on using these bits, refer to page 562. When configuring a sample sequence, multiple uses of the same input pin within the same sequence are allowed. In the ADCSSCTLn register, the IEn bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete execution of the sample sequence after the fifth sample. After a sample sequence completes execution, the result data can be retrieved from the ADC Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers that read a single address to "pop" result data. For software debug purposes, the positions of the FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn) registers along with FULL and EMPTY status flags. If a write is attempted when the FIFO is full, the write does not occur and an overflow condition is indicated. Overflow and underflow conditions are monitored using the ADCOSTAT and ADCUSTAT registers. 524 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 11.3.2 Module Control Outside of the sample sequencers, the remainder of the control logic is responsible for tasks such as: ■ Interrupt generation ■ DMA operation ■ Sequence prioritization ■ Trigger configuration ■ Comparator configuration ■ External voltage reference ■ Sample phase control Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is configured for 16-MHz operation automatically by hardware when the system XTAL is selected. 11.3.2.1 Interrupts The register configurations of the sample sequencers and digital comparators dictate which events generate raw interrupts, but do not have control over whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signals are controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of the various interrupt signals; and the ADC Interrupt Status and Clear (ADCISC) register, which shows active interrupts that are enabled by the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the corresponding IN bit in ADCISC. Digital comparator interrupts are cleared by writing a 1 to the ADC Digital Comparator Interrupt Status and Clear (ADCDCISC) register. 11.3.2.2 DMA Operation DMA may be used to increase efficiency by allowing each sample sequencer to operate independently and transfer data without processor intervention or reconfiguration. The ADC module provides a request signal from each sample sequencer to the associated dedicated channel of the μDMA controller. The ADC does not support single transfer requests. A burst transfer request is asserted when the interrupt bit for the sample sequence is set (IE bit in the ADCSSCTLn register is set). The arbitration size of the μDMA transfer must be a power of 2, and the associated IE bits in the ADDSSCTLn register must be set. For example, if the μDMA channel of SS0 has an arbitration size of four, the IE3 bit (4th sample) and the IE7 bit (8th sample) must be set. Thus the μDMA request occurs every time 4 samples have been acquired. No other special steps are needed to enable the ADC module for μDMA operation. Refer to the “Micro Direct Memory Access (μDMA)” on page 333 for more details about programming the μDMA controller. 11.3.2.3 Prioritization When sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample July 22, 2011 525 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) sequencer units with the same priority do not provide consistent results, so software must ensure that all active sample sequencer units have a unique priority value. 11.3.2.4 Sampling Events Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select (ADCEMUX) register. Trigger sources include processor (default), analog comparators, an external signal on GPIO PB4, a GP Timer, a PWM generator, and continuous sampling. The processor triggers sampling by setting the SSx bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. Care must be taken when using the continuous sampling trigger. If a sequencer's priority is too high, it is possible to starve other lower priority sequencers. Generally, a sample sequencer using continuous sampling should be set to the lowest priority. Continuous sampling can be used with a digital comparator to cause an interrupt when a particular voltage is seen on an input. 11.3.2.5 Sample Phase Control The trigger source for ADC0 and ADC1 may be independent or the two ADC modules may operate from the same trigger source and operate on the same or different inputs. If the converters are running at the same sample rate, they may be configured to start the conversions coincidentally or with one of 15 different discrete phases relative to each other. The sample time can be delayed from the standard sampling time in 22.5° increments up to 337.5º using the ADC Sample Phase Control (ADCSPC) register. Figure 11-3 on page 526 shows an example of various phase relationships at a 1 Msps rate. Figure 11-3. ADC Sample Phases 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ADC Sample Clock PHASE 0x0 (0.0°) PHASE 0x1 (22.5°) . . . . . . . . . . . . PHASE 0xE (315.0°) PHASE 0xF (337.5°) This feature can be used to double the sampling rate of an input. Both ADC module 0 and ADC module 1 can be programmed to sample the same input. ADC module 0 could sample at the standard position (the PHASE field in the ADCSPC register is 0x0). ADC module 1 can be configured to sample at 180 (PHASE = 0x8). The two modules can be be synchronized using the GSYNC and SYNCWAIT bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. Software could then combine the results from the two modules to create a sample rate of two million samples/second at 16 MHz as shown in Figure 11-4 on page 527. 526 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 11-4. Doubling the ADC Sample Rate 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ADC Sample Clock GSYNC ADC 0 PHASE 0x0 (0.0°) ADC 1 PHASE 0x8 (180.0°) Using the ADCSPC register, ADC0 and ADC1 may provide a number of interesting applications: ■ Coincident sampling of different signals. The sample sequence steps run coincidently in both converters. – ADC Module 0, ADCSPC = 0x0, sampling AIN0 – ADC Module 1, ADCSPC = 0x0, sampling AIN1 ■ Skewed sampling of the same signal. The sample sequence steps are 1/2 of an ADC clock (500 µs for a 1Ms/s ADC) out of phase with each other. This configuration doubles the conversion bandwidth of a single input when software combines the results as shown in Figure 11-5 on page 527. – ADC Module 0, ADCSPC = 0x0, sampling AIN0 – ADC Module 1, ADCSPC = 0x8, sampling AIN0 Figure 11-5. Skewed Sampling ADC0 ADC1 11.3.3 S1 S2 S1 S3 S2 S4 S3 S5 S4 S6 S5 S7 S6 S8 S7 S8 Hardware Sample Averaging Circuit Higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the July 22, 2011 527 Texas Instruments-Production Data 18 Analog-to-Digital Converter (ADC) number of samples in the averaging calculation. For example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. By default the averaging circuit is off, and all data from the converter passes through to the sequencer FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC) register (see page 564). A single averaging circuit has been implemented, thus all input channels receive the same amount of averaging whether they are single-ended or differential. Figure 11-6 on page 528 shows an example in which the ADCSAC register is set to 0x2 for 4x hardware oversampling and the IE1 bit is set for the sample sequence, resulting in an interrupt after the second averaged value is stored in the FIFO. Figure 11-6. Sample Averaging Example A+B+C+D 4 A+B+C+D 4 INT 11.3.4 Analog-to-Digital Converter The Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR) architecture to deliver a 10-bit, low-power, high-precision conversion value. The successive-approximation algorithm uses a current mode D/A converter to achieve lower settling time, resulting in higher conversion speeds for the A/D converter. In addition, built-in sample-and-hold circuitry with offset-calibration circuitry improves conversion accuracy. The ADC must be run from the PLL or a 14- to 18-MHz clock source. The ADC operates from both the 3.3-V analog and 1.2-V digital power supplies. The ADC clock can be configured to reduce power consumption when ADC conversions are not required (see “System Control” on page 206). The analog inputs are connected to the ADC through custom pads and specially balanced input paths to minimize the distortion on the inputs. Detailed information on the ADC power supplies and analog inputs can be found in “Analog-to-Digital Converter (ADC)” on page 1199. 528 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 11.3.4.1 Internal Voltage Reference The band-gap circuitry generates an internal 3.0 V reference that can be used by the ADC to produce a conversion value from the selected analog input. The range of this conversion value is from 0x000 to 0x3FF. This configuration results in a resolution of approximately 2.9 mV per ADC code. While the analog input pads can handle voltages beyond this range, the ADC conversions saturate in under-voltage and over-voltage cases. Figure 11-7 on page 529 shows the ADC conversion function of the analog inputs. Figure 11-7. Internal Voltage Conversion Result 0x3FF 0x2FF 0x1FF 0x0FF 0.00 V 0.75 V 1.50 V 2.25 V 3.00 V VIN - Input Saturation 11.3.4.2 External Voltage Reference The ADC can use an external voltage reference to produce the conversion value from the selected analog input by setting the VREF bit in the ADC Control (ADCCTL) register. The VREF bit specifies whether to use the internal or external reference. While the range of the conversion value remains the same (0x000 to 0x3FF), the analog voltage associated with the 0x3FF value corresponds to the value of the voltage when using the 3.0-V setting and three times the voltage when using the 1.0-V setting, resulting in a smaller voltage resolution per ADC code. Ground is always used as the reference level for the minimum conversion value. Analog input voltages above the external voltage reference saturate to 0x3FF while those below 0.0 V continue to saturate at 0x000. The VREFA specification defines the useful range for the external voltage reference, see Table 25-18 on page 1200. Care must be taken to supply a reference voltage of acceptable quality. Figure 11-8 on page 530 shows the ADC conversion function of the analog inputs when using an external voltage reference. The external voltage reference can be more accurate than the internal reference by using a high-precision source or trimming the source. July 22, 2011 529 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 11-8. External Voltage Conversion Result 0x3FF 0x2FF 0x1FF 0x0FF 0.00 V ½ VREFA VREFA VDD VIN - Input Saturation 11.3.5 Differential Sampling In addition to traditional single-ended sampling, the ADC module supports differential sampling of two analog input channels. To enable differential sampling, software must set the Dn bit in the ADCSSCTL0n register in a step's configuration nibble. When a sequence step is configured for differential sampling, the input pair to sample must be configured in the ADCSSMUXn register. Differential pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see Table 11-4 on page 530). The ADC does not support other differential pairings such as analog input 0 with analog input 3. Table 11-4. Differential Sampling Pairs Differential Pair Analog Inputs 0 0 and 1 1 2 and 3 2 4 and 5 3 6 and 7 4 8 and 9 5 10 and 11 6 12 and 13 7 14 and 15 The voltage sampled in differential mode is the difference between the odd and even channels: ∆V (differential voltage) = VIN_EVEN (even channel) – VIN_ODD (odd channel), therefore: ■ If ∆V = 0, then the conversion result = 0x1FF 530 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ If ∆V > 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF) ■ If ∆V < 0, then the conversion result < 0x1FF (range is 0–0x1FF) The differential pairs assign polarities to the analog inputs: the even-numbered input is always positive, and the odd-numbered input is always negative. In order for a valid conversion result to appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped, meaning it appears as either 3 V or 0 V , respectively, to the ADC. Figure 11-9 on page 531 shows an example of the negative input centered at 1.5 V. In this configuration, the differential range spans from -1.5 V to 1.5 V. Figure 11-10 on page 532 shows an example where the negative input is centered at 0.75 V, meaning inputs on the positive input saturate past a differential voltage of -0.75 V because the input voltage is less than 0 V. Figure 11-11 on page 532 shows an example of the negative input centered at 2.25 V, where inputs on the positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater than 3 V. Figure 11-9. Differential Sampling Range, VIN_ODD = 1.5 V 0x3FF 0x1FF 0V -1.5 V 1.5 V 0V 3.0 V VIN_EVEN 1.5 V DV VIN_ODD = 1.5 V - Input Saturation July 22, 2011 531 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 11-10. Differential Sampling Range, VIN_ODD = 0.75 V ADC Conversion Result 0x3FF 0x1FF 0x0FF -1.5 V 0V -0.75 V +0.75 V +2.25 V +1.5 V VIN_EVEN DV - Input Saturation Figure 11-11. Differential Sampling Range, VIN_ODD = 2.25 V 0x3FF 0x2FF 0x1FF 0.75 V -1.5 V 2.25 V 3.0 V 0.75 V 1.5 V VIN_EVEN DV - Input Saturation 532 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 11.3.6 Internal Temperature Sensor The temperature sensor's primary purpose is to notify the system that the internal temperature is too high or low for reliable operation. The temperature sensor does not have a separate enable, because it also contains the bandgap reference and must always be enabled. The reference is supplied to other analog modules; not just the ADC. The internal temperature sensor provides an analog temperature reading as well as a reference voltage. This reference voltage, SENSO, is given by the following equation: SENSO = 2.7 - ((T + 55) / 75) This relation is shown in Figure 11-12 on page 533. Figure 11-12. Internal Temperature Sensor Characteristic Sensor = 2.7 V – (T+55) 75 Sensor 2.7 V 1.633 V 0.3 V -55° C 25° C 125° C Temp The temperature sensor reading can be sampled in a sample sequence by setting the TSn bit in the ADCSSCTLn register. The temperature reading from the temperature sensor can also be given as a function of the ADC value. The following formula calculates temperature (in ℃) based on the ADC reading: Temperature = 147.5 - ((225 × ADC) / 1023) 11.3.7 Digital Comparator Unit An ADC is commonly used to sample an external signal and to monitor its value to ensure that it remains in a given range. To automate this monitoring procedure and reduce the amount of processor overhead that is required, each module provides eight digital comparators. Conversions from the ADC that are sent to the digital comparators are compared against the user programmable limits July 22, 2011 533 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) in the ADC Digital Comparator Range (ADCDCCMPn) registers. If the observed signal moves out of the acceptable range, a processor interrupt can be generated and/or a trigger can be sent to the PWM module. The digital comparators four operational modes (Once, Always, Hysteresis Once, Hysteresis Always) can be applied to three separate regions (low band, mid band, high band) as defined by the user. 11.3.7.1 Output Functions ADC conversions can either be stored in the ADC Sample Sequence FIFOs or compared using the digital comparator resources as defined by the SnDCOP bits in the ADC Sample Sequence n Operation (ADCSSOPn) register. These selected ADC conversions are used by their respective digital comparator to monitor the external signal. Each comparator has two possible output functions: processor interrupts and triggers. Each function has its own state machine to track the monitored signal. Even though the interrupt and trigger functions can be enabled individually or both at the same time, the same conversion data is used by each function to determine if the right conditions have been met to assert the associated output. Interrupts The digital comparator interrupt function is enabled by setting the CIE bit in the ADC Digital Comparator Control (ADCDCCTLn) register. This bit enables the interrupt function state machine to start monitoring the incoming ADC conversions. When the appropriate set of conditions is met, and the DCONSSx bit is set in the ADCIM register, an interrupt is sent to the interrupt controller. Triggers The digital comparator trigger function is enabled by setting the CTE bit in the ADCDCCTLn register. This bit enables the trigger function state machine to start monitoring the incoming ADC conversions. When the appropriate set of conditions is met, the corresponding digital comparator trigger to the PWM module is asserted 11.3.7.2 Operational Modes Four operational modes are provided to support a broad range of applications and multiple possible signaling requirements: Always, Once, Hysteresis Always, and Hysteresis Once. The operational mode is selected using the CIM or CTM field in the ADCDCCTLn register. Always Mode In the Always operational mode, the associated interrupt or trigger is asserted whenever the ADC conversion value meets its comparison criteria. The result is a string of assertions on the interrupt or trigger while the conversions are within the appropriate range. Once Mode In the Once operational mode, the associated interrupt or trigger is asserted whenever the ADC conversion value meets its comparison criteria, and the previous ADC conversion value did not. The result is a single assertion of the interrupt or trigger when the conversions are within the appropriate range. Hysteresis-Always Mode The Hysteresis-Always operational mode can only be used in conjunction with the low-band or high-band regions because the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. In the Hysteresis-Always mode, the associated interrupt or trigger 534 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller is asserted in the following cases: 1) the ADC conversion value meets its comparison criteria or 2) a previous ADC conversion value has met the comparison criteria, and the hysteresis condition has not been cleared by entering the opposite region. The result is a string of assertions on the interrupt or trigger that continue until the opposite region is entered. Hysteresis-Once Mode The Hysteresis-Once operational mode can only be used in conjunction with the low-band or high-band regions because the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. In the Hysteresis-Once mode, the associated interrupt or trigger is asserted only when the ADC conversion value meets its comparison criteria, the hysteresis condition is clear, and the previous ADC conversion did not meet the comparison criteria. The result is a single assertion on the interrupt or trigger. 11.3.7.3 Function Ranges The two comparison values, COMP0 and COMP1, in the ADC Digital Comparator Range (ADCDCCMPn) register effectively break the conversion area into three distinct regions. These regions are referred to as the low-band (less than or equal to COMP0), mid-band (greater than COMP0 but less than or equal to COMP1), and high-band (greater than COMP1) regions. COMP0 and COMP1 may be programmed to the same value, effectively creating two regions, but COMP1 must always be greater than or equal to the value of COMP0. A COMP1 value that is less than COMP0 generates unpredictable results. Low-Band Operation To operate in the low-band region, either the CIC field or the CTC field in the ADCDCCTLn register must be programmed to 0x0. This setting causes interrupts or triggers to be generated in the low-band region as defined by the programmed operational mode. An example of the state of the interrupt/trigger signal in the low-band region for each of the operational modes is shown in Figure 11-13 on page 536. Note that a "0" in a column following the operational mode name (Always, Once, Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. July 22, 2011 535 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 11-13. Low-Band Operation (CIC=0x0 and/or CTC=0x0) COMP1 COMP0 Always – 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 Once – 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 Hysteresis Always – 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 Hysteresis Once – 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 Mid-Band Operation To operate in the mid-band region, either the CIC field or the CTC field in the ADCDCCTLn register must be programmed to 0x1. This setting causes interrupts or triggers to be generated in the mid-band region according the operation mode. Only the Always and Once operational modes are available in the mid-band region. An example of the state of the interrupt/trigger signal in the mid-band region for each of the allowed operational modes is shown in Figure 11-14 on page 537. Note that a "0" in a column following the operational mode name (Always or Once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. 536 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 11-14. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) COMP1 COMP0 Always – 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 Once – 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 Hysteresis Always – - - - - - - - - - - - - - - - - Hysteresis Once – - - - - - - - - - - - - - - - - High-Band Operation To operate in the high-band region, either the CIC field or the CTC field in the ADCDCCTLn register must be programmed to 0x3. This setting causes interrupts or triggers to be generated in the high-band region according the operation mode. An example of the state of the interrupt/trigger signal in the high-band region for each of the allowed operational modes is shown in Figure 11-15 on page 538. Note that a "0" in a column following the operational mode name (Always, Once, Hysteresis Always, and Hysteresis Once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. July 22, 2011 537 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 11-15. High-Band Operation (CIC=0x3 and/or CTC=0x3) COMP1 COMP0 11.4 Always – 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 Once – 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 Hysteresis Always – 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 Hysteresis Once – 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 Initialization and Configuration In order for the ADC module to be used, the PLL must be enabled and programmed to a supported crystal frequency in the RCC register (see page 221). Using unsupported frequencies can cause faulty operation in the ADC module. 11.4.1 Module Initialization Initialization of the ADC module is a simple process with very few steps: enabling the clock to the ADC, disabling the analog isolation circuit associated with all inputs that are to be used, and reconfiguring the sample sequencer priorities (if needed). The initialization sequence for the ADC is as follows: 1. Enable the ADC clock by using the RCGC0 register (see page 264). 2. Enable the clock to the appropriate GPIO modules via the RCGC2 register (see page 281). To find out which GPIO ports to enable, refer to “Signal Description” on page 522. 3. Set the GPIO AFSEL bits for the ADC input pins (see page 416). To determine which GPIOs to configure, see Table 23-4 on page 1137. 4. Configure the AINx and VREFA signals to be analog inputs by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register (see page 427). 5. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to the appropriate bits of the GPIOAMSEL register (see page 432) in the associated GPIO block. 538 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 6. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI register. The default configuration has Sample Sequencer 0 with the highest priority and Sample Sequencer 3 as the lowest priority. 11.4.2 Sample Sequencer Configuration Configuration of the sample sequencers is slightly more complex than the module initialization because each sample sequencer is completely programmable. The configuration for each sample sequencer should be as follows: 1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the ADCACTSS register. Programming of the sample sequencers is allowed without having them enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. Configure the trigger event for the sample sequencer in the ADCEMUX register. 3. For each sample in the sample sequence, configure the corresponding input source in the ADCSSMUXn register. 4. For each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. 5. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register. 6. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS register. 11.5 Register Map Table 11-5 on page 539 lists the ADC registers. The offset listed is a hexadecimal increment to the register’s address, relative to that ADC module's base address of: ■ ADC0: 0x4003.8000 ■ ADC1: 0x4003.9000 Note that the ADC module clock must be enabled before the registers can be programmed (see page 264). There must be a delay of 3 system clocks after the ADC module clock is enabled before any ADC module registers are accessed. Table 11-5. ADC Register Map Description See page Offset Name Type Reset 0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 542 0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 543 0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 545 0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 547 0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 550 0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 552 July 22, 2011 539 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Table 11-5. ADC Register Map (continued) Offset Name 0x018 See page Type Reset Description ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 557 0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 558 0x024 ADCSPC R/W 0x0000.0000 ADC Sample Phase Control 560 0x028 ADCPSSI R/W - ADC Processor Sample Sequence Initiate 562 0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 564 0x034 ADCDCISC R/W1C 0x0000.0000 ADC Digital Comparator Interrupt Status and Clear 565 0x038 ADCCTL R/W 0x0000.0000 ADC Control 567 0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 568 0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 570 0x048 ADCSSFIFO0 RO - ADC Sample Sequence Result FIFO 0 573 0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 574 0x050 ADCSSOP0 R/W 0x0000.0000 ADC Sample Sequence 0 Operation 576 0x054 ADCSSDC0 R/W 0x0000.0000 ADC Sample Sequence 0 Digital Comparator Select 578 0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 580 0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 581 0x068 ADCSSFIFO1 RO - ADC Sample Sequence Result FIFO 1 573 0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 574 0x070 ADCSSOP1 R/W 0x0000.0000 ADC Sample Sequence 1 Operation 583 0x074 ADCSSDC1 R/W 0x0000.0000 ADC Sample Sequence 1 Digital Comparator Select 584 0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 580 0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 581 0x088 ADCSSFIFO2 RO - ADC Sample Sequence Result FIFO 2 573 0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 574 0x090 ADCSSOP2 R/W 0x0000.0000 ADC Sample Sequence 2 Operation 583 0x094 ADCSSDC2 R/W 0x0000.0000 ADC Sample Sequence 2 Digital Comparator Select 584 0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 586 0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 587 0x0A8 ADCSSFIFO3 RO - ADC Sample Sequence Result FIFO 3 573 0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 574 0x0B0 ADCSSOP3 R/W 0x0000.0000 ADC Sample Sequence 3 Operation 588 0x0B4 ADCSSDC3 R/W 0x0000.0000 ADC Sample Sequence 3 Digital Comparator Select 589 0xD00 ADCDCRIC R/W 0x0000.0000 ADC Digital Comparator Reset Initial Conditions 590 540 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 11-5. ADC Register Map (continued) Name Type Reset 0xE00 ADCDCCTL0 R/W 0x0000.0000 ADC Digital Comparator Control 0 595 0xE04 ADCDCCTL1 R/W 0x0000.0000 ADC Digital Comparator Control 1 595 0xE08 ADCDCCTL2 R/W 0x0000.0000 ADC Digital Comparator Control 2 595 0xE0C ADCDCCTL3 R/W 0x0000.0000 ADC Digital Comparator Control 3 595 0xE10 ADCDCCTL4 R/W 0x0000.0000 ADC Digital Comparator Control 4 595 0xE14 ADCDCCTL5 R/W 0x0000.0000 ADC Digital Comparator Control 5 595 0xE18 ADCDCCTL6 R/W 0x0000.0000 ADC Digital Comparator Control 6 595 0xE1C ADCDCCTL7 R/W 0x0000.0000 ADC Digital Comparator Control 7 595 0xE40 ADCDCCMP0 R/W 0x0000.0000 ADC Digital Comparator Range 0 598 0xE44 ADCDCCMP1 R/W 0x0000.0000 ADC Digital Comparator Range 1 598 0xE48 ADCDCCMP2 R/W 0x0000.0000 ADC Digital Comparator Range 2 598 0xE4C ADCDCCMP3 R/W 0x0000.0000 ADC Digital Comparator Range 3 598 0xE50 ADCDCCMP4 R/W 0x0000.0000 ADC Digital Comparator Range 4 598 0xE54 ADCDCCMP5 R/W 0x0000.0000 ADC Digital Comparator Range 5 598 0xE58 ADCDCCMP6 R/W 0x0000.0000 ADC Digital Comparator Range 6 598 0xE5C ADCDCCMP7 R/W 0x0000.0000 ADC Digital Comparator Range 7 598 11.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the ADC registers, in numerical order by address offset. July 22, 2011 541 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the sample sequencers. Each sample sequencer can be enabled or disabled independently. ADC Active Sample Sequencer (ADCACTSS) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 ASEN3 ASEN2 ASEN1 ASEN0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 ASEN3 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC SS3 Enable Value Description 2 ASEN2 R/W 0 1 Sample Sequencer 3 is enabled. 0 Sample Sequencer 3 is disabled. ADC SS2 Enable Value Description 1 ASEN1 R/W 0 1 Sample Sequencer 2 is enabled. 0 Sample Sequencer 2 is disabled. ADC SS1 Enable Value Description 0 ASEN0 R/W 0 1 Sample Sequencer 1 is enabled. 0 Sample Sequencer 1 is disabled. ADC SS0 Enable Value Description 1 Sample Sequencer 0 is enabled. 0 Sample Sequencer 0 is disabled. 542 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each sample sequencer. These bits may be polled by software to look for interrupt conditions without sending the interrupts to the interrupt controller. ADC Raw Interrupt Status (ADCRIS) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 1 0 INR3 INR2 INR1 INR0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset INRDC reserved Type Reset 16 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 INRDC RO 0 Digital Comparator Raw Interrupt Status Value Description 1 At least one bit in the ADCDCISC register is set, meaning that a digital comparator interrupt has occurred. 0 All bits in the ADCDCISC register are clear. 15:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 INR3 RO 0 SS3 Raw Interrupt Status Value Description 1 A sample has completed conversion and the respective ADCSSCTL3 IEn bit is set, enabling a raw interrupt. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN3 bit in the ADCISC register. 2 INR2 RO 0 SS2 Raw Interrupt Status Value Description 1 A sample has completed conversion and the respective ADCSSCTL2 IEn bit is set, enabling a raw interrupt. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN2 bit in the ADCISC register. July 22, 2011 543 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 1 INR1 RO 0 Description SS1 Raw Interrupt Status Value Description 1 A sample has completed conversion and the respective ADCSSCTL1 IEn bit is set, enabling a raw interrupt. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN1 bit in the ADCISC register. 0 INR0 RO 0 SS0 Raw Interrupt Status Value Description 1 A sample has completed conversion and the respective ADCSSCTL0 IEn bit is set, enabling a raw interrupt. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN0 bit in the ADCISC register. 544 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the sample sequencer and digital comparator raw interrupt signals are sent to the interrupt controller. Each raw interrupt signal can be masked independently. Only a single DCONSSn bit should be set at any given time. Setting more than one of these bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is generated on any of the sample sequencer interrupt lines. ADC Interrupt Mask (ADCIM) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 25 24 23 22 21 20 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 9 8 7 6 5 4 3 2 1 0 MASK3 MASK2 MASK1 MASK0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 18 17 16 DCONSS3 DCONSS2 DCONSS1 DCONSS0 reserved Type Reset 19 Bit/Field Name Type Reset Description 31:20 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 DCONSS3 R/W 0 Digital Comparator Interrupt on SS3 Value Description 18 DCONSS2 R/W 0 1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS3 interrupt line. 0 The status of the digital comparators does not affect the SS3 interrupt status. Digital Comparator Interrupt on SS2 Value Description 17 DCONSS1 R/W 0 1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS2 interrupt line. 0 The status of the digital comparators does not affect the SS2 interrupt status. Digital Comparator Interrupt on SS1 Value Description 1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS1 interrupt line. 0 The status of the digital comparators does not affect the SS1 interrupt status. July 22, 2011 545 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 16 DCONSS0 R/W 0 Description Digital Comparator Interrupt on SS0 Value Description 1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register) is sent to the interrupt controller on the SS0 interrupt line. 0 The status of the digital comparators does not affect the SS0 interrupt status. 15:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 MASK3 R/W 0 SS3 Interrupt Mask Value Description 2 MASK2 R/W 0 1 The raw interrupt signal from Sample Sequencer 3 (ADCRIS register INR3 bit) is sent to the interrupt controller. 0 The status of Sample Sequencer 3 does not affect the SS3 interrupt status. SS2 Interrupt Mask Value Description 1 MASK1 R/W 0 1 The raw interrupt signal from Sample Sequencer 2 (ADCRIS register INR2 bit) is sent to the interrupt controller. 0 The status of Sample Sequencer 2 does not affect the SS2 interrupt status. SS1 Interrupt Mask Value Description 0 MASK0 R/W 0 1 The raw interrupt signal from Sample Sequencer 1 (ADCRIS register INR1 bit) is sent to the interrupt controller. 0 The status of Sample Sequencer 1 does not affect the SS1 interrupt status. SS0 Interrupt Mask Value Description 1 The raw interrupt signal from Sample Sequencer 0 (ADCRIS register INR0 bit) is sent to the interrupt controller. 0 The status of Sample Sequencer 0 does not affect the SS0 interrupt status. 546 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing sample sequencer interrupt conditions and shows the status of interrupts generated by the sample sequencers and the digital comparators which have been sent to the interrupt controller. When read, each bit field is the logical AND of the respective INR and MASK bits. Sample sequencer interrupts are cleared by writing a 1 to the corresponding bit position. Digital comparator interrupts are cleared by writing a 1 to the appropriate bits in the ADCDCISC register. If software is polling the ADCRIS instead of generating interrupts, the sample sequence INRn bits are still cleared via the ADCISC register, even if the INn bit is not set. ADC Interrupt Status and Clear (ADCISC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x00C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 25 24 23 22 21 20 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 2 1 0 IN3 IN2 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset 18 17 16 DCINSS3 DCINSS2 DCINSS1 DCINSS0 reserved Type Reset 19 Bit/Field Name Type Reset Description 31:20 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 DCINSS3 RO 0 Digital Comparator Interrupt Status on SS3 Value Description 1 Both the INRDC bit in the ADCRIS register and the DCONSS3 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the ADCRIS register. 18 DCINSS2 RO 0 Digital Comparator Interrupt Status on SS2 Value Description 1 Both the INRDC bit in the ADCRIS register and the DCONSS2 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the ADCRIS register. July 22, 2011 547 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 17 DCINSS1 RO 0 Description Digital Comparator Interrupt Status on SS1 Value Description 1 Both the INRDC bit in the ADCRIS register and the DCONSS1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the ADCRIS register. 16 DCINSS0 RO 0 Digital Comparator Interrupt Status on SS0 Value Description 1 Both the INRDC bit in the ADCRIS register and the DCONSS0 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the ADCRIS register. 15:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 IN3 R/W1C 0 SS3 Interrupt Status and Clear Value Description 1 Both the INR3 bit in the ADCRIS register and the MASK3 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INR3 bit in the ADCRIS register. 2 IN2 R/W1C 0 SS2 Interrupt Status and Clear Value Description 1 Both the INR2 bit in the ADCRIS register and the MASK2 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INR2 bit in the ADCRIS register. 548 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 1 IN1 R/W1C 0 Description SS1 Interrupt Status and Clear Value Description 1 Both the INR1 bit in the ADCRIS register and the MASK1 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INR1 bit in the ADCRIS register. 0 IN0 R/W1C 0 SS0 Interrupt Status and Clear Value Description 1 Both the INR0 bit in the ADCRIS register and the MASK0 bit in the ADCIM register are set, providing a level-based interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INR0 bit in the ADCRIS register. July 22, 2011 549 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x010 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 OV3 OV2 OV1 OV0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 OV3 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Overflow Value Description 1 The FIFO for Sample Sequencer 3 has hit an overflow condition, meaning that the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. 0 The FIFO has not overflowed. This bit is cleared by writing a 1. 2 OV2 R/W1C 0 SS2 FIFO Overflow Value Description 1 The FIFO for Sample Sequencer 2 has hit an overflow condition, meaning that the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. 0 The FIFO has not overflowed. This bit is cleared by writing a 1. 1 OV1 R/W1C 0 SS1 FIFO Overflow Value Description 1 The FIFO for Sample Sequencer 1 has hit an overflow condition, meaning that the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. 0 The FIFO has not overflowed. This bit is cleared by writing a 1. 550 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 OV0 R/W1C 0 Description SS0 FIFO Overflow Value Description 1 The FIFO for Sample Sequencer 0 has hit an overflow condition, meaning that the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. 0 The FIFO has not overflowed. This bit is cleared by writing a 1. July 22, 2011 551 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each sample sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset EM3 Type Reset EM2 EM1 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 EM0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 552 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 15:12 EM3 R/W 0x0 Description SS3 Trigger Select This field selects the trigger source for Sample Sequencer 3. The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 1013). 0x2 Analog Comparator 1 This trigger is configured by the Analog Comparator Control 1 (ACCTL1) register (page 1013). 0x3 reserved 0x4 External (GPIO PB4) This trigger is connected to the GPIO interrupt for PB4 (see “ADC Trigger Source” on page 400). Note: 0x5 PB4 can be used to trigger the ADC. However, the PB4/AIN10 pin cannot be used as both a GPIO and an analog input. Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (page 470). 0x6 PWM0 The PWM generator 0 trigger can be configured with the PWM0 Interrupt and Trigger Enable (PWM0INTEN) register (page 1056). 0x7 PWM1 The PWM generator 1 trigger can be configured with the PWM1INTEN register (page 1056). 0x8 PWM2 The PWM generator 2 trigger can be configured with the PWM2INTEN register (page 1056). 0x9 reserved 0xA-0xE reserved 0xF Always (continuously sample) July 22, 2011 553 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 11:8 EM2 R/W 0x0 Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 1013). 0x2 Analog Comparator 1 This trigger is configured by the Analog Comparator Control 1 (ACCTL1) register (page 1013). 0x3 reserved 0x4 External (GPIO PB4) This trigger is connected to the GPIO interrupt for PB4 (see “ADC Trigger Source” on page 400). Note: 0x5 PB4 can be used to trigger the ADC. However, the PB4/AIN10 pin cannot be used as both a GPIO and an analog input. Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (page 470). 0x6 PWM0 The PWM generator 0 trigger can be configured with the PWM0 Interrupt and Trigger Enable (PWM0INTEN) register (page 1056). 0x7 PWM1 The PWM generator 1 trigger can be configured with the PWM1INTEN register (page 1056). 0x8 PWM2 The PWM generator 2 trigger can be configured with the PWM2INTEN register (page 1056). 0x9 reserved 0xA-0xE reserved 0xF Always (continuously sample) 554 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 7:4 EM1 R/W 0x0 Description SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 1013). 0x2 Analog Comparator 1 This trigger is configured by the Analog Comparator Control 1 (ACCTL1) register (page 1013). 0x3 reserved 0x4 External (GPIO PB4) This trigger is connected to the GPIO interrupt for PB4 (see “ADC Trigger Source” on page 400). Note: 0x5 PB4 can be used to trigger the ADC. However, the PB4/AIN10 pin cannot be used as both a GPIO and an analog input. Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (page 470). 0x6 PWM0 The PWM generator 0 trigger can be configured with the PWM0 Interrupt and Trigger Enable (PWM0INTEN) register (page 1056). 0x7 PWM1 The PWM generator 1 trigger can be configured with the PWM1INTEN register (page 1056). 0x8 PWM2 The PWM generator 2 trigger can be configured with the PWM2INTEN register (page 1056). 0x9 reserved 0xA-0xE reserved 0xF Always (continuously sample) July 22, 2011 555 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 3:0 EM0 R/W 0x0 Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0 The valid configurations for this field are: Value Event 0x0 Processor (default) The trigger is initiated by setting the SSn bit in the ADCPSSI register. 0x1 Analog Comparator 0 This trigger is configured by the Analog Comparator Control 0 (ACCTL0) register (page 1013). 0x2 Analog Comparator 1 This trigger is configured by the Analog Comparator Control 1 (ACCTL1) register (page 1013). 0x3 reserved 0x4 External (GPIO PB4) This trigger is connected to the GPIO interrupt for PB4 (see “ADC Trigger Source” on page 400). Note: 0x5 PB4 can be used to trigger the ADC. However, the PB4/AIN10 pin cannot be used as both a GPIO and an analog input. Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (page 470). 0x6 PWM0 The PWM generator 0 trigger can be configured with the PWM0 Interrupt and Trigger Enable (PWM0INTEN) register (page 1056). 0x7 PWM1 The PWM generator 1 trigger can be configured with the PWM1INTEN register (page 1056). 0x8 PWM2 The PWM generator 2 trigger can be configured with the PWM2INTEN register (page 1056). 0x9 reserved 0xA-0xE reserved 0xF Always (continuously sample) 556 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding underflow condition is cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x018 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 UV3 UV2 UV1 UV0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 UV3 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Underflow The valid configurations for this field are shown below. This bit is cleared by writing a 1. Value Description 2 UV2 R/W1C 0 1 The FIFO for the Sample Sequencer has hit an underflow condition, meaning that the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. 0 The FIFO has not underflowed. SS2 FIFO Underflow The valid configurations are the same as those for the UV3 field. This bit is cleared by writing a 1. 1 UV1 R/W1C 0 SS1 FIFO Underflow The valid configurations are the same as those for the UV3 field. This bit is cleared by writing a 1. 0 UV0 R/W1C 0 SS0 FIFO Underflow The valid configurations are the same as those for the UV3 field. This bit is cleared by writing a 1. July 22, 2011 557 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority for the ADC to operate properly. ADC Sample Sequencer Priority (ADCSSPRI) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x020 Type R/W, reset 0x0000.3210 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 1 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 RO 0 RO 0 R/W 0 R/W 1 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 SS3 R/W 1 reserved RO 0 SS2 R/W 1 Bit/Field Name Type Reset 31:14 reserved RO 0x0000.0 13:12 SS3 R/W 0x3 reserved SS1 reserved SS0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 3. A priority encoding of 0x0 is highest and 0x3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 11:10 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9:8 SS2 R/W 0x2 SS2 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 2. A priority encoding of 0x0 is highest and 0x3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 SS1 R/W 0x1 SS1 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 1. A priority encoding of 0x0 is highest and 0x3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 558 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 1:0 SS0 R/W 0x0 SS0 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. A priority encoding of 0x0 is highest and 0x3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. July 22, 2011 559 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024 This register allows the ADC module to sample at one of 16 different discrete phases from 0.0° through 337.5°. For example, the sample rate could be effectively doubled by sampling a signal using one ADC module configured with the standard sample time and the second ADC module configured with a 180.0° phase lag. Note: Care should be taken when the PHASE field is non-zero, as the resulting delay in sampling the AINx input may result in undesirable system consequences. The time from ADC trigger to sample is increased and could make the response time longer than anticipated. The added latency could have ramifications in the system design. Designers should carefully consider the impact of this delay. ADC Sample Phase Control (ADCSPC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 PHASE RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 560 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 3:0 PHASE R/W 0x0 Description Phase Difference This field selects the sample phase difference from the standard sample time. Value Description 0x0 ADC sample lags by 0.0° 0x1 ADC sample lags by 22.5° 0x2 ADC sample lags by 45.0° 0x3 ADC sample lags by 67.5° 0x4 ADC sample lags by 90.0° 0x5 ADC sample lags by 112.5° 0x6 ADC sample lags by 135.0° 0x7 ADC sample lags by 157.5° 0x8 ADC sample lags by 180.0° 0x9 ADC sample lags by 202.5° 0xA ADC sample lags by 225.0° 0xB ADC sample lags by 247.5° 0xC ADC sample lags by 270.0° 0xD ADC sample lags by 292.5° 0xE ADC sample lags by 315.0° 0xF ADC sample lags by 337.5° July 22, 2011 561 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the sample sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. This register also provides a means to configure and then initiate concurrent sampling on all ADC modules. To do this, the first ADC module should be configured. The ADCPSSI register for that module should then be written. The appropriate SS bits should be set along with the SYNCWAIT bit. Additional ADC modules should then be configured following the same procedure. Once the final ADC module is configured, its ADCPSSI register should be written with the appropriate SS bits set along with the GSYNC bit. All of the ADC modules then begin concurrent sampling according to their configuration. ADC Processor Sample Sequence Initiate (ADCPSSI) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x028 Type R/W, reset 31 30 GSYNC Type Reset 29 28 reserved 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved SYNCWAIT R/W 0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31 GSYNC R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 SS3 SS2 SS1 SS0 WO - WO - WO - WO - Description Global Synchronize Value Description 30:28 reserved RO 0x0 27 SYNCWAIT R/W 0 1 This bit initiates sampling in multiple ADC modules at the same time. Any ADC module that has been initialized by setting an SSn bit and the SYNCWAIT bit starts sampling once this bit is written. 0 This bit is cleared once sampling has been initiated. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Synchronize Wait Value Description 26:4 reserved RO 0x0000.0 1 This bit allows the sample sequences to be initiated, but delays sampling until the GSYNC bit is set. 0 Sampling begins when a sample sequence has been initiated. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 562 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 3 SS3 WO - SS3 Initiate Value Description 1 Begin sampling on Sample Sequencer 3, if the sequencer is enabled in the ADCACTSS register. 0 No effect. Only a write by software is valid; a read of this register returns no meaningful data. 2 SS2 WO - SS2 Initiate Value Description 1 Begin sampling on Sample Sequencer 2, if the sequencer is enabled in the ADCACTSS register. 0 No effect. Only a write by software is valid; a read of this register returns no meaningful data. 1 SS1 WO - SS1 Initiate Value Description 1 Begin sampling on Sample Sequencer 1, if the sequencer is enabled in the ADCACTSS register. 0 No effect. Only a write by software is valid; a read of this register returns no meaningful data. 0 SS0 WO - SS0 Initiate Value Description 1 Begin sampling on Sample Sequencer 0, if the sequencer is enabled in the ADCACTSS register. 0 No effect. Only a write by software is valid; a read of this register returns no meaningful data. July 22, 2011 563 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An AVG=7 provides unpredictable results. ADC Sample Averaging Control (ADCSAC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2:0 AVG R/W 0x0 AVG R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hardware Averaging Control Specifies the amount of hardware averaging that will be applied to ADC samples. The AVG field can be any value between 0 and 6. Entering a value of 7 creates unpredictable results. Value Description 0x0 No hardware oversampling 0x1 2x hardware oversampling 0x2 4x hardware oversampling 0x3 8x hardware oversampling 0x4 16x hardware oversampling 0x5 32x hardware oversampling 0x6 64x hardware oversampling 0x7 reserved 564 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 This register provides status and acknowledgement of digital comparator interrupts. One bit is provided for each comparator. ADC Digital Comparator Interrupt Status and Clear (ADCDCISC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x034 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 DCINT7 R/W1C 0 RO 0 RO 0 7 6 5 4 3 2 1 0 DCINT7 DCINT6 DCINT5 DCINT4 DCINT3 DCINT2 DCINT1 DCINT0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Comparator 7 Interrupt Status and Clear Value Description 1 Digital Comparator 7 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 6 DCINT6 R/W1C 0 Digital Comparator 6 Interrupt Status and Clear Value Description 1 Digital Comparator 6 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 5 DCINT5 R/W1C 0 Digital Comparator 5 Interrupt Status and Clear Value Description 1 Digital Comparator 5 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. July 22, 2011 565 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 4 DCINT4 R/W1C 0 Description Digital Comparator 4 Interrupt Status and Clear Value Description 1 Digital Comparator 4 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 3 DCINT3 R/W1C 0 Digital Comparator 3 Interrupt Status and Clear Value Description 1 Digital Comparator 3 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 2 DCINT2 R/W1C 0 Digital Comparator 2 Interrupt Status and Clear Value Description 1 Digital Comparator 2 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 1 DCINT1 R/W1C 0 Digital Comparator 1 Interrupt Status and Clear Value Description 1 Digital Comparator 1 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 0 DCINT0 R/W1C 0 Digital Comparator 0 Interrupt Status and Clear Value Description 1 Digital Comparator 0 has generated an interrupt. 0 No interrupt. This bit is cleared by writing a 1. 566 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 13: ADC Control (ADCCTL), offset 0x038 This register configures the voltage reference. The voltage reference for the conversion can be the internal 3.0-V reference or an external voltage reference in the range of 2.4 V to 3.06 V. ADC Control (ADCCTL) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 VREF R/W 0 RO 0 VREF R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Voltage Reference Select Value Description 1 The external VREFA input is the voltage reference. 0 The internal reference as the voltage reference. July 22, 2011 567 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 14: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. This register is 32 bits wide and contains information for eight possible samples. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 MUX7 Type Reset R/W 0 R/W 0 15 14 R/W 0 R/W 0 R/W 0 R/W 0 13 12 11 10 MUX3 Type Reset R/W 0 R/W 0 25 24 23 22 MUX6 R/W 0 R/W 0 R/W 0 R/W 0 9 8 7 6 MUX2 R/W 0 R/W 0 R/W 0 R/W 0 21 20 19 18 MUX5 R/W 0 R/W 0 R/W 0 R/W 0 5 4 3 2 MUX1 R/W 0 Bit/Field Name Type Reset 31:28 MUX7 R/W 0x0 R/W 0 R/W 0 R/W 0 17 16 R/W 0 R/W 0 1 0 R/W 0 R/W 0 MUX4 MUX0 R/W 0 R/W 0 R/W 0 R/W 0 Description 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. The value set here indicates the corresponding pin, for example, a value of 0x1 indicates the input is AIN1. 27:24 MUX6 R/W 0x0 7th Sample Input Select The MUX6 field is used during the seventh sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 23:20 MUX5 R/W 0x0 6th Sample Input Select The MUX5 field is used during the sixth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 19:16 MUX4 R/W 0x0 5th Sample Input Select The MUX4 field is used during the fifth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 15:12 MUX3 R/W 0x0 4th Sample Input Select The MUX3 field is used during the fourth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 11:8 MUX2 R/W 0x0 3rd Sample Input Select The MUX2 field is used during the third sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 568 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 7:4 MUX1 R/W 0x0 Description 2nd Sample Input Select The MUX1 field is used during the second sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 3:0 MUX0 R/W 0x0 1st Sample Input Select The MUX0 field is used during the first sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. July 22, 2011 569 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 15: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with a sample sequencer. When configuring a sample sequence, the END bit must be set for the final sample, whether it be after the first sample, eighth sample, or any sample in between. This register is 32 bits wide and contains information for eight possible samples. ADC Sample Sequence Control 0 (ADCSSCTL0) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x044 Type R/W, reset 0x0000.0000 31 Type Reset Type Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31 TS7 R/W 0 Description 8th Sample Temp Sensor Select Value Description 30 IE7 R/W 0 1 The temperature sensor is read during the eighth sample of the sample sequence. 0 The input pin specified by the ADCSSMUXn register is read during the eighth sample of the sample sequence. 8th Sample Interrupt Enable Value Description 1 The raw interrupt signal (INR0 bit) is asserted at the end of the eighth sample's conversion. If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to the interrupt controller. 0 The raw interrupt is not asserted to the interrupt controller. It is legal to have multiple samples within a sequence generate interrupts. 29 END7 R/W 0 8th Sample is End of Sequence Value Description 1 The eighth sample is the last sample of the sequence. 0 Another sample in the sequence is the final sample. It is possible to end the sequence on any sample position. Software must set an ENDn bit somewhere within the sequence. Samples defined after the sample containing a set ENDn bit are not requested for conversion even though the fields may be non-zero. 570 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 28 D7 R/W 0 Description 8th Sample Diff Input Select Value Description 1 The analog input is differentially sampled. The corresponding ADCSSMUXn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". 0 The analog inputs are not differentially sampled. Because the temperature sensor does not have a differential option, this bit must not be set when the TS7 bit is set. 27 TS6 R/W 0 7th Sample Temp Sensor Select Same definition as TS7 but used during the seventh sample. 26 IE6 R/W 0 7th Sample Interrupt Enable Same definition as IE7 but used during the seventh sample. 25 END6 R/W 0 7th Sample is End of Sequence Same definition as END7 but used during the seventh sample. 24 D6 R/W 0 7th Sample Diff Input Select Same definition as D7 but used during the seventh sample. 23 TS5 R/W 0 6th Sample Temp Sensor Select Same definition as TS7 but used during the sixth sample. 22 IE5 R/W 0 6th Sample Interrupt Enable Same definition as IE7 but used during the sixth sample. 21 END5 R/W 0 6th Sample is End of Sequence Same definition as END7 but used during the sixth sample. 20 D5 R/W 0 6th Sample Diff Input Select Same definition as D7 but used during the sixth sample. 19 TS4 R/W 0 5th Sample Temp Sensor Select Same definition as TS7 but used during the fifth sample. 18 IE4 R/W 0 5th Sample Interrupt Enable Same definition as IE7 but used during the fifth sample. 17 END4 R/W 0 5th Sample is End of Sequence Same definition as END7 but used during the fifth sample. 16 D4 R/W 0 5th Sample Diff Input Select Same definition as D7 but used during the fifth sample. 15 TS3 R/W 0 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. July 22, 2011 571 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 13 END3 R/W 0 Description 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 TS2 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 10 IE2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 8 D2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 7 TS1 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 6 IE1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 TS0 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 572 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 16: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 18: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 19: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 Important: This register is read-sensitive. See the register description for details. This register contains the conversion results for samples collected with the sample sequencer (the ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1, ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT registers. ADC Sample Sequence Result FIFO n (ADCSSFIFOn) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x048 Type RO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 4 3 2 1 0 RO - RO - RO - RO - RO - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DATA RO 0 RO 0 RO - Bit/Field Name Type Reset 31:10 reserved RO 0x0000.00 9:0 DATA RO - RO - RO - RO - RO - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Conversion Result Data July 22, 2011 573 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C Register 23: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC This register provides a window into the sample sequencer, providing full/empty status information as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty FIFO with the head and tail pointers both pointing to index 0. The ADCSSFSTAT0 register provides status on FIFO0, which has 8 entries; ADCSSFSTAT1 on FIFO1, which has 4 entries; ADCSSFSTAT2 on FIFO2, which has 4 entries; and ADCSSFSTAT3 on FIFO3 which has a single entry. ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x04C Type RO, reset 0x0000.0100 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RO 0 FULL RO 0 RO 0 reserved RO 0 RO 0 EMPTY RO 0 Bit/Field Name Type Reset 31:13 reserved RO 0x0000.0 12 FULL RO 0 RO 1 HPTR TPTR Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Full Value Description 11:9 reserved RO 0x0 8 EMPTY RO 1 1 The FIFO is currently full. 0 The FIFO is not currently full. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Empty Value Description 1 The FIFO is currently empty. 0 The FIFO is not currently empty. 574 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 7:4 HPTR RO 0x0 Description FIFO Head Pointer This field contains the current "head" pointer index for the FIFO, that is, the next entry to be written. Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and 0x0 for FIFO3. 3:0 TPTR RO 0x0 FIFO Tail Pointer This field contains the current "tail" pointer index for the FIFO, that is, the next entry to be read. Valid values are 0x0-0x7 for FIFO0; 0x0-0x3 for FIFO1 and FIFO2; and 0x0 for FIFO3. July 22, 2011 575 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 24: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 This register determines whether the sample from the given conversion on Sample Sequence 0 is saved in the Sample Sequence FIFO0 or sent to the digital comparator unit. ADC Sample Sequence 0 Operation (ADCSSOP0) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x050 Type R/W, reset 0x0000.0000 31 30 29 reserved Type Reset 27 S7DCOP 26 25 reserved 24 23 S6DCOP 22 21 reserved 20 19 S5DCOP 18 17 reserved 16 S4DCOP RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Type Reset 28 RO 0 RO 0 S3DCOP RO 0 R/W 0 reserved RO 0 RO 0 S2DCOP RO 0 Bit/Field Name Type Reset 31:29 reserved RO 0x0 28 S7DCOP R/W 0 R/W 0 reserved RO 0 RO 0 S1DCOP RO 0 R/W 0 reserved RO 0 RO 0 S0DCOP RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 7 Digital Comparator Operation Value Description 27:25 reserved RO 0x0 24 S6DCOP R/W 0 1 The eighth sample is sent to the digital comparator unit specified by the S7DCSEL bit in the ADCSSDC0 register, and the value is not written to the FIFO. 0 The eighth sample is saved in Sample Sequence FIFO0. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 6 Digital Comparator Operation Same definition as S7DCOP but used during the seventh sample. 23:21 reserved RO 0x0 20 S5DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 5 Digital Comparator Operation Same definition as S7DCOP but used during the sixth sample. 19:17 reserved RO 0x0 16 S4DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 4 Digital Comparator Operation Same definition as S7DCOP but used during the fifth sample. 15:13 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 576 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 12 S3DCOP R/W 0 Description Sample 3 Digital Comparator Operation Same definition as S7DCOP but used during the fourth sample. 11:9 reserved RO 0x0 8 S2DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 2 Digital Comparator Operation Same definition as S7DCOP but used during the third sample. 7:5 reserved RO 0x0 4 S1DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 1 Digital Comparator Operation Same definition as S7DCOP but used during the second sample. 3:1 reserved RO 0x0 0 S0DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 0 Digital Comparator Operation Same definition as S7DCOP but used during the first sample. July 22, 2011 577 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 25: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 This register determines which digital comparator receives the sample from the given conversion on Sample Sequence 0, if the corresponding SnDCOP bit in the ADCSSOP0 register is set. ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 S7DCSEL Type Reset 24 23 22 21 20 19 S5DCSEL 18 17 16 S4DCSEL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S3DCSEL Type Reset 25 S6DCSEL R/W 0 R/W 0 S2DCSEL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:28 S7DCSEL R/W 0x0 S1DCSEL R/W 0 R/W 0 R/W 0 R/W 0 S0DCSEL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Sample 7 Digital Comparator Select When the S7DCOP bit in the ADCSSOP0 register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the eighth sample from Sample Sequencer 0. Note: Values not listed are reserved. Value Description 27:24 S6DCSEL R/W 0x0 0x0 Digital Comparator Unit 0 (ADCDCCMP0 and ADCDCCTL0) 0x1 Digital Comparator Unit 1 (ADCDCCMP1 and ADCDCCTL1) 0x2 Digital Comparator Unit 2 (ADCDCCMP2 and ADCDCCTL2) 0x3 Digital Comparator Unit 3 (ADCDCCMP3 and ADCDCCTL3) 0x4 Digital Comparator Unit 4 (ADCDCCMP4 and ADCDCCTL4) 0x5 Digital Comparator Unit 5 (ADCDCCMP5 and ADCDCCTL5) 0x6 Digital Comparator Unit 6 (ADCDCCMP6 and ADCDCCTL6) 0x7 Digital Comparator Unit 7 (ADCDCCMP7 and ADCDCCTL7) Sample 6 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the seventh sample. 23:20 S5DCSEL R/W 0x0 Sample 5 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the sixth sample. 19:16 S4DCSEL R/W 0x0 Sample 4 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the fifth sample. 15:12 S3DCSEL R/W 0x0 Sample 3 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the fourth sample. 578 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 11:8 S2DCSEL R/W 0x0 Description Sample 2 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the third sample. 7:4 S1DCSEL R/W 0x0 Sample 1 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the second sample. 3:0 S0DCSEL R/W 0x0 Sample 0 Digital Comparator Select This field has the same encodings as S7DCSEL but is used during the first sample. July 22, 2011 579 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 26: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 27: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. These registers are 16 bits wide and contain information for four possible samples. See the ADCSSMUX0 register on page 568 for detailed bit descriptions. The ADCSSMUX1 register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2. ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x060 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset MUX3 Type Reset MUX2 MUX1 MUX0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 15:12 MUX3 R/W 0x0 4th Sample Input Select 11:8 MUX2 R/W 0x0 3rd Sample Input Select 7:4 MUX1 R/W 0x0 2nd Sample Input Select 3:0 MUX0 R/W 0x0 1st Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 580 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 28: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 29: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set for the final sample, whether it be after the first sample, fourth sample, or any sample in between. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0 register on page 570 for detailed bit descriptions. The ADCSSCTL1 register configures Sample Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2. ADC Sample Sequence Control 1 (ADCSSCTL1) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x064 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 TS3 IE3 END3 D3 TS2 IE2 END2 D2 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TS1 IE1 END1 D1 TS0 IE0 END0 D0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 TS3 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 13 END3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 TS2 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 10 IE2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 8 D2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. July 22, 2011 581 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 7 TS1 R/W 0 Description 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 6 IE1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 TS0 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 582 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 30: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 Register 31: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 This register determines whether the sample from the given conversion on Sample Sequence n is saved in the Sample Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1 register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2. ADC Sample Sequence 1 Operation (ADCSSOP1) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x070 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset reserved Type Reset RO 0 RO 0 S3DCOP RO 0 R/W 0 reserved RO 0 RO 0 S2DCOP RO 0 Bit/Field Name Type Reset 31:13 reserved RO 0x0000.0 12 S3DCOP R/W 0 R/W 0 reserved RO 0 RO 0 S1DCOP RO 0 R/W 0 reserved RO 0 RO 0 S0DCOP RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 3 Digital Comparator Operation Value Description 11:9 reserved RO 0x0 8 S2DCOP R/W 0 1 The fourth sample is sent to the digital comparator unit specified by the S3DCSEL bit in the ADCSSDC0n register, and the value is not written to the FIFO. 0 The fourth sample is saved in Sample Sequence FIFOn. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 2 Digital Comparator Operation Same definition as S3DCOP but used during the third sample. 7:5 reserved RO 0x0 4 S1DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 1 Digital Comparator Operation Same definition as S3DCOP but used during the second sample. 3:1 reserved RO 0x0 0 S0DCOP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 0 Digital Comparator Operation Same definition as S3DCOP but used during the first sample. July 22, 2011 583 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 32: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 Register 33: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 These registers determine which digital comparator receives the sample from the given conversion on Sample Sequence n if the corresponding SnDCOP bit in the ADCSSOPn register is set. The ADCSSDC1 register controls the selection for Sample Sequencer 1 and the ADCSSDC2 register controls the selection for Sample Sequencer 2. ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x074 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset S3DCSEL Type Reset S2DCSEL R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15:12 S3DCSEL R/W 0x0 S1DCSEL R/W 0 S0DCSEL R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 3 Digital Comparator Select When the S3DCOP bit in the ADCSSOPn register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the eighth sample from Sample Sequencer n. Note: Values not listed are reserved. Value Description 11:8 S2DCSEL R/W 0x0 0x0 Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0) 0x1 Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1) 0x2 Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2) 0x3 Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3) 0x4 Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4) 0x5 Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5) 0x6 Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6) 0x7 Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7) Sample 2 Digital Comparator Select This field has the same encodings as S3DCSEL but is used during the third sample. 584 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 7:4 S1DCSEL R/W 0x0 Description Sample 1 Digital Comparator Select This field has the same encodings as S3DCSEL but is used during the second sample. 3:0 S0DCSEL R/W 0x0 Sample 0 Digital Comparator Select This field has the same encodings as S3DCSEL but is used during the first sample. July 22, 2011 585 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 34: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register defines the analog input configuration for the sample executed with Sample Sequencer 3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSMUX0 register on page 568 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x0A0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 MUX0 RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3:0 MUX0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select 586 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 35: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for a sample executed with Sample Sequencer 3. The END0 bit is always set as this sequencer can execute only one sample. This register is 4 bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 570 for detailed bit descriptions. ADC Sample Sequence Control 3 (ADCSSCTL3) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x0A4 Type R/W, reset 0x0000.0002 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TS0 IE0 END0 D0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 TS0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 1 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Because this sequencer has only one entry, this bit must be set. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. July 22, 2011 587 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 36: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 This register determines whether the sample from the given conversion on Sample Sequence 3 is saved in the Sample Sequence 3 FIFO or sent to the digital comparator unit. ADC Sample Sequence 3 Operation (ADCSSOP3) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x0B0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 S0DCOP R/W 0 RO 0 S0DCOP R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 0 Digital Comparator Operation Value Description 1 The sample is sent to the digital comparator unit specified by the S0DCSEL bit in the ADCSSDC03 register, and the value is not written to the FIFO. 0 The sample is saved in Sample Sequence FIFO3. 588 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 37: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 This register determines which digital comparator receives the sample from the given conversion on Sample Sequence 3 if the corresponding SnDCOP bit in the ADCSSOP3 register is set. ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0x0B4 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3:0 S0DCSEL R/W 0x0 S0DCSEL RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sample 0 Digital Comparator Select When the S0DCOP bit in the ADCSSOP3 register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the sample from Sample Sequencer 3. Note: Values not listed are reserved. Value Description 0x0 Digital Comparator Unit 0 (ADCDCCMP0 and ADCCCTL0) 0x1 Digital Comparator Unit 1 (ADCDCCMP1 and ADCCCTL1) 0x2 Digital Comparator Unit 2 (ADCDCCMP2 and ADCCCTL2) 0x3 Digital Comparator Unit 3 (ADCDCCMP3 and ADCCCTL3) 0x4 Digital Comparator Unit 4 (ADCDCCMP4 and ADCCCTL4) 0x5 Digital Comparator Unit 5 (ADCDCCMP5 and ADCCCTL5) 0x6 Digital Comparator Unit 6 (ADCDCCMP6 and ADCCCTL6) 0x7 Digital Comparator Unit 7 (ADCDCCMP7 and ADCCCTL7) July 22, 2011 589 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 38: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 This register provides the ability to reset any of the digital comparator interrupt or trigger functions back to their initial conditions. Resetting these functions ensures that the data that is being used by the interrupt and trigger functions in the digital comparator unit is not stale. ADC Digital Comparator Reset Initial Conditions (ADCDCRIC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0xD00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 DCTRIG7 DCTRIG6 DCTRIG5 DCTRIG4 DCTRIG3 DCTRIG2 DCTRIG1 DCTRIG0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 DCINT7 DCINT6 DCINT5 DCINT4 DCINT3 DCINT2 DCINT1 DCINT0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23 DCTRIG7 R/W 0 Digital Comparator Trigger 7 Value Description 1 Resets the Digital Comparator 7 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. After setting this bit, software should wait until the bit clears before continuing. 22 DCTRIG6 R/W 0 Digital Comparator Trigger 6 Value Description 1 Resets the Digital Comparator 6 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 590 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 21 DCTRIG5 R/W 0 Description Digital Comparator Trigger 5 Value Description 1 Resets the Digital Comparator 5 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 20 DCTRIG4 R/W 0 Digital Comparator Trigger 4 Value Description 1 Resets the Digital Comparator 4 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 19 DCTRIG3 R/W 0 Digital Comparator Trigger 3 Value Description 1 Resets the Digital Comparator 3 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 18 DCTRIG2 R/W 0 Digital Comparator Trigger 2 Value Description 1 Resets the Digital Comparator 2 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. July 22, 2011 591 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 17 DCTRIG1 R/W 0 Description Digital Comparator Trigger 1 Value Description 1 Resets the Digital Comparator 1 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 16 DCTRIG0 R/W 0 Digital Comparator Trigger 0 Value Description 1 Resets the Digital Comparator 0 trigger unit to its initial conditions. 0 No effect. When the trigger has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 15:8 reserved RO 0x00 7 DCINT7 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Comparator Interrupt 7 Value Description 1 Resets the Digital Comparator 7 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 6 DCINT6 R/W 0 Digital Comparator Interrupt 6 Value Description 1 Resets the Digital Comparator 6 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 592 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 5 DCINT5 R/W 0 Description Digital Comparator Interrupt 5 Value Description 1 Resets the Digital Comparator 5 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 4 DCINT4 R/W 0 Digital Comparator Interrupt 4 Value Description 1 Resets the Digital Comparator 4 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 3 DCINT3 R/W 0 Digital Comparator Interrupt 3 Value Description 1 Resets the Digital Comparator 3 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 2 DCINT2 R/W 0 Digital Comparator Interrupt 2 Value Description 1 Resets the Digital Comparator 2 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. July 22, 2011 593 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 1 DCINT1 R/W 0 Description Digital Comparator Interrupt 1 Value Description 1 Resets the Digital Comparator 1 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 DCINT0 R/W 0 Digital Comparator Interrupt 0 Value Description 1 Resets the Digital Comparator 0 interrupt unit to its initial conditions. 0 No effect. When the interrupt has been cleared, this bit is automatically cleared. Because the digital comparators use the current and previous ADC conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 594 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 39: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 Register 40: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 Register 41: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 Register 42: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C Register 43: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 Register 44: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 Register 45: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 Register 46: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C This register provides the comparison encodings that generate an interrupt and/or PWM trigger. See “Interrupt/ADC-Trigger Selector” on page 1023 for more information on using the ADC digital comparators to trigger a PWM generator. ADC Digital Comparator Control 0 (ADCDCCTL0) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0xE00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 CTE RO 0 R/W 0 CTC R/W 0 CTM Bit/Field Name Type Reset 31:13 reserved RO 0x0000.0 12 CTE R/W 0 reserved RO 0 CIE CIC R/W 0 CIM R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparison Trigger Enable Value Description 1 Enables the trigger function state machine. The ADC conversion data is used to determine if a trigger should be generated according to the programming of the CTC and CTM fields. 0 Disables the trigger function state machine. ADC conversion data is ignored by the trigger function. July 22, 2011 595 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 11:10 CTC R/W 0x0 Description Comparison Trigger Condition This field specifies the operational region in which a trigger is generated when the ADC conversion data is compared against the values of COMP0 and COMP1. The COMP0 and COMP1 fields are defined in the ADCDCCMPx registers. Value Description 0x0 Low Band ADC Data < COMP0 ≤ COMP1 0x1 Mid Band COMP0 ≤ ADC Data < COMP1 0x2 reserved 0x3 High Band COMP0 ≤ COMP1 ≤ ADC Data 9:8 CTM R/W 0x0 Comparison Trigger Mode This field specifies the mode by which the trigger comparison is made. Value Description 0x0 Always This mode generates a trigger every time the ADC conversion data falls within the selected operational region. 0x1 Once This mode generates a trigger the first time that the ADC conversion data enters the selected operational region. 0x2 Hysteresis Always This mode generates a trigger when the ADC conversion data falls within the selected operational region and continues to generate the trigger until the hysteresis condition is cleared by entering the opposite operational region. Note that the hysteresis modes are only defined for CTC encodings of 0x0 and 0x3. 0x3 Hysteresis Once This mode generates a trigger the first time that the ADC conversion data falls within the selected operational region. No additional triggers are generated until the hysteresis condition is cleared by entering the opposite operational region. Note that the hysteresis modes are only defined for CTC encodings of 0x0 and 0x3. 7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 596 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 4 CIE R/W 0 Description Comparison Interrupt Enable Value Description 3:2 CIC R/W 0x0 1 Enables the comparison interrupt. The ADC conversion data is used to determine if an interrupt should be generated according to the programming of the CIC and CIM fields. 0 Disables the comparison interrupt. ADC conversion data has no effect on interrupt generation. Comparison Interrupt Condition This field specifies the operational region in which an interrupt is generated when the ADC conversion data is compared against the values of COMP0 and COMP1. The COMP0 and COMP1 fields are defined in the ADCDCCMPx registers. Value Description 0x0 Low Band ADC Data < COMP0 ≤ COMP1 0x1 Mid Band COMP0 ≤ ADC Data < COMP1 0x2 reserved 0x3 High Band COMP0 < COMP1 ≤ ADC Data 1:0 CIM R/W 0x0 Comparison Interrupt Mode This field specifies the mode by which the interrupt comparison is made. Value Description 0x0 Always This mode generates an interrupt every time the ADC conversion data falls within the selected operational region. 0x1 Once This mode generates an interrupt the first time that the ADC conversion data enters the selected operational region. 0x2 Hysteresis Always This mode generates an interrupt when the ADC conversion data falls within the selected operational region and continues to generate the interrupt until the hysteresis condition is cleared by entering the opposite operational region. Note that the hysteresis modes are only defined for CTC encodings of 0x0 and 0x3. 0x3 Hysteresis Once This mode generates an interrupt the first time that the ADC conversion data falls within the selected operational region. No additional interrupts are generated until the hysteresis condition is cleared by entering the opposite operational region. Note that the hysteresis modes are only defined for CTC encodings of 0x0 and 0x3. July 22, 2011 597 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 47: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 Register 48: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 Register 49: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 Register 50: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C Register 51: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 Register 52: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 Register 53: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 Register 54: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C This register defines the comparison values that are used to determine if the ADC conversion data falls in the appropriate operating region. Note: The value in the COMP1 field must be greater than or equal to the value in the COMP0 field or unexpected results can occur. ADC Digital Comparator Range 0 (ADCDCCMP0) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 Offset 0xE40 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 reserved Type Reset 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset 20 COMP1 RO 0 RO 0 RO 0 RO 0 COMP0 RO 0 RO 0 R/W 0 Bit/Field Name Type Reset 31:26 reserved RO 0x0 25:16 COMP1 R/W 0x000 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Compare 1 The value in this field is compared against the ADC conversion data. The result of the comparison is used to determine if the data lies within the high-band region. Note that the value of COMP1 must be greater than or equal to the value of COMP0. 15:10 reserved RO 0x0 9:0 COMP0 R/W 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Compare 0 The value in this field is compared against the ADC conversion data. The result of the comparison is used to determine if the data lies within the low-band region. 598 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 12 Universal Asynchronous Receivers/Transmitters (UARTs) ® The Stellaris LM3S9L71 controller includes three Universal Asynchronous Receiver/Transmitter (UART) with the following features: ■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by 16) and 10 Mbps for high speed (divide by 8) ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Standard asynchronous communication bits for start, stop, and parity ■ Line-break generation and detection ■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Support for communication with ISO 7816 smart cards ■ Full modem handshake support (on UART1) ■ LIN protocol support ■ Standard FIFO-level and End-of-Transmission interrupts ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level July 22, 2011 599 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level 12.1 Block Diagram Figure 12-1. UART Module Block Diagram System Clock DMA Request DMA Control UARTDMACTL Interrupt Interrupt Control Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 12.2 UARTIFLS UARTIM UARTMIS UARTRIS UARTICR TxFIFO 16 x 8 . . . Baud Rate Generator UARTDR UARTRSR/ECR UARTFR UARTLCRH UARTCTL UARTILPR UARTLCTL UARTLSS UARTLTIM UnTx UARTIBRD UARTFBRD Control/Status Transmitter (with SIR Transmit Encoder) RxFIFO 16 x 8 Receiver (with SIR Receive Decoder) UnRx . . . Signal Description The following table lists the external signals of the UART module and describes the function of each. The UART signals are alternate functions for some GPIO signals and default to be GPIO signals at reset, with the exception of the U0Rx and U0Tx pins which default to the UART function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the UART function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the UART signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. 600 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 12-1. Signals for UART (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description U0Rx 26 PA0 (1) I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 PA1 (1) O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS 2 10 34 50 PE6 (9) PD0 (9) PA6 (9) PJ3 (9) I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD 1 11 35 52 PE7 (9) PD1 (9) PA7 (9) PJ4 (9) I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR 47 53 PF0 (9) PJ5 (9) I TTL UART module 1 Data Set Ready modem output control line. U1DTR 40 55 100 PG5 (10) PJ7 (9) PD7 (9) O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI 37 41 97 PG6 (10) PG4 (10) PD4 (9) I TTL UART module 1 Ring Indicator modem status input signal. U1RTS 43 54 61 PF6 (10) PJ6 (9) PF1 (9) O TTL UART module 1 Request to Send modem flow control output line. U1Rx 10 12 23 26 66 92 PD0 (5) PD2 (1) PC6 (5) PA0 (9) PB0 (5) PB4 (7) I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 11 13 22 27 67 91 PD1 (5) PD3 (1) PC7 (5) PA1 (9) PB1 (5) PB5 (7) O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx 10 19 92 98 PD0 (4) PG0 (1) PB4 (4) PD5 (9) I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx 6 11 18 99 PE4 (5) PD1 (4) PG1 (1) PD6 (9) O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 12-2. Signals for UART (108BGA) Pin Name U0Rx Pin Number Pin Mux / Pin Assignment L3 PA0 (1) a Pin Type Buffer Type I TTL Description UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. July 22, 2011 601 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Table 12-2. Signals for UART (108BGA) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description U0Tx M3 PA1 (1) O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS A1 G1 L6 M10 PE6 (9) PD0 (9) PA6 (9) PJ3 (9) I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD B1 G2 M6 K11 PE7 (9) PD1 (9) PA7 (9) PJ4 (9) I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR M9 K12 PF0 (9) PJ5 (9) I TTL UART module 1 Data Set Ready modem output control line. U1DTR M7 L12 A2 PG5 (10) PJ7 (9) PD7 (9) O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI L7 K3 B5 PG6 (10) PG4 (10) PD4 (9) I TTL UART module 1 Ring Indicator modem status input signal. U1RTS M8 L10 H12 PF6 (10) PJ6 (9) PF1 (9) O TTL UART module 1 Request to Send modem flow control output line. U1Rx G1 H2 M2 L3 E12 A6 PD0 (5) PD2 (1) PC6 (5) PA0 (9) PB0 (5) PB4 (7) I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx G2 H1 L2 M3 D12 B7 PD1 (5) PD3 (1) PC7 (5) PA1 (9) PB1 (5) PB5 (7) O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx G1 K1 A6 C6 PD0 (4) PG0 (1) PB4 (4) PD5 (9) I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx B2 G2 K2 A3 PE4 (5) PD1 (4) PG1 (1) PD6 (9) O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 12.3 Functional Description Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 626). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in 602 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. 12.3.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 12-2 on page 603 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 12-2. UART Character Frame UnTX LSB 1 5-8 data bits 0 n Parity bit if enabled Start 12.3.2 1-2 stop bits MSB Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 622) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 623). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.) BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate) where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in UARTCTL is clear) or 8 (if HSE is set). The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to as Baud8 and Baud16, depending on the setting of the HSE bit (bit 5) in UARTCTL). This reference clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations. Note that the state of the HSE bit has no effect on clock generation in ISO 7816 smart card mode (when the SMART bit in the UARTCTL register is set). Along with the UART Line Control, High Byte (UARTLCRH) register (see page 624), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated July 22, 2011 603 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write ■ UARTFBRD write and UARTLCRH write 12.3.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 618) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 or fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL (described in “Transmit/Receive Logic” on page 603). The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE clear) or the fourth cycle of Baud 8 (HSE set), otherwise it is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one bit period later) according to the programmed length of the data characters and value of the HSE bit in UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO along with any error bits associated with that word. 12.3.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream and a half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output and decoded input to the UART. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol. These signals should be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception.The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as a high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light 604 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW and driving the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. See page 621 for more information on IrDA low-power pulse-duration configuration. Figure 12-3 on page 605 shows the UART transmit and receive signals, with and without IrDA modulation. Figure 12-3. IrDA Data Modulation Data bits Start bit UnTx 1 0 0 0 1 Stop bit 0 0 1 1 1 UnTx with IrDA 3 16 Bit period Bit period UnRx with IrDA UnRx 0 1 0 Start 1 0 0 1 1 Data bits 0 1 Stop In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10-ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency or receiver setup time. 12.3.5 ISO 7816 Support The UART offers basic support to allow communication with an ISO 7816 smartcard. When bit 3 (SMART) of the UARTCTL register is set, the UnTx signal is used as a bit clock, and the UnRx signal is used as the half-duplex communication line connected to the smartcard. A GPIO signal can be used to generate the reset signal to the smartcard. The remaining smartcard signals should be provided by the system design. The maximum clock rate in this mode is system clock / 16. When using ISO 7816 mode, the UARTLCRH register must be set to transmit 8-bit words (WLEN bits 6:5 configured to 0x3) with EVEN parity (PEN set and EPS set). In this mode, the UART automatically uses 2 stop bits, and the STP2 bit of the UARTLCRH register is ignored. If a parity error is detected during transmission, UnRx is pulled Low during the second stop bit. In this case, the UART aborts the transmission, flushes the transmit FIFO and discards any data it contains, and raises a parity error interrupt, allowing software to detect the problem and initiate July 22, 2011 605 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) retransmission of the affected data. Note that the UART does not support automatic retransmission in this case. 12.3.6 Modem Handshake Support This section describes how to configure and use the modem flow control and status signals for UART1 when connected as a DTE (data terminal equipment) or as a DCE (data communications equipment). In general, a modem is a DCE and a computing device that connects to a modem is the DTE. 12.3.6.1 Signaling The status signals provided by UART1 differ based on whether the UART is used as a DTE or DCE. When used as a DTE, the modem flow control and status signals are defined as: ■ U1CTS is Clear To Send ■ U1DSR is Data Set Ready ■ U1DCD is Data Carrier Detect ■ U1RI is Ring Indicator ■ U1RTS is Request To Send ■ U1DTR is Data Terminal Ready When used as a DCE, the the modem flow control and status signals are defined as: ■ U1CTS is Request To Send ■ U1DSR is Data Terminal Ready ■ U1RTS is Clear To Send ■ U1DTR is Data Set Ready Note that the support for DCE functions Data Carrier Detect and Ring Indicator are not provided. If these signals are required, their function can be emulated by using a general-purpose I/O signal and providing software support. 12.3.6.2 Flow Control Flow control can be accomplished by either hardware or software. The following sections describe the different methods. Hardware Flow Control (RTS/CTS) Hardware flow control between two devices is accomplished by connecting the U1RTS output to the Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the receiving device to the U1CTS input. The U1CTS input controls the transmitter. The transmitter may only transmit data when the U1CTS input is asserted. The U1RTS output signal indicates the state of the receive FIFO. U1CTS remains asserted until the preprogrammed watermark level is reached, indicating that the Receive FIFO has no space to store additional characters. 606 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller The UARTCTL register bits 15 (CTSEN) and 14 (RTSEN) specify the flow control mode as shown in Table 12-3 on page 607. Table 12-3. Flow Control Mode Description CTSEN RTSEN 1 1 RTS and CTS flow control enabled 1 0 Only CTS flow control enabled 0 1 Only RTS flow control enabled 0 0 Both RTS and CTS flow control disabled Note that when RTSEN is 1, software cannot modify the U1RTS output value through the UARTCTL register Request to Send (RTS) bit, and the status of the RTS bit should be ignored. Software Flow Control (Modem Status Interrupts) Software flow control between two devices is accomplished by using interrupts to indicate the status of the UART. Interrupts may be generated for the U1DSR, U1DCD, U1CTS, and U1RI signals using bits 3:0 of the UARTIM register, respectively. The raw and masked interrupt status may be checked using the UARTRIS and UARTMIS register. These interrupts may be cleared using the UARTICR register. 12.3.7 LIN Support The UART module offers hardware support for the LIN protocol as either a master or a slave. The LIN mode is enabled by setting the LIN bit in the UARTCTL register. A LIN message is identified by the use of a Sync Break at the beginning of the message. The Sync Break is a transmission of a series of 0s. The Sync Break is followed by the Sync data field (0x55). Figure 12-4 on page 607 illustrates the structure of a LIN message. Figure 12-4. LIN Message Message Frame Header Synch Break Synch Field Response Ident Field Data Field(s) In-Frame Response Data Field Checksum Field Interbyte Space The UART should be configured as followed to operate in LIN mode: 1. Configure the UART for 1 start bit, 8 data bits, no parity, and 1 stop bit. Enable the Transmit FIFO. 2. Set the LIN bit in the UARTCTL register. July 22, 2011 607 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) When preparing to send a LIN message, the TXFIFO should contain the Sync data (0x55) at FIFO location 0 and the Identifier data at location 1, followed by the data to be transmitted, and with the checksum in the final FIFO entry. 12.3.7.1 LIN Master The UART is enabled to be the LIN master by setting the MASTER bit in the UARTLCTL register. The length of the Sync Break is programmable using the BLEN field in the UARTLCTL register and can be 13-16 bits (baud clock cycles). 12.3.7.2 LIN Slave The LIN UART slave is required to adjust its baud rate to that of the LIN master. In slave mode, the LIN UART recognizes the Sync Break, which must be at least 13 bits in duration. A timer is provided to capture timing data on the 1st and 5th falling edges of the Sync field so that the baud rate can be adjusted to match the master. After detecting a Sync Break, the UART waits for the synchronization field. The first falling edge generates an interrupt using the LME1RIS bit in the UARTRIS register, and the timer value is captured and stored in the UARTLSS register (T1). On the fifth falling edge, a second interrupt is generated using the LME5RIS bit in the UARTRIS register, and the timer value is captured again (T2). The actual baud rate can be calculated using (T2-T1)/8, and the local baud rate should be adjusted as needed. Figure 12-5 on page 608 illustrates the synchronization field. Figure 12-5. LIN Synchronization Field Sync Break 0 1 2 3 4 5 6 7 8 Synch Field 9 10 11 12 13 0 1 2 Edge 1 3 4 5 6 Edge 5 7 8 8 Tbit Sync Break Detect 12.3.8 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 613). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 624). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 618) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 630). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include ⅛, ¼, ½, ¾, and ⅞. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 608 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 12.3.9 Interrupts The UART can generate interrupts when the following conditions are observed: ■ Overrun Error ■ Break Error ■ Parity Error ■ Framing Error ■ Receive Timeout ■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer) ■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 639). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM) register (see page 632) by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 636). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a 1 to the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 642). The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register. 12.3.10 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work by setting the LBE bit in the UARTCTL register (see page 626). In loopback mode, data transmitted on the UnTx output is received on the UnRx input. Note that the LBE bit should be set before the UART is enabled. 12.3.11 DMA Operation The UART provides an interface to the μDMA controller with separate channels for transmit and receive. The DMA operation of the UART is enabled through the UART DMA Control (UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger level configured in the UARTIFLS register. For the transmit channel, a single transfer request is asserted whenever there is at least one empty location in the transmit FIFO. The burst request is asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The July 22, 2011 609 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) single and burst DMA transfer requests are handled automatically by the μDMA controller depending on how the DMA channel is configured. To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control (UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive error occurs, the DMA receive requests are automatically disabled. This error condition can be cleared by clearing the appropriate UART error interrupt. If DMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The interrupt occurs on the UART interrupt vector. Therefore, if interrupts are used for UART operation and DMA is enabled, the UART interrupt handler must be designed to handle the μDMA completion interrupt. See “Micro Direct Memory Access (μDMA)” on page 333 for more details about programming the μDMA controller. 12.4 Initialization and Configuration To enable and initialize the UART, the following steps are necessary: 1. The peripheral clock must be enabled by setting the UART0, UART1, or UART2 bits in the RCGC1 register (see page 272). 2. The clock to the appropriate GPIO module must be enabled via the RCGC2 register in the System Control module (see page 281). 3. Set the GPIO AFSEL bits for the appropriate pins (see page 416). To determine which GPIOs to configure, see Table 23-4 on page 1137. 4. Configure the GPIO current level and/or slew rate as specified for the mode selected (see page 418 and page 426). 5. Configure the PMCn fields in the GPIOPCTL register to assign the UART signals to the appropriate pins (see page 434 and Table 23-5 on page 1145). To use the UART, the peripheral clock must be enabled by setting the appropriate bit in the RCGC1 register (page 272). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2 register (page 281) in the System Control module. To find out which GPIO port to enable, refer to Table 23-5 on page 1145. This section discusses the steps that are required to use a UART module. For this example, the UART clock is assumed to be 20 MHz, and the desired UART configuration is: ■ 115200 baud rate ■ Data length of 8 bits ■ One stop bit ■ No parity ■ FIFOs disabled ■ No interrupts 610 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller The first thing to consider when programming the UART is the baud-rate divisor (BRD), because the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 603, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 622) should be set to 10 decimal or 0xA. The value to be loaded into the UARTFBRD register (see page 623) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 333) and enable the DMA option(s) in the UARTDMACTL register. 6. Enable the UART by setting the UARTEN bit in the UARTCTL register. 12.5 Register Map Table 12-4 on page 611 lists the UART registers. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address: ■ UART0: 0x4000.C000 ■ UART1: 0x4000.D000 ■ UART2: 0x4000.E000 Note that the UART module clock must be enabled before the registers can be programmed (see page 272). There must be a delay of 3 system clocks after the UART module clock is enabled before any UART module registers are accessed. Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 626) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 12-4. UART Register Map Offset Name Type Reset Description See page 0x000 UARTDR R/W 0x0000.0000 UART Data 613 0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 615 0x018 UARTFR RO 0x0000.0090 UART Flag 618 0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 621 0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 622 July 22, 2011 611 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Table 12-4. UART Register Map (continued) Name Type Reset 0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 623 0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 624 0x030 UARTCTL R/W 0x0000.0300 UART Control 626 0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 630 0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 632 0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 636 0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 639 0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 642 0x048 UARTDMACTL R/W 0x0000.0000 UART DMA Control 644 0x090 UARTLCTL R/W 0x0000.0000 UART LIN Control 645 0x094 UARTLSS RO 0x0000.0000 UART LIN Snap Shot 646 0x098 UARTLTIM RO 0x0000.0000 UART LIN Timer 647 0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 648 0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 649 0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 650 0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 651 0xFE0 UARTPeriphID0 RO 0x0000.0060 UART Peripheral Identification 0 652 0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 653 0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 654 0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 655 0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 656 0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 657 0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 658 0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 659 12.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. 612 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 1: UART Data (UARTDR), offset 0x000 Important: This register is read-sensitive. See the register description for details. This register is the data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 OE BE PE FE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 OE RO 0 DATA Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Value Description 10 BE RO 0 1 New data was received when the FIFO was full, resulting in data loss. 0 No data has been lost due to a FIFO overrun. UART Break Error Value Description 1 A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0 No break condition has occurred In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state), and the next valid start bit is received. July 22, 2011 613 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 9 PE RO 0 Description UART Parity Error Value Description 1 The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0 No parity error has occurred In FIFO mode, this error is associated with the character at the top of the FIFO. 8 FE RO 0 UART Framing Error Value Description 7:0 DATA R/W 0x00 1 The received character does not have a valid stop bit (a valid stop bit is 1). 0 No framing error has occurred Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 614 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared on reset. Read-Only Status Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 OE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 OE BE PE FE RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Value Description 1 New data was received when the FIFO was full, resulting in data loss. 0 No data has been lost due to a FIFO overrun. This bit is cleared by a write to UARTECR. The FIFO contents remain valid because no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO. July 22, 2011 615 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 2 BE RO 0 Description UART Break Error Value Description 1 A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 0 No break condition has occurred This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 1 PE RO 0 UART Parity Error Value Description 1 The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. 0 No parity error has occurred This bit is cleared to 0 by a write to UARTECR. 0 FE RO 0 UART Framing Error Value Description 1 The received character does not have a valid stop bit (a valid stop bit is 1). 0 No framing error has occurred This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. Write-Only Error Clear Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset WO 0 DATA 616 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 31:8 reserved WO 0x0000.00 7:0 DATA WO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. July 22, 2011 617 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. The RI, DCD, DSR and CTS bits indicate the modem flow control and status. Note that the modem bits are only implemented on UART1 and are reserved on UART0 and UART2. UART Flag (UARTFR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RI TXFE RXFF TXFF RXFE BUSY DCD DSR CTS RO 0 RO 1 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:9 reserved RO 0x0000.00 8 RI RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Ring Indicator Value Description 1 The U1RI signal is asserted. 0 The U1RI signal is not asserted. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 7 TXFE RO 1 UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. Value Description 1 If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. 0 The transmitter has data to transmit. 618 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 6 RXFF RO 0 Description UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. Value Description 1 If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. 0 5 TXFF RO 0 The receiver can receive data. UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. Value Description 1 If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0 4 RXFE RO 1 The transmitter is not full. UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. Value Description 1 If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. 0 3 BUSY RO 0 The receiver is not empty. UART Busy Value Description 1 The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. 0 The UART is not busy. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 2 DCD RO 0 Data Carrier Detect Value Description 1 The U1DCD signal is asserted. 0 The U1DCD signal is not asserted. This bit is implemented only on UART1 and is reserved for UART0 and UART2. July 22, 2011 619 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 1 DSR RO 0 Description Data Set Ready Value Description 1 The U1DSR signal is asserted. 0 The U1DSR signal is not asserted. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 0 CTS RO 0 Clear To Send Value Description 1 The U1CTS signal is asserted. 0 The U1CTS signal is not asserted. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 620 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when reset. The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. The divisor must be programmed such that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, resulting in a low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but pulses greater than 1.4 μs are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset ILPDVSR RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 ILPDVSR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. IrDA Low-Power Divisor This field contains the 8-bit low-power divisor value. July 22, 2011 621 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 603 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset DIVINT Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor 622 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 603 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 DIVFRAC Bit/Field Name Type Reset 31:6 reserved RO 0x0000.000 5:0 DIVFRAC R/W 0x0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fractional Baud-Rate Divisor July 22, 2011 623 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 SPS RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 SPS R/W 0 RO 0 R/W 0 5 WLEN R/W 0 R/W 0 4 3 2 1 0 FEN STP2 EPS PEN BRK R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 6:5 WLEN R/W 0x0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 4 FEN R/W 0 0x0 5 bits (default) 0x1 6 bits 0x2 7 bits 0x3 8 bits UART Enable FIFOs Value Description 1 The transmit and receive FIFO buffers are enabled (FIFO mode). 0 The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 624 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 3 STP2 R/W 0 Description UART Two Stop Bits Select Value Description 1 Two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. When in 7816 smartcard mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0 2 EPS R/W 0 One stop bit is transmitted at the end of a frame. UART Even Parity Select Value Description 1 Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 0 Odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 1 PEN R/W 0 UART Parity Enable Value Description 0 BRK R/W 0 1 Parity checking and generation is enabled. 0 Parity is disabled and no parity bit is added to the data frame. UART Send Break Value Description 1 A Low level is continually output on the UnTx signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). 0 Normal use. July 22, 2011 625 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set. To enable the UART module, the UARTEN bit must be set. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. Note that bits [15:14,11:10] are only implemented on UART1. These bits are reserved on UART0 and UART2. Note: The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register. 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by clearing bit 4 (FEN) in the line control register (UARTLCRH). 4. Reprogram the control register. 5. Enable the UART. UART Control (UARTCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 Type Reset RO 0 RO 0 RO 0 13 12 15 14 CTSEN RTSEN R/W 0 R/W 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 6 5 4 3 2 1 0 RTS DTR RXE TXE LBE LIN HSE EOT SMART SIRLP SIREN UARTEN R/W 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 626 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 15 CTSEN R/W 0 Description Enable Clear To Send Value Description 1 CTS hardware flow control is enabled. Data is only transmitted when the U1CTS signal is asserted. 0 CTS hardware flow control is disabled. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 14 RTSEN R/W 0 Enable Request to Send Value Description 1 RTS hardware flow control is enabled. Data is only requested (by asserting U1RTS) when the receive FIFO has available entries. 0 RTS hardware flow control is disabled. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 13:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 RTS R/W 0 Request to Send When RTSEN is clear, the status of this bit is reflected on the U1RTS signal. If RTSEN is set, this bit is ignored on a write and should be ignored on read. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 10 DTR R/W 0 Data Terminal Ready This bit sets the state of the U1DTR output. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 9 RXE R/W 1 UART Receive Enable Value Description 1 The receive section of the UART is enabled. 0 The receive section of the UART is disabled. If the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: To enable reception, the UARTEN bit must also be set. July 22, 2011 627 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 8 TXE R/W 1 Description UART Transmit Enable Value Description 1 The transmit section of the UART is enabled. 0 The transmit section of the UART is disabled. If the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: 7 LBE R/W 0 To enable transmission, the UARTEN bit must also be set. UART Loop Back Enable Value Description 6 LIN R/W 0 1 The UnTx path is fed through the UnRx path. 0 Normal operation. LIN Mode Enable Value Description 5 HSE R/W 0 1 The UART operates in LIN mode. 0 Normal operation. High-Speed Enable Value Description 0 The UART is clocked using the system clock divided by 16. 1 The UART is clocked using the system clock divided by 8. Note: System clock used is also dependent on the baud-rate divisor configuration (see page 622) and page 623). The state of this bit has no effect on clock generation in ISO 7816 smart card mode (the SMART bit is set). 4 EOT R/W 0 End of Transmission This bit determines the behavior of the TXRIS bit in the UARTRIS register. Value Description 1 The TXRIS bit is set only after all transmitted data, including stop bits, have cleared the serializer. 0 The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met. 628 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 3 SMART R/W 0 Description ISO 7816 Smart Card Support Value Description 1 The UART operates in Smart Card mode. 0 Normal operation. The application must ensure that it sets 8-bit word length (WLEN set to 0x3) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO 7816 mode. In this mode, the value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. Note that the UART does not support automatic retransmission on parity errors. If a parity error is detected on transmission, all further transmit operations are aborted and software must handle retransmission of the affected byte or message. 2 SIRLP R/W 0 UART SIR Low-Power Mode This bit selects the IrDA encoding mode. Value Description 1 The UART operates in SIR Low-Power mode. Low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. 0 Low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. Setting this bit uses less power, but might reduce transmission distances. See page 621 for more information. 1 SIREN R/W 0 UART SIR Enable Value Description 0 UARTEN R/W 0 1 The IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 0 Normal operation. UART Enable Value Description 1 The UART is enabled. 0 The UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. July 22, 2011 629 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x034 Type R/W, reset 0x0000.0012 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RXIFLSEL Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:3 RXIFLSEL R/W 0x2 R/W 1 TXIFLSEL R/W 1 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Value Description 0x0 RX FIFO ≥ ⅛ full 0x1 RX FIFO ≥ ¼ full 0x2 RX FIFO ≥ ½ full (default) 0x3 RX FIFO ≥ ¾ full 0x4 RX FIFO ≥ ⅞ full 0x5-0x7 Reserved 630 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 2:0 TXIFLSEL R/W 0x2 Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value Description 0x0 TX FIFO ≤ ⅞ empty 0x1 TX FIFO ≤ ¾ empty 0x2 TX FIFO ≤ ½ empty (default) 0x3 TX FIFO ≤ ¼ empty 0x4 TX FIFO ≤ ⅛ empty 0x5-0x7 Reserved Note: If the EOT bit in UARTCTL is set (see page 626), the transmit interrupt is generated once the FIFO is completely empty and all data including stop bits have left the transmit serializer. In this case, the setting of TXIFLSEL is ignored. July 22, 2011 631 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller. Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2. UART Interrupt Mask (UARTIM) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 LME5IM LME1IM LMSBIM OEIM R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BEIM PEIM FEIM RTIM TXIM RXIM DSRIM DCDIM CTSIM RIIM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset reserved RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 LME5IM R/W 0 LIN Mode Edge 5 Interrupt Mask Value Description 14 LME1IM R/W 0 1 An interrupt is sent to the interrupt controller when the LME5RIS bit in the UARTRIS register is set. 0 The LME5RIS interrupt is suppressed and not sent to the interrupt controller. LIN Mode Edge 1 Interrupt Mask Value Description 13 LMSBIM R/W 0 1 An interrupt is sent to the interrupt controller when the LME1RIS bit in the UARTRIS register is set. 0 The LME1RIS interrupt is suppressed and not sent to the interrupt controller. LIN Mode Sync Break Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the LMSBRIS bit in the UARTRIS register is set. 0 The LMSBRIS interrupt is suppressed and not sent to the interrupt controller. 632 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 12:11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIM R/W 0 UART Overrun Error Interrupt Mask Value Description 9 BEIM R/W 0 1 An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set. 0 The OERIS interrupt is suppressed and not sent to the interrupt controller. UART Break Error Interrupt Mask Value Description 8 PEIM R/W 0 1 An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set. 0 The BERIS interrupt is suppressed and not sent to the interrupt controller. UART Parity Error Interrupt Mask Value Description 7 FEIM R/W 0 1 An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set. 0 The PERIS interrupt is suppressed and not sent to the interrupt controller. UART Framing Error Interrupt Mask Value Description 6 RTIM R/W 0 1 An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set. 0 The FERIS interrupt is suppressed and not sent to the interrupt controller. UART Receive Time-Out Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set. 0 The RTRIS interrupt is suppressed and not sent to the interrupt controller. July 22, 2011 633 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 5 TXIM R/W 0 Description UART Transmit Interrupt Mask Value Description 4 RXIM R/W 0 1 An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set. 0 The TXRIS interrupt is suppressed and not sent to the interrupt controller. UART Receive Interrupt Mask Value Description 3 DSRIM R/W 0 1 An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set. 0 The RXRIS interrupt is suppressed and not sent to the interrupt controller. UART Data Set Ready Modem Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the DSRRIS bit in the UARTRIS register is set. 0 The DSRRIS interrupt is suppressed and not sent to the interrupt controller. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 2 DCDIM R/W 0 UART Data Carrier Detect Modem Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the DCDRIS bit in the UARTRIS register is set. 0 The DCDRIS interrupt is suppressed and not sent to the interrupt controller. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 1 CTSIM R/W 0 UART Clear to Send Modem Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the CTSRIS bit in the UARTRIS register is set. 0 The CTSRIS interrupt is suppressed and not sent to the interrupt controller. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 634 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 RIIM R/W 0 Description UART Ring Indicator Modem Interrupt Mask Value Description 1 An interrupt is sent to the interrupt controller when the RIRIS bit in the UARTRIS register is set. 0 The RIRIS interrupt is suppressed and not sent to the interrupt controller. This bit is implemented only on UART1 and is reserved for UART0 and UART2. July 22, 2011 635 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x03C Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 LME5RIS LME1RIS LMSBRIS Type Reset RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 3 2 1 0 OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS DSRRIS DCDRIS CTSRIS RIRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 LME5RIS RO 0 LIN Mode Edge 5 Raw Interrupt Status Value Description 1 The timer value at the 5th falling edge of the LIN Sync Field has been captured. 0 No interrupt This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR register. 14 LME1RIS RO 0 LIN Mode Edge 1 Raw Interrupt Status Value Description 1 The timer value at the 1st falling edge of the LIN Sync Field has been captured. 0 No interrupt This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR register. 13 LMSBRIS RO 0 LIN Mode Sync Break Raw Interrupt Status Value Description 1 A LIN Sync Break has been detected. 0 No interrupt This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR register. 636 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 12:11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OERIS RO 0 UART Overrun Error Raw Interrupt Status Value Description 1 An overrun error has occurred. 0 No interrupt This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register. 9 BERIS RO 0 UART Break Error Raw Interrupt Status Value Description 1 A break error has occurred. 0 No interrupt This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register. 8 PERIS RO 0 UART Parity Error Raw Interrupt Status Value Description 1 A parity error has occurred. 0 No interrupt This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register. 7 FERIS RO 0 UART Framing Error Raw Interrupt Status Value Description 1 A framing error has occurred. 0 No interrupt This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register. 6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status Value Description 1 A receive time out has occurred. 0 No interrupt This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register. 5 TXRIS RO 0 UART Transmit Raw Interrupt Status Value Description 1 If the EOT bit in the UARTCTL register is clear, the transmit FIFO level has passed through the condition defined in the UARTIFLS register. If the EOT bit is set, the last bit of all transmitted data and flags has left the serializer. 0 No interrupt This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register. July 22, 2011 637 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 4 RXRIS RO 0 Description UART Receive Raw Interrupt Status Value Description 1 The receive FIFO level has passed through the condition defined in the UARTIFLS register. 0 No interrupt This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register. 3 DSRRIS RO 0 UART Data Set Ready Modem Raw Interrupt Status Value Description 1 Data Set Ready used for software flow control. 0 No interrupt This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 2 DCDRIS RO 0 UART Data Carrier Detect Modem Raw Interrupt Status Value Description 1 Data Carrier Detect used for software flow control. 0 No interrupt This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 1 CTSRIS RO 0 UART Clear to Send Modem Raw Interrupt Status Value Description 1 Clear to Send used for software flow control. 0 No interrupt This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 0 RIRIS RO 0 UART Ring Indicator Modem Raw Interrupt Status Value Description 1 Ring Indicator used for software flow control. 0 No interrupt This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 638 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x040 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 LME5MIS LME1MIS LMSBMIS Type Reset RO 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 DSRMIS DCDMIS RO 0 RO 0 1 0 CTSMIS RIMIS RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 LME5MIS RO 0 LIN Mode Edge 5 Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to the 5th falling edge of the LIN Sync Field. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR register. 14 LME1MIS RO 0 LIN Mode Edge 1 Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to the 1st falling edge of the LIN Sync Field. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR register. 13 LMSBMIS RO 0 LIN Mode Sync Break Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to the receipt of a LIN Sync Break. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR register. July 22, 2011 639 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description 12:11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEMIS RO 0 UART Overrun Error Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to an overrun error. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register. 9 BEMIS RO 0 UART Break Error Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a break error. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register. 8 PEMIS RO 0 UART Parity Error Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a parity error. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register. 7 FEMIS RO 0 UART Framing Error Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a framing error. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register. 6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to a receive time out. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register. 5 TXMIS RO 0 UART Transmit Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to passing through the specified transmit FIFO level (if the EOT bit is clear) or due to the transmission of the last data bit (if the EOT bit is set). 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register. 640 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 4 RXMIS RO 0 Description UART Receive Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to passing through the specified receive FIFO level. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register. 3 DSRMIS RO 0 UART Data Set Ready Modem Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to Data Set Ready. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 2 DCDMIS RO 0 UART Data Carrier Detect Modem Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to Data Carrier Detect. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 1 CTSMIS RO 0 UART Clear to Send Modem Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to Clear to Send. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 0 RIMIS RO 0 UART Ring Indicator Modem Masked Interrupt Status Value Description 1 An unmasked interrupt was signaled due to Ring Indicator. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. July 22, 2011 641 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x044 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 reserved Type Reset RO 0 Type Reset RO 0 RO 0 RO 0 RO 0 12 11 15 14 13 LME5IC LME1IC LMSBIC W1C 0 W1C 0 W1C 0 RO 0 reserved RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 4 OEIC BEIC PEIC FEIC RTIC TXIC RXIC W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 DSRMIC DCDMIC CTSMIC W1C 0 W1C 0 W1C 0 0 RIMIC W1C 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 LME5IC W1C 0 LIN Mode Edge 5 Interrupt Clear Writing a 1 to this bit clears the LME5RIS bit in the UARTRIS register and the LME5MIS bit in the UARTMIS register. 14 LME1IC W1C 0 LIN Mode Edge 1 Interrupt Clear Writing a 1 to this bit clears the LME1RIS bit in the UARTRIS register and the LME1MIS bit in the UARTMIS register. 13 LMSBIC W1C 0 LIN Mode Sync Break Interrupt Clear Writing a 1 to this bit clears the LMSBRIS bit in the UARTRIS register and the LMSBMIS bit in the UARTMIS register. 12:11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 OEIC W1C 0 Overrun Error Interrupt Clear Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and the OEMIS bit in the UARTMIS register. 9 BEIC W1C 0 Break Error Interrupt Clear Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and the BEMIS bit in the UARTMIS register. 8 PEIC W1C 0 Parity Error Interrupt Clear Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and the PEMIS bit in the UARTMIS register. 642 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 7 FEIC W1C 0 Description Framing Error Interrupt Clear Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and the FEMIS bit in the UARTMIS register. 6 RTIC W1C 0 Receive Time-Out Interrupt Clear Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and the RTMIS bit in the UARTMIS register. 5 TXIC W1C 0 Transmit Interrupt Clear Writing a 1 to this bit clears the TXRIS bit in the UARTRIS register and the TXMIS bit in the UARTMIS register. 4 RXIC W1C 0 Receive Interrupt Clear Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and the RXMIS bit in the UARTMIS register. 3 DSRMIC W1C 0 UART Data Set Ready Modem Interrupt Clear Writing a 1 to this bit clears the DSRRIS bit in the UARTRIS register and the DSRMIS bit in the UARTMIS register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 2 DCDMIC W1C 0 UART Data Carrier Detect Modem Interrupt Clear Writing a 1 to this bit clears the DCDRIS bit in the UARTRIS register and the DCDMIS bit in the UARTMIS register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 1 CTSMIC W1C 0 UART Clear to Send Modem Interrupt Clear Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register and the CTSMIS bit in the UARTMIS register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. 0 RIMIC W1C 0 UART Ring Indicator Modem Interrupt Clear Writing a 1 to this bit clears the RIRIS bit in the UARTRIS register and the RIMIS bit in the UARTMIS register. This bit is implemented only on UART1 and is reserved for UART0 and UART2. July 22, 2011 643 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 14: UART DMA Control (UARTDMACTL), offset 0x048 The UARTDMACTL register is the DMA control register. UART DMA Control (UARTDMACTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x048 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type 31:3 reserved RO 2 DMAERR R/W RO 0 Reset DMAERR TXDMAE RXDMAE R/W 0 R/W 0 R/W 0 Description 0x00000.000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 DMA on Error Value Description 1 TXDMAE R/W 0 1 µDMA receive requests are automatically disabled when a receive error occurs. 0 µDMA receive requests are unaffected when a receive error occurs. Transmit DMA Enable Value Description 0 RXDMAE R/W 0 1 µDMA for the transmit FIFO is enabled. 0 µDMA for the transmit FIFO is disabled. Receive DMA Enable Value Description 1 µDMA for the receive FIFO is enabled. 0 µDMA for the receive FIFO is disabled. 644 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 15: UART LIN Control (UARTLCTL), offset 0x090 The UARTLCTL register is the configures the operation of the UART when in LIN mode. UART LIN Control (UARTLCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x090 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset RO 0 BLEN Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:4 BLEN R/W 0x0 reserved RO 0 MASTER RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Sync Break Length Value Description 3:1 reserved RO 0x0 0 MASTER R/W 0 0x3 Sync break length is 16T bits 0x2 Sync break length is 15T bits 0x1 Sync break length is 14T bits 0x0 Sync break length is 13T bits (default) Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LIN Master Enable Value Description 1 The UART operates as a LIN master. 0 The UART operates as a LIN slave. July 22, 2011 645 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094 The UARTLSS register captures the free-running timer value when either the Sync Edge 1 or the Sync Edge 5 is detected in LIN mode. UART LIN Snap Shot (UARTLSS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x094 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset TSS Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TSS RO 0x0000 Timer Snap Shot This field contains the value of the free-running timer when either the Sync Edge 5 or the Sync Edge 1 was detected. 646 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 17: UART LIN Timer (UARTLTIM), offset 0x098 The UARTLTIM register contains the current timer value for the free-running timer that is used to calculate the baud rate when in LIN slave mode. The value in this register is used along with the value in the UART LIN Snap Shot (UARTLSS) register to adjust the baud rate to match that of the master. UART LIN Timer (UARTLTIM) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x098 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset TIMER Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TIMER RO 0x0000 Timer Value This field contains the value of the free-running timer. July 22, 2011 647 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 18: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 648 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 19: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID5 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 22, 2011 649 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 20: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID6 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 650 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 21: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID7 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 22, 2011 651 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 22: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE0 Type RO, reset 0x0000.0060 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x60 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 652 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 23: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 22, 2011 653 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 24: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x18 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 654 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 25: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x01 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 22, 2011 655 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 26: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 656 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 27: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. July 22, 2011 657 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) Register 28: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID2 RO 0x05 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 658 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 29: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID3 RO 0xB1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. July 22, 2011 659 Texas Instruments-Production Data Synchronous Serial Interface (SSI) 13 Synchronous Serial Interface (SSI) ® The Stellaris microcontroller includes two Synchronous Serial Interface (SSI) modules. Each SSI is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. The Stellaris LM3S9L71 controller includes two SSI modules with the following features: ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Master or slave operation ■ Programmable clock bit rate and prescaler ■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing ■ Standard FIFO-based interrupts and End-of-Transmission interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries – Transmit single request asserted when there is space in the FIFO; burst request asserted when FIFO contains 4 entries 660 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 13.1 Block Diagram Figure 13-1. SSI Module Block Diagram DMA Request DMA Control SSIDMACTL Interrupt Interrupt Control TxFIFO 8 x 16 SSIIM SSIMIS SSIRIS SSIICR . . . Control/Status SSITx SSICR0 SSICR1 SSISR SSIRx Transmit/ Receive Logic SSIDR RxFIFO 8 x 16 Clock Prescaler System Clock SSIClk SSIFss . . . SSICPSR Identification Registers SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 13.2 SSIPeriphID0 SSIPeriphID1 SSIPeriphID2 SSIPeriphID3 SSIPeriphID4 SSIPeriphID5 SSIPeriphID6 SSIPeriphID7 Signal Description The following table lists the external signals of the SSI module and describes the function of each. The SSI signals are alternate functions for some GPIO signals and default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the SSI function. The number in July 22, 2011 661 Texas Instruments-Production Data Synchronous Serial Interface (SSI) parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the SSI signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. Table 13-1. Signals for SSI (100LQFP) Pin Name SSI0Clk Pin Number Pin Mux / Pin Assignment 28 a Pin Type Buffer Type PA2 (1) I/O TTL Description SSI module 0 clock. SSI0Fss 29 PA3 (1) I/O TTL SSI module 0 frame. SSI0Rx 30 PA4 (1) I TTL SSI module 0 receive. SSI0Tx 31 PA5 (1) O TTL SSI module 0 transmit. SSI1Clk 60 74 76 PF2 (9) PE0 (2) PH4 (11) I/O TTL SSI module 1 clock. SSI1Fss 59 63 75 PF3 (9) PH5 (11) PE1 (2) I/O TTL SSI module 1 frame. SSI1Rx 58 62 95 PF4 (9) PH6 (11) PE2 (2) I TTL SSI module 1 receive. SSI1Tx 15 46 96 PH7 (11) PF5 (9) PE3 (2) O TTL SSI module 1 transmit. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 13-2. Signals for SSI (108BGA) Pin Name SSI0Clk Pin Number Pin Mux / Pin Assignment M4 a Pin Type Buffer Type PA2 (1) I/O TTL Description SSI module 0 clock. SSI0Fss L4 PA3 (1) I/O TTL SSI module 0 frame. SSI0Rx L5 PA4 (1) I TTL SSI module 0 receive. SSI0Tx M5 PA5 (1) O TTL SSI module 0 transmit. SSI1Clk J11 B11 B10 PF2 (9) PE0 (2) PH4 (11) I/O TTL SSI module 1 clock. SSI1Fss J12 F10 A12 PF3 (9) PH5 (11) PE1 (2) I/O TTL SSI module 1 frame. SSI1Rx L9 G3 A4 PF4 (9) PH6 (11) PE2 (2) I TTL SSI module 1 receive. SSI1Tx H3 L8 B4 PH7 (11) PF5 (9) PE3 (2) O TTL SSI module 1 transmit. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 13.3 Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit 662 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller and receive modes. The SSI also supports the µDMA interface. The transmit and receive FIFOs can be programmed as destination/source addresses in the µDMA module. µDMA operation is enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 689). 13.3.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 682). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register (see page 675). The frequency of the output clock SSIClk is defined by: SSIClk = SysClk / (CPSDVSR * (1 + SCR)) Note: For master mode, the system clock must be at least two times faster than the SSIClk, with the restriction that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock must be at least 12 times faster than the SSIClk. See “Synchronous Serial Interface (SSI)” on page 1200 to view SSI timing parameters. 13.3.2 FIFO Operation 13.3.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 679), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or a µDMA request when the FIFO is empty. 13.3.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 13.3.3 Interrupts The SSI can generate interrupts when the following conditions are observed: ■ Transmit FIFO service (when the transmit FIFO is half full or less) ■ Receive FIFO service (when the receive FIFO is half full or more) July 22, 2011 663 Texas Instruments-Production Data Synchronous Serial Interface (SSI) ■ Receive FIFO time-out ■ Receive FIFO overrun ■ End of transmission All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI generates a single interrupt request to the controller regardless of the number of active interrupts. Each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt Mask (SSIIM) register (see page 683). Setting the appropriate mask bit enables the interrupt. The individual outputs, along with a combined interrupt output, allow use of either a global interrupt service routine or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 684 and page 686, respectively). The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is emptied before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing a 1 to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared so late that the ISR returns before the interrupt is actually cleared, or the ISR may be re-activated unnecessarily. The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This interrupt can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In addition, because transmitted data and received data complete at exactly the same time, the interrupt can also indicate that read data is ready immediately, without waiting for the receive FIFO time-out period to complete. 13.3.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: ■ Texas Instruments synchronous serial ■ Freescale SPI ■ MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk and latch data from the other device on the falling edge. 664 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 13.3.4.1 Texas Instruments Synchronous Serial Frame Format Figure 13-2 on page 665 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on each falling edge of SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 13-3 on page 665 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits July 22, 2011 665 Texas Instruments-Production Data Synchronous Serial Interface (SSI) 13.3.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits in the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is clear, it produces a steady state Low value on the SSIClk pin. If the SPO bit is set, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is clear, data is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second clock edge transition. 13.3.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 13-4 on page 666 and Figure 13-5 on page 666. Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB MSB Q 4 to 16 bits SSITx MSB Note: LSB Q is undefined. Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB LSB MSB MSB 4 to16 bits SSITx LSB MSB LSB MSB In this configuration, during idle periods: ■ SSIClk is forced Low 666 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, causing slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Once both the master and slave data have been set, the SSIClk master clock pin goes High after one additional half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 13.3.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 13-6 on page 667, which covers both single and continuous transfers. Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 SSIClk SSIFss SSIRx Q Q MSB LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad July 22, 2011 667 Texas Instruments-Production Data Synchronous Serial Interface (SSI) ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After an additional one-half SSIClk period, both master and slave valid data are enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words, and termination is the same as that of the single word transfer. 13.3.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 13-7 on page 668 and Figure 13-8 on page 668. Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSIRx MSB LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined. Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRx MSB LSB LSB MSB 4 to 16 bits In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad 668 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, causing slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One-half period later, valid master data is transferred to the SSITx line. Once both the master and slave data have been set, the SSIClk master clock pin becomes Low after one additional half SSIClk period, meaning that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 13.3.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 13-9 on page 669, which covers both single and continuous transfers. Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 SSIClk SSIFss SSIRx Q MSB LSB Q 4 to 16 bits MSB SSITx Note: LSB Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After an additional one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. July 22, 2011 669 Texas Instruments-Production Data Synchronous Serial Interface (SSI) After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state until the final bit of the last word has been captured and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 13.3.4.7 MICROWIRE Frame Format Figure 13-10 on page 670 shows the MICROWIRE frame format for a single frame. Figure 13-11 on page 671 shows the same format when back-to-back frames are transmitted. Figure 13-10. MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSITx LSB MSB 8-bit control 0 SSIRx MSB LSB 4 to 16 bits output data MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex and uses a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on each rising edge of SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, causing the data to be transferred to the receive FIFO. 670 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) SSIClk SSIFss SSITx LSB MSB LSB 8-bit control SSIRx 0 MSB MSB LSB 4 to 16 bits output data In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 13-12 on page 671 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements tSetup=(2*tSSIClk) tHold=tSSIClk SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave 13.3.5 DMA Operation The SSI peripheral provides an interface to the μDMA controller with separate channels for transmit and receive. The µDMA operation of the SSI is enabled through the SSI DMA Control (SSIDMACTL) register. When µDMA operation is enabled, the SSI asserts a µDMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is 4 or more items. For the transmit channel, a single transfer request is asserted whenever at least one empty location is in the transmit FIFO. The burst request is asserted whenever the transmit FIFO has 4 or more empty slots. The July 22, 2011 671 Texas Instruments-Production Data Synchronous Serial Interface (SSI) single and burst µDMA transfer requests are handled automatically by the μDMA controller depending how the µDMA channel is configured. To enable µDMA operation for the receive channel, the RXDMAE bit of the DMA Control (SSIDMACTL) register should be set. To enable µDMA operation for the transmit channel, the TXDMAE bit of SSIDMACTL should be set. If µDMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The interrupt occurs on the SSI interrupt vector. Therefore, if interrupts are used for SSI operation and µDMA is enabled, the SSI interrupt handler must be designed to handle the μDMA completion interrupt. See “Micro Direct Memory Access (μDMA)” on page 333 for more details about programming the μDMA controller. 13.4 Initialization and Configuration To enable and initialize the SSI, the following steps are necessary: 1. Enable the SSI module by setting the SSI bit in the RCGC1 register (see page 272). 2. Enable the clock to the appropriate GPIO module via the RCGC2 register (see page 281). To find out which GPIO port to enable, refer to Table 23-5 on page 1145. 3. Set the GPIO AFSEL bits for the appropriate pins (see page 416). To determine which GPIOs to configure, see Table 23-4 on page 1137. 4. Configure the PMCn fields in the GPIOPCTL register to assign the SSI signals to the appropriate pins. See page 434 and Table 23-5 on page 1145. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x0000.0000. b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. 4. Write the SSICR0 register with the following configuration: ■ Serial clock rate (SCR) ■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) ■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) ■ The data size (DSS) 5. Optionally, configure the μDMA channel (see “Micro Direct Memory Access (μDMA)” on page 333) and enable the DMA option(s) in the SSIDMACTL register. 6. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: 672 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ Master operation ■ Freescale SPI mode (SPO=1, SPH=1) ■ 1 Mbps bit rate ■ 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: SSIClk = SysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=0x2, SCR must be 0x9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is clear. 2. Write the SSICR1 register with a value of 0x0000.0000. 3. Write the SSICPSR register with a value of 0x0000.0002. 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register. 13.5 Register Map Table 13-3 on page 673 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s address, relative to that SSI module’s base address: ■ SSI0: 0x4000.8000 ■ SSI1: 0x4000.9000 Note that the SSI module clock must be enabled before the registers can be programmed (see page 272). There must be a delay of 3 system clocks after the SSI module clock is enabled before any SSI module registers are accessed. Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. Table 13-3. SSI Register Map Offset Name Type Reset Description See page 0x000 SSICR0 R/W 0x0000.0000 SSI Control 0 675 0x004 SSICR1 R/W 0x0000.0000 SSI Control 1 677 0x008 SSIDR R/W 0x0000.0000 SSI Data 679 0x00C SSISR RO 0x0000.0003 SSI Status 680 0x010 SSICPSR R/W 0x0000.0000 SSI Clock Prescale 682 0x014 SSIIM R/W 0x0000.0000 SSI Interrupt Mask 683 July 22, 2011 673 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Table 13-3. SSI Register Map (continued) Name Type Reset 0x018 SSIRIS RO 0x0000.0008 SSI Raw Interrupt Status 684 0x01C SSIMIS RO 0x0000.0000 SSI Masked Interrupt Status 686 0x020 SSIICR W1C 0x0000.0000 SSI Interrupt Clear 688 0x024 SSIDMACTL R/W 0x0000.0000 SSI DMA Control 689 0xFD0 SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 690 0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 691 0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 692 0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 693 0xFE0 SSIPeriphID0 RO 0x0000.0022 SSI Peripheral Identification 0 694 0xFE4 SSIPeriphID1 RO 0x0000.0000 SSI Peripheral Identification 1 695 0xFE8 SSIPeriphID2 RO 0x0000.0018 SSI Peripheral Identification 2 696 0xFEC SSIPeriphID3 RO 0x0000.0001 SSI Peripheral Identification 3 697 0xFF0 SSIPCellID0 RO 0x0000.000D SSI PrimeCell Identification 0 698 0xFF4 SSIPCellID1 RO 0x0000.00F0 SSI PrimeCell Identification 1 699 0xFF8 SSIPCellID2 RO 0x0000.0005 SSI PrimeCell Identification 2 700 0xFFC SSIPCellID3 RO 0x0000.00B1 SSI PrimeCell Identification 3 701 13.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. 674 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 1: SSI Control 0 (SSICR0), offset 0x000 The SSICR0 register contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 SPH SPO R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset SCR Type Reset Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15:8 SCR R/W 0x00 FRF R/W 0 DSS Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Serial Clock Rate This bit field is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=SysClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 7 SPH R/W 0 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. This bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. Value Description 6 SPO R/W 0 0 Data is captured on the first clock edge transition. 1 Data is captured on the second clock edge transition. SSI Serial Clock Polarity Value Description 0 A steady state Low value is placed on the SSIClk pin. 1 A steady state High value is placed on the SSIClk pin when data is not being transferred. July 22, 2011 675 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 5:4 FRF R/W 0x0 Description SSI Frame Format Select Value Frame Format 3:0 DSS R/W 0x0 0x0 Freescale SPI Frame Format 0x1 Texas Instruments Synchronous Serial Frame Format 0x2 MICROWIRE Frame Format 0x3 Reserved SSI Data Size Select Value Data Size 0x0-0x2 Reserved 0x3 4-bit data 0x4 5-bit data 0x5 6-bit data 0x6 7-bit data 0x7 8-bit data 0x8 9-bit data 0x9 10-bit data 0xA 11-bit data 0xB 12-bit data 0xC 13-bit data 0xD 14-bit data 0xE 15-bit data 0xF 16-bit data 676 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: SSI Control 1 (SSICR1), offset 0x004 The SSICR1 register contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 EOT SOD MS SSE LBM RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.0 4 EOT R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. End of Transmission Value Description 3 SOD R/W 0 0 The TXRIS interrupt indicates that the transmit FIFO is half full or less. 1 The End of Transmit interrupt mode for the TXRIS interrupt is enabled. SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. Value Description 2 MS R/W 0 0 SSI can drive the SSITx output in Slave mode. 1 SSI must not drive the SSITx output in Slave mode. SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when the SSI is disabled (SSE=0). Value Description 0 The SSI is configured as a master. 1 The SSI is configured as a slave. July 22, 2011 677 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 1 SSE R/W 0 Description SSI Synchronous Serial Port Enable Value Description 0 SSI operation is disabled. 1 SSI operation is enabled. Note: 0 LBM R/W 0 This bit must be cleared before any control registers are reprogrammed. SSI Loopback Mode Value Description 0 Normal serial port operation enabled. 1 Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. 678 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 3: SSI Data (SSIDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. The SSIDR register is 16-bits wide. When the SSIDR register is read, the entry in the receive FIFO that is pointed to by the current FIFO read pointer is accessed. When a data value is removed by the SSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO pointed to by the current FIFO write pointer. When the SSIDR register is written to, the entry in the transmit FIFO that is pointed to by the write pointer is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. Each data value is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is cleared, allowing the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 DATA R/W 0x0000 SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. July 22, 2011 679 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 4: SSI Status (SSISR), offset 0x00C The SSISR register contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x00C Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BSY RFF RNE TNF TFE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.00 4 BSY RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Busy Bit Value Description 3 RFF RO 0 0 The SSI is idle. 1 The SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. SSI Receive FIFO Full Value Description 2 RNE RO 0 0 The receive FIFO is not full. 1 The receive FIFO is full. SSI Receive FIFO Not Empty Value Description 1 TNF RO 1 0 The receive FIFO is empty. 1 The receive FIFO is not empty. SSI Transmit FIFO Not Full Value Description 0 The transmit FIFO is full. 1 The transmit FIFO is not full. 680 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 TFE RO 1 Description SSI Transmit FIFO Empty Value Description 0 The transmit FIFO is not empty. 1 The transmit FIFO is empty. July 22, 2011 681 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 The SSICPSR register specifies the division factor which is used to derive the SSIClk from the system clock. The clock is further divided by a value from 1 to 256, which is 1 + SCR. SCR is programmed in the SSICR0 register. The frequency of the SSIClk is defined by: SSIClk = SysClk / (CPSDVSR * (1 + SCR)) The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset CPSDVSR RO 0 R/W 0 Bit/Field Name Type Reset Description 31:8 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 CPSDVSR R/W 0x00 SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. 682 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared on reset. On a read, this register gives the current value of the mask on the corresponding interrupt. Setting a bit sets the mask, preventing the interrupt from being signaled to the interrupt controller. Clearing a bit clears the corresponding mask, enabling the interrupt to be sent to the interrupt controller. SSI Interrupt Mask (SSIIM) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 TXIM RXIM RTIM RORIM R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXIM R/W 0 SSI Transmit FIFO Interrupt Mask Value Description 2 RXIM R/W 0 0 The transmit FIFO interrupt is masked. 1 The transmit FIFO interrupt is not masked. SSI Receive FIFO Interrupt Mask Value Description 1 RTIM R/W 0 0 The receive FIFO interrupt is masked. 1 The receive FIFO interrupt is not masked. SSI Receive Time-Out Interrupt Mask Value Description 0 RORIM R/W 0 0 The receive FIFO time-out interrupt is masked. 1 The receive FIFO time-out interrupt is not masked. SSI Receive Overrun Interrupt Mask Value Description 0 The receive FIFO overrun interrupt is masked. 1 The receive FIFO overrun interrupt is not masked. July 22, 2011 683 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x018 Type RO, reset 0x0000.0008 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXRIS RXRIS RTRIS RORRIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXRIS RO 1 SSI Transmit FIFO Raw Interrupt Status Value Description 0 No interrupt. 1 If the EOT bit in the SSICR1 register is clear, the transmit FIFO is half full or less. If the EOT bit is set, the transmit FIFO is empty, and the last bit has been transmitted out of the serializer. This bit is cleared when the transmit FIFO is more than half full (if the EOT bit is clear) or when it has any data in it (if the EOT bit is set). 2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status Value Description 0 No interrupt. 1 The receive FIFO is half full or more. This bit is cleared when the receive FIFO is less than half full. 1 RTRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Value Description 0 No interrupt. 1 The receive time-out has occurred. This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. 684 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 RORRIS RO 0 Description SSI Receive Overrun Raw Interrupt Status Value Description 0 No interrupt. 1 The receive FIFO has overflowed This bit is cleared when a 1 is written to the RORIC bit in the SSI Interrupt Clear (SSIICR) register. July 22, 2011 685 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 TXMIS RXMIS RTMIS RORMIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 TXMIS RO 0 SSI Transmit FIFO Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the transmit FIFO being half full or less (if the EOT bit is clear) or due to the transmission of the last data bit (if the EOT bit is set). This bit is cleared when the transmit FIFO is more than half full (if the EOT bit is clear) or when it has any data in it (if the EOT bit is set). 2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the receive FIFO being half full or less. This bit is cleared when the receive FIFO is less than half full. 1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the receive time out. This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt Clear (SSIICR) register. 686 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 RORMIS RO 0 Description SSI Receive Overrun Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked. 1 An unmasked interrupt was signaled due to the receive FIFO overflowing. This bit is cleared when a 1 is written to the RORIC bit in the SSI Interrupt Clear (SSIICR) register. July 22, 2011 687 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x020 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RTIC RORIC RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 W1C 0 W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 RTIC W1C 0 SSI Receive Time-Out Interrupt Clear Writing a 1 to this bit clears the RTRIS bit in the SSIRIS register and the RTMIS bit in the SSIMIS register. 0 RORIC W1C 0 SSI Receive Overrun Interrupt Clear Writing a 1 to this bit clears the RORRIS bit in the SSIRIS register and the RORMIS bit in the SSIMIS register. 688 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 The SSIDMACTL register is the µDMA control register. SSI DMA Control (SSIDMACTL) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 TXDMAE R/W 0 TXDMAE RXDMAE R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Transmit DMA Enable Value Description 0 RXDMAE R/W 0 0 µDMA for the transmit FIFO is disabled. 1 µDMA for the transmit FIFO is enabled. Receive DMA Enable Value Description 0 µDMA for the receive FIFO is disabled. 1 µDMA for the receive FIFO is enabled. July 22, 2011 689 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID4 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID4 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 690 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID5 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID5 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 22, 2011 691 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID6 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID6 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 692 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID7 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID7 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 22, 2011 693 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFE0 Type RO, reset 0x0000.0022 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 reserved Type Reset reserved Type Reset PID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID0 RO 0x22 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [7:0] Can be used by software to identify the presence of this peripheral. 694 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID1 RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. July 22, 2011 695 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset PID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID2 RO 0x18 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 696 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset PID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 PID3 RO 0x01 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. July 22, 2011 697 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID0 RO 0x0D Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 698 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset CID1 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID1 RO 0xF0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. July 22, 2011 699 Texas Instruments-Production Data Synchronous Serial Interface (SSI) Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 reserved Type Reset reserved Type Reset CID2 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID2 RO 0x05 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 700 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 reserved Type Reset reserved Type Reset CID3 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 CID3 RO 0xB1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. July 22, 2011 701 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface 14 Inter-Integrated Circuit (I2C) Interface The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S9L71 microcontroller includes two I2C modules, providing the ability to interact (both transmit and receive) with other I2C devices on the bus. ® The Stellaris LM3S9L71 controller includes two I2C modules with the following features: ■ Devices on the I2C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation ■ Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive ■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) ■ Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected ■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 702 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 14.1 Block Diagram Figure 14-1. I2C Block Diagram I2CSCL I2C Control Interrupt I2CMSA I2CSOAR I2CMCS I2CSCSR I2CMDR I2CSDR I2CMTPR I2CSIMR I2CMIMR I2CSRIS I2CMRIS I2CSMIS I2CMMIS I2CSICR I2C Master Core I2CSDA I2CSCL 2 I C I/O Select I2CSDA I2CSCL I2C Slave Core I2CMICR I2CSDA I2CMCR 14.2 Signal Description The following table lists the external signals of the I2C interface and describes the function of each. The I2C interface signals are alternate functions for some GPIO signals and default to be GPIO signals at reset., with the exception of the I2C0SCL and I2CSDA pins which default to the I2C function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the I2C function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the I2C signal to the specified GPIO port pin. Note that the I2C pins should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. Table 14-1. Signals for I2C (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description I2C0SCL 72 PB2 (1) I/O OD I2C module 0 clock. I2C0SDA 65 PB3 (1) I/O OD I2C module 0 data. I2C1SCL 14 19 26 34 PJ0 (11) PG0 (3) PA0 (8) PA6 (1) I/O OD I2C module 1 clock. I2C1SDA 18 27 35 87 PG1 (3) PA1 (8) PA7 (1) PJ1 (11) I/O OD I2C module 1 data. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 14-2. Signals for I2C (108BGA) Pin Name I2C0SCL Pin Number Pin Mux / Pin Assignment A11 PB2 (1) a Pin Type Buffer Type I/O OD Description I2C module 0 clock. July 22, 2011 703 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Table 14-2. Signals for I2C (108BGA) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description I2C0SDA E11 PB3 (1) I/O OD I2C module 0 data. I2C1SCL F3 K1 L3 L6 PJ0 (11) PG0 (3) PA0 (8) PA6 (1) I/O OD I2C module 1 clock. I2C1SDA K2 M3 M6 B6 PG1 (3) PA1 (8) PA7 (1) PJ1 (11) I/O OD I2C module 1 data. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 14.3 Functional Description Each I2C module is comprised of both master and slave functions. For proper operation, the SDA and SCL pins must be configured as open-drain signals. A typical I2C bus configuration is shown in Figure 14-2. See “Inter-Integrated Circuit (I2C) Interface” on page 1202 for I2C timing diagrams. Figure 14-2. I2C Bus Configuration RPUP SCL SDA I2C Bus I2CSCL I2CSDA Stellaris® 14.3.1 RPUP SCL SDA 3rd Party Device with I2C Interface SCL SDA 3rd Party Device with I2C Interface I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines are High. Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in “START and STOP Conditions” on page 704) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. 14.3.1.1 START and STOP Conditions The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition, and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition. See Figure 14-3. 704 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 14-3. START and STOP Conditions SDA SDA SCL SCL START condition STOP condition The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and the Control register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the I2C Master Data (I2CMDR) register. When the I2C module operates in Master receiver mode, the ACK bit is normally set causing the I2C bus controller to transmit an acknowledge automatically after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter. When operating in slave mode, two bits in the I2C Slave Raw Interrupt Status (I2CSRIS) register indicate detection of start and stop conditions on the bus; while two bits in the I2C Slave Masked Interrupt Status (I2CSMIS) register allow start and stop conditions to be promoted to controller interrupts (when interrupts are enabled). 14.3.1.2 Data Format with 7-Bit Address Data transfers follow the format shown in Figure 14-4. After the START condition, a slave address is transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). If the R/S bit is clear, it indicates a transmit operation (send), and if it is set, it indicates a request for data (receive). A data transfer is always terminated by a STOP condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/transmit formats are then possible within a single transfer. Figure 14-4. Complete Data Transfer with a 7-Bit Address SDA MSB SCL 1 Start 2 LSB R/S ACK 7 8 9 MSB 1 2 Slave address 7 Data LSB ACK 8 9 Stop The first seven bits of the first byte make up the slave address (see Figure 14-5). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master transmits (sends) data to the selected slave, and a one in this position means that the master receives data from the slave. July 22, 2011 705 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 14-5. R/S Bit in First Byte MSB LSB R/S Slave address 14.3.1.3 Data Validity The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is Low (see Figure 14-6). Figure 14-6. Data Validity During Bit Transfer on the I2C Bus SDA SCL Data line Change stable of data allowed 14.3.1.4 Acknowledge All bus transactions have a required acknowledge clock cycle that is generated by the master. During the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line. To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data transmitted out by the receiver during the acknowledge cycle must comply with the data validity requirements described in “Data Validity” on page 706. When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave so that the master can generate a STOP condition and abort the current transfer. If the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Because the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to allow the master to generate the STOP or a repeated START condition. 14.3.1.5 Arbitration A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate a START condition within minimum hold time of the START condition. In these situations, an arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of the competing master devices to place a '1' (High) on SDA while another master transmits a '0' (Low) switches off its data output stage and retires until the bus is idle again. Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 14.3.2 Available Speed Modes The I2C bus can run in either Standard mode (100 kbps) or Fast mode (400 kbps). The selected mode should match the speed of the other I2C devices on the bus. 706 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 14.3.2.1 Standard and Fast Modes Standard and Fast modes are selected using a value in the I2C Master Timer Period (I2CMTPR) register that results in an SCL frequency of 100 kbps for Standard mode or 400 kbps for Fast mode. The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP where: CLK_PRD is the system clock period SCL_LP is the low phase of SCL (fixed at 6) SCL_HP is the high phase of SCL (fixed at 4) TIMER_PRD is the programmed value in the I2CMTPR register (see page 725). The I2C clock period is calculated as follows: SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD For example: CLK_PRD = 50 ns TIMER_PRD = 2 SCL_LP=6 SCL_HP=4 yields a SCL frequency of: 1/SCL_PERIOD = 333 Khz Table 14-3 gives examples of the timer periods that should be used to generate both Standard and Fast mode SCL frequencies based on various system clock frequencies. Table 14-3. Examples of I2C Master Timer Period versus Speed Mode 14.3.3 System Clock Timer Period Standard Mode Timer Period Fast Mode 4 MHz 0x01 100 Kbps - - 6 MHz 0x02 100 Kbps - - 12.5 MHz 0x06 89 Kbps 0x01 312 Kbps 16.7 MHz 0x08 93 Kbps 0x02 278 Kbps 20 MHz 0x09 100 Kbps 0x02 333 Kbps 25 MHz 0x0C 96.2 Kbps 0x03 312 Kbps 33 MHz 0x10 97.1 Kbps 0x04 330 Kbps 40 MHz 0x13 100 Kbps 0x04 400 Kbps 50 MHz 0x18 100 Kbps 0x06 357 Kbps 80 MHz 0x27 100 Kbps 0x09 400 Kbps Interrupts The I2C can generate interrupts when the following conditions are observed: ■ Master transaction completed ■ Master arbitration lost July 22, 2011 707 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface ■ Master transaction error ■ Slave transaction received ■ Slave transaction requested ■ Stop condition on bus detected ■ Start condition on bus detected The I2C master and I2C slave modules have separate interrupt signals. While both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller. 14.3.3.1 I2C Master Interrupts The I2C master module generates an interrupt when a transaction completes (either transmit or receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C master interrupt, software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I2C Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration, the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in the I2C Master Interrupt Clear (I2CMICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Master Raw Interrupt Status (I2CMRIS) register. 14.3.3.2 I2C Slave Interrupts The slave module can generate an interrupt when data has been received or requested. This interrupt is enabled by setting the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register. Software determines whether the module should write (transmit) or read (receive) data from the I2C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by setting the DATAIC bit in the I2C Slave Interrupt Clear (I2CSICR) register. In addition, the slave module can generate an interrupt when a start and stop condition is detected. These interrupts are enabled by setting the STARTIM and STOPIM bits of the I2C Slave Interrupt Mask (I2CSIMR) register and cleared by writing a 1 to the STOPIC and STARTIC bits of the I2C Slave Interrupt Clear (I2CSICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Slave Raw Interrupt Status (I2CSRIS) register. 14.3.4 Loopback Operation The I2C modules can be placed into an internal loopback mode for diagnostic or debug work by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL signals from the master and slave modules are tied together. 708 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 14.3.5 Command Sequence Flow Charts This section details the steps required to perform the various I2C transfer types in both master and slave mode. 14.3.5.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master. July 22, 2011 709 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 14-7. Master Single TRANSMIT Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Write data to I2CMDR Read I2CMCS NO BUSBSY bit=0? YES Write ---0-111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle 710 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 14-8. Master Single RECEIVE Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS NO BUSBSY bit=0? YES Write ---00111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Read data from I2CMDR Idle July 22, 2011 711 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 14-9. Master TRANSMIT with Repeated START Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS Write data to I2CMDR BUSY bit=0? YES Read I2CMCS ERROR bit=0? NO NO NO BUSBSY bit=0? YES Write data to I2CMDR YES Write ---0-011 to I2CMCS NO ARBLST bit=1? YES Write ---0-001 to I2CMCS NO Index=n? YES Write ---0-101 to I2CMCS Write ---0-100 to I2CMCS Error Service Idle Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle 712 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 14-10. Master RECEIVE with Repeated START Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS BUSY bit=0? Read I2CMCS NO YES NO BUSBSY bit=0? ERROR bit=0? NO YES Write ---01011 to I2CMCS NO Read data from I2CMDR ARBLST bit=1? YES Write ---01001 to I2CMCS NO Write ---0-100 to I2CMCS Index=m-1? Error Service YES Write ---00101 to I2CMCS Idle Read I2CMCS BUSY bit=0? NO YES NO ERROR bit=0? YES Error Service Read data from I2CMDR Idle July 22, 2011 713 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 14-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated START Idle Master operates in Master Transmit mode STOP condition is not generated Write Slave Address to I2CMSA Write ---01011 to I2CMCS Master operates in Master Receive mode Repeated START condition is generated with changing data direction Idle 714 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 14-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated START Idle Master operates in Master Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write ---0-011 to I2CMCS Master operates in Master Transmit mode Repeated START condition is generated with changing data direction Idle 14.3.5.2 I2C Slave Command Sequences Figure 14-13 on page 716 presents the command sequence available for the I2C slave. July 22, 2011 715 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Figure 14-13. Slave Command Sequence Idle Write OWN Slave Address to I2CSOAR Write -------1 to I2CSCSR Read I2CSCSR NO TREQ bit=1? YES Write data to I2CSDR 14.4 NO RREQ bit=1? FBR is also valid YES Read data from I2CSDR Initialization and Configuration The following example shows how to configure the I2C module to transmit a single byte as a master. This assumes the system clock is 20 MHz. 1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System Control module (see page 272). 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module (see page 281). To find out which GPIO port to enable, refer to Table 23-5 on page 1145. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register (see page 416). To determine which GPIOs to configure, see Table 23-4 on page 1137. 4. Enable the I2C pins for Open Drain operation. See page 421. 5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate pins. See page 434 and Table 23-5 on page 1145. 6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010. 716 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by the following equation: TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1; TPR = (20MHz/(2*(6+4)*100000))-1; TPR = 9 Write the I2CMTPR register with the value of 0x0000.0009. 8. Specify the slave address of the master and that the next operation is a Transmit by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B. 9. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the desired data. 10. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register with a value of 0x0000.0007 (STOP, START, RUN). 11. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has been cleared. 12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged. 14.5 Register Map Table 14-4 on page 717 lists the I2C registers. All addresses given are relative to the I2C base address: ■ I2C 0: 0x4002.0000 ■ I2C 1: 0x4002.1000 Note that the I2C module clock must be enabled before the registers can be programmed (see page 272). There must be a delay of 3 system clocks after the I2C module clock is enabled before any I2C module registers are accessed. ® The hw_i2c.h file in the StellarisWare Driver Library uses a base address of 0x800 for the I2C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare uses an offset between 0x000 and 0x018 with the slave base address. Table 14-4. Inter-Integrated Circuit (I2C) Interface Register Map Offset Description See page Name Type Reset 0x000 I2CMSA R/W 0x0000.0000 I2C Master Slave Address 719 0x004 I2CMCS R/W 0x0000.0000 I2C Master Control/Status 720 0x008 I2CMDR R/W 0x0000.0000 I2C Master Data 724 0x00C I2CMTPR R/W 0x0000.0001 I2C Master Timer Period 725 0x010 I2CMIMR R/W 0x0000.0000 I2C Master Interrupt Mask 726 0x014 I2CMRIS RO 0x0000.0000 I2C Master Raw Interrupt Status 727 I2C Master July 22, 2011 717 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Table 14-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued) Offset Name 0x018 Description See page Type Reset I2CMMIS RO 0x0000.0000 I2C Master Masked Interrupt Status 728 0x01C I2CMICR WO 0x0000.0000 I2C Master Interrupt Clear 729 0x020 I2CMCR R/W 0x0000.0000 I2C Master Configuration 730 0x800 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 731 0x804 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 732 0x808 I2CSDR R/W 0x0000.0000 I2C Slave Data 734 0x80C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 735 0x810 I2CSRIS RO 0x0000.0000 I2C Slave Raw Interrupt Status 736 0x814 I2CSMIS RO 0x0000.0000 I2C Slave Masked Interrupt Status 737 0x818 I2CSICR WO 0x0000.0000 I2C Slave Interrupt Clear 738 I2C Slave 14.6 Register Descriptions (I2C Master) The remainder of this section lists and describes the I2C master registers, in numerical order by address offset. 718 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Transmit (Low). I2C Master Slave Address (I2CMSA) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset SA RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:1 SA R/W 0x00 R/S Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Address This field specifies bits A6 through A0 of the slave address. 0 R/S R/W 0 Receive/Send The R/S bit specifies if the next operation is a Receive (High) or Transmit (Low). Value Description 0 Transmit 1 Receive July 22, 2011 719 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit is normally set, causing the I2C bus controller to transmit an acknowledge automatically after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter. Read-Only Status Register I2C Master Control/Status (I2CMCS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 BUSBSY IDLE ARBLST ERROR BUSY RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6 BUSBSY RO 0 DATACK ADRACK RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bus Busy Value Description 0 The I2C bus is idle. 1 The I2C bus is busy. The bit changes based on the START and STOP conditions. 5 IDLE RO 0 I2C Idle Value Description 0 The I2C controller is not idle. 1 The I2C controller is idle. 720 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 4 ARBLST RO 0 Description Arbitration Lost Value Description 3 DATACK RO 0 0 The I2C controller won arbitration. 1 The I2C controller lost arbitration. Acknowledge Data Value Description 2 ADRACK RO 0 0 The transmitted data was acknowledged 1 The transmitted data was not acknowledged. Acknowledge Address Value Description 1 ERROR RO 0 0 The transmitted address was acknowledged 1 The transmitted address was not acknowledged. Error Value Description 0 No error was detected on the last operation. 1 An error occurred on the last operation. The error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0 BUSY RO 0 I2C Busy Value Description 0 The controller is idle. 1 The controller is busy. When the BUSY bit is set, the other status bits are not valid. Write-Only Control Register I2C Master Control/Status (I2CMCS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 ACK STOP START RUN RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset July 22, 2011 721 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset Description 31:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 ACK WO 0 Data Acknowledge Enable Value Description 2 STOP WO 0 0 The received data byte is not acknowledged automatically by the master. 1 The received data byte is acknowledged automatically by the master. See field decoding in Table 14-5 on page 722. Generate STOP Value Description 1 START WO 0 0 The controller does not generate the STOP condition. 1 The controller generates the STOP condition. See field decoding in Table 14-5 on page 722. Generate START Value Description 0 RUN WO 0 The controller does not generate the START condition. 1 The controller generates the START or repeated START condition. See field decoding in Table 14-5 on page 722. I2C Master Enable 0 Value Description 0 The master is disabled. 1 The master is enabled to transmit or receive data. See field decoding in Table 14-5 on page 722. Table 14-5. Write Field Decoding for I2CMCS[3:0] Field Current I2CMSA[0] State R/S Idle I2CMCS[3:0] ACK STOP START RUN Description 0 X a 0 1 1 START condition followed by TRANSMIT (master goes to the Master Transmit state). 0 X 1 1 1 START condition followed by a TRANSMIT and STOP condition (master remains in Idle state). 1 0 0 1 1 START condition followed by RECEIVE operation with negative ACK (master goes to the Master Receive state). 1 0 1 1 1 START condition followed by RECEIVE and STOP condition (master remains in Idle state). 1 1 0 1 1 START condition followed by RECEIVE (master goes to the Master Receive state). 1 1 1 1 1 Illegal All other combinations not listed are non-operations. NOP 722 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 14-5. Write Field Decoding for I2CMCS[3:0] Field (continued) Current I2CMSA[0] State R/S Master Transmit I2CMCS[3:0] Description ACK STOP START RUN X X 0 0 1 TRANSMIT operation (master remains in Master Transmit state). X X 1 0 0 STOP condition (master goes to Idle state). X X 1 0 1 TRANSMIT followed by STOP condition (master goes to Idle state). 0 X 0 1 1 Repeated START condition followed by a TRANSMIT (master remains in Master Transmit state). 0 X 1 1 1 Repeated START condition followed by TRANSMIT and STOP condition (master goes to Idle state). 1 0 0 1 1 Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive state). 1 0 1 1 1 Repeated START condition followed by a TRANSMIT and STOP condition (master goes to Idle state). 1 1 0 1 1 Repeated START condition followed by RECEIVE (master goes to Master Receive state). 1 1 1 1 1 Illegal. All other combinations not listed are non-operations. NOP. X 0 0 0 1 RECEIVE operation with negative ACK (master remains in Master Receive state). X X 1 0 0 STOP condition (master goes to Idle state). X 0 1 0 1 RECEIVE followed by STOP condition (master goes to Idle state). X 1 0 0 1 RECEIVE operation (master remains in Master Receive state). X 1 1 0 1 Illegal. 1 0 0 1 1 Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receive state). 1 0 1 1 1 Repeated START condition followed by RECEIVE and STOP condition (master goes to Idle state). 1 1 0 1 1 Repeated START condition followed by RECEIVE (master remains in Master Receive state). 0 X 0 1 1 Repeated START condition followed by TRANSMIT (master goes to Master Transmit state). 0 X 1 1 1 Repeated START condition followed by TRANSMIT and STOP condition (master goes to Idle state). Master Receive All other combinations not listed are non-operations. b NOP. a. An X in a table cell indicates the bit can be 0 or 1. b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave. July 22, 2011 723 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 3: I2C Master Data (I2CMDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state. I2C Master Data (I2CMDR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DATA R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data Transferred Data transferred during transaction. 724 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register specifies the period of the SCL clock. Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur. I2C Master Timer Period (I2CMTPR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x00C Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset reserved Type Reset TPR RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6:0 TPR R/W 0x1 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SCL Clock Period This field specifies the period of the SCL clock. SCL_PRD = 2×(1 + TPR)×(SCL_LP + SCL_HP)×CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the system clock period in ns. July 22, 2011 725 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Master Interrupt Mask (I2CMIMR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 IM Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 IM R/W 0 Interrupt Mask Value Description 1 The master interrupt is sent to the interrupt controller when the RIS bit in the I2CMRIS register is set. 0 The RIS interrupt is suppressed and not sent to the interrupt controller. 726 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending. I2C Master Raw Interrupt Status (I2CMRIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RIS RO 0 Raw Interrupt Status Value Description 1 A master interrupt is pending. 0 No interrupt. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register. July 22, 2011 727 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled. I2C Master Masked Interrupt Status (I2CMMIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 MIS RO 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 MIS RO 0 Masked Interrupt Status Value Description 1 An unmasked master interrupt was signaled and is pending. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register. 728 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw and masked interrupts. I2C Master Interrupt Clear (I2CMICR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x01C Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 reserved Type Reset reserved Type Reset RO 0 IC Bit/Field Name Type Reset Description 31:1 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 IC WO 0 Interrupt Clear Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the MIS bit in the I2CMMIS register. A read of this register returns no meaningful data. July 22, 2011 729 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave) and sets the interface for test mode loopback. I2C Master Configuration (I2CMCR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SFE MFE RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 SFE R/W 0 reserved RO 0 RO 0 LPBK RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Function Enable Value Description 4 MFE R/W 0 1 Slave mode is enabled. 0 Slave mode is disabled. I2C Master Function Enable Value Description 3:1 reserved RO 0x0 0 LPBK R/W 0 1 Master mode is enabled. 0 Master mode is disabled. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Loopback Value Description 14.7 1 The controller in a test mode loopback configuration. 0 Normal operation. Register Descriptions (I2C Slave) The remainder of this section lists and describes the I2C slave registers, in numerical order by address offset. 730 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus. I2C Slave Own Address (I2CSOAR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x800 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset OAR RO 0 Bit/Field Name Type Reset 31:7 reserved RO 0x0000.00 6:0 OAR R/W 0x00 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. July 22, 2011 731 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 This register functions as a control register when written, and a status register when read. Read-Only Status Register I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x804 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2 FBR RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 FBR TREQ RREQ RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. First Byte Received Value Description 1 The first byte following the slave’s own address has been received. 0 The first byte has not been received. This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the I2CSDR register. Note: 1 TREQ RO 0 This bit is not used for slave transmit operations. Transmit Request Value Description 0 RREQ RO 0 1 The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the I2CSDR register. 0 No outstanding transmit request. Receive Request Value Description 1 The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until the data has been read from the I2CSDR register. 0 No outstanding receive data. 732 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Write-Only Control Register I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x804 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 DA WO 0 RO 0 DA Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Active Value Description 0 Disables the I2C slave operation. 1 Enables the I2C slave operation. July 22, 2011 733 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 12: I2C Slave Data (I2CSDR), offset 0x808 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. I2C Slave Data (I2CSDR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x808 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset DATA RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DATA R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. 734 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Slave Interrupt Mask (I2CSIMR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x80C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STOPIM STARTIM DATAIM R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 STOPIM R/W 0 Stop Condition Interrupt Mask Value Description 1 STARTIM R/W 0 1 The STOP condition interrupt is sent to the interrupt controller when the STOPRIS bit in the I2CSRIS register is set. 0 The STOPRIS interrupt is suppressed and not sent to the interrupt controller. Start Condition Interrupt Mask Value Description 0 DATAIM R/W 0 1 The START condition interrupt is sent to the interrupt controller when the STARTRIS bit in the I2CSRIS register is set. 0 The STARTRIS interrupt is suppressed and not sent to the interrupt controller. Data Interrupt Mask Value Description 1 The data received or data requested interrupt is sent to the interrupt controller when the DATARIS bit in the I2CSRIS register is set. 0 The DATARIS interrupt is suppressed and not sent to the interrupt controller. July 22, 2011 735 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 This register specifies whether an interrupt is pending. I2C Slave Raw Interrupt Status (I2CSRIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x810 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STOPRIS STARTRIS DATARIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 STOPRIS RO 0 Stop Condition Raw Interrupt Status Value Description 1 A STOP condition interrupt is pending. 0 No interrupt. This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register. 1 STARTRIS RO 0 Start Condition Raw Interrupt Status Value Description 1 A START condition interrupt is pending. 0 No interrupt. This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register. 0 DATARIS RO 0 Data Raw Interrupt Status Value Description 1 A data received or data requested interrupt is pending. 0 No interrupt. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. 736 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 This register specifies whether an interrupt was signaled. I2C Slave Masked Interrupt Status (I2CSMIS) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x814 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STOPMIS STARTMIS DATAMIS RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 STOPMIS RO 0 Stop Condition Masked Interrupt Status Value Description 1 An unmasked STOP condition interrupt was signaled is pending. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register. 1 STARTMIS RO 0 Start Condition Masked Interrupt Status Value Description 1 An unmasked START condition interrupt was signaled is pending. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register. 0 DATAMIS RO 0 Data Masked Interrupt Status Value Description 1 An unmasked data received or data requested interrupt was signaled is pending. 0 An interrupt has not occurred or is masked. This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register. July 22, 2011 737 Texas Instruments-Production Data Inter-Integrated Circuit (I2C) Interface Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 This register clears the raw interrupt. A read of this register returns no meaningful data. I2C Slave Interrupt Clear (I2CSICR) I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 Offset 0x818 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 STOPIC STARTIC WO 0 WO 0 DATAIC WO 0 Bit/Field Name Type Reset Description 31:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 STOPIC WO 0 Stop Condition Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. 1 STARTIC WO 0 Start Condition Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. 0 DATAIC WO 0 Data Interrupt Clear Writing a 1 to this bit clears the STOPRIS bit in the I2CSRIS register and the STOPMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. 738 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 15 Inter-Integrated Circuit Sound (I2S) Interface The I2S module is a configurable serial audio core that contains a transmit module and a receive module. The module is configurable for the I2S as well as Left-Justified and Right-Justified serial audio formats. Data can be in one of four modes: Stereo, Mono, Compact 16-bit Stereo and Compact 8-Bit Stereo. The transmit and receive modules each have an 8-entry audio-sample FIFO. An audio sample can consist of a Left and Right Stereo sample, a Mono sample, or a Left and Right Compact Stereo sample. In Compact 16-Bit Stereo, each FIFO entry contains both the 16-bit left and 16-bit right samples, allowing efficient data transfers and requiring less memory space. In Compact 8-bit Stereo, each FIFO entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements further. Both the transmitter and receiver are capable of being a master or a slave. ® The Stellaris I2S module has the following features: ■ Configurable audio format supporting I2S, Left-justification, and Right-justification ■ Configurable sample size from 8 to 32 bits ■ Mono and Stereo support ■ 8-, 16-, and 32-bit FIFO interface for packing memory ■ Independent transmit and receive 8-entry FIFOs ■ Configurable FIFO-level interrupt and µDMA requests ■ Independent transmit and receive MCLK direction control ■ Transmit and receive internal MCLK sources ■ Independent transmit and receive control for serial clock and word select ■ MCLK and SCLK can be independently set to master or slave ■ Configurable transmit zero or last sample when FIFO empty ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Burst requests – Channel requests asserted when FIFO contains required amount of data July 22, 2011 739 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface 15.1 Block Diagram Figure 15-1. I2S Block Diagram I2S0TXMCLK I2STXCFG Transmit FIFO 8 entry SysClk I2STXFIFO I2S0TXSCK BitClk/WdSel Generation I2S0TXWS I2STXFIFOCFG System AHB Bus I2STXLIMIT Serial Encoder I2STXSD I2STXLEV Registers I2SCFG Interrupts/ DMA I2STXISM Transmit FIFO I2SIC I2SRIS I2SMIS I2SRXCFG I2SIM I2S0RXMCLK Receive FIFO 8 entry I2SRXFIFO I2S0RXSCK BitClk/WdSel Generation I2S0RXWS I2SRXFIFOCFG I2SRXLIMIT Serial Decoder I2SRXSD I2SRXLEV Receive FIFO I2SRXISM 15.2 Signal Description The following table lists the external signals of the I2S module and describes the function of each. The I2S module signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the I2S signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the I2S function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the I2S signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. 740 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 15-1. Signals for I2S (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description I2S0RXMCLK 16 29 98 PG3 (9) PA3 (9) PD5 (8) I/O TTL I2S module 0 receive master clock. I2S0RXSCK 10 40 PD0 (8) PG5 (9) I/O TTL I2S module 0 receive clock. I2S0RXSD 17 28 97 PG2 (9) PA2 (9) PD4 (8) I/O TTL I2S module 0 receive data. I2S0RXWS 11 37 PD1 (8) PG6 (9) I/O TTL I2S module 0 receive word select. I2S0TXMCLK 43 61 PF6 (9) PF1 (8) I/O TTL I2S module 0 transmit master clock. I2S0TXSCK 30 90 99 PA4 (9) PB6 (9) PD6 (8) I/O TTL I2S module 0 transmit clock. I2S0TXSD 5 47 PE5 (9) PF0 (8) I/O TTL I2S module 0 transmit data. I2S0TXWS 6 31 100 PE4 (9) PA5 (9) PD7 (8) I/O TTL I2S module 0 transmit word select. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 15-2. Signals for I2S (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description I2S0RXMCLK J2 L4 C6 PG3 (9) PA3 (9) PD5 (8) I/O TTL I2S module 0 receive master clock. I2S0RXSCK G1 M7 PD0 (8) PG5 (9) I/O TTL I2S module 0 receive clock. I2S0RXSD J1 M4 B5 PG2 (9) PA2 (9) PD4 (8) I/O TTL I2S module 0 receive data. I2S0RXWS G2 L7 PD1 (8) PG6 (9) I/O TTL I2S module 0 receive word select. I2S0TXMCLK M8 H12 PF6 (9) PF1 (8) I/O TTL I2S module 0 transmit master clock. I2S0TXSCK L5 A7 A3 PA4 (9) PB6 (9) PD6 (8) I/O TTL I2S module 0 transmit clock. I2S0TXSD B3 M9 PE5 (9) PF0 (8) I/O TTL I2S module 0 transmit data. I2S0TXWS B2 M5 A2 PE4 (9) PA5 (9) PD7 (8) I/O TTL I2S module 0 transmit word select. a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 22, 2011 741 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface 15.3 Functional Description The Inter-Integrated Circuit Sound (I2S) module contains separate transmit and receive engines. Each engine consists of the following: ■ Serial encoder for the transmitter; serial decoder for the receiver ■ 8-entry FIFO to store sample data ■ Independent configuration of all programmable settings The basic programming model of the I2S block is as follows: ■ Configuration – Overall I2S module configuration in the I2S Module Configuration (I2SCFG) register. This register is used to select the MCLK source and enable the receiver and transmitter. – Transmit and receive configuration in the I2S Transmit Module Configuration (I2STXCFG) and I2S Receive Module Configuration (I2SRXCFG) registers. These registers set the basic parameters for the receiver and transmitter such as data configuration (justification, delay, read mode, sample size, and system data size); SCLK (polarity and source); and word select polarity. – Transmit and receive FIFO configuration in the I2S Transmit FIFO Configuration (I2STXFIFOCFG) and I2S Receive FIFO Configuration (I2SRXFIFOCFG) registers. These registers select the Compact Stereo mode size (16-bit or 8-bit), provide indication of whether the next sample is Left or Right, and select mono mode for the receiver. ■ FIFO – Transmit and receive FIFO data in the I2S Transmit FIFO Data (I2STXFIFO) and I2S Receive FIFO Data (I2SRXFIFO) registers – Information on FIFO data levels in the I2S Transmit FIFO Level (I2STXLEV) and I2S Receive FIFO Level (I2SRXLEV) registers – Configuration for FIFO service requests based on FIFO levels in the I2S Transmit FIFO Limit (I2STXLIMIT) and I2S Receive FIFO Limit (I2SRXLIM) registers ■ Interrupt Control – Interrupt masking configuration in the I2S Interrupt Mask (I2SIM) register – Raw and masked interrupt status in the I2S Raw Interrupt Status (I2SRIS) and I2S Masked Interrupt Status (I2SMIS) registers – Interrupt clearing through the I2S Interrupt Clear (I2SIC) register – Configuration for FIFO service requests interrupts and transmit/receive error interrupts in the I2S Transmit Interrupt Status and Mask (I2STXISM) and I2S Receive Interrupt Status and Mask (I2SRXISM) registers 742 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 15-2 on page 743 provides an example of an I2S data transfer. Figure 15-3 on page 743 provides an example of an Left-Justified data transfer. Figure 15-4 on page 743 provides an example of an Right-Justified data transfer. Figure 15-2. I2S Data Transfer SCK Word Select Serial Data MSB LSB WORD n-1 RIGHT CHANNEL MSB WORD n+1 RIGHT CHANNEL WORD n LEFT CHANNEL Figure 15-3. Left-Justified Data Transfer System Data Size Right Channel Word Select Left Channel SCLK Serial Data MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +5 +4 +1 LSB Sample Size Figure 15-4. Right-Justified Data Transfer System Data Size Word Select Right Channel Left Channel SCLK Serial 0 Data MSB -1 -2 -3 -4 -5 +7 +6 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 -5 +7 +6 +3 +2 +1 LSB Sample Size 15.3.1 Transmit The transmitter consists of a serial encoder, an 8-entry FIFO, and control logic. The transmitter has independent MCLK (I2S0TXMCLK), SCLK (I2S0TXSCK), and Word-Select (I2S0TXWS) signals. 15.3.1.1 Serial Encoder The serial encoder reads audio samples from the receive FIFO and converts them into an audio stream. By configuring the serial encoder, common audio formats I2S, Left-Justified, and Right-Justified are supported. The MSB is transmitted first. The sample size and system data size July 22, 2011 743 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface are configurable with the SSZ and SDSZ bits in the I2S Transmit Module Configuration (I2STXCFG) register. The sample size is the number of bits of data being transmitted, and the system data size is the number of I2S0TXSCK transitions between the word select transitions. The system data size must be large enough to accommodate the maximum sample size. In Mono mode, the sample data is repeated in both the left and right channels. When the FIFO is empty, the user may select either transmission of zeros or of the last sample. The serial encoder is enabled using the TXEN bit in the I2S Module Configuration (I2SCFG) register. 15.3.1.2 FIFO Operation The transmit FIFO stores eight Mono samples or eight Stereo sample-pairs of data and is accessed through the I2S Transmit FIFO Data (I2STXFIFO) register. The FIFO interface for the audio data is different based on the Write mode, defined by the I2S Transmit FIFO Configuration (I2STXFIFOCFG) Compact Stereo Sample Size bit (CSS) and the I2STXCFG Write Mode field (WM). All data samples are MSB-aligned. Table 15-3 on page 744 defines the interface for each Write mode. Stereo samples are written first left then right. The next sample (right or left) to be written is indicated by the LRS bit in the I2STXFIFOCFG register. Table 15-3. I2S Transmit FIFO Interface WM field in I2STXCFG CSS bit in I2STXFIFOCFG 0x0 don't care 0x1 Write Mode Sample Width Samples per FIFO Write Data Alignment Stereo 8-32 bits 1 MSB 0 Compact Stereo - 16 bit 8-16 bits 2 MSB Right [31:16], Left [15:0] 0x1 1 Compact Stereo - 8 bit 8 bits 2 Right [15:8], Left[7:0] 0x2 don't care 8-32 bits 1 MSB Mono The number of samples in the transmit FIFO can be read using the I2S Transmit FIFO Level (I2STXLEV) register. The value ranges from 0 to 16. Stereo and compact stereo sample pairs are counted as two. The mono samples also increment the count by two, therefore, four mono samples will have a count of eight. 15.3.1.3 Clock Control The transmitter MCLK and SCLK can be independently programmed to be the master or slave. The transmitter is programmed to be the master or slave of the SCLK using the MSL bit in the I2STXCFG register. When the transmitter is the master, the I2S0TXSCK frequency is the specified I2S0TXMCLK divided by four. The I2S0TXSCK may be inverted using the SCP bit in the I2STXCFG register. The transmitter can also be the master or slave of the MCLK. When the transmitter is the master, the PLL must be active and a fractional clock divider must be programmed. See page 236 for the setup for the master I2S0TXMCLK source. An external transmit I2S0TXMCLK does not require the use of the PLL and is selected using the TXSLV bit in the I2SCFG register. The following tables show combinations of the TXINT and TXFRAC bits in the I2S MCLK Configuration (I2SMCLKCFG) register that provide MCLK frequencies within acceptable error limits. In the table, Fs is the sampling frequency in kHz and possible crystal frequencies are shown in MHz across the top row of the table. The words "not supported" in the table mean that it is not possible to obtain the specified sampling frequencies with the specified crystal frequency within the error tolerance of 0.3%. The values in the table are based on the following values: MCLK = Fs × 256 PLL = 400 MHz 744 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller The Integer value is taken from the result of the following calculation: ROUND(PLL/MCLK) The remaining fractional component is converted to binary, and the first four bits are the Fractional value. Table 15-4. Crystal Frequency (Values from 3.5795 MHz to 5 MHz) Sampling Frequency Fs (kHz) Crystal Frequency (MHz) 3.5795 3.6864 4 4.096 4.9152 5 Integer Fractional Integer Fractional Integer Fractional Integer Fractional Integer Fractional Integer Fractional 8 195 12 194 6 195 5 196 0 194 6 195 5 11.025 142 1 141 1 141 12 142 4 141 1 141 12 12 130 8 129 10 130 3 130 11 129 10 130 3 16 97 14 97 3 97 10 98 0 97 3 97 10 22.05 71 0 70 8 70 14 71 2 70 8 70 14 24 65 4 64 13 65 2 65 5 64 13 65 2 32 48 15 48 10 48 13 49 0 48 10 48 13 44.1 35 8 35 4 35 7 35 9 35 4 35 7 48 32 10 32 6 32 9 32 11 32 6 32 9 64 24 8 24 5 24 7 24 8 24 5 24 7 88.2 17 12 17 10 17 11 17 12 17 10 17 11 96 16 5 16 3 16 4 16 5 16 3 16 4 128 12 4 12 2 12 3 12 4 12 2 12 3 176.4 8 14 8 13 8 14 8 14 8 13 8 14 8 2 8 3 Not supported 8 2 192 Not supported Not supported Table 15-5. Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) Sampling Frequency Fs (kHz) Crystal Frequency (MHz) 5.12 6 6.144 7.3728 8 8.192 Integer Fractional Integer Fractional Integer Fractional Integer Fractional Integer Fractional Integer Fractional 8 195 0 195 5 195 0 194 11.025 141 8 141 12 141 8 141 12 130 0 130 3 130 0 129 6 195 5 194 11 1 141 12 141 4 10 130 3 129 12 16 97 8 97 10 97 8 97 3 97 10 97 5 22.05 70 12 70 14 70 12 70 8 70 14 70 10 24 65 0 65 2 65 0 64 13 65 2 64 14 32 48 12 48 13 48 12 48 10 48 13 48 11 44.1 35 6 35 7 35 6 35 4 35 7 35 5 48 32 8 32 9 32 8 32 6 32 9 32 7 64 24 6 24 7 24 6 24 5 24 7 24 5 88.2 17 11 17 11 17 11 17 10 17 11 17 11 96 16 4 16 4 16 4 16 3 16 4 16 4 128 12 3 12 3 12 3 12 2 12 3 12 3 Not supported 8 14 Not supported 8 13 8 14 8 13 8 8 2 8 Not supported 8 2 8 2 176.4 192 2 2 July 22, 2011 745 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Table 15-6. Crystal Frequency (Values from 10 MHz to 14.3181 MHz) Crystal Frequency (MHz) Sampling Frequency Fs (kHz) 10 Integer 12 Fractional Integer 12.288 Fractional Integer 13.56 Fractional Integer 14.3181 Fractional Integer Fractional 8 195 5 195 5 196 0 194 3 195 12 11.025 141 12 141 12 142 4 140 15 142 1 12 130 3 130 3 130 11 129 8 130 8 16 97 10 97 10 98 0 97 2 97 14 22.05 70 14 70 14 71 2 70f 7 71 0 24 65 2 65 2 65 5 64 12 65 4 32 48 13 48 13 49 0 48 9 48 15 44.1 35 7 35 7 35 9 35 4 35 8 48 32 9 32 9 32 11 32 6 32 10 64 24 7 24 7 24 8 24 4 24 8 88.2 17 11 17 11 17 12 17 10 17 12 96 16 4 16 4 16 5 16 3 16 5 128 12 3 12 3 12 4 12 2 12 4 176.4 8 14 8 14 8 14 8 13 8 14 192 8 2 8 2 8 3 Not supported Not supported Table 15-7. Crystal Frequency (Values from 16 MHz to 16.384 MHz) Crystal Frequency (MHz) Sampling Frequency Fs (kHz) 16.384 Integer Fractional Integer Fractional 195 5 192 0 11.025 141 12 139 5 12 130 3 128 0 8 15.3.1.4 16 16 97 10 96 0 22.05 70 14 69 11 24 65 2 64 0 32 48 13 48 0 44.1 35 7 34 13 48 32 9 32 0 64 24 7 24 0 88.2 17 11 17 7 96 16 4 16 0 128 12 3 12 0 176.4 8 14 8 11 192 8 2 8 0 Interrupt Control A single interrupt is asserted to the CPU whenever any of the transmit or receive sources is asserted. The transmit module has two interrupt sources: the FIFO service request and write error. The interrupts may be masked using the TXSRIM and TXWEIM bits in the I2S Interrupt Mask (I2SIM) 746 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller register. The status of the interrupt source is indicated by the I2S Raw Interrupt Status (I2SRIS) register. The status of enabled interrupts is indicated by the I2S Masked Interrupt Status (I2SMIS) register. The FIFO level interrupt has a second level of masking using the FFM bit in the I2S Transmit Interrupt Status and Mask (I2STXISM) register. The FIFO service request interrupt is asserted when the FIFO level (indicated by the LEVEL field in the I2S Transmit FIFO Level (I2STXLEV) register) is below the FIFO limit (programmed using the I2S Transmit FIFO Limit (I2STXLIMIT) register) and both the TXSRIM and FFM bits are set. If software attempts to write to a full FIFO, a Transmit FIFO Write error occurs (indicated by the TXWERIS bit in the I2S Raw Interrupt Status (I2SRIS) register). The TXWERIS bit in the I2SRIS register and the TXWEMIS bit in the I2SMIS register are cleared by setting the TXWEIC bit in the I2S Interrupt Clear (I2SIC) register. 15.3.1.5 DMA Support The µDMA can be used to more efficiently stream data to and from the I2S bus. The I2S tranmit and receive modules have separate µDMA channels. The FIFO Interrupt Mask bit (FFM) in the I2STXISM register must be set for the request signaling to propagate to the µDMA module. See “Micro Direct Memory Access (μDMA)” on page 333 for channel configuration. The I2S module uses the µDMA burst request signal, not the single request. Thus each time a µDMA request is made, the µDMA controller transfers the number of items specified as the burst size for the µDMA channel. Therefore, the µDMA channel burst size and the I2S FIFO service request limit must be set to the same value (using the LIMIT field in the I2STXLIMIT register). 15.3.2 Receive The receiver consists of a serial decoder, an 8-entry FIFO, and control logic. The receiver has independent MCLK (I2S0RXMCLK), SCLK (I2S0RXSCK), and Word-Select (I2S0RXWS) signals. 15.3.2.1 Serial Decoder The serial decoder accepts incoming audio stream data and places the sample data in the receive FIFO. By configuring the serial decoder, common audio formats I2S, Left-Justified, and Right-Justified are supported. The MSB is transmitted first. The sample size and system data size are configurable with the SSZ and SDSZ bits in the I2S Receive Module Configuration (I2SRXCFG) register. The sample size is the number of bits of data being received, and the system data size is the number of I2S0RXSCK transitions between the word select transitions. The system data size must be large enough to accommodate the maximum sample size. Any bits received after the LSB are 0s. If the FIFO is full, the incoming sample (in Mono) or sample-pairs (Stereo) are dropped until the FIFO has space. The serial decoder is enabled using the RXEN bit in the I2SCFG register. 15.3.2.2 FIFO Operation The receive FIFO stores eight Mono samples or eight Stereo sample-pairs of data and is accessed through the I2S Receive FIFO Data (I2SRXFIFO) register. Table 15-8 on page 748 defines the interface for each Read mode. All data is stored MSB-aligned. The Stereo data is read left sample then right. In Mono mode, the FIFO interface can be configured to read the right or left channel by setting the FIFO Mono Mode bit (FMM) in the I2S Receive FIFO Configuration (I2SRXFIFOCFG) register. This enables reads from a single channel, where the channel selected can be either the right or left as determined by the LRP bit in the I2SRXCFG register. July 22, 2011 747 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Table 15-8. I2S Receive FIFO Interface RM bit in I2RXCFG CSS bit in Read Mode I2SRXFIFOCFG Sample Width Samples per FIFO Read Data Alignment Stereo 8-32 bits 1 MSB 0 don't care 1 0 Compact Stereo - 16 bit 8-16 bits 2 MSB Right [31:15], Left [15:0] 1 1 Compact Stereo - 8 bit 8 bits 2 Right [15:8] Left[7:0] 0 don't care 8-32 bits 1 MSB Mono (FMM bit in the I2SRXFIFOCFG register must be set.) The number of samples in the receive FIFO can be read using the I2S Receive FIFO Level (I2SRXLEV) register. The value ranges from 0 to 16. Stereo and compact stereo sample pairs are counted as two. The mono samples also increment the count by two, therefore four Mono samples will have a count of eight. 15.3.2.3 Clock Control The receiver MCLK and SCLK can be independently programmed to be the master or slave. The receiver is programmed to be the master or slave of the SCLK using the MSL bit in the I2SRXCFG register. When the receiver is the master, the I2S0RXSCK frequency is the specified I2S0RXMCLK divided by four. The I2S0RXSCK may be inverted using the SCP bit in the I2SRXCFG register. The receiver can also be the master or slave of the MCLK. When the receiver is the master, the PLL must be active and a fractional clock divider must be programmed. See page 236 for the setup for the master I2S0RXMCLK source. An external transmit I2S0RXMCLK does not require the use of the PLL and is selected using the RXSLV bit in the I2SCFG register. Refer to “Clock Control” on page 744 for combinations of the RXINT and RXFRAC bits in the I2S MCLK Configuration (I2SMCLKCFG) register that provide MCLK frequencies within acceptable error limits. In the table, Fs is the sampling frequency in kHz and possible crystal frequencies are shown in MHz across the top row of the table. The words "not supported" in the table mean that it is not possible to obtain the specified sampling frequencies with the specified crystal frequency within the error tolerance of 0.3%. 15.3.2.4 Interrupt Control A single interrupt is asserted to the CPU whenever any of the transmit or receive sources is asserted. The receive module has two interrupt sources: the FIFO service request and read error. The interrupts may be masked using the RXSRIM and RXREIM bits in the I2SIM register. The status of the interrupt source is indicated by the I2SRIS register. The status of enabled interrupts is indicated by the I2SMIS register. The FIFO service request interrupt has a second level of masking using the FFM bit in the I2S Receive Interrupt Status and Mask (I2SRXISM) register. The sources may be masked using the I2SIM register. The FIFO service request interrupt is asserted when the FIFO level (indicated by the LEVEL field in the I2S Receive FIFO Level (I2SRXLEV) register) is above the FIFO limit (programmed using the I2S Receive FIFO Limit (I2SRXLIMIT) register) and both the RXSRIM and FFM bits are set. An error occurs when reading an empty FIFO or if a stereo sample pair is not read left then right. To clear an interrupt, write a 1 to the appropriate bit in the I2SIC register. If software attempts to read an empty FIFO or if a stereo sample pair is not read left then right, a Receive FIFO Read error occurs (indicated by the RXRERIS bit in the I2SRIS register). The RXRERIS bit in the I2SRIS register and the RXREMIS bit in the I2SMIS register are cleared by setting the RXREIC bit in the I2SIC register. 748 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 15.3.2.5 DMA Support The µDMA can be used to more efficiently stream data to and from the I2S bus. The I2S transmit and receive modules have separate µDMA channels. The FIFO Interrupt Mask bit (FFM) in the I2SRXISM register must be set for the request signaling to propagate to the µDMA module. See “Micro Direct Memory Access (μDMA)” on page 333 for channel configuration. The I2S module uses the µDMA burst request signal, not the single request. Thus each time a µDMA request is made, the µDMA controller transfers the number of items specified as the burst size for the µDMA channel. Therefore, the µDMA channel burst size and the I2S FIFO service request limit must be set to the same value (using the LIMIT field in the I2SRXLIMIT register). 15.4 Initialization and Configuration The default setup for the I2S transmit and receive is to use external MCLK, external SCLK, Stereo, I2S audio format, and 32-bit data samples. The following example shows how to configure a system using the internal MCLK, internal SCLK, Compact Stereo, and Left-Justified audio format with 16-bit data samples. 1. Enable the I2S peripheral clock by writing a value of 0x1000.0000 to the RCGC1 register in the System Control module (see page 272). 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module (see page 281). To find out which GPIO port to enable, refer to Table 23-5 on page 1145. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register (see page 416). To determine which GPIOs to configure, see Table 23-4 on page 1137. 4. Configure the PMCn fields in the GPIOPCTL register to assign the I2S signals to the appropriate pins (see page 434 and Table 23-5 on page 1145). 5. Set up the MCLK sources for a 48-kHz sample rate. The input crystal is assumed to be 6 MHz for this example (internal source). ■ Enable the PLL by clearing the PWRDWN bit in the RCC register in the System Control module (see page 221). ■ Set the MCLK dividers and enable them by writing 0x0208.0208 to the I2SMCLKCFG register in the System Control module (see page 236). ■ Enable the MCLK internal sources by writing 0x8208.8208 to the I2SMCLKCFG register in the System Control module. To allow an external MCLK to be used, set bits 4 and 5 of the I2SCFG register. Starting up the PLL and enabling the MCLK sources is not required. 6. Set up the Serial Bit Clock SCLK source. By default, the SCLK is externally sourced. ■ Receiver: Masters the I2S0RXSCK by ORing 0x0040.0000 into the I2SRXCFG register. ■ Transmitter: Masters the I2S0TXSCK by ORing 0x0040.0000 into the I2STXCFG register. 7. Configure the Serial Encoder/Decoder (Left-Justified, Compact Stereo, 16-bit samples, 32-bit system data size). July 22, 2011 749 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface ■ Set the audio format using the Justification (JST), Data Delay (DLY), SCLK polarity (SCP), and Left-Right Polarity (LRP) bits written to the I2STXCFG and I2SRXCFG registers. The settings are shown in the table below. Table 15-9. Audio Formats Configuration I2STXCFG/I2SRXCFG Register Bit Audio Format JST DLY SCP LRP I2S 0 1 0 1 Left-Justified 0 0 0 0 Right-Justified 1 0 0 0 ■ Write 0x0140.3DF0 to both the I2STXCFG and I2SRXCFG registers to program the following configurations: – Set the sample size to 16 bits using the SSZ field of the I2STXCFG and I2SRXCFG registers. – Set the system data size to 32 bits using the SDSZ field of the I2STXCFG and I2SRXCFG registers. – Set the Write and Read modes using the WM and RM fields in the I2STXCFG and I2SRXCFG registers, respectively. 8. Set up the FIFO limits for triggering interrupts (also used for µDMA) ■ Set up the transmit FIFO to trigger when it has less than four sample pairs by writing a 0x0000.0008 to the I2STXLIMIT register. ■ Set up the receive FIFO to trigger when there are more than four sample pairs by writing a 0x0000.00008 to the I2SRXLIMIT register. 9. Enable interrupts. ■ Enable the transmit FIFO interrupt by setting the FFM bit in the I2STXISM register (write 0x0000.0001). ■ Set up the receive FIFO interrupts by setting the FFM bit in the I2SRXISM register (write 0x0000.0001). ■ Enable the TX FIFO service request, the TX Error, the RX FIFO service request, and the RX Error interrupts to be sent to the CPU by writing a 0x0000.0033 to the I2SSIM register. 10. Enable the Serial Encoder and Serial Decoders by writing a 0x0000.0003 to the I2SCFG register. 15.5 Register Map Table 15-10 on page 751 lists the I2S registers. The offset listed is a hexadecimal increment to the register’s address, relative to the I2S interface base address of 0x4005.4000. Note that the I2S module clock must be enabled before the registers can be programmed (see page 272). There must be a delay of 3 system clocks after the I2S module clock is enabled before any I2S module registers are accessed. 750 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 15-10. Inter-Integrated Circuit Sound (I2S) Interface Register Map Name Type Reset 0x000 I2STXFIFO WO 0x0000.0000 I2S Transmit FIFO Data 752 0x004 I2STXFIFOCFG R/W 0x0000.0000 I2S Transmit FIFO Configuration 753 0x008 I2STXCFG R/W 0x1400.7DF0 I2S Transmit Module Configuration 754 0x00C I2STXLIMIT R/W 0x0000.0000 I2S Transmit FIFO Limit 756 0x010 I2STXISM R/W 0x0000.0000 I2S Transmit Interrupt Status and Mask 757 0x018 I2STXLEV RO 0x0000.0000 I2S Transmit FIFO Level 758 0x800 I2SRXFIFO RO 0x0000.0000 I2S Receive FIFO Data 759 0x804 I2SRXFIFOCFG R/W 0x0000.0000 I2S Receive FIFO Configuration 760 0x808 I2SRXCFG R/W 0x1400.7DF0 I2S Receive Module Configuration 761 0x80C I2SRXLIMIT R/W 0x0000.7FFF I2S Receive FIFO Limit 764 0x810 I2SRXISM R/W 0x0000.0000 I2S Receive Interrupt Status and Mask 765 0x818 I2SRXLEV RO 0x0000.0000 I2S Receive FIFO Level 766 0xC00 I2SCFG R/W 0x0000.0000 I2S Module Configuration 767 0xC10 I2SIM R/W 0x0000.0000 I2S Interrupt Mask 769 0xC14 I2SRIS RO 0x0000.0000 I2S Raw Interrupt Status 771 0xC18 I2SMIS RO 0x0000.0000 I2S Masked Interrupt Status 773 0xC1C I2SIC WO 0x0000.0000 I2S Interrupt Clear 775 15.6 Description See page Offset Register Descriptions The remainder of this section lists and describes the I2S registers, in numerical order by address offset. July 22, 2011 751 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Register 1: I2S Transmit FIFO Data (I2STXFIFO), offset 0x000 This register is the 32-bit serial audio transmit data register. In Stereo mode, the data is written left, right, left, right, and so on. The LRS bit in the I2S Transmit FIFO Configuration (I2STXFIFOCFG) register can be read to verify the next position expected. In Compact 16-bit mode, bits [31:16] contain the right sample, and bits [15:0] contain the left sample. In Compact 8-bit mode, bits [15:8] contain the right sample, and bits [7:0] contain the left sample. In Mono mode, each 32-bit entry is a single sample. Note that if the FIFO is full and a write is attempted, a transmit FIFO write error is generated. I2S Transmit FIFO Data (I2STXFIFO) Base 0x4005.4000 Offset 0x000 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 TXFIFO Type Reset TXFIFO Type Reset Bit/Field Name Type 31:0 TXFIFO WO Reset Description 0x0000.0000 TX Data Serial audio sample data to be transmitted. 752 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: I2S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 This register configures the sample for dual-channel operation. In Stereo mode, the LRS bit toggles between left and right samples as the Transmit FIFO is written. The left sample is written first, followed by the right. I2S Transmit FIFO Configuration (I2STXFIFOCFG) Base 0x4005.4000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 CSS LRS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 CSS R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Compact Stereo Sample Size Value Description 0 LRS R/W 0 0 The transmitter is in Compact 16-bit Stereo Mode with a 16-bit sample size. 1 The transmitter is in Compact 8-bit Stereo Mode with an 8-bit sample size. Left-Right Sample Indicator Value Description 0 The left sample is the next position. 1 The right sample is the next position. In Mono mode and Compact stereo mode, this bit toggles as if it were in Stereo mode, but it has no meaning and should be ignored. July 22, 2011 753 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Register 3: I2S Transmit Module Configuration (I2STXCFG), offset 0x008 This register controls the configuration of the Transmit module. I2S Transmit Module Configuration (I2STXCFG) Base 0x4005.4000 Offset 0x008 Type R/W, reset 0x1400.7DF0 31 30 reserved Type Reset 29 28 27 26 25 24 WM 23 22 20 19 18 17 16 JST DLY SCP LRP FMT MSL RO 0 RO 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 RO 0 RO 0 RO 0 SSZ Type Reset 21 reserved SDSZ Bit/Field Name Type Reset 31:30 reserved RO 0x0 29 JST R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Justification of Output Data Value Description 28 DLY R/W 1 0 The data is Left-Justified. 1 The data is Right-Justified. Data Delay Value Description 27 SCP R/W 0 0 Data is latched on the next latching edge of I2S0TXSCK as defined by the SCP bit. This bit should be clear in Left-Justified or Right-Justified mode. 1 A one-I2S0TXSCK delay from the edge of I2S0TXWS is inserted before data is latched. This bit should be set in I2S mode. SCLK Polarity Value Description 26 LRP R/W 1 0 Data and the I2S0TXWS signal (when the MSL bit is set) are launched on the falling edge of I2S0TXSCK. 1 Data and the I2S0TXWS signal (when the MSL bit is set) are launched on the rising edge of I2S0TXSCK. Left/Right Clock Polarity Value Description 0 I2S0TXWS is high during the transmission of the left channel data. 1 I2S0TXWS is high during the transmission of the right channel data. 754 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 25:24 WM R/W 0x0 Write Mode This bit field selects the mode in which the transmit data is stored in the FIFO and transmitted. Value Description 0x0 Stereo mode 0x1 Compact Stereo mode Left/Right sample packed. Refer to I2STXFIFOCFG for 8/16-bit sample size selection. 23 FMT R/W 0 0x2 Mono mode 0x3 reserved FIFO Empty Value Description 22 MSL R/W 0 0 All zeroes are transmitted if the FIFO is empty. 1 The last sample is transmitted if the FIFO is empty. SCLK Master/Slave Source of serial bit clock (I2S0TXSCK) and Word Select (I2S0TXWS). Value Description 0 The transmitter is a slave using the externally driven I2S0TXSCK and I2S0TXWS signals. 1 The transmitter is a master using the internally generated I2S0TXSCK and I2S0TXWS signals. 21:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:10 SSZ R/W 0x1F Sample Size This field contains the number of bits minus one in the sample. Note: 9:4 SDSZ R/W 0x1F This field is only used in Right-Justified mode. Unused bits are not masked. System Data Size This field contains the number of bits minus one during the high or low phase of the I2S0TXWS signal. 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 755 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Register 4: I2S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C This register sets the lower FIFO limit at which a FIFO service request is issued. I2S Transmit FIFO Limit (I2STXLIMIT) Base 0x4005.4000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 LIMIT Bit/Field Name Type Reset 31:5 reserved RO 0x0000.00 4:0 LIMIT R/W 0x00 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Limit This field sets the FIFO level at which a FIFO service request is issued, generating an interrupt or a µDMA transfer request. The transmit FIFO generates a service request when the number of items in the FIFO is less than the level specified by the LIMIT field. For example, if the LIMIT field is set to 8, then a service request is generated when there are less than 8 samples remaining in the transmit FIFO. 756 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 5: I2S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 This register indicates the transmit interrupt status and interrupt masking control. I2S Transmit Interrupt Status and Mask (I2STXISM) Base 0x4005.4000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset FFI reserved Type Reset RO 0 FFM R/W 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 FFI RO 0 Transmit FIFO Service Request Interrupt Value Description 15:1 reserved RO 0x000 0 FFM R/W 0 0 The FIFO level is equal to or above the FIFO limit. 1 The FIFO level is below the FIFO limit. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Interrupt Mask Value Description 0 The FIFO interrupt is masked and not sent to the CPU. 1 The FIFO interrupt is enabled to be sent to the interrupt controller. July 22, 2011 757 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Register 6: I2S Transmit FIFO Level (I2STXLEV), offset 0x018 The number of samples in the transmit FIFO can be read using the I2STXLEV register. The value ranges from 0 to 16. Stereo and Compact Stereo sample-pairs are counted as two. Mono samples also increment the count by two. For example, the LEVEL field is set to eight if there are four Mono samples. I2S Transmit FIFO Level (I2STXLEV) Base 0x4005.4000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 LEVEL Bit/Field Name Type Reset 31:5 reserved RO 0x0000.00 4:0 LEVEL RO 0x00 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Number of Audio Samples This field contains the number of samples in the FIFO. 758 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 7: I2S Receive FIFO Data (I2SRXFIFO), offset 0x800 Important: This register is read-sensitive. See the register description for details. This register is the 32-bit serial audio receive data register. In Stereo mode, the data is read left, right, left, right, and so on. The LRS bit in the I2S Receive FIFO Configuration (I2SRXFIFOCFG) register can be read to verify the next position expected. In Compact 16-bit mode, bits [31:16] contain the right sample, and bits [15:0] contain the left sample. In Compact 8-bit mode, bits [15:8] contain the right sample, and bits [7:0] contain the left sample. In Mono mode, each 32-bit entry is a single sample. If the FIFO is empty, a read of this register returns a value of 0x0000.0000 and generates a receive FIFO read error. I2S Receive FIFO Data (I2SRXFIFO) Base 0x4005.4000 Offset 0x800 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXFIFO Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RXFIFO Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type 31:0 RXFIFO RO RO 0 Reset RO 0 Description 0x0000.0000 RX Data Serial audio sample data received. The read of an empty FIFO returns a value of 0x0. July 22, 2011 759 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Register 8: I2S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 This register configures the sample for dual-channel operation. In Stereo mode, the LRS bit toggles between Left and Right as the samples are read from the receive FIFO. In Mono mode, both the left and right samples are stored in the FIFO. The FMM bit can be used to read only the left or right sample as determined by the LRP bit. In Compact Stereo 8- or 16-bit mode, both the left and right samples are read in one access from the FIFO. I2S Receive FIFO Configuration (I2SRXFIFOCFG) Base 0x4005.4000 Offset 0x804 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2 FMM R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 FMM CSS LRS R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Mono Mode Value Description 0 The receiver is in Stereo Mode. 1 The receiver is in Mono mode. If the LRP bit in the I2SRXCFG register is clear, data is read while the I2S0RXWS signal is low (Right Channel); if the LRP bit is set, data is read while the I2S0RXWS signal is high (Left Channel). 1 CSS R/W 0 Compact Stereo Sample Size Value Description 0 LRS R/W 0 0 The receiver is in Compact 16-bit Stereo Mode with a 16-bit sample size. 1 The receiver is in Compact 8-bit Stereo Mode with a 8-bit sample size. Left-Right Sample Indicator Value Description 0 The left sample is the next position to be read. 1 The right sample is the next position to be read. This bit is only meaningful in Compact Stereo Mode. 760 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 9: I2S Receive Module Configuration (I2SRXCFG), offset 0x808 This register controls the configuration of the receive module. I2S Receive Module Configuration (I2SRXCFG) Base 0x4005.4000 Offset 0x808 Type R/W, reset 0x1400.7DF0 31 30 reserved Type Reset 29 28 27 26 25 24 23 22 20 19 18 17 16 JST DLY SCP LRP reserved RM reserved MSL RO 0 RO 0 R/W 0 R/W 1 R/W 0 R/W 1 RO 0 R/W 0 RO 0 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 RO 0 RO 0 RO 0 SSZ Type Reset 21 reserved SDSZ Bit/Field Name Type Reset 31:30 reserved RO 0x0 29 JST R/W 0 reserved Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Justification of Input Data Value Description 28 DLY R/W 1 0 The data is Left-Justified. 1 The data is Right-Justified. Data Delay Value Description 27 SCP R/W 0 0 Data is latched on the next latching edge of I2S0RXSCK as defined by the SCP bit. This bit should be clear in Left-Justified or Right-Justified mode. 1 A one-I2S0RXSCK delay from the edge of I2S0RXWS is inserted before data is latched. This bit should be set in I2S mode. SCLK Polarity Value Description 0 Data is latched on the rising edge and the I2S0RXWS signal (when the MSL bit is set) is launched on the falling edge of I2S0RXSCK. 1 Data is latched on the falling edge and the I2S0RXWS signal (when the MSL bit is set) is launched on the rising edge of I2S0RXSCK. July 22, 2011 761 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Bit/Field Name Type Reset 26 LRP R/W 1 Description Left/Right Clock Polarity Value Description 0 In Stereo mode, I2S0RXWS is high during the transmission of the left channel data. In Mono mode, data is read while the I2S0RXWS signal is low (Right Channel). 1 In Stereo mode, I2S0RXWS is high during the transmission of the right channel data. In Mono mode, data is read while the I2S0RXWS signal is high (Left Channel). 25 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24 RM R/W 0 Read Mode This bit selects the mode in which the receive data is received and stored in the FIFO. Value Description 0 Stereo/Mono mode I2SRXFIFOCFG FMM bit specifies Stereo or Mono FIFO read behavior. 1 Compact Stereo mode Left/Right sample packed. Refer to I2SRXFIFOCFG for 8/16-bit sample size selection. 23 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22 MSL R/W 0 SCLK Master/Slave Value Description 0 The receiver is a slave and uses the externally driven I2S0RXSCK and I2S0RXWS signals. 1 The receiver is a master and uses the internally generated I2S0RXSCK and I2S0RXWS signals. 21:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:10 SSZ R/W 0x1F Sample Size This field contains the number of bits minus one in the sample. 9:4 SDSZ R/W 0x1F System Data Size This field contains the number of bits minus one during the high or low phase of the I2S0RXWS signal. 762 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 3:0 reserved RO 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 763 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Register 10: I2S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C This register sets the upper FIFO limit at which a FIFO service request is issued. I2S Receive FIFO Limit (I2SRXLIMIT) Base 0x4005.4000 Offset 0x80C Type R/W, reset 0x0000.7FFF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 1 RO 1 RO 1 RO 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset reserved Type Reset RO 1 LIMIT R/W 1 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:5 reserved RO 0x7FF Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4:0 LIMIT R/W 0x1F FIFO Limit This field sets the FIFO level at which a FIFO service request is issued, generating an interrupt or a µDMA transfer request. The receive FIFO generates a service request when the number of items in the FIFO is greater than the level specified by the LIMIT field. For example, if the LIMIT field is set to 4, then a service request is generated when there are more than 4 samples remaining in the transmit FIFO. 764 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 11: I2S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 This register indicates the receive interrupt status and interrupt masking control. I2S Receive Interrupt Status and Mask (I2SRXISM) Base 0x4005.4000 Offset 0x810 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset FFI reserved Type Reset RO 0 FFM R/W 0 Bit/Field Name Type Reset Description 31:17 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16 FFI RO 0 Receive FIFO Service Request Interrupt Value Description 15:1 reserved RO 0x000 0 FFM R/W 0 0 The FIFO level is equal to or below the FIFO limit. 1 The FIFO level is above the FIFO limit. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Interrupt Mask Value Description 0 The FIFO interrupt is masked and not sent to the CPU. 1 The FIFO interrupt is enabled to be sent to the interrupt controller. July 22, 2011 765 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Register 12: I2S Receive FIFO Level (I2SRXLEV), offset 0x818 The number of samples in the receive FIFO can be read using the I2SRXLEV register. The value ranges from 0 to 16. Stereo and Compact Stereo sample pairs are counted as two. Mono samples also increment the count by two. For example, the LEVEL field is set to eight if there are four Mono samples. I2S Receive FIFO Level (I2SRXLEV) Base 0x4005.4000 Offset 0x818 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 LEVEL Bit/Field Name Type Reset 31:5 reserved RO 0x0000.00 4:0 LEVEL RO 0x00 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Number of Audio Samples This field contains the number of samples in the FIFO. 766 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 13: I2S Module Configuration (I2SCFG), offset 0xC00 This register enables the transmit and receive serial engines and sets the source of the I2S0TXMCLK and I2S0RXMCLK signals. I2S Module Configuration (I2SCFG) Base 0x4005.4000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RXSLV TXSLV RXEN TXEN RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 RXSLV R/W 0 reserved RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Use External I2S0RXMCLK Value Description 4 TXSLV R/W 0 0 The receiver uses the internally generated MCLK as the I2S0RXMCLK signal. See “Clock Control” on page 744 for information on how to program the I2S0RXMCLK. 1 The receiver uses the externally driven I2S0RXMCLK signal. Use External I2S0TXMCLK Value Description 3:2 reserved RO 0x0 1 RXEN R/W 0 0 The transmitter uses the internally generated MCLK as the I2S0TXMCLK signal. See “Clock Control” on page 744 for information on how to program the I2S0TXMCLK. 1 The transmitter uses the externally driven I2S0TXMCLK signal. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Serial Receive Engine Enable Value Description 0 Disables the serial receive engine. 1 Enables the serial receive engine. July 22, 2011 767 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Bit/Field Name Type Reset 0 TXEN R/W 0 Description Serial Transmit Engine Enable Value Description 0 Disables the serial transmit engine. 1 Enables the serial transmit engine. 768 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 14: I2S Interrupt Mask (I2SIM), offset 0xC10 This register masks the interrupts to the CPU. I2S Interrupt Mask (I2SIM) Base 0x4005.4000 Offset 0xC10 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RXREIM RXSRIM TXWEIM TXSRIM RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 RXREIM R/W 0 reserved RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Receive FIFO Read Error Value Description 4 RXSRIM R/W 0 0 The receive FIFO read error interrupt is masked and not sent to the CPU. 1 The receive FIFO read error is enabled to be sent to the interrupt controller. Receive FIFO Service Request Value Description 3:2 reserved RO 0x0 1 TXWEIM R/W 0 0 The receive FIFO service request interrupt is masked and not sent to the CPU. 1 The receive FIFO service request is enabled to be sent to the interrupt controller. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Transmit FIFO Write Error Value Description 0 The transmit FIFO write error interrupt is masked and not sent to the CPU. 1 The transmit FIFO write error is enabled to be sent to the interrupt controller. July 22, 2011 769 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Bit/Field Name Type Reset 0 TXSRIM R/W 0 Description Transmit FIFO Service Request Value Description 0 The transmit FIFO service request interrupt is masked and not sent to the CPU. 1 The transmit FIFO service request is enabled to be sent to the interrupt controller. 770 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 15: I2S Raw Interrupt Status (I2SRIS), offset 0xC14 This register reads the unmasked interrupt status. I2S Raw Interrupt Status (I2SRIS) Base 0x4005.4000 Offset 0xC14 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RXRERIS RXSRRIS Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 RXRERIS RO 0 RO 0 RO 0 reserved RO 0 TXWERIS TXSRRIS RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Receive FIFO Read Error Value Description 1 A receive FIFO read error interrupt has occurred. 0 No interrupt This bit is cleared by setting the RXREIC bit in the I2SIC register. 4 RXSRRIS RO 0 Receive FIFO Service Request Value Description 1 A receive FIFO service request interrupt has occurred. 0 No interrupt This bit is cleared when the level in the receive FIFO has risen to a value greater than the value programmed in the LIMIT field in the I2SRXLIMIT register. 3:2 reserved RO 0x0 1 TXWERIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Transmit FIFO Write Error Value Description 1 A transmit FIFO write error interrupt has occurred. 0 No interrupt This bit is cleared by setting the TXWEIC bit in the I2SIC register. July 22, 2011 771 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Bit/Field Name Type Reset 0 TXSRRIS RO 0 Description Transmit FIFO Service Request Value Description 1 A transmit FIFO service request interrupt has occurred. 0 No interrupt This bit is cleared when the level in the transmit FIFO has fallen to a value less than the value programmed in the LIMIT field in the I2STXLIMIT register. 772 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 16: I2S Masked Interrupt Status (I2SMIS), offset 0xC18 This register reads the masked interrupt status. The mask is defined in the I2SIM register. I2S Masked Interrupt Status (I2SMIS) Base 0x4005.4000 Offset 0xC18 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RXREMIS RXSRMIS Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 RXREMIS RO 0 RO 0 RO 0 reserved RO s RO 0 TXWEMIS TXSRMIS RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Receive FIFO Read Error Value Description 1 An unmasked interrupt was signaled due to a receive FIFO read error. 0 An interrupt has not occurred or is masked. This bit is cleared by setting the RXREIC bit in the I2SIC register. 4 RXSRMIS RO 0 Receive FIFO Service Request Value Description 1 An unmasked interrupt was signaled due to a receive FIFO service request. 0 An interrupt has not occurred or is masked. This bit is cleared when the level in the receive FIFO has risen to a value greater than the value programmed in the LIMIT field in the I2SRXLIMIT register. 3:2 reserved RO 0s0 1 TXWEMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Transmit FIFO Write Error Value Description 1 An unmasked interrupt was signaled due to a transmit FIFO write error. 0 An interrupt has not occurred or is masked. This bit is cleared by setting the TXWEIC bit in the I2SIC register. July 22, 2011 773 Texas Instruments-Production Data Inter-Integrated Circuit Sound (I2S) Interface Bit/Field Name Type Reset 0 TXSRMIS RO 0 Description Transmit FIFO Service Request Value Description 1 An unmasked interrupt was signaled due to a transmit FIFO service request. 0 An interrupt has not occurred or is masked. This bit is cleared when the level in the transmit FIFO has fallen to a value less than the value programmed in the LIMIT field in the I2STXLIMIT register. 774 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 17: I2S Interrupt Clear (I2SIC), offset 0xC1C Writing a 1 to a bit in this register clears the corresponding interrupt. I2S Interrupt Clear (I2SIC) Base 0x4005.4000 Offset 0xC1C Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 8 7 6 5 4 3 2 1 0 TXWEIC reserved WO 0 WO 0 WO 0 WO 0 WO 0 reserved Type Reset reserved Type Reset WO 0 RXREIC Bit/Field Name Type Reset 31:6 reserved WO 0x0000.00 5 RXREIC WO 0 WO 0 reserved WO 0 WO 0 WO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Receive FIFO Read Error Writing a 1 to this bit clears the RXRERIS bit in the I2CRIS register and the RXREMIS bit in the I2CMIS register. 4:2 reserved WO 0x0 1 TXWEIC WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Transmit FIFO Write Error Writing a 1 to this bit clears the TXWERIS bit in the I2CRIS register and the TXWEMIS bit in the I2CMIS register. 0 reserved WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 775 Texas Instruments-Production Data Controller Area Network (CAN) Module 16 Controller Area Network (CAN) Module Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire. Originally created for automotive purposes, it is also used in many embedded control applications (such as industrial and medical). Bit rates up to 1 Mbps are possible at network lengths less than 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at 500 meters). ® The Stellaris LM3S9L71 microcontroller includes two CAN units with the following features: ■ CAN protocol version 2.0 part A/B ■ Bit rates up to 1 Mbps ■ 32 message objects with individual identifier masks ■ Maskable interrupt ■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications ■ Programmable Loopback mode for self-test operation ■ Programmable FIFO mode enables storage of multiple message objects ■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals 776 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 16.1 Block Diagram Figure 16-1. CAN Controller Block Diagram CAN Control CANCTL CANSTS CANERR CANBIT CANINT CANTST CANBRPE CAN Tx CAN Interface 1 APB Pins APB Interface CANIF1CRQ CANIF1CMSK CANIF1MSK1 CANIF1MSK2 CANIF1ARB1 CANIF1ARB2 CANIF1MCTL CANIF1DA1 CANIF1DA2 CANIF1DB1 CANIF1DB2 CAN Core CAN Rx CAN Interface 2 CANIF2CRQ CANIF2CMSK CANIF2MSK1 CANIF2MSK2 CANIF2ARB1 CANIF2ARB2 CANIF2MCTL CANIF2DA1 CANIF2DA2 CANIF2DB1 CANIF2DB2 Message Object Registers CANTXRQ1 CANTXRQ2 CANNWDA1 CANNWDA2 CANMSG1INT CANMSG2INT CANMSG1VAL CANMSG2VAL Message RAM 32 Message Objects 16.2 Signal Description The following table lists the external signals of the CAN controller and describes the function of each. The CAN controller signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the CAN signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the CAN controller function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the CAN signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. July 22, 2011 777 Texas Instruments-Production Data Controller Area Network (CAN) Module Table 16-1. Signals for Controller Area Network (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CAN0Rx 10 30 34 92 PD0 (2) PA4 (5) PA6 (6) PB4 (5) I TTL CAN module 0 receive. CAN0Tx 11 31 35 91 PD1 (2) PA5 (5) PA7 (6) PB5 (5) O TTL CAN module 0 transmit. CAN1Rx 47 PF0 (1) I TTL CAN module 1 receive. CAN1Tx 61 PF1 (1) O TTL CAN module 1 transmit. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 16-2. Signals for Controller Area Network (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CAN0Rx G1 L5 L6 A6 PD0 (2) PA4 (5) PA6 (6) PB4 (5) I TTL CAN module 0 receive. CAN0Tx G2 M5 M6 B7 PD1 (2) PA5 (5) PA7 (6) PB5 (5) O TTL CAN module 0 transmit. CAN1Rx M9 PF0 (1) I TTL CAN module 1 receive. CAN1Tx H12 PF1 (1) O TTL CAN module 1 transmit. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 16.3 Functional Description The Stellaris CAN controller conforms to the CAN protocol version 2.0 (parts A and B). Message transfers that include data, remote, error, and overload frames with an 11-bit identifier (standard) or a 29-bit identifier (extended) are supported. Transfer rates can be programmed up to 1 Mbps. The CAN module consists of three major parts: ■ CAN protocol controller and message handler ■ Message memory ■ CAN register interface A data frame contains data for transmission, whereas a remote frame contains no data and is used to request the transmission of a specific message object. The CAN data/remote frame is constructed as shown in Figure 16-2. 778 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 16-2. CAN Data/Remote Frame Remote Transmission Request Start Of Frame Bus Idle R S Control O Message Delimiter T Field R F Number 1 Of Bits 11 or 29 1 6 Delimiter Bits Data Field CRC Sequence A C K EOP IFS 0 . . . 64 15 1 1 1 7 3 CRC Sequence CRC Field Arbitration Field Bit Stuffing End of Frame Field Bus Idle Interframe Field Acknowledgement Field CAN Data Frame The protocol controller transfers and receives the serial data from the CAN bus and passes the data on to the message handler. The message handler then loads this information into the appropriate message object based on the current filtering and identifiers in the message object memory. The message handler is also responsible for generating interrupts based on events on the CAN bus. The message object memory is a set of 32 identical memory blocks that hold the current configuration, status, and actual data for each message object. These memory blocks are accessed via either of the CAN message object register interfaces. The message memory is not directly accessible in the Stellaris memory map, so the Stellaris CAN controller provides an interface to communicate with the message memory via two CAN interface register sets for communicating with the message objects. The message object memory cannot be directly accessed, so these two interfaces must be used to read or write to each message object. The two message object interfaces allow parallel access to the CAN controller message objects when multiple objects may have new information that must be processed. In general, one interface is used for transmit data and one for receive data. 16.3.1 Initialization To use the CAN controller, the peripheral clock must be enabled using the RCGC0 register (see page 264). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2 register (see page 281). To find out which GPIO port to enable, refer to Table 23-4 on page 1137. Set the GPIO AFSEL bits for the appropriate pins (see page 416). Configure the PMCn fields in the GPIOPCTL register to assign the CAN signals to the appropriate pins. See page 434 and Table 23-5 on page 1145. Software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register (with software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus are stopped and the CANnTX signal is held High. Entering the initialization state does not change the configuration of the CAN controller, the message objects, or the error counters. However, some configuration registers are only accessible while in the initialization state. July 22, 2011 779 Texas Instruments-Production Data Controller Area Network (CAN) Module To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each message object. If a message object is not needed, label it as not valid by clearing the MSGVAL bit in the CAN IFn Arbitration 2 (CANIFnARB2) register. Otherwise, the whole message object must be initialized, as the fields of the message object may not have valid information, causing unexpected results. Both the INIT and CCE bits in the CANCTL register must be set in order to access the CANBIT register and the CAN Baud Rate Prescaler Extension (CANBRPE) register to configure the bit timing. To leave the initialization state, the INIT bit must be cleared. Afterwards, the internal Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (indicating a bus idle condition) before it takes part in bus activities and starts message transfers. Message object initialization does not require the CAN to be in the initialization state and can be done on the fly. However, message objects should all be configured to particular identifiers or set to not valid before message transfer starts. To change the configuration of a message object during normal operation, clear the MSGVAL bit in the CANIFnARB2 register to indicate that the message object is not valid during the change. When the configuration is completed, set the MSGVAL bit again to indicate that the message object is once again valid. 16.3.2 Operation Two sets of CAN Interface Registers (CANIF1x and CANIF2x) are used to access the message objects in the Message RAM. The CAN controller coordinates transfers to and from the Message RAM to and from the registers. The two sets are independent and identical and can be used to queue transactions. Generally, one interface is used to transmit data and one is used to receive data. Once the CAN module is initialized and the INIT bit in the CANCTL register is cleared, the CAN module synchronizes itself to the CAN bus and starts the message transfer. As each message is received, it goes through the message handler's filtering process, and if it passes through the filter, is stored in the message object specified by the MNUM bit in the CAN IFn Command Request (CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and eight data bytes) is stored in the message object. If the Identifier Mask (the MSK bits in the CAN IFn Mask 1 and CAN IFn Mask 2 (CANIFnMSKn) registers) is used, the arbitration bits that are masked to "don't care" may be overwritten in the message object. The CPU may read or write each message at any time via the CAN Interface Registers. The message handler guarantees data consistency in case of concurrent accesses. The transmission of message objects is under the control of the software that is managing the CAN hardware. Message objects can be used for one-time data transfers or can be permanent message objects used to respond in a more periodic manner. Permanent message objects have all arbitration and control set up, and only the data bytes are updated. At the start of transmission, the appropriate TXRQST bit in the CAN Transmission Request n (CANTXRQn) register and the NEWDAT bit in the CAN New Data n (CANNWDAn) register are set. If several transmit messages are assigned to the same message object (when the number of message objects is not sufficient), the whole message object has to be configured before the transmission of this message is requested. The transmission of any number of message objects may be requested at the same time; they are transmitted according to their internal priority, which is based on the message identifier (MNUM) for the message object, with 1 being the highest priority and 32 being the lowest priority. Messages may be updated or set to not valid any time, even when their requested transmission is still pending. The old data is discarded when a message is updated before its pending transmission has started. Depending on the configuration of the message object, the transmission of a message may be requested autonomously by the reception of a remote frame with a matching identifier. 780 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Transmission can be automatically started by the reception of a matching remote frame. To enable this mode, set the RMTEN bit in the CAN IFn Message Control (CANIFnMCTL) register. A matching received remote frame causes the TXRQST bit to be set, and the message object automatically transfers its data or generates an interrupt indicating a remote frame was requested. A remote frame can be strictly a single message identifier, or it can be a range of values specified in the message object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are identified as remote frame requests. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the CANIFnMSKn register to filter which frames are identified as a remote frame request. The MXTD bit in the CANIFnMSK2 register should be set if a remote frame request is expected to be triggered by 29-bit extended identifiers. 16.3.3 Transmitting Message Objects If the internal transmit shift register of the CAN module is ready for loading, and if a data transfer is not occurring between the CAN Interface Registers and message RAM, the valid message object with the highest priority that has a pending transmission request is loaded into the transmit shift register by the message handler and the transmission is started. The message object's NEWDAT bit in the CANNWDAn register is cleared. After a successful transmission, and if no new data was written to the message object since the start of the transmission, the TXRQST bit in the CANTXRQn register is cleared. If the CAN controller is configured to interrupt on a successful transmission of a message object, (the TXIE bit in the CAN IFn Message Control (CANIFnMCTL) register is set), the INTPND bit in the CANIFnMCTL register is set after a successful transmission. If the CAN module has lost the arbitration or if an error occurred during the transmission, the message is re-transmitted as soon as the CAN bus is free again. If, meanwhile, the transmission of a message with higher priority has been requested, the messages are transmitted in the order of their priority. 16.3.4 Configuring a Transmit Message Object The following steps illustrate how to configure a transmit message object. 1. In the CAN IFn Command Mask (CANIFnCMASK) register: ■ Set the WRNRD bit to specify a write to the CANIFnCMASK register; specify whether to transfer the IDMASK, DIR, and MXTD of the message object into the CAN IFn registers using the MASK bit ■ Specify whether to transfer the ID, DIR, XTD, and MSGVAL of the message object into the interface registers using the ARB bit ■ Specify whether to transfer the control bits into the interface registers using the CONTROL bit ■ Specify whether to clear the INTPND bit in the CANIFnMCTL register using the CLRINTPND bit ■ Specify whether to clear the NEWDAT bit in the CANNWDAn register using the NEWDAT bit ■ Specify which bits to transfer using the DATAA and DATAB bits 2. In the CANIFnMSK1 register, use the MSK[15:0] bits to specify which of the bits in the 29-bit or 11-bit message identifier are used for acceptance filtering. Note that MSK[15:0] in this register are used for bits [15:0] of the 29-bit message identifier and are not used for an 11-bit identifier. A value of 0x00 enables all messages to pass through the acceptance filtering. Also July 22, 2011 781 Texas Instruments-Production Data Controller Area Network (CAN) Module note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the UMASK bit in the CANIFnMCTL register. 3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the acceptance filtering. Also note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the UMASK bit in the CANIFnMCTL register. 4. For a 29-bit identifier, configure ID[15:0] in the CANIFnARB1 register to are used for bits [15:0] of the message identifier and ID[12:0] in the CANIFnARB2 register to are used for bits [28:16] of the message identifier. Set the XTD bit to indicate an extended identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to indicate that the message object is valid. 5. For an 11-bit identifier, disregard the CANIFnARB1 register and configure ID[12:2] in the CANIFnARB2 register to are used for bits [10:0] of the message identifier. Clear the XTD bit to indicate a standard identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to indicate that the message object is valid. 6. In the CANIFnMCTL register: ■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering ■ Optionally set the TXIE bit to enable the INTPND bit to be set after a successful transmission ■ Optionally set the RMTEN bit to enable the TXRQST bit to be set on the reception of a matching remote frame allowing automatic transmission ■ Set the EOB bit for a single message object ■ Configure the DLC[3:0] field to specify the size of the data frame. Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits. 7. Load the data to be transmitted into the CAN IFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1, CANIFnDB2) registers. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. 8. Program the number of the message object to be transmitted in the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. 9. When everything is properly configured, set the TXRQST bit in the CANIFnMCTL register. Once this bit is set, the message object is available to be transmitted, depending on priority and bus availability. Note that setting the RMTEN bit in the CANIFnMCTL register can also start message transmission if a matching remote frame has been received. 16.3.5 Updating a Transmit Message Object The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface Registers and neither the MSGVAL bit in the CANIFnARB2 register nor the TXRQST bits in the CANIFnMCTL register have to be cleared before the update. 782 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Even if only some of the data bytes are to be updated, all four bytes of the corresponding CANIFnDAn/CANIFnDBn register have to be valid before the content of that register is transferred to the message object. Either the CPU must write all four bytes into the CANIFnDAn/CANIFnDBn register or the message object is transferred to the CANIFnDAn/CANIFnDBn register before the CPU writes the new data bytes. In order to only update the data in a message object, the WRNRD, DATAA and DATAB bits in the CANIFnMSKn register are set, followed by writing the updated data into CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2 registers, and then the number of the message object is written to the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. To begin transmission of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register. To prevent the clearing of the TXRQST bit in the CANIFnMCTL register at the end of a transmission that may already be in progress while the data is updated, the NEWDAT and TXRQST bits have to be set at the same time in the CANIFnMCTL register. When these bits are set at the same time, NEWDAT is cleared as soon as the new transmission has started. 16.3.6 Accepting Received Message Objects When the arbitration and control field (the ID and XTD bits in the CANIFnARB2 and the RMTEN and DLC[3:0] bits of the CANIFnMCTL register) of an incoming message is completely shifted into the CAN controller, the message handling capability of the controller starts scanning the message RAM for a matching valid message object. To scan the message RAM for a matching message object, the controller uses the acceptance filtering programmed through the mask bits in the CANIFnMSKn register and enabled using the UMASK bit in the CANIFnMCTL register. Each valid message object, starting with object 1, is compared with the incoming message to locate a matching message object in the message RAM. If a match occurs, the scanning is stopped and the message handler proceeds depending on whether it is a data frame or remote frame that was received. 16.3.7 Receiving a Data Frame The message handler stores the message from the CAN controller receive shift register into the matching message object in the message RAM. The data bytes, all arbitration bits, and the DLC bits are all stored into the corresponding message object. In this manner, the data bytes are connected with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register is set to indicate that new data has been received. The CPU should clear this bit when it reads the message object to indicate to the controller that the message has been received, and the buffer is free to receive more messages. If the CAN controller receives a message and the NEWDAT bit is already set, the MSGLST bit in the CANIFnMCTL register is set to indicate that the previous data was lost. If the system requires an interrupt on successful reception of a frame, the RXIE bit of the CANIFnMCTL register should be set. In this case, the INTPND bit of the same register is set, causing the CANINT register to point to the message object that just received a message. The TXRQST bit of this message object should be cleared to prevent the transmission of a remote frame. 16.3.8 Receiving a Remote Frame A remote frame contains no data, but instead specifies which object should be transmitted. When a remote frame is received, three different configurations of the matching message object have to be considered: July 22, 2011 783 Texas Instruments-Production Data Controller Area Network (CAN) Module Table 16-3. Message Object Configurations Configuration in CANIFnMCTL ■ ■ DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this CANIFnARB2 register message object is set. The rest of the message object remains unchanged, and the controller automatically transfers the data in RMTEN = 1 (set the TXRQST bit of the the message object as soon as possible. CANIFnMCTL register at reception of the frame to enable transmission) ■ UMASK = 1 or 0 ■ DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this CANIFnARB2 register message object remains unchanged, and the remote frame is ignored. This remote frame is disabled, the data is not transferred RMTEN = 0 (do not change the TXRQST bit of the and nothing indicates that the remote frame ever happened. CANIFnMCTL register at reception of the frame) ■ ■ UMASK = 0 (ignore mask in the CANIFnMSKn register) ■ DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this message object is cleared. The arbitration and control field (ID + CANIFnARB2 register XTD + RMTEN + DLC) from the shift register is stored into the message RMTEN = 0 (do not change the TXRQST bit of the object in the message RAM, and the NEWDAT bit of this message CANIFnMCTL register at reception of the frame) object is set. The data field of the message object remains unchanged; the remote frame is treated similar to a received data UMASK = 1 (use mask (MSK, MXTD, and MDIR in frame. This mode is useful for a remote data request from another the CANIFnMSKn register) for acceptance filtering) CAN device for which the Stellaris controller does not have readily available data. The software must fill the data and answer the frame manually. ■ ■ 16.3.9 Description Receive/Transmit Priority The receive/transmit priority for the message objects is controlled by the message number. Message object 1 has the highest priority, while message object 32 has the lowest priority. If more than one transmission request is pending, the message objects are transmitted in order based on the message object with the lowest message number. This prioritization is separate from that of the message identifier which is enforced by the CAN bus. As a result, if message object 1 and message object 2 both have valid messages to be transmitted, message object 1 is always transmitted first regardless of the message identifier in the message object itself. 16.3.10 Configuring a Receive Message Object The following steps illustrate how to configure a receive message object. 1. Program the CAN IFn Command Mask (CANIFnCMASK) register as described in the “Configuring a Transmit Message Object” on page 781 section, except that the WRNRD bit is set to specify a write to the message RAM. 2. Program the CANIFnMSK1and CANIFnMSK2 registers as described in the “Configuring a Transmit Message Object” on page 781 section to configure which bits are used for acceptance filtering. Note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the UMASK bit in the CANIFnMCTL register. 3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and 784 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the acceptance filtering. Also note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the UMASK bit in the CANIFnMCTL register. 4. Program the CANIFnARB1 and CANIFnARB2 registers as described in the “Configuring a Transmit Message Object” on page 781 section to program XTD and ID bits for the message identifier to be received; set the MSGVAL bit to indicate a valid message; and clear the DIR bit to specify receive. 5. In the CANIFnMCTL register: ■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering ■ Optionally set the RXIE bit to enable the INTPND bit to be set after a successful reception ■ Clear the RMTEN bit to leave the TXRQST bit unchanged ■ Set the EOB bit for a single message object ■ Configure the DLC[3:0] field to specify the size of the data frame Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits. 6. Program the number of the message object to be received in the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. Reception of the message object begins as soon as a matching frame is available on the CAN bus. When the message handler stores a data frame in the message object, it stores the received Data Length Code and eight data bytes in the CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2 register. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. If the Data Length Code is less than 8, the remaining bytes of the message object are overwritten by unspecified values. The CAN mask registers can be used to allow groups of data frames to be received by a message object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register should be set if only 29-bit extended identifiers are expected by this message object. 16.3.11 Handling of Received Message Objects The CPU may read a received message any time via the CAN Interface registers because the data consistency is guaranteed by the message handler state machine. Typically, the CPU first writes 0x007F to the CANIFnCMSK register and then writes the number of the message object to the CANIFnCRQ register. That combination transfers the whole received message from the message RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn, and CANIFnMCTL). Additionally, the NEWDAT and INTPND bits are cleared in the message RAM, acknowledging that the message has been read and clearing the pending interrupt generated by this message object. If the message object uses masks for acceptance filtering, the CANIFnARBn registers show the full, unmasked ID for the received message. July 22, 2011 785 Texas Instruments-Production Data Controller Area Network (CAN) Module The NEWDAT bit in the CANIFnMCTL register shows whether a new message has been received since the last time this message object was read. The MSGLST bit in the CANIFnMCTL register shows whether more than one message has been received since the last time this message object was read. MSGLST is not automatically cleared, and should be cleared by software after reading its status. Using a remote frame, the CPU may request new data from another CAN node on the CAN bus. Setting the TXRQST bit of a receive object causes the transmission of a remote frame with the receive object's identifier. This remote frame triggers the other CAN node to start the transmission of the matching data frame. If the matching data frame is received before the remote frame could be transmitted, the TXRQST bit is automatically reset. This prevents the possible loss of data when the other device on the CAN bus has already transmitted the data slightly earlier than expected. 16.3.11.1 Configuration of a FIFO Buffer With the exception of the EOB bit in the CANIFnMCTL register, the configuration of receive message objects belonging to a FIFO buffer is the same as the configuration of a single receive message object (see “Configuring a Receive Message Object” on page 784). To concatenate two or more message objects into a FIFO buffer, the identifiers and masks (if used) of these message objects have to be programmed to matching values. Due to the implicit priority of the message objects, the message object with the lowest message object number is the first message object in a FIFO buffer. The EOB bit of all message objects of a FIFO buffer except the last one must be cleared. The EOB bit of the last message object of a FIFO buffer is set, indicating it is the last entry in the buffer. 16.3.11.2 Reception of Messages with FIFO Buffers Received messages with identifiers matching to a FIFO buffer are stored starting with the message object with the lowest message number. When a message is stored into a message object of a FIFO buffer, the NEWDAT of the CANIFnMCTL register bit of this message object is set. By setting NEWDAT while EOB is clear, the message object is locked and cannot be written to by the message handler until the CPU has cleared the NEWDAT bit. Messages are stored into a FIFO buffer until the last message object of this FIFO buffer is reached. Until all of the preceding message objects have been released by clearing the NEWDAT bit, all further messages for this FIFO buffer are written into the last message object of the FIFO buffer and therefore overwrite previous messages. 16.3.11.3 Reading from a FIFO Buffer When the CPU transfers the contents of a message object from a FIFO buffer by writing its number to the CANIFnCRQ register, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should be set such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the read. The values of these bits in the CANIFnMCTL register always reflect the status of the message object before the bits are cleared. To assure the correct function of a FIFO buffer, the CPU should read out the message objects starting with the message object with the lowest message number. When reading from the FIFO buffer, the user should be aware that a new received message could be placed in the location of any message object for which the NEWDAT bit of the CANIFnMCTL register is clear. As a result, the order of the received messages in the FIFO is not guaranteed. Figure 16-3 on page 787 shows how a set of message objects which are concatenated to a FIFO Buffer can be handled by the CPU. 786 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 16-3. Message Objects in a FIFO Buffer START Message Interrupt Read Interrupt Pointer 0x0000 Case Interrupt Pointer else 0x8000 END Status Change Interrupt Handling MNUM = Interrupt Pointer Write MNUM to IFn Command Request (Read Message to IFn Registers, Reset NEWDAT = 0, Reset INTPND = 0 Read IFn Message Control Yes No NEWDAT = 1 Read Data from IFn Data A,B EOB = 1 Yes No MNUM = MNUM + 1 16.3.12 Handling of Interrupts If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt with the highest priority, disregarding their chronological order. The status interrupt has the highest July 22, 2011 787 Texas Instruments-Production Data Controller Area Network (CAN) Module priority. Among the message interrupts, the message object's interrupt with the lowest message number has the highest priority. A message interrupt is cleared by clearing the message object's INTPND bit in the CANIFnMCTL register or by reading the CAN Status (CANSTS) register. The status Interrupt is cleared by reading the CANSTS register. The interrupt identifier INTID in the CANINT register indicates the cause of the interrupt. When no interrupt is pending, the register reads as 0x0000. If the value of the INTID field is different from 0, then an interrupt is pending. If the IE bit is set in the CANCTL register, the interrupt line to the interrupt controller is active. The interrupt line remains active until the INTID field is 0, meaning that all interrupt sources have been cleared (the cause of the interrupt is reset), or until IE is cleared, which disables interrupts from the CAN controller. The INTID field of the CANINT register points to the pending message interrupt with the highest interrupt priority. The SIE bit in the CANCTL register controls whether a change of the RXOK, TXOK, and LEC bits in the CANSTS register can cause an interrupt. The EIE bit in the CANCTLregister controls whether a change of the BOFF and EWARN bits in the CANSTS register can cause an interrupt. The IE bit in the CANCTL register controls whether any interrupt from the CAN controller actually generates an interrupt to the interrupt controller. The CANINT register is updated even when the IE bit in the CANCTL register is clear, but the interrupt is not indicated to the CPU. A value of 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN module has updated, but not necessarily changed, the CANSTS register, indicating that either an error or status interrupt has been generated. A write access to the CANSTS register can clear the RXOK, TXOK, and LEC bits in that same register; however, the only way to clear the source of a status interrupt is to read the CANSTS register. The source of an interrupt can be determined in two ways during interrupt handling. The first is to read the INTID bit in the CANINT register to determine the highest priority interrupt that is pending, and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see all of the message objects that have pending interrupts. An interrupt service routine reading the message that is the source of the interrupt may read the message and clear the message object's INTPND bit at the same time by setting the CLRINTPND bit in the CANIFnCMSK register. Once the INTPND bit has been cleared, the CANINT register contains the message number for the next message object with a pending interrupt. 16.3.13 Test Mode A Test Mode is provided which allows various diagnostics to be performed. Test Mode is entered by setting the TEST bit in the CANCTL register. Once in Test Mode, the TX[1:0], LBACK, SILENT and BASIC bits in the CAN Test (CANTST) register can be used to put the CAN controller into the various diagnostic modes. The RX bit in the CANTST register allows monitoring of the CANnRX signal. All CANTST register functions are disabled when the TEST bit is cleared. 16.3.13.1 Silent Mode Silent Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames). The CAN Controller is put in Silent Mode setting the SILENT bit in the CANTST register. In Silent Mode, the CAN controller is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the CAN bus and cannot start a transmission. If the CAN Controller is required to send a dominant bit (ACK bit, overload flag, or active error flag), the bit is rerouted internally so that the CAN Controller monitors this dominant bit, although the CAN bus remains in recessive state. 788 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 16.3.13.2 Loopback Mode Loopback mode is useful for self-test functions. In Loopback Mode, the CAN Controller internally routes the CANnTX signal on to the CANnRX signal and treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into the message buffer. The CAN Controller is put in Loopback Mode by setting the LBACK bit in the CANTST register. To be independent from external stimulation, the CAN Controller ignores acknowledge errors (a recessive bit sampled in the acknowledge slot of a data/remote frame) in Loopback Mode. The actual value of the CANnRX signal is disregarded by the CAN Controller. The transmitted messages can be monitored on the CANnTX signal. 16.3.13.3 Loopback Combined with Silent Mode Loopback Mode and Silent Mode can be combined to allow the CAN Controller to be tested without affecting a running CAN system connected to the CANnTX and CANnRX signals. In this mode, the CANnRX signal is disconnected from the CAN Controller and the CANnTX signal is held recessive. This mode is enabled by setting both the LBACK and SILENT bits in the CANTST register. 16.3.13.4 Basic Mode Basic Mode allows the CAN Controller to be operated without the Message RAM. In Basic Mode, The CANIF1 registers are used as the transmit buffer. The transmission of the contents of the IF1 registers is requested by setting the BUSY bit of the CANIF1CRQ register. The CANIF1 registers are locked while the BUSY bit is set. The BUSY bit indicates that a transmission is pending. As soon the CAN bus is idle, the CANIF1 registers are loaded into the shift register of the CAN Controller and transmission is started. When the transmission has completed, the BUSY bit is cleared and the locked CANIF1 registers are released. A pending transmission can be aborted at any time by clearing the BUSY bit in the CANIF1CRQ register while the CANIF1 registers are locked. If the CPU has cleared the BUSY bit, a possible retransmission in case of lost arbitration or an error is disabled. The CANIF2 Registers are used as a receive buffer. After the reception of a message, the contents of the shift register are stored in the CANIF2 registers, without any acceptance filtering. Additionally, the actual contents of the shift register can be monitored during the message transfer. Each time a read message object is initiated by setting the BUSY bit of the CANIF2CRQ register, the contents of the shift register are stored into the CANIF2 registers. In Basic Mode, all message-object-related control and status bits and of the control bits of the CANIFnCMSK registers are not evaluated. The message number of the CANIFnCRQ registers is also not evaluated. In the CANIF2MCTL register, the NEWDAT and MSGLST bits retain their function, the DLC[3:0] field shows the received DLC, the other control bits are cleared. Basic Mode is enabled by setting the BASIC bit in the CANTST register. 16.3.13.5 Transmit Control Software can directly override control of the CANnTX signal in four different ways. ■ CANnTX is controlled by the CAN Controller ■ The sample point is driven on the CANnTX signal to monitor the bit timing ■ CANnTX drives a low value ■ CANnTX drives a high value July 22, 2011 789 Texas Instruments-Production Data Controller Area Network (CAN) Module The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check the physical layer of the CAN bus. The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register. The three test functions for the CANnTX signal interfere with all CAN protocol functions. TX[1:0] must be cleared when CAN message transfer or Loopback Mode, Silent Mode, or Basic Mode are selected. 16.3.14 Bit Timing Configuration Error Considerations Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the performance of a CAN network can be reduced significantly. In many cases, the CAN bit synchronization amends a faulty configuration of the CAN bit timing to such a degree that only occasionally an error frame is generated. In the case of arbitration, however, when two or more CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the transmitters to become error passive. The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on the CAN bus. 16.3.15 Bit Time and Bit Rate The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member of the CAN network has its own clock generator. The timing parameter of the bit time can be configured individually for each CAN node, creating a common bit rate even though the CAN nodes' oscillator periods may be different. Because of small variations in frequency caused by changes in temperature or voltage and by deteriorating components, these oscillators are not absolutely stable. As long as the variations remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the different bit rates by periodically resynchronizing to the bit stream. According to the CAN specification, the bit time is divided into four segments (see Figure 16-4 on page 791): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable number of time quanta (see Table 16-4 on page 791). The length of the time quantum (tq), which is the basic time unit of the bit time, is defined by the CAN controller's input clock (fsys) and the Baud Rate Prescaler (BRP): tq = BRP / fsys The fsys input clock is the system clock frequency as configured by the RCC or RCC2 registers (see page 221 or page 229). The Synchronization Segment Sync is that part of the bit time where edges of the CAN bus level are expected to occur; the distance between an edge that occurs outside of Sync and the Sync is called the phase error of that edge. The Propagation Time Segment Prop is intended to compensate for the physical delay times within the CAN network. The Phase Buffer Segments Phase1 and Phase2 surround the Sample Point. The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase errors. A given bit rate may be met by different bit-time configurations, but for the proper function of the CAN network, the physical delay times and the oscillator's tolerance range have to be considered. 790 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 16-4. CAN Bit Time Nominal CAN Bit Time a b TSEG1 Sync Prop TSEG2 Phase1 c 1 Time Quantum q) (tq Phase2 Sample Point a. TSEG1 = Prop + Phase1 b. TSEG2 = Phase2 c. Phase1 = Phase2 or Phase1 + 1 = Phase2 a Table 16-4. CAN Protocol Ranges Parameter Range Remark BRP [1 .. 64] Defines the length of the time quantum tq. The CANBRPE register can be used to extend the range to 1024. Sync 1 tq Fixed length, synchronization of bus input to system clock Prop [1 .. 8] tq Compensates for the physical delay times Phase1 [1 .. 8] tq May be lengthened temporarily by synchronization Phase2 [1 .. 8] tq May be shortened temporarily by synchronization SJW [1 .. 4] tq May not be longer than either Phase Buffer Segment a. This table describes the minimum programmable ranges required by the CAN protocol. The bit timing configuration is programmed in two register bytes in the CANBIT register. In the CANBIT register, the four components TSEG2, TSEG1, SJW, and BRP have to be programmed to a numerical value that is one less than its functional value; so instead of values in the range of [1..n], values in the range of [0..n-1] are programmed. That way, for example, SJW (functional range of [1..4]) is represented by only two bits in the SJW bit field. Table 16-5 shows the relationship between the CANBIT register values and the parameters. Table 16-5. CANBIT Register Values CANBIT Register Field Setting TSEG2 Phase2 - 1 TSEG1 Prop + Phase1 - 1 SJW SJW - 1 BRP BRP Therefore, the length of the bit time is (programmed values): [TSEG1 + TSEG2 + 3] × tq or (functional values): [Sync + Prop + Phase1 + Phase2] × tq The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time July 22, 2011 791 Texas Instruments-Production Data Controller Area Network (CAN) Module unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number of time quanta in the bit time. The processing of the bit time, the calculation of the position of the sample point, and occasional synchronizations are controlled by the CAN controller and are evaluated once per time quantum. The CAN controller translates messages to and from frames. In addition, the controller generates and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC code, performs the error management, and decides which type of synchronization is to be used. The bit value is received or transmitted at the sample point. The information processing time (IPT) is the time after the sample point needed to calculate the next bit to be transmitted on the CAN bus. The IPT includes any of the following: retrieving the next data bit, handling a CRC bit, determining if bit stuffing is required, generating an error flag or simply going idle. The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is the lower limit of the programmed length of Phase2. In case of synchronization, Phase2 may be shortened to a value less than IPT, which does not affect bus timing. 16.3.16 Calculating the Bit Timing Parameters Usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. The resulting bit time (1/bit rate) must be an integer multiple of the system clock period. The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the required bit time, allowing iterations of the following steps. The first part of the bit time to be defined is Prop. Its length depends on the delay times measured in the system. A maximum bus length as well as a maximum node delay has to be defined for expandable CAN bus systems. The resulting time for Prop is converted into time quanta (rounded up to the nearest integer multiple of tq). Sync is 1 tq long (fixed), which leaves (bit time - Prop - 1) tq for the two Phase Buffer Segments. If the number of remaining tq is even, the Phase Buffer Segments have the same length, that is, Phase2 = Phase1, else Phase2 = Phase1 + 1. The minimum nominal length of Phase2 has to be regarded as well. Phase2 may not be shorter than the CAN controller's Information Processing Time, which is, depending on the actual implementation, in the range of [0..2] tq. The length of the synchronization jump width is set to the least of 4, Phase1 or Phase2. The oscillator tolerance range necessary for the resulting configuration is calculated by the formula given below: (1 − df ) × fnom ≤ fosc ≤ (1 + df ) × fnom where: df ≤ (Phase _ seg1, Phase _ seg2) min 2 × (13 × tbit − Phase _ Seg 2) ■ df = Maximum tolerance of oscillator frequency ■ fosc Actual=oscillator df =max 2 × dffrequency × fnom ■ fnom = Nominal oscillator frequency Maximum frequency tolerance must take into account the following formulas: 792 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller − )df × fnom ≤ fosc + )df × fnom (1 −(1df × )fnom ≤ fosc ≤ (1≤ +(1df × )fnom (Phase _ seg 1, Phase _ seg 2) min (Phase _ seg 1, Phase _ seg 2) min df df ≤ ≤ 2 × (13 × tbit − Phase _ Seg 2) 2 × (13 × tbit − Phase _ Seg 2) × df × fnom df df maxmax = 2=× 2df × fnom where: ■ Phase1 and Phase2 are from Table 16-4 on page 791 ■ tbit = Bit Time ■ dfmax = Maximum difference between two oscillators If more than one configuration is possible, that configuration allowing the highest oscillator tolerance range should be chosen. CAN nodes with different system clocks require different configurations to come to the same bit rate. The calculation of the propagation time in the CAN network, based on the nodes with the longest delay times, is done once for the whole network. The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range. The calculation may show that bus length or bit rate have to be decreased or that the oscillator frequencies' stability has to be increased in order to find a protocol-compliant configuration of the CAN bit timing. 16.3.16.1 Example for Bit Timing at High Baud Rate In this example, the frequency of CAN clock is 25 MHz, and the bit rate is 1 Mbps. bit time = 1 µs = n * tq = 5 * tq = 200 ns tq = (Baud rate Prescaler)/CAN Baud rate Prescaler = tq * CAN Baud rate Prescaler = 200E-9 * tq Clock Clock 25E6 = 5 tSync = 1 * tq = 200 ns \\fixed at 1 time quanta delay delay delay tProp \\400 is next integer multiple of tq of bus driver 50 ns of receiver circuit 30 ns of bus line (40m) 220 ns 400 ns = 2 * tq bit time = tSync + bit time = tSync + tPhase 1 + tPhase2 tPhase 1 + tPhase2 tPhase 1 + tPhase2 tPhase1 = 1 * tq tPhase2 = 1 * tq tTSeg1 + tTSeg2 = 5 * tq tProp + tPhase 1 + tPhase2 = bit time - tSync - tProp = (5 * tq) - (1 * tq) - (2 * tq) = 2 * tq \\tPhase2 = tPhase1 July 22, 2011 793 Texas Instruments-Production Data Controller Area Network (CAN) Module tTSeg1 = tProp + tPhase1 tTSeg1 = (2 * tq) + (1 * tq) tTSeg1 = 3 * tq tTSeg2 = tPhase2 tTSeg2 = (Information Processing Time + 1) * tq tTSeg2 = 1 * tq \\Assumes IPT=0 tSJW = 1 * tq \\Least of 4, Phase1 and Phase2 In the above example, the bit field values for the CANBIT register are: = TSeg2 -1 TSEG2 = 1-1 =0 = TSeg1 -1 TSEG1 = 3-1 =2 = SJW -1 SJW = 1-1 =0 = Baud rate prescaler - 1 BRP = 5-1 =4 The final value programmed into the CANBIT register = 0x0204. 16.3.16.2 Example for Bit Timing at Low Baud Rate In this example, the frequency of the CAN clock is 50 MHz, and the bit rate is 100 Kbps. bit time = 10 µs = n * tq = 10 * tq tq = 1 µs tq = (Baud rate Prescaler)/CAN Clock Baud rate Prescaler = tq * CAN Clock Baud rate Prescaler = 1E-6 * 50E6 = 50 tSync = 1 * tq = 1 µs \\fixed at 1 time quanta delay delay delay tProp \\1 µs is next integer multiple of tq of bus driver 200 ns of receiver circuit 80 ns of bus line (40m) 220 ns 1 µs = 1 * tq bit time = tSync + bit time = tSync + tPhase 1 + tPhase2 tPhase 1 + tPhase2 tPhase 1 + tPhase2 tPhase1 = 4 * tq tPhase2 = 4 * tq tTSeg1 + tTSeg2 = 10 * tq tProp + tPhase 1 + tPhase2 = bit time - tSync - tProp = (10 * tq) - (1 * tq) - (1 * tq) = 8 * tq \\tPhase1 = tPhase2 794 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller tTSeg1 tTSeg1 tTSeg1 tTSeg2 tTSeg2 tTSeg2 = = = = = = tProp + tPhase1 (1 * tq) + (4 * tq) 5 * tq tPhase2 (Information Processing Time + 4) × tq 4 * tq \\Assumes IPT=0 tSJW = 4 * tq \\Least of 4, Phase1, and Phase2 = TSeg2 -1 TSEG2 = 4-1 =3 = TSeg1 -1 TSEG1 = 5-1 =4 = SJW -1 SJW = 4-1 =3 = Baud rate prescaler - 1 BRP = 50-1 =49 The final value programmed into the CANBIT register = 0x34F1. 16.4 Register Map Table 16-6 on page 795 lists the registers. All addresses given are relative to the CAN base address of: ■ CAN0: 0x4004.0000 ■ CAN1: 0x4004.1000 Note that the CAN controller clock must be enabled before the registers can be programmed (see page 264). There must be a delay of 3 system clocks after the CAN module clock is enabled before any CAN module registers are accessed. Table 16-6. CAN Register Map Offset Name Type Reset Description See page 0x000 CANCTL R/W 0x0000.0001 CAN Control 798 0x004 CANSTS R/W 0x0000.0000 CAN Status 800 0x008 CANERR RO 0x0000.0000 CAN Error Counter 803 0x00C CANBIT R/W 0x0000.2301 CAN Bit Timing 804 0x010 CANINT RO 0x0000.0000 CAN Interrupt 805 0x014 CANTST R/W 0x0000.0000 CAN Test 806 0x018 CANBRPE R/W 0x0000.0000 CAN Baud Rate Prescaler Extension 808 0x020 CANIF1CRQ R/W 0x0000.0001 CAN IF1 Command Request 809 July 22, 2011 795 Texas Instruments-Production Data Controller Area Network (CAN) Module Table 16-6. CAN Register Map (continued) Name Type Reset 0x024 CANIF1CMSK R/W 0x0000.0000 CAN IF1 Command Mask 810 0x028 CANIF1MSK1 R/W 0x0000.FFFF CAN IF1 Mask 1 813 0x02C CANIF1MSK2 R/W 0x0000.FFFF CAN IF1 Mask 2 814 0x030 CANIF1ARB1 R/W 0x0000.0000 CAN IF1 Arbitration 1 816 0x034 CANIF1ARB2 R/W 0x0000.0000 CAN IF1 Arbitration 2 817 0x038 CANIF1MCTL R/W 0x0000.0000 CAN IF1 Message Control 819 0x03C CANIF1DA1 R/W 0x0000.0000 CAN IF1 Data A1 822 0x040 CANIF1DA2 R/W 0x0000.0000 CAN IF1 Data A2 822 0x044 CANIF1DB1 R/W 0x0000.0000 CAN IF1 Data B1 822 0x048 CANIF1DB2 R/W 0x0000.0000 CAN IF1 Data B2 822 0x080 CANIF2CRQ R/W 0x0000.0001 CAN IF2 Command Request 809 0x084 CANIF2CMSK R/W 0x0000.0000 CAN IF2 Command Mask 810 0x088 CANIF2MSK1 R/W 0x0000.FFFF CAN IF2 Mask 1 813 0x08C CANIF2MSK2 R/W 0x0000.FFFF CAN IF2 Mask 2 814 0x090 CANIF2ARB1 R/W 0x0000.0000 CAN IF2 Arbitration 1 816 0x094 CANIF2ARB2 R/W 0x0000.0000 CAN IF2 Arbitration 2 817 0x098 CANIF2MCTL R/W 0x0000.0000 CAN IF2 Message Control 819 0x09C CANIF2DA1 R/W 0x0000.0000 CAN IF2 Data A1 822 0x0A0 CANIF2DA2 R/W 0x0000.0000 CAN IF2 Data A2 822 0x0A4 CANIF2DB1 R/W 0x0000.0000 CAN IF2 Data B1 822 0x0A8 CANIF2DB2 R/W 0x0000.0000 CAN IF2 Data B2 822 0x100 CANTXRQ1 RO 0x0000.0000 CAN Transmission Request 1 823 0x104 CANTXRQ2 RO 0x0000.0000 CAN Transmission Request 2 823 0x120 CANNWDA1 RO 0x0000.0000 CAN New Data 1 824 0x124 CANNWDA2 RO 0x0000.0000 CAN New Data 2 824 0x140 CANMSG1INT RO 0x0000.0000 CAN Message 1 Interrupt Pending 825 0x144 CANMSG2INT RO 0x0000.0000 CAN Message 2 Interrupt Pending 825 0x160 CANMSG1VAL RO 0x0000.0000 CAN Message 1 Valid 826 0x164 CANMSG2VAL RO 0x0000.0000 CAN Message 2 Valid 826 16.5 Description See page Offset CAN Register Descriptions The remainder of this section lists and describes the CAN registers, in numerical order by address offset. There are two sets of Interface Registers that are used to access the Message Objects in 796 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used to queue transactions. July 22, 2011 797 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 1: CAN Control (CANCTL), offset 0x000 This control register initializes the module and enables test mode and interrupts. The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11 consecutive High bits) before resuming normal operations. At the end of the bus-off recovery sequence, the Error Management Counters are reset. During the waiting time after INIT is cleared, each time a sequence of 11 High bits has been monitored, a BITERROR0 code is written to the CANSTS register (the LEC field = 0x5), enabling the CPU to readily check whether the CAN bus is stuck Low or continuously disturbed, and to monitor the proceeding of the bus-off recovery sequence. CAN Control (CANCTL) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x000 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 TEST CCE DAR reserved EIE SIE IE INIT R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 TEST R/W 0 6 5 CCE DAR R/W R/W 0 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Test Mode Enable Value Description 0 The CAN controller is operating normally. 1 The CAN controller is in test mode. Configuration Change Enable Value Description 0 Write accesses to the CANBIT register are not allowed. 1 Write accesses to the CANBIT register are allowed if the INIT bit is 1. Disable Automatic-Retransmission Value Description 0 Auto-retransmission of disturbed messages is enabled. 1 Auto-retransmission is disabled. 798 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 EIE R/W 0 Error Interrupt Enable 2 1 0 SIE IE INIT R/W R/W R/W 0 0 1 Description Value Description 0 No error status interrupt is generated. 1 A change in the BOFF or EWARN bits in the CANSTS register generates an interrupt. Status Interrupt Enable Value Description 0 No status interrupt is generated. 1 An interrupt is generated when a message has successfully been transmitted or received, or a CAN bus error has been detected. A change in the TXOK, RXOK or LEC bits in the CANSTS register generates an interrupt. CAN Interrupt Enable Value Description 0 Interrupts disabled. 1 Interrupts enabled. Initialization Value Description 0 Normal operation. 1 Initialization started. July 22, 2011 799 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 2: CAN Status (CANSTS), offset 0x004 Important: This register is read-sensitive. See the register description for details. The status register contains information for interrupt servicing such as Bus-Off, error count threshold, and error types. The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This field is cleared when a message has been transferred (reception or transmission) without error. The unused error code 0x7 may be written by the CPU to manually set this field to an invalid error so that it can be checked for a change later. An error interrupt is generated by the BOFF and EWARN bits, and a status interrupt is generated by the RXOK, TXOK, and LEC bits, if the corresponding enable bits in the CAN Control (CANCTL) register are set. A change of the EPASS bit or a write to the RXOK, TXOK, or LEC bits does not generate an interrupt. Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is pending. CAN Status (CANSTS) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 BOFF RO 0 6 EWARN RO 0 RO 0 7 6 5 4 3 BOFF EWARN EPASS RXOK TXOK RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 LEC R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bus-Off Status Value Description 0 The CAN controller is not in bus-off state. 1 The CAN controller is in bus-off state. Warning Status Value Description 0 Both error counters are below the error warning limit of 96. 1 At least one of the error counters has reached the error warning limit of 96. 800 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 5 EPASS RO 0 4 RXOK R/W 0 Description Error Passive Value Description 0 The CAN module is in the Error Active state, that is, the receive or transmit error count is less than or equal to 127. 1 The CAN module is in the Error Passive state, that is, the receive or transmit error count is greater than 127. Received a Message Successfully Value Description 0 Since this bit was last cleared, no message has been successfully received. 1 Since this bit was last cleared, a message has been successfully received, independent of the result of the acceptance filtering. This bit must be cleared by writing a 0 to it. 3 TXOK R/W 0 Transmitted a Message Successfully Value Description 0 Since this bit was last cleared, no message has been successfully transmitted. 1 Since this bit was last cleared, a message has been successfully transmitted error-free and acknowledged by at least one other node. This bit must be cleared by writing a 0 to it. July 22, 2011 801 Texas Instruments-Production Data Controller Area Network (CAN) Module Bit/Field Name Type Reset 2:0 LEC R/W 0x0 Description Last Error Code This is the type of the last error to occur on the CAN bus. Value Description 0x0 No Error 0x1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x2 Format Error A fixed format part of the received frame has the wrong format. 0x3 ACK Error The message transmitted was not acknowledged by another node. 0x4 Bit 1 Error When a message is transmitted, the CAN controller monitors the data lines to detect any conflicts. When the arbitration field is transmitted, data conflicts are a part of the arbitration protocol. When other frame fields are transmitted, data conflicts are considered errors. A Bit 1 Error indicates that the device wanted to send a High level (logical 1) but the monitored bus value was Low (logical 0). 0x5 Bit 0 Error A Bit 0 Error indicates that the device wanted to send a Low level (logical 0), but the monitored bus value was High (logical 1). During bus-off recovery, this status is set each time a sequence of 11 High bits has been monitored. By checking for this status, software can monitor the proceeding of the bus-off recovery sequence without any disturbances to the bus. 0x6 CRC Error The CRC checksum was incorrect in the received message, indicating that the calculated value received did not match the calculated CRC of the data. 0x7 No Event When the LEC bit shows this value, no CAN bus event was detected since this value was written to the LEC field. 802 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 3: CAN Error Counter (CANERR), offset 0x008 This register contains the error counter values, which can be used to analyze the cause of an error. CAN Error Counter (CANERR) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x008 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RP Type Reset RO 0 REC TEC RO 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 RP RO 0 14:8 REC RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Received Error Passive Value Description 0 The Receive Error counter is below the Error Passive level (127 or less). 1 The Receive Error counter has reached the Error Passive level (128 or greater). Receive Error Counter This field contains the state of the receiver error counter (0 to 127). 7:0 TEC RO 0x00 Transmit Error Counter This field contains the state of the transmit error counter (0 to 255). July 22, 2011 803 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 4: CAN Bit Timing (CANBIT), offset 0x00C This register is used to program the bit width and bit quantum. Values are programmed to the system clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL register. See “Bit Time and Bit Rate” on page 790 for more information. CAN Bit Timing (CANBIT) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x00C Type R/W, reset 0x0000.2301 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 1 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset TSEG2 reserved Type Reset RO 0 R/W 0 R/W 1 TSEG1 Bit/Field Name Type Reset 31:15 reserved RO 0x0000 14:12 TSEG2 R/W 0x2 SJW BRP Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Time Segment after Sample Point 0x00-0x07: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. So, for example, the reset value of 0x2 means that 3 (2+1) bit time quanta are defined for Phase2 (see Figure 16-4 on page 791). The bit time quanta is defined by the BRP field. 11:8 TSEG1 R/W 0x3 Time Segment Before Sample Point 0x00-0x0F: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. So, for example, the reset value of 0x3 means that 4 (3+1) bit time quanta are defined for Phase1 (see Figure 16-4 on page 791). The bit time quanta is defined by the BRP field. 7:6 SJW R/W 0x0 (Re)Synchronization Jump Width 0x00-0x03: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. During the start of frame (SOF), if the CAN controller detects a phase error (misalignment), it can adjust the length of TSEG2 or TSEG1 by the value in SJW. So the reset value of 0 adjusts the length by 1 bit time quanta. 5:0 BRP R/W 0x1 Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quantum. 0x00-0x03F: The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. BRP defines the number of CAN clock periods that make up 1 bit time quanta, so the reset value is 2 bit time quanta (1+1). The CANBRPE register can be used to further divide the bit time. 804 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 5: CAN Interrupt (CANINT), offset 0x010 This register indicates the source of the interrupt. If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in the CANCTL register is set, the interrupt is active. The interrupt line remains active until the INTID field is cleared by reading the CANSTS register, or until the IE bit in the CANCTL register is cleared. Note: Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is pending. CAN Interrupt (CANINT) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset INTID Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 INTID RO 0x0000 Interrupt Identifier The number in this field indicates the source of the interrupt. Value Description 0x0000 No interrupt pending 0x0001-0x0020 Number of the message object that caused the interrupt 0x0021-0x7FFF Reserved 0x8000 Status Interrupt 0x8001-0xFFFF Reserved July 22, 2011 805 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 6: CAN Test (CANTST), offset 0x014 This register is used for self-test and external pin access. It is write-enabled by setting the TEST bit in the CANCTL register. Different test functions may be combined, however, CAN transfers are affected if the TX bits in this register are not zero. CAN Test (CANTST) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 LBACK SILENT BASIC RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RX RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 RX RO 0 6:5 TX R/W 0x0 TX R/W 0 R/W 0 reserved RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Receive Observation Value Description 0 The CANnRx pin is low. 1 The CANnRx pin is high. Transmit Control Overrides control of the CANnTx pin. Value Description 0x0 CAN Module Control CANnTx is controlled by the CAN module; default operation 0x1 Sample Point The sample point is driven on the CANnTx signal. This mode is useful to monitor bit timing. 0x2 Driven Low CANnTx drives a low value. This mode is useful for checking the physical layer of the CAN bus. 0x3 Driven High CANnTx drives a high value. This mode is useful for checking the physical layer of the CAN bus. 806 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 4 LBACK R/W 0 3 2 1:0 SILENT BASIC reserved R/W R/W RO 0 0 0x0 Description Loopback Mode Value Description 0 Loopback mode is disabled. 1 Loopback mode is enabled. In loopback mode, the data from the transmitter is routed into the receiver. Any data on the receive input is ignored. Silent Mode Value Description 0 Silent mode is disabled. 1 Silent mode is enabled. In silent mode, the CAN controller does not transmit data but instead monitors the bus. This mode is also known as Bus Monitor mode. Basic Mode Value Description 0 Basic mode is disabled. 1 Basic mode is enabled. In basic mode, software should use the CANIF1 registers as the transmit buffer and use the CANIF2 registers as the receive buffer. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 807 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is write-enabled by setting the CCE bit in the CANCTL register. CAN Baud Rate Prescaler Extension (CANBRPE) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3:0 BRPE R/W 0x0 BRPE Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Baud Rate Prescaler Extension 0x00-0x0F: Extend the BRP bit in the CANBIT register to values up to 1023. The actual interpretation by the hardware is one more than the value programmed by BRPE (MSBs) and BRP (LSBs). 808 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 A message transfer is started as soon as there is a write of the message object number to the MNUM field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY bit is automatically set to indicate that a transfer between the CAN Interface Registers and the internal message RAM is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the interface register and the message RAM completes, which then clears the BUSY bit. CAN IF1 Command Request (CANIF1CRQ) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x020 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 reserved Type Reset BUSY Type Reset RO 0 reserved RO 0 MNUM Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 BUSY RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Busy Flag Value Description 0 This bit is cleared when read/write action has finished. 1 This bit is set when a write occurs to the message number in this register. 14:6 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:0 MNUM R/W 0x01 Message Number Selects one of the 32 message objects in the message RAM for data transfer. The message objects are numbered from 1 to 32. Value Description 0x00 Reserved 0 is not a valid message number; it is interpreted as 0x20, or object 32. 0x01-0x20 Message Number Indicates specified message object 1 to 32. 0x21-0x3F Reserved Not a valid message number; values are shifted and it is interpreted as 0x01-0x1F. July 22, 2011 809 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 Reading the Command Mask registers provides status for various functions. Writing to the Command Mask registers specifies the transfer direction and selects which buffer registers are the source or target of the data transfer. Note that when a read from the message object buffer occurs when the WRNRD bit is clear and the CLRINTPND and/or NEWDAT bits are set, the interrupt pending and/or new data flags in the message object buffer are cleared. CAN IF1 Command Mask (CANIF1CMSK) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 2 1 0 DATAA DATAB R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 WRNRD R/W 0 6 MASK R/W 0 WRNRD MASK ARB R/W 0 R/W 0 R/W 0 RO 0 CONTROL CLRINTPND R/W 0 R/W 0 NEWDAT / TXRQST R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Write, Not Read Value Description 0 Transfer the data in the CAN message object specified by the the MNUM field in the CANIFnCRQ register into the CANIFn registers. 1 Transfer the data in the CANIFn registers to the CAN message object specified by the MNUM field in the CAN Command Request (CANIFnCRQ). Note: Interrupt pending and new data conditions in the message buffer can be cleared by reading from the buffer (WRNRD = 0) when the CLRINTPND and/or NEWDAT bits are set. Access Mask Bits Value Description 0 Mask bits unchanged. 1 Transfer IDMASK + DIR + MXTD of the message object into the Interface registers. 810 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 5 ARB R/W 0 4 3 CONTROL CLRINTPND R/W R/W 0 0 Description Access Arbitration Bits Value Description 0 Arbitration bits unchanged. 1 Transfer ID + DIR + XTD + MSGVAL of the message object into the Interface registers. Access Control Bits Value Description 0 Control bits unchanged. 1 Transfer control bits from the CANIFnMCTL register into the Interface registers. Clear Interrupt Pending Bit The function of this bit depends on the configuration of the WRNRD bit. Value 0 Description If WRNRD is clear, the interrupt pending status is transferred from the message buffer into the CANIFnMCTL register. If WRNRD is set, the INTPND bit in the message object remains unchanged. 1 If WRNRD is clear, the interrupt pending status is cleared in the message buffer. Note the value of this bit that is transferred to the CANIFnMCTL register always reflects the status of the bits before clearing. If WRNRD is set, the INTPND bit is cleared in the message object. 2 NEWDAT / TXRQST R/W 0 NEWDAT / TXRQST Bit The function of this bit depends on the configuration of the WRNRD bit. Value 0 Description If WRNRD is clear, the value of the new data status is transferred from the message buffer into the CANIFnMCTL register. If WRNRD is set, a transmission is not requested. 1 If WRNRD is clear, the new data status is cleared in the message buffer. Note the value of this bit that is transferred to the CANIFnMCTL register always reflects the status of the bits before clearing. If WRNRD is set, a transmission is requested. Note that when this bit is set, the TXRQST bit in the CANIFnMCTL register is ignored. July 22, 2011 811 Texas Instruments-Production Data Controller Area Network (CAN) Module Bit/Field Name Type Reset 1 DATAA R/W 0 Description Access Data Byte 0 to 3 The function of this bit depends on the configuration of the WRNRD bit. Value Description 0 Data bytes 0-3 are unchanged. 1 If WRNRD is clear, transfer data bytes 0-3 in CANIFnDA1 and CANIFnDA2 to the message object. If WRNRD is set, transfer data bytes 0-3 in message object to CANIFnDA1 and CANIFnDA2. 0 DATAB R/W 0 Access Data Byte 4 to 7 The function of this bit depends on the configuration of the WRNRD bit as follows: Value Description 0 Data bytes 4-7 are unchanged. 1 If WRNRD is clear, transfer data bytes 4-7 in CANIFnDA1 and CANIFnDA2 to the message object. If WRNRD is set, transfer data bytes 4-7 in message object to CANIFnDA1 and CANIFnDA2. 812 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 The mask information provided in this register accompanies the data (CANIFnDAn), arbitration information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance filtering. Additional mask information is contained in the CANIFnMSK2 register. CAN IF1 Mask 1 (CANIF1MSK1) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x028 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset MSK Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MSK R/W 0xFFFF Identifier Mask When using a 29-bit identifier, these bits are used for bits [15:0] of the ID. The MSK field in the CANIFnMSK2 register are used for bits [28:16] of the ID. When using an 11-bit identifier, these bits are ignored. Value Description 0 The corresponding identifier field (ID) in the message object cannot inhibit the match in acceptance filtering. 1 The corresponding identifier field (ID) is used for acceptance filtering. July 22, 2011 813 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C This register holds extended mask information that accompanies the CANIFnMSK1 register. CAN IF1 Mask 2 (CANIF1MSK2) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 MXTD MDIR reserved R/W 1 R/W 1 RO 1 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset Type Reset MSK Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 MXTD R/W 1 14 13 MDIR reserved R/W RO 1 1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Mask Extended Identifier Value Description 0 The extended identifier bit (XTD in the CANIFnARB2 register) has no effect on the acceptance filtering. 1 The extended identifier bit XTD is used for acceptance filtering. Mask Message Direction Value Description 0 The message direction bit (DIR in the CANIFnARB2 register) has no effect for acceptance filtering. 1 The message direction bit DIR is used for acceptance filtering. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 814 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 12:0 MSK R/W 0xFF Identifier Mask When using a 29-bit identifier, these bits are used for bits [28:16] of the ID. The MSK field in the CANIFnMSK1 register are used for bits [15:0] of the ID. When using an 11-bit identifier, MSK[12:2] are used for bits [10:0] of the ID. Value Description 0 The corresponding identifier field (ID) in the message object cannot inhibit the match in acceptance filtering. 1 The corresponding identifier field (ID) is used for acceptance filtering. July 22, 2011 815 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 These registers hold the identifiers for acceptance filtering. CAN IF1 Arbitration 1 (CANIF1ARB1) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset ID Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 ID R/W 0x0000 Message Identifier This bit field is used with the ID field in the CANIFnARB2 register to create the message identifier. When using a 29-bit identifier, bits 15:0 of the CANIFnARB1 register are [15:0] of the ID, while bits 12:0 of the CANIFnARB2 register are [28:16] of the ID. When using an 11-bit identifier, these bits are not used. 816 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 These registers hold information for acceptance filtering. CAN IF1 Arbitration 2 (CANIF1ARB2) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 MSGVAL XTD DIR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset Type Reset ID Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 MSGVAL R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Message Valid Value Description 0 The message object is ignored by the message handler. 1 The message object is configured and ready to be considered by the message handler within the CAN controller. All unused message objects should have this bit cleared during initialization and before clearing the INIT bit in the CANCTL register. The MSGVAL bit must also be cleared before any of the following bits are modified or if the message object is no longer required: the ID fields in the CANIFnARBn registers, the XTD and DIR bits in the CANIFnARB2 register, or the DLC field in the CANIFnMCTL register. 14 XTD R/W 0 Extended Identifier Value Description 0 An 11-bit Standard Identifier is used for this message object. 1 A 29-bit Extended Identifier is used for this message object. July 22, 2011 817 Texas Instruments-Production Data Controller Area Network (CAN) Module Bit/Field Name Type Reset 13 DIR R/W 0 12:0 ID R/W 0x000 Description Message Direction Value Description 0 Receive. When the TXRQST bit in the CANIFnMCTL register is set, a remote frame with the identifier of this message object is received. On reception of a data frame with matching identifier, that message is stored in this message object. 1 Transmit. When the TXRQST bit in the CANIFnMCTL register is set, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TXRQST bit of this message object is set (if RMTEN=1). Message Identifier This bit field is used with the ID field in the CANIFnARB2 register to create the message identifier. When using a 29-bit identifier, ID[15:0] of the CANIFnARB1 register are [15:0] of the ID, while these bits, ID[12:0], are [28:16] of the ID. When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of the ID. The ID field in the CANIFnARB1 register is ignored. 818 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 This register holds the control information associated with the message object to be sent to the Message RAM. CAN IF1 Message Control (CANIF1MCTL) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 UMASK TXIE RXIE R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RMTEN TXRQST EOB R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset NEWDAT MSGLST INTPND Type Reset R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15 NEWDAT R/W 0 14 MSGLST R/W 0 reserved RO 0 RO 0 DLC Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. New Data Value Description 0 No new data has been written into the data portion of this message object by the message handler since the last time this flag was cleared by the CPU. 1 The message handler or the CPU has written new data into the data portion of this message object. Message Lost Value Description 0 No message was lost since the last time this bit was cleared by the CPU. 1 The message handler stored a new message into this object when NEWDAT was set; the CPU has lost a message. This bit is only valid for message objects when the DIR bit in the CANIFnARB2 register is clear (receive). 13 INTPND R/W 0 Interrupt Pending Value Description 0 This message object is not the source of an interrupt. 1 This message object is the source of an interrupt. The interrupt identifier in the CANINT register points to this message object if there is not another interrupt source with a higher priority. July 22, 2011 819 Texas Instruments-Production Data Controller Area Network (CAN) Module Bit/Field Name Type Reset 12 UMASK R/W 0 11 10 9 8 TXIE RXIE RMTEN TXRQST R/W R/W R/W R/W 0 0 0 0 Description Use Acceptance Mask Value Description 0 Mask is ignored. 1 Use mask (MSK, MXTD, and MDIR bits in the CANIFnMSKn registers) for acceptance filtering. Transmit Interrupt Enable Value Description 0 The INTPND bit in the CANIFnMCTL register is unchanged after a successful transmission of a frame. 1 The INTPND bit in the CANIFnMCTL register is set after a successful transmission of a frame. Receive Interrupt Enable Value Description 0 The INTPND bit in the CANIFnMCTL register is unchanged after a successful reception of a frame. 1 The INTPND bit in the CANIFnMCTL register is set after a successful reception of a frame. Remote Enable Value Description 0 At the reception of a remote frame, the TXRQST bit in the CANIFnMCTL register is left unchanged. 1 At the reception of a remote frame, the TXRQST bit in the CANIFnMCTL register is set. Transmit Request Value Description 0 This message object is not waiting for transmission. 1 The transmission of this message object is requested and is not yet done. Note: If the WRNRD and TXRQST bits in the CANIFnCMSK register are set, this bit is ignored. 820 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 7 EOB R/W 0 Description End of Buffer Value Description 0 Message object belongs to a FIFO Buffer and is not the last message object of that FIFO Buffer. 1 Single message object or last message object of a FIFO Buffer. This bit is used to concatenate two or more message objects (up to 32) to build a FIFO buffer. For a single message object (thus not belonging to a FIFO buffer), this bit must be set. 6:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 DLC R/W 0x0 Data Length Code Value Description 0x0-0x8 Specifies the number of bytes in the data frame. 0x9-0xF Defaults to a data frame with 8 bytes. The DLC field in the CANIFnMCTL register of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it writes DLC to the value given by the received message. July 22, 2011 821 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 These registers contain the data to be sent or that has been received. In a CAN data frame, data byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte is transmitted first. CAN IF1 Data A1 (CANIF1DA1) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset DATA Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 DATA R/W 0x0000 Data The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2 data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2 data bytes 7 and 6. 822 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By reading out these bits, the CPU can check which message object has a transmission request pending. The TXRQST bit of a specific message object can be changed by three sources: (1) the CPU via the CANIFnMCTL register, (2) the message handler state machine after the reception of a remote frame, or (3) the message handler state machine after a successful transmission. The CANTXRQ1 register contains the TXRQST bits of the first 16 message objects in the message RAM; the CANTXRQ2 register contains the TXRQST bits of the second 16 message objects. CAN Transmission Request 1 (CANTXRQ1) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x100 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 TXRQST Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 TXRQST RO 0x0000 Transmission Request Bits Value Description 0 The corresponding message object is not waiting for transmission. 1 The transmission of the corresponding message object is requested and is not yet done. July 22, 2011 823 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By reading these bits, the CPU can check which message object has its data portion updated. The NEWDAT bit of a specific message object can be changed by three sources: (1) the CPU via the CANIFnMCTL register, (2) the message handler state machine after the reception of a data frame, or (3) the message handler state machine after a successful transmission. The CANNWDA1 register contains the NEWDAT bits of the first 16 message objects in the message RAM; the CANNWDA2 register contains the NEWDAT bits of the second 16 message objects. CAN New Data 1 (CANNWDA1) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x120 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 NEWDAT Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 NEWDAT RO 0x0000 New Data Bits Value Description 0 No new data has been written into the data portion of the corresponding message object by the message handler since the last time this flag was cleared by the CPU. 1 The message handler or the CPU has written new data into the data portion of the corresponding message object. 824 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects. By reading these bits, the CPU can check which message object has an interrupt pending. The INTPND bit of a specific message object can be changed through two sources: (1) the CPU via the CANIFnMCTL register, or (2) the message handler state machine after the reception or transmission of a frame. This field is also encoded in the CANINT register. The CANMSG1INT register contains the INTPND bits of the first 16 message objects in the message RAM; the CANMSG2INT register contains the INTPND bits of the second 16 message objects. CAN Message 1 Interrupt Pending (CANMSG1INT) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x140 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset INTPND Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 INTPND RO 0x0000 Interrupt Pending Bits Value Description 0 The corresponding message object is not the source of an interrupt. 1 The corresponding message object is the source of an interrupt. July 22, 2011 825 Texas Instruments-Production Data Controller Area Network (CAN) Module Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects. By reading these bits, the CPU can check which message object is valid. The message valid bit of a specific message object can be changed with the CANIFnARB2 register. The CANMSG1VAL register contains the MSGVAL bits of the first 16 message objects in the message RAM; the CANMSG2VAL register contains the MSGVAL bits of the second 16 message objects in the message RAM. CAN Message 1 Valid (CANMSG1VAL) CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 Offset 0x160 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 MSGVAL Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MSGVAL RO 0x0000 Message Valid Bits Value Description 0 The corresponding message object is not configured and is ignored by the message handler. 1 The corresponding message object is configured and should be considered by the message handler. 826 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 17 Ethernet Controller ® The Stellaris Ethernet Controller consists of a media access controller (MAC) with a Media Independent Interface (MII). The Ethernet MAC conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. The Stellaris Ethernet MAC module has the following features: ■ Conforms to the IEEE 802.3-2002 specification ■ Multiple operational modes – Full- and half-duplex 100 Mbps – Full- and half-duplex 10 Mbps ■ Highly configurable – Programmable MAC address – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts ■ Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers ■ IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive channel request asserted on packet receipt – Transmit channel request asserted on empty transmit FIFO 17.1 Block Diagram As shown in Figure 17-1 on page 827, the Ethernet Controller includes the Media Access Controller (MAC) layer and a Media Independent Interface (MII) interface for communicating to an external PHY layer. These layers correspond to the OSI model layers 2 and 1. The CPU accesses the MAC layer which provides transmit and receive processing for Ethernet frames. The PHY layer communicates with the Ethernet bus. Figure 17-1. Ethernet Controller ARM Cortex M3 Stellaris® Media Access Controller MAC (Layer 2) MII Physical Layer Entity Magnetics RJ45 PHY (Layer 1) July 22, 2011 827 Texas Instruments-Production Data Ethernet Controller Figure 17-2 on page 828 shows more detail of the internal structure of the Ethernet MAC and how the register set relates to various functions. Figure 17-2. Ethernet MAC Block Diagram PHYINT Interrupt Control Interrupt TXCK Receive Control MACRIS MACIACK MACIM MACRCTL MACNP TXD[3:0] Transmit FIFO Data Access TXEN TXER COL CRS MACDDATA Transmit Control Timer Support MACTCTL MACTHR MACTSR Receive FIFO RXCK RXD[3:0] RXDV RXER MACTR MII Control MACMCTL MACMDV MACMTXD Individual Address MACMRXD MACIA0 MACIA1 17.2 MDC MDIO Signal Description The following table lists the external signals of the Ethernet MAC and describes the function of each. The MII and MAC Control signals are alternate functions for GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the MII and MAC Control signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the MII and MAC Control function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the MII and MAC Control signals to the specified GPIO port pins. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. Table 17-1. Signals for Ethernet (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description COL 17 PG2 (3) I TTL MII collision detect. CRS 16 PG3 (3) I TTL MII carrier sense. MDC 59 PF3 (3) O TTL MII management clock. MDIO 58 PF4 (3) I/O OD MDIO of the Ethernet PHY. PHYINT 60 PF2 (3) I TTL PHY interrupt. 828 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 17-1. Signals for Ethernet (100LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description RXCK 15 34 47 PH7 (3) PA6 (3) PF0 (4) I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. RXD0 6 41 PE4 (7) PG4 (3) I TTL MII receive data 0. RXD1 42 89 PF7 (3) PB7 (7) I TTL MII receive data 1. RXD2 43 PF6 (3) I TTL MII receive data 2. RXD3 46 PF5 (3) I TTL MII receive data 3. RXDV 10 31 62 PD0 (7) PA5 (3) PH6 (9) I TTL MII receive data valid. RXER 14 35 61 PJ0 (3) PA7 (3) PF1 (4) I TTL MII receive error. TXCK 37 PG6 (3) I TTL MII transmit clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. TXD0 30 63 100 PA4 (3) PH5 (9) PD7 (4) O TTL MII transmit data 0. TXD1 29 76 99 PA3 (3) PH4 (9) PD6 (4) O TTL Ethernet MII transmit data 1. TXD2 28 83 98 PA2 (3) PH3 (9) PD5 (4) O TTL MII transmit data 2. TXD3 25 84 97 PC4 (3) PH2 (9) PD4 (4) O TTL Ethernet MII transmit data 3. TXEN 40 PG5 (3) O TTL MII transmit enable. TXER 11 36 PD1 (7) PG7 (3) O TTL MII transmit error. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 17-2. Signals for Ethernet (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description COL J1 PG2 (3) I TTL MII collision detect. CRS J2 PG3 (3) I TTL MII carrier sense. MDC J12 PF3 (3) O TTL MII management clock. MDIO L9 PF4 (3) I/O OD MDIO of the Ethernet PHY. PHYINT J11 PF2 (3) I TTL PHY interrupt. RXCK H3 L6 M9 PH7 (3) PA6 (3) PF0 (4) I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. RXD0 B2 K3 PE4 (7) PG4 (3) I TTL MII receive data 0. July 22, 2011 829 Texas Instruments-Production Data Ethernet Controller Table 17-2. Signals for Ethernet (108BGA) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description RXD1 K4 A8 PF7 (3) PB7 (7) I TTL MII receive data 1. RXD2 M8 PF6 (3) I TTL MII receive data 2. RXD3 L8 PF5 (3) I TTL MII receive data 3. RXDV G1 M5 G3 PD0 (7) PA5 (3) PH6 (9) I TTL MII receive data valid. RXER F3 M6 H12 PJ0 (3) PA7 (3) PF1 (4) I TTL MII receive error. TXCK L7 PG6 (3) I TTL MII transmit clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. TXD0 L5 F10 A2 PA4 (3) PH5 (9) PD7 (4) O TTL MII transmit data 0. TXD1 L4 B10 A3 PA3 (3) PH4 (9) PD6 (4) O TTL Ethernet MII transmit data 1. TXD2 M4 D10 C6 PA2 (3) PH3 (9) PD5 (4) O TTL MII transmit data 2. TXD3 L1 D11 B5 PC4 (3) PH2 (9) PD4 (4) O TTL Ethernet MII transmit data 3. TXEN M7 PG5 (3) O TTL MII transmit enable. TXER G2 C10 PD1 (7) PG7 (3) O TTL MII transmit error. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 17.3 Functional Description The functional description of the Ethernet Controller is discussed in the following sections. 17.3.1 MAC Operation The following sections describe the operation of the MAC layer, including an overview of the Ethernet frame format, the MAC layer FIFOs, Ethernet transmission and reception options, packet timestamps, and LED indicators. 17.3.1.1 Ethernet Frame Format Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure 17-3 on page 830. Figure 17-3. Ethernet Frame Preamble 7 Bytes SFD Destination Address 1 Byte 6 Bytes Source Address Length/ Type Data FCS 6 Bytes 2 Bytes 46 - 1500 Bytes 4 Bytes 830 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller The seven fields of the frame are transmitted from left to right. The bits within the frame are transmitted from least to most significant bit. ■ Preamble The Preamble field is used to synchronize with the received frame’s timing. The preamble is 7 octets long. ■ Start Frame Delimiter (SFD) The SFD field follows the preamble pattern and indicates the start of the frame. Its value is 1010.1011b. ■ Destination Address (DA) This field specifies destination addresses for which the frame is intended. The LSB (bit 16 of DA oct 1 in the frame, see Table 17-3 on page 832) of the DA determines whether the address is an individual (0), or group/multicast (1) address. ■ Source Address (SA) The source address field identifies the station from which the frame was initiated. ■ Length/Type Field The meaning of this field depends on its numeric value. This field can be interpreted as length or type code. The maximum length of the data field is 1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates the number of MAC client data octets. If the value of this field is greater than or equal to 1536 decimal, then it encodes the type interpretation. The meaning of the Length/Type field when the value is between 1500 and 1536 decimal is unspecified by the IEEE 802.3 standard. However, the Ethernet MAC assumes type interpretation if the value of the Length/Type field is greater than 1500 decimal. The definition of the Type field is specified in the IEEE 802.3 standard. The first of the two octets in this field is most significant. ■ Data The data field is a sequence of octets that is at least 46 in length, up to 1500 in length. Full data transparency is provided so any values can appear in this field. A minimum frame size of 46 octets is required to meet the IEEE standard. If the frame size is too small, the Ethernet MAC automatically appends extra bits (a pad), thus the pad can have a size of 0 to 46 octets. Data padding can be disabled by clearing the PADEN bit in the Ethernet MAC Transmit Control (MACTCTL) register. For the Ethernet MAC, data sent/received can be larger than 1500 bytes without causing a Frame Too Long error. Instead, a FIFO overrun error is reported using the FOV bit in the Ethernet MAC Raw Interrupt Status (MACRIS) register when the frame received is too large to fit into the Ethernet MAC’s 2K RAM. ■ Frame Check Sequence (FCS) The frame check sequence carries the cyclic redundancy check (CRC) value. The CRC is computed over the destination address, source address, length/type, and data (including pad) fields using the CRC-32 algorithm. The Ethernet MAC computes the FCS value one nibble at a time. For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by clearing the CRC bit in the MACTCTL register. For received frames, this field is automatically July 22, 2011 831 Texas Instruments-Production Data Ethernet Controller checked. If the FCS does not pass, the frame is not placed in the RX FIFO, unless the FCS check is disabled by clearing the BADCRC bit in the MACRCTL register. 17.3.1.2 MAC Layer FIFOs The Ethernet MAC is capable of simultaneous transmission and reception. This feature is enabled by setting the DUPLEX bit in the MACTCTL register. For Ethernet frame transmission, a 2-KB transmit FIFO is provided that can be used to store a single frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to 1500 Bytes, the Ethernet MAC places no such limit. The full buffer can be used for a payload of up to 2032 bytes (as the first 16 bytes in the FIFO are reserved for destination address, source address and length/type information). For Ethernet frame reception, a 2-KB receive FIFO is provided that can be used to store multiple frames, up to a maximum of 31 frames. If a frame is received, and there is insufficient space in the RX FIFO, an overflow error is indicated using the FOV bit in the MACRIS register. For details regarding the TX and RX FIFO layout, refer to Table 17-3 on page 832. Please note the following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions. For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including the Length/Type bytes and the FCS bits. If FCS generation is disabled by clearing the CRC bit in the MACTCTL register, the last word in the TX FIFO must contain the FCS bytes for the frame that has been written to the FIFO. Also note that if the length of the data payload section is not a multiple of 4, the FCS field is not aligned on a word boundary in the FIFO. However, for the RX FIFO, the beginning of the next frame is always on a word boundary. Table 17-3. TX & RX FIFO Organization FIFO Word Read/Write Sequence 1st 2nd 3rd 4th Word Bit Fields TX FIFO (Write) 7:0 Data Length Least Significant Frame Length Least Byte Significant Byte 15:8 Data Length Most Significant Frame Length Most Significant Byte Byte 23:16 DA oct 1 31:24 DA oct 2 7:0 DA oct 3 15:8 DA oct 4 23:16 DA oct 5 31:24 DA oct 6 7:0 SA oct 1 15:8 SA oct 2 23:16 SA oct 3 31:24 SA oct 4 7:0 SA oct 5 15:8 SA oct 6 23:16 Len/Type Most Significant Byte 31:24 Len/Type Least Significant Byte 832 RX FIFO (Read) July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 17-3. TX & RX FIFO Organization (continued) FIFO Word Read/Write Sequence 5th to nth last Word Bit Fields TX FIFO (Write) RX FIFO (Read) 7:0 data oct n 15:8 data oct n+1 23:16 data oct n+2 31:24 data oct n+3 a 7:0 FCS 1 15:8 FCS 2 23:16 FCS 3 31:24 FCS 4 a a a a. If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the correct CRC. If the CRC bit is set, the Ethernet MAC automatically writes the FCS bytes. 17.3.1.3 Ethernet Transmission Options At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation by using the DUPLEX bit in the MACTCTL register. Note that in 10BASE-T half-duplex mode, the transmitted data is looped back on the receive path. The Ethernet MAC automatically generates and inserts the Frame Check Sequence (FCS) at the end of the transmit frame when the CRC bit in the MACTCTL register is set. However, for test purposes, this feature can be disabled in order to generate a frame with an invalid CRC by clearing the CRC bit. The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46 bytes. The Ethernet MAC automatically pads the data section if the payload data section loaded into the FIFO is less than the minimum 46 bytes when the PADEN bit in the MACTCTL register is set. This feature can be disabled by clearing the PADEN bit. The transmitter must be enabled by setting the TXEN bit in the MACTCTL register. 17.3.1.4 Ethernet Reception Options The Ethernet MAC RX FIFO should be cleared during software initialization. The receiver should first be disabled by clearing the RXEN bit in the Ethernet MAC Receive Control (MACRCTL) register, then the FIFO can be cleared by setting the RSTFIFO bit in the MACRCTL register. The receiver automatically rejects frames that contain bad CRC values in the FCS field. In this case, a Receive Error interrupt is generated and the receive data is lost. To accept all frames, clear the BADCRC bit in the MACRCTL register. In normal operating mode, the receiver accepts only those frames that have a destination address that matches the address programmed into the Ethernet MAC Individual Address 0 (MACIA0) and Ethernet MAC Individual Address 1 (MACIA1) registers. However, the Ethernet receiver can also be configured for Promiscuous and Multicast modes by setting the PRMS and AMUL bits in the MACRCTL register. 17.3.1.5 Packet Timestamps Some applications require a very precise clock for time stamping samples or triggering events. The IEEE Precision Time Protocol (PTP), or IEEE-1588, provides a mechanism for synchronizing clocks across an Ethernet to sub-microsecond precision. The accuracy of the PTP clock depends greatly upon the accuracy of timestamps of the PTP Ethernet packets. In a software-only PTP solution, July 22, 2011 833 Texas Instruments-Production Data Ethernet Controller there can be jitter in the Ethernet packet timestamps, resulting in a less precise PTP clock on the target. In some Stellaris devices, General-Purpose Timer 3 (GPT3) can be used in conjunction with the Ethernet MAC Timer Support (MACTS) register to provide a more accurate timestamp for Ethernet packets. This feature is enabled by setting the TSEN bit in the MACTS register. Note that when this feature is enabled, GPT3 must be dedicated to the Ethernet MAC. GPT3 must be configured to 16-bit edge capture mode, see page 466. Timer A of GPT3 stores the transmit time, and Timer B stores the receive time. One other General-Purpose Timer can be set up as a 16-bit free-running timer to synchronize the receiver and transmitter timers and provide a timestamp with which to compare the ® timestamps stored in GPT3. The enet_ptpd example in the StellarisWare software package provides a sample PTP application that illustrates both software-only time stamping as well the use of the GPT3 and MACTS register for more accurate timestamps. This example supports version 1 of the IEEE-1588 protocol, but Stellaris microcontrollers support both versions 1 and 2. 17.3.2 Media Independent Interface The Media Independent Interface (MII) is used for communication between the MAC layer and the off-chip PHY layer. The MII can accommodate up to 32 external PHYs and can communicate at either 10 Mb/s or 100 Mb/s. The functionality is identical at both data rates, as are the signal timing relationships. The only difference between the two data rates is the nominal clock frequency. An external PHY may support only one data rate or both. The signals in this standard interface can be broken down into three groups: ■ Receive signals ■ Transmit signals ■ Control signals 17.3.2.1 Receive Interface The receive clock, RXCK, is a continuous clock that provides a timing reference for the receive data transfer. RXCK is sourced by the PHY and should be 25% of the nominal receive data rate. For 100BASE-T, RXCK should be 25 MHz; for 10BASE-T, RXCK should be 2.5 MHz. Data is received from the PHY using 4 data signals, RXD[3:0], which are driven synchronously from the PHY. RXD0 is the LSB and RXD3 is the MSB. Data from the PHY is valid when the data valid signal, RXDV, is asserted. RXDV must be asserted with the first recovered nibbled of the frame and stay asserted through the final recovered nibble. RXDV should be negated prior to the first RXCK that follows the final nibble. If the PHY detects an error in the frame, the RXER input should be asserted for at least one clock period. Table 17-4. Receive Signal Encoding RXDV RXER RXD[3:0] Decscription 0 0 0x0 - 0xF Normal inter-frame 0 1 0x0 Normal inter-frame 0 1 0x1 - 0xD 0 1 0xE False carrier indication 0 1 0xF Reserved 1 0 0x0 - 0xF Normal data reception 1 1 0x0 - 0xF Error during data reception Reserved 834 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 17.3.2.2 Transmit Interface The transmit clock, TXCK, is a continuous clock that provides a timing reference for the transmit data transfer. TXCK is sourced by the PHY and should be 25% of the nominal transmit data rate. For 100BASE-T, TXCK should be 25 MHz; for 10BASE-T, TXCK should be 2.5 MHz. Data is transmitted from the PHY using 4 data signals, TXD[3:0], which are driven synchronously from the MAC. TXD0 is the LSB and TXD3 is the MSB. Data from the MAC is valid when the transmission enable signal, TXEN, is asserted. TXEN is asserted with the first nibble of the preamble and stays asserted through the last nibble to be transmitted. TXEN is negated prior to the first TXCK following the final nibble of the frame. If the MAC detects an error in the frame, the TXER input is asserted for at least one clock period. Table 17-5. Transmit Signal Encoding 17.3.2.3 Decscription TXEN TXER TXD[3:0] 0 0 0x0 - 0xF Normal inter-frame 0 1 0x0 - 0xF Reserved 1 0 0x0 - 0xF Normal data transmission 1 1 0x0 - 0xF Transmit error propagation Control Signals The MII control signals consist of two subsets of signals: ■ Serial Management Interface (SMI) which is used to access the external PHY registers ■ Signals that provide information concerning the status of the PHY Station Management A simple serial interface is used for controlling the PHY and gathering status from the PHY. The station management interface consists of signals that transport the management information across the MII, a frame format and a protocol specification for exchanging management frames, and a register set that can be read and written using these frames. The serial signals consist of the Management Data Clock (MDC) signal and the Management Data Input/Output (MDIO) signal. The MDC signal is a period clock which provides the timing reference for the transfer occurring on the MDIO signal. The clock divider for the MDC signal is set in the Ethernet MAC Managment Divider (MACMDV) register. The maximum frequency of the MDC signal is 2.5 MHz. Software can select one of up to 32 PHYs and one of up to 32 registers within any PHY and send control data or receive status information. Only one register in one PHY can be accessed at any given time. PHY accesses are configured as follows: 1. Program the clock divider for the MDC signal in the MACMDV register. 2. If the system has multiple PHYs, program the address of the PHY in the Ethernet MAC Address (MACMADD) register. PHYs can be numbered 0 to 31. 3. If data is to be written to the PHY, store the data in the Ethernet MAC Management Transmit Data (MACMTXD) register. July 22, 2011 835 Texas Instruments-Production Data Ethernet Controller 4. In the Ethernet MAC Management Control (MACMCTL) register, program the address identifier for the specific PHY register, 0 to 31. Also, configure the WRITE bit appropriately for the transaction whether it is a read or a write and set the START bit in the MACMCTL register. 5. If data was read from the PHY, read the data from the Ethernet MAC Management Receive Data (MACMRXD) register. The station management frame format is different from the regular Ethernet frame format as shown in Figure 17-4. Figure 17-4. Management Frame Format PRE 32 bits ST OP PHYAD REGAD TA DATA 2 2 bits bits 16 bits 5 bits 5 bits 2 bits IDLE The seven fields of the frame are transmitted from left to right. The bits within the frame are transmitted from least to most significant bit. ■ Preamble (PRE) At the beginning of each transaction, the MAC sends 32 contiguous logic one bits on MDIO with 32 corresponding cycles of the MDC clock signal. The Preamble is sent at the beginning of every transmission. ■ Start (ST) Start of frame is indicated by 01b. ■ Operation code (OP) The operation code defines the transaction type. This field is 10b for read and 01b for write. ■ PHY address (PHYAD) The PHY address is transmitted MSB first. ■ MII register address (REGAD) The MII register address is transmitted MSB first. ■ Turnaround (TA) The turnaround time is 2 bit time spacing between the REGAD field and the DATA field of a management frame to avoid contention during a read transaction. For a read transaction, both the MAC and PHY remain in a high-impedance state for the first bit time. During the second bit time, the PHY drives MDIO low. During a write transaction, the MAC drives MDIO high for the first bit time and low for the second bit time. ■ Data (DATA) The data field is 16 bits and is transmitted and received MSB first. ■ Idle (IDLE) 836 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Between frames, the MDIO signal is in a high-impedance state. All three-state drivers must be disabled and a pull-up resistor should be attached to the MDIO signal. PHY Status Signals The carrier sense (CRS) signal is asserted by the external PHY when either the transmit or receive interface is not idle. The PHY negates the signal when both the transmit and receive interfaces are idle. CRS is not synchronous to either TXCK or RXCK. If a collision is detected, the CRS signal remains asserted throughout the duration of the collision condition. This signal is not used in full duplex mode. The collision (COL) signal is asserted by the PHY when a collision is detected on either the transmit or receive interface and remains asserted while the collision condition persists. COL is not synchronous to either TXCK or RXCK. This signal is not used in full duplex mode. The PHYINT signal can be asserted by the PHY layer to indicate to the MAC layer that one of the PHY interrupt sources is active. The PHYINT signal must be asserted for at least 2 system clock periods in order to be recognized as asserted by the microcontroller, at which time the PHYINT bit in the MACRIS register is set. The PHYINT signal is not part of the IEEE 802.3 standard, and its implementation is optional. 17.3.3 Interrupts The Ethernet MAC can generate an interrupt for one or more of the following conditions: ■ A frame has been received into an empty RX FIFO ■ A frame transmission error has occurred ■ A frame has been transmitted successfully ■ A frame has been received with inadequate room in the RX FIFO (overrun) ■ A frame has been received with one or more error conditions (for example, FCS failed) ■ An MII management transaction between the MAC and PHY layers has completed ■ The external PHY has signalled an interrupt 17.3.4 DMA Operation The Ethernet peripheral provides request signals to the μDMA controller and has a dedicated channel for transmit and one for receive. The request is a single type for both channels. Burst requests are not supported. The RX channel request is asserted when a packet is received while the TX channel request is asserted when the transmit FIFO becomes empty. No special configuration is needed to enable the Ethernet peripheral for use with the μDMA controller. Because the size of a received packet is not known until the header is examined, it is best to set up the initial μDMA transfer to copy the first 4 words including the packet length plus the Ethernet header from the RX FIFO when the RX request occurs. The μDMA causes an interrupt when this transfer is complete. Upon entering the interrupt handler, the packet length in the FIFO and the Ethernet header are in a buffer and can be examined. Once the packet length is known, then another μDMA transfer can be set up to transfer the remaining received packet payload from the FIFO into a buffer. This transfer should be initiated by software. Another interrupt occurs when this transfer is done. July 22, 2011 837 Texas Instruments-Production Data Ethernet Controller Even though the TX channel generates a TX empty request, the recommended way to handle μDMA transfers for transmitting packets is to set up the transfer from the buffer containing the packet to the transmit FIFO, and then to initiate the transfer with a software request. An interrupt occurs when this transfer is complete. For both channels, the "auto-request" transfer mode should be used. See “Micro Direct Memory Access (μDMA)” on page 333 for more details about programming the µDMA controller. 17.4 Initialization and Configuration The following sections describe the software configuration required to set up the Ethernet MAC. 17.4.1 Software Configuration To use the Ethernet MAC, it must be enabled by setting the EMAC0 bit in the RCGC2 register (see page 281). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2 register in the System Control module. See page 281. To find out which GPIO port to enable, refer to Table 23-4 on page 1137. Configure the PMCn fields in the GPIOPCTL register to assign the Ethernet signals to the appropriate pins. See page 434 and Table 23-5 on page 1145. The following steps can then be used to configure the Ethernet MAC for basic operation. 1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the MII. Assuming a 20-MHz system clock, the MACDIV value should be 0x03 or greater. 2. The external PHY should be initialized; steps may vary depending upon the PHY used. 3. Program the MACIA0 and MACIA1 register for address filtering. 4. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation using a value of 0x16. 5. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using a value of 0x18. 6. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and MACRCTL registers. 7. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA) register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available for the next transmit frame. 8. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP) register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet() API or compare the number of bytes received to the Length field from the frame to determine when the packet has been completely read. 17.5 Register Map Table 17-6 on page 839 lists the Ethernet MAC registers. The MAC register addresses given are relative to the Ethernet base address of 0x4004.8000. Note that the Ethernet MAC clock must be enabled before the registers can be programmed (see page 281). There must be a delay of 3 system clocks after the Ethernet module clock is enabled before any Ethernet module registers are accessed. 838 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer. The registers are collectively known as the MII Management registers and are detailed in Section 22.2.4 of the IEEE 802.3 specification. The Ethernet MAC Management Control (MACMCTL) register is used to access MII Management registers on the external PHY device. The format of registers 0 to 15 are defined by the IEEE specification and are common to all PHY layer implementations. The only variance allowed is for features that may or may not be supported by a specific PHY implementation. Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a vendor's PHY implementation. Vendor-specific registers not listed are reserved. Table 17-6. Ethernet Register Map Offset Name 0x000 MACRIS/MACIACK 0x004 Reset R/W1C 0x0000.0000 Ethernet MAC Raw Interrupt Status/Acknowledge 840 MACIM R/W 0x0000.007F Ethernet MAC Interrupt Mask 843 0x008 MACRCTL R/W 0x0000.0008 Ethernet MAC Receive Control 845 0x00C MACTCTL R/W 0x0000.0000 Ethernet MAC Transmit Control 847 0x010 MACDATA R/W 0x0000.0000 Ethernet MAC Data 849 0x014 MACIA0 R/W 0x0000.0000 Ethernet MAC Individual Address 0 851 0x018 MACIA1 R/W 0x0000.0000 Ethernet MAC Individual Address 1 852 0x01C MACTHR R/W 0x0000.003F Ethernet MAC Threshold 853 0x020 MACMCTL R/W 0x0000.0000 Ethernet MAC Management Control 855 0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 856 0x028 MACMADD RO 0x0000.0000 Ethernet MAC Management Address 857 0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 858 0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 859 0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 860 0x038 MACTR R/W 0x0000.0000 Ethernet MAC Transmission Request 861 0x03C MACTS R/W 0x0000.0000 Ethernet MAC Timer Support 862 17.6 Description See page Type Ethernet MAC Register Descriptions The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by address offset. July 22, 2011 839 Texas Instruments-Production Data Ethernet Controller Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this register gives the current status value of the corresponding interrupt prior to masking. On a write, setting any bit clears the corresponding interrupt status bit. Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Base 0x4004.8000 Offset 0x000 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 15 14 13 12 RO 0 RO 0 RO 0 RO 0 RO 0 11 10 9 8 7 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 PHYINT MDINT RXER FOV TXEMP TXER RXINT R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 RO 0 Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PHYINT R/W1C 0 PHY Interrupt Value Description 1 An enabled interrupt in the PHY layer has occurred. Refer the PHY register descriptions to determine the specific PHY event that triggered this interrupt. 0 No interrupt. This bit is cleared by writing a 1 to it. 5 MDINT R/W1C 0 MII Transaction Complete Value Description 1 A transaction (read or write) on the MII interface has completed successfully. 0 No interrupt. This bit is cleared by writing a 1 to it. 840 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 4 RXER R/W1C 0 Description Receive Error Value Description 1 0 An error was encountered on the receiver. The possible errors that can cause this interrupt bit to be set are: ■ A receive error occurs during the reception of a frame (100 Mbps only). ■ The frame is not an integer number of bytes (dribble bits) due to an alignment error. ■ The CRC of the frame does not pass the FCS check. ■ The length/type field is inconsistent with the frame data size when interpreted as a length field. No interrupt. This bit is cleared by writing a 1 to it. 3 FOV R/W1C 0 FIFO Overrun Value Description 1 An overrun was encountered on the receive FIFO. 0 No interrupt. This bit is cleared by writing a 1 to it. 2 TXEMP R/W1C 0 Transmit FIFO Empty Value Description 1 The packet was transmitted and that the TX FIFO is empty. 0 No interrupt. This bit is cleared by writing a 1 to it. 1 TXER R/W1C 0 Transmit Error Value Description 1 0 An error was encountered on the transmitter. The possible errors that can cause this interrupt bit to be set are: ■ The data length field stored in the TX FIFO exceeds 2032 decimal (buffer length - 16 bytes of header data). The frame is not sent when this error occurs. ■ The retransmission attempts during the backoff process have exceeded the maximum limit of 16 decimal. No interrupt. Writing a 1 to this bit clears it and resets the TX FIFO write pointer. July 22, 2011 841 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 0 RXINT R/W1C 0 Description Packet Received Value Description 1 At least one packet has been received and is stored in the receiver FIFO. 0 No interrupt. This bit is cleared by writing a 1 to it. 842 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the interrupt, while setting the bit enables it. Ethernet MAC Interrupt Mask (MACIM) Base 0x4004.8000 Offset 0x004 Type R/W, reset 0x0000.007F 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RXERM FOVM TXEMPM TXERM RXINTM RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 reserved Type Reset reserved Type Reset PHYINTM MDINTM RO 0 R/W 1 R/W 1 Bit/Field Name Type Reset Description 31:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 PHYINTM R/W 1 Mask PHY Interrupt Value Description 5 MDINTM R/W 1 1 An interrupt is sent to the interrupt controller when the PHYINT bit in the MACRIS/MACIACK register is set. 0 The PHYINT interrupt is suppressed and not sent to the interrupt controller. Mask MII Transaction Complete Value Description 4 RXERM R/W 1 1 An interrupt is sent to the interrupt controller when the MDINT bit in the MACRIS/MACIACK register is set. 0 The MDINT interrupt is suppressed and not sent to the interrupt controller. Mask Receive Error Value Description 1 An interrupt is sent to the interrupt controller when the RXER bit in the MACRIS/MACIACK register is set. 0 The RXER interrupt is suppressed and not sent to the interrupt controller. July 22, 2011 843 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 3 FOVM R/W 1 Description Mask FIFO Overrun Value Description 2 TXEMPM R/W 1 1 An interrupt is sent to the interrupt controller when the FOV bit in the MACRIS/MACIACK register is set. 0 The FOV interrupt is suppressed and not sent to the interrupt controller. Mask Transmit FIFO Empty Value Description 1 TXERM R/W 1 1 An interrupt is sent to the interrupt controller when the TXEMP bit in the MACRIS/MACIACK register is set. 0 The TXEMP interrupt is suppressed and not sent to the interrupt controller. Mask Transmit Error Value Description 0 RXINTM R/W 1 1 An interrupt is sent to the interrupt controller when the TXER bit in the MACRIS/MACIACK register is set. 0 The TXER interrupt is suppressed and not sent to the interrupt controller. Mask Packet Received Value Description 1 An interrupt is sent to the interrupt controller when the RXINT bit in the MACRIS/MACIACK register is set. 0 The RXINT interrupt is suppressed and not sent to the interrupt controller. 844 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 This register configures the receiver and controls the types of frames that are received. It is important to note that when the receiver is enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address field are received and stored in the RX FIFO, even if the AMUL bit is not set. Ethernet MAC Receive Control (MACRCTL) Base 0x4004.8000 Offset 0x008 Type R/W, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 9 8 7 6 5 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RSTFIFO BADCRC RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.000 4 RSTFIFO R/W 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 2 1 0 PRMS AMUL RXEN R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clear Receive FIFO Value Description 1 Clear the receive FIFO. The receive FIFO should be cleared when software initialization is performed. 0 No effect. This bit is automatically cleared when read. The receiver should be disabled (RXEN = 0), before a reset is initiated (RSTFIFO = 1). This sequence flushes and resets the RX FIFO. 3 BADCRC R/W 1 Enable Reject Bad CRC Value Description 2 PRMS R/W 0 1 Enables the rejection of frames with an incorrectly calculated CRC. If a bad CRC is encountered, the RXER bit in the MACRIS register is set and the receiver FIFO is reset. 0 Disables the rejection of frames with an incorrectly calculated CRC. Enable Promiscuous Mode Value Description 1 Enables Promiscuous mode, which accepts all valid frames, regardless of the specified Destination Address. 0 Disables Promiscuous mode, accepting only frames with the programmed Destination Address. July 22, 2011 845 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 1 AMUL R/W 0 Description Enable Multicast Frames Value Description 0 RXEN R/W 0 1 Enables the reception of multicast frames. 0 Disables the reception of multicast frames. Enable Receiver Value Description 1 Enables the Ethernet receiver. 0 Disables the receiver. All frames are ignored. 846 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C This register configures the transmitter and controls the frames that are transmitted. Ethernet MAC Transmit Control (MACTCTL) Base 0x4004.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 DUPLEX reserved CRC PADEN TXEN RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:5 reserved RO 0x0000.000 4 DUPLEX R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable Duplex Mode Value Description 1 Enables Duplex mode, allowing simultaneous transmission and reception. 0 Disables Duplex mode. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 CRC R/W 0 Enable CRC Generation Value Description 1 Enables the automatic generation of the CRC and its placement at the end of the packet. 0 The frames placed in the TX FIFO are sent exactly as they are written into the FIFO. Note that this bit should generally be set. 1 PADEN R/W 0 Enable Packet Padding Value Description 1 Enables the automatic padding of packets that do not meet the minimum frame size. 0 Disables automatic padding. Note that this bit should generally be set. July 22, 2011 847 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset 0 TXEN R/W 0 Description Enable Transmitter Value Description 1 Enables the transmitter. 0 Disables the transmitter. 848 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 5: Ethernet MAC Data (MACDATA), offset 0x010 Important: This register is read-sensitive. See the register description for details. This register enables software to access the TX and RX FIFOs. Reads from this register return the data stored in the RX FIFO from the location indicated by the read pointer. The read pointer is then auto incremented to the next RX FIFO location. Reading from the RX FIFO when a frame has not been received or is in the process of being received returns indeterminate data and does not increment the read pointer. Writes to this register store the data in the TX FIFO at the location indicated by the write pointer. The write pointer is then auto incremented to the next TX FIFO location. Writing more data into the TX FIFO than indicated in the length field results in the data being lost. Writing less data into the TX FIFO than indicated in the length field results in indeterminate data being appended to the end of the frame to achieve the indicated length. Attempting to write the next frame into the TX FIFO before transmission of the first has completed results in the data being lost. Bytes may not be randomly accessed in either the RX or TX FIFOs. Data must be read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data re-written. Reads Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RXDATA Type Reset RXDATA Type Reset Bit/Field Name Type 31:0 RXDATA RO Reset Description 0x0000.0000 Receive FIFO Data The RXDATA bits represent the next word of data stored in the RX FIFO. July 22, 2011 849 Texas Instruments-Production Data Ethernet Controller Writes Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 15 14 13 12 11 10 9 8 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 23 22 21 20 19 18 17 16 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 6 5 4 3 2 1 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 TXDATA Type Reset TXDATA Type Reset Bit/Field Name Type 31:0 TXDATA WO Reset Description 0x0000.0000 Transmit FIFO Data The TXDATA bits represent the next word of data to place in the TX FIFO for transmission. 850 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 This register enables software to program the first four bytes of the hardware MAC address of the Network Interface Card (NIC). The last two bytes are in MACIA1. The 6-byte Individual Address is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 0 (MACIA0) Base 0x4004.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 R/W 0 R/W 0 R/W 0 R/W 0 27 26 25 24 23 22 21 20 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 11 10 9 8 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MACOCT4 Type Reset 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 MACOCT3 MACOCT2 Type Reset 19 MACOCT1 R/W 0 Bit/Field Name Type Reset Description 31:24 MACOCT4 R/W 0x00 MAC Address Octet 4 R/W 0 The MACOCT4 bits represent the fourth octet of the MAC address used to uniquely identify the Ethernet MAC. 23:16 MACOCT3 R/W 0x00 MAC Address Octet 3 The MACOCT3 bits represent the third octet of the MAC address used to uniquely identify the Ethernet MAC. 15:8 MACOCT2 R/W 0x00 MAC Address Octet 2 The MACOCT2 bits represent the second octet of the MAC address used to uniquely identify the Ethernet MAC. 7:0 MACOCT1 R/W 0x00 MAC Address Octet 1 The MACOCT1 bits represent the first octet of the MAC address used to uniquely identify the Ethernet MAC. July 22, 2011 851 Texas Instruments-Production Data Ethernet Controller Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 This register enables software to program the last two bytes of the hardware MAC address of the Network Interface Card (NIC). The first four bytes are in MACIA0. The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 1 (MACIA1) Base 0x4004.8000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset MACOCT6 Type Reset MACOCT5 R/W 0 Bit/Field Name Type Reset 31:16 reserved RO 0x0000 15:8 MACOCT6 R/W 0x00 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC Address Octet 6 The MACOCT6 bits represent the sixth octet of the MAC address used to uniquely identify each Ethernet MAC. 7:0 MACOCT5 R/W 0x00 MAC Address Octet 5 The MACOCT5 bits represent the fifth octet of the MAC address used to uniquely identify the Ethernet MAC. 852 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C In order to increase the transmission rate, it is possible to program the Ethernet MAC to begin transmission of the next frame prior to the completion of the transmission of the current frame. Caution – Extreme care must be used when implementing this function. Software must be able to guarantee that the complete frame is able to be stored in the transmission FIFO prior to the completion of the transmission frame. This register enables software to set the threshold level at which the transmission of the frame begins. If the THRESH bits are set to 0x3F, which is the reset value, the early transmission feature is disabled, and transmission does not start until the NEWTX bit is set in the MACTR register. Writing the THRESH field to any value besides 0x3F enables the early transmission feature. Once the byte count of data in the TX FIFO reaches the value derived from the THRESH bits as shown below, transmission of the frame begins. When the THRESH field is clear, transmission of the frame begins after 4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore, a value of 0x01 causes the transmitter to wait for 36 bytes of data to be written while a value of 0x02 makes the wait equal to 68 bytes of written data. In general, early transmission starts when: Number of Bytes ≥ 4 ((THRESH x 8) + 1) Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register. Transmission of the frame begins, and then the number of bytes indicated by the Data Length field is transmitted. Because underrun checking is not performed, if any event, such as an interrupt, delays the filling of the FIFO, the tail pointer may reach and pass the write pointer in the TX FIFO. In this event, indeterminate values are transmitted rather than the end of the frame. Therefore, sufficient bus bandwidth for writing to the TX FIFO must be guaranteed by the software. If a frame smaller than the threshold level must be sent, the NEWTX bit in the MACTR register must be set with an explicit write, which initiates the transmission of the frame even though the threshold limit has not been reached. If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the transmit frame is aborted, and a transmit error occurs. Note that in this case, the TXER bit in the MACRIS is not set, meaning that the CPU receives no indication that a transmit error happened. Ethernet MAC Threshold (MACTHR) Base 0x4004.8000 Offset 0x01C Type R/W, reset 0x0000.003F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 THRESH RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 853 Texas Instruments-Production Data Ethernet Controller Bit/Field Name Type Reset Description 5:0 THRESH R/W 0x3F Threshold Value The THRESH bits represent the early transmit threshold. Once the amount of data in the TX FIFO exceeds the value represented by the above equation, transmission of the packet begins. 854 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 This register enables software to control the transfer of data to and from the MII Management registers in the Ethernet PHY layer. See the documentation for the external PHY device for the MII register address and functional description. In order to initiate a read transaction from the MII Management registers, the WRITE bit must be cleared during the same cycle that the START bit is set. In order to initiate a write transaction to the MII Management registers, the WRITE bit must be set during the same cycle that the START bit is set. Ethernet MAC Management Control (MACMCTL) Base 0x4004.8000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 reserved WRITE START RO 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset REGADR RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:3 REGADR R/W 0x0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MII Register Address The REGADR bit field represents the MII Management register address for the next MII management interface transaction. Refer to the external PHY documentation for the PHY register offsets. 2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 WRITE R/W 0 MII Register Transaction Type Value Description 0 START R/W 0 1 The next operation of the next MII management interface is a write transaction. 0 The next operation of the next MII management interface is a read transaction. MII Register Transaction Enable Value Description 1 The MII register located at REGADR is read (WRITE=0) or written (WRITE=1). 0 No effect. July 22, 2011 855 Texas Instruments-Production Data Ethernet Controller Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 This register enables software to set the clock divider for the Management Data Clock (MDC). This clock is used to synchronize read and write transactions on the SMI. The frequency of the MDC clock can be calculated from the following formula: Fmdc = Fipclk 2 × (MACMDV + 1) The clock divider must be written with a value that ensures that the MDC clock does not exceed a frequency of 2.5 MHz. Ethernet MAC Management Divider (MACMDV) Base 0x4004.8000 Offset 0x024 Type R/W, reset 0x0000.0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 DIV RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7:0 DIV R/W 0x80 RO 0 R/W 1 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Divider The DIV bits are used to set the clock divider for the MDC clock signal used to transmit data between the MAC and PHY layers over the serial management interface. 856 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 11: Ethernet MAC Management Address (MACMADD), offset 0x028 This register enables software to choose the address of the PHY for the next MII Management register transaction. Ethernet MAC Management Address (MACMADD) Base 0x4004.8000 Offset 0x028 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 PHYADR Bit/Field Name Type Reset 31:5 reserved RO 0x0000.000 4:0 PHYADR R/W 0x0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PHY Address The PHYADR bits represent the address of the PHY that is accessed in the next SMI management transaction. July 22, 2011 857 Texas Instruments-Production Data Ethernet Controller Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C This register holds the next value to be written to the MII Management registers. Ethernet MAC Management Transmit Data (MACMTXD) Base 0x4004.8000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 MDTX Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MDTX R/W 0x0000 MII Register Transmit Data The MDTX bits represent the data to be written in the next MII management transaction. 858 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 This register holds the last value read from the MII Management registers. Ethernet MAC Management Receive Data (MACMRXD) Base 0x4004.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 MDRX Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MDRX R/W 0x0000 MII Register Receive Data The MDRX bits represent the data that was read in the previous MII management transaction. July 22, 2011 859 Texas Instruments-Production Data Ethernet Controller Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there are no frames in the RX FIFO, and the RXINT bit is clear. When NPR is any other value, at least one frame is in the RX FIFO, and the RXINT bit in the MACRIS register is set. Note: The FCS bytes are not included in the NPR value. As a result, the NPR value could be zero before the FCS bytes are read from the FIFO. In addition, a new packet could be received before the NPR value reaches zero. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet() API or compare the number of bytes received to the Length field from the frame to determine when the packet has been completely read. Ethernet MAC Number of Packets (MACNP) Base 0x4004.8000 Offset 0x034 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 NPR RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5:0 NPR RO 0x00 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Number of Packets in Receive FIFO The NPR bits represent the number of packets stored in the RX FIFO. While the NPR field is greater than 0, the RXINT interrupt in the MACRIS register is set. 860 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 This register enables software to initiate the transmission of the frame currently located in the TX FIFO. Once the frame has been transmitted from the TX FIFO or a transmission error has been encountered, the NEWTX bit is automatically cleared. Ethernet MAC Transmission Request (MACTR) Base 0x4004.8000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 NEWTX R/W 0 RO 0 NEWTX R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. New Transmission Value Description 1 Initiates an Ethernet transmission once the packet has been placed in the TX FIFO. 0 The transmission has completed. If early transmission is being used (see the MACTHR register), this bit does not need to be set. July 22, 2011 861 Texas Instruments-Production Data Ethernet Controller Register 16: Ethernet MAC Timer Support (MACTS), offset 0x03C This register enables software to enable highly precise timing on the transmission and reception of frames. To enable this function, set the TSEN bit. Ethernet MAC Timer Support (MACTS) Base 0x4004.8000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 TSEN R/W 0 RO 0 TSEN R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Time Stamp Enable Value Description 1 The TX and RX interrupts are routed to the CCP inputs of General-Purpose Timer 3. 0 No effect. 862 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 18 Universal Serial Bus (USB) Controller ® The Stellaris USB controller operates as a full-speed or low-speed function controller during point-to-point communications with USB Host, Device, or OTG functions. The controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. 32 endpoints including two hard-wired for control transfers (one endpoint for IN and one endpoint for OUT) plus 30 endpoints defined by firmware along with a dynamic sizable FIFO support multiple packet queueing. µDMA access to the FIFO allows minimal interference from system software. Software-controlled connect and disconnect allows flexibility during USB device start-up. The controller complies with OTG standard's session request protocol (SRP) and host negotiation protocol (HNP). The Stellaris USB module has the following features: ■ Complies with USB-IF certification standards ■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation with integrated PHY ■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous ■ 32 endpoints – 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint – 15 configurable IN endpoints and 15 configurable OUT endpoints ■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size ■ VBUS droop and valid ID detection and interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints – Channel requests asserted when FIFO contains required amount of data July 22, 2011 863 Texas Instruments-Production Data Universal Serial Bus (USB) Controller 18.1 Block Diagram Figure 18-1. USB Module Block Diagram DMA Requests Endpoint Control Transmit EP0 – 31 Control Receive CPU Interface Combine Endpoints Host Transaction Scheduler Interrupt Control Interrupts EP Reg. Decoder UTM Synchronization Packet Encode/Decode Data Sync Packet Encode USB PHY USB FS/LS PHY HNP/SRP Packet Decode Timers CRC Gen/Check FIFO RAM Controller Rx Rx Buff Buff Tx Buff Common Regs AHB bus – Slave mode Cycle Control Tx Buff Cycle Control FIFO Decoder USB Data Lines D+ and D- 18.2 Signal Description The following table lists the external signals of the USB controller and describes the function of each. Some USB controller signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these USB signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the USB function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the USB signal to the specified GPIO port pin. The USB0VBUS and USB0ID signals are configured by clearing the appropriate DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. The remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment and function. Note: When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they are dedicated pins for the USB controller and directly connect to the USB connector's VBUS and ID signals. If the USB controller is used as either a dedicated Host or Device, the DEVMODOTG and DEVMOD bits in the USB General-Purpose Control and Status (USBGPCS) register can be used to connect the USB0VBUS and USB0ID inputs to fixed levels internally, freeing the PB0 and PB1 pins for GPIO use. For proper self-powered Device operation, the VBUS value must still be monitored to assure that if the Host removes VBUS, the self-powered Device disables the D+/D- pull-up resistors. This function can be accomplished by connecting a standard GPIO to VBUS. Table 18-1. Signals for USB (100LQFP) Pin Name USB0DM Pin Number Pin Mux / Pin Assignment 70 fixed a Pin Type Buffer Type I/O Analog Description Bidirectional differential data pin (D- per USB specification) for USB0. 864 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 18-1. Signals for USB (100LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description USB0DP 71 fixed I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. USB0EPEN 19 24 34 72 83 PG0 (7) PC5 (6) PA6 (8) PB2 (8) PH3 (4) O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0ID 66 PB0 I Analog This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side). USB0PFLT 22 23 35 65 74 76 87 PC7 (6) PC6 (7) PA7 (8) PB3 (8) PE0 (9) PH4 (4) PJ1 (9) I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. USB0RBIAS 73 fixed O Analog 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. USB0VBUS 67 PB1 I/O Analog This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 18-2. Signals for USB (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description USB0DM C11 fixed I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP C12 fixed I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. USB0EPEN K1 M1 L6 A11 D10 PG0 (7) PC5 (6) PA6 (8) PB2 (8) PH3 (4) O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0ID E12 PB0 I Analog This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side). USB0PFLT L2 M2 M6 E11 B11 B10 B6 PC7 (6) PC6 (7) PA7 (8) PB3 (8) PE0 (9) PH4 (4) PJ1 (9) I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. July 22, 2011 865 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Table 18-2. Signals for USB (108BGA) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description USB0RBIAS B12 fixed O Analog 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. USB0VBUS D12 PB1 I/O Analog This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 18.3 Functional Description Note: A 9.1-kΩ resistor should be connected between the USB0RBIAS and ground. The 9.1-kΩ resistor should have a 1% tolerance and should be located in close proximity to the USB0RBIAS pin. Power dissipation in the resistor is low, so a chip resistor of any geometry may be used. The Stellaris USB controller provides full OTG negotiation by supporting both the session request protocol (SRP) and the host negotiation protocol (HNP). The session request protocol allows devices on the B side of a cable to request the A side device turn on VBUS. The host negotiation protocol is used after the initial session request protocol has powered the bus and provides a method to determine which end of the cable will act as the Host controller. When the device is connected to non-OTG peripherals or devices, the controller can detect which cable end was used and provides a register to indicate if the controller should act as the Host or the Device controller. This indication and the mode of operation are handled automatically by the USB controller. This auto-detection allows the system to use a single A/B connector instead of having both A and B connectors in the system and supports full OTG negotiations with other OTG devices. In addition, the USB controller provides support for connecting to non-OTG peripherals or Host controllers. The USB controller can be configured to act as either a dedicated Host or Device, in which case, the USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a self-powered Device, a GPIO input or analog comparator input must be connected to VBUS and configured to generate an interrupt when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal. Note: 18.3.1 When USB is used in the system, the minimum system frequency is 20 MHz. Operation as a Device This section describes the Stellaris USB controller's actions when it is being used as a USB Device. Before the USB controller's operating mode is changed from Device to Host or Host to Device, software must reset the USB controller by setting the USB0 bit in the Software Reset Control 2 (SRCR2) register (see page 295). IN endpoints, OUT endpoints, entry into and exit from SUSPEND mode, and recognition of Start of Frame (SOF) are all described. When in Device mode, IN transactions are controlled by an endpoint’s transmit interface and use the transmit endpoint registers for the given endpoint. OUT transactions are handled with an endpoint's receive interface and use the receive endpoint registers for the given endpoint. When configuring the size of the FIFOs for endpoints, take into account the maximum packet size for an endpoint. ■ Bulk. Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used (described further in the following section). 866 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used. ■ Isochronous. Isochronous endpoints are more flexible and can be up to 1023 bytes. ■ Control. It is also possible to specify a separate control endpoint for a USB Device. However, in most cases the USB Device should use the dedicated control endpoint on the USB controller’s endpoint 0. 18.3.1.1 Endpoints When operating as a Device, the USB controller provides two dedicated control endpoints (IN and OUT) and 30 configurable endpoints (15 IN and 15 OUT) that can be used for communications with a Host controller. The endpoint number and direction associated with an endpoint is directly related to its register designation. For example, when the Host is transmitting to endpoint 1, all configuration and data is in the endpoint 1 transmit register interface. Endpoint 0 is a dedicated control endpoint used for all control transactions to endpoint 0 during enumeration or when any other control requests are made to endpoint 0. Endpoint 0 uses the first 64 bytes of the USB controller's FIFO RAM as a shared memory for both IN and OUT transactions. The remaining 30 endpoints can be configured as control, bulk, interrupt, or isochronous endpoints. They should be treated as 15 configurable IN and 15 configurable OUT endpoints. The endpoint pairs are not required to have the same type for their IN and OUT endpoint configuration. For example, the OUT portion of an endpoint pair could be a bulk endpoint, while the IN portion of that endpoint pair could be an interrupt endpoint. The address and size of the FIFOs attached to each endpoint can be modified to fit the application's needs. 18.3.1.2 IN Transactions as a Device When operating as a USB Device, data for IN transactions is handled through the FIFOs attached to the transmit endpoints. The sizes of the FIFOs for the 15 configurable IN endpoints are determined by the USB Transmit FIFO Start Address (USBTXFIFOADD) register. The maximum size of a data packet that may be placed in a transmit endpoint’s FIFO for transmission is programmable and is determined by the value written to the USB Maximum Transmit Data Endpoint n (USBTXMAXPn) register for that endpoint. The endpoint’s FIFO can also be configured to use double-packet or single-packet buffering. When double-packet buffering is enabled, two data packets can be buffered in the FIFO, which also requires that the FIFO is at least two packets in size. When double-packet buffering is disabled, only one packet can be buffered, even if the packet size is less than half the FIFO size. Note: The maximum packet size set for any endpoint must not exceed the FIFO size. The USBTXMAXPn register should not be written to while data is in the FIFO as unexpected results may occur. Single-Packet Buffering If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint (as set in the USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) register), only one packet can be buffered in the FIFO and single-packet buffering is required. When each packet is completely loaded into the transmit FIFO, the TXRDY bit in the USB Transmit Control and Status Endpoint n Low (USBTXCSRLn) register must be set. If the AUTOSET bit in the USB Transmit Control and Status Endpoint n High (USBTXCSRHn) register is set, the TXRDY bit is automatically set when a maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, the TXRDY bit must be set manually. When the TXRDY bit is set, either manually or automatically, the packet is ready to be sent. When the packet has been successfully sent, both TXRDY and FIFONE July 22, 2011 867 Texas Instruments-Production Data Universal Serial Bus (USB) Controller are cleared, and the appropriate transmit endpoint interrupt signaled. At this point, the next packet can be loaded into the FIFO. Double-Packet Buffering If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint, two packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is loaded into the transmit FIFO, the TXRDY bit in the USBTXCSRLn register must be set. If the AUTOSET bit in the USBTXCSRHn register is set, the TXRDY bit is automatically set when a maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, TXRDY must be set manually. When the TXRDY bit is set, either manually or automatically, the packet is ready to be sent. After the first packet is loaded, TXRDY is immediately cleared and an interrupt is generated. A second packet can now be loaded into the transmit FIFO and TXRDY set again (either manually or automatically if the packet is the maximum size). At this point, both packets are ready to be sent. After each packet has been successfully sent, TXRDY is automatically cleared and the appropriate transmit endpoint interrupt signaled to indicate that another packet can now be loaded into the transmit FIFO. The state of the FIFONE bit in the USBTXCSRLn register at this point indicates how many packets may be loaded. If the FIFONE bit is set, then another packet is in the FIFO and only one more packet can be loaded. If the FIFONE bit is clear, then no packets are in the FIFO and two more packets can be loaded. Note: 18.3.1.3 Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS) register. This bit is set by default, so it must be cleared to enable double-packet buffering. OUT Transactions as a Device When in Device mode, OUT transactions are handled through the USB controller receive FIFOs. The sizes of the receive FIFOs for the 15 configurable OUT endpoints are determined by the USB Receive FIFO Start Address (USBRXFIFOADD) register. The maximum amount of data received by an endpoint in any packet is determined by the value written to the USB Maximum Receive Data Endpoint n (USBRXMAXPn) register for that endpoint. When double-packet buffering is enabled, two data packets can be buffered in the FIFO. When double-packet buffering is disabled, only one packet can be buffered even if the packet is less than half the FIFO size. Note: In all cases, the maximum packet size must not exceed the FIFO size. Single-Packet Buffering If the size of the receive endpoint FIFO is less than twice the maximum packet size for an endpoint, only one data packet can be buffered in the FIFO and single-packet buffering is required. When a packet is received and placed in the receive FIFO, the RXRDY and FULL bits in the USB Receive Control and Status Endpoint n Low (USBRXCSRLn) register are set and the appropriate receive endpoint is signaled, indicating that a packet can now be unloaded from the FIFO. After the packet has been unloaded, the RXRDY bit must be cleared in order to allow further packets to be received. This action also generates the acknowledge signaling to the Host controller. If the AUTOCL bit in the USB Receive Control and Status Endpoint n High (USBRXCSRHn) register is set and a maximum-sized packet is unloaded from the FIFO, the RXRDY and FULL bits are cleared automatically. For packet sizes less than the maximum, RXRDY must be cleared manually. Double-Packet Buffering If the size of the receive endpoint FIFO is at least twice the maximum packet size for the endpoint, two data packets can be buffered and double-packet buffering can be used. When the first packet is received and loaded into the receive FIFO, the RXRDY bit in the USBRXCSRLn register is set 868 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be unloaded from the FIFO. Note: The FULL bit in USBRXCSRLn is not set when the first packet is received. It is only set if a second packet is received and loaded into the receive FIFO. After each packet has been unloaded, the RXRDY bit must be cleared to allow further packets to be received. If the AUTOCL bit in the USBRXCSRHn register is set and a maximum-sized packet is unloaded from the FIFO, the RXRDY bit is cleared automatically. For packet sizes less than the maximum, RXRDY must be cleared manually. If the FULL bit is set when RXRDY is cleared, the USB controller first clears the FULL bit, then sets RXRDY again to indicate that there is another packet waiting in the FIFO to be unloaded. Note: 18.3.1.4 Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) register. This bit is set by default, so it must be cleared to enable double-packet buffering. Scheduling The Device has no control over the scheduling of transactions as scheduling is determined by the Host controller. The Stellaris USB controller can set up a transaction at any time. The USB controller waits for the request from the Host controller and generates an interrupt when the transaction is complete or if it was terminated due to some error. If the Host controller makes a request and the Device controller is not ready, the USB controller sends a busy response (NAK) to all requests until it is ready. 18.3.1.5 Additional Actions The USB controller responds automatically to certain conditions on the USB bus or actions by the Host controller such as when the USB controller automatically stalls a control transfer or unexpected zero length OUT data packets. Stalled Control Transfer The USB controller automatically issues a STALL handshake to a control transfer under the following conditions: 1. The Host sends more data during an OUT data phase of a control transfer than was specified in the Device request during the SETUP phase. This condition is detected by the USB controller when the Host sends an OUT token (instead of an IN token) after the last OUT packet has been unloaded and the DATAEND bit in the USB Control and Status Endpoint 0 Low (USBCSRL0) register has been set. 2. The Host requests more data during an IN data phase of a control transfer than was specified in the Device request during the SETUP phase. This condition is detected by the USB controller when the Host sends an IN token (instead of an OUT token) after the CPU has cleared TXRDY and set DATAEND in response to the ACK issued by the Host to what should have been the last packet. 3. The Host sends more than USBRXMAXPn bytes of data with an OUT data token. 4. The Host sends more than a zero length data packet for the OUT STATUS phase. July 22, 2011 869 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Zero Length OUT Data Packets A zero-length OUT data packet is used to indicate the end of a control transfer. In normal operation, such packets should only be received after the entire length of the Device request has been transferred. However, if the Host sends a zero-length OUT data packet before the entire length of Device request has been transferred, it is signaling the premature end of the transfer. In this case, the USB controller automatically flushes any IN token ready for the data phase from the FIFO and sets the DATAEND bit in the USBCSRL0 register. Setting the Device Address When a Host is attempting to enumerate the USB Device, it requests that the Device change its address from zero to some other value. The address is changed by writing the value that the Host requested to the USB Device Functional Address (USBFADDR) register. However, care should be taken when writing to USBFADDR to avoid changing the address before the transaction is complete. This register should only be set after the SET_ADDRESS command is complete. Like all control transactions, the transaction is only complete after the Device has left the STATUS phase. In the case of a SET_ADDRESS command, the transaction is completed by responding to the IN request from the Host with a zero-byte packet. Once the Device has responded to the IN request, the USBFADDR register should be programmed to the new value as soon as possible to avoid missing any new commands sent to the new address. Note: 18.3.1.6 If the USBFADDR register is set to the new value as soon as the Device receives the OUT transaction with the SET_ADDRESS command in the packet, it changes the address during the control transfer. In this case, the Device does not receive the IN request that allows the USB transaction to exit the STATUS phase of the control transfer because it is sent to the old address. As a result, the Host does not get a response to the IN request, and the Host fails to enumerate the Device. Device Mode SUSPEND When no activity has occurred on the USB bus for 3 ms, the USB controller automatically enters SUSPEND mode. If the SUSPEND interrupt has been enabled in the USB Interrupt Enable (USBIE) register, an interrupt is generated at this time. When in SUSPEND mode, the PHY also goes into SUSPEND mode. When RESUME signaling is detected, the USB controller exits SUSPEND mode and takes the PHY out of SUSPEND. If the RESUME interrupt is enabled, an interrupt is generated. The USB controller can also be forced to exit SUSPEND mode by setting the RESUME bit in the USB Power (USBPOWER) register. When this bit is set, the USB controller exits SUSPEND mode and drives RESUME signaling onto the bus. The RESUME bit must be cleared after 10 ms (a maximum of 15 ms) to end RESUME signaling. To meet USB power requirements, the controller can be put into Deep Sleep mode which keeps the controller in a static state. 18.3.1.7 Start-of-Frame When the USB controller is operating in Device mode, it receives a Start-Of-Frame (SOF) packet from the Host once every millisecond. When the SOF packet is received, the 11-bit frame number contained in the packet is written into the USB Frame Value (USBFRAME) register, and an SOF interrupt is also signaled and can be handled by the application. Once the USB controller has started to receive SOF packets, it expects one every millisecond. If no SOF packet is received after 1.00358 ms, the packet is assumed to have been lost, and the USBFRAME register is not updated. The USB controller continues and resynchronizes these pulses to the received SOF packets when these packets are successfully received again. 870 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 18.3.1.8 USB RESET When the USB controller is in Device mode and a RESET condition is detected on the USB bus, the USB controller automatically performs the following actions: ■ Clears the USBFADDR register. ■ Clears the USB Endpoint Index (USBEPIDX) register. ■ Flushes all endpoint FIFOs. ■ Clears all control/status registers. ■ Enables all endpoint interrupts. ■ Generates a RESET interrupt. When the application software driving the USB controller receives a RESET interrupt, any open pipes are closed and the USB controller waits for bus enumeration to begin. 18.3.1.9 Connect/Disconnect The USB controller connection to the USB bus is handled by software. The USB PHY can be switched between normal mode and non-driving mode by setting or clearing the SOFTCONN bit of the USBPOWER register. When the SOFTCONN bit is set, the PHY is placed in its normal mode, and the USB0DP/USB0DM lines of the USB bus are enabled. At the same time, the USB controller is placed into a state, in which it does not respond to any USB signaling except a USB RESET. When the SOFTCONN bit is cleared, the PHY is put into non-driving mode, USB0DP and USB0DM are tristated, and the USB controller appears to other devices on the USB bus as if it has been disconnected. The non-driving mode is the default so the USB controller appears disconnected until the SOFTCONN bit has been set. The application software can then choose when to set the PHY into its normal mode. Systems with a lengthy initialization procedure may use this to ensure that initialization is complete, and the system is ready to perform enumeration before connecting to the USB bus. Once the SOFTCONN bit has been set, the USB controller can be disconnected by clearing this bit. Note: 18.3.2 The USB controller does not generate an interrupt when the Device is connected to the Host. However, an interrupt is generated when the Host terminates a session. Operation as a Host When the Stellaris USB controller is operating in Host mode, it can either be used for point-to-point communications with another USB device or, when attached to a hub, for communication with multiple devices. Before the USB controller's operating mode is changed from Host to Device or Device to Host, software must reset the USB controller by setting the USB0 bit in the Software Reset Control 2 (SRCR2) register (see page 295). Full-speed and low-speed USB devices are supported, both for point-to-point communication and for operation through a hub. The USB controller automatically carries out the necessary transaction translation needed to allow a low-speed or full-speed device to be used with a USB 2.0 hub. Control, bulk, isochronous, and interrupt transactions are supported. This section describes the USB controller's actions when it is being used as a USB Host. Configuration of IN endpoints, OUT endpoints, entry into and exit from SUSPEND mode, and RESET are all described. When in Host mode, IN transactions are controlled by an endpoint’s receive interface. All IN transactions use the receive endpoint registers and all OUT endpoints use the transmit endpoint July 22, 2011 871 Texas Instruments-Production Data Universal Serial Bus (USB) Controller registers for a given endpoint. As in Device mode, the FIFOs for endpoints should take into account the maximum packet size for an endpoint. ■ Bulk. Bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used (described further in the following section). ■ Interrupt. Interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used. ■ Isochronous. Isochronous endpoints are more flexible and can be up to 1023 bytes. ■ Control. It is also possible to specify a separate control endpoint to communicate with a Device. However, in most cases the USB controller should use the dedicated control endpoint to communicate with a Device’s endpoint 0. 18.3.2.1 Endpoints The endpoint registers are used to control the USB endpoint interfaces which communicate with Device(s) that are connected. The endpoints consist of a dedicated control IN endpoint, a dedicated control OUT endpoint, 15 configurable OUT endpoints, and 15 configurable IN endpoints. The dedicated control interface can only be used for control transactions to endpoint 0 of Devices. These control transactions are used during enumeration or other control functions that communicate using endpoint 0 of Devices. This control endpoint shares the first 64 bytes of the USB controller’s FIFO RAM for IN and OUT transactions. The remaining IN and OUT interfaces can be configured to communicate with control, bulk, interrupt, or isochronous Device endpoints. These USB interfaces can be used to simultaneously schedule as many as 15 independent OUT and 15 independent IN transactions to any endpoints on any Device. The IN and OUT controls are paired in three sets of registers. However, they can be configured to communicate with different types of endpoints and different endpoints on Devices. For example, the first pair of endpoint controls can be split so that the OUT portion is communicating with a Device’s bulk OUT endpoint 1, while the IN portion is communicating with a Device’s interrupt IN endpoint 2. Before accessing any Device, whether for point-to-point communications or for communications via a hub, the relevant USB Receive Functional Address Endpoint n (USBRXFUNCADDRn) or USB Transmit Functional Address Endpoint n (USBTXFUNCADDRn) registers must be set for each receive or transmit endpoint to record the address of the Device being accessed. The USB controller also supports connections to Devices through a USB hub by providing a register that specifies the hub address and port of each USB transfer. The FIFO address and size are customizable and can be specified for each USB IN and OUT transfer. Customization includes allowing one FIFO per transaction, sharing a FIFO across transactions, and allowing for double-buffered FIFOs. 18.3.2.2 IN Transactions as a Host IN transactions are handled in a similar manner to the way in which OUT transactions are handled when the USB controller is in Device mode except that the transaction first must be initiated by setting the REQPKT bit in the USBCSRL0 register, indicating to the transaction scheduler that there is an active transaction on this endpoint. The transaction scheduler then sends an IN token to the target Device. When the packet is received and placed in the receive FIFO, the RXRDY bit in the USBCSRL0 register is set, and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be unloaded from the FIFO. When the packet has been unloaded, RXRDY must be cleared. The AUTOCL bit in the USBRXCSRHn register can be used to have RXRDY automatically cleared when a maximum-sized packet has been 872 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller unloaded from the FIFO. The AUTORQ bit in USBRXCSRHn causes the REQPKT bit to be automatically set when the RXRDY bit is cleared. The AUTOCL and AUTORQ bits can be used with µDMA accesses to perform complete bulk transfers without main processor intervention. When the RXRDY bit is cleared, the controller sends an acknowledge to the Device. When there is a known number of packets to be transferred, the USB Request Packet Count in Block Transfer Endpoint n (USBRQPKTCOUNTn) register associated with the endpoint should be configured to the number of packets to be transferred. The USB controller decrements the value in the USBRQPKTCOUNTn register following each request. When the USBRQPKTCOUNTn value decrements to 0, the AUTORQ bit is cleared to prevent any further transactions being attempted. For cases where the size of the transfer is unknown, USBRQPKTCOUNTn should be cleared. AUTORQ then remains set until cleared by the reception of a short packet (that is, less than the MAXLOAD value in the USBRXMAXPn register) such as may occur at the end of a bulk transfer. If the Device responds to a bulk or interrupt IN token with a NAK, the USB Host controller keeps retrying the transaction until any NAK Limit that has been set has been reached. If the target Device responds with a STALL, however, the USB Host controller does not retry the transaction but sets the STALLED bit in the USBCSRL0 register. If the target Device does not respond to the IN token within the required time, or the packet contained a CRC or bit-stuff error, the USB Host controller retries the transaction. If after three attempts the target Device has still not responded, the USB Host controller clears the REQPKT bit and sets the ERROR bit in the USBCSRL0 register. 18.3.2.3 OUT Transactions as a Host OUT transactions are handled in a similar manner to the way in which IN transactions are handled when the USB controller is in Device mode. The TXRDY bit in the USBTXCSRLn register must be set as each packet is loaded into the transmit FIFO. Again, setting the AUTOSET bit in the USBTXCSRHn register automatically sets TXRDY when a maximum-sized packet has been loaded into the FIFO. Furthermore, AUTOSET can be used with the µDMA controller to perform complete bulk transfers without software intervention. If the target Device responds to the OUT token with a NAK, the USB Host controller keeps retrying the transaction until the NAK Limit that has been set has been reached. However, if the target Device responds with a STALL, the USB controller does not retry the transaction but interrupts the main processor by setting the STALLED bit in the USBTXCSRLn register. If the target Device does not respond to the OUT token within the required time, or the packet contained a CRC or bit-stuff error, the USB Host controller retries the transaction. If after three attempts the target Device has still not responded, the USB controller flushes the FIFO and sets the ERROR bit in the USBTXCSRLn register. 18.3.2.4 Transaction Scheduling Scheduling of transactions is handled automatically by the USB Host controller. The Host controller allows configuration of the endpoint communication scheduling based on the type of endpoint transaction. Interrupt transactions can be scheduled to occur in the range of every frame to every 255 frames in 1 frame increments. Bulk endpoints do not allow scheduling parameters, but do allow for a NAK timeout in the event an endpoint on a Device is not responding. Isochronous endpoints can be scheduled from every frame to every 216 frames, in powers of 2. The USB controller maintains a frame counter. If the target Device is a full-speed device, the USB controller automatically sends an SOF packet at the start of each frame and increments the frame counter. If the target Device is a low-speed device, a K state is transmitted on the bus to act as a keep-alive to stop the low-speed device from going into SUSPEND mode. After the SOF packet has been transmitted, the USB Host controller cycles through all the configured endpoints looking for active transactions. An active transaction is defined as a receive endpoint for July 22, 2011 873 Texas Instruments-Production Data Universal Serial Bus (USB) Controller which the REQPKT bit is set or a transmit endpoint for which the TXRDY bit and/or the FIFONE bit is set. An isochronous or interrupt transaction is started if the transaction is found on the first scheduler cycle of a frame and if the interval counter for that endpoint has counted down to zero. As a result, only one interrupt or isochronous transaction occurs per endpoint every n frames, where n is the interval set via the USB Host Transmit Interval Endpoint n (USBTXINTERVALn) or USB Host Receive Interval Endpoint n (USBRXINTERVALn) register for that endpoint. An active bulk transaction starts immediately, provided sufficient time is left in the frame to complete the transaction before the next SOF packet is due. If the transaction must be retried (for example, because a NAK was received or the target Device did not respond), then the transaction is not retried until the transaction scheduler has first checked all the other endpoints for active transactions. This process ensures that an endpoint that is sending a lot of NAKs does not block other transactions on the bus. The controller also allows the user to specify a limit to the length of time for NAKs to be received from a target Device before the endpoint times out. 18.3.2.5 USB Hubs The following setup requirements apply to the USB Host controller only if it is used with a USB hub. When a full- or low-speed Device is connected to the USB controller via a USB 2.0 hub, details of the hub address and the hub port also must be recorded in the corresponding USB Receive Hub Address Endpoint n (USBRXHUBADDRn) and USB Receive Hub Port Endpoint n (USBRXHUBPORTn) or the USB Transmit Hub Address Endpoint n (USBTXHUBADDRn) and USB Transmit Hub Port Endpoint n (USBTXHUBPORTn) registers. In addition, the speed at which the Device operates (full or low) must be recorded in the USB Type Endpoint 0 (USBTYPE0) (endpoint 0), USB Host Configure Transmit Type Endpoint n (USBTXTYPEn), or USB Host Configure Receive Type Endpoint n (USBRXTYPEn) registers for each endpoint that is accessed by the Device. For hub communications, the settings in these registers record the current allocation of the endpoints to the attached USB Devices. To maximize the number of Devices supported, the USB Host controller allows this allocation to be changed dynamically by simply updating the address and speed information recorded in these registers. Any changes in the allocation of endpoints to Device functions must be made following the completion of any on-going transactions on the endpoints affected. 18.3.2.6 Babble The USB Host controller does not start a transaction until the bus has been inactive for at least the minimum inter-packet delay. The controller also does not start a transaction unless it can be finished before the end of the frame. If the bus is still active at the end of a frame, then the USB Host controller assumes that the target Device to which it is connected has malfunctioned, and the USB controller suspends all transactions and generates a babble interrupt. 18.3.2.7 Host SUSPEND If the SUSPEND bit in the USBPOWER register is set, the USB Host controller completes the current transaction then stops the transaction scheduler and frame counter. No further transactions are started and no SOF packets are generated. To exit SUSPEND mode, set the RESUME bit and clear the SUSPEND bit. While the RESUME bit is set, the USB Host controller generates RESUME signaling on the bus. After 20 ms, the RESUME bit must be cleared, at which point the frame counter and transaction scheduler start. The Host supports the detection of a remote wake-up. 874 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 18.3.2.8 USB RESET If the RESET bit in the USBPOWER register is set, the USB Host controller generates USB RESET signaling on the bus. The RESET bit must be set for at least 20 ms to ensure correct resetting of the target Device. After the CPU has cleared the bit, the USB Host controller starts its frame counter and transaction scheduler. 18.3.2.9 Connect/Disconnect A session is started by setting the SESSION bit in the USB Device Control (USBDEVCTL) register, enabling the USB controller to wait for a Device to be connected. When a Device is detected, a connect interrupt is generated. The speed of the Device that has been connected can be determined by reading the USBDEVCTL register where the FSDEV bit is set for a full-speed Device, and the LSDEV bit is set for a low-speed Device. The USB controller must generate a RESET to the Device, and then the USB Host controller can begin Device enumeration. If the Device is disconnected while a session is in progress, a disconnect interrupt is generated. 18.3.3 OTG Mode To conserve power, the USB On-The-Go (OTG) supplement allows VBUS to only be powered up when required and to be turned off when the bus is not in use. VBUS is always supplied by the A device on the bus. The USB OTG controller determines whether it is the A device or the B device by sampling the ID input from the PHY. This signal is pulled Low when an A-type plug is sensed (signifying that the USB OTG controller should act as the A device) but taken High when a B-type plug is sensed (signifying that the USB controller is a B device). Note that when switching between OTG A and OTG B, the USB controller retains all register contents. 18.3.3.1 Starting a Session When the USB OTG controller is ready to start a session, the SESSION bit must be set in the USBDEVCTL register. The USB OTG controller then enables ID pin sensing. The ID input is either taken Low if an A-type connection is detected or High if a B-type connection is detected. The DEV bit in the USBDEVCTL register is also set to indicate whether the USB OTG controller has adopted the role of the A device or the B device. The USB OTG controller also provides an interrupt to indicate that ID pin sensing has completed and the mode value in the USBDEVCTL register is valid. This interrupt is enabled in the USBIDVIM register, and the status is checked in the USBIDVISC register. As soon as the USB controller has detected that it is on the A side of the cable, it must enable VBUS power within 100ms or the USB controller reverts to Device mode. If the USB OTG controller is the A device, then the USB OTG controller enters Host mode (the A device is always the default Host), turns on VBUS, and waits for VBUS to go above the VBUS Valid threshold, as indicated by the VBUS bit in the USBDEVCTL register going to 0x3. The USB OTG controller then waits for a peripheral to be connected. When a peripheral is detected, a Connect interrupt is signaled and either the FSDEV or LSDEV bit in the USBDEVCTL register is set, depending whether a full-speed or a low-speed peripheral is detected. The USB controller then issues a RESET to the connected Device. The SESSION bit in the USBDEVCTL register can be cleared to end a session. The USB OTG controller also automatically ends the session if babble is detected or if VBUS drops below session valid. Note: The USB OTG controller may not remain in Host mode when connected to high-current devices. Some devices draw enough current to momentarily drop VBUS below the VBUS-valid level causing the controller to drop out of Host mode. The only way to get back into Host mode is to allow VBUS to go below the Session End level. In this situation, the device is causing VBUS to drop repeatedly and pull VBUS back low the next time VBUS is enabled. July 22, 2011 875 Texas Instruments-Production Data Universal Serial Bus (USB) Controller In addition, the USB OTG controller may not remain in Host mode when a device is told that it can start using it's active configuration. At this point the device starts drawing more current and can also drop VBUS below VBUS valid. If the USB OTG controller is the B device, then the USB OTG controller requests a session using the session request protocol defined in the USB On-The-Go supplement, that is, it first discharges VBUS. Then when VBUS has gone below the Session End threshold (VBUS bit in the USBDEVCTL register goes to 0x0) and the line state has been a single-ended zero for > 2 ms, the USB OTG controller pulses the data line, then pulses VBUS. At the end of the session, the SESSION bit is cleared either by the USB OTG controller or by the application software. The USB OTG controller then causes the PHY to switch out the pull-up resistor on D+, signaling the A device to end the session. 18.3.3.2 Detecting Activity When the other device of the OTG setup wishes to start a session, it either raises VBUS above the Session Valid threshold if it is the A device, or if it is the B device, it pulses the data line then pulses VBUS. Depending on which of these actions happens, the USB controller can determine whether it is the A device or the B device in the current setup and act accordingly. If VBUS is raised above the Session Valid threshold, then the USB controller is the B device. The USB controller sets the SESSION bit in the USBDEVCTL register. When RESET signaling is detected on the bus, a RESET interrupt is signaled, which is interpreted as the start of a session. The USB controller is in Device mode as the B device is the default mode. At the end of the session, the A device turns off the power to VBUS. When VBUS drops below the Session Valid threshold, the USB controller detects this drop and clears the SESSION bit to indicate that the session has ended, causing a disconnect interrupt to be signaled. If data line and VBUS pulsing is detected, then the USB controller is the A device. The controller generates a SESSION REQUEST interrupt to indicate that the B device is requesting a session. The SESSION bit in the USBDEVCTL register must be set to start a session. 18.3.3.3 Host Negotiation When the USB controller is the A device, ID is Low, and the controller automatically enters Host mode when a session starts. When the USB controller is the B device, ID is High, and the controller automatically enters Device mode when a session starts. However, software can request that the USB controller become the Host by setting the HOSTREQ bit in the USBDEVCTL register. This bit can be set either at the same time as requesting a Session Start by setting the SESSION bit in the USBDEVCTL register or at any time after a session has started. When the USB controller next enters SUSPEND mode and if the HOSTREQ bit remains set, the controller enters Host mode and begins host negotiation (as specified in the USB On-The-Go supplement) by causing the PHY to disconnect the pull-up resistor on the D+ line, causing the A device to switch to Device mode and connect its own pull-up resistor. When the USB controller detects this, a Connect interrupt is generated and the RESET bit in the USBPOWER register is set to begin resetting the A device. The USB controller begins this reset sequence automatically to ensure that RESET is started as required within 1 ms of the A device connecting its pull-up resistor. The main processor should wait at least 20 ms, then clear the RESET bit and enumerate the A device. When the USB OTG controller B device has finished using the bus, the USB controller goes into SUSPEND mode by setting the SUSPEND bit in the USBPOWER register. The A device detects this and either terminates the session or reverts to Host mode. If the A device is USB OTG controller, it generates a Disconnect interrupt. 876 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 18.3.4 DMA Operation The USB peripheral provides an interface connected to the μDMA controller with separate channels for 3 transmit endpoints and 3 receive endpoints. Software selects which endpoints to service with the μDMA channels using the USB DMA Select (USBDMASEL) register. The μDMA operation of the USB is enabled through the USBTXCSRHn and USBRXCSRHn registers, for the TX and RX channels respectively. When μDMA operation is enabled, the USB asserts a μDMA request on the enabled receive or transmit channel when the associated FIFO can transfer data. When either FIFO can transfer data, the burst request for that channel is asserted. The μDMA channel must be configured to operate in Basic mode, and the size of the μDMA transfer must be restricted to whole multiples of the size of the USB FIFO. Both read and write transfers of the USB FIFOs using μDMA must be configured in this manner. For example, if the USB endpoint is configured with a FIFO size of 64 bytes, the μDMA channel can be used to transfer 64 bytes to or from the endpoint FIFO. If the number of bytes to transfer is less than 64, then a programmed I/O method must be used to copy the data to or from the FIFO. If the DMAMOD bit in the USBTXCSRHn/USBRXCSRHn register is clear, an interrupt is generated after every packet is transferred, but the μDMA continues transferring data. If the DMAMOD bit is set, an interrupt is generated only when the entire μDMA transfer is complete. The interrupt occurs on the USB interrupt vector. Therefore, if interrupts are used for USB operation and the μDMA is enabled, the USB interrupt handler must be designed to handle the μDMA completion interrupt. Care must be taken when using the μDMA to unload the receive FIFO as data is read from the receive FIFO in 4 byte chunks regardless of value of the MAXLOAD field in the USBRXCSRHn register. The RXRDY bit is cleared as follows. Table 18-3. Remainder (MAXLOAD/4) Value Description 0 MAXLOAD = 64 bytes 1 MAXLOAD = 61 bytes 2 MAXLOAD = 62 bytes 3 MAXLOAD = 63 bytes Table 18-4. Actual Bytes Read Value Description 0 MAXLOAD 1 MAXLOAD+3 2 MAXLOAD+2 3 MAXLOAD+1 Table 18-5. Packet Sizes That Clear RXRDY Value Description 0 MAXLOAD, MAXLOAD-1, MAXLOAD-2, MAXLOAD-3 1 MAXLOAD 2 MAXLOAD, MAXLOAD-1 3 MAXLOAD, MAXLOAD-1, MAXLOAD-2 July 22, 2011 877 Texas Instruments-Production Data Universal Serial Bus (USB) Controller To enable DMA operation for the endpoint receive channel, the DMAEN bit of the USBRXCSRHn register should be set. To enable DMA operation for the endpoint transmit channel, the DMAEN bit of the USBTXCSRHn register must be set. See “Micro Direct Memory Access (μDMA)” on page 333 for more details about programming the μDMA controller. 18.4 Initialization and Configuration To use the USB Controller, the peripheral clock must be enabled via the RCGC2 register (see page 281). In addition, the clock to the appropriate GPIO module must be enabled via the RCGC2 register in the System Control module (see page 281). To find out which GPIO port to enable, refer to Table 23-4 on page 1137. Configure the PMCn fields in the GPIOPCTL register to assign the USB signals to the appropriate pins (see page 434 and Table 23-5 on page 1145). The initial configuration in all cases requires that the processor enable the USB controller and USB controller’s physical layer interface (PHY) before setting any registers. The next step is to enable the USB PLL so that the correct clocking is provided to the PHY. To ensure that voltage is not supplied to the bus incorrectly, the external power control signal, USB0EPEN, should be negated on start up by configuring the USB0EPEN and USB0PFLT pins to be controlled by the USB controller and not exhibit their default GPIO behavior. Note: 18.4.1 When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they are dedicated pins for the USB controller and directly connect to the USB connector's VBUS and ID signals. If the USB controller is used as either a dedicated Host or Device, the DEVMODOTG and DEVMOD bits in the USB General-Purpose Control and Status (USBGPCS) register can be used to connect the USB0VBUS and USB0ID inputs to fixed levels internally, freeing the PB0 and PB1 pins for GPIO use. For proper self-powered Device operation, the VBUS value must still be monitored to assure that if the Host removes VBUS, the self-powered Device disables the D+/D- pull-up resistors. This function can be accomplished by connecting a standard GPIO to VBUS. Pin Configuration When using the Device controller portion of the USB controller in a system that also provides Host functionality, the power to VBUS must be disabled to allow the external Host controller to supply power. Usually, the USB0EPEN signal is used to control the external regulator and should be negated to avoid having two devices driving the USB0VBUS power pin on the USB connector. When the USB controller is acting as a Host, it is in control of two signals that are attached to an external voltage supply that provides power to VBUS. The Host controller uses the USB0EPEN signal to enable or disable power to the USB0VBUS pin on the USB connector. An input pin, USB0PFLT, provides feedback when there has been a power fault on VBUS. The USB0PFLT signal can be configured to either automatically negate the USB0EPEN signal to disable power, and/or it can generate an interrupt to the interrupt controller to allow software to handle the power fault condition. The polarity and actions related to both USB0EPEN and USB0PFLT are fully configurable in the USB controller. The controller also provides interrupts on Device insertion and removal to allow the Host controller code to respond to these external events. 18.4.2 Endpoint Configuration To start communication in Host or Device mode, the endpoint registers must first be configured. In Host mode, this configuration establishes a connection between an endpoint register and an endpoint on a Device. In Device mode, an endpoint must be configured before enumerating to the Host controller. 878 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller In both cases, the endpoint 0 configuration is limited because it is a fixed-function, fixed-FIFO-size endpoint. In Device and Host modes, the endpoint requires little setup but does require a software-based state machine to progress through the setup, data, and status phases of a standard control transaction. In Device mode, the configuration of the remaining endpoints is done once before enumerating and then only changed if an alternate configuration is selected by the Host controller. In Host mode, the endpoints must be configured to operate as control, bulk, interrupt or isochronous mode. Once the type of endpoint is configured, a FIFO area must be assigned to each endpoint. In the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per transaction. Isochronous endpoints can have packets with up to 1023 bytes per packet. In either mode, the maximum packet size for the given endpoint must be set prior to sending or receiving data. Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to each endpoint. The total FIFO RAM available is 4 Kbytes with the first 64 bytes reserved for endpoint 0. The endpoint’s FIFO must be at least as large as the maximum packet size. The FIFO can also be configured as a double-buffered FIFO so that interrupts occur at the end of each packet and allow filling the other half of the FIFO. If operating as a Device, the USB Device controller's soft connect must be enabled when the Device is ready to start communications, indicating to the Host controller that the Device is ready to start the enumeration process. If operating as a Host controller, the Device soft connect must be disabled and power must be provided to VBUS via the USB0EPEN signal. 18.5 Register Map Table 18-6 on page 879 lists the registers. All addresses given are relative to the USB base address of 0x4005.0000. Note that the USB controller clock must be enabled before the registers can be programmed (see page 281). There must be a delay of 3 system clocks after the USB module clock is enabled before any USB module registers are accessed. Table 18-6. Universal Serial Bus (USB) Controller Register Map See page Offset Name Type Reset Description 0x000 USBFADDR R/W 0x00 USB Device Functional Address 891 0x001 USBPOWER R/W 0x20 USB Power 892 0x002 USBTXIS RO 0x0000 USB Transmit Interrupt Status 895 0x004 USBRXIS RO 0x0000 USB Receive Interrupt Status 897 0x006 USBTXIE R/W 0xFFFF USB Transmit Interrupt Enable 899 0x008 USBRXIE R/W 0xFFFE USB Receive Interrupt Enable 901 0x00A USBIS RO 0x00 USB General Interrupt Status 903 0x00B USBIE R/W 0x06 USB Interrupt Enable 906 0x00C USBFRAME RO 0x0000 USB Frame Value 909 0x00E USBEPIDX R/W 0x00 USB Endpoint Index 910 0x00F USBTEST R/W 0x00 USB Test Mode 911 0x020 USBFIFO0 R/W 0x0000.0000 USB FIFO Endpoint 0 913 0x024 USBFIFO1 R/W 0x0000.0000 USB FIFO Endpoint 1 913 July 22, 2011 879 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x028 USBFIFO2 R/W 0x0000.0000 USB FIFO Endpoint 2 913 0x02C USBFIFO3 R/W 0x0000.0000 USB FIFO Endpoint 3 913 0x030 USBFIFO4 R/W 0x0000.0000 USB FIFO Endpoint 4 913 0x034 USBFIFO5 R/W 0x0000.0000 USB FIFO Endpoint 5 913 0x038 USBFIFO6 R/W 0x0000.0000 USB FIFO Endpoint 6 913 0x03C USBFIFO7 R/W 0x0000.0000 USB FIFO Endpoint 7 913 0x040 USBFIFO8 R/W 0x0000.0000 USB FIFO Endpoint 8 913 0x044 USBFIFO9 R/W 0x0000.0000 USB FIFO Endpoint 9 913 0x048 USBFIFO10 R/W 0x0000.0000 USB FIFO Endpoint 10 913 0x04C USBFIFO11 R/W 0x0000.0000 USB FIFO Endpoint 11 913 0x050 USBFIFO12 R/W 0x0000.0000 USB FIFO Endpoint 12 913 0x054 USBFIFO13 R/W 0x0000.0000 USB FIFO Endpoint 13 913 0x058 USBFIFO14 R/W 0x0000.0000 USB FIFO Endpoint 14 913 0x05C USBFIFO15 R/W 0x0000.0000 USB FIFO Endpoint 15 913 0x060 USBDEVCTL R/W 0x80 USB Device Control 915 0x062 USBTXFIFOSZ R/W 0x00 USB Transmit Dynamic FIFO Sizing 917 0x063 USBRXFIFOSZ R/W 0x00 USB Receive Dynamic FIFO Sizing 917 0x064 USBTXFIFOADD R/W 0x0000 USB Transmit FIFO Start Address 918 0x066 USBRXFIFOADD R/W 0x0000 USB Receive FIFO Start Address 918 0x07A USBCONTIM R/W 0x5C USB Connect Timing 919 0x07B USBVPLEN R/W 0x3C USB OTG VBUS Pulse Timing 920 0x07D USBFSEOF R/W 0x77 USB Full-Speed Last Transaction to End of Frame Timing 921 0x07E USBLSEOF R/W 0x72 USB Low-Speed Last Transaction to End of Frame Timing 922 0x080 USBTXFUNCADDR0 R/W 0x00 USB Transmit Functional Address Endpoint 0 923 0x082 USBTXHUBADDR0 R/W 0x00 USB Transmit Hub Address Endpoint 0 925 0x083 USBTXHUBPORT0 R/W 0x00 USB Transmit Hub Port Endpoint 0 927 0x088 USBTXFUNCADDR1 R/W 0x00 USB Transmit Functional Address Endpoint 1 923 0x08A USBTXHUBADDR1 R/W 0x00 USB Transmit Hub Address Endpoint 1 925 0x08B USBTXHUBPORT1 R/W 0x00 USB Transmit Hub Port Endpoint 1 927 0x08C USBRXFUNCADDR1 R/W 0x00 USB Receive Functional Address Endpoint 1 929 0x08E USBRXHUBADDR1 R/W 0x00 USB Receive Hub Address Endpoint 1 931 880 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x08F USBRXHUBPORT1 R/W 0x00 USB Receive Hub Port Endpoint 1 933 0x090 USBTXFUNCADDR2 R/W 0x00 USB Transmit Functional Address Endpoint 2 923 0x092 USBTXHUBADDR2 R/W 0x00 USB Transmit Hub Address Endpoint 2 925 0x093 USBTXHUBPORT2 R/W 0x00 USB Transmit Hub Port Endpoint 2 927 0x094 USBRXFUNCADDR2 R/W 0x00 USB Receive Functional Address Endpoint 2 929 0x096 USBRXHUBADDR2 R/W 0x00 USB Receive Hub Address Endpoint 2 931 0x097 USBRXHUBPORT2 R/W 0x00 USB Receive Hub Port Endpoint 2 933 0x098 USBTXFUNCADDR3 R/W 0x00 USB Transmit Functional Address Endpoint 3 923 0x09A USBTXHUBADDR3 R/W 0x00 USB Transmit Hub Address Endpoint 3 925 0x09B USBTXHUBPORT3 R/W 0x00 USB Transmit Hub Port Endpoint 3 927 0x09C USBRXFUNCADDR3 R/W 0x00 USB Receive Functional Address Endpoint 3 929 0x09E USBRXHUBADDR3 R/W 0x00 USB Receive Hub Address Endpoint 3 931 0x09F USBRXHUBPORT3 R/W 0x00 USB Receive Hub Port Endpoint 3 933 0x0A0 USBTXFUNCADDR4 R/W 0x00 USB Transmit Functional Address Endpoint 4 923 0x0A2 USBTXHUBADDR4 R/W 0x00 USB Transmit Hub Address Endpoint 4 925 0x0A3 USBTXHUBPORT4 R/W 0x00 USB Transmit Hub Port Endpoint 4 927 0x0A4 USBRXFUNCADDR4 R/W 0x00 USB Receive Functional Address Endpoint 4 929 0x0A6 USBRXHUBADDR4 R/W 0x00 USB Receive Hub Address Endpoint 4 931 0x0A7 USBRXHUBPORT4 R/W 0x00 USB Receive Hub Port Endpoint 4 933 0x0A8 USBTXFUNCADDR5 R/W 0x00 USB Transmit Functional Address Endpoint 5 923 0x0AA USBTXHUBADDR5 R/W 0x00 USB Transmit Hub Address Endpoint 5 925 0x0AB USBTXHUBPORT5 R/W 0x00 USB Transmit Hub Port Endpoint 5 927 0x0AC USBRXFUNCADDR5 R/W 0x00 USB Receive Functional Address Endpoint 5 929 0x0AE USBRXHUBADDR5 R/W 0x00 USB Receive Hub Address Endpoint 5 931 0x0AF USBRXHUBPORT5 R/W 0x00 USB Receive Hub Port Endpoint 5 933 0x0B0 USBTXFUNCADDR6 R/W 0x00 USB Transmit Functional Address Endpoint 6 923 0x0B2 USBTXHUBADDR6 R/W 0x00 USB Transmit Hub Address Endpoint 6 925 0x0B3 USBTXHUBPORT6 R/W 0x00 USB Transmit Hub Port Endpoint 6 927 0x0B4 USBRXFUNCADDR6 R/W 0x00 USB Receive Functional Address Endpoint 6 929 0x0B6 USBRXHUBADDR6 R/W 0x00 USB Receive Hub Address Endpoint 6 931 0x0B7 USBRXHUBPORT6 R/W 0x00 USB Receive Hub Port Endpoint 6 933 0x0B8 USBTXFUNCADDR7 R/W 0x00 USB Transmit Functional Address Endpoint 7 923 July 22, 2011 881 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x0BA USBTXHUBADDR7 R/W 0x00 USB Transmit Hub Address Endpoint 7 925 0x0BB USBTXHUBPORT7 R/W 0x00 USB Transmit Hub Port Endpoint 7 927 0x0BC USBRXFUNCADDR7 R/W 0x00 USB Receive Functional Address Endpoint 7 929 0x0BE USBRXHUBADDR7 R/W 0x00 USB Receive Hub Address Endpoint 7 931 0x0BF USBRXHUBPORT7 R/W 0x00 USB Receive Hub Port Endpoint 7 933 0x0C0 USBTXFUNCADDR8 R/W 0x00 USB Transmit Functional Address Endpoint 8 923 0x0C2 USBTXHUBADDR8 R/W 0x00 USB Transmit Hub Address Endpoint 8 925 0x0C3 USBTXHUBPORT8 R/W 0x00 USB Transmit Hub Port Endpoint 8 927 0x0C4 USBRXFUNCADDR8 R/W 0x00 USB Receive Functional Address Endpoint 8 929 0x0C6 USBRXHUBADDR8 R/W 0x00 USB Receive Hub Address Endpoint 8 931 0x0C7 USBRXHUBPORT8 R/W 0x00 USB Receive Hub Port Endpoint 8 933 0x0C8 USBTXFUNCADDR9 R/W 0x00 USB Transmit Functional Address Endpoint 9 923 0x0CA USBTXHUBADDR9 R/W 0x00 USB Transmit Hub Address Endpoint 9 925 0x0CB USBTXHUBPORT9 R/W 0x00 USB Transmit Hub Port Endpoint 9 927 0x0CC USBRXFUNCADDR9 R/W 0x00 USB Receive Functional Address Endpoint 9 929 0x0CE USBRXHUBADDR9 R/W 0x00 USB Receive Hub Address Endpoint 9 931 0x0CF USBRXHUBPORT9 R/W 0x00 USB Receive Hub Port Endpoint 9 933 0x0D0 USBTXFUNCADDR10 R/W 0x00 USB Transmit Functional Address Endpoint 10 923 0x0D2 USBTXHUBADDR10 R/W 0x00 USB Transmit Hub Address Endpoint 10 925 0x0D3 USBTXHUBPORT10 R/W 0x00 USB Transmit Hub Port Endpoint 10 927 0x0D4 USBRXFUNCADDR10 R/W 0x00 USB Receive Functional Address Endpoint 10 929 0x0D6 USBRXHUBADDR10 R/W 0x00 USB Receive Hub Address Endpoint 10 931 0x0D7 USBRXHUBPORT10 R/W 0x00 USB Receive Hub Port Endpoint 10 933 0x0D8 USBTXFUNCADDR11 R/W 0x00 USB Transmit Functional Address Endpoint 11 923 0x0DA USBTXHUBADDR11 R/W 0x00 USB Transmit Hub Address Endpoint 11 925 0x0DB USBTXHUBPORT11 R/W 0x00 USB Transmit Hub Port Endpoint 11 927 0x0DC USBRXFUNCADDR11 R/W 0x00 USB Receive Functional Address Endpoint 11 929 0x0DE USBRXHUBADDR11 R/W 0x00 USB Receive Hub Address Endpoint 11 931 0x0DF USBRXHUBPORT11 R/W 0x00 USB Receive Hub Port Endpoint 11 933 0x0E0 USBTXFUNCADDR12 R/W 0x00 USB Transmit Functional Address Endpoint 12 923 0x0E2 USBTXHUBADDR12 R/W 0x00 USB Transmit Hub Address Endpoint 12 925 0x0E3 USBTXHUBPORT12 R/W 0x00 USB Transmit Hub Port Endpoint 12 927 882 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x0E4 USBRXFUNCADDR12 R/W 0x00 USB Receive Functional Address Endpoint 12 929 0x0E6 USBRXHUBADDR12 R/W 0x00 USB Receive Hub Address Endpoint 12 931 0x0E7 USBRXHUBPORT12 R/W 0x00 USB Receive Hub Port Endpoint 12 933 0x0E8 USBTXFUNCADDR13 R/W 0x00 USB Transmit Functional Address Endpoint 13 923 0x0EA USBTXHUBADDR13 R/W 0x00 USB Transmit Hub Address Endpoint 13 925 0x0EB USBTXHUBPORT13 R/W 0x00 USB Transmit Hub Port Endpoint 13 927 0x0EC USBRXFUNCADDR13 R/W 0x00 USB Receive Functional Address Endpoint 13 929 0x0EE USBRXHUBADDR13 R/W 0x00 USB Receive Hub Address Endpoint 13 931 0x0EF USBRXHUBPORT13 R/W 0x00 USB Receive Hub Port Endpoint 13 933 0x0F0 USBTXFUNCADDR14 R/W 0x00 USB Transmit Functional Address Endpoint 14 923 0x0F2 USBTXHUBADDR14 R/W 0x00 USB Transmit Hub Address Endpoint 14 925 0x0F3 USBTXHUBPORT14 R/W 0x00 USB Transmit Hub Port Endpoint 14 927 0x0F4 USBRXFUNCADDR14 R/W 0x00 USB Receive Functional Address Endpoint 14 929 0x0F6 USBRXHUBADDR14 R/W 0x00 USB Receive Hub Address Endpoint 14 931 0x0F7 USBRXHUBPORT14 R/W 0x00 USB Receive Hub Port Endpoint 14 933 0x0F8 USBTXFUNCADDR15 R/W 0x00 USB Transmit Functional Address Endpoint 15 923 0x0FA USBTXHUBADDR15 R/W 0x00 USB Transmit Hub Address Endpoint 15 925 0x0FB USBTXHUBPORT15 R/W 0x00 USB Transmit Hub Port Endpoint 15 927 0x0FC USBRXFUNCADDR15 R/W 0x00 USB Receive Functional Address Endpoint 15 929 0x0FE USBRXHUBADDR15 R/W 0x00 USB Receive Hub Address Endpoint 15 931 0x0FF USBRXHUBPORT15 R/W 0x00 USB Receive Hub Port Endpoint 15 933 0x102 USBCSRL0 W1C 0x00 USB Control and Status Endpoint 0 Low 937 0x103 USBCSRH0 W1C 0x00 USB Control and Status Endpoint 0 High 941 0x108 USBCOUNT0 RO 0x00 USB Receive Byte Count Endpoint 0 943 0x10A USBTYPE0 R/W 0x00 USB Type Endpoint 0 944 0x10B USBNAKLMT R/W 0x00 USB NAK Limit 945 0x110 USBTXMAXP1 R/W 0x0000 USB Maximum Transmit Data Endpoint 1 935 0x112 USBTXCSRL1 R/W 0x00 USB Transmit Control and Status Endpoint 1 Low 946 0x113 USBTXCSRH1 R/W 0x00 USB Transmit Control and Status Endpoint 1 High 951 0x114 USBRXMAXP1 R/W 0x0000 USB Maximum Receive Data Endpoint 1 955 0x116 USBRXCSRL1 R/W 0x00 USB Receive Control and Status Endpoint 1 Low 957 0x117 USBRXCSRH1 R/W 0x00 USB Receive Control and Status Endpoint 1 High 962 July 22, 2011 883 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) Offset Name 0x118 See page Type Reset Description USBRXCOUNT1 RO 0x0000 USB Receive Byte Count Endpoint 1 967 0x11A USBTXTYPE1 R/W 0x00 USB Host Transmit Configure Type Endpoint 1 969 0x11B USBTXINTERVAL1 R/W 0x00 USB Host Transmit Interval Endpoint 1 971 0x11C USBRXTYPE1 R/W 0x00 USB Host Configure Receive Type Endpoint 1 973 0x11D USBRXINTERVAL1 R/W 0x00 USB Host Receive Polling Interval Endpoint 1 975 0x120 USBTXMAXP2 R/W 0x0000 USB Maximum Transmit Data Endpoint 2 935 0x122 USBTXCSRL2 R/W 0x00 USB Transmit Control and Status Endpoint 2 Low 946 0x123 USBTXCSRH2 R/W 0x00 USB Transmit Control and Status Endpoint 2 High 951 0x124 USBRXMAXP2 R/W 0x0000 USB Maximum Receive Data Endpoint 2 955 0x126 USBRXCSRL2 R/W 0x00 USB Receive Control and Status Endpoint 2 Low 957 0x127 USBRXCSRH2 R/W 0x00 USB Receive Control and Status Endpoint 2 High 962 0x128 USBRXCOUNT2 RO 0x0000 USB Receive Byte Count Endpoint 2 967 0x12A USBTXTYPE2 R/W 0x00 USB Host Transmit Configure Type Endpoint 2 969 0x12B USBTXINTERVAL2 R/W 0x00 USB Host Transmit Interval Endpoint 2 971 0x12C USBRXTYPE2 R/W 0x00 USB Host Configure Receive Type Endpoint 2 973 0x12D USBRXINTERVAL2 R/W 0x00 USB Host Receive Polling Interval Endpoint 2 975 0x130 USBTXMAXP3 R/W 0x0000 USB Maximum Transmit Data Endpoint 3 935 0x132 USBTXCSRL3 R/W 0x00 USB Transmit Control and Status Endpoint 3 Low 946 0x133 USBTXCSRH3 R/W 0x00 USB Transmit Control and Status Endpoint 3 High 951 0x134 USBRXMAXP3 R/W 0x0000 USB Maximum Receive Data Endpoint 3 955 0x136 USBRXCSRL3 R/W 0x00 USB Receive Control and Status Endpoint 3 Low 957 0x137 USBRXCSRH3 R/W 0x00 USB Receive Control and Status Endpoint 3 High 962 0x138 USBRXCOUNT3 RO 0x0000 USB Receive Byte Count Endpoint 3 967 0x13A USBTXTYPE3 R/W 0x00 USB Host Transmit Configure Type Endpoint 3 969 0x13B USBTXINTERVAL3 R/W 0x00 USB Host Transmit Interval Endpoint 3 971 0x13C USBRXTYPE3 R/W 0x00 USB Host Configure Receive Type Endpoint 3 973 0x13D USBRXINTERVAL3 R/W 0x00 USB Host Receive Polling Interval Endpoint 3 975 0x140 USBTXMAXP4 R/W 0x0000 USB Maximum Transmit Data Endpoint 4 935 0x142 USBTXCSRL4 R/W 0x00 USB Transmit Control and Status Endpoint 4 Low 946 0x143 USBTXCSRH4 R/W 0x00 USB Transmit Control and Status Endpoint 4 High 951 0x144 USBRXMAXP4 R/W 0x0000 USB Maximum Receive Data Endpoint 4 955 0x146 USBRXCSRL4 R/W 0x00 USB Receive Control and Status Endpoint 4 Low 957 884 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x147 USBRXCSRH4 R/W 0x00 USB Receive Control and Status Endpoint 4 High 962 0x148 USBRXCOUNT4 RO 0x0000 USB Receive Byte Count Endpoint 4 967 0x14A USBTXTYPE4 R/W 0x00 USB Host Transmit Configure Type Endpoint 4 969 0x14B USBTXINTERVAL4 R/W 0x00 USB Host Transmit Interval Endpoint 4 971 0x14C USBRXTYPE4 R/W 0x00 USB Host Configure Receive Type Endpoint 4 973 0x14D USBRXINTERVAL4 R/W 0x00 USB Host Receive Polling Interval Endpoint 4 975 0x150 USBTXMAXP5 R/W 0x0000 USB Maximum Transmit Data Endpoint 5 935 0x152 USBTXCSRL5 R/W 0x00 USB Transmit Control and Status Endpoint 5 Low 946 0x153 USBTXCSRH5 R/W 0x00 USB Transmit Control and Status Endpoint 5 High 951 0x154 USBRXMAXP5 R/W 0x0000 USB Maximum Receive Data Endpoint 5 955 0x156 USBRXCSRL5 R/W 0x00 USB Receive Control and Status Endpoint 5 Low 957 0x157 USBRXCSRH5 R/W 0x00 USB Receive Control and Status Endpoint 5 High 962 0x158 USBRXCOUNT5 RO 0x0000 USB Receive Byte Count Endpoint 5 967 0x15A USBTXTYPE5 R/W 0x00 USB Host Transmit Configure Type Endpoint 5 969 0x15B USBTXINTERVAL5 R/W 0x00 USB Host Transmit Interval Endpoint 5 971 0x15C USBRXTYPE5 R/W 0x00 USB Host Configure Receive Type Endpoint 5 973 0x15D USBRXINTERVAL5 R/W 0x00 USB Host Receive Polling Interval Endpoint 5 975 0x160 USBTXMAXP6 R/W 0x0000 USB Maximum Transmit Data Endpoint 6 935 0x162 USBTXCSRL6 R/W 0x00 USB Transmit Control and Status Endpoint 6 Low 946 0x163 USBTXCSRH6 R/W 0x00 USB Transmit Control and Status Endpoint 6 High 951 0x164 USBRXMAXP6 R/W 0x0000 USB Maximum Receive Data Endpoint 6 955 0x166 USBRXCSRL6 R/W 0x00 USB Receive Control and Status Endpoint 6 Low 957 0x167 USBRXCSRH6 R/W 0x00 USB Receive Control and Status Endpoint 6 High 962 0x168 USBRXCOUNT6 RO 0x0000 USB Receive Byte Count Endpoint 6 967 0x16A USBTXTYPE6 R/W 0x00 USB Host Transmit Configure Type Endpoint 6 969 0x16B USBTXINTERVAL6 R/W 0x00 USB Host Transmit Interval Endpoint 6 971 0x16C USBRXTYPE6 R/W 0x00 USB Host Configure Receive Type Endpoint 6 973 0x16D USBRXINTERVAL6 R/W 0x00 USB Host Receive Polling Interval Endpoint 6 975 0x170 USBTXMAXP7 R/W 0x0000 USB Maximum Transmit Data Endpoint 7 935 0x172 USBTXCSRL7 R/W 0x00 USB Transmit Control and Status Endpoint 7 Low 946 0x173 USBTXCSRH7 R/W 0x00 USB Transmit Control and Status Endpoint 7 High 951 0x174 USBRXMAXP7 R/W 0x0000 USB Maximum Receive Data Endpoint 7 955 July 22, 2011 885 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x176 USBRXCSRL7 R/W 0x00 USB Receive Control and Status Endpoint 7 Low 957 0x177 USBRXCSRH7 R/W 0x00 USB Receive Control and Status Endpoint 7 High 962 0x178 USBRXCOUNT7 RO 0x0000 USB Receive Byte Count Endpoint 7 967 0x17A USBTXTYPE7 R/W 0x00 USB Host Transmit Configure Type Endpoint 7 969 0x17B USBTXINTERVAL7 R/W 0x00 USB Host Transmit Interval Endpoint 7 971 0x17C USBRXTYPE7 R/W 0x00 USB Host Configure Receive Type Endpoint 7 973 0x17D USBRXINTERVAL7 R/W 0x00 USB Host Receive Polling Interval Endpoint 7 975 0x180 USBTXMAXP8 R/W 0x0000 USB Maximum Transmit Data Endpoint 8 935 0x182 USBTXCSRL8 R/W 0x00 USB Transmit Control and Status Endpoint 8 Low 946 0x183 USBTXCSRH8 R/W 0x00 USB Transmit Control and Status Endpoint 8 High 951 0x184 USBRXMAXP8 R/W 0x0000 USB Maximum Receive Data Endpoint 8 955 0x186 USBRXCSRL8 R/W 0x00 USB Receive Control and Status Endpoint 8 Low 957 0x187 USBRXCSRH8 R/W 0x00 USB Receive Control and Status Endpoint 8 High 962 0x188 USBRXCOUNT8 RO 0x0000 USB Receive Byte Count Endpoint 8 967 0x18A USBTXTYPE8 R/W 0x00 USB Host Transmit Configure Type Endpoint 8 969 0x18B USBTXINTERVAL8 R/W 0x00 USB Host Transmit Interval Endpoint 8 971 0x18C USBRXTYPE8 R/W 0x00 USB Host Configure Receive Type Endpoint 8 973 0x18D USBRXINTERVAL8 R/W 0x00 USB Host Receive Polling Interval Endpoint 8 975 0x190 USBTXMAXP9 R/W 0x0000 USB Maximum Transmit Data Endpoint 9 935 0x192 USBTXCSRL9 R/W 0x00 USB Transmit Control and Status Endpoint 9 Low 946 0x193 USBTXCSRH9 R/W 0x00 USB Transmit Control and Status Endpoint 9 High 951 0x194 USBRXMAXP9 R/W 0x0000 USB Maximum Receive Data Endpoint 9 955 0x196 USBRXCSRL9 R/W 0x00 USB Receive Control and Status Endpoint 9 Low 957 0x197 USBRXCSRH9 R/W 0x00 USB Receive Control and Status Endpoint 9 High 962 0x198 USBRXCOUNT9 RO 0x0000 USB Receive Byte Count Endpoint 9 967 0x19A USBTXTYPE9 R/W 0x00 USB Host Transmit Configure Type Endpoint 9 969 0x19B USBTXINTERVAL9 R/W 0x00 USB Host Transmit Interval Endpoint 9 971 0x19C USBRXTYPE9 R/W 0x00 USB Host Configure Receive Type Endpoint 9 973 0x19D USBRXINTERVAL9 R/W 0x00 USB Host Receive Polling Interval Endpoint 9 975 0x1A0 USBTXMAXP10 R/W 0x0000 USB Maximum Transmit Data Endpoint 10 935 0x1A2 USBTXCSRL10 R/W 0x00 USB Transmit Control and Status Endpoint 10 Low 946 0x1A3 USBTXCSRH10 R/W 0x00 USB Transmit Control and Status Endpoint 10 High 951 886 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x1A4 USBRXMAXP10 R/W 0x0000 USB Maximum Receive Data Endpoint 10 955 0x1A6 USBRXCSRL10 R/W 0x00 USB Receive Control and Status Endpoint 10 Low 957 0x1A7 USBRXCSRH10 R/W 0x00 USB Receive Control and Status Endpoint 10 High 962 0x1A8 USBRXCOUNT10 RO 0x0000 USB Receive Byte Count Endpoint 10 967 0x1AA USBTXTYPE10 R/W 0x00 USB Host Transmit Configure Type Endpoint 10 969 0x1AB USBTXINTERVAL10 R/W 0x00 USB Host Transmit Interval Endpoint 10 971 0x1AC USBRXTYPE10 R/W 0x00 USB Host Configure Receive Type Endpoint 10 973 0x1AD USBRXINTERVAL10 R/W 0x00 USB Host Receive Polling Interval Endpoint 10 975 0x1B0 USBTXMAXP11 R/W 0x0000 USB Maximum Transmit Data Endpoint 11 935 0x1B2 USBTXCSRL11 R/W 0x00 USB Transmit Control and Status Endpoint 11 Low 946 0x1B3 USBTXCSRH11 R/W 0x00 USB Transmit Control and Status Endpoint 11 High 951 0x1B4 USBRXMAXP11 R/W 0x0000 USB Maximum Receive Data Endpoint 11 955 0x1B6 USBRXCSRL11 R/W 0x00 USB Receive Control and Status Endpoint 11 Low 957 0x1B7 USBRXCSRH11 R/W 0x00 USB Receive Control and Status Endpoint 11 High 962 0x1B8 USBRXCOUNT11 RO 0x0000 USB Receive Byte Count Endpoint 11 967 0x1BA USBTXTYPE11 R/W 0x00 USB Host Transmit Configure Type Endpoint 11 969 0x1BB USBTXINTERVAL11 R/W 0x00 USB Host Transmit Interval Endpoint 11 971 0x1BC USBRXTYPE11 R/W 0x00 USB Host Configure Receive Type Endpoint 11 973 0x1BD USBRXINTERVAL11 R/W 0x00 USB Host Receive Polling Interval Endpoint 11 975 0x1C0 USBTXMAXP12 R/W 0x0000 USB Maximum Transmit Data Endpoint 12 935 0x1C2 USBTXCSRL12 R/W 0x00 USB Transmit Control and Status Endpoint 12 Low 946 0x1C3 USBTXCSRH12 R/W 0x00 USB Transmit Control and Status Endpoint 12 High 951 0x1C4 USBRXMAXP12 R/W 0x0000 USB Maximum Receive Data Endpoint 12 955 0x1C6 USBRXCSRL12 R/W 0x00 USB Receive Control and Status Endpoint 12 Low 957 0x1C7 USBRXCSRH12 R/W 0x00 USB Receive Control and Status Endpoint 12 High 962 0x1C8 USBRXCOUNT12 RO 0x0000 USB Receive Byte Count Endpoint 12 967 0x1CA USBTXTYPE12 R/W 0x00 USB Host Transmit Configure Type Endpoint 12 969 0x1CB USBTXINTERVAL12 R/W 0x00 USB Host Transmit Interval Endpoint 12 971 0x1CC USBRXTYPE12 R/W 0x00 USB Host Configure Receive Type Endpoint 12 973 0x1CD USBRXINTERVAL12 R/W 0x00 USB Host Receive Polling Interval Endpoint 12 975 0x1D0 USBTXMAXP13 R/W 0x0000 USB Maximum Transmit Data Endpoint 13 935 0x1D2 USBTXCSRL13 R/W 0x00 USB Transmit Control and Status Endpoint 13 Low 946 July 22, 2011 887 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x1D3 USBTXCSRH13 R/W 0x00 USB Transmit Control and Status Endpoint 13 High 951 0x1D4 USBRXMAXP13 R/W 0x0000 USB Maximum Receive Data Endpoint 13 955 0x1D6 USBRXCSRL13 R/W 0x00 USB Receive Control and Status Endpoint 13 Low 957 0x1D7 USBRXCSRH13 R/W 0x00 USB Receive Control and Status Endpoint 13 High 962 0x1D8 USBRXCOUNT13 RO 0x0000 USB Receive Byte Count Endpoint 13 967 0x1DA USBTXTYPE13 R/W 0x00 USB Host Transmit Configure Type Endpoint 13 969 0x1DB USBTXINTERVAL13 R/W 0x00 USB Host Transmit Interval Endpoint 13 971 0x1DC USBRXTYPE13 R/W 0x00 USB Host Configure Receive Type Endpoint 13 973 0x1DD USBRXINTERVAL13 R/W 0x00 USB Host Receive Polling Interval Endpoint 13 975 0x1E0 USBTXMAXP14 R/W 0x0000 USB Maximum Transmit Data Endpoint 14 935 0x1E2 USBTXCSRL14 R/W 0x00 USB Transmit Control and Status Endpoint 14 Low 946 0x1E3 USBTXCSRH14 R/W 0x00 USB Transmit Control and Status Endpoint 14 High 951 0x1E4 USBRXMAXP14 R/W 0x0000 USB Maximum Receive Data Endpoint 14 955 0x1E6 USBRXCSRL14 R/W 0x00 USB Receive Control and Status Endpoint 14 Low 957 0x1E7 USBRXCSRH14 R/W 0x00 USB Receive Control and Status Endpoint 14 High 962 0x1E8 USBRXCOUNT14 RO 0x0000 USB Receive Byte Count Endpoint 14 967 0x1EA USBTXTYPE14 R/W 0x00 USB Host Transmit Configure Type Endpoint 14 969 0x1EB USBTXINTERVAL14 R/W 0x00 USB Host Transmit Interval Endpoint 14 971 0x1EC USBRXTYPE14 R/W 0x00 USB Host Configure Receive Type Endpoint 14 973 0x1ED USBRXINTERVAL14 R/W 0x00 USB Host Receive Polling Interval Endpoint 14 975 0x1F0 USBTXMAXP15 R/W 0x0000 USB Maximum Transmit Data Endpoint 15 935 0x1F2 USBTXCSRL15 R/W 0x00 USB Transmit Control and Status Endpoint 15 Low 946 0x1F3 USBTXCSRH15 R/W 0x00 USB Transmit Control and Status Endpoint 15 High 951 0x1F4 USBRXMAXP15 R/W 0x0000 USB Maximum Receive Data Endpoint 15 955 0x1F6 USBRXCSRL15 R/W 0x00 USB Receive Control and Status Endpoint 15 Low 957 0x1F7 USBRXCSRH15 R/W 0x00 USB Receive Control and Status Endpoint 15 High 962 0x1F8 USBRXCOUNT15 RO 0x0000 USB Receive Byte Count Endpoint 15 967 0x1FA USBTXTYPE15 R/W 0x00 USB Host Transmit Configure Type Endpoint 15 969 0x1FB USBTXINTERVAL15 R/W 0x00 USB Host Transmit Interval Endpoint 15 971 0x1FC USBRXTYPE15 R/W 0x00 USB Host Configure Receive Type Endpoint 15 973 0x1FD USBRXINTERVAL15 R/W 0x00 USB Host Receive Polling Interval Endpoint 15 975 888 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset Description 0x304 USBRQPKTCOUNT1 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 1 977 0x308 USBRQPKTCOUNT2 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 2 977 0x30C USBRQPKTCOUNT3 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 3 977 0x310 USBRQPKTCOUNT4 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 4 977 0x314 USBRQPKTCOUNT5 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 5 977 0x318 USBRQPKTCOUNT6 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 6 977 0x31C USBRQPKTCOUNT7 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 7 977 0x320 USBRQPKTCOUNT8 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 8 977 0x324 USBRQPKTCOUNT9 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 9 977 0x328 USBRQPKTCOUNT10 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 10 977 0x32C USBRQPKTCOUNT11 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 11 977 0x330 USBRQPKTCOUNT12 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 12 977 0x334 USBRQPKTCOUNT13 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 13 977 0x338 USBRQPKTCOUNT14 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 14 977 0x33C USBRQPKTCOUNT15 R/W 0x0000 USB Request Packet Count in Block Transfer Endpoint 15 977 0x340 USBRXDPKTBUFDIS R/W 0x0000 USB Receive Double Packet Buffer Disable 979 0x342 USBTXDPKTBUFDIS R/W 0x0000 USB Transmit Double Packet Buffer Disable 981 0x400 USBEPC R/W 0x0000.0000 USB External Power Control 983 0x404 USBEPCRIS RO 0x0000.0000 USB External Power Control Raw Interrupt Status 986 0x408 USBEPCIM R/W 0x0000.0000 USB External Power Control Interrupt Mask 987 0x40C USBEPCISC R/W 0x0000.0000 USB External Power Control Interrupt Status and Clear 988 0x410 USBDRRIS RO 0x0000.0000 USB Device RESUME Raw Interrupt Status 989 0x414 USBDRIM R/W 0x0000.0000 USB Device RESUME Interrupt Mask 990 0x418 USBDRISC W1C 0x0000.0000 USB Device RESUME Interrupt Status and Clear 991 July 22, 2011 889 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Table 18-6. Universal Serial Bus (USB) Controller Register Map (continued) See page Offset Name Type Reset 0x41C USBGPCS R/W 0x0000.0001 USB General-Purpose Control and Status 992 0x430 USBVDC R/W 0x0000.0000 USB VBUS Droop Control 993 0x434 USBVDCRIS RO 0x0000.0000 USB VBUS Droop Control Raw Interrupt Status 994 0x438 USBVDCIM R/W 0x0000.0000 USB VBUS Droop Control Interrupt Mask 995 0x43C USBVDCISC R/W 0x0000.0000 USB VBUS Droop Control Interrupt Status and Clear 996 0x444 USBIDVRIS RO 0x0000.0000 USB ID Valid Detect Raw Interrupt Status 997 0x448 USBIDVIM R/W 0x0000.0000 USB ID Valid Detect Interrupt Mask 998 0x44C USBIDVISC R/W1C 0x0000.0000 USB ID Valid Detect Interrupt Status and Clear 999 0x450 USBDMASEL R/W 0x0033.2211 USB DMA Select 1000 18.6 Description Register Descriptions The LM3S9L71 USB controller has On-The-Go (OTG) capabilities as specified in the USB0 bit field in the DC6 register (see page 253). OTG B / Device OTG A / Host OTG This icon indicates that the register is used in OTG B or Device mode. Some registers are used for both Host and Device mode and may have different bit definitions depending on the mode. This icon indicates that the register is used in OTG A or Host mode. Some registers are used for both Host and Device mode and may have different bit definitions depending on the mode. The USB controller is in OTG B or Device mode upon reset, so the reset values shown for these registers apply to the Device mode definition. This icon indicates that the register is used for OTG-specific functions such as ID detection and negotiation. Once OTG negotiation is complete, then the USB controller registers are used according to their Host or Device mode meanings depending on whether the OTG negotiations made the USB controller OTG A (Host) or OTG B (Device). 890 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 1: USB Device Functional Address (USBFADDR), offset 0x000 OTG B / Device USBFADDR is an 8-bit register that contains the 7-bit address of the Device part of the transaction. When the USB controller is being used in Device mode (the HOST bit in the USBDEVCTL register is clear), this register must be written with the address received through a SET_ADDRESS command, which is then used for decoding the function address in subsequent token packets. Important: See the section called “Setting the Device Address” on page 870 for special considerations when writing this register. USB Device Functional Address (USBFADDR) Base 0x4005.0000 Offset 0x000 Type R/W, reset 0x00 7 6 5 4 Type Reset RO 0 3 2 1 0 R/W 0 R/W 0 R/W 0 FUNCADDR reserved R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 FUNCADDR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Function Address Function Address of Device as received through SET_ADDRESS. July 22, 2011 891 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 2: USB Power (USBPOWER), offset 0x001 OTG A / USBPOWER is an 8-bit register used for controlling SUSPEND and RESUME signaling and some basic operational aspects of the USB controller. Host OTG B / Device OTG A / Host Mode USB Power (USBPOWER) Base 0x4005.0000 Offset 0x001 Type R/W, reset 0x20 7 6 5 4 reserved Type Reset RO 0 RO 0 3 2 RESET RO 1 RO 0 1 0 RESUME SUSPEND PWRDNPHY R/W 0 R/W 0 R/W1S 0 Bit/Field Name Type Reset 7:4 reserved RO 0x2 3 RESET R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RESET Signaling Value Description 2 RESUME R/W 0 1 Enables RESET signaling on the bus. 0 Ends RESET signaling on the bus. RESUME Signaling Value Description 1 Enables RESUME signaling when the Device is in SUSPEND mode. 0 Ends RESUME signaling on the bus. This bit must be cleared by software 20 ms after being set. 1 SUSPEND R/W1S 0 SUSPEND Mode Value Description 1 Enables SUSPEND mode. 0 No effect. 892 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 PWRDNPHY R/W 0 Description Power Down PHY Value Description 1 Powers down the internal USB PHY. 0 No effect. OTG B / Device Mode USB Power (USBPOWER) Base 0x4005.0000 Offset 0x001 Type R/W, reset 0x20 Type Reset 7 6 ISOUP SOFTCONN R/W 0 R/W 0 5 4 reserved RO 1 RO 0 3 2 RESET 1 0 RESUME SUSPEND PWRDNPHY RO 0 R/W 0 RO 0 Bit/Field Name Type Reset 7 ISOUP R/W 0 R/W 0 Description Isochronous Update Value Description 1 The USB controller waits for an SOF token from the time the TXRDY bit is set in the USBTXCSRLn register before sending the packet. If an IN token is received before an SOF token, then a zero-length data packet is sent. 0 No effect. Note: 6 SOFTCONN R/W 0 This bit is only valid for isochronous transfers. Soft Connect/Disconnect Value Description 5:4 reserved RO 0x2 3 RESET RO 0 1 The USB D+/D- lines are enabled. 0 The USB D+/D- lines are tri-stated. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RESET Signaling Value Description 1 RESET signaling is present on the bus. 0 RESET signaling is not present on the bus. July 22, 2011 893 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 2 RESUME R/W 0 Description RESUME Signaling Value Description 1 Enables RESUME signaling when the Device is in SUSPEND mode. 0 Ends RESUME signaling on the bus. This bit must be cleared by software 10 ms (a maximum of 15 ms) after being set. 1 SUSPEND RO 0 SUSPEND Mode Value Description 0 PWRDNPHY R/W 0 1 The USB controller is in SUSPEND mode. 0 This bit is cleared when software reads the interrupt register or sets the RESUME bit above. Power Down PHY Value Description 1 Powers down the internal USB PHY. 0 No effect. 894 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 3: USB Transmit Interrupt Status (USBTXIS), offset 0x002 Important: This register is read-sensitive. See the register description for details. OTG B / USBTXIS is a 16-bit read-only register that indicates which interrupts are currently active for endpoint 0 and the transmit endpoints 1–15. The meaning of the EPn bits in this register is based on the mode of the device. The EP1 through EP15 bits always indicate that the USB controller is sending data; however, in Host mode, the bits refer to OUT endpoints; while in Device mode, the bits refer to IN endpoints. The EP0 bit is special in Host and Device modes and indicates that either a control IN or control OUT endpoint has generated an interrupt. Device Note: OTG A / Host Bits relating to endpoints that have not been configured always return 0. Note also that all active interrupts are cleared when this register is read. USB Transmit Interrupt Status (USBTXIS) Base 0x4005.0000 Offset 0x002 Type RO, reset 0x0000 Type Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 15 EP15 RO 0 Description TX Endpoint 15 Interrupt Value Description 14 EP14 RO 0 0 No interrupt. 1 The Endpoint 15 transmit interrupt is asserted. TX Endpoint 14 Interrupt Same description as EP15. 13 EP13 RO 0 TX Endpoint 13 Interrupt Same description as EP15. 12 EP12 RO 0 TX Endpoint 12 Interrupt Same description as EP15. 11 EP11 RO 0 TX Endpoint 11 Interrupt Same description as EP15. 10 EP10 RO 0 TX Endpoint 10 Interrupt Same description as EP15. 9 EP9 RO 0 TX Endpoint 9 Interrupt Same description as EP15. 8 EP8 RO 0 TX Endpoint 8 Interrupt Same description as EP15. 7 EP7 RO 0 TX Endpoint 7 Interrupt Same description as EP15. July 22, 2011 895 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 6 EP6 RO 0 Description TX Endpoint 6 Interrupt Same description as EP15. 5 EP5 RO 0 TX Endpoint 5 Interrupt Same description as EP15. 4 EP4 RO 0 TX Endpoint 4 Interrupt Same description as EP15. 3 EP3 RO 0 TX Endpoint 3 Interrupt Same description as EP15. 2 EP2 RO 0 TX Endpoint 2 Interrupt Same description as EP15. 1 EP1 RO 0 TX Endpoint 1 Interrupt Same description as EP15. 0 EP0 RO 0 TX and RX Endpoint 0 Interrupt Value Description 0 No interrupt. 1 The Endpoint 0 transmit and receive interrupt is asserted. 896 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: USB Receive Interrupt Status (USBRXIS), offset 0x004 Important: This register is read-sensitive. See the register description for details. OTG A / USBRXIS is a 16-bit read-only register that indicates which of the interrupts for receive endpoints 1–15 are currently active. Host Note: OTG B / Device Type Reset Bits relating to endpoints that have not been configured always return 0. Note also that all active interrupts are cleared when this register is read. USB Receive Interrupt Status (USBRXIS) Base 0x4005.0000 Offset 0x004 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 15 EP15 RO 0 Description RX Endpoint 15 Interrupt Value Description 14 EP14 RO 0 0 No interrupt. 1 The Endpoint 15 receive interrupt is asserted. RX Endpoint 14 Interrupt Same description as EP15. 13 EP13 RO 0 RX Endpoint 13 Interrupt Same description as EP15. 12 EP12 RO 0 RX Endpoint 12 Interrupt Same description as EP15. 11 EP11 RO 0 RX Endpoint 11 Interrupt Same description as EP15. 10 EP10 RO 0 RX Endpoint 10 Interrupt Same description as EP15. 9 EP9 RO 0 RX Endpoint 9 Interrupt Same description as EP15. 8 EP8 RO 0 RX Endpoint 8 Interrupt Same description as EP15. 7 EP7 RO 0 RX Endpoint 7 Interrupt Same description as EP15. 6 EP6 RO 0 RX Endpoint 6 Interrupt Same description as EP15. July 22, 2011 897 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 5 EP5 RO 0 Description RX Endpoint 5 Interrupt Same description as EP15. 4 EP4 RO 0 RX Endpoint 4 Interrupt Same description as EP15. 3 EP3 RO 0 RX Endpoint 3 Interrupt Same description as EP15. 2 EP2 RO 0 RX Endpoint 2 Interrupt Same description as EP15. 1 EP1 RO 0 RX Endpoint 1 Interrupt Same description as EP15. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 898 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 5: USB Transmit Interrupt Enable (USBTXIE), offset 0x006 OTG A / Host USBTXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBTXIS register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the corresponding interrupt bit in the USBTXIS register is set. When a bit is cleared, the interrupt in the USBTXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset, all interrupts are enabled. OTG B / Device USB Transmit Interrupt Enable (USBTXIE) Base 0x4005.0000 Offset 0x006 Type R/W, reset 0xFFFF Type Reset 15 14 13 12 11 10 9 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset 15 EP15 R/W 1 8 7 6 5 4 3 2 1 0 Description TX Endpoint 15 Interrupt Enable Value Description 14 EP14 R/W 1 1 An interrupt is sent to the interrupt controller when the EP15 bit in the USBTXIS register is set. 0 The EP15 transmit interrupt is suppressed and not sent to the interrupt controller. TX Endpoint 14 Interrupt Enable Same description as EP15. 13 EP13 R/W 1 TX Endpoint 13 Interrupt Enable Same description as EP15. 12 EP12 R/W 1 TX Endpoint 12 Interrupt Enable Same description as EP15. 11 EP11 R/W 1 TX Endpoint 11 Interrupt Enable Same description as EP15. 10 EP10 R/W 1 TX Endpoint 10 Interrupt Enable Same description as EP15. 9 EP9 R/W 1 TX Endpoint 9 Interrupt Enable Same description as EP15. 8 EP8 R/W 1 TX Endpoint 8 Interrupt Enable Same description as EP15. 7 EP7 R/W 1 TX Endpoint 7 Interrupt Enable Same description as EP15. 6 EP6 R/W 1 TX Endpoint 6 Interrupt Enable Same description as EP15. July 22, 2011 899 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 5 EP5 R/W 1 Description TX Endpoint 5 Interrupt Enable Same description as EP15. 4 EP4 R/W 1 TX Endpoint 4 Interrupt Enable Same description as EP15. 3 EP3 R/W 1 TX Endpoint 3 Interrupt Enable Same description as EP15. 2 EP2 R/W 1 TX Endpoint 2 Interrupt Enable Same description as EP15. 1 EP1 R/W 1 TX Endpoint 1 Interrupt Enable Same description as EP15. 0 EP0 R/W 1 TX and RX Endpoint 0 Interrupt Enable Value Description 1 An interrupt is sent to the interrupt controller when the EP0 bit in the USBTXIS register is set. 0 The EP0 transmit and receive interrupt is suppressed and not sent to the interrupt controller. 900 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 6: USB Receive Interrupt Enable (USBRXIE), offset 0x008 OTG A / Host USBRXIE is a 16-bit register that provides interrupt enable bits for the interrupts in the USBRXIS register. When a bit is set, the USB interrupt is asserted to the interrupt controller when the corresponding interrupt bit in the USBRXIS register is set. When a bit is cleared, the interrupt in the USBRXIS register is still set but the USB interrupt to the interrupt controller is not asserted. On reset, all interrupts are enabled. OTG B / Device USB Receive Interrupt Enable (USBRXIE) Base 0x4005.0000 Offset 0x008 Type R/W, reset 0xFFFE Type Reset 15 14 13 12 11 10 9 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EP4 EP3 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field Name Type Reset 15 EP15 R/W 1 8 7 6 5 4 3 2 1 0 EP2 EP1 reserved R/W 1 R/W 1 RO 0 Description RX Endpoint 15 Interrupt Enable Value Description 14 EP14 R/W 1 1 An interrupt is sent to the interrupt controller when the EP15 bit in the USBRXIS register is set. 0 The EP15 receive interrupt is suppressed and not sent to the interrupt controller. RX Endpoint 14 Interrupt Enable Same description as EP15. 13 EP13 R/W 1 RX Endpoint 13 Interrupt Enable Same description as EP15. 12 EP12 R/W 1 RX Endpoint 12 Interrupt Enable Same description as EP15. 11 EP11 R/W 1 RX Endpoint 11 Interrupt Enable Same description as EP15. 10 EP10 R/W 1 RX Endpoint 10 Interrupt Enable Same description as EP15. 9 EP9 R/W 1 RX Endpoint 9 Interrupt Enable Same description as EP15. 8 EP8 R/W 1 RX Endpoint 8 Interrupt Enable Same description as EP15. 7 EP7 R/W 1 RX Endpoint 7 Interrupt Enable Same description as EP15. 6 EP6 R/W 1 RX Endpoint 6 Interrupt Enable Same description as EP15. July 22, 2011 901 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 5 EP5 R/W 1 Description RX Endpoint 5 Interrupt Enable Same description as EP15. 4 EP4 R/W 1 RX Endpoint 4 Interrupt Enable Same description as EP15. 3 EP3 R/W 1 RX Endpoint 3 Interrupt Enable Same description as EP15. 2 EP2 R/W 1 RX Endpoint 2 Interrupt Enable Same description as EP15. 1 EP1 R/W 1 RX Endpoint 1 Interrupt Enable Same description as EP15. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 902 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 7: USB General Interrupt Status (USBIS), offset 0x00A Important: This register is read-sensitive. See the register description for details. OTG A / USBIS is an 8-bit read-only register that indicates which USB interrupts are currently active. All active interrupts are cleared when this register is read. Host OTG B / Device OTG A / Host Mode USB General Interrupt Status (USBIS) Base 0x4005.0000 Offset 0x00A Type RO, reset 0x00 7 6 5 VBUSERR SESREQ DISCON Type Reset RO 0 RO 0 4 3 CONN SOF RO 0 RO 0 RO 0 2 1 BABBLE RESUME RO 0 RO 0 0 reserved RO 0 Bit/Field Name Type Reset Description 7 VBUSERR RO 0 VBUS Error Value Description 6 SESREQ RO 0 1 VBUS has dropped below the VBUS Valid threshold during a session. 0 No interrupt. SESSION REQUEST Value Description 5 DISCON RO 0 1 SESSION REQUEST signaling has been detected. 0 No interrupt. Session Disconnect Value Description 4 CONN RO 0 1 A Device disconnect has been detected. 0 No interrupt. Session Connect Value Description 1 A Device connection has been detected. 0 No interrupt. July 22, 2011 903 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 3 SOF RO 0 Description Start of Frame Value Description 2 BABBLE RO 0 1 A new frame has started. 0 No interrupt. Babble Detected Value Description 1 RESUME RO 0 1 Babble has been detected. This interrupt is active only after the first SOF has been sent. 0 No interrupt. RESUME Signaling Detected Value Description 1 RESUME signaling has been detected on the bus while the USB controller is in SUSPEND mode. 0 No interrupt. This interrupt can only be used if the USB controller's system clock is enabled. If the user disables the clock programming, the USBDRRIS, USBDRIM, and USBDRISC registers should be used. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 0 OTG B / Device Mode USB General Interrupt Status (USBIS) Base 0x4005.0000 Offset 0x00A Type RO, reset 0x00 7 6 reserved Type Reset RO 0 RO 0 5 4 3 2 DISCON reserved SOF RESET RO 0 RO 0 RO 0 RO 0 RESUME SUSPEND RO 0 Bit/Field Name Type Reset 7:6 reserved RO 0x0 5 DISCON RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Session Disconnect Value Description 1 The device has been disconnected from the host. 0 No interrupt. 904 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 SOF RO 0 Start of Frame Value Description 2 RESET RO 0 1 A new frame has started. 0 No interrupt. RESET Signaling Detected Value Description 1 RESUME RO 0 1 RESET signaling has been detected on the bus. 0 No interrupt. RESUME Signaling Detected Value Description 1 RESUME signaling has been detected on the bus while the USB controller is in SUSPEND mode. 0 No interrupt. This interrupt can only be used if the USB controller's system clock is enabled. If the user disables the clock programming, the USBDRRIS, USBDRIM, and USBDRISC registers should be used. 0 SUSPEND RO 0 SUSPEND Signaling Detected Value Description 1 SUSPEND signaling has been detected on the bus. 0 No interrupt. July 22, 2011 905 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 8: USB Interrupt Enable (USBIE), offset 0x00B OTG A / USBIE is an 8-bit register that provides interrupt enable bits for each of the interrupts in USBIS. At reset interrupts 1 and 2 are enabled in Device mode. Host OTG B / Device OTG A / Host Mode USB Interrupt Enable (USBIE) Base 0x4005.0000 Offset 0x00B Type R/W, reset 0x06 7 6 5 VBUSERR SESREQ DISCON Type Reset R/W 0 R/W 0 4 3 CONN SOF R/W 0 R/W 0 R/W 0 2 1 BABBLE RESUME R/W 1 R/W 1 Bit/Field Name Type Reset 7 VBUSERR R/W 0 0 reserved RO 0 Description Enable VBUS Error Interrupt Value Description 6 SESREQ R/W 0 1 An interrupt is sent to the interrupt controller when the VBUSERR bit in the USBIS register is set. 0 The VBUSERR interrupt is suppressed and not sent to the interrupt controller. Enable Session Request Value Description 5 DISCON R/W 0 1 An interrupt is sent to the interrupt controller when the SESREEQ bit in the USBIS register is set. 0 The SESREQ interrupt is suppressed and not sent to the interrupt controller. Enable Disconnect Interrupt Value Description 1 An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set. 0 The DISCON interrupt is suppressed and not sent to the interrupt controller. 906 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 4 CONN R/W 0 Description Enable Connect Interrupt Value Description 3 SOF R/W 0 1 An interrupt is sent to the interrupt controller when the CONN bit in the USBIS register is set. 0 The CONN interrupt is suppressed and not sent to the interrupt controller. Enable Start-of-Frame Interrupt Value Description 2 BABBLE R/W 1 1 An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set. 0 The SOF interrupt is suppressed and not sent to the interrupt controller. Enable Babble Interrupt Value Description 1 RESUME R/W 1 1 An interrupt is sent to the interrupt controller when the BABBLE bit in the USBIS register is set. 0 The BABBLE interrupt is suppressed and not sent to the interrupt controller. Enable RESUME Interrupt Value Description 0 reserved RO 1 An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set. 0 The RESUME interrupt is suppressed and not sent to the interrupt controller. 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 0 OTG B / Device Mode USB Interrupt Enable (USBIE) Base 0x4005.0000 Offset 0x00B Type R/W, reset 0x06 7 6 reserved Type Reset RO 0 RO 0 5 4 3 2 DISCON reserved SOF RESET R/W 0 RO 0 R/W 0 R/W 1 RESUME SUSPEND R/W 1 R/W 0 July 22, 2011 907 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 7:6 reserved RO 0x0 5 DISCON R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable Disconnect Interrupt Value Description 1 An interrupt is sent to the interrupt controller when the DISCON bit in the USBIS register is set. 0 The DISCON interrupt is suppressed and not sent to the interrupt controller. 4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 SOF R/W 0 Enable Start-of-Frame Interrupt Value Description 2 RESET R/W 1 1 An interrupt is sent to the interrupt controller when the SOF bit in the USBIS register is set. 0 The SOF interrupt is suppressed and not sent to the interrupt controller. Enable RESET Interrupt Value Description 1 RESUME R/W 1 1 An interrupt is sent to the interrupt controller when the RESET bit in the USBIS register is set. 0 The RESET interrupt is suppressed and not sent to the interrupt controller. Enable RESUME Interrupt Value Description 0 SUSPEND R/W 0 1 An interrupt is sent to the interrupt controller when the RESUME bit in the USBIS register is set. 0 The RESUME interrupt is suppressed and not sent to the interrupt controller. Enable SUSPEND Interrupt Value Description 1 An interrupt is sent to the interrupt controller when the SUSPEND bit in the USBIS register is set. 0 The SUSPEND interrupt is suppressed and not sent to the interrupt controller. 908 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 9: USB Frame Value (USBFRAME), offset 0x00C OTG A / Host USBFRAME is a 16-bit read-only register that holds the last received frame number. USB Frame Value (USBFRAME) Base 0x4005.0000 Offset 0x00C Type RO, reset 0x0000 OTG B / 15 14 RO 0 RO 0 Device 13 12 11 10 9 8 7 6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 FRAME Bit/Field Name Type Reset 15:11 reserved RO 0x0 10:0 FRAME RO 0x000 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Frame Number July 22, 2011 909 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 10: USB Endpoint Index (USBEPIDX), offset 0x00E OTG A / Host Each endpoint's buffer can be accessed by configuring a FIFO size and starting address. The USBEPIDX 8-bit register is used with the USBTXFIFOSZ, USBRXFIFOSZ, USBTXFIFOADD, and USBRXFIFOADD registers. USB Endpoint Index (USBEPIDX) OTG B / Device Base 0x4005.0000 Offset 0x00E Type R/W, reset 0x00 7 6 RO 0 RO 0 5 4 3 2 RO 0 R/W 0 R/W 0 reserved Type Reset RO 0 1 0 R/W 0 R/W 0 EPIDX Bit/Field Name Type Reset Description 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 EPIDX R/W 0x0 Endpoint Index This bit field configures which endpoint is accessed when reading or writing to one of the USB controller's indexed registers. A value of 0x0 corresponds to Endpoint 0 and a value of 0xF corresponds to Endpoint 15. 910 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 11: USB Test Mode (USBTEST), offset 0x00F OTG A / Host USBTEST is an 8-bit register that is primarily used to put the USB controller into one of the four test modes for operation described in the USB 2.0 Specification, in response to a SET FEATURE: USBTESTMODE command. This register is not used in normal operation. Note: Only one of these bits should be set at any time. OTG B / Device OTG A / Host Mode USB Test Mode (USBTEST) Base 0x4005.0000 Offset 0x00F Type R/W, reset 0x00 7 6 5 4 3 FORCEH FIFOACC FORCEFS Type Reset R/W 0 R/W1S 0 R/W 0 2 1 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset 7 FORCEH R/W 0 Description Force Host Mode Value Description 1 Forces the USB controller to enter Host mode when the SESSION bit is set, regardless of whether the USB controller is connected to any peripheral. The state of the USB0DP and USB0DM signals is ignored. The USB controller then remains in Host mode until the SESSION bit is cleared, even if a Device is disconnected. If the FORCEH bit remains set, the USB controller re-enters Host mode the next time the SESSION bit is set. 0 No effect. While in this mode, status of the bus connection may be read using the DEV bit of the USBDEVCTL register. The operating speed is determined from the FORCEFS bit. 6 FIFOACC R/W1S 0 FIFO Access Value Description 1 Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO. 0 No effect. This bit is cleared automatically. 5 FORCEFS R/W 0 Force Full-Speed Mode Value Description 1 Forces the USB controller into Full-Speed mode upon receiving a USB RESET. 0 The USB controller operates at Low Speed. July 22, 2011 911 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 4:0 reserved RO 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. OTG B / Device Mode USB Test Mode (USBTEST) Base 0x4005.0000 Offset 0x00F Type R/W, reset 0x00 7 reserved Type Reset RO 0 6 5 4 3 FIFOACC FORCEFS R/W1S 0 R/W 0 2 1 0 RO 0 RO 0 reserved RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 FIFOACC R/W1S 0 FIFO Access Value Description 1 Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO. 0 No effect. This bit is cleared automatically. 5 FORCEFS R/W 0 Force Full-Speed Mode Value Description 4:0 reserved RO 0x0 1 Forces the USB controller into Full-Speed mode upon receiving a USB RESET. 0 The USB controller operates at Low Speed. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 912 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 Register 13: USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 Register 14: USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 Register 15: USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C Register 16: USB FIFO Endpoint 4 (USBFIFO4), offset 0x030 Register 17: USB FIFO Endpoint 5 (USBFIFO5), offset 0x034 Register 18: USB FIFO Endpoint 6 (USBFIFO6), offset 0x038 Register 19: USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C Register 20: USB FIFO Endpoint 8 (USBFIFO8), offset 0x040 Register 21: USB FIFO Endpoint 9 (USBFIFO9), offset 0x044 Register 22: USB FIFO Endpoint 10 (USBFIFO10), offset 0x048 Register 23: USB FIFO Endpoint 11 (USBFIFO11), offset 0x04C Register 24: USB FIFO Endpoint 12 (USBFIFO12), offset 0x050 Register 25: USB FIFO Endpoint 13 (USBFIFO13), offset 0x054 Register 26: USB FIFO Endpoint 14 (USBFIFO14), offset 0x058 Register 27: USB FIFO Endpoint 15 (USBFIFO15), offset 0x05C Important: This register is read-sensitive. See the register description for details. OTG A / Host OTG B / Device These 32-bit registers provide an address for CPU access to the FIFOs for each endpoint. Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint. Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint. Transfers to and from FIFOs may be 8-bit, 16-bit or 32-bit as required, and any combination of accesses is allowed provided the data accessed is contiguous. All transfers associated with one packet must be of the same width so that the data is consistently byte-, halfword- or word-aligned. However, the last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer. Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support either single-packet or double-packet buffering (see the section called “Single-Packet Buffering” on page 868). Burst writing of multiple packets is not supported as flags must be set after each packet is written. Following a STALL response or a transmit error on endpoint 1–15, the associated FIFO is completely flushed. July 22, 2011 913 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB FIFO Endpoint 0 (USBFIFO0) Base 0x4005.0000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 EPDATA Type Reset EPDATA Type Reset Bit/Field Name Type 31:0 EPDATA R/W Reset Description 0x0000.0000 Endpoint Data Writing to this register loads the data into the Transmit FIFO and reading unloads data from the Receive FIFO. 914 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 28: USB Device Control (USBDEVCTL), offset 0x060 OTG A / Host USBDEVCTL is an 8-bit register used for controlling and monitoring the USB VBUS line. If the PHY is suspended, no PHY clock is received and the VBUS is not sampled. In addition, in Host mode, USBDEVCTL provides the status information for the current operating mode (Host or Device) of the USB controller. If the USB controller is in Host mode, this register also indicates if a full- or low-speed Device has been connected. USB Device Control (USBDEVCTL) Base 0x4005.0000 Offset 0x060 Type R/W, reset 0x80 Type Reset 7 6 5 4 DEV FSDEV LSDEV RO 1 RO 0 RO 0 3 2 VBUS RO 0 HOST RO 0 RO 0 1 0 HOSTREQ SESSION R/W 0 Bit/Field Name Type Reset 7 DEV RO 1 R/W 0 Description Device Mode Value Description 0 The USB controller is operating on the OTG A side of the cable. 1 The USB controller is operating on the OTG B side of the cable. Note: 6 FSDEV RO 0 This value is only valid while a session is in progress. Full-Speed Device Detected Value Description 5 LSDEV RO 0 0 A full-speed Device has not been detected on the port. 1 A full-speed Device has been detected on the port. Low-Speed Device Detected Value Description 4:3 VBUS RO 0x0 0 A low-speed Device has not been detected on the port. 1 A low-speed Device has been detected on the port. VBUS Level Value Description 0x0 Below SessionEnd VBUS is detected as under 0.5 V. 0x1 Above SessionEnd, below AValid VBUS is detected as above 0.5 V and under 1.5 V. 0x2 Above AValid, below VBUSValid VBUS is detected as above 1.5 V and below 4.75 V. 0x3 Above VBUSValid VBUS is detected as above 4.75 V. July 22, 2011 915 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset Description 2 HOST RO 0 Host Mode Value Description 0 The USB controller is acting as a Device. 1 The USB controller is acting as a Host. Note: 1 HOSTREQ R/W 0 This value is only valid while a session is in progress. Host Request Value Description 0 No effect. 1 Initiates the Host Negotiation when SUSPEND mode is entered. This bit is cleared when Host Negotiation is completed. 0 SESSION R/W 0 Session Start/End When operating as an OTG A device: Value Description 0 When cleared by software, this bit ends a session. 1 When set by software, this bit starts a session. When operating as an OTG B device: Value Description 0 The USB controller has ended a session. When the USB controller is in SUSPEND mode, this bit may be cleared by software to perform a software disconnect. 1 The USB controller has started a session. When set by software, the Session Request Protocol is initiated. Note: Clearing this bit when the USB controller is not suspended results in undefined behavior. 916 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 29: USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 Register 30: USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 OTG A / Host These 8-bit registers allow the selected TX/RX endpoint FIFOs to be dynamically sized. USBEPIDX is used to configure each transmit endpoint's FIFO size. USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) OTG B / Base 0x4005.0000 Offset 0x062 Type R/W, reset 0x00 Device 7 6 5 reserved Type Reset RO 0 RO 0 4 3 2 R/W 0 R/W 0 DPB RO 0 R/W 0 1 0 R/W 0 R/W 0 SIZE Bit/Field Name Type Reset 7:5 reserved RO 0x0 4 DPB R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Double Packet Buffer Support Value Description 3:0 SIZE R/W 0x0 0 Only single-packet buffering is supported. 1 Double-packet buffering is supported. Max Packet Size Maximum packet size to be allowed. If DPB = 0, the FIFO also is this size; if DPB = 1, the FIFO is twice this size. Value Packet Size (Bytes) 0x0 8 0x1 16 0x2 32 0x3 64 0x4 128 0x5 256 0x6 512 0x7 1024 0x8 2048 0x9-0xF Reserved July 22, 2011 917 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 31: USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 Register 32: USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 OTG A / Host OTG B / USBTXFIFOADD and USBRXFIFOADD are 16-bit registers that control the start address of the selected transmit and receive endpoint FIFOs. USB Transmit FIFO Start Address (USBTXFIFOADD) Base 0x4005.0000 Offset 0x064 Type R/W, reset 0x0000 Device 15 14 13 RO 0 RO 0 RO 0 12 11 10 9 8 7 6 5 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 ADDR R/W 0 Bit/Field Name Type Reset Description 15:9 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8:0 ADDR R/W 0x00 Transmit/Receive Start Address Start address of the endpoint FIFO. Value Start Address 0x0 0 0x1 8 0x2 16 0x3 24 0x4 32 0x5 40 0x6 48 0x7 56 0x8 64 ... ... 0x1FF 4095 918 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 33: USB Connect Timing (USBCONTIM), offset 0x07A OTG A / Host This 8-bit configuration register specifies connection and negotiation delays. USB Connect Timing (USBCONTIM) Base 0x4005.0000 Offset 0x07A Type R/W, reset 0x5C OTG B / 7 6 R/W 0 R/W 1 Device 5 4 3 2 R/W 1 R/W 1 R/W 1 WTCON Type Reset R/W 0 1 0 R/W 0 R/W 0 WTID Bit/Field Name Type Reset 7:4 WTCON R/W 0x5 Description Connect Wait This field configures the wait required to allow for the user’s connect/disconnect filter, in units of 533.3 ns. The default corresponds to 2.667 µs. 3:0 WTID R/W 0xC Wait ID This field configures the delay required from the enable of the ID detection to when the ID value is valid, in units of 4.369 ms. The default corresponds to 52.43 ms. July 22, 2011 919 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 34: USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B This 8-bit configuration register specifies the duration of the VBUS pulsing charge. OTG USB OTG VBUS Pulse Timing (USBVPLEN) Base 0x4005.0000 Offset 0x07B Type R/W, reset 0x3C 7 6 5 4 R/W 0 R/W 0 R/W 1 R/W 1 3 2 1 0 R/W 1 R/W 1 R/W 0 R/W 0 VPLEN Type Reset Bit/Field Name Type Reset Description 7:0 VPLEN R/W 0x3C VBUS Pulse Length This field configures the duration of the VBUS pulsing charge in units of 546.1 µs. The default corresponds to 32.77 ms. 920 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 35: USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D OTG A / Host OTG B / This 8-bit configuration register specifies the minimum time gap allowed between the start of the last transaction and the EOF for full-speed transactions. USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF) Base 0x4005.0000 Offset 0x07D Type R/W, reset 0x77 Device 7 6 5 4 3 2 1 0 R/W 1 R/W 1 R/W 1 FSEOFG Type Reset R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 Bit/Field Name Type Reset Description 7:0 FSEOFG R/W 0x77 Full-Speed End-of-Frame Gap This field is used during full-speed transactions to configure the gap between the last transaction and the End-of-Frame (EOF), in units of 533.3 ns. The default corresponds to 63.46 µs. July 22, 2011 921 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 36: USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E OTG A / Host OTG B / This 8-bit configuration register specifies the minimum time gap that is to be allowed between the start of the last transaction and the EOF for low-speed transactions. USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF) Base 0x4005.0000 Offset 0x07E Type R/W, reset 0x72 Device 7 6 5 4 3 2 1 0 R/W 0 R/W 1 R/W 0 LSEOFG Type Reset R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 Bit/Field Name Type Reset Description 7:0 LSEOFG R/W 0x72 Low-Speed End-of-Frame Gap This field is used during low-speed transactions to set the gap between the last transaction and the End-of-Frame (EOF), in units of 1.067 µs. The default corresponds to 121.6 µs. 922 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 37: USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 Register 38: USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 Register 39: USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 Register 40: USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 Register 41: USB Transmit Functional Address Endpoint 4 (USBTXFUNCADDR4), offset 0x0A0 Register 42: USB Transmit Functional Address Endpoint 5 (USBTXFUNCADDR5), offset 0x0A8 Register 43: USB Transmit Functional Address Endpoint 6 (USBTXFUNCADDR6), offset 0x0B0 Register 44: USB Transmit Functional Address Endpoint 7 (USBTXFUNCADDR7), offset 0x0B8 Register 45: USB Transmit Functional Address Endpoint 8 (USBTXFUNCADDR8), offset 0x0C0 Register 46: USB Transmit Functional Address Endpoint 9 (USBTXFUNCADDR9), offset 0x0C8 Register 47: USB Transmit Functional Address Endpoint 10 (USBTXFUNCADDR10), offset 0x0D0 Register 48: USB Transmit Functional Address Endpoint 11 (USBTXFUNCADDR11), offset 0x0D8 Register 49: USB Transmit Functional Address Endpoint 12 (USBTXFUNCADDR12), offset 0x0E0 Register 50: USB Transmit Functional Address Endpoint 13 (USBTXFUNCADDR13), offset 0x0E8 Register 51: USB Transmit Functional Address Endpoint 14 (USBTXFUNCADDR14), offset 0x0F0 Register 52: USB Transmit Functional Address Endpoint 15 (USBTXFUNCADDR15), offset 0x0F8 OTG A / Host USBTXFUNCADDRn is an 8-bit read/write register that records the address of the target function to be accessed through the associated endpoint (EPn). USBTXFUNCADDRn must be defined for each transmit endpoint that is used. Note: USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0. July 22, 2011 923 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0) Base 0x4005.0000 Offset 0x080 Type R/W, reset 0x00 7 6 5 4 R/W 0 R/W 0 R/W 0 RO 0 2 1 0 R/W 0 R/W 0 R/W 0 ADDR reserved Type Reset 3 R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 ADDR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Address Specifies the USB bus address for the target Device. 924 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 53: USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 Register 54: USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A Register 55: USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 Register 56: USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A Register 57: USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4), offset 0x0A2 Register 58: USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5), offset 0x0AA Register 59: USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6), offset 0x0B2 Register 60: USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7), offset 0x0BA Register 61: USB Transmit Hub Address Endpoint 8 (USBTXHUBADDR8), offset 0x0C2 Register 62: USB Transmit Hub Address Endpoint 9 (USBTXHUBADDR9), offset 0x0CA Register 63: USB Transmit Hub Address Endpoint 10 (USBTXHUBADDR10), offset 0x0D2 Register 64: USB Transmit Hub Address Endpoint 11 (USBTXHUBADDR11), offset 0x0DA Register 65: USB Transmit Hub Address Endpoint 12 (USBTXHUBADDR12), offset 0x0E2 Register 66: USB Transmit Hub Address Endpoint 13 (USBTXHUBADDR13), offset 0x0EA Register 67: USB Transmit Hub Address Endpoint 14 (USBTXHUBADDR14), offset 0x0F2 Register 68: USB Transmit Hub Address Endpoint 15 (USBTXHUBADDR15), offset 0x0FA OTG A / Host USBTXHUBADDRn is an 8-bit read/write register that, like USBTXHUBPORTn, only must be written when a USB Device is connected to transmit endpoint EPn via a USB 2.0 hub. This register records the address of the USB 2.0 hub through which the target associated with the endpoint is accessed. Note: USBTXHUBADDR0 is used for both receive and transmit for endpoint 0. July 22, 2011 925 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0) Base 0x4005.0000 Offset 0x082 Type R/W, reset 0x00 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 2 1 0 R/W 0 R/W 0 R/W 0 ADDR MULTTRAN Type Reset 3 R/W 0 Bit/Field Name Type Reset 7 MULTTRAN R/W 0 Description Multiple Translators Value Description 6:0 ADDR R/W 0x00 0 Clear to indicate that the hub has a single transaction translator. 1 Set to indicate that the hub has multiple transaction translators. Hub Address This field specifies the USB bus address for the USB 2.0 hub. 926 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 69: USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 Register 70: USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B Register 71: USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 Register 72: USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B Register 73: USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset 0x0A3 Register 74: USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset 0x0AB Register 75: USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset 0x0B3 Register 76: USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset 0x0BB Register 77: USB Transmit Hub Port Endpoint 8 (USBTXHUBPORT8), offset 0x0C3 Register 78: USB Transmit Hub Port Endpoint 9 (USBTXHUBPORT9), offset 0x0CB Register 79: USB Transmit Hub Port Endpoint 10 (USBTXHUBPORT10), offset 0x0D3 Register 80: USB Transmit Hub Port Endpoint 11 (USBTXHUBPORT11), offset 0x0DB Register 81: USB Transmit Hub Port Endpoint 12 (USBTXHUBPORT12), offset 0x0E3 Register 82: USB Transmit Hub Port Endpoint 13 (USBTXHUBPORT13), offset 0x0EB Register 83: USB Transmit Hub Port Endpoint 14 (USBTXHUBPORT14), offset 0x0F3 Register 84: USB Transmit Hub Port Endpoint 15 (USBTXHUBPORT15), offset 0x0FB OTG A / Host USBTXHUBPORTn is an 8-bit read/write register that, like USBTXHUBADDRn, only must be written when a full- or low-speed Device is connected to transmit endpoint EPn via a USB 2.0 hub. This register records the port of the USB 2.0 hub through which the target associated with the endpoint is accessed. Note: USBTXHUBPORT0 is used for both receive and transmit for endpoint 0. July 22, 2011 927 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0) Base 0x4005.0000 Offset 0x083 Type R/W, reset 0x00 7 6 5 4 R/W 0 R/W 0 R/W 0 RO 0 2 1 0 R/W 0 R/W 0 R/W 0 PORT reserved Type Reset 3 R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 PORT R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hub Port This field specifies the USB hub port number. 928 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 85: USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C Register 86: USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 Register 87: USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C Register 88: USB Receive Functional Address Endpoint 4 (USBRXFUNCADDR4), offset 0x0A4 Register 89: USB Receive Functional Address Endpoint 5 (USBRXFUNCADDR5), offset 0x0AC Register 90: USB Receive Functional Address Endpoint 6 (USBRXFUNCADDR6), offset 0x0B4 Register 91: USB Receive Functional Address Endpoint 7 (USBRXFUNCADDR7), offset 0x0BC Register 92: USB Receive Functional Address Endpoint 8 (USBRXFUNCADDR8), offset 0x0C4 Register 93: USB Receive Functional Address Endpoint 9 (USBRXFUNCADDR9), offset 0x0CC Register 94: USB Receive Functional Address Endpoint 10 (USBRXFUNCADDR10), offset 0x0D4 Register 95: USB Receive Functional Address Endpoint 11 (USBRXFUNCADDR11), offset 0x0DC Register 96: USB Receive Functional Address Endpoint 12 (USBRXFUNCADDR12), offset 0x0E4 Register 97: USB Receive Functional Address Endpoint 13 (USBRXFUNCADDR13), offset 0x0EC Register 98: USB Receive Functional Address Endpoint 14 (USBRXFUNCADDR14), offset 0x0F4 Register 99: USB Receive Functional Address Endpoint 15 (USBRXFUNCADDR15), offset 0x0FC OTG A / Host USBRXFUNCADDRn is an 8-bit read/write register that records the address of the target function accessed through the associated endpoint (EPn). USBRXFUNCADDRn must be defined for each receive endpoint that is used. Note: USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0. July 22, 2011 929 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1) Base 0x4005.0000 Offset 0x08C Type R/W, reset 0x00 7 6 5 4 R/W 0 R/W 0 R/W 0 RO 0 2 1 0 R/W 0 R/W 0 R/W 0 ADDR reserved Type Reset 3 R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 ADDR R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Address This field specifies the USB bus address for the target Device. 930 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 100: USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E Register 101: USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 Register 102: USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E Register 103: USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4), offset 0x0A6 Register 104: USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5), offset 0x0AE Register 105: USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6), offset 0x0B6 Register 106: USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7), offset 0x0BE Register 107: USB Receive Hub Address Endpoint 8 (USBRXHUBADDR8), offset 0x0C6 Register 108: USB Receive Hub Address Endpoint 9 (USBRXHUBADDR9), offset 0x0CE Register 109: USB Receive Hub Address Endpoint 10 (USBRXHUBADDR10), offset 0x0D6 Register 110: USB Receive Hub Address Endpoint 11 (USBRXHUBADDR11), offset 0x0DE Register 111: USB Receive Hub Address Endpoint 12 (USBRXHUBADDR12), offset 0x0E6 Register 112: USB Receive Hub Address Endpoint 13 (USBRXHUBADDR13), offset 0x0EE Register 113: USB Receive Hub Address Endpoint 14 (USBRXHUBADDR14), offset 0x0F6 Register 114: USB Receive Hub Address Endpoint 15 (USBRXHUBADDR15), offset 0x0FE OTG A / Host USBRXHUBADDRn is an 8-bit read/write register that, like USBRXHUBPORTn, only must be written when a full- or low-speed Device is connected to receive endpoint EPn via a USB 2.0 hub. This register records the address of the USB 2.0 hub through which the target associated with the endpoint is accessed. Note: USBTXHUBADDR0 is used for both receive and transmit for endpoint 0. July 22, 2011 931 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1) Base 0x4005.0000 Offset 0x08E Type R/W, reset 0x00 7 6 5 4 R/W 0 R/W 0 R/W 0 R/W 0 2 1 0 R/W 0 R/W 0 R/W 0 ADDR MULTTRAN Type Reset 3 R/W 0 Bit/Field Name Type Reset 7 MULTTRAN R/W 0 Description Multiple Translators Value Description 6:0 ADDR R/W 0x00 0 Clear to indicate that the hub has a single transaction translator. 1 Set to indicate that the hub has multiple transaction translators. Hub Address This field specifies the USB bus address for the USB 2.0 hub. 932 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 115: USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F Register 116: USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 Register 117: USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F Register 118: USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset 0x0A7 Register 119: USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset 0x0AF Register 120: USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset 0x0B7 Register 121: USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset 0x0BF Register 122: USB Receive Hub Port Endpoint 8 (USBRXHUBPORT8), offset 0x0C7 Register 123: USB Receive Hub Port Endpoint 9 (USBRXHUBPORT9), offset 0x0CF Register 124: USB Receive Hub Port Endpoint 10 (USBRXHUBPORT10), offset 0x0D7 Register 125: USB Receive Hub Port Endpoint 11 (USBRXHUBPORT11), offset 0x0DF Register 126: USB Receive Hub Port Endpoint 12 (USBRXHUBPORT12), offset 0x0E7 Register 127: USB Receive Hub Port Endpoint 13 (USBRXHUBPORT13), offset 0x0EF Register 128: USB Receive Hub Port Endpoint 14 (USBRXHUBPORT14), offset 0x0F7 Register 129: USB Receive Hub Port Endpoint 15 (USBRXHUBPORT15), offset 0x0FF OTG A / Host USBRXHUBPORTn is an 8-bit read/write register that, like USBRXHUBADDRn, only must be written when a full- or low-speed Device is connected to receive endpoint EPn via a USB 2.0 hub. This register records the port of the USB 2.0 hub through which the target associated with the endpoint is accessed. Note: USBTXHUBPORT0 is used for both receive and transmit for endpoint 0. July 22, 2011 933 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1) Base 0x4005.0000 Offset 0x08F Type R/W, reset 0x00 7 6 5 4 R/W 0 R/W 0 R/W 0 RO 0 2 1 0 R/W 0 R/W 0 R/W 0 PORT reserved Type Reset 3 R/W 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 PORT R/W 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hub Port This field specifies the USB hub port number. 934 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 130: USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 Register 131: USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 Register 132: USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 Register 133: USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset 0x140 Register 134: USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset 0x150 Register 135: USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset 0x160 Register 136: USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset 0x170 Register 137: USB Maximum Transmit Data Endpoint 8 (USBTXMAXP8), offset 0x180 Register 138: USB Maximum Transmit Data Endpoint 9 (USBTXMAXP9), offset 0x190 Register 139: USB Maximum Transmit Data Endpoint 10 (USBTXMAXP10), offset 0x1A0 Register 140: USB Maximum Transmit Data Endpoint 11 (USBTXMAXP11), offset 0x1B0 Register 141: USB Maximum Transmit Data Endpoint 12 (USBTXMAXP12), offset 0x1C0 Register 142: USB Maximum Transmit Data Endpoint 13 (USBTXMAXP13), offset 0x1D0 Register 143: USB Maximum Transmit Data Endpoint 14 (USBTXMAXP14), offset 0x1E0 Register 144: USB Maximum Transmit Data Endpoint 15 (USBTXMAXP15), offset 0x1F0 OTG A / Host OTG B / Device The USBTXMAXPn 16-bit register defines the maximum amount of data that can be transferred through the transmit endpoint in a single operation. Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed operation. The total amount of data represented by the value written to this register must not exceed the FIFO size for the transmit endpoint, and must not exceed half the FIFO size if double-buffering is required. July 22, 2011 935 Texas Instruments-Production Data Universal Serial Bus (USB) Controller If this register is changed after packets have been sent from the endpoint, the transmit endpoint FIFO must be completely flushed (using the FLUSH bit in USBTXCSRLn) after writing the new value to this register. Note: USBTXMAXPn must be set to an even number of bytes for proper interrupt generation in µDMA Basic Mode. USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1) Base 0x4005.0000 Offset 0x110 Type R/W, reset 0x0000 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MAXLOAD RO 0 RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 15:11 reserved RO 0x0 10:0 MAXLOAD R/W 0x000 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Maximum Payload This field specifies the maximum payload in bytes per transaction. 936 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 145: USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 OTG A / USBCSRL0 is an 8-bit register that provides control and status bits for endpoint 0. Host OTG B / Device OTG A / Host Mode USB Control and Status Endpoint 0 Low (USBCSRL0) Base 0x4005.0000 Offset 0x102 Type W1C, reset 0x00 7 NAKTO Type Reset R/W 0 6 5 STATUS REQPKT R/W 0 4 3 2 1 0 ERROR SETUP STALLED TXRDY RXRDY R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 NAKTO R/W 0 Description NAK Timeout Value Description 0 No timeout. 1 Indicates that endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the USBNAKLMT register. Software must clear this bit to allow the endpoint to continue. 6 STATUS R/W 0 STATUS Packet Value Description 0 No transaction. 1 Initiates a STATUS stage transaction. This bit must be set at the same time as the TXRDY or REQPKT bit is set. Setting this bit ensures that the DT bit is set in the USBCSRH0 register so that a DATA1 packet is used for the STATUS stage transaction. This bit is automatically cleared when the STATUS stage is over. 5 REQPKT R/W 0 Request Packet Value Description 0 No request. 1 Requests an IN transaction. This bit is cleared when the RXRDY bit is set. July 22, 2011 937 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 4 ERROR R/W 0 Description Error Value Description 0 No error. 1 Three attempts have been made to perform a transaction with no response from the peripheral. The EP0 bit in the USBTXIS register is also set in this situation. Software must clear this bit. 3 SETUP R/W 0 Setup Packet Value Description 0 Sends an OUT token. 1 Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set. Setting this bit always clears the DT bit in the USBCSRH0 register to send a DATA0 packet. 2 STALLED R/W 0 Endpoint Stalled Value Description 0 No handshake has been received. 1 A STALL handshake has been received. Software must clear this bit. 1 TXRDY R/W 0 Transmit Packet Ready Value Description 0 No transmit packet is ready. 1 Software sets this bit after loading a data packet into the TX FIFO. The EP0 bit in the USBTXIS register is also set in this situation. If both the TXRDY and SETUP bits are set, a setup packet is sent. If just TXRDY is set, an OUT packet is sent. This bit is cleared automatically when the data packet has been transmitted. 0 RXRDY R/W 0 Receive Packet Ready Value Description 0 No received packet has been received. 1 Indicates that a data packet has been received in the RX FIFO. The EP0 bit in the USBTXIS register is also set in this situation. Software must clear this bit after the packet has been read from the FIFO to acknowledge that the data has been read from the FIFO. 938 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller OTG B / Device Mode USB Control and Status Endpoint 0 Low (USBCSRL0) Base 0x4005.0000 Offset 0x102 Type W1C, reset 0x00 7 6 SETENDC RXRDYC Type Reset W1C 0 W1C 0 5 STALL 4 3 2 SETEND DATAEND STALLED R/W 0 RO 0 R/W 0 R/W 0 1 0 TXRDY RXRDY R/W 0 RO 0 Bit/Field Name Type Reset 7 SETENDC W1C 0 Description Setup End Clear Writing a 1 to this bit clears the SETEND bit. 6 RXRDYC W1C 0 RXRDY Clear Writing a 1 to this bit clears the RXRDY bit. 5 STALL R/W 0 Send Stall Value Description 0 No effect. 1 Terminates the current transaction and transmits the STALL handshake. This bit is cleared automatically after the STALL handshake is transmitted. 4 SETEND RO 0 Setup End Value Description 0 A control transaction has not ended or ended after the DATAEND bit was set. 1 A control transaction has ended before the DATAEND bit has been set. The EP0 bit in the USBTXIS register is also set in this situation. This bit is cleared by writing a 1 to the SETENDC bit. 3 DATAEND R/W 0 Data End Value Description 0 No effect. 1 Set this bit in the following situations: ■ When setting TXRDY for the last data packet ■ When clearing RXRDY after unloading the last data packet ■ When setting TXRDY for a zero-length data packet This bit is cleared automatically. July 22, 2011 939 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 2 STALLED R/W 0 Description Endpoint Stalled Value Description 0 A STALL handshake has not been transmitted. 1 A STALL handshake has been transmitted. Software must clear this bit. 1 TXRDY R/W 0 Transmit Packet Ready Value Description 0 No transmit packet is ready. 1 Software sets this bit after loading an IN data packet into the TX FIFO. The EP0 bit in the USBTXIS register is also set in this situation. This bit is cleared automatically when the data packet has been transmitted. 0 RXRDY RO 0 Receive Packet Ready Value Description 0 No data packet has been received. 1 A data packet has been received. The EP0 bit in the USBTXIS register is also set in this situation. This bit is cleared by writing a 1 to the RXRDYC bit. 940 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 146: USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 OTG A / USBSR0H is an 8-bit register that provides control and status bits for endpoint 0. Host OTG B / Device OTG A / Host Mode USB Control and Status Endpoint 0 High (USBCSRH0) Base 0x4005.0000 Offset 0x103 Type W1C, reset 0x00 7 6 RO 0 RO 0 5 4 3 RO 0 RO 0 2 reserved Type Reset RO 0 1 0 DTWE DT FLUSH R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7:3 reserved RO 0x0 2 DTWE R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data Toggle Write Enable Value Description 0 The DT bit cannot be written. 1 Enables the current state of the endpoint 0 data toggle to be written (see DT bit). This bit is automatically cleared once the new value is written. 1 DT R/W 0 Data Toggle When read, this bit indicates the current state of the endpoint 0 data toggle. If DTWE is set, this bit may be written with the required setting of the data toggle. If DTWE is Low, this bit cannot be written. Care should be taken when writing to this bit as it should only be changed to RESET USB endpoint 0. July 22, 2011 941 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset Description 0 FLUSH R/W 0 Flush FIFO Value Description 0 No effect. 1 Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is cleared. This bit is automatically cleared after the flush is performed. Important: This bit should only be set when TXRDY/RXRDY is set. At other times, it may cause data to be corrupted. OTG B / Device Mode USB Control and Status Endpoint 0 High (USBCSRH0) Base 0x4005.0000 Offset 0x103 Type W1C, reset 0x00 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 0 FLUSH RO 0 RO 0 RO 0 R/W 0 Bit/Field Name Type Reset Description 7:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 FLUSH R/W 0 Flush FIFO Value Description 0 No effect. 1 Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and the TXRDY/RXRDY bit is cleared. This bit is automatically cleared after the flush is performed. Important: This bit should only be set when TXRDY/RXRDY is set. At other times, it may cause data to be corrupted. 942 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 147: USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 OTG A / Host USBCOUNT0 is an 8-bit read-only register that indicates the number of received data bytes in the endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while the RXRDY bit is set. USB Receive Byte Count Endpoint 0 (USBCOUNT0) OTG B / Device Base 0x4005.0000 Offset 0x108 Type RO, reset 0x00 7 6 5 4 RO 0 RO 0 RO 0 RO 0 2 1 0 RO 0 RO 0 RO 0 COUNT reserved Type Reset 3 RO 0 Bit/Field Name Type Reset 7 reserved RO 0 6:0 COUNT RO 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Count COUNT is a read-only value that indicates the number of received data bytes in the endpoint 0 FIFO. July 22, 2011 943 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 148: USB Type Endpoint 0 (USBTYPE0), offset 0x10A OTG A / Host This is an 8-bit register that must be written with the operating speed of the targeted Device being communicated with using endpoint 0. USB Type Endpoint 0 (USBTYPE0) Base 0x4005.0000 Offset 0x10A Type R/W, reset 0x00 7 6 5 4 3 R/W 0 RO 0 RO 0 RO 0 SPEED Type Reset R/W 0 2 1 0 RO 0 RO 0 RO 0 reserved Bit/Field Name Type Reset 7:6 SPEED R/W 0x0 Description Operating Speed This field specifies the operating speed of the target Device. If selected, the target is assumed to have the same connection speed as the USB controller. Value Description 0x0 - 0x1 Reserved 5:0 reserved RO 0x0 0x2 Full 0x3 Low Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 944 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 149: USB NAK Limit (USBNAKLMT), offset 0x10B OTG A / Host USBNAKLMT is an 8-bit register that sets the number of frames after which endpoint 0 should time out on receiving a stream of NAK responses. (Equivalent settings for other endpoints can be made through their USBTXINTERVALn and USBRXINTERVALn registers.) (m-1) The number of frames selected is 2 (where m is the value set in the register, with valid values of 2–16). If the Host receives NAK responses from the target for more frames than the number represented by the limit set in this register, the endpoint is halted. Note: A value of 0 or 1 disables the NAK timeout function. USB NAK Limit (USBNAKLMT) Base 0x4005.0000 Offset 0x10B Type R/W, reset 0x00 7 6 5 4 3 2 RO 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 1 0 R/W 0 R/W 0 NAKLMT R/W 0 Bit/Field Name Type Reset Description 7:5 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4:0 NAKLMT R/W 0x0 EP0 NAK Limit This field specifies the number of frames after receiving a stream of NAK responses. July 22, 2011 945 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 150: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 Register 151: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 Register 152: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 Register 153: USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142 Register 154: USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152 Register 155: USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162 Register 156: USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172 Register 157: USB Transmit Control and Status Endpoint 8 Low (USBTXCSRL8), offset 0x182 Register 158: USB Transmit Control and Status Endpoint 9 Low (USBTXCSRL9), offset 0x192 Register 159: USB Transmit Control and Status Endpoint 10 Low (USBTXCSRL10), offset 0x1A2 Register 160: USB Transmit Control and Status Endpoint 11 Low (USBTXCSRL11), offset 0x1B2 Register 161: USB Transmit Control and Status Endpoint 12 Low (USBTXCSRL12), offset 0x1C2 Register 162: USB Transmit Control and Status Endpoint 13 Low (USBTXCSRL13), offset 0x1D2 Register 163: USB Transmit Control and Status Endpoint 14 Low (USBTXCSRL14), offset 0x1E2 Register 164: USB Transmit Control and Status Endpoint 15 Low (USBTXCSRL15), offset 0x1F2 OTG A / USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the currently selected transmit endpoint. Host OTG B / Device 946 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller OTG A / Host Mode USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1) Base 0x4005.0000 Offset 0x112 Type R/W, reset 0x00 Type Reset 7 6 5 4 3 2 1 0 NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 NAKTO R/W 0 Description NAK Timeout Value Description 6 CLRDT R/W 0 0 No timeout. 1 Bulk endpoints only: Indicates that the transmit endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBTXINTERVALn register. Software must clear this bit to allow the endpoint to continue. Clear Data Toggle Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register. 5 STALLED R/W 0 Endpoint Stalled Value Description 0 A STALL handshake has not been received. 1 Indicates that a STALL handshake has been received. When this bit is set, any µDMA request that is in progress is stopped, the FIFO is completely flushed, and the TXRDY bit is cleared. Software must clear this bit. 4 SETUP R/W 0 Setup Packet Value Description 0 No SETUP token is sent. 1 Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same time as the TXRDY bit is set. Note: Setting this bit also clears the DT bit in the USBTXCSRHn register. July 22, 2011 947 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset Description 3 FLUSH R/W 0 Flush FIFO Value Description 0 No effect. 1 Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation. This bit may be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Important: 2 ERROR R/W 0 This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. Error Value Description 0 No error. 1 Three attempts have been made to send a packet and no handshake packet has been received. The TXRDY bit is cleared, the EPn bit in the USBTXIS register is set, and the FIFO is completely flushed in this situation. Software must clear this bit. Note: 1 FIFONE R/W 0 This is valid only when the endpoint is operating in Bulk or Interrupt mode. FIFO Not Empty Value Description 0 TXRDY R/W 0 0 The FIFO is empty. 1 At least one packet is in the transmit FIFO. Transmit Packet Ready Value Description 0 No transmit packet is ready. 1 Software sets this bit after loading a data packet into the TX FIFO. This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO. 948 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller OTG B / Device Mode USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1) Base 0x4005.0000 Offset 0x112 Type R/W, reset 0x00 Type Reset 7 6 5 4 3 2 1 0 reserved CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 CLRDT R/W 0 Clear Data Toggle Writing a 1 to this bit clears the DT bit in the USBTXCSRHn register. 5 STALLED R/W 0 Endpoint Stalled Value Description 0 A STALL handshake has not been transmitted. 1 A STALL handshake has been transmitted. The FIFO is flushed and the TXRDY bit is cleared. Software must clear this bit. 4 STALL R/W 0 Send STALL Value Description 0 No effect. 1 Issues a STALL handshake to an IN token. Software clears this bit to terminate the STALL condition. Note: 3 FLUSH R/W 0 This bit has no effect in isochronous transfers. Flush FIFO Value Description 0 No effect. 1 Flushes the latest packet from the endpoint transmit FIFO. The FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit in the USBTXIS register is also set in this situation. This bit may be set simultaneously with the TXRDY bit to abort the packet that is currently being loaded into the FIFO. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Important: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be corrupted. July 22, 2011 949 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 2 UNDRN R/W 0 Description Underrun Value Description 0 No underrun. 1 An IN token has been received when TXRDY is not set. Software must clear this bit. 1 FIFONE R/W 0 FIFO Not Empty Value Description 0 TXRDY R/W 0 0 The FIFO is empty. 1 At least one packet is in the transmit FIFO. Transmit Packet Ready Value Description 0 No transmit packet is ready. 1 Software sets this bit after loading a data packet into the TX FIFO. This bit is cleared automatically when a data packet has been transmitted. The EPn bit in the USBTXIS register is also set at this point. TXRDY is also automatically cleared prior to loading a second packet into a double-buffered FIFO. 950 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 165: USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 Register 166: USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 Register 167: USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 Register 168: USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143 Register 169: USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153 Register 170: USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163 Register 171: USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173 Register 172: USB Transmit Control and Status Endpoint 8 High (USBTXCSRH8), offset 0x183 Register 173: USB Transmit Control and Status Endpoint 9 High (USBTXCSRH9), offset 0x193 Register 174: USB Transmit Control and Status Endpoint 10 High (USBTXCSRH10), offset 0x1A3 Register 175: USB Transmit Control and Status Endpoint 11 High (USBTXCSRH11), offset 0x1B3 Register 176: USB Transmit Control and Status Endpoint 12 High (USBTXCSRH12), offset 0x1C3 Register 177: USB Transmit Control and Status Endpoint 13 High (USBTXCSRH13), offset 0x1D3 Register 178: USB Transmit Control and Status Endpoint 14 High (USBTXCSRH14), offset 0x1E3 Register 179: USB Transmit Control and Status Endpoint 15 High (USBTXCSRH15), offset 0x1F3 OTG A / USBTXCSRHn is an 8-bit register that provides additional control for transfers through the currently selected transmit endpoint. Host OTG B / Device July 22, 2011 951 Texas Instruments-Production Data Universal Serial Bus (USB) Controller OTG A / Host Mode USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1) Base 0x4005.0000 Offset 0x113 Type R/W, reset 0x00 7 6 AUTOSET reserved Type Reset R/W 0 RO 0 5 4 3 2 1 MODE DMAEN FDT DMAMOD DTWE DT R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 AUTOSET R/W 0 0 Description Auto Set Value Description 0 The TXRDY bit must be set manually. 1 Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in USBTXMAXPn) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then the TXRDY bit must be set manually. 6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 MODE R/W 0 Mode Value Description 0 Enables the endpoint direction as RX. 1 Enables the endpoint direction as TX. Note: 4 DMAEN R/W 0 This bit only has an effect when the same endpoint FIFO is used for both transmit and receive transactions. DMA Request Enable Value Description 0 Disables the µDMA request for the transmit endpoint. 1 Enables the µDMA request for the transmit endpoint. Note: 3 FDT R/W 0 3 TX and 3 /RX endpoints can be connected to the µDMA module. If this bit is set for a particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. Force Data Toggle Value Description 0 No effect. 1 Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints. 952 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 2 DMAMOD R/W 0 Description DMA Request Mode Value Description 0 An interrupt is generated after every µDMA packet transfer. 1 An interrupt is generated only after the entire μDMA transfer is complete. Note: 1 DTWE R/W 0 This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Data Toggle Write Enable Value Description 0 The DT bit cannot be written. 1 Enables the current state of the transmit endpoint data to be written (see DT bit). This bit is automatically cleared once the new value is written. 0 DT R/W 0 Data Toggle When read, this bit indicates the current state of the transmit endpoint data toggle. If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the transmit endpoint. OTG B / Device Mode USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1) Base 0x4005.0000 Offset 0x113 Type R/W, reset 0x00 Type Reset 7 6 5 4 3 2 AUTOSET ISO MODE DMAEN FDT DMAMOD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 1 0 reserved RO 0 Bit/Field Name Type Reset 7 AUTOSET R/W 0 RO 0 Description Auto Set Value Description 0 The TXRDY bit must be set manually. 1 Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in USBTXMAXPn) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then the TXRDY bit must be set manually. July 22, 2011 953 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 6 ISO R/W 0 Description Isochronous Transfers Value Description 5 MODE R/W 0 0 Enables the transmit endpoint for bulk or interrupt transfers. 1 Enables the transmit endpoint for isochronous transfers. Mode Value Description 0 Enables the endpoint direction as RX. 1 Enables the endpoint direction as TX. Note: 4 DMAEN R/W 0 This bit only has an effect where the same endpoint FIFO is used for both transmit and receive transactions. DMA Request Enable Value Description 0 Disables the µDMA request for the transmit endpoint. 1 Enables the µDMA request for the transmit endpoint. Note: 3 FDT R/W 0 3 TX and 3 RX endpoints can be connected to the µDMA module. If this bit is set for a particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. Force Data Toggle Value Description 2 DMAMOD R/W 0 0 No effect. 1 Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints. DMA Request Mode Value Description 0 An interrupt is generated after every µDMA packet transfer. 1 An interrupt is generated only after the entire μDMA transfer is complete. Note: 1:0 reserved RO 0 This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 954 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 180: USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 Register 181: USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 Register 182: USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 Register 183: USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144 Register 184: USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154 Register 185: USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164 Register 186: USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174 Register 187: USB Maximum Receive Data Endpoint 8 (USBRXMAXP8), offset 0x184 Register 188: USB Maximum Receive Data Endpoint 9 (USBRXMAXP9), offset 0x194 Register 189: USB Maximum Receive Data Endpoint 10 (USBRXMAXP10), offset 0x1A4 Register 190: USB Maximum Receive Data Endpoint 11 (USBRXMAXP11), offset 0x1B4 Register 191: USB Maximum Receive Data Endpoint 12 (USBRXMAXP12), offset 0x1C4 Register 192: USB Maximum Receive Data Endpoint 13 (USBRXMAXP13), offset 0x1D4 Register 193: USB Maximum Receive Data Endpoint 14 (USBRXMAXP14), offset 0x1E4 Register 194: USB Maximum Receive Data Endpoint 15 (USBRXMAXP15), offset 0x1F4 OTG A / Host OTG B / Device The USBRXMAXPn is a 16-bit register which defines the maximum amount of data that can be transferred through the selected receive endpoint in a single operation. Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed operations. The total amount of data represented by the value written to this register must not exceed the FIFO size for the receive endpoint, and must not exceed half the FIFO size if double-buffering is required. July 22, 2011 955 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Note: USBRXMAXPn must be set to an even number of bytes for proper interrupt generation in µDMA Basic mode. USB Maximum Receive Data Endpoint 1 (USBRXMAXP1) Base 0x4005.0000 Offset 0x114 Type R/W, reset 0x0000 15 14 RO 0 RO 0 13 12 11 10 9 8 7 6 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MAXLOAD Bit/Field Name Type Reset 15:11 reserved RO 0x0 10:0 MAXLOAD R/W 0x000 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Maximum Payload The maximum payload in bytes per transaction. 956 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 195: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 Register 196: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 Register 197: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 Register 198: USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146 Register 199: USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156 Register 200: USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166 Register 201: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 Register 202: USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8), offset 0x186 Register 203: USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9), offset 0x196 Register 204: USB Receive Control and Status Endpoint 10 Low (USBRXCSRL10), offset 0x1A6 Register 205: USB Receive Control and Status Endpoint 11 Low (USBRXCSRL11), offset 0x1B6 Register 206: USB Receive Control and Status Endpoint 12 Low (USBRXCSRL12), offset 0x1C6 Register 207: USB Receive Control and Status Endpoint 13 Low (USBRXCSRL13), offset 0x1D6 Register 208: USB Receive Control and Status Endpoint 14 Low (USBRXCSRL14), offset 0x1E6 Register 209: USB Receive Control and Status Endpoint 15 Low (USBRXCSRL15), offset 0x1F6 OTG A / USBRXCSRLn is an 8-bit register that provides control and status bits for transfers through the currently selected receive endpoint. Host OTG B / Device July 22, 2011 957 Texas Instruments-Production Data Universal Serial Bus (USB) Controller OTG A / Host Mode USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1) Base 0x4005.0000 Offset 0x116 Type R/W, reset 0x00 7 CLRDT Type Reset W1C 0 6 5 STALLED REQPKT R/W 0 4 FLUSH R/W 0 R/W 0 3 DATAERR / NAKTO 2 1 0 ERROR FULL RXRDY R/W 0 RO 0 R/W 0 R/W 0 Bit/Field Name Type Reset 7 CLRDT W1C 0 Description Clear Data Toggle Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register. 6 STALLED R/W 0 Endpoint Stalled Value Description 0 A STALL handshake has not been received. 1 A STALL handshake has been received. The EPn bit in the USBRXIS register is also set. Software must clear this bit. 5 REQPKT R/W 0 Request Packet Value Description 0 No request. 1 Requests an IN transaction. This bit is cleared when RXRDY is set. 4 FLUSH R/W 0 Flush FIFO Value Description 0 No effect. 1 Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Important: This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted. 958 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 3 DATAERR / NAKTO R/W 0 Description Data Error / NAK Timeout Value Description 0 Normal operation. 1 Isochronous endpoints only: Indicates that RXRDY is set and the data packet has a CRC or bit-stuff error. This bit is cleared when RXRDY is cleared. Bulk endpoints only: Indicates that the receive endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBRXINTERVALn register. Software must clear this bit to allow the endpoint to continue. 2 ERROR R/W 0 Error Value Description 0 No error. 1 Three attempts have been made to receive a packet and no data packet has been received. The EPn bit in the USBRXIS register is set in this situation. Software must clear this bit. Note: 1 FULL RO 0 This bit is only valid when the receive endpoint is operating in Bulk or Interrupt mode. In Isochronous mode, it always returns zero. FIFO Full Value Description 0 RXRDY R/W 0 0 The receive FIFO is not full. 1 No more packets can be loaded into the receive FIFO. Receive Packet Ready Value Description 0 No data packet has been received. 1 A data packet has been received. The EPn bit in the USBRXIS register is also set in this situation. If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit is automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO. July 22, 2011 959 Texas Instruments-Production Data Universal Serial Bus (USB) Controller OTG B / Device Mode USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1) Base 0x4005.0000 Offset 0x116 Type R/W, reset 0x00 Type Reset 7 6 5 CLRDT STALLED STALL W1C 0 R/W 0 R/W 0 4 3 FLUSH DATAERR R/W 0 2 1 0 OVER FULL RXRDY R/W 0 RO 0 R/W 0 RO 0 Bit/Field Name Type Reset 7 CLRDT W1C 0 Description Clear Data Toggle Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register. 6 STALLED R/W 0 Endpoint Stalled Value Description 0 A STALL handshake has not been transmitted. 1 A STALL handshake has been transmitted. Software must clear this bit. 5 STALL R/W 0 Send STALL Value Description 0 No effect. 1 Issues a STALL handshake. Software must clear this bit to terminate the STALL condition. Note: 4 FLUSH R/W 0 This bit has no effect where the endpoint is being used for isochronous transfers. Flush FIFO Value Description 0 No effect. 1 Flushes the next packet from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Important: This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted. 960 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 3 DATAERR RO 0 Data Error Value Description 0 Normal operation. 1 Indicates that RXRDY is set and the data packet has a CRC or bit-stuff error. This bit is cleared when RXRDY is cleared. Note: 2 OVER R/W 0 This bit is only valid when the endpoint is operating in Isochronous mode. In Bulk mode, it always returns zero. Overrun Value Description 0 No overrun error. 1 Indicates that an OUT packet cannot be loaded into the receive FIFO. Software must clear this bit. Note: 1 FULL RO 0 This bit is only valid when the endpoint is operating in Isochronous mode. In Bulk mode, it always returns zero. FIFO Full Value Description 0 RXRDY R/W 0 0 The receive FIFO is not full. 1 No more packets can be loaded into the receive FIFO. Receive Packet Ready Value Description 0 No data packet has been received. 1 A data packet has been received. The EPn bit in the USBRXIS register is also set in this situation. If the AUTOCLR bit in the USBRXCSRHn register is set, then the this bit is automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO. July 22, 2011 961 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 210: USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 Register 211: USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 Register 212: USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 Register 213: USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147 Register 214: USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157 Register 215: USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167 Register 216: USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177 Register 217: USB Receive Control and Status Endpoint 8 High (USBRXCSRH8), offset 0x187 Register 218: USB Receive Control and Status Endpoint 9 High (USBRXCSRH9), offset 0x197 Register 219: USB Receive Control and Status Endpoint 10 High (USBRXCSRH10), offset 0x1A7 Register 220: USB Receive Control and Status Endpoint 11 High (USBRXCSRH11), offset 0x1B7 Register 221: USB Receive Control and Status Endpoint 12 High (USBRXCSRH12), offset 0x1C7 Register 222: USB Receive Control and Status Endpoint 13 High (USBRXCSRH13), offset 0x1D7 Register 223: USB Receive Control and Status Endpoint 14 High (USBRXCSRH14), offset 0x1E7 Register 224: USB Receive Control and Status Endpoint 15 High (USBRXCSRH15), offset 0x1F7 OTG A / USBRXCSRHn is an 8-bit register that provides additional control and status bits for transfers through the currently selected receive endpoint. Host OTG B / Device 962 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller OTG A / Host Mode USB Receive Control and Status Endpoint 1 High (USBRXCSRH1) Base 0x4005.0000 Offset 0x117 Type R/W, reset 0x00 7 6 5 AUTOCL AUTORQ DMAEN Type Reset R/W 0 R/W 0 4 3 2 PIDERR DMAMOD R/W 0 RO 0 1 0 DTWE DT reserved RO 0 RO 0 RO 0 R/W 0 Bit/Field Name Type Reset Description 7 AUTOCL R/W 0 Auto Clear Value Description 6 AUTORQ R/W 0 0 No effect. 1 Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using µDMA to unload the receive FIFO as data is read from the receive FIFO in 4 byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXPn register, see “DMA Operation” on page 877. Auto Request Value Description 0 No effect. 1 Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared. Note: 5 DMAEN R/W 0 This bit is automatically cleared when a short packet is received. DMA Request Enable Value Description 0 Disables the µDMA request for the receive endpoint. 1 Enables the µDMA request for the receive endpoint. Note: 4 PIDERR RO 0 3 TX and 3 RX endpoints can be connected to the µDMA module. If this bit is set for a particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. PID Error Value Description 0 No error. 1 Indicates a PID error in the received packet of an isochronous transaction. This bit is ignored in bulk or interrupt transactions. July 22, 2011 963 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 3 DMAMOD R/W 0 Description DMA Request Mode Value Description 0 An interrupt is generated after every µDMA packet transfer. 1 An interrupt is generated only after the entire μDMA transfer is complete. Note: 2 DTWE RO 0 This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. Data Toggle Write Enable Value Description 0 The DT bit cannot be written. 1 Enables the current state of the receive endpoint data to be written (see DT bit). This bit is automatically cleared once the new value is written. 1 DT RO 0 Data Toggle When read, this bit indicates the current state of the receive data toggle. If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the receive endpoint. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. OTG B / Device Mode USB Receive Control and Status Endpoint 1 High (USBRXCSRH1) Base 0x4005.0000 Offset 0x117 Type R/W, reset 0x00 7 Type Reset 6 5 AUTOCL ISO DMAEN R/W 0 R/W 0 R/W 0 4 DISNYET / PIDERR R/W 0 3 2 DMAMOD R/W 0 1 0 reserved RO 0 RO 0 RO 0 964 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 7 AUTOCL R/W 0 Auto Clear Value Description 6 ISO R/W 0 0 No effect. 1 Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXPn bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using µDMA to unload the receive FIFO as data is read from the receive FIFO in 4 byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXPn register, see “DMA Operation” on page 877. Isochronous Transfers Value Description 5 DMAEN R/W 0 0 Enables the receive endpoint for isochronous transfers. 1 Enables the receive endpoint for bulk/interrupt transfers. DMA Request Enable Value Description 0 Disables the µDMA request for the receive endpoint. 1 Enables the µDMA request for the receive endpoint. Note: 4 DISNYET / PIDERR R/W 0 3 TX and 3 RX endpoints can be connected to the µDMA module. If this bit is set for a particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. Disable NYET / PID Error Value Description 0 No effect. 1 For bulk or interrupt transactions: Disables the sending of NYET handshakes. When this bit is set, all successfully received packets are acknowledged, including at the point at which the FIFO becomes full. For isochronous transactions: Indicates a PID error in the received packet. 3 DMAMOD R/W 0 DMA Request Mode Value Description 0 An interrupt is generated after every µDMA packet transfer. 1 An interrupt is generated only after the entire μDMA transfer is complete. Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. July 22, 2011 965 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 2:0 reserved RO 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 966 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 225: USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 Register 226: USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 Register 227: USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 Register 228: USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148 Register 229: USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158 Register 230: USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168 Register 231: USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178 Register 232: USB Receive Byte Count Endpoint 8 (USBRXCOUNT8), offset 0x188 Register 233: USB Receive Byte Count Endpoint 9 (USBRXCOUNT9), offset 0x198 Register 234: USB Receive Byte Count Endpoint 10 (USBRXCOUNT10), offset 0x1A8 Register 235: USB Receive Byte Count Endpoint 11 (USBRXCOUNT11), offset 0x1B8 Register 236: USB Receive Byte Count Endpoint 12 (USBRXCOUNT12), offset 0x1C8 Register 237: USB Receive Byte Count Endpoint 13 (USBRXCOUNT13), offset 0x1D8 Register 238: USB Receive Byte Count Endpoint 14 (USBRXCOUNT14), offset 0x1E8 Register 239: USB Receive Byte Count Endpoint 15 (USBRXCOUNT15), offset 0x1F8 OTG A / Host OTG B / Note: The value returned changes as the FIFO is unloaded and is only valid while the RXRDY bit in the USBRXCSRLn register is set. USBRXCOUNTn is a 16-bit read-only register that holds the number of data bytes in the packet currently in line to be read from the receive FIFO. If the packet is transmitted as multiple bulk packets, the number given is for the combined packet. Device July 22, 2011 967 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Receive Byte Count Endpoint 1 (USBRXCOUNT1) Base 0x4005.0000 Offset 0x118 Type RO, reset 0x0000 15 14 13 12 11 10 9 8 7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 COUNT Bit/Field Name Type Reset 15:13 reserved RO 0x0 12:0 COUNT RO 0x000 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Receive Packet Count Indicates the number of bytes in the receive packet. 968 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 240: USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A Register 241: USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A Register 242: USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A Register 243: USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4), offset 0x14A Register 244: USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5), offset 0x15A Register 245: USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6), offset 0x16A Register 246: USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7), offset 0x17A Register 247: USB Host Transmit Configure Type Endpoint 8 (USBTXTYPE8), offset 0x18A Register 248: USB Host Transmit Configure Type Endpoint 9 (USBTXTYPE9), offset 0x19A Register 249: USB Host Transmit Configure Type Endpoint 10 (USBTXTYPE10), offset 0x1AA Register 250: USB Host Transmit Configure Type Endpoint 11 (USBTXTYPE11), offset 0x1BA Register 251: USB Host Transmit Configure Type Endpoint 12 (USBTXTYPE12), offset 0x1CA Register 252: USB Host Transmit Configure Type Endpoint 13 (USBTXTYPE13), offset 0x1DA Register 253: USB Host Transmit Configure Type Endpoint 14 (USBTXTYPE14), offset 0x1EA Register 254: USB Host Transmit Configure Type Endpoint 15 (USBTXTYPE15), offset 0x1FA OTG A / Host USBTXTYPEn is an 8-bit register that must be written with the endpoint number to be targeted by the endpoint, the transaction protocol to use for the currently selected transmit endpoint, and its operating speed. July 22, 2011 969 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1) Base 0x4005.0000 Offset 0x11A Type R/W, reset 0x00 7 6 5 R/W 0 R/W 0 SPEED Type Reset R/W 0 4 3 2 R/W 0 R/W 0 R/W 0 PROTO 1 0 R/W 0 R/W 0 TEP Bit/Field Name Type Reset 7:6 SPEED R/W 0x0 Description Operating Speed This bit field specifies the operating speed of the target Device: Value Description 0x0 Default The target is assumed to be using the same connection speed as the USB controller. 5:4 PROTO R/W 0x0 0x1 Reserved 0x2 Full 0x3 Low Protocol Software must configure this bit field to select the required protocol for the transmit endpoint: Value Description 3:0 TEP R/W 0x0 0x0 Control 0x1 Isochronous 0x2 Bulk 0x3 Interrupt Target Endpoint Number Software must configure this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during Device enumeration. 970 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 255: USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B Register 256: USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B Register 257: USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B Register 258: USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4), offset 0x14B Register 259: USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5), offset 0x15B Register 260: USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6), offset 0x16B Register 261: USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7), offset 0x17B Register 262: USB Host Transmit Interval Endpoint 8 (USBTXINTERVAL8), offset 0x18B Register 263: USB Host Transmit Interval Endpoint 9 (USBTXINTERVAL9), offset 0x19B Register 264: USB Host Transmit Interval Endpoint 10 (USBTXINTERVAL10), offset 0x1AB Register 265: USB Host Transmit Interval Endpoint 11 (USBTXINTERVAL11), offset 0x1BB Register 266: USB Host Transmit Interval Endpoint 12 (USBTXINTERVAL12), offset 0x1CB Register 267: USB Host Transmit Interval Endpoint 13 (USBTXINTERVAL13), offset 0x1DB Register 268: USB Host Transmit Interval Endpoint 14 (USBTXINTERVAL14), offset 0x1EB Register 269: USB Host Transmit Interval Endpoint 15 (USBTXINTERVAL15), offset 0x1FB OTG A / Host USBTXINTERVALn is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently selected transmit endpoint. For bulk endpoints, this register defines the number of frames after which the endpoint should time out on receiving a stream of NAK responses. The USBTXINTERVALn register value defines a number of frames, as follows: July 22, 2011 971 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Transfer Type Speed Valid values (m) Low-Speed or Full-Speed 0x01 – 0xFF The polling interval is m frames. Isochronous Full-Speed 0x01 – 0x10 The polling interval is 2(m-1) frames. Bulk Full-Speed 0x02 – 0x10 The NAK Limit is 2(m-1) frames. A value of 0 or 1 disables the NAK timeout function. Interrupt Interpretation USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1) Base 0x4005.0000 Offset 0x11B Type R/W, reset 0x00 7 6 5 R/W 0 R/W 0 R/W 0 4 3 2 1 0 R/W 0 R/W 0 R/W 0 TXPOLL / NAKLMT Type Reset R/W 0 R/W 0 Bit/Field Name Type Reset Description 7:0 TXPOLL / NAKLMT R/W 0x00 TX Polling / NAK Limit The polling interval for interrupt/isochronous transfers; the NAK limit for bulk transfers. See table above for valid entries; other values are reserved. 972 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 270: USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C Register 271: USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C Register 272: USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C Register 273: USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4), offset 0x14C Register 274: USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5), offset 0x15C Register 275: USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6), offset 0x16C Register 276: USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7), offset 0x17C Register 277: USB Host Configure Receive Type Endpoint 8 (USBRXTYPE8), offset 0x18C Register 278: USB Host Configure Receive Type Endpoint 9 (USBRXTYPE9), offset 0x19C Register 279: USB Host Configure Receive Type Endpoint 10 (USBRXTYPE10), offset 0x1AC Register 280: USB Host Configure Receive Type Endpoint 11 (USBRXTYPE11), offset 0x1BC Register 281: USB Host Configure Receive Type Endpoint 12 (USBRXTYPE12), offset 0x1CC Register 282: USB Host Configure Receive Type Endpoint 13 (USBRXTYPE13), offset 0x1DC Register 283: USB Host Configure Receive Type Endpoint 14 (USBRXTYPE14), offset 0x1EC Register 284: USB Host Configure Receive Type Endpoint 15 (USBRXTYPE15), offset 0x1FC OTG A / Host USBRXTYPEn is an 8-bit register that must be written with the endpoint number to be targeted by the endpoint, the transaction protocol to use for the currently selected receive endpoint, and its operating speed. July 22, 2011 973 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1) Base 0x4005.0000 Offset 0x11C Type R/W, reset 0x00 7 6 5 R/W 0 R/W 0 SPEED Type Reset R/W 0 4 3 2 R/W 0 R/W 0 R/W 0 PROTO 1 0 R/W 0 R/W 0 TEP Bit/Field Name Type Reset 7:6 SPEED R/W 0x0 Description Operating Speed This bit field specifies the operating speed of the target Device: Value Description 0x0 Default The target is assumed to be using the same connection speed as the USB controller. 5:4 PROTO R/W 0x0 0x1 Reserved 0x2 Full 0x3 Low Protocol Software must configure this bit field to select the required protocol for the receive endpoint: Value Description 3:0 TEP R/W 0x0 0x0 Control 0x1 Isochronous 0x2 Bulk 0x3 Interrupt Target Endpoint Number Software must set this value to the endpoint number contained in the receive endpoint descriptor returned to the USB controller during Device enumeration. 974 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 285: USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D Register 286: USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D Register 287: USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D Register 288: USB Host Receive Polling Interval Endpoint 4 (USBRXINTERVAL4), offset 0x14D Register 289: USB Host Receive Polling Interval Endpoint 5 (USBRXINTERVAL5), offset 0x15D Register 290: USB Host Receive Polling Interval Endpoint 6 (USBRXINTERVAL6), offset 0x16D Register 291: USB Host Receive Polling Interval Endpoint 7 (USBRXINTERVAL7), offset 0x17D Register 292: USB Host Receive Polling Interval Endpoint 8 (USBRXINTERVAL8), offset 0x18D Register 293: USB Host Receive Polling Interval Endpoint 9 (USBRXINTERVAL9), offset 0x19D Register 294: USB Host Receive Polling Interval Endpoint 10 (USBRXINTERVAL10), offset 0x1AD Register 295: USB Host Receive Polling Interval Endpoint 11 (USBRXINTERVAL11), offset 0x1BD Register 296: USB Host Receive Polling Interval Endpoint 12 (USBRXINTERVAL12), offset 0x1CD Register 297: USB Host Receive Polling Interval Endpoint 13 (USBRXINTERVAL13), offset 0x1DD Register 298: USB Host Receive Polling Interval Endpoint 14 (USBRXINTERVAL14), offset 0x1ED Register 299: USB Host Receive Polling Interval Endpoint 15 (USBRXINTERVAL15), offset 0x1FD OTG A / Host USBRXINTERVALn is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently selected receive endpoint. For bulk endpoints, this register defines the number of frames after which the endpoint should time out on receiving a stream of NAK responses. The USBTXINTERVALn register value defines a number of frames, as follows: Transfer Type Interrupt Isochronous Speed Valid values (m) Low-Speed or Full-Speed 0x01 – 0xFF The polling interval is m frames. Full-Speed 0x01 – 0x10 The polling interval is 2(m-1) frames. July 22, 2011 Interpretation 975 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Transfer Type Bulk Speed Valid values (m) Full-Speed 0x02 – 0x10 Interpretation The NAK Limit is 2(m-1) frames. A value of 0 or 1 disables the NAK timeout function. USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1) Base 0x4005.0000 Offset 0x11D Type R/W, reset 0x00 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 TXPOLL / NAKLMT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 7:0 TXPOLL / NAKLMT R/W 0x00 RX Polling / NAK Limit The polling interval for interrupt/isochronous transfers; the NAK limit for bulk transfers. See table above for valid entries; other values are reserved. 976 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 300: USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset 0x304 Register 301: USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset 0x308 Register 302: USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset 0x30C Register 303: USB Request Packet Count in Block Transfer Endpoint 4 (USBRQPKTCOUNT4), offset 0x310 Register 304: USB Request Packet Count in Block Transfer Endpoint 5 (USBRQPKTCOUNT5), offset 0x314 Register 305: USB Request Packet Count in Block Transfer Endpoint 6 (USBRQPKTCOUNT6), offset 0x318 Register 306: USB Request Packet Count in Block Transfer Endpoint 7 (USBRQPKTCOUNT7), offset 0x31C Register 307: USB Request Packet Count in Block Transfer Endpoint 8 (USBRQPKTCOUNT8), offset 0x320 Register 308: USB Request Packet Count in Block Transfer Endpoint 9 (USBRQPKTCOUNT9), offset 0x324 Register 309: USB Request Packet Count in Block Transfer Endpoint 10 (USBRQPKTCOUNT10), offset 0x328 Register 310: USB Request Packet Count in Block Transfer Endpoint 11 (USBRQPKTCOUNT11), offset 0x32C Register 311: USB Request Packet Count in Block Transfer Endpoint 12 (USBRQPKTCOUNT12), offset 0x330 Register 312: USB Request Packet Count in Block Transfer Endpoint 13 (USBRQPKTCOUNT13), offset 0x334 Register 313: USB Request Packet Count in Block Transfer Endpoint 14 (USBRQPKTCOUNT14), offset 0x338 Register 314: USB Request Packet Count in Block Transfer Endpoint 15 (USBRQPKTCOUNT15), offset 0x33C OTG A / Host This 16-bit read/write register is used in Host mode to specify the number of packets that are to be transferred in a block transfer of one or more bulk packets to receive endpoint n. The USB controller uses the value recorded in this register to determine the number of requests to issue where the AUTORQ bit in the USBRXCSRHn register has been set. See “IN Transactions as a Host” on page 872. Note: Multiple packets combined into a single bulk packet within the FIFO count as one packet. July 22, 2011 977 Texas Instruments-Production Data Universal Serial Bus (USB) Controller USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1) Base 0x4005.0000 Offset 0x304 Type R/W, reset 0x0000 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 COUNT Type Reset Bit/Field Name Type Reset 15:0 COUNT R/W 0x0000 Description Block Transfer Packet Count Sets the number of packets of the size defined by the MAXLOAD bit field that are to be transferred in a block transfer. Note: This is only used in Host mode when AUTORQ is set. The bit has no effect in Device mode or when AUTORQ is not set. 978 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 315: USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 OTG A / Host USBRXDPKTBUFDIS is a 16-bit register that indicates which of the receive endpoints have disabled the double-packet buffer functionality (see the section called “Double-Packet Buffering” on page 868). USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) OTG B / Base 0x4005.0000 Offset 0x340 Type R/W, reset 0x0000 Device Type Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 reserved R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 Bit/Field Name Type Reset 15 EP15 R/W 0 Description EP15 RX Double-Packet Buffer Disable Value Description 14 EP14 R/W 0 0 Disables double-packet buffering. 1 Enables double-packet buffering. EP14 RX Double-Packet Buffer Disable Same description as EP15. 13 EP13 R/W 0 EP13 RX Double-Packet Buffer Disable Same description as EP15. 12 EP12 R/W 0 EP12 RX Double-Packet Buffer Disable Same description as EP15. 11 EP11 R/W 0 EP11 RX Double-Packet Buffer Disable Same description as EP15. 10 EP10 R/W 0 EP10 RX Double-Packet Buffer Disable Same description as EP15. 9 EP9 R/W 0 EP9 RX Double-Packet Buffer Disable Same description as EP15. 8 EP8 R/W 0 EP8 RX Double-Packet Buffer Disable Same description as EP15. 7 EP7 R/W 0 EP7 RX Double-Packet Buffer Disable Same description as EP15. 6 EP6 R/W 0 EP6 RX Double-Packet Buffer Disable Same description as EP15. 5 EP5 R/W 0 EP5 RX Double-Packet Buffer Disable Same description as EP15. 4 EP4 R/W 0 EP4 RX Double-Packet Buffer Disable Same description as EP15. July 22, 2011 979 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 3 EP3 R/W 0 Description EP3 RX Double-Packet Buffer Disable Same description as EP15. 2 EP2 R/W 0 EP2 RX Double-Packet Buffer Disable Same description as EP15. 1 EP1 R/W 0 EP1 RX Double-Packet Buffer Disable Same description as EP15. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 980 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 316: USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 OTG A / Host USBTXDPKTBUFDIS is a 16-bit register that indicates which of the transmit endpoints have disabled the double-packet buffer functionality (see the section called “Double-Packet Buffering” on page 868). USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS) OTG B / Base 0x4005.0000 Offset 0x342 Type R/W, reset 0x0000 Device Type Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 reserved R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 Bit/Field Name Type Reset 15 EP15 R/W 0 Description EP15 TX Double-Packet Buffer Disable Value Description 14 EP14 R/W 0 0 Disables double-packet buffering. 1 Enables double-packet buffering. EP14 TX Double-Packet Buffer Disable Same description as EP15. 13 EP13 R/W 0 EP13 TX Double-Packet Buffer Disable Same description as EP15. 12 EP12 R/W 0 EP12 TX Double-Packet Buffer Disable Same description as EP15. 11 EP11 R/W 0 EP11 TX Double-Packet Buffer Disable Same description as EP15. 10 EP10 R/W 0 EP10 TX Double-Packet Buffer Disable Same description as EP15. 9 EP9 R/W 0 EP9 TX Double-Packet Buffer Disable Same description as EP15. 8 EP8 R/W 0 EP8 TX Double-Packet Buffer Disable Same description as EP15. 7 EP7 R/W 0 EP7 TX Double-Packet Buffer Disable Same description as EP15. 6 EP6 R/W 0 EP6 TX Double-Packet Buffer Disable Same description as EP15. 5 EP5 R/W 0 EP5 TX Double-Packet Buffer Disable Same description as EP15. 4 EP4 R/W 0 EP4 TX Double-Packet Buffer Disable Same description as EP15. July 22, 2011 981 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 3 EP3 R/W 0 Description EP3 TX Double-Packet Buffer Disable Same description as EP15. 2 EP2 R/W 0 EP2 TX Double-Packet Buffer Disable Same description as EP15. 1 EP1 R/W 0 EP1 TX Double-Packet Buffer Disable Same description as EP15. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 982 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 317: USB External Power Control (USBEPC), offset 0x400 OTG A / Host This 32-bit register specifies the function of the two-pin external power interface (USB0EPEN and USB0PFLT). The assertion of the power fault input may generate an automatic action, as controlled by the hardware configuration registers. The automatic action is necessary because the fault condition may require a response faster than one provided by firmware. OTG B / USB External Power Control (USBEPC) Device Base 0x4005.0000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved EPENDE RO 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 PFLTACT Bit/Field Name Type Reset 31:10 reserved RO 0x0000.0 9:8 PFLTACT R/W 0x0 reserved R/W 0 PFLTAEN PFLTSEN PFLTEN RO 0 R/W 0 R/W 0 R/W 0 EPEN R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power Fault Action This bit field specifies how the USB0EPEN signal is changed when detecting a USB power fault. Value Description 0x0 Unchanged USB0EPEN is controlled by the combination of the EPEN and EPENDE bits. 0x1 Tristate USB0EPEN is undriven (tristate). 0x2 Low USB0EPEN is driven Low. 0x3 High USB0EPEN is driven High. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 983 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Bit/Field Name Type Reset 6 PFLTAEN R/W 0 Description Power Fault Action Enable This bit specifies whether a USB power fault triggers any automatic corrective action regarding the driven state of the USB0EPEN signal. Value Description 0 Disabled USB0EPEN is controlled by the combination of the EPEN and EPENDE bits. 1 Enabled The USB0EPEN output is automatically changed to the state specified by the PFLTACT field. 5 PFLTSEN R/W 0 Power Fault Sense This bit specifies the logical sense of the USB0PFLT input signal that indicates an error condition. The complementary state is the inactive state. Value Description 0 Low Fault If USB0PFLT is driven Low, the power fault is signaled internally (if enabled by the PFLTEN bit). 1 High Fault If USB0PFLT is driven High, the power fault is signaled internally (if enabled by the PFLTEN bit). 4 PFLTEN R/W 0 Power Fault Input Enable This bit specifies whether the USB0PFLT input signal is used in internal logic. Value Description 0 Not Used The USB0PFLT signal is ignored. 1 Used The USB0PFLT signal is used internally. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 984 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 2 EPENDE R/W 0 Description EPEN Drive Enable This bit specifies whether the USB0EPEN signal is driven or undriven (tristate). When driven, the signal value is specified by the EPEN field. When not driven, the EPEN field is ignored and the USB0EPEN signal is placed in a high-impedance state. Value Description 0 Not Driven The USB0EPEN signal is high impedance. 1 Driven The USB0EPEN signal is driven to the logical value specified by the value of the EPEN field. The USB0EPEN signal is undriven at reset because the sense of the external power supply enable is unknown. By adding the high-impedance state, system designers may bias the power supply enable to the disabled state using a large resistor (100 kΩ) and later configure and drive the output signal to enable the power supply. 1:0 EPEN R/W 0x0 External Power Supply Enable Configuration This bit field specifies and controls the logical value driven on the USB0EPEN signal. Value Description 0x0 Power Enable Active Low The USB0EPEN signal is driven Low if the EPENDE bit is set. 0x1 Power Enable Active High The USB0EPEN signal is driven High if the EPENDE bit is set. 0x2 Power Enable High if VBUS Low The USB0EPEN signal is driven High when the A device is not recognized. 0x3 Power Enable High if VBUS High The USB0EPEN signal is driven High when the A device is recognized. July 22, 2011 985 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 318: USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 OTG A / This 32-bit register specifies the unmasked interrupt status of the two-pin external power interface. USB External Power Control Raw Interrupt Status (USBEPCRIS) Host Base 0x4005.0000 Offset 0x404 Type RO, reset 0x0000.0000 OTG B / 31 30 29 28 27 26 25 Device 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PF RO 0 RO 0 RO 0 0 PF RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Power Fault Interrupt Status Value Description 1 A Power Fault status has been detected. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the PF bit in the USBEPCISC register. 986 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 319: USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 OTG A / This 32-bit register specifies the interrupt mask of the two-pin external power interface. USB External Power Control Interrupt Mask (USBEPCIM) Host Base 0x4005.0000 Offset 0x408 Type R/W, reset 0x0000.0000 OTG B / 31 30 29 28 27 26 25 Device 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PF R/W 0 RO 0 RO 0 0 PF RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Power Fault Interrupt Mask Value Description 1 The raw interrupt signal from a detected power fault is sent to the interrupt controller. 0 A detected power fault does not affect the interrupt status. July 22, 2011 987 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 320: USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C OTG A / Host This 32-bit register specifies the masked interrupt status of the two-pin external power interface. It also provides a method to clear the interrupt state. USB External Power Control Interrupt Status and Clear (USBEPCISC) OTG B / Base 0x4005.0000 Offset 0x40C Type R/W, reset 0x0000.0000 Device 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 PF R/W1C 0 RO 0 RO 0 0 PF RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. USB Power Fault Interrupt Status and Clear Value Description 1 The PF bits in the USBEPCRIS and USBEPCIM registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the PF bit in the USBEPCRIS register. 988 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 321: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 OTG A / Host The USBDRRIS 32-bit register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. USB Device RESUME Raw Interrupt Status (USBDRRIS) OTG B / Base 0x4005.0000 Offset 0x410 Type RO, reset 0x0000.0000 Device 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 RESUME RO 0 RO 0 RO 0 0 RESUME RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RESUME Interrupt Status Value Description 1 A RESUME status has been detected. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the RESUME bit in the USBDRISC register. July 22, 2011 989 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 322: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 OTG A / Host The USBDRIM 32-bit register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. USB Device RESUME Interrupt Mask (USBDRIM) OTG B / Base 0x4005.0000 Offset 0x414 Type R/W, reset 0x0000.0000 Device 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 RESUME R/W 0 Bit/Field Name Type Reset Description 31:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RESUME R/W 0 RESUME Interrupt Mask Value Description 1 The raw interrupt signal from a detected RESUME is sent to the interrupt controller. This bit should only be set when a SUSPEND has been detected (the SUSPEND bit in the USBIS register is set). 0 A detected RESUME does not affect the interrupt status. 990 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 323: USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 OTG A / Host The USBDRISC 32-bit register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. USB Device RESUME Interrupt Status and Clear (USBDRISC) OTG B / Base 0x4005.0000 Offset 0x418 Type W1C, reset 0x0000.0000 Device 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 RESUME R/W1C 0 RO 0 RO 0 0 RESUME RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RESUME Interrupt Status and Clear Value Description 1 The RESUME bits in the USBDRRIS and USBDRCIM registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the RESUME bit in the USBDRCRIS register. July 22, 2011 991 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 324: USB General-Purpose Control and Status (USBGPCS), offset 0x41C OTG A / USBGPCS provides the state of the internal ID signal. Note: Host OTG B / Device When used in OTG mode, USB0VBUS and USB0ID do not require any configuration as they are dedicated pins for the USB controller and directly connect to the USB connector's VBUS and ID signals. If the USB controller is used as either a dedicated Host or Device, the DEVMODOTG and DEVMOD bits in the USB General-Purpose Control and Status (USBGPCS) register can be used to connect the USB0VBUS and USB0ID inputs to fixed levels internally, freeing the PB0 and PB1 pins for GPIO use. For proper self-powered Device operation, the VBUS value must still be monitored to assure that if the Host removes VBUS, the self-powered Device disables the D+/D- pull-up resistors. This function can be accomplished by connecting a standard GPIO to VBUS. USB General-Purpose Control and Status (USBGPCS) Base 0x4005.0000 Offset 0x41C Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 DEVMODOTG DEVMOD RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 DEVMODOTG R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable Device Mode This bit enables the DEVMOD bit to control the state of the internal ID signal in OTG mode. Value Description 0 DEVMOD R/W 1 0 The mode is specified by the state of the internal ID signal. 1 This bit enables the DEVMOD bit to control the internal ID signal. Device Mode This bit specifies the state of the internal ID signal in Host mode and in OTG mode when the DEVMODOTG bit is set. In Device mode this bit is ignored (assumed set). Value Description 0 Host mode 1 Device mode 992 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 325: USB VBUS Droop Control (USBVDC), offset 0x430 OTG A / Host This 32-bit register enables a controlled masking of VBUS to compensate for any in-rush current by a Device that is connected to the Host controller. The in-rush current can cause VBUS to droop, causing the USB controller's behavior to be unexpected. The USB Host controller allows VBUS to fall lower than the VBUS Valid level (4.75 V) but not below AValid (2.0 V) for 65 microseconds without signaling a VBUSERR interrupt in the controller. Without this, any glitch on VBUS would force the USB Host controller to remove power from VBUS and then re-enumerate the Device. USB VBUS Droop Control (USBVDC) Base 0x4005.0000 Offset 0x430 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 VBDEN R/W 0 RO 0 VBDEN R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. VBUS Droop Enable Value Description 0 No effect. 1 Any changes from VBUSVALID are masked when VBUS goes below 4.75 V but not lower than 2.0 V for 65 microseconds. During this time, the VBUS state indicates VBUSVALID. July 22, 2011 993 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 326: USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS), offset 0x434 OTG A / Host This 32-bit register specifies the unmasked interrupt status of the VBUS droop limit of 65 microseconds. USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS) Base 0x4005.0000 Offset 0x434 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 VD RO 0 RO 0 0 VD RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. VBUS Droop Raw Interrupt Status Value Description 1 A VBUS droop lasting for 65 microseconds has been detected. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the VD bit in the USBVDCISC register. 994 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 327: USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset 0x438 OTG A / This 32-bit register specifies the interrupt mask of the VBUS droop. USB VBUS Droop Control Interrupt Mask (USBVDCIM) Host Base 0x4005.0000 Offset 0x438 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 VD R/W 0 RO 0 0 VD RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. VBUS Droop Interrupt Mask Value Description 1 The raw interrupt signal from a detected VBUS droop is sent to the interrupt controller. 0 A detected VBUS droop does not affect the interrupt status. July 22, 2011 995 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 328: USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC), offset 0x43C OTG A / Host This 32-bit register specifies the masked interrupt status of the VBUS droop and provides a method to clear the interrupt state. USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC) Base 0x4005.0000 Offset 0x43C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 VD R/W1C 0 RO 0 0 VD RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. VBUS Droop Interrupt Status and Clear Value Description 1 The VD bits in the USBVDCRIS and USBVDCIM registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the VD bit in the USBVDCRIS register. 996 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 329: USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset 0x444 This 32-bit register specifies whether the unmasked interrupt status of the ID value is valid. OTG USB ID Valid Detect Raw Interrupt Status (USBIDVRIS) Base 0x4005.0000 Offset 0x444 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 ID RO 0 RO 0 0 ID RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ID Valid Detect Raw Interrupt Status Value Description 1 A valid ID has been detected. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the ID bit in the USBIDVISC register. July 22, 2011 997 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 330: USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448 This 32-bit register specifies the interrupt mask of the ID valid detection. OTG USB ID Valid Detect Interrupt Mask (USBIDVIM) Base 0x4005.0000 Offset 0x448 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 ID R/W 0 RO 0 ID Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ID Valid Detect Interrupt Mask Value Description 1 The raw interrupt signal from a detected ID valid is sent to the interrupt controller. 0 A detected ID valid does not affect the interrupt status. 998 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 331: USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C This 32-bit register specifies the masked interrupt status of the ID valid detect. It also provides a method to clear the interrupt state. OTG USB ID Valid Detect Interrupt Status and Clear (USBIDVISC) Base 0x4005.0000 Offset 0x44C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 ID R/W1C 0 RO 0 0 ID RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ID Valid Detect Interrupt Status and Clear Value Description 1 The ID bits in the USBIDVRIS and USBIDVIM registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the ID bit in the USBIDVRIS register. July 22, 2011 999 Texas Instruments-Production Data Universal Serial Bus (USB) Controller Register 332: USB DMA Select (USBDMASEL), offset 0x450 OTG A / Host OTG B / This 32-bit register specifies which endpoints are mapped to the 6 allocated µDMA channels, see Table 7-1 on page 335 for more information on channel assignments. USB DMA Select (USBDMASEL) Base 0x4005.0000 Offset 0x450 Type R/W, reset 0x0033.2211 Device 31 30 29 28 RO 0 RO 0 RO 0 RO 0 15 14 13 R/W 0 R/W 0 27 26 25 24 23 22 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 12 11 10 9 8 7 6 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset R/W 1 20 19 18 R/W 1 R/W 1 R/W 0 R/W 0 R/W 1 R/W 1 5 4 3 2 1 0 R/W 1 R/W 0 R/W 0 DMACTX DMABTX Type Reset 21 DMABRX R/W 1 16 DMACRX DMAATX R/W 0 17 DMAARX R/W 0 R/W 1 Bit/Field Name Type Reset Description 31:24 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 DMACTX R/W 0x3 DMA C TX Select Specifies the TX mapping of the third USB endpoint on µDMA channel 5 (primary assignment). Value Description 0x0 reserved 0x1 Endpoint 1 TX 0x2 Endpoint 2 TX 0x3 Endpoint 3 TX 0x4 Endpoint 4 TX 0x5 Endpoint 5 TX 0x6 Endpoint 6 TX 0x7 Endpoint 7 TX 0x8 Endpoint 8 TX 0x9 Endpoint 9 TX 0xA Endpoint 10 TX 0xB Endpoint 11 TX 0xC Endpoint 12 TX 0xD Endpoint 13 TX 0xE Endpoint 14 TX 0xF Endpoint 15 TX 1000 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 19:16 DMACRX R/W 0x3 Description DMA C RX Select Specifies the RX and TX mapping of the third USB endpoint on µDMA channel 4 (primary assignment). Value Description 15:12 DMABTX R/W 0x2 0x0 reserved 0x1 Endpoint 1 RX 0x2 Endpoint 2 RX 0x3 Endpoint 3 RX 0x4 Endpoint 4 RX 0x5 Endpoint 5 RX 0x6 Endpoint 6 RX 0x7 Endpoint 7 RX 0x8 Endpoint 8 RX 0x9 Endpoint 9 RX 0xA Endpoint 10 RX 0xB Endpoint 11 RX 0xC Endpoint 12 RX 0xD Endpoint 13 RX 0xE Endpoint 14 RX 0xF Endpoint 15 RX DMA B TX Select Specifies the TX mapping of the second USB endpoint on µDMA channel 3 (primary assignment). Same bit definitions as the DMACTX field. 11:8 DMABRX R/W 0x2 DMA B RX Select Specifies the RX mapping of the second USB endpoint on µDMA channel 2 (primary assignment). Same bit definitions as the DMACRX field. 7:4 DMAATX R/W 0x1 DMA A TX Select Specifies the TX mapping of the first USB endpoint on µDMA channel 1 (primary assignment). Same bit definitions as the DMACTX field. 3:0 DMAARX R/W 0x1 DMA A RX Select Specifies the RX mapping of the first USB endpoint on µDMA channel 0 (primary assignment). Same bit definitions as the DMACRX field. July 22, 2011 1001 Texas Instruments-Production Data Analog Comparators 19 Analog Comparators An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. Note: Not all comparators have the option to drive an output pin. See “Signal Description” on page 1003 for more information. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board. In addition, the comparator can signal the application via interrupts or trigger the start of a sample sequence in the ADC. The interrupt generation and ADC triggering logic is separate and independent. This flexibility means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. ® The Stellaris LM3S9L71 microcontroller provides two independent integrated analog comparators with the following functions: ■ Compare external pin input to external pin input or to internal programmable voltage reference ■ Compare a test voltage against any one of the following voltages: – An individual external reference voltage – A shared single external reference voltage – A shared internal reference voltage 19.1 Block Diagram Figure 19-1. Analog Comparator Module Block Diagram C1- -ve input C1+ +ve input Comparator 1 output +ve input (alternate) trigger ACCTL1 C1o trigger ACSTAT1 interrupt reference input C0- -ve input C0+ +ve input Comparator 0 output +ve input (alternate) trigger ACCTL0 C0o trigger ACSTAT0 interrupt reference input Voltage Ref internal bus ACREFCTL Interrupt Control ACRIS ACMIS ACINTEN interrupt 1002 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 19.2 Signal Description The following table lists the external signals of the Analog Comparators and describes the function of each. The Analog Comparator output signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for the Analog Comparator signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the Analog Comparator function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the Analog Comparator signal to the specified GPIO port pin. The positive and negative input signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. Table 19-1. Signals for Analog Comparators (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment PB6 a Pin Type Buffer Type Description I Analog Analog comparator 0 positive input. Analog comparator 0 negative input. C0+ 90 C0- 92 PB4 I Analog C0o 24 58 90 91 100 PC5 (3) PF4 (2) PB6 (3) PB5 (1) PD7 (2) O TTL C1+ 24 PC5 I Analog Analog comparator 1 positive input. C1- 91 PB5 I Analog Analog comparator 1 negative input. C1o 2 22 24 46 84 PE6 (2) PC7 (7) PC5 (2) PF5 (2) PH2 (2) O TTL Analog comparator 0 output. Analog comparator 1 output. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 19-2. Signals for Analog Comparators (108BGA) Pin Name C0+ Pin Number Pin Mux / Pin Assignment A7 PB6 a Pin Type Buffer Type I Analog Analog comparator 0 positive input. Analog comparator 0 negative input. C0- A6 PB4 I Analog C0o M1 L9 A7 B7 A2 PC5 (3) PF4 (2) PB6 (3) PB5 (1) PD7 (2) O TTL Description Analog comparator 0 output. C1+ M1 PC5 I Analog Analog comparator 1 positive input. C1- B7 PB5 I Analog Analog comparator 1 negative input. C1o A1 L2 M1 L8 D11 PE6 (2) PC7 (7) PC5 (2) PF5 (2) PH2 (2) O TTL Analog comparator 1 output. a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 22, 2011 1003 Texas Instruments-Production Data Analog Comparators 19.3 Functional Description The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT. VIN- < VIN+, VOUT = 1 VIN- > VIN+, VOUT = 0 As shown in Figure 19-2 on page 1004, the input source for VIN- is an external input, Cn-. In addition to an external input, Cn+, input sources for VIN+ can be the C0+ or an internal reference, VIREF. Figure 19-2. Structure of Comparator Unit - ve input + ve input (alternate) reference input 0 output CINV 1 IntGen 2 TrigGen internal bus ACCTL ACSTAT trigger interrupt + ve input A comparator is configured through two status/control registers, Analog Comparator Control (ACCTL) and Analog Comparator Status (ACSTAT). The internal reference is configured through one control register, Analog Comparator Reference Voltage Control (ACREFCTL). Interrupt status and control are configured through three registers, Analog Comparator Masked Interrupt Status (ACMIS), Analog Comparator Raw Interrupt Status (ACRIS), and Analog Comparator Interrupt Enable (ACINTEN). Typically, the comparator output is used internally to generate an interrupt as controlled by the ISEN bit in the ACCTL register. The output may also be used to drive an external pin, Co or generate an analog-to-digital converter (ADC) trigger. Important: The ASRCP bits in the ACCTL register must be set before using the analog comparators. 19.3.1 Internal Reference Programming The structure of the internal reference is shown in Figure 19-3 on page 1005. The internal reference is controlled by a single configuration register (ACREFCTL). Table 19-3 on page 1005 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally (VIREF). 1004 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 19-3. Comparator Internal Reference Structure 8R VDDA 8R R R R ••• EN 15 14 ••• 1 0 Decoder VREF internal reference VIREF RNG Table 19-3. Internal Reference Voltage and ACREFCTL Field Values ACREFCTL Register EN Bit Value EN=0 RNG Bit Value Output Reference Voltage Based on VREF Field Value RNG=X 0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0 for the least noisy ground reference. RNG=0 Total resistance in ladder is 31 R. RVREF RT RVREF VIREF = VDDA × RVREF RT + 8) VIREF = VDDA × (VREF VIREF = VDDA × RT 31 + 8) (VREF VIREF = VDDA × (VREF + 8) RVREF 31 × VREF V DDA 0DDA .85× .106 IREF = VIREF = V V ×+R0VREF RT 31 IREF = VDDA × VIREF V = 0.85 +R0VREF R.T 106 × VREF IREF = DDA V V ×+R0VREF V IREF = 0 . 85 ( ) VREF VIREF = VDDA × VREF R.T 106+ ×8VREF VIREF = VDDA × R R T IREF = VDDA × (VREF VIREF 31 + 8) V = VDDAreference × RVREF RTin 31 The range this mode is 0.85-2.448 V. IREF of=internal DDA × VREF V V VIREF = VDDA × (VREF + 8) R T Total resistance in ladder is 23 R. VIREF = V 0DDA .85×+VREF 023 .106 × VREF 31 × VREF VIREF = V 0DDA .85×+VREF 0.106 23 VREF R × × VREF V IREF = V 0DDA .143 IREF = V 23 VIREF = V 0DDA .85×+R0VREF .T 106 × VREF IREF = VIREF × ×RVREF V = V 0DDA .143 RVREF T R V IREF = 0.143 VREF ×VREF IREF = VDDA × V VIREF = VDDA × VREF RT VIREF = VDDA × 23 23 VREF × × VREF VIREF = V 0DDA .143 VIREF = 0.143 × 23 VREF VIREF = VDDA × EN=1 RNG=1 VIREF = 0.143 × VREF The range of internal reference for this mode is 0-2.152 V. July 22, 2011 1005 Texas Instruments-Production Data Analog Comparators 19.4 Initialization and Configuration The following example shows how to configure an analog comparator to read back its output value from an internal register. 1. Enable the analog comparator clock by writing a value of 0x0010.0000 to the RCGC1 register in the System Control module (see page 272). 2. Enable the clock to the appropriate GPIO modules via the RCGC2 register (see page 281). To find out which GPIO ports to enable, refer to Table 23-5 on page 1145. 3. In the GPIO module, enable the GPIO port/pin associated with the input signals as GPIO inputs. To determine which GPIO to configure, see Table 23-4 on page 1137. 4. Configure the PMCn fields in the GPIOPCTL register to assign the analog comparator output signals to the appropriate pins (see page 434 and Table 23-5 on page 1145). 5. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the value 0x0000.030C. 6. Configure the comparator to use the internal voltage reference and to not invert the output by writing the ACCTLn register with the value of 0x0000.040C. 7. Delay for 10 µs. 8. Read the comparator output value by reading the ACSTATn register’s OVAL value. Change the level of the comparator negative input signal C- to see the OVAL value change. 19.5 Register Map Table 19-4 on page 1006 lists the comparator registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Analog Comparator base address of 0x4003.C000. Note that the analog comparator clock must be enabled before the registers can be programmed (see page 272). There must be a delay of 3 system clocks after the analog comparator module clock is enabled before any analog comparator module registers are accessed. Table 19-4. Analog Comparators Register Map Description See page 0x0000.0000 Analog Comparator Masked Interrupt Status 1008 RO 0x0000.0000 Analog Comparator Raw Interrupt Status 1009 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 1010 0x010 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 1011 0x020 ACSTAT0 RO 0x0000.0000 Analog Comparator Status 0 1012 0x024 ACCTL0 R/W 0x0000.0000 Analog Comparator Control 0 1013 0x040 ACSTAT1 RO 0x0000.0000 Analog Comparator Status 1 1012 0x044 ACCTL1 R/W 0x0000.0000 Analog Comparator Control 1 1013 Offset Name Type Reset 0x000 ACMIS R/W1C 0x004 ACRIS 0x008 1006 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 19.6 Register Descriptions The remainder of this section lists and describes the Analog Comparator registers, in numerical order by address offset. July 22, 2011 1007 Texas Instruments-Production Data Analog Comparators Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 This register provides a summary of the interrupt status (masked) of the comparators. Analog Comparator Masked Interrupt Status (ACMIS) Base 0x4003.C000 Offset 0x000 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 IN1 R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator 1 Masked Interrupt Status Value Description 1 The IN1 bits in the ACRIS register and the ACINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the IN1 bit in the ACRIS register. 0 IN0 R/W1C 0 Comparator 0 Masked Interrupt Status Value Description 1 The IN0 bits in the ACRIS register and the ACINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the IN0 bit in the ACRIS register. 1008 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 This register provides a summary of the interrupt status (raw) of the comparators. The bits in this register must be enabled to generate interrupts using the ACINTEN register. Analog Comparator Raw Interrupt Status (ACRIS) Base 0x4003.C000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 IN1 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator 1 Interrupt Status Value Description 1 Comparator 1 has generated an interruptfor an event as configured by the ISEN bit in the ACCTL1 register. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN1 bit in the ACMIS register. 0 IN0 RO 0 Comparator 0 Interrupt Status Value Description 1 Comparator 0 has generated an interrupt for an event as configured by the ISEN bit in the ACCTL0 register. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the IN0 bit in the ACMIS register. July 22, 2011 1009 Texas Instruments-Production Data Analog Comparators Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 This register provides the interrupt enable for the comparators. Analog Comparator Interrupt Enable (ACINTEN) Base 0x4003.C000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 IN1 IN0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset Description 31:2 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 IN1 R/W 0 Comparator 1 Interrupt Enable Value Description 0 IN0 R/W 0 1 The raw interrupt signal comparator 1 is sent to the interrupt controller. 0 A comparator 1 interrupt does not affect the interrupt status. Comparator 0 Interrupt Enable Value Description 1 The raw interrupt signal comparator 0 is sent to the interrupt controller. 0 A comparator 0 interrupt does not affect the interrupt status. 1010 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 This register specifies whether the resistor ladder is powered on as well as the range and tap. Analog Comparator Reference Voltage Control (ACREFCTL) Base 0x4003.C000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 1 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 9 8 EN RNG R/W 0 R/W 0 Bit/Field Name Type Reset 31:10 reserved RO 0x0000.0 9 EN R/W 0 reserved RO 0 RO 0 RO 0 VREF RO 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Resistor Ladder Enable Value Description 0 The resistor ladder is unpowered. 1 Powers on the resistor ladder. The resistor ladder is connected to VDDA. This bit is cleared at reset so that the internal reference consumes the least amount of power if it is not used. 8 RNG R/W 0 Resistor Ladder Range Value Description 0 The resistor ladder has a total resistance of 31 R. 1 The resistor ladder has a total resistance of 23 R. 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 VREF R/W 0x0 Resistor Ladder Voltage Ref The VREF bit field specifies the resistor ladder tap that is passed through an analog multiplexer. The voltage corresponding to the tap position is the internal reference voltage available for comparison. See Table 19-3 on page 1005 for some output reference voltage examples. July 22, 2011 1011 Texas Instruments-Production Data Analog Comparators Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 These registers specify the current output value of the comparator. Analog Comparator Status 0 (ACSTAT0) Base 0x4003.C000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 OVAL reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 OVAL RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator Output Value Value Description 0 VIN- > VIN+ 1 VIN- < VIN+ VIN - is the voltage on the Cn- pin. VIN+ is the voltage on the Cn+ pin, the C0+ pin, or the internal voltage reference (VIREF) as defined by the ASRCP bit in the ACCTL register. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1012 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 These registers configure the comparator’s input and output. Analog Comparator Control 0 (ACCTL0) Base 0x4003.C000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 reserved TSLVAL CINV reserved RO 0 R/W 0 R/W 0 RO 0 reserved Type Reset reserved Type Reset TOEN RO 0 RO 0 ASRCP R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11 TOEN R/W 0 TSEN R/W 0 ISLVAL R/W 0 R/W 0 ISEN R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Trigger Output Enable Value Description 10:9 ASRCP R/W 0x0 0 ADC events are suppressed and not sent to the ADC. 1 ADC events are sent to the ADC. Analog Source Positive The ASRCP field specifies the source of input voltage to the VIN+ terminal of the comparator. The encodings for this field are as follows: Value Description 0x0 Pin value of Cn+ 0x1 Pin value of C0+ 0x2 Internal voltage reference (VIREF) 0x3 Reserved 8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 TSLVAL R/W 0 Trigger Sense Level Value Value Description 0 An ADC event is generated if the comparator output is Low. 1 An ADC event is generated if the comparator output is High. July 22, 2011 1013 Texas Instruments-Production Data Analog Comparators Bit/Field Name Type Reset 6:5 TSEN R/W 0x0 Description Trigger Sense The TSEN field specifies the sense of the comparator output that generates an ADC event. The sense conditioning is as follows: Value Description 4 ISLVAL R/W 0 0x0 Level sense, see TSLVAL 0x1 Falling edge 0x2 Rising edge 0x3 Either edge Interrupt Sense Level Value Value Description 3:2 ISEN R/W 0x0 0 An interrupt is generated if the comparator output is Low. 1 An interrupt is generated if the comparator output is High. Interrupt Sense The ISEN field specifies the sense of the comparator output that generates an interrupt. The sense conditioning is as follows: Value Description 1 CINV R/W 0 0x0 Level sense, see ISLVAL 0x1 Falling edge 0x2 Rising edge 0x3 Either edge Comparator Output Invert Value Description 0 reserved RO 0 0 The output of the comparator is unchanged. 1 The output of the comparator is inverted prior to being processed by hardware. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1014 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 20 Pulse Width Modulator (PWM) Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. ® The Stellaris microcontroller contains one PWM module, with three PWM generator blocks and a control block, for a total of 6 PWM outputs. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. Each PWM generator block produces two PWM signals that share the same timer and frequency and can either be programmed with independent actions or as a single pair of complementary signals with dead-band delays inserted. The output signals, pwmA' and pwmB', of the PWM generation blocks are managed by the output control block before being passed to the device pins as PWM0 and PWM1 or PWM2 and PWM3, and so on. The Stellaris PWM module provides a great deal of flexibility and can generate simple PWM signals, such as those required by a simple charge pump as well as paired PWM signals with dead-band delays, such as those required by a half-H bridge driver. Each PWM generator block has the following features: ■ Four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled ■ One 16-bit counter – Runs in Down or Up/Down mode – Output frequency controlled by a 16-bit load value – Load value updates can be synchronized – Produces output signals at zero and load value ■ Two PWM comparators – Comparator value updates can be synchronized – Produces output signals on match ■ PWM signal generator – Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals – Produces two independent PWM signals ■ Dead-band generator – Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge – Can be bypassed, leaving input PWM signals unmodified July 22, 2011 1015 Texas Instruments-Production Data Pulse Width Modulator (PWM) ■ Can initiate an ADC sample sequence The control block determines the polarity of the PWM signals and which signals are passed through to the pins. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. The PWM control block has the following options: ■ PWM output enable of each PWM signal ■ Optional output inversion of each PWM signal (polarity control) ■ Optional fault handling for each PWM signal ■ Synchronization of timers in the PWM generator blocks ■ Synchronization of timer/comparator updates across the PWM generator blocks ■ Synchronization of PWM output enables across the PWM generator blocks ■ Interrupt status summary of the PWM generator blocks ■ Extended PWM fault handling, with multiple fault signals, programmable polarities, and filtering ■ PWM generators can be operated independently or synchronized with other generators 20.1 Block Diagram Figure 20-1 on page 1017 provides the Stellaris PWM module diagram and Figure 20-2 on page 1017 provides a more detailed diagram of a Stellaris PWM generator. The LM3S9L71 controller contains three generator blocks that generate six independent PWM signals or three paired PWM signals with dead-band delays inserted. 1016 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 20-1. PWM Module Diagram PWM Clock pwm0A’ Triggers / Faults System Clock PWM Generator 0 Control and Status PWM 0 pwm0B’ PWM 1 pwm0fault PWM PWMCTL PWMSYNC PWMSTATUS pwm1A’ PWM Generator 1 Output pwm1fault Control PWM 3 Logic Interrupt pwm2A’ Interrupts PWM 2 pwm1B’ PWMINTEN PWMRIS PWMISC PWM Generator 2 PWM 4 pwm2B’ PWM 5 pwm2fault Triggers Output PWMENABLE PWMINVERT PWMFAULT PWMFAULTVAL PWMENUPD Figure 20-2. PWM Generator Block Diagram PWM Generator Block Interrupts / Triggers Control PWMnLOAD PWMnCOUNT PWMnFLTSRC0 PWMnFLTSRC1 PWMnMINFLTPER PWMnFLTSEN PWMnFLTSTAT0 PWMnFLTSTAT1 PWMnINTEN PWMnRIS PWMnISC PWMnCTL Timer Fault Condition Interrupt and Trigger Generator load dir pwmfault Signal Generator pwmA pwmB PWM Clock 20.2 Fault(s) zero Comparators PWMnCMPA PWMnCMPB Digital Trigger(s) cmpA cmpB PWMnGENA PWMnGENB Dead-Band Generator PWMnDBCTL PWMnDBRISE PWMnDBFALL pwmA’ pwmB’ Signal Description The following table lists the external signals of the PWM module and describes the function of each. The PWM controller signals are alternate functions for some GPIO signals and default to be GPIO July 22, 2011 1017 Texas Instruments-Production Data Pulse Width Modulator (PWM) signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these PWM signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the PWM function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the PWM signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. Table 20-1. Signals for PWM (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description Fault0 6 16 17 39 58 65 75 83 99 PE4 (4) PG3 (8) PG2 (4) PJ2 (10) PF4 (4) PB3 (2) PE1 (3) PH3 (2) PD6 (1) I TTL PWM Fault 0. Fault1 37 40 41 42 90 PG6 (8) PG5 (5) PG4 (4) PF7 (9) PB6 (4) I TTL PWM Fault 1. Fault2 16 24 63 PG3 (4) PC5 (4) PH5 (10) I TTL PWM Fault 2. Fault3 65 84 PB3 (4) PH2 (4) I TTL PWM Fault 3. PWM0 10 14 17 19 34 47 PD0 (1) PJ0 (10) PG2 (1) PG0 (2) PA6 (4) PF0 (3) O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 11 16 18 35 61 87 PD1 (1) PG3 (1) PG1 (2) PA7 (4) PF1 (3) PJ1 (10) O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 12 60 66 86 PD2 (3) PF2 (4) PB0 (2) PH0 (2) O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 13 59 67 85 PD3 (3) PF3 (4) PB1 (2) PH1 (2) O TTL PWM 3. This signal is controlled by PWM Generator 1. 1018 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 20-1. Signals for PWM (100LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description PWM4 2 19 28 34 60 62 74 86 PE6 (1) PG0 (4) PA2 (4) PA6 (5) PF2 (2) PH6 (10) PE0 (1) PH0 (9) O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 1 15 18 29 35 59 75 85 PE7 (1) PH7 (10) PG1 (4) PA3 (4) PA7 (5) PF3 (2) PE1 (1) PH1 (9) O TTL PWM 5. This signal is controlled by PWM Generator 2. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 20-2. Signals for PWM (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description Fault0 B2 J2 J1 K6 L9 E11 A12 D10 A3 PE4 (4) PG3 (8) PG2 (4) PJ2 (10) PF4 (4) PB3 (2) PE1 (3) PH3 (2) PD6 (1) I TTL PWM Fault 0. Fault1 L7 M7 K3 K4 A7 PG6 (8) PG5 (5) PG4 (4) PF7 (9) PB6 (4) I TTL PWM Fault 1. Fault2 J2 M1 F10 PG3 (4) PC5 (4) PH5 (10) I TTL PWM Fault 2. Fault3 E11 D11 PB3 (4) PH2 (4) I TTL PWM Fault 3. PWM0 G1 F3 J1 K1 L6 M9 PD0 (1) PJ0 (10) PG2 (1) PG0 (2) PA6 (4) PF0 (3) O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 G2 J2 K2 M6 H12 B6 PD1 (1) PG3 (1) PG1 (2) PA7 (4) PF1 (3) PJ1 (10) O TTL PWM 1. This signal is controlled by PWM Generator 0. July 22, 2011 1019 Texas Instruments-Production Data Pulse Width Modulator (PWM) Table 20-2. Signals for PWM (108BGA) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description PWM2 H2 J11 E12 C9 PD2 (3) PF2 (4) PB0 (2) PH0 (2) O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 H1 J12 D12 C8 PD3 (3) PF3 (4) PB1 (2) PH1 (2) O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 A1 K1 M4 L6 J11 G3 B11 C9 PE6 (1) PG0 (4) PA2 (4) PA6 (5) PF2 (2) PH6 (10) PE0 (1) PH0 (9) O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 B1 H3 K2 L4 M6 J12 A12 C8 PE7 (1) PH7 (10) PG1 (4) PA3 (4) PA7 (5) PF3 (2) PE1 (1) PH1 (9) O TTL PWM 5. This signal is controlled by PWM Generator 2. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 20.3 Functional Description 20.3.1 PWM Timer The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used for generating center-aligned PWM signals. The timers output three signals that are used in the PWM generation process: the direction signal (this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero pulse is immediately followed by the load pulse. In the figures in this chapter, these signals are labelled "dir," "zero," and "load." 20.3.2 PWM Comparators Each PWM generator has two comparators that monitor the value of the counter; when either comparator matches the counter, they output a single-clock-cycle-width High pulse, labelled "cmpA" and "cmpB" in the figures in this chapter. When in Count-Up/Down mode, these comparators match both when counting up and when counting down, and thus are qualified by the counter direction signal. These qualified pulses are used in the PWM generation process. If either comparator match value is greater than the counter load value, then that comparator never outputs a High pulse. 1020 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 20-3 on page 1021 shows the behavior of the counter and the relationship of these pulses when the counter is in Count-Down mode. Figure 20-4 on page 1022 shows the behavior of the counter and the relationship of these pulses when the counter is in Count-Up/Down mode. In these figures, the following definitions apply: ■ LOAD is the value in the PWMnLOAD register ■ COMPA is the value in the PWMnCMPA register ■ COMPB is the value in the PWMnCMPB register ■ 0 is the value zero ■ load is the internal signal that has a single-clock-cycle-width High pulse when the counter is equal to the load value ■ zero is the internal signal that has a single-clock-cycle-width High pulse when the counter is zero ■ cmpA is the internal signal that has a single-clock-cycle-width High pulse when the counter is equal to COMPA ■ cmpB is the internal signal that has a single-clock-cycle-width High pulse when the counter is equal to COMPB ■ dir is the internal signal that indicates the count direction Figure 20-3. PWM Count-Down Mode LOAD COMPA COMPB 0 load zero cmpA cmpB dir BDown ADown July 22, 2011 1021 Texas Instruments-Production Data Pulse Width Modulator (PWM) Figure 20-4. PWM Count-Up/Down Mode LOAD COMPA COMPB 0 load zero cmpA cmpB dir BUp AUp 20.3.3 BDown ADown PWM Signal Generator Each PWM generator takes the load, zero, cmpA, and cmpB pulses (qualified by the dir signal) and generates two internal PWM signals, pwmA and pwmB. In Count-Down mode, there are four events that can affect these signals: zero, load, match A down, and match B down. In Count-Up/Down mode, there are six events that can affect these signals: zero, load, match A down, match A up, match B down, and match B up. The match A or match B events are ignored when they coincide with the zero or load events. If the match A and match B events coincide, the first signal, pwmA, is generated based only on the match A event, and the second signal, pwmB, is generated based only on the match B event. For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be used to generate a pair of PWM signals of various positions and duty cycles, which do or do not overlap. Figure 20-5 on page 1022 shows the use of Count-Up/Down mode to generate a pair of center-aligned, overlapped PWM signals that have different duty cycles. This figure shows the pwmA and pwmB signals before they have passed through the dead-band generator. Figure 20-5. PWM Generation Example In Count-Up/Down Mode LOAD COMPA COMPB 0 pwmA pwmB In this example, the first generator is set to drive High on match A up, drive Low on match A down, and ignore the other four events. The second generator is set to drive High on match B up, drive Low on match B down, and ignore the other four events. Changing the value of comparator A changes the duty cycle of the pwmA signal, and changing the value of comparator B changes the duty cycle of the pwmB signal. 1022 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 20.3.4 Dead-Band Generator The pwmA and pwmB signals produced by each PWM generator are passed to the dead-band generator. If the dead-band generator is disabled, the PWM signals simply pass through to the pwmA' and pwmB' signals unmodified. If the dead-band generator is enabled, the pwmB signal is lost and two PWM signals are generated based on the pwmA signal. The first output PWM signal, pwmA' is the pwmA signal with the rising edge delayed by a programmable amount. The second output PWM signal, pwmB', is the inversion of the pwmA signal with a programmable delay added between the falling edge of the pwmA signal and the rising edge of the pwmB' signal. The resulting signals are a pair of active High signals where one is always High, except for a programmable amount of time at transitions where both are Low. These signals are therefore suitable for driving a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the power electronics. Figure 20-6 on page 1023 shows the effect of the dead-band generator on the pwmA signal and the resulting pwmA' and pwmB' signals that are transmitted to the output control block. Figure 20-6. PWM Dead-Band Generator pwmA pwmA’ pwmB’ Rising Edge Delay 20.3.5 Falling Edge Delay Interrupt/ADC-Trigger Selector Each PWM generator also takes the same four (or six) counter events and uses them to generate an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a source for an interrupt; when any of the selected events occur, an interrupt is generated. Additionally, the same event, a different event, the same set of events, or a different set of events can be selected as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position within the pwmA or pwmB signal. Note that interrupts and ADC triggers are based on the raw events; delays in the PWM signal edges caused by the dead-band generator are not taken into account. 20.3.6 Synchronization Methods The PWM module provides three PWM generators, each providing two PWM outputs that may be used in a wide variety of applications. Generally speaking, the PWM is used in one of two categories of operation: ■ Unsynchronized. The PWM generator and its two output signals are used alone, independent of other PWM generators. ■ Synchronized. The PWM generator and its two outputs signals are used in conjunction with other PWM generators using a common, unified time base. If multiple PWM generators are configured with the same counter load value, synchronization can be used to guarantee that they also have the same count value (the PWM generators must be configured before they are synchronized). With this feature, more than two PWMn signals can be produced with a known relationship between the edges of those signals because the counters always have the same values. Other states in the module provide mechanisms to maintain the common time base and mutual synchronization. July 22, 2011 1023 Texas Instruments-Production Data Pulse Width Modulator (PWM) The counter in a PWM generator can be reset to zero by writing the PWM Time Base Sync (PWMSYNC) register and setting the SYNCn bit associated with the generator. Multiple PWM generators can be synchronized together by setting all necessary SYNCn bits in one access. For example, setting the SYNC0 and SYNC1 bits in the PWMSYNC register causes the counters in PWM generators 0 and 1 to reset together. Additional synchronization can occur between multiple PWM generators by updating register contents in one of the following three ways: ■ Immediately. The write value has immediate effect, and the hardware reacts immediately. ■ Locally Synchronized. The write value does not affect the logic until the counter reaches the value zero at the end of the PWM cycle. In this case, the effect of the write is deferred, providing a guaranteed defined behavior and preventing overly short or overly long output PWM pulses. ■ Globally Synchronized. The write value does not affect the logic until two sequential events have occurred: (1) the Update mode for the generator function is programmed for global synchronization in the PWMnCTL register, and (2) the counter reaches zero at the end of the PWM cycle. In this case, the effect of the write is deferred until the end of the PWM cycle following the end of all updates. This mode allows multiple items in multiple PWM generators to be updated simultaneously without odd effects during the update; everything runs from the old values until a point at which they all run from the new values. The Update mode of the load and comparator match values can be individually configured in each PWM generator block. It typically makes sense to use the synchronous update mechanism across PWM generator blocks when the timers in those blocks are synchronized, although this is not required in order for this mechanism to function properly. The following registers provide either local or global synchronization based on the state of various Update mode bits and fields in the PWMnCTL register (LOADUPD; CMPAUPD; CMPBUPD): ■ Generator Registers: PWMnLOAD, PWMnCMPA, and PWMnCMPB The following registers default to immediate update, but are provided with the optional functionality of synchronously updating rather than having all updates take immediate effect: ■ Module-Level Register: PWMENABLE (based on the state of the ENUPDn bits in the PWMENUPD register). ■ Generator Register: PWMnGENA, PWMnGENB, PWMnDBCTL, PWMnDBRISE, and PWMnDBFALL (based on the state of various Update mode bits and fields in the PWMnCTL register (GENAUPD; GENBUPD; DBCTLUPD; DBRISEUPD; DBFALLUPD)). All other registers are considered statically provisioned for the execution of an application or are used dynamically for purposes unrelated to maintaining synchronization and therefore do not need synchronous update functionality. 20.3.7 Fault Conditions A fault condition is one in which the controller must be signaled to stop normal PWM function and then set the PWMn signals to a safe state. Two basic situations cause fault conditions: ■ The microcontroller is stalled and cannot perform the necessary computation in the time required for motion control ■ An external error or event is detected 1024 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller The PWM generator can use the following inputs to generate a fault condition, including: ■ FAULTn pin assertion ■ A stall of the controller generated by the debugger ■ The trigger of an ADC digital comparator Fault conditions are calculated on a per-PWM generator basis. Each PWM generator configures the necessary conditions to indicate a fault condition exists. This method allows the development of applications with dependent and independent control. Four fault input pins (FAULT0-FAULT3). These inputs may be used with circuits that generate an active High or active Low signal to indicate an error condition. A FAULTn pins may be individually programmed for the appropriate logic sense using the PWMnFLTSEN register. The PWM generator's mode control, including fault condition handling, is provided in the PWMnCTL register. This register determines whether the input or a combination of FAULTn input signals and/or digital comparator triggers (as configured by the PWMnFLTSRC0 and PWMnFLTSRC1 registers) is used to generate a fault condition. The PWMnCTL register also selects whether the fault condition is maintained as long as the external condition lasts or if it is latched until the fault condition until cleared by software. Finally, this register also enables a counter that may be used to extend the period of a fault condition for external events to assure that the duration is a minimum length. The minimum fault period count is specified in the PWMnMINFLTPER register. Status regarding the specific fault cause is provided in the PWMnFLTSTAT0 and PWMnFLTSTAT1 registers. PWM generator fault conditions may be promoted to a controller interrupt using the PWMINTEN register. 20.3.8 Output Control Block The output control block takes care of the final conditioning of the pwmA' and pwmB' signals before they go to the pins as the PWMn signals. Via a single register, the PWM Output Enable (PWNENABLE) register, the set of PWM signals that are actually enabled to the pins can be modified. This function can be used, for example, to perform commutation of a brushless DC motor with a single register write (and without modifying the individual PWM generators, which are modified by the feedback control loop). In addition, the updating of the bits in the PWMENABLE register can be configured to be immediate or locally or globally synchronized to the next synchronous update using the PWM Enable Update (PWMENUPD) register. During fault conditions, the PWM output signals, PWMn, usually must be driven to safe values so that external equipment may be safely controlled. The PWMFAULT register specifies whether during a fault condition, the generated signal continues to be passed driven or to an encoding specified in the PWMFAULTVAL register. A final inversion can be applied to any of the PWMn signals, making them active Low instead of the default active High using the PWM Output Inversion (PWMINVERT). The inversion is applied even if a value has been enabled in the PWMFAULT register and specified in the PWMFAULTVAL register. In other words, if a bit is set in the PWMFAULT, PWMFAULTVAL, and PWMINVERT registers, the output on the PWMn signal is 0, not 1 as specified in the PWMFAULTVAL register. July 22, 2011 1025 Texas Instruments-Production Data Pulse Width Modulator (PWM) 20.4 Initialization and Configuration The following example shows how to initialize PWM Generator 0 with a 25-kHz frequency, a 25% duty cycle on the PWM0 pin, and a 75% duty cycle on the PWM1 pin. This example assumes the system clock is 20 MHz. 1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System Control module (see page 264). 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module (see page 281). 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. To determine which GPIOs to configure, see Table 23-4 on page 1137. 4. Configure the PMCn fields in the GPIOPCTL register to assign the PWM signals to the appropriate pins (see page 434 and Table 23-5 on page 1145). 5. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000). 6. Configure the PWM generator for countdown mode with immediate updates to the parameters. ■ Write the PWM0CTL register with a value of 0x0000.0000. ■ Write the PWM0GENA register with a value of 0x0000.008C. ■ Write the PWM0GENB register with a value of 0x0000.080C. 7. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM clock source is 10 MHz; the system clock divided by 2. Thus there are 400 clock ticks per period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the LOAD field in the PWM0LOAD register to the requested period minus one. ■ Write the PWM0LOAD register with a value of 0x0000.018F. 8. Set the pulse width of the PWM0 pin for a 25% duty cycle. ■ Write the PWM0CMPA register with a value of 0x0000.012B. 9. Set the pulse width of the PWM1 pin for a 75% duty cycle. ■ Write the PWM0CMPB register with a value of 0x0000.0063. 10. Start the timers in PWM generator 0. ■ Write the PWM0CTL register with a value of 0x0000.0001. 11. Enable PWM outputs. ■ Write the PWMENABLE register with a value of 0x0000.0003. 20.5 Register Map Table 20-3 on page 1027 lists the PWM registers. The offset listed is a hexadecimal increment to the register's address, relative to the PWM module's base address: 1026 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller ■ PWM0: 0x4002.8000 Note that the PWM module clock must be enabled before the registers can be programmed (see page 264). There must be a delay of 3 system clocks after the PWM module clock is enabled before any PWM module registers are accessed. Table 20-3. PWM Register Map Description See page 0x0000.0000 PWM Master Control 1030 R/W 0x0000.0000 PWM Time Base Sync 1031 PWMENABLE R/W 0x0000.0000 PWM Output Enable 1032 0x00C PWMINVERT R/W 0x0000.0000 PWM Output Inversion 1034 0x010 PWMFAULT R/W 0x0000.0000 PWM Output Fault 1036 0x014 PWMINTEN R/W 0x0000.0000 PWM Interrupt Enable 1038 0x018 PWMRIS RO 0x0000.0000 PWM Raw Interrupt Status 1040 0x01C PWMISC R/W1C 0x0000.0000 PWM Interrupt Status and Clear 1042 0x020 PWMSTATUS RO 0x0000.0000 PWM Status 1044 0x024 PWMFAULTVAL R/W 0x0000.0000 PWM Fault Condition Value 1046 0x028 PWMENUPD R/W 0x0000.0000 PWM Enable Update 1048 0x040 PWM0CTL R/W 0x0000.0000 PWM0 Control 1051 0x044 PWM0INTEN R/W 0x0000.0000 PWM0 Interrupt and Trigger Enable 1056 0x048 PWM0RIS RO 0x0000.0000 PWM0 Raw Interrupt Status 1059 0x04C PWM0ISC R/W1C 0x0000.0000 PWM0 Interrupt Status and Clear 1061 0x050 PWM0LOAD R/W 0x0000.0000 PWM0 Load 1063 0x054 PWM0COUNT RO 0x0000.0000 PWM0 Counter 1064 0x058 PWM0CMPA R/W 0x0000.0000 PWM0 Compare A 1065 0x05C PWM0CMPB R/W 0x0000.0000 PWM0 Compare B 1066 0x060 PWM0GENA R/W 0x0000.0000 PWM0 Generator A Control 1067 0x064 PWM0GENB R/W 0x0000.0000 PWM0 Generator B Control 1070 0x068 PWM0DBCTL R/W 0x0000.0000 PWM0 Dead-Band Control 1073 0x06C PWM0DBRISE R/W 0x0000.0000 PWM0 Dead-Band Rising-Edge Delay 1074 0x070 PWM0DBFALL R/W 0x0000.0000 PWM0 Dead-Band Falling-Edge-Delay 1075 0x074 PWM0FLTSRC0 R/W 0x0000.0000 PWM0 Fault Source 0 1076 0x078 PWM0FLTSRC1 R/W 0x0000.0000 PWM0 Fault Source 1 1078 0x07C PWM0MINFLTPER R/W 0x0000.0000 PWM0 Minimum Fault Period 1081 0x080 PWM1CTL R/W 0x0000.0000 PWM1 Control 1051 Offset Name Type Reset 0x000 PWMCTL R/W 0x004 PWMSYNC 0x008 July 22, 2011 1027 Texas Instruments-Production Data Pulse Width Modulator (PWM) Table 20-3. PWM Register Map (continued) Description See page 0x0000.0000 PWM1 Interrupt and Trigger Enable 1056 RO 0x0000.0000 PWM1 Raw Interrupt Status 1059 R/W1C 0x0000.0000 PWM1 Interrupt Status and Clear 1061 PWM1LOAD R/W 0x0000.0000 PWM1 Load 1063 0x094 PWM1COUNT RO 0x0000.0000 PWM1 Counter 1064 0x098 PWM1CMPA R/W 0x0000.0000 PWM1 Compare A 1065 0x09C PWM1CMPB R/W 0x0000.0000 PWM1 Compare B 1066 0x0A0 PWM1GENA R/W 0x0000.0000 PWM1 Generator A Control 1067 0x0A4 PWM1GENB R/W 0x0000.0000 PWM1 Generator B Control 1070 0x0A8 PWM1DBCTL R/W 0x0000.0000 PWM1 Dead-Band Control 1073 0x0AC PWM1DBRISE R/W 0x0000.0000 PWM1 Dead-Band Rising-Edge Delay 1074 0x0B0 PWM1DBFALL R/W 0x0000.0000 PWM1 Dead-Band Falling-Edge-Delay 1075 0x0B4 PWM1FLTSRC0 R/W 0x0000.0000 PWM1 Fault Source 0 1076 0x0B8 PWM1FLTSRC1 R/W 0x0000.0000 PWM1 Fault Source 1 1078 0x0BC PWM1MINFLTPER R/W 0x0000.0000 PWM1 Minimum Fault Period 1081 0x0C0 PWM2CTL R/W 0x0000.0000 PWM2 Control 1051 0x0C4 PWM2INTEN R/W 0x0000.0000 PWM2 Interrupt and Trigger Enable 1056 0x0C8 PWM2RIS RO 0x0000.0000 PWM2 Raw Interrupt Status 1059 0x0CC PWM2ISC R/W1C 0x0000.0000 PWM2 Interrupt Status and Clear 1061 0x0D0 PWM2LOAD R/W 0x0000.0000 PWM2 Load 1063 0x0D4 PWM2COUNT RO 0x0000.0000 PWM2 Counter 1064 0x0D8 PWM2CMPA R/W 0x0000.0000 PWM2 Compare A 1065 0x0DC PWM2CMPB R/W 0x0000.0000 PWM2 Compare B 1066 0x0E0 PWM2GENA R/W 0x0000.0000 PWM2 Generator A Control 1067 0x0E4 PWM2GENB R/W 0x0000.0000 PWM2 Generator B Control 1070 0x0E8 PWM2DBCTL R/W 0x0000.0000 PWM2 Dead-Band Control 1073 0x0EC PWM2DBRISE R/W 0x0000.0000 PWM2 Dead-Band Rising-Edge Delay 1074 0x0F0 PWM2DBFALL R/W 0x0000.0000 PWM2 Dead-Band Falling-Edge-Delay 1075 0x0F4 PWM2FLTSRC0 R/W 0x0000.0000 PWM2 Fault Source 0 1076 0x0F8 PWM2FLTSRC1 R/W 0x0000.0000 PWM2 Fault Source 1 1078 0x0FC PWM2MINFLTPER R/W 0x0000.0000 PWM2 Minimum Fault Period 1081 0x800 PWM0FLTSEN R/W 0x0000.0000 PWM0 Fault Pin Logic Sense 1082 Offset Name Type Reset 0x084 PWM1INTEN R/W 0x088 PWM1RIS 0x08C PWM1ISC 0x090 1028 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 20-3. PWM Register Map (continued) Description See page 0x0000.0000 PWM0 Fault Status 0 1083 - 0x0000.0000 PWM0 Fault Status 1 1085 R/W 0x0000.0000 PWM1 Fault Pin Logic Sense 1082 PWM1FLTSTAT0 - 0x0000.0000 PWM1 Fault Status 0 1083 0x888 PWM1FLTSTAT1 - 0x0000.0000 PWM1 Fault Status 1 1085 0x900 PWM2FLTSEN R/W 0x0000.0000 PWM2 Fault Pin Logic Sense 1082 0x904 PWM2FLTSTAT0 - 0x0000.0000 PWM2 Fault Status 0 1083 0x908 PWM2FLTSTAT1 - 0x0000.0000 PWM2 Fault Status 1 1085 0x980 PWM3FLTSEN R/W 0x0000.0000 PWM3 Fault Pin Logic Sense 1082 Offset Name Type Reset 0x804 PWM0FLTSTAT0 - 0x808 PWM0FLTSTAT1 0x880 PWM1FLTSEN 0x884 20.6 Register Descriptions The remainder of this section lists and describes the PWM registers, in numerical order by address offset. July 22, 2011 1029 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 1: PWM Master Control (PWMCTL), offset 0x000 This register provides master control over the PWM generation blocks. PWM Master Control (PWMCTL) PWM0 base: 0x4002.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000 2 GLOBALSYNC2 R/W 0 GLOBALSYNC2 GLOBALSYNC1 GLOBALSYNC0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Update PWM Generator 2 Value Description 1 Any queued update to a load or comparator register in PWM generator 2 is applied the next time the corresponding counter becomes zero. 0 No effect. This bit automatically clears when the updates have completed; it cannot be cleared by software. 1 GLOBALSYNC1 R/W 0 Update PWM Generator 1 Value Description 1 Any queued update to a load or comparator register in PWM generator 1 is applied the next time the corresponding counter becomes zero. 0 No effect. This bit automatically clears when the updates have completed; it cannot be cleared by software. 0 GLOBALSYNC0 R/W 0 Update PWM Generator 0 Value Description 1 Any queued update to a load or comparator register in PWM generator 0 is applied the next time the corresponding counter becomes zero. 0 No effect. This bit automatically clears when the updates have completed; it cannot be cleared by software. 1030 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 This register provides a method to perform synchronization of the counters in the PWM generation blocks. Setting a bit in this register causes the specified counter to reset back to 0; setting multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed. PWM Time Base Sync (PWMSYNC) PWM0 base: 0x4002.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 SYNC2 SYNC1 SYNC0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:3 reserved RO 0x0000.000 2 SYNC2 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Reset Generator 2 Counter Value Description 1 SYNC1 R/W 0 1 Resets the PWM generator 2 counter. 0 No effect. Reset Generator 1 Counter Value Description 0 SYNC0 R/W 0 1 Resets the PWM generator 1 counter. 0 No effect. Reset Generator 0 Counter Value Description 1 Resets the PWM generator 0 counter. 0 No effect. July 22, 2011 1031 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 3: PWM Output Enable (PWMENABLE), offset 0x008 This register provides a master control of which generated pwmA' and pwmB' signals are output to the PWMn pins. By disabling a PWM output, the generation process can continue (for example, when the time bases are synchronized) without driving PWM signals to the pins. When bits in this register are set, the corresponding pwmA' or pwmB' signal is passed through to the output stage. When bits are clear, the pwmA' or pwmB' signal is replaced by a zero value which is also passed to the output stage. The PWMINVERT register controls the output stage, so if the corresponding bit is set in that register, the value seen on the PWMn signal is inverted from what is configured by the bits in this register. Updates to the bits in this register can be immediate or locally or globally synchronized to the next synchronous update as controlled by the ENUPDn fields in the PWMENUPD register. PWM Output Enable (PWMENABLE) PWM0 base: 0x4002.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 PWM5EN PWM4EN PWM3EN PWM2EN PWM1EN PWM0EN Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 PWM5EN R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM5 Output Enable Value Description 4 PWM4EN R/W 0 1 The generated pwm2B' signal is passed to the PWM5 pin. 0 The PWM5 signal has a zero value. PWM4 Output Enable Value Description 3 PWM3EN R/W 0 1 The generated pwm2A' signal is passed to the PWM4 pin. 0 The PWM4 signal has a zero value. PWM3 Output Enable Value Description 1 The generated pwm1B' signal is passed to the PWM3 pin. 0 The PWM3 signal has a zero value. 1032 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 2 PWM2EN R/W 0 Description PWM2 Output Enable Value Description 1 PWM1EN R/W 0 1 The generated pwm1A' signal is passed to the PWM2 pin. 0 The PWM2 signal has a zero value. PWM1 Output Enable Value Description 0 PWM0EN R/W 0 1 The generated pwm0B' signal is passed to the PWM1 pin. 0 The PWM1 signal has a zero value. PWM0 Output Enable Value Description 1 The generated pwm0A' signal is passed to the PWM0 pin. 0 The PWM0 signal has a zero value. July 22, 2011 1033 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C This register provides a master control of the polarity of the PWMn signals on the device pins. The pwmA' and pwmB' signals generated by the PWM generator are active High; but can be made active Low via this register. Disabled PWM channels are also passed through the output inverter (if so configured) so that inactive signals can be High. In addition, if the PWMFAULT register enables a specific value to be placed on the PWMn signals during a fault condition, that value is inverted if the corresponding bit in this register is set. PWM Output Inversion (PWMINVERT) PWM0 base: 0x4002.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 PWM5INV PWM4INV PWM3INV PWM2INV PWM1INV PWM0INV Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 PWM5INV R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Invert PWM5 Signal Value Description 4 PWM4INV R/W 0 1 The PWM5 signal is inverted. 0 The PWM5 signal is not inverted. Invert PWM4 Signal Value Description 3 PWM3INV R/W 0 1 The PWM4 signal is inverted. 0 The PWM4 signal is not inverted. Invert PWM3 Signal Value Description 2 PWM2INV R/W 0 1 The PWM3 signal is inverted. 0 The PWM3 signal is not inverted. Invert PWM2 Signal Value Description 1 The PWM2 signal is inverted. 0 The PWM2 signal is not inverted. 1034 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 1 PWM1INV R/W 0 Description Invert PWM1 Signal Value Description 0 PWM0INV R/W 0 1 The PWM1 signal is inverted. 0 The PWM1 signal is not inverted. Invert PWM0 Signal Value Description 1 The PWM0 signal is inverted. 0 The PWM0 signal is not inverted. July 22, 2011 1035 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 5: PWM Output Fault (PWMFAULT), offset 0x010 This register controls the behavior of the PWMn outputs in the presence of fault conditions. Both the fault inputs (FAULTn pins and digital comparator outputs) and debug events are considered fault conditions. On a fault condition, each pwmA' or pwmB' signal can be passed through unmodified or driven to the value specified by the corresponding bit in the PWMFAULTVAL register. For outputs that are configured for pass-through, the debug event handling on the corresponding PWM generator also determines if the pwmA' or pwmB' signal continues to be generated. Fault condition control occurs before the output inverter, so PWM signals driven to a specified value on fault are inverted if the channel is configured for inversion (therefore, the pin is driven to the logical complement of the specified value on a fault condition). PWM Output Fault (PWMFAULT) PWM0 base: 0x4002.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 FAULT5 R/W 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 FAULT5 FAULT4 FAULT3 FAULT2 FAULT1 FAULT0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM5 Fault Value Description 4 FAULT4 R/W 0 1 The PWM5 output signal is driven to the value specified by the PWM5 bit in the PWMFAULTVAL register. 0 The generated pwm2B' signal is passed to the PWM5 pin. PWM4 Fault Value Description 3 FAULT3 R/W 0 1 The PWM4 output signal is driven to the value specified by the PWM4 bit in the PWMFAULTVAL register. 0 The generated pwm2A' signal is passed to the PWM4 pin. PWM3 Fault Value Description 1 The PWM3 output signal is driven to the value specified by the PWM3 bit in the PWMFAULTVAL register. 0 The generated pwm1B' signal is passed to the PWM3 pin. 1036 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset Description 2 FAULT2 R/W 0 PWM2 Fault Value Description 1 FAULT1 R/W 0 1 The PWM2 output signal is driven to the value specified by the PWM2 bit in the PWMFAULTVAL register. 0 The generated pwm1A' signal is passed to the PWM2 pin. PWM1 Fault Value Description 0 FAULT0 R/W 0 1 The PWM1 output signal is driven to the value specified by the PWM1 bit in the PWMFAULTVAL register. 0 The generated pwm0B' signal is passed to the PWM1 pin. PWM0 Fault Value Description 1 The PWM0 output signal is driven to the value specified by the PWM0 bit in the PWMFAULTVAL register. 0 The generated pwm0A' signal is passed to the PWM0 pin. July 22, 2011 1037 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 This register controls the global interrupt generation capabilities of the PWM module. The events that can cause an interrupt are the fault input and the individual interrupts from the PWM generators. PWM Interrupt Enable (PWMINTEN) PWM0 base: 0x4002.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 25 24 23 22 21 20 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 19 17 16 INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0 reserved Type Reset 18 RO 0 INTPWM2 INTPWM1 INTPWM0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:20 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 INTFAULT3 R/W 0 Interrupt Fault 3 Value Description 18 INTFAULT2 R/W 0 1 An interrupt is sent to the interrupt controller when the fault condition for PWM generator 3 is asserted. 0 The fault condition for PWM generator 3 is suppressed and not sent to the interrupt controller. Interrupt Fault 2 Value Description 17 INTFAULT1 R/W 0 1 An interrupt is sent to the interrupt controller when the fault condition for PWM generator 2 is asserted. 0 The fault condition for PWM generator 2 is suppressed and not sent to the interrupt controller. Interrupt Fault 1 Value Description 1 An interrupt is sent to the interrupt controller when the fault condition for PWM generator 1 is asserted. 0 The fault condition for PWM generator 1 is suppressed and not sent to the interrupt controller. 1038 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 16 INTFAULT0 R/W 0 Description Interrupt Fault 0 Value Description 15:3 reserved RO 0x000 2 INTPWM2 R/W 0 1 An interrupt is sent to the interrupt controller when the fault condition for PWM generator 0 is asserted. 0 The fault condition for PWM generator 0 is suppressed and not sent to the interrupt controller. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM2 Interrupt Enable Value Description 1 INTPWM1 R/W 0 1 An interrupt is sent to the interrupt controller when the PWM generator 2 block asserts an interrupt. 0 The PWM generator 2 interrupt is suppressed and not sent to the interrupt controller. PWM1 Interrupt Enable Value Description 0 INTPWM0 R/W 0 1 An interrupt is sent to the interrupt controller when the PWM generator 1 block asserts an interrupt. 0 The PWM generator 1 interrupt is suppressed and not sent to the interrupt controller. PWM0 Interrupt Enable Value Description 1 An interrupt is sent to the interrupt controller when the PWM generator 0 block asserts an interrupt. 0 The PWM generator 0 interrupt is suppressed and not sent to the interrupt controller. July 22, 2011 1039 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 This register provides the current set of interrupt sources that are asserted, regardless of whether they are enabled to cause an interrupt to be asserted to the interrupt controller. The fault interrupt is asserted based on the fault condition source that is specified by the PWMnCTL, PWMnFLTSRC0 and PWMnFLTSRC1 registers. The fault interrupt is latched on detection and must be cleared through the PWM Interrupt Status and Clear (PWMISC) register. The actual value of the FAULTn signals can be observed using the PWMSTATUS register. The PWM generator interrupts simply reflect the status of the PWM generators and are cleared via the interrupt status register in the PWM generator blocks. If a bit is set, the event is active; if a bit is clear the event is not active. PWM Raw Interrupt Status (PWMRIS) PWM0 base: 0x4002.8000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 19 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 3 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 18 17 16 INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0 RO 0 RO 0 RO 0 RO 0 2 1 0 INTPWM2 INTPWM1 INTPWM0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:20 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 INTFAULT3 RO 0 Interrupt Fault PWM 3 Value Description 1 The fault condition for PWM generator 3 is asserted. 0 The fault condition for PWM generator 3 has not been asserted. This bit is cleared by writing a 1 to the INTFAULT3 bit in the PWMISC register. 18 INTFAULT2 RO 0 Interrupt Fault PWM 2 Value Description 1 The fault condition for PWM generator 2 is asserted. 0 The fault condition for PWM generator 2 has not been asserted. This bit is cleared by writing a 1 to the INTFAULT2 bit in the PWMISC register. 1040 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 17 INTFAULT1 RO 0 Description Interrupt Fault PWM 1 Value Description 1 The fault condition for PWM generator 1 is asserted. 0 The fault condition for PWM generator 1 has not been asserted. This bit is cleared by writing a 1 to the INTFAULT1 bit in the PWMISC register. 16 INTFAULT0 RO 0 Interrupt Fault PWM 0 Value Description 1 The fault condition for PWM generator 0 is asserted. 0 The fault condition for PWM generator 0 has not been asserted. This bit is cleared by writing a 1 to the INTFAULT0 bit in the PWMISC register. 15:3 reserved RO 0x000 2 INTPWM2 RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM2 Interrupt Asserted Value Description 1 The PWM generator 2 block interrupt is asserted. 0 The PWM generator 2 block interrupt has not been asserted. The PWM2RIS register shows the source of this interrupt. This bit is cleared by writing a 1 to the corresponding bit in the PWM2ISC register. 1 INTPWM1 RO 0 PWM1 Interrupt Asserted Value Description 1 The PWM generator 1 block interrupt is asserted. 0 The PWM generator 1 block interrupt has not been asserted. The PWM1RIS register shows the source of this interrupt. This bit is cleared by writing a 1 to the corresponding bit in the PWM1ISC register. 0 INTPWM0 RO 0 PWM0 Interrupt Asserted Value Description 1 The PWM generator 0 block interrupt is asserted. 0 The PWM generator 0 block interrupt has not been asserted. The PWM0RIS register shows the source of this interrupt. This bit is cleared by writing a 1 to the corresponding bit in the PWM0ISC register. July 22, 2011 1041 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C This register provides a summary of the interrupt status of the individual PWM generator blocks. If a fault interrupt is set, the corresponding FAULTn input has caused an interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched interrupt status. If an block interrupt bit is set, the corresponding generator block is asserting an interrupt. The individual interrupt status registers, PWMnISC, in each block must be consulted to determine the reason for the interrupt and used to clear the interrupt. PWM Interrupt Status and Clear (PWMISC) PWM0 base: 0x4002.8000 Offset 0x01C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 25 24 23 22 21 20 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset 19 17 16 INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0 reserved Type Reset 18 RO 0 INTPWM2 INTPWM1 INTPWM0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:20 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19 INTFAULT3 R/W1C 0 FAULT3 Interrupt Asserted Value Description 1 An enabled interrupt for the fault condition for PWM generator 3 is asserted or is latched. 0 The fault condition for PWM generator 3 has not been asserted or is not enabled. Writing a 1 to this bit clears it and the INTFAULT3 bit in the PWMRIS register. 18 INTFAULT2 R/W1C 0 FAULT2 Interrupt Asserted Value Description 1 An enabled interrupt for the fault condition for PWM generator 2 is asserted or is latched. 0 The fault condition for PWM generator 2 has not been asserted or is not enabled. Writing a 1 to this bit clears it and the INTFAULT2 bit in the PWMRIS register. 1042 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 17 INTFAULT1 R/W1C 0 Description FAULT1 Interrupt Asserted Value Description 1 An enabled interrupt for the fault condition for PWM generator 1 is asserted or is latched. 0 The fault condition for PWM generator 1 has not been asserted or is not enabled. Writing a 1 to this bit clears it and the INTFAULT1 bit in the PWMRIS register. 16 INTFAULT0 R/W1C 0 FAULT0 Interrupt Asserted Value Description 1 An enabled interrupt for the fault condition for PWM generator 0 is asserted or is latched. 0 The fault condition for PWM generator 0 has not been asserted or is not enabled. Writing a 1 to this bit clears it and the INTFAULT0 bit in the PWMRIS register. 15:3 reserved RO 0x000 2 INTPWM2 RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM2 Interrupt Status Value Description 1 An enabled interrupt for the PWM generator 2 block is asserted. 0 The PWM generator 2 block interrupt is not asserted or is not enabled. The PWM2RIS register shows the source of this interrupt. This bit is cleared by writing a 1 to the corresponding bit in the PWM2ISC register. 1 INTPWM1 RO 0 PWM1 Interrupt Status Value Description 1 An enabled interrupt for the PWM generator 1 block is asserted. 0 The PWM generator 1 block interrupt is not asserted or is not enabled. The PWM1RIS register shows the source of this interrupt. This bit is cleared by writing a 1 to the corresponding bit in the PWM1ISC register. 0 INTPWM0 RO 0 PWM0 Interrupt Status Value Description 1 An enabled interrupt for the PWM generator 0 block is asserted. 0 The PWM generator 0 block interrupt is not asserted or is not enabled. The PWM0RIS register shows the source of this interrupt. This bit is cleared by writing a 1 to the corresponding bit in the PWM0ISC register. July 22, 2011 1043 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 9: PWM Status (PWMSTATUS), offset 0x020 This register provides the unlatched status of the PWM generator fault condition. PWM Status (PWMSTATUS) PWM0 base: 0x4002.8000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 FAULT3 FAULT2 FAULT1 FAULT0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 FAULT3 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Generator 3 Fault Status Value Description 1 The fault condition for PWM generator 3 is asserted. If the FLTSRC bit in the PWM3CTL register is clear, the input is the source of the fault condition, and is therefore asserted. 0 2 FAULT2 RO 0 The fault condition for PWM generator 3 is not asserted. Generator 2 Fault Status Value Description 1 The fault condition for PWM generator 2 is asserted. If the FLTSRC bit in the PWM2CTL register is clear, the input is the source of the fault condition, and is therefore asserted. 0 1 FAULT1 RO 0 The fault condition for PWM generator 2 is not asserted. Generator 1 Fault Status Value Description 1 The fault condition for PWM generator 1 is asserted. If the FLTSRC bit in the PWM1CTL register is clear, the input is the source of the fault condition, and is therefore asserted. 0 The fault condition for PWM generator 1 is not asserted. 1044 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 0 FAULT0 RO 0 Description Generator 0 Fault Status Value Description 1 The fault condition for PWM generator 0 is asserted. If the FLTSRC bit in the PWM0CTL register is clear, the input is the source of the fault condition, and is therefore asserted. 0 The fault condition for PWM generator 0 is not asserted. July 22, 2011 1045 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 This register specifies the output value driven on the PWMn signals during a fault condition if enabled by the corresponding bit in the PWMFAULT register. Note that if the corresponding bit in the PWMINVERT register is set, the output value is driven to the logical NOT of the bit value in this register. PWM Fault Condition Value (PWMFAULTVAL) PWM0 base: 0x4002.8000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:6 reserved RO 0x0000.00 5 PWM5 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM5 Fault Value Value Description 4 PWM4 R/W 0 1 The PWM5 output signal is driven High during fault conditions if the FAULT5 bit in the PWMFAULT register is set. 0 The PWM5 output signal is driven Low during fault conditions if the FAULT5 bit in the PWMFAULT register is set. PWM4 Fault Value Value Description 3 PWM3 R/W 0 1 The PWM4 output signal is driven High during fault conditions if the FAULT4 bit in the PWMFAULT register is set. 0 The PWM4 output signal is driven Low during fault conditions if the FAULT4 bit in the PWMFAULT register is set. PWM3 Fault Value Value Description 1 0 The PWM3 output signal is driven High during fault conditions if the FAULT3 bit in the PWMFAULT register is set. The PWM3 output signal is driven Low during fault conditions if the FAULT3 bit in the PWMFAULT register is set. 1046 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 2 PWM2 R/W 0 Description PWM2 Fault Value Value Description 1 PWM1 R/W 0 1 The PWM2 output signal is driven High during fault conditions if the FAULT2 bit in the PWMFAULT register is set. 0 The PWM2 output signal is driven Low during fault conditions if the FAULT2 bit in the PWMFAULT register is set. PWM1 Fault Value Value Description 0 PWM0 R/W 0 1 The PWM1 output signal is driven High during fault conditions if the FAULT1 bit in the PWMFAULT register is set. 0 The PWM1 output signal is driven Low during fault conditions if the FAULT1 bit in the PWMFAULT register is set. PWM0 Fault Value Value Description 1 The PWM0 output signal is driven High during fault conditions if the FAULT0 bit in the PWMFAULT register is set. 0 The PWM0 output signal is driven Low during fault conditions if the FAULT0 bit in the PWMFAULT register is set. July 22, 2011 1047 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 11: PWM Enable Update (PWMENUPD), offset 0x028 This register specifies when updates to the PWMnEN bit in the PWMENABLE register are performed. The PWMnEN bit enables the pwmA' or pwmB' output to be passed to the microcontroller's pin. Updates can be immediate or locally or globally synchronized to the next synchronous update. PWM Enable Update (PWMENUPD) PWM0 base: 0x4002.8000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset ENUPD5 RO 0 R/W 0 ENUPD4 R/W 0 ENUPD3 ENUPD2 ENUPD1 ENUPD0 R/W 0 Bit/Field Name Type Reset Description 31:12 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 ENUPD5 R/W 0 PWM5 Enable Update Mode Value Description 0x0 Immediate Writes to the PWM5EN bit in the PWMENABLE register are used by the PWM generator immediately. 0x1 Reserved 0x2 Locally Synchronized Writes to the PWM5EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0. 0x3 Globally Synchronized Writes to the PWM5EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register. 1048 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 9:8 ENUPD4 R/W 0 Description PWM4 Enable Update Mode Value Description 0x0 Immediate Writes to the PWM4EN bit in the PWMENABLE register are used by the PWM generator immediately. 0x1 Reserved 0x2 Locally Synchronized Writes to the PWM4EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0. 0x3 Globally Synchronized Writes to the PWM4EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register. 7:6 ENUPD3 R/W 0 Enable Update Mode Value Description 0x0 Immediate Writes to the PWM3EN bit in the PWMENABLE register are used by the PWM generator immediately. 0x1 Reserved 0x2 Locally Synchronized Writes to the PWM3EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0. 0x3 Globally Synchronized Writes to the PWM3EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register. 5:4 ENUPD2 R/W 0 PWM2 Enable Update Mode Value Description 0x0 Immediate Writes to the PWM2EN bit in the PWMENABLE register are used by the PWM generator immediately. 0x1 Reserved 0x2 Locally Synchronized Writes to the PWM2EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0. 0x3 Globally Synchronized Writes to the PWM2EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register. July 22, 2011 1049 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 3:2 ENUPD1 R/W 0 Description PWM1 Enable Update Mode Value Description 0x0 Immediate Writes to the PWM1EN bit in the PWMENABLE register are used by the PWM generator immediately. 0x1 Reserved 0x2 Locally Synchronized Writes to the PWM1EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0. 0x3 Globally Synchronized Writes to the PWM1EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register. 1:0 ENUPD0 R/W 0 PWM0 Enable Update Mode Value Description 0x0 Immediate Writes to the PWM0EN bit in the PWMENABLE register are used by the PWM generator immediately. 0x1 Reserved 0x2 Locally Synchronized Writes to the PWM0EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0. 0x3 Globally Synchronized Writes to the PWM0EN bit in the PWMENABLE register are used by the PWM generator the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register. 1050 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 12: PWM0 Control (PWM0CTL), offset 0x040 Register 13: PWM1 Control (PWM1CTL), offset 0x080 Register 14: PWM2 Control (PWM2CTL), offset 0x0C0 These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator 0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable mode are all controlled via these registers. The blocks produce the PWM signals, which can be either two independent PWM signals (from the same counter), or a paired set of PWM signals with dead-band delays added. The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and PWM3 outputs, and the PWM2 block produces the PWM4 and PWM5 outputs. PWM0 Control (PWM0CTL) PWM0 base: 0x4002.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 DBFALLUPD Type Reset R/W 0 R/W 0 DBRISEUPD R/W 0 R/W 0 DBCTLUPD R/W 0 R/W 0 GENBUPD R/W 0 18 17 16 LATCH MINFLTPER FLTSRC GENAUPD R/W 0 R/W 0 R/W 0 RO 0 RO 0 RO 0 R/W 0 5 4 3 2 CMPBUPD CMPAUPD LOADUPD DEBUG R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 1 0 MODE ENABLE R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:19 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 18 LATCH R/W 0 Latch Fault Input Value Description 0 Fault Condition Not Latched A fault condition is in effect for as long as the generating source is asserting. 1 Fault Condition Latched A fault condition is set as the result of the assertion of the faulting source and is held (latched) while the PWMISC INTFAULTn bit is set. Clearing the INTFAULTn bit clears the fault condition. July 22, 2011 1051 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 17 MINFLTPER R/W 0 Description Minimum Fault Period This bit specifies that the PWM generator enables a one-shot counter to provide a minimum fault condition period. The timer begins counting on the rising edge of the fault condition to extend the condition for a minimum duration of the count value. The timer ignores the state of the fault condition while counting. The minimum fault delay is in effect only when the MINFLTPER bit is set. If a detected fault is in the process of being extended when the MINFLTPER bit is cleared, the fault condition extension is aborted. The delay time is specified by the PWMnMINFLTPER register MFP field value. The effect of this is to pulse stretch the fault condition input. The delay value is defined by the PWM clock period. Because the fault input is not synchronized to the PWM clock, the period of the time is PWMClock * (MFP value + 1) or PWMClock * (MFP value + 2). The delay function makes sense only if the fault source is unlatched. A latched fault source makes the fault condition appear asserted until cleared by software and negates the utility of the extend feature. It applies to all fault condition sources as specified in the FLTSRC field. Value Description 16 FLTSRC R/W 0 0 The FAULT input deassertion is unaffected. 1 The PWMnMINFLTPER one-shot counter is active and extends the period of the fault condition to a minimum period. Fault Condition Source Value Description 15:14 DBFALLUPD R/W 0x0 0 The Fault condition is determined by the Fault0 input. 1 The Fault condition is determined by the configuration of the PWMnFLTSRC0 and PWMnFLTSRC1 registers. PWMnDBFALL Update Mode Value Description 0x0 Immediate The PWMnDBFALL register value is immediately updated on a write. 0x1 Reserved 0x2 Locally Synchronized Updates to the register are reflected to the generator the next time the counter is 0. 0x3 Globally Synchronized Updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register. 1052 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 13:12 DBRISEUPD R/W 0x0 Description PWMnDBRISE Update Mode Value Description 0x0 Immediate The PWMnDBRISE register value is immediately updated on a write. 0x1 Reserved 0x2 Locally Synchronized Updates to the register are reflected to the generator the next time the counter is 0. 0x3 Globally Synchronized Updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register. 11:10 DBCTLUPD R/W 0x0 PWMnDBCTL Update Mode Value Description 0x0 Immediate The PWMnDBCTL register value is immediately updated on a write. 0x1 Reserved 0x2 Locally Synchronized Updates to the register are reflected to the generator the next time the counter is 0. 0x3 Globally Synchronized Updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register. 9:8 GENBUPD R/W 0x0 PWMnGENB Update Mode Value Description 0x0 Immediate The PWMnGENB register value is immediately updated on a write. 0x1 Reserved 0x2 Locally Synchronized Updates to the register are reflected to the generator the next time the counter is 0. 0x3 Globally Synchronized Updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register. July 22, 2011 1053 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 7:6 GENAUPD R/W 0x0 Description PWMnGENA Update Mode Value Description 0x0 Immediate The PWMnGENA register value is immediately updated on a write. 0x1 Reserved 0x2 Locally Synchronized Updates to the register are reflected to the generator the next time the counter is 0. 0x3 Globally Synchronized Updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register. 5 CMPBUPD R/W 0 Comparator B Update Mode Value Description 0 Locally Synchronized Updates to the PWMnCMPB register are reflected to the generator the next time the counter is 0. 1 Globally Synchronized Updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register. 4 CMPAUPD R/W 0 Comparator A Update Mode Value Description 0 Locally Synchronized Updates to the PWMnCMPA register are reflected to the generator the next time the counter is 0. 1 Globally Synchronized Updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register. 3 LOADUPD R/W 0 Load Register Update Mode Value Description 0 Locally Synchronized Updates to the PWMnLOAD register are reflected to the generator the next time the counter is 0. 1 Globally Synchronized Updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register. 1054 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 2 DEBUG R/W 0 Description Debug Mode Value Description 1 MODE R/W 0 0 The counter stops running when it next reaches 0 and continues running again when no longer in Debug mode. 1 The counter always runs when in Debug mode. Counter Mode Value Description 0 ENABLE R/W 0 0 The counter counts down from the load value to 0 and then wraps back to the load value (Count-Down mode). 1 The counter counts up from 0 to the load value, back down to 0, and then repeats (Count-Up/Down mode). PWM Block Enable Value Description 0 The entire PWM generation block is disabled and not clocked. 1 The PWM generation block is enabled and produces PWM signals. July 22, 2011 1055 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 15: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 Register 16: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 Register 17: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 These registers control the interrupt and ADC trigger generation capabilities of the PWM generators (PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an interrupt or an ADC trigger are: ■ The counter being equal to the load register ■ The counter being equal to zero ■ The counter being equal to the PWMnCMPA register while counting up ■ The counter being equal to the PWMnCMPA register while counting down ■ The counter being equal to the PWMnCMPB register while counting up ■ The counter being equal to the PWMnCMPB register while counting down Any combination of these events can generate either an interrupt or an ADC trigger, though no determination can be made as to the actual event that caused an ADC trigger if more than one is specified. The PWMnRIS register provides information about which events have caused raw interrupts. PWM0 Interrupt and Trigger Enable (PWM0INTEN) PWM0 base: 0x4002.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 15 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 13 12 11 10 9 8 7 6 TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved RO 0 RO 0 INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 TRCMPBD R/W 0 Trigger for Counter=PWMnCMPB Down Value Description 1 An ADC trigger pulse is output when the counter matches the value in the PWMnCMPB register value while counting down. 0 No ADC trigger is output. 1056 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 12 TRCMPBU R/W 0 Description Trigger for Counter=PWMnCMPB Up Value Description 11 TRCMPAD R/W 0 1 An ADC trigger pulse is output when the counter matches the value in the PWMnCMPB register value while counting up. 0 No ADC trigger is output. Trigger for Counter=PWMnCMPA Down Value Description 10 TRCMPAU R/W 0 1 An ADC trigger pulse is output when the counter matches the value in the PWMnCMPA register value while counting down. 0 No ADC trigger is output. Trigger for Counter=PWMnCMPA Up Value Description 9 TRCNTLOAD R/W 0 1 An ADC trigger pulse is output when the counter matches the value in the PWMnCMPA register value while counting up. 0 No ADC trigger is output. Trigger for Counter=PWMnLOAD Value Description 8 TRCNTZERO R/W 0 1 An ADC trigger pulse is output when the counter matches the PWMnLOAD register. 0 No ADC trigger is output. Trigger for Counter=0 Value Description 7:6 reserved RO 0x0 5 INTCMPBD R/W 0 1 An ADC trigger pulse is output when the counter is 0. 0 No ADC trigger is output. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt for Counter=PWMnCMPB Down Value Description 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPB register value while counting down. 0 No interrupt. July 22, 2011 1057 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 4 INTCMPBU R/W 0 Description Interrupt for Counter=PWMnCMPB Up Value Description 3 INTCMPAD R/W 0 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPB register value while counting up. 0 No interrupt. Interrupt for Counter=PWMnCMPA Down Value Description 2 INTCMPAU R/W 0 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPA register value while counting down. 0 No interrupt. Interrupt for Counter=PWMnCMPA Up Value Description 1 INTCNTLOAD R/W 0 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPA register value while counting up. 0 No interrupt. Interrupt for Counter=PWMnLOAD Value Description 0 INTCNTZERO R/W 0 1 A raw interrupt occurs when the counter matches the value in the PWMnLOAD register value. 0 No interrupt. Interrupt for Counter=0 Value Description 1 A raw interrupt occurs when the counter is zero. 0 No interrupt. 1058 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 18: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 Register 19: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 Register 20: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 These registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0 block, and so on). If a bit is set, the event has occurred; if a bit is clear, the event has not occurred. Bits in this register are cleared by writing a 1 to the corresponding bit in the PWMnISC register. PWM0 Raw Interrupt Status (PWM0RIS) PWM0 base: 0x4002.8000 Offset 0x048 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 INTCMPBD RO 0 Comparator B Down Interrupt Status Value Description 1 The counter has matched the value in the PWMnCMPB register while counting down. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTCMPBD bit in the PWMnISC register. 4 INTCMPBU RO 0 Comparator B Up Interrupt Status Value Description 1 The counter has matched the value in the PWMnCMPB register while counting up. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTCMPBU bit in the PWMnISC register. July 22, 2011 1059 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 3 INTCMPAD RO 0 Description Comparator A Down Interrupt Status Value Description 1 The counter has matched the value in the PWMnCMPA register while counting down. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTCMPAD bit in the PWMnISC register. 2 INTCMPAU RO 0 Comparator A Up Interrupt Status Value Description 1 The counter has matched the value in the PWMnCMPA register while counting up. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTCMPAU bit in the PWMnISC register. 1 INTCNTLOAD RO 0 Counter=Load Interrupt Status Value Description 1 The counter has matched the value in the PWMnLOAD register. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTCNTLOAD bit in the PWMnISC register. 0 INTCNTZERO RO 0 Counter=0 Interrupt Status Value Description 1 The counter has matched zero. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTCNTZERO bit in the PWMnISC register. 1060 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 21: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C Register 22: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C Register 23: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC These registers provide the current set of interrupt sources that are asserted to the interrupt controller (PWM0ISC controls the PWM generator 0 block, and so on). A bit is set if the event has occurred and is enabled in the PWMnINTEN register; if a bit is clear, the event has not occurred or is not enabled. These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason. PWM0 Interrupt Status and Clear (PWM0ISC) PWM0 base: 0x4002.8000 Offset 0x04C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset RO 0 INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 Bit/Field Name Type Reset Description 31:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5 INTCMPBD R/W1C 0 Comparator B Down Interrupt Value Description 1 The INTCMPBD bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTCMPBD bit in the PWMnRIS register. 4 INTCMPBU R/W1C 0 Comparator B Up Interrupt Value Description 1 The INTCMPBU bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTCMPBU bit in the PWMnRIS register. July 22, 2011 1061 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 3 INTCMPAD R/W1C 0 Description Comparator A Down Interrupt Value Description 1 The INTCMPAD bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTCMPAD bit in the PWMnRIS register. 2 INTCMPAU R/W1C 0 Comparator A Up Interrupt Value Description 1 The INTCMPAU bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTCMPAU bit in the PWMnRIS register. 1 INTCNTLOAD R/W1C 0 Counter=Load Interrupt Value Description 1 The INTCNTLOAD bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTCNTLOAD bit in the PWMnRIS register. 0 INTCNTZERO R/W1C 0 Counter=0 Interrupt Value Description 1 The INTCNTZERO bits in the PWMnRIS and PWMnINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTCNTZERO bit in the PWMnRIS register. 1062 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 24: PWM0 Load (PWM0LOAD), offset 0x050 Register 25: PWM1 Load (PWM1LOAD), offset 0x090 Register 26: PWM2 Load (PWM2LOAD), offset 0x0D0 These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM generator 0 block, and so on). Based on the counter mode configured by the MODE bit in the PWMnCTL register, this value is either loaded into the counter after it reaches zero or is the limit of up-counting after which the counter decrements back to zero. When this value matches the counter, a pulse is output which can be configured to drive the generation of the pwmA and/or pwmB signal (via the PWMnGENA/PWMnGENB register) or drive an interruptor ADC trigger (via the PWMnINTEN register). If the Load Value Update mode is locally synchronized (based on the LOADUPD field encoding in the PWMnCTL register), the 16-bit LOAD value is used the next time the counter reaches zero. If the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 1030). If this register is re-written before the actual update occurs, the previous value is never used and is lost. PWM0 Load (PWM0LOAD) PWM0 base: 0x4002.8000 Offset 0x050 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 LOAD Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 LOAD R/W 0x0000 Counter Load Value The counter load value. July 22, 2011 1063 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 27: PWM0 Counter (PWM0COUNT), offset 0x054 Register 28: PWM1 Counter (PWM1COUNT), offset 0x094 Register 29: PWM2 Counter (PWM2COUNT), offset 0x0D4 These registers contain the current value of the PWM counter (PWM0COUNT is the value of the PWM generator 0 block, and so on). When this value matches zero or the value in the PWMnLOAD, PWMnCMPA, or PWMnCMPB registers, a pulse is output which can be configured to drive the generation of a PWM signal or drive an interrupt or ADC trigger. PWM0 Counter (PWM0COUNT) PWM0 base: 0x4002.8000 Offset 0x054 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset COUNT Type Reset Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 COUNT RO 0x0000 Counter Value The current value of the counter. 1064 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 30: PWM0 Compare A (PWM0CMPA), offset 0x058 Register 31: PWM1 Compare A (PWM1CMPA), offset 0x098 Register 32: PWM2 Compare A (PWM2CMPA), offset 0x0D8 These registers contain a value to be compared against the counter (PWM0CMPA controls the PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register (see page 1063), then no pulse is ever output. If the comparator A update mode is locally synchronized (based on the CMPAUPD bit in the PWMnCTL register), the 16-bit COMPA value is used the next time the counter reaches zero. If the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 1030). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Compare A (PWM0CMPA) PWM0 base: 0x4002.8000 Offset 0x058 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 COMPA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 COMPA R/W 0x00 Comparator A Value The value to be compared against the counter. July 22, 2011 1065 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 33: PWM0 Compare B (PWM0CMPB), offset 0x05C Register 34: PWM1 Compare B (PWM1CMPB), offset 0x09C Register 35: PWM2 Compare B (PWM2CMPB), offset 0x0DC These registers contain a value to be compared against the counter (PWM0CMPB controls the PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register, no pulse is ever output. If the comparator B update mode is locally synchronized (based on the CMPBUPD bit in the PWMnCTL register), the 16-bit COMPB value is used the next time the counter reaches zero. If the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 1030). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Compare B (PWM0CMPB) PWM0 base: 0x4002.8000 Offset 0x05C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 COMPB Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:16 reserved RO 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 COMPB R/W 0x0000 Comparator B Value The value to be compared against the counter. 1066 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 36: PWM0 Generator A Control (PWM0GENA), offset 0x060 Register 37: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 Register 38: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 These registers control the generation of the pwmA signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM signal. The PWM0GENA register controls generation of the pwm0A signal; PWM1GENA, the pwm1A signal; and PWM2GENA, the pwm2A signal. If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare A action is taken and the compare B action is ignored. If the Generator A update mode is immediate (based on the GENAUPD field encoding in the PWMnCTL register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are used immediately. If the update mode is locally synchronized, these values are used the next time the counter reaches zero. If the update mode is globally synchronized, these values are used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 1030). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Generator A Control (PWM0GENA) PWM0 base: 0x4002.8000 Offset 0x060 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 ACTCMPBD RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 9 8 ACTCMPBU R/W 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 R/W 0 ACTCMPAD R/W 0 R/W 0 ACTCMPAU R/W 0 R/W 0 ACTLOAD R/W 0 R/W 0 ACTZERO R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. July 22, 2011 1067 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 11:10 ACTCMPBD R/W 0x0 Description Action for Comparator B Down This field specifies the action to be taken when the counter matches comparator B while counting down. Value Description 9:8 ACTCMPBU R/W 0x0 0x0 Do nothing. 0x1 Invert pwmA. 0x2 Drive pwmA Low. 0x3 Drive pwmA High. Action for Comparator B Up This field specifies the action to be taken when the counter matches comparator B while counting up. This action can only occur when the MODE bit in the PWMnCTL register is set. Value Description 7:6 ACTCMPAD R/W 0x0 0x0 Do nothing. 0x1 Invert pwmA. 0x2 Drive pwmA Low. 0x3 Drive pwmA High. Action for Comparator A Down This field specifies the action to be taken when the counter matches comparator A while counting down. Value Description 5:4 ACTCMPAU R/W 0x0 0x0 Do nothing. 0x1 Invert pwmA. 0x2 Drive pwmA Low. 0x3 Drive pwmA High. Action for Comparator A Up This field specifies the action to be taken when the counter matches comparator A while counting up. This action can only occur when the MODE bit in the PWMnCTL register is set. Value Description 0x0 Do nothing. 0x1 Invert pwmA. 0x2 Drive pwmA Low. 0x3 Drive pwmA High. 1068 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 3:2 ACTLOAD R/W 0x0 Description Action for Counter=LOAD This field specifies the action to be taken when the counter matches the value in the PWMnLOAD register. Value Description 1:0 ACTZERO R/W 0x0 0x0 Do nothing. 0x1 Invert pwmA. 0x2 Drive pwmA Low. 0x3 Drive pwmA High. Action for Counter=0 This field specifies the action to be taken when the counter is zero. Value Description 0x0 Do nothing. 0x1 Invert pwmA. 0x2 Drive pwmA Low. 0x3 Drive pwmA High. July 22, 2011 1069 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 39: PWM0 Generator B Control (PWM0GENB), offset 0x064 Register 40: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 Register 41: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 These registers control the generation of the pwmB signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM signal. The PWM0GENB register controls generation of the pwm0B signal; PWM1GENB, the pwm1B signal; and PWM2GENB, the pwm2B signal. If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare B action is taken and the compare A action is ignored. If the Generator B update mode is immediate (based on the GENBUPD field encoding in the PWMnCTL register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are used immediately. If the update mode is locally synchronized, these values are used the next time the counter reaches zero. If the update mode is globally synchronized, these values are used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 1030). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Generator B Control (PWM0GENB) PWM0 base: 0x4002.8000 Offset 0x064 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 ACTCMPBD RO 0 RO 0 R/W 0 R/W 0 RO 0 RO 0 9 8 ACTCMPBU R/W 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 R/W 0 ACTCMPAD R/W 0 R/W 0 ACTCMPAU R/W 0 R/W 0 ACTLOAD R/W 0 R/W 0 ACTZERO R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1070 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 11:10 ACTCMPBD R/W 0x0 Description Action for Comparator B Down This field specifies the action to be taken when the counter matches comparator B while counting down. Value Description 9:8 ACTCMPBU R/W 0x0 0x0 Do nothing. 0x1 Invert pwmB. 0x2 Drive pwmB Low. 0x3 Drive pwmB High. Action for Comparator B Up This field specifies the action to be taken when the counter matches comparator B while counting up. This action can only occur when the MODE bit in the PWMnCTL register is set. Value Description 7:6 ACTCMPAD R/W 0x0 0x0 Do nothing. 0x1 Invert pwmB. 0x2 Drive pwmB Low. 0x3 Drive pwmB High. Action for Comparator A Down This field specifies the action to be taken when the counter matches comparator A while counting down. Value Description 5:4 ACTCMPAU R/W 0x0 0x0 Do nothing. 0x1 Invert pwmB. 0x2 Drive pwmB Low. 0x3 Drive pwmB High. Action for Comparator A Up This field specifies the action to be taken when the counter matches comparator A while counting up. This action can only occur when the MODE bit in the PWMnCTL register is set. Value Description 0x0 Do nothing. 0x1 Invert pwmB. 0x2 Drive pwmB Low. 0x3 Drive pwmB High. July 22, 2011 1071 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 3:2 ACTLOAD R/W 0x0 Description Action for Counter=LOAD This field specifies the action to be taken when the counter matches the load value. Value Description 1:0 ACTZERO R/W 0x0 0x0 Do nothing. 0x1 Invert pwmB. 0x2 Drive pwmB Low. 0x3 Drive pwmB High. Action for Counter=0 This field specifies the action to be taken when the counter is 0. Value Description 0x0 Do nothing. 0x1 Invert pwmB. 0x2 Drive pwmB Low. 0x3 Drive pwmB High. 1072 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 42: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 Register 43: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 Register 44: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 The PWMnDBCTL register controls the dead-band generator, which produces the PWMn signals based on the pwmA and pwmB signals. When disabled, the pwmA signal passes through to the pwmA' signal and the pwmB signal passes through to the pwmB' signal. When dead-band control is enabled, the pwmB signal is ignored, the pwmA' signal is generated by delaying the rising edge(s) of the pwmA signal by the value in the PWMnDBRISE register (see page 1074), and the pwmB' signal is generated by inverting the pwmA signal and delaying the falling edge(s) of the pwmA signal by the value in the PWMnDBFALL register (see page 1075). The Output Control block outputs the pwm0A' signal on the PWM0 signal and the pwm0B' signal on the PWM1 signal. In a similar manner, PWM2 and PWM3 are produced from the pwm1A' and pwm1B' signals, and PWM4 and PWM5 are produced from the pwm2A' and pwm2B' signals. If the Dead-Band Control mode is immediate (based on the DBCTLUPD field encoding in the PWMnCTL register), the ENABLE bit value is used immediately. If the update mode is locally synchronized, this value is used the next time the counter reaches zero. If the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 1030). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Dead-Band Control (PWM0DBCTL) PWM0 base: 0x4002.8000 Offset 0x068 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:1 reserved RO 0x0000.000 0 ENABLE R/W 0 RO 0 0 ENABLE RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Dead-Band Generator Enable Value Description 1 The dead-band generator modifies the pwmA signal by inserting dead bands into the pwmA' and pwmB' signals. 0 The pwmA and pwmB signals pass through to the pwmA' and pwmB' signals unmodified. July 22, 2011 1073 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 45: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C Register 46: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC Register 47: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC The PWMnDBRISE register contains the number of clock cycles to delay the rising edge of the pwmA signal when generating the pwmA' signal. If the dead-band generator is disabled through the PWMnDBCTL register, this register is ignored. If the value of this register is larger than the width of a High pulse on the pwmA signal, the rising-edge delay consumes the entire High time of the signal, resulting in no High time on the output. Care must be taken to ensure that the pwmA High time always exceeds the rising-edge delay. If the Dead-Band Rising-Edge Delay mode is immediate (based on the DBRISEUPD field encoding in the PWMnCTL register), the 12-bit RISEDELAY value is used immediately. If the update mode is locally synchronized, this value is used the next time the counter reaches zero. If the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 1030). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE) PWM0 base: 0x4002.8000 Offset 0x06C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RISEDELAY RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11:0 RISEDELAY R/W 0x000 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Dead-Band Rise Delay The number of clock cycles to delay the rising edge of pwmA' after the rising edge of pwmA. 1074 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 48: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 Register 49: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 Register 50: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 The PWMnDBFALL register contains the number of clock cycles to delay the rising edge of the pwmB' signal from the falling edge of the pwmA signal. If the dead-band generator is disabled through the PWMnDBCTL register, this register is ignored. If the value of this register is larger than the width of a Low pulse on the pwmA signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time on the output. Care must be taken to ensure that the pwmA Low time always exceeds the falling-edge delay. If the Dead-Band Falling-Edge-Delay mode is immediate (based on the DBFALLUP field encoding in the PWMnCTL register), the 12-bit FALLDELAY value is used immediately. If the update mode is locally synchronized, this value is used the next time the counter reaches zero. If the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 1030). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL) PWM0 base: 0x4002.8000 Offset 0x070 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset FALLDELAY RO 0 Bit/Field Name Type Reset 31:12 reserved RO 0x0000.0 11:0 FALLDELAY R/W 0x000 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Dead-Band Fall Delay The number of clock cycles to delay the falling edge of pwmB' from the rising edge of pwmA. July 22, 2011 1075 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 51: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 Register 52: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 Register 53: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 This register specifies which fault pin inputs are used to generate a fault condition. Each bit in the following register indicates whether the corresponding fault pin is included in the fault condition. All enabled fault pins are ORed together to form the PWMnFLTSRC0 portion of the fault condition. The PWMnFLTSRC0 fault condition is then ORed with the PWMnFLTSRC1 fault condition to generate the final fault condition for the PWM generator. If the FLTSRC bit in the PWMnCTL register (see page 1051) is clear, only the Fault0 signal affects the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1 affect the fault condition generated. PWM0 Fault Source 0 (PWM0FLTSRC0) PWM0 base: 0x4002.8000 Offset 0x074 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:4 reserved RO 0x0000 3 FAULT3 R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 FAULT3 FAULT2 FAULT1 FAULT0 R/W 0 R/W 0 R/W 0 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault3 Input Value Description 0 The Fault3 signal is suppressed and cannot generate a fault condition. 1 The Fault3 signal value is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 2 FAULT2 R/W 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. Fault2 Input Value Description 0 The Fault2 signal is suppressed and cannot generate a fault condition. 1 The Fault2 signal value is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. 1076 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 1 FAULT1 R/W 0 Description Fault1 Input Value Description 0 The Fault1 signal is suppressed and cannot generate a fault condition. 1 The Fault1 signal value is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 0 FAULT0 R/W 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. Fault0 Input Value Description 0 The Fault0 signal is suppressed and cannot generate a fault condition. 1 The Fault0 signal value is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. July 22, 2011 1077 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 54: PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078 Register 55: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 Register 56: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 This register specifies which digital comparator triggers from the ADC are used to generate a fault condition. Each bit in the following register indicates whether the corresponding digital comparator trigger is included in the fault condition. All enabled digital comparator triggers are ORed together to form the PWMnFLTSRC1 portion of the fault condition. The PWMnFLTSRC1 fault condition is then ORed with the PWMnFLTSRC0 fault condition to generate the final fault condition for the PWM generator. If the FLTSRC bit in the PWMnCTL register (see page 1051) is clear, only the PWM Fault0 pin affects the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1 affect the fault condition generated. PWM0 Fault Source 1 (PWM0FLTSRC1) PWM0 base: 0x4002.8000 Offset 0x078 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 DCMP7 R/W 0 RO 0 7 6 5 4 3 2 1 0 DCMP7 DCMP6 DCMP5 DCMP4 DCMP3 DCMP2 DCMP1 DCMP0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Comparator 7 Value Description 0 The trigger from digital comparator 7 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 7 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. 1078 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 6 DCMP6 R/W 0 Description Digital Comparator 6 Value Description 0 The trigger from digital comparator 6 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 6 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 5 DCMP5 R/W 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. Digital Comparator 5 Value Description 0 The trigger from digital comparator 5 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 5 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 4 DCMP4 R/W 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. Digital Comparator 4 Value Description 0 The trigger from digital comparator 4 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 4 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 3 DCMP3 R/W 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. Digital Comparator 3 Value Description 0 The trigger from digital comparator 3 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 3 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. July 22, 2011 1079 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 2 DCMP2 R/W 0 Description Digital Comparator 2 Value Description 0 The trigger from digital comparator 2 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 2 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 1 DCMP1 R/W 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. Digital Comparator 1 Value Description 0 The trigger from digital comparator 1 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 1 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: 0 DCMP0 R/W 0 The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. Digital Comparator 0 Value Description 0 The trigger from digital comparator 0 is suppressed and cannot generate a fault condition. 1 The trigger from digital comparator 0 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators). Note: The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation. 1080 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 57: PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C Register 58: PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC Register 59: PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC If the MINFLTPER bit in the PWMnCTL register is set, this register specifies the 16-bit time-extension value to be used in extending the fault condition. The value is loaded into a 16-bit down counter, and the counter value is used to extend the fault condition. The fault condition is released in the clock immediately after the counter value reaches 0. The fault condition is asynchronous to the PWM clock; and the delay value is the product of the PWM clock period and the (MFP field value + 1) or (MFP field value + 2) depending on when the fault condition asserts with respect to the PWM clock. The counter decrements at the PWM clock rate, without pause or condition. PWM0 Minimum Fault Period (PWM0MINFLTPER) PWM0 base: 0x4002.8000 Offset 0x07C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset MFP Type Reset Bit/Field Name Type Reset Description 31:16 reserved R/W 0x0000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:0 MFP RO 0x0000 Minimum Fault Period The number of PWM clocks by which a fault condition is extended when the delay is enabled by PWMnCTL MINFLTPER. July 22, 2011 1081 Texas Instruments-Production Data Pulse Width Modulator (PWM) Register 60: PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 Register 61: PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880 Register 62: PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900 Register 63: PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980 This register defines the PWM fault pin logic sense. PWM0 Fault Pin Logic Sense (PWM0FLTSEN) PWM0 base: 0x4002.8000 Offset 0x800 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 FAULT3 FAULT2 FAULT1 FAULT0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 FAULT3 R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault3 Sense Value Description 2 FAULT2 R/W 0 0 An error is indicated if the Fault3 signal is High. 1 An error is indicated if the Fault3 signal is Low. Fault2 Sense Value Description 1 FAULT1 R/W 0 0 An error is indicated if the Fault2 signal is High. 1 An error is indicated if the Fault2 signal is Low. Fault1 Sense Value Description 0 FAULT0 R/W 0 0 An error is indicated if the Fault1 signal is High. 1 An error is indicated if the Fault1 signal is Low. Fault0 Sense Value Description 0 An error is indicated if the Fault0 signal is High. 1 An error is indicated if the Fault0 signal is Low. 1082 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 64: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 Register 65: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 Register 66: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 Along with the PWMnFLTSTAT1 register, this register provides status regarding the fault condition inputs. If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT0 register are read-only (RO) and provide the current state of the FAULTn inputs. If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT0 register are read / write 1 to clear (R/W1C) and provide a latched version of the FAULTn inputs. In this mode, the register bits are cleared by writing a 1 to a set bit. The FAULTn inputs are recorded after their sense is adjusted in the generator. The contents of this register can only be written if the fault source extensions are enabled (the FLTSRC bit in the PWMnCTL register is set). PWM0 Fault Status 0 (PWM0FLTSTAT0) PWM0 base: 0x4002.8000 Offset 0x804 Type -, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 FAULT3 FAULT2 FAULT1 FAULT0 RO 0 RO 0 RO 0 RO 0 RO 0 0 0 0 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000 3 FAULT3 - 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault Input 3 If the PWMnCTL register LATCH bit is clear, this bit is RO and represents the current state of the FAULT3 input signal after the logic sense adjustment. If the PWMnCTL register LATCH bit is set, this bit is R/W1C and represents a sticky version of the FAULT3 input signal after the logic sense adjustment. ■ If FAULT3 is set, the input transitioned to the active state previously. ■ If FAULT3 is clear, the input has not transitioned to the active state since the last time it was cleared. ■ The FAULT3 bit is cleared by writing it with the value 1. July 22, 2011 1083 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset Description 2 FAULT2 - 0 Fault Input 2 If the PWMnCTL register LATCH bit is clear, this bit is RO and represents the current state of the FAULT2 input signal after the logic sense adjustment. If the PWMnCTL register LATCH bit is set, this bit is R/W1C and represents a sticky version of the FAULT2 input signal after the logic sense adjustment. 1 FAULT1 - 0 ■ If FAULT2 is set, the input transitioned to the active state previously. ■ If FAULT2 is clear, the input has not transitioned to the active state since the last time it was cleared. ■ The FAULT2 bit is cleared by writing it with the value 1. Fault Input 1 If the PWMnCTL register LATCH bit is clear, this bit is RO and represents the current state of the FAULT1 input signal after the logic sense adjustment. If the PWMnCTL register LATCH bit is set, this bit is R/W1C and represents a sticky version of the FAULT1 input signal after the logic sense adjustment. 0 FAULT0 - 0 ■ If FAULT1 is set, the input transitioned to the active state previously. ■ If FAULT1 is clear, the input has not transitioned to the active state since the last time it was cleared. ■ The FAULT1 bit is cleared by writing it with the value 1. Fault Input 0 If the PWMnCTL register LATCH bit is clear, this bit is RO and represents the current state of the input signal after the logic sense adjustment. If the PWMnCTL register LATCH bit is set, this bit is R/W1C and represents a sticky version of the input signal after the logic sense adjustment. ■ If FAULT0 is set, the input transitioned to the active state previously. ■ If FAULT0 is clear, the input has not transitioned to the active state since the last time it was cleared. ■ The FAULT0 bit is cleared by writing it with the value 1. 1084 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 67: PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808 Register 68: PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888 Register 69: PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908 Along with the PWMnFLTSTAT0 register, this register provides status regarding the fault condition inputs. If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT1 register are read-only (RO) and provide the current state of the digital comparator triggers. If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT1 register are read / write 1 to clear (R/W1C) and provide a latched version of the digital comparator triggers. In this mode, the register bits are cleared by writing a 1 to a set bit. The contents of this register can only be written if the fault source extensions are enabled (the FLTSRC bit in the PWMnCTL register is set). PWM0 Fault Status 1 (PWM0FLTSTAT1) PWM0 base: 0x4002.8000 Offset 0x808 Type -, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 6 5 4 3 2 1 0 DCMP7 DCMP6 DCMP5 DCMP4 DCMP3 DCMP2 DCMP1 DCMP0 0 0 0 0 0 0 0 0 reserved Type Reset reserved Type Reset RO 0 Bit/Field Name Type Reset 31:8 reserved RO 0x0000.00 7 DCMP7 - 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Comparator 7 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 7 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. ■ If DCMP7 is set, the trigger transitioned to the active state previously. ■ If DCMP7 is clear, the trigger has not transitioned to the active state since the last time it was cleared. ■ The DCMP7 bit is cleared by writing it with the value 1. July 22, 2011 1085 Texas Instruments-Production Data Pulse Width Modulator (PWM) Bit/Field Name Type Reset 6 DCMP6 - 0 Description Digital Comparator 6 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 6 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. 5 DCMP5 - 0 ■ If DCMP6 is set, the trigger transitioned to the active state previously. ■ If DCMP6 is clear, the trigger has not transitioned to the active state since the last time it was cleared. ■ The DCMP6 bit is cleared by writing it with the value 1. Digital Comparator 5 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 5 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. 4 DCMP4 - 0 ■ If DCMP5 is set, the trigger transitioned to the active state previously. ■ If DCMP5 is clear, the trigger has not transitioned to the active state since the last time it was cleared. ■ The DCMP5 bit is cleared by writing it with the value 1. Digital Comparator 4 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 4 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. 3 DCMP3 - 0 ■ If DCMP4 is set, the trigger transitioned to the active state previously. ■ If DCMP4 is clear, the trigger has not transitioned to the active state since the last time it was cleared. ■ The DCMP4 bit is cleared by writing it with the value 1. Digital Comparator 3 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 3 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. ■ If DCMP3 is set, the trigger transitioned to the active state previously. ■ If DCMP3 is clear, the trigger has not transitioned to the active state since the last time it was cleared. ■ The DCMP3 bit is cleared by writing it with the value 1. 1086 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 2 DCMP2 - 0 Description Digital Comparator 2 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 2 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. 1 DCMP1 - 0 ■ If DCMP2 is set, the trigger transitioned to the active state previously. ■ If DCMP2 is clear, the trigger has not transitioned to the active state since the last time it was cleared. ■ The DCMP2 bit is cleared by writing it with the value 1. Digital Comparator 1 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 1 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. 0 DCMP0 - 0 ■ If DCMP1 is set, the trigger transitioned to the active state previously. ■ If DCMP1 is clear, the trigger has not transitioned to the active state since the last time it was cleared. ■ The DCMP1 bit is cleared by writing it with the value 1. Digital Comparator 0 Trigger If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 0 trigger input. If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger. ■ If DCMP0 is set, the trigger transitioned to the active state previously. ■ If DCMP0 is clear, the trigger has not transitioned to the active state since the last time it was cleared. ■ The DCMP0 bit is cleared by writing it with the value 1. July 22, 2011 1087 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) 21 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter. The LM3S9L71 microcontroller includes two quadrature encoder interface (QEI) modules. Each QEI module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. ® The Stellaris LM3S9L71 microcontroller includes two QEI modules providing control of two motors at the same time with the following features: ■ Position integrator that tracks the encoder position ■ Programmable noise filter on the inputs ■ Velocity capture using built-in timer ■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system) ■ Interrupt generation on: – Index pulse – Velocity-timer expiration – Direction change – Quadrature error detection 21.1 Block Diagram Figure 21-1 on page 1089 provides a block diagram of a Stellaris QEI module. 1088 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 21-1. QEI Block Diagram QEILOAD Control & Status Velocity Timer QEITIME QEICTL QEISTAT Velocity Accumulator Velocity Predivider clk PhA PhB QEICOUNT QEISPEED QEIMAXPOS Quadrature Encoder dir Position Integrator QEIPOS IDX QEIINTEN Interrupt Control Interrupt QEIRIS QEIISC 21.2 Signal Description The following table lists the external signals of the QEI module and describes the function of each. The QEI signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these QEI signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 416) should be set to choose the QEI function. The number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 434) to assign the QEI signal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 391. Table 21-1. Signals for QEI (100LQFP) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description IDX0 10 40 72 90 92 100 PD0 (3) PG5 (4) PB2 (2) PB6 (5) PB4 (6) PD7 (1) I TTL QEI module 0 index. IDX1 17 61 84 PG2 (8) PF1 (2) PH2 (1) I TTL QEI module 1 index. PhA0 11 25 43 95 PD1 (3) PC4 (2) PF6 (4) PE2 (4) I TTL QEI module 0 phase A. PhA1 37 96 PG6 (1) PE3 (3) I TTL QEI module 1 phase A. July 22, 2011 1089 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Table 21-1. Signals for QEI (100LQFP) (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description PhB0 22 23 42 47 83 96 PC7 (2) PC6 (2) PF7 (4) PF0 (2) PH3 (1) PE3 (4) I TTL QEI module 0 phase B. PhB1 11 36 95 PD1 (11) PG7 (1) PE2 (3) I TTL QEI module 1 phase B. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 21-2. Signals for QEI (108BGA) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description IDX0 G1 M7 A11 A7 A6 A2 PD0 (3) PG5 (4) PB2 (2) PB6 (5) PB4 (6) PD7 (1) I TTL QEI module 0 index. IDX1 J1 H12 D11 PG2 (8) PF1 (2) PH2 (1) I TTL QEI module 1 index. PhA0 G2 L1 M8 A4 PD1 (3) PC4 (2) PF6 (4) PE2 (4) I TTL QEI module 0 phase A. PhA1 L7 B4 PG6 (1) PE3 (3) I TTL QEI module 1 phase A. PhB0 L2 M2 K4 M9 D10 B4 PC7 (2) PC6 (2) PF7 (4) PF0 (2) PH3 (1) PE3 (4) I TTL QEI module 0 phase B. PhB1 G2 C10 A4 PD1 (11) PG7 (1) PE2 (3) I TTL QEI module 1 phase B. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 21.3 Functional Description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The position integrator and velocity capture can be independently enabled, though the position integrator must be enabled before the velocity capture can be enabled. The two phase signals, PhA and PhB, can be swapped before being interpreted by the QEI module to change the meaning of forward and backward and to correct for miswiring of the system. Alternatively, the phase signals can be interpreted as a clock and direction signal as output by some encoders. 1090 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller The QEI module input signals have a digital noise filter on them that can be enabled to prevent spurious operation. The noise filter requires that the inputs be stable for a specified number of consecutive clock cycles before updating the edge detector. The filter is enabled by the FILTEN bit in the QEI Control (QEICTL) register. The frequency of the input update is programmable using the FILTCNT bit field in the QEICTL register. The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode, the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction of rotation. This mode is determined by the SIGMODE bit of the QEICTL register (see page 1095). When the QEI module is set to use the quadrature phase mode (SIGMODE bit is clear), the capture mode for the position integrator can be set to update the position counter on every edge of the PhA signal or to update on every edge of both PhA and PhB. Updating the position counter on every PhA and PhB edge provides more positional resolution at the cost of less range in the positional counter. When edges on PhA lead edges on PhB, the position counter is incremented. When edges on PhB lead edges on PhA, the position counter is decremented. When a rising and falling edge pair is seen on one of the phases without any edges on the other, the direction of rotation has changed. The positional counter is automatically reset on one of two conditions: sensing the index pulse or reaching the maximum position value. The reset mode is determined by the RESMODE bit of the QEICTL register. When RESMODE is set, the positional counter is reset when the index pulse is sensed. This mode limits the positional counter to the values [0:N-1], where N is the number of phase edges in a full revolution of the encoder wheel. The QEI Maximum Position (QEIMAXPOS) register must be programmed with N-1 so that the reverse direction from position 0 can move the position counter to N-1. In this mode, the position register contains the absolute position of the encoder relative to the index (or home) position once an index pulse has been seen. When RESMODE is clear, the positional counter is constrained to the range [0:M], where M is the programmable maximum value. The index pulse is ignored by the positional counter in this mode. Velocity capture uses a configurable timer and a count register. The timer counts the number of phase edges (using the same configuration as for the position integrator) in a given time period. The edge count from the previous time period is available to the controller via the QEI Velocity (QEISPEED) register, while the edge count for the current time period is being accumulated in the QEI Velocity Counter (QEICOUNT) register. As soon as the current time period is complete, the total number of edges counted in that time period is made available in the QEISPEED register (overwriting the previous value), the QEICOUNT register is cleared, and counting commences on a new time period. The number of edges counted in a given time period is directly proportional to the velocity of the encoder. Figure 21-2 on page 1092 shows how the Stellaris quadrature encoder converts the phase input signals into clock pulses, the direction signal, and how the velocity predivider operates (in Divide by 4 mode). July 22, 2011 1091 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Figure 21-2. Quadrature Encoder and Velocity Predivider Operation PhA PhB clk clkdiv dir pos rel -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 The period of the timer is configurable by specifying the load value for the timer in the QEI Timer Load (QEILOAD) register. When the timer reaches zero, an interrupt can be triggered, and the hardware reloads the timer with the QEILOAD value and continues to count down. At lower encoder speeds, a longer timer period is required to be able to capture enough edges to have a meaningful result. At higher encoder speeds, both a shorter timer period and/or the velocity predivider can be used. The following equation converts the velocity counter value into an rpm value: rpm = (clock * (2 ^ VELDIV) * SPEED * 60) ÷ (LOAD * ppr * edges) where: clock is the controller clock rate ppr is the number of pulses per revolution of the physical encoder edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CAPMODE clear and 4 for CAPMODE set) For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of ÷1 (VELDIV is clear) and clocking on both PhA and PhB edges, this results in 81,920 pulses per second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation: rpm = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 rpm Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second, or 102,400 every ¼ of a second. Again, the above equation gives: rpm = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 rpm Care must be taken when evaluating this equation because intermediate values may exceed the capacity of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500; both could be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. In fact, if they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled by the ÷4 for the edge-count factor. Important: Reducing constant factors at compile time is the best way to control the intermediate values of this equation and reduce the processing requirement of computing this equation. The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses per revolution, the load value can be a power of 2. For other encoders, a load value must be selected such that the product is very close to a power of 2. For example, a 100 pulse-per-revolution encoder 1092 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 214. In this case a shift by 15 would be an adequate approximation of the divide in most cases. If absolute accuracy were required, the microcontroller’s divide instruction could be used. The QEI module can produce a controller interrupt on several events: phase error, direction change, reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt status, interrupt status, and interrupt clear capabilities are provided. 21.4 Initialization and Configuration The following example shows how to configure the Quadrature Encoder module to read back an absolute position: 1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System Control module (see page 272). 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module (see page 281). 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. To determine which GPIOs to configure, see Table 23-4 on page 1137. 4. Configure the PMCn fields in the GPIOPCTL register to assign the QEI signals to the appropriate pins (see page 434 and Table 23-5 on page 1145). 5. Configure the quadrature encoder to capture edges on both signals and maintain an absolute position by resetting on index pulses. A 1000-line encoder with four edges per line, results in 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) as the count is zero-based. ■ Write the QEICTL register with the value of 0x0000.0018. ■ Write the QEIMAXPOS register with the value of 0x0000.0F9F. 6. Enable the quadrature encoder by setting bit 0 of the QEICTL register. 7. Delay until the encoder position is required. 8. Read the encoder position by reading the QEI Position (QEIPOS) register value. 21.5 Register Map Table 21-3 on page 1094 lists the QEI registers. The offset listed is a hexadecimal increment to the register’s address, relative to the module’s base address: ■ QEI0: 0x4002.C000 ■ QEI1: 0x4002.D000 Note that the QEI module clock must be enabled before the registers can be programmed (see page 272). There must be a delay of 3 system clocks after the QEI module clock is enabled before any QEI module registers are accessed. July 22, 2011 1093 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Table 21-3. QEI Register Map Offset Name Type Reset Description See page 0x000 QEICTL R/W 0x0000.0000 QEI Control 1095 0x004 QEISTAT RO 0x0000.0000 QEI Status 1098 0x008 QEIPOS R/W 0x0000.0000 QEI Position 1099 0x00C QEIMAXPOS R/W 0x0000.0000 QEI Maximum Position 1100 0x010 QEILOAD R/W 0x0000.0000 QEI Timer Load 1101 0x014 QEITIME RO 0x0000.0000 QEI Timer 1102 0x018 QEICOUNT RO 0x0000.0000 QEI Velocity Counter 1103 0x01C QEISPEED RO 0x0000.0000 QEI Velocity 1104 0x020 QEIINTEN R/W 0x0000.0000 QEI Interrupt Enable 1105 0x024 QEIRIS RO 0x0000.0000 QEI Raw Interrupt Status 1107 0x028 QEIISC R/W1C 0x0000.0000 QEI Interrupt Status and Clear 1109 21.6 Register Descriptions The remainder of this section lists and describes the QEI registers, in numerical order by address offset. 1094 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 1: QEI Control (QEICTL), offset 0x000 This register contains the configuration of the QEI module. Separate enables are provided for the quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in order to capture the velocity, but the velocity does not need to be captured in applications that do not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset mode, and velocity predivider are all set via this register. QEI Control (QEICTL) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 FILTEN STALLEN R/W 0 R/W 0 25 24 23 22 21 20 19 18 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 10 9 8 7 6 5 4 3 2 1 0 INVI INVB INVA SWAP ENABLE R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset RO 0 RO 0 17 16 FILTCNT VELDIV R/W 0 R/W 0 VELEN RESMODE CAPMODE SIGMODE R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field Name Type Reset Description 31:20 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:16 FILTCNT R/W 0x0 Input Filter Prescale Count This field controls the frequency of the input update. When this field is clear, the input is sampled after 2 system clocks. When this field ix 0x1, the input is sampled after 3 system clocks. Similarly, when this field is 0xF, the input is sampled after 17 clocks. 15:14 reserved RO 0x0 13 FILTEN R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable Input Filter Value Description 12 STALLEN R/W 0 0 The QEI inputs are not filtered. 1 Enables the digital noise filter on the QEI input signals. Inputs must be stable for 3 consecutive clock edges before the edge detector is updated. Stall QEI Value Description 0 The QEI module does not stall when the microcontroller is stopped by a debugger. 1 The QEI module stalls when the microcontroller is stopped by a debugger. July 22, 2011 1095 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Bit/Field Name Type Reset 11 INVI R/W 0 Description Invert Index Pulse Value Description 10 INVB R/W 0 0 No effect. 1 Inverts the IDX input. Invert PhB Value Description 9 INVA R/W 0 0 No effect. 1 Inverts the PhB input. Invert PhA Value Description 8:6 VELDIV R/W 0x0 0 No effect. 1 Inverts the PhA input. Predivide Velocity This field defines the predivider of the input quadrature pulses before being applied to the QEICOUNT accumulator. Value Predivider 5 VELEN R/W 0 0x0 ÷1 0x1 ÷2 0x2 ÷4 0x3 ÷8 0x4 ÷16 0x5 ÷32 0x6 ÷64 0x7 ÷128 Capture Velocity Value Description 4 RESMODE R/W 0 0 No effect. 1 Enables capture of the velocity of the quadrature encoder. Reset Mode Value Description 0 The position counter is reset when it reaches the maximum as defined by the MAXPOS field in the QEIMAXPOS register. 1 The position counter is reset when the index pulse is captured. 1096 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Bit/Field Name Type Reset 3 CAPMODE R/W 0 Description Capture Mode Value Description 2 SIGMODE R/W 0 0 Only the PhA edges are counted. 1 The PhA and PhB edges are counted, providing twice the positional resolution but half the range. Signal Mode Value Description 1 SWAP R/W 0 0 The PhA and PhB signals operate as quadrature phase signals. 1 The PhA and PhB signals operate as clock and direction. Swap Signals Value Description 0 ENABLE R/W 0 0 No effect. 1 Swaps the PhA and PhB signals. Enable QEI Value Description 0 No effect. 1 Enables the quadrature encoder module. July 22, 2011 1097 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 2: QEI Status (QEISTAT), offset 0x004 This register provides status about the operation of the QEI module. QEI Status (QEISTAT) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 DIRECTION ERROR RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:2 reserved RO 0x0000.000 1 DIRECTION RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Direction of Rotation Indicates the direction the encoder is rotating. Value Description 0 ERROR RO 0 0 The encoder is rotating forward. 1 The encoder is rotating in reverse. Error Detected Value Description 0 No error. 1 An error was detected in the gray code sequence (that is, both signals changing at the same time). 1098 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 3: QEI Position (QEIPOS), offset 0x008 This register contains the current value of the position integrator. The value is updated by the status of the QEI phase inputs and can be set to a specific value by writing to it. QEI Position (QEIPOS) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 POSITION Type Reset POSITION Type Reset Bit/Field Name Type 31:0 POSITION R/W Reset R/W 0 Description 0x0000.0000 Current Position Integrator Value The current value of the position integrator. July 22, 2011 1099 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C This register contains the maximum value of the position integrator. When moving forward, the position register resets to zero when it increments past this value. When moving in reverse, the position register resets to this value when it decrements from zero. QEI Maximum Position (QEIMAXPOS) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MAXPOS Type Reset MAXPOS Type Reset Bit/Field Name Type 31:0 MAXPOS R/W Reset Description 0x0000.0000 Maximum Position Integrator Value The maximum value of the position integrator. 1100 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 5: QEI Timer Load (QEILOAD), offset 0x010 This register contains the load value for the velocity timer. Because this value is loaded into the timer on the clock cycle after the timer is zero, this value should be one less than the number of clocks in the desired period. So, for example, to have 2000 decimal clocks per timer period, this register should contain 1999 decimal. QEI Timer Load (QEILOAD) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 LOAD Type Reset LOAD Type Reset Bit/Field Name Type 31:0 LOAD R/W Reset Description 0x0000.0000 Velocity Timer Load Value The load value for the velocity timer. July 22, 2011 1101 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 6: QEI Timer (QEITIME), offset 0x014 This register contains the current value of the velocity timer. This counter does not increment when the VELEN bit in the QEICTL register is clear. QEI Timer (QEITIME) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 TIME Type Reset TIME Type Reset Bit/Field Name Type 31:0 TIME RO Reset Description 0x0000.0000 Velocity Timer Current Value The current value of the velocity timer. 1102 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 This register contains the running count of velocity pulses for the current time period. Because this count is a running total, the time period to which it applies cannot be known with precision (that is, a read of this register does not necessarily correspond to the time returned by the QEITIME register because there is a small window of time between the two reads, during which either value may have changed). The QEISPEED register should be used to determine the actual encoder velocity; this register is provided for information purposes only. This counter does not increment when the VELEN bit in the QEICTL register is clear. QEI Velocity Counter (QEICOUNT) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 COUNT Type Reset COUNT Type Reset Bit/Field Name Type 31:0 COUNT RO Reset Description 0x0000.0000 Velocity Pulse Count The running total of encoder pulses during this velocity timer period. July 22, 2011 1103 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Register 8: QEI Velocity (QEISPEED), offset 0x01C This register contains the most recently measured velocity of the quadrature encoder. This value corresponds to the number of velocity pulses counted in the previous velocity timer period. This register does not update when the VELEN bit in the QEICTL register is clear. QEI Velocity (QEISPEED) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 SPEED Type Reset SPEED Type Reset Bit/Field Name Type 31:0 SPEED RO Reset Description 0x0000.0000 Velocity The measured speed of the quadrature encoder in pulses per period. 1104 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 This register contains enables for each of the QEI module interrupts. An interrupt is asserted to the interrupt controller if the corresponding bit in this register is set. QEI Interrupt Enable (QEIINTEN) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 INTERROR INTDIR INTTIMER INTINDEX RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 INTERROR R/W 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Phase Error Interrupt Enable Value Description 2 INTDIR R/W 0 1 An interrupt is sent to the interrupt controller when the INTERROR bit in the QEIRIS register is set. 0 The INTERROR interrupt is suppressed and not sent to the interrupt controller. Direction Change Interrupt Enable Value Description 1 INTTIMER R/W 0 1 An interrupt is sent to the interrupt controller when the INTDIR bit in the QEIRIS register is set. 0 The INTDIR interrupt is suppressed and not sent to the interrupt controller. Timer Expires Interrupt Enable Value Description 1 An interrupt is sent to the interrupt controller when the INTTIMER bit in the QEIRIS register is set. 0 The INTTIMER interrupt is suppressed and not sent to the interrupt controller. July 22, 2011 1105 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Bit/Field Name Type Reset 0 INTINDEX R/W 0 Description Index Pulse Detected Interrupt Enable Value Description 1 An interrupt is sent to the interrupt controller when the INTINDEX bit in the QEIRIS register is set. 0 The INTINDEX interrupt is suppressed and not sent to the interrupt controller. 1106 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (configured through the QEIINTEN register). If a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred. QEI Raw Interrupt Status (QEIRIS) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x024 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 INTERROR INTDIR INTTIMER INTINDEX RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 INTERROR RO 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Phase Error Detected Value Description 1 A phase error has been detected. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTERROR bit in the QEIISC register. 2 INTDIR RO 0 Direction Change Detected Value Description 1 The rotation direction has changed 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTDIR bit in the QEIISC register. 1 INTTIMER RO 0 Velocity Timer Expired Value Description 1 The velocity timer has expired. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTTIMER bit in the QEIISC register. July 22, 2011 1107 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Bit/Field Name Type Reset 0 INTINDEX RO 0 Description Index Pulse Asserted Value Description 1 The index pulse has occurred. 0 An interrupt has not occurred. This bit is cleared by writing a 1 to the INTINDEX bit in the QEIISC register. 1108 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 This register provides the current set of interrupt sources that are asserted to the controller. If a bit is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the event in question has not occurred or is not enabled to generate an interrupt. This register is R/W1C; writing a 1 to a bit position clears the bit and the corresponding interrupt reason. QEI Interrupt Status and Clear (QEIISC) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x028 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 15 14 13 12 11 10 9 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 23 22 21 20 19 18 17 16 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 1 0 INTERROR INTDIR INTTIMER INTINDEX RO 0 RO 0 RO 0 RO 0 RO 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 reserved Type Reset reserved Type Reset Bit/Field Name Type Reset 31:4 reserved RO 0x0000.000 3 INTERROR R/W1C 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Phase Error Interrupt Value Description 1 The INTERROR bits in the QEIRIS register and the QEIINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTERROR bit in the QEIRIS register. 2 INTDIR R/W1C 0 Direction Change Interrupt Value Description 1 The INTDIR bits in the QEIRIS register and the QEIINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTDIR bit in the QEIRIS register. 1 INTTIMER R/W1C 0 Velocity Timer Expired Interrupt Value Description 1 The INTTIMER bits in the QEIRIS register and the QEIINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTTIMER bit in the QEIRIS register. July 22, 2011 1109 Texas Instruments-Production Data Quadrature Encoder Interface (QEI) Bit/Field Name Type Reset 0 INTINDEX R/W1C 0 Description Index Pulse Interrupt Value Description 1 The INTINDEX bits in the QEIRIS register and the QEIINTEN registers are set, providing an interrupt to the interrupt controller. 0 No interrupt has occurred or the interrupt is masked. This bit is cleared by writing a 1. Clearing this bit also clears the INTINDEX bit in the QEIRIS register. 1110 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 22 Pin Diagram The LM3S9L71 microcontroller pin diagram is shown below. Each GPIO signal is identified by its GPIO port unless it defaults to an alternate function on reset. In this case, the GPIO port name is followed by the default alternate function. To see a complete list of possible functions for each pin, see Table 23-5 on page 1145. Figure 22-1. 100-Pin LQFP Package Pin Diagram July 22, 2011 1111 Texas Instruments-Production Data Pin Diagram Figure 22-2. 108-Ball BGA Package Pin Diagram (Top View) 1112 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 23 Signal Tables The following tables list the signals available for each pin. Signals are configured as GPIOs on reset, except for those noted below. Use the GPIOAMSEL register (see page 432) to select analog mode. For a GPIO pin to be used for an alternate digital function, the corresponding bit in the GPIOAFSEL register (see page 416) must be set. Further pin muxing options are provided through the PMCx bit field in the GPIOPCTL register (see page 434), which selects one of several available peripheral functions for that GPIO. Important: All GPIO pins are configured as GPIOs by default with the exception of the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 23-1. GPIO Pins With Default Alternate Functions GPIO Pin Default State GPIOAFSEL Bit GPIOPCTL PMCx Bit Field PA[1:0] UART0 0 0x1 PA[5:2] SSI0 0 0x1 PB[3:2] I2C0 0 0x1 PC[3:0] JTAG/SWD 1 0x3 Table 23-2 on page 1114 shows the pin-to-signal-name mapping, including functional characteristics of the signals. Each possible alternate analog and digital function is listed for each pin. Table 23-3 on page 1126 lists the signals in alphabetical order by signal name. If it is possible for a signal to be on multiple pins, each possible pin assignment is listed. The "Pin Mux" column indicates the GPIO and the encoding needed in the PMCx bit field in the GPIOPCTL register. Table 23-4 on page 1137 groups the signals by functionality, except for GPIOs. If it is possible for a signal to be on multiple pins, each possible pin assignment is listed. Table 23-5 on page 1145 lists the GPIO pins and their analog and digital alternate functions. The AINx and VREFA analog signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. Other analog signals are 5-V tolerant and are connected directly to their circuitry (C0-, C0+, C1-, C1+, USB0VBUS, USB0ID). These signals are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. The digital signals are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric enoding shown in the table below. Table entries that are shaded gray are the default values for the corresponding GPIO pin. Table 23-6 on page 1148 lists the signals based on number of possible pin assignments. This table can be used to plan how to configure the pins for a particular functionality. Application Note AN01274 ® Configuring Stellaris Microcontrollers with Pin Multiplexing provides an overview of the pin muxing implementation, an explanation of how a system designer defines a pin configuration, and examples of the pin configuration process. Note: All digital inputs are Schmitt triggered. July 22, 2011 1113 Texas Instruments-Production Data Signal Tables 23.1 100-Pin LQFP Package Pin Tables Table 23-2. Signals by Pin Number Pin Number Pin Type Buffer Type PE7 I/O TTL AIN0 I Analog PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. PE6 I/O TTL GPIO port E bit 6. AIN1 I Analog C1o O TTL Analog comparator 1 output. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. 1 2 a Pin Name Description GPIO port E bit 7. Analog-to-digital converter input 0. Analog-to-digital converter input 1. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. VDDA - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. GNDA - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. PE5 I/O TTL AIN2 I Analog CCP5 I/O TTL Capture/Compare/PWM 5. I2S0TXSD I/O TTL I2S module 0 transmit data. GPIO port E bit 4. 3 4 5 GPIO port E bit 5. Analog-to-digital converter input 2. PE4 I/O TTL AIN3 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. Analog-to-digital converter input 3. CCP3 I/O TTL Capture/Compare/PWM 3. Fault0 I TTL PWM Fault 0. I2S0TXWS I/O TTL I2S module 0 transmit word select. RXD0 I TTL MII receive data 0. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. LDO - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). 8 VDD - Power Positive supply for I/O and some logic. 9 GND - Power Ground reference for logic and I/O pins. 6 7 1114 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-2. Signals by Pin Number (continued) Pin Number 10 11 12 13 Pin Name Pin Type a Buffer Type Description PD0 I/O TTL AIN15 I Analog GPIO port D bit 0. CAN0Rx I TTL CAN module 0 receive. Analog-to-digital converter input 15. CCP6 I/O TTL Capture/Compare/PWM 6. I2S0RXSCK I/O TTL I2S module 0 receive clock. IDX0 I TTL QEI module 0 index. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. RXDV I TTL MII receive data valid. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. PD1 I/O TTL GPIO port D bit 1. AIN14 I Analog CAN0Tx O TTL CAN module 0 transmit. CCP2 I/O TTL Capture/Compare/PWM 2. Analog-to-digital converter input 14. CCP7 I/O TTL Capture/Compare/PWM 7. I2S0RXWS I/O TTL I2S module 0 receive word select. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. PhA0 I TTL QEI module 0 phase A. PhB1 I TTL QEI module 1 phase B. TXER O TTL MII transmit error. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PD2 I/O TTL GPIO port D bit 2. AIN13 I Analog CCP5 I/O TTL Capture/Compare/PWM 5. CCP6 I/O TTL Capture/Compare/PWM 6. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. PD3 I/O TTL GPIO port D bit 3. AIN12 I Analog CCP0 I/O TTL Capture/Compare/PWM 0. CCP7 I/O TTL Capture/Compare/PWM 7. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. Analog-to-digital converter input 13. Analog-to-digital converter input 12. July 22, 2011 1115 Texas Instruments-Production Data Signal Tables Table 23-2. Signals by Pin Number (continued) Pin Number Pin Type Buffer Type Description PJ0 I/O TTL GPIO port J bit 0. I2C1SCL I/O OD I2C module 1 clock. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. RXER I TTL MII receive error. PH7 I/O TTL GPIO port H bit 7. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. RXCK I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. SSI1Tx O TTL SSI module 1 transmit. PG3 I/O TTL GPIO port G bit 3. 14 15 a Pin Name CRS I TTL MII carrier sense. Fault0 I TTL PWM Fault 0. Fault2 I TTL PWM Fault 2. I2S0RXMCLK I/O TTL I2S module 0 receive master clock. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. PG2 I/O TTL GPIO port G bit 2. 16 COL I TTL MII collision detect. Fault0 I TTL PWM Fault 0. I2S0RXSD I/O TTL I2S module 0 receive data. IDX1 I TTL QEI module 1 index. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. 17 PG1 I/O TTL GPIO port G bit 1. I2C1SDA I/O OD I2C module 1 data. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PG0 I/O TTL GPIO port G bit 0. I2C1SCL I/O OD I2C module 1 clock. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. 20 VDD - Power Positive supply for I/O and some logic. 21 GND - Power Ground reference for logic and I/O pins. 18 19 1116 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-2. Signals by Pin Number (continued) Pin Number 22 23 24 25 26 a Pin Name Pin Type Buffer Type Description PC7 I/O TTL GPIO port C bit 7. C1o O TTL Analog comparator 1 output. CCP0 I/O TTL Capture/Compare/PWM 0. CCP4 I/O TTL Capture/Compare/PWM 4. PhB0 I TTL QEI module 0 phase B. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PC6 I/O TTL GPIO port C bit 6. CCP0 I/O TTL Capture/Compare/PWM 0. CCP3 I/O TTL Capture/Compare/PWM 3. PhB0 I TTL QEI module 0 phase B. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PC5 I/O TTL GPIO port C bit 5. C0o O TTL Analog comparator 0 output. C1+ I Analog C1o O TTL Analog comparator 1 output. CCP1 I/O TTL Capture/Compare/PWM 1. Analog comparator 1 positive input. CCP3 I/O TTL Capture/Compare/PWM 3. Fault2 I TTL PWM Fault 2. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. PC4 I/O TTL GPIO port C bit 4. CCP1 I/O TTL Capture/Compare/PWM 1. CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. CCP5 I/O TTL Capture/Compare/PWM 5. PhA0 I TTL QEI module 0 phase A. TXD3 O TTL Ethernet MII transmit data 3. PA0 I/O TTL GPIO port A bit 0. I2C1SCL I/O OD I2C module 1 clock. U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. July 22, 2011 1117 Texas Instruments-Production Data Signal Tables Table 23-2. Signals by Pin Number (continued) Pin Number 27 28 29 30 a Pin Name Pin Type Buffer Type Description PA1 I/O TTL GPIO port A bit 1. I2C1SDA I/O OD I2C module 1 data. U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PA2 I/O TTL GPIO port A bit 2. I2S0RXSD I/O TTL I2S module 0 receive data. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. SSI0Clk I/O TTL SSI module 0 clock. TXD2 O TTL MII transmit data 2. PA3 I/O TTL GPIO port A bit 3. I2S0RXMCLK I/O TTL I2S module 0 receive master clock. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. SSI0Fss I/O TTL SSI module 0 frame. TXD1 O TTL Ethernet MII transmit data 1. PA4 I/O TTL GPIO port A bit 4. CAN0Rx I TTL CAN module 0 receive. I2S0TXSCK I/O TTL I2S module 0 transmit clock. SSI0Rx I TTL SSI module 0 receive. TXD0 O TTL MII transmit data 0. PA5 I/O TTL GPIO port A bit 5. CAN0Tx O TTL CAN module 0 transmit. I2S0TXWS I/O TTL I2S module 0 transmit word select. RXDV I TTL MII receive data valid. SSI0Tx O TTL SSI module 0 transmit. 32 VDD - Power Positive supply for I/O and some logic. 33 GND - Power Ground reference for logic and I/O pins. PA6 I/O TTL GPIO port A bit 6. CAN0Rx I TTL CAN module 0 receive. CCP1 I/O TTL Capture/Compare/PWM 1. I2C1SCL I/O OD I2C module 1 clock. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. RXCK I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. 31 34 1118 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-2. Signals by Pin Number (continued) Pin Number 35 Pin Type Buffer Type 38 39 40 41 Description PA7 I/O TTL GPIO port A bit 7. CAN0Tx O TTL CAN module 0 transmit. CCP3 I/O TTL Capture/Compare/PWM 3. CCP4 I/O TTL Capture/Compare/PWM 4. I2C1SDA I/O OD I2C module 1 data. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. RXER I TTL MII receive error. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PG7 I/O TTL GPIO port G bit 7. CCP5 I/O TTL Capture/Compare/PWM 5. PhB1 I TTL QEI module 1 phase B. TXER O TTL MII transmit error. 36 37 a Pin Name PG6 I/O TTL GPIO port G bit 6. Fault1 I TTL PWM Fault 1. I2S0RXWS I/O TTL I2S module 0 receive word select. PhA1 I TTL QEI module 1 phase A. TXCK I TTL MII transmit clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. U1RI I TTL UART module 1 Ring Indicator modem status input signal. VDDC - Power Positive supply for most of the logic function, including the processor core and most peripherals. PJ2 I/O TTL GPIO port J bit 2. CCP0 I/O TTL Capture/Compare/PWM 0. Fault0 I TTL PWM Fault 0. PG5 I/O TTL GPIO port G bit 5. CCP5 I/O TTL Capture/Compare/PWM 5. Fault1 I TTL PWM Fault 1. I2S0RXSCK I/O TTL I2S module 0 receive clock. IDX0 I TTL QEI module 0 index. TXEN O TTL MII transmit enable. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. PG4 I/O TTL GPIO port G bit 4. CCP3 I/O TTL Capture/Compare/PWM 3. Fault1 I TTL PWM Fault 1. RXD0 I TTL MII receive data 0. U1RI I TTL UART module 1 Ring Indicator modem status input signal. July 22, 2011 1119 Texas Instruments-Production Data Signal Tables Table 23-2. Signals by Pin Number (continued) Pin Number 42 a Pin Name Pin Type Buffer Type Description PF7 I/O TTL GPIO port F bit 7. CCP4 I/O TTL Capture/Compare/PWM 4. Fault1 I TTL PWM Fault 1. PhB0 I TTL QEI module 0 phase B. RXD1 I TTL MII receive data 1. PF6 I/O TTL GPIO port F bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. I2S0TXMCLK I/O TTL I2S module 0 transmit master clock. PhA0 I TTL QEI module 0 phase A. RXD2 I TTL MII receive data 2. U1RTS O TTL UART module 1 Request to Send modem flow control output line. 44 VDD - Power Positive supply for I/O and some logic. 45 GND - Power Ground reference for logic and I/O pins. PF5 I/O TTL GPIO port F bit 5. C1o O TTL Analog comparator 1 output. CCP2 I/O TTL Capture/Compare/PWM 2. 43 46 47 48 49 RXD3 I TTL MII receive data 3. SSI1Tx O TTL SSI module 1 transmit. PF0 I/O TTL GPIO port F bit 0. CAN1Rx I TTL CAN module 1 receive. I2S0TXSD I/O TTL I2S module 0 transmit data. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. PhB0 I TTL QEI module 0 phase B. RXCK I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. U1DSR I TTL UART module 1 Data Set Ready modem output control line. OSC0 I Analog Main oscillator crystal input or an external clock reference input. OSC1 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. PJ3 I/O TTL GPIO port J bit 3. CCP6 I/O TTL Capture/Compare/PWM 6. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. 51 NC - - PJ4 I/O TTL GPIO port J bit 4. 52 CCP4 I/O TTL Capture/Compare/PWM 4. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. PJ5 I/O TTL GPIO port J bit 5. CCP2 I/O TTL Capture/Compare/PWM 2. U1DSR I TTL UART module 1 Data Set Ready modem output control line. PJ6 I/O TTL GPIO port J bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. U1RTS O TTL UART module 1 Request to Send modem flow control output line. 50 53 54 No connect. Leave the pin electrically unconnected/isolated. 1120 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-2. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type PJ7 I/O TTL GPIO port J bit 7. 55 CCP0 I/O TTL Capture/Compare/PWM 0. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. 56 VDD - Power Positive supply for I/O and some logic. 57 GND - Power Ground reference for logic and I/O pins. PF4 I/O TTL GPIO port F bit 4. C0o O TTL Analog comparator 0 output. CCP0 I/O TTL Capture/Compare/PWM 0. Fault0 I TTL PWM Fault 0. MDIO I/O OD MDIO of the Ethernet PHY. SSI1Rx I TTL SSI module 1 receive. PF3 I/O TTL GPIO port F bit 3. MDC O TTL MII management clock. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. SSI1Fss I/O TTL SSI module 1 frame. PF2 I/O TTL GPIO port F bit 2. PHYINT I TTL PHY interrupt. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. SSI1Clk I/O TTL SSI module 1 clock. 58 59 60 PF1 I/O TTL GPIO port F bit 1. CAN1Tx O TTL CAN module 1 transmit. CCP3 I/O TTL Capture/Compare/PWM 3. I2S0TXMCLK I/O TTL I2S module 0 transmit master clock. IDX1 I TTL QEI module 1 index. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. RXER I TTL MII receive error. U1RTS O TTL UART module 1 Request to Send modem flow control output line. PH6 I/O TTL GPIO port H bit 6. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. 61 62 RXDV I TTL MII receive data valid. SSI1Rx I TTL SSI module 1 receive. PH5 I/O TTL GPIO port H bit 5. Fault2 I TTL PWM Fault 2. SSI1Fss I/O TTL SSI module 1 frame. TXD0 O TTL MII transmit data 0. RST I TTL System reset input. 63 64 Description July 22, 2011 1121 Texas Instruments-Production Data Signal Tables Table 23-2. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type Description PB3 I/O TTL GPIO port B bit 3. Fault0 I TTL PWM Fault 0. Fault3 I TTL PWM Fault 3. I2C0SDA I/O OD I2C module 0 data. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PB0 I/O TTL GPIO port B bit 0. This pin is not 5-V tolerant. CCP0 I/O TTL Capture/Compare/PWM 0. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. USB0ID I Analog This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side). PB1 I/O TTL GPIO port B bit 1. This pin is not 5-V tolerant. CCP1 I/O TTL Capture/Compare/PWM 1. CCP2 I/O TTL Capture/Compare/PWM 2. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. USB0VBUS I/O Analog This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing. 68 VDD - Power Positive supply for I/O and some logic. 69 GND - Power Ground reference for logic and I/O pins. USB0DM I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. 65 66 67 70 71 72 73 74 PB2 I/O TTL GPIO port B bit 2. CCP0 I/O TTL Capture/Compare/PWM 0. CCP3 I/O TTL Capture/Compare/PWM 3. I2C0SCL I/O OD I2C module 0 clock. IDX0 I TTL QEI module 0 index. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0RBIAS O Analog PE0 I/O TTL GPIO port E bit 0. CCP3 I/O TTL Capture/Compare/PWM 3. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. SSI1Clk I/O TTL SSI module 1 clock. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. 1122 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-2. Signals by Pin Number (continued) Pin Number Pin Type Buffer Type Description PE1 I/O TTL GPIO port E bit 1. CCP2 I/O TTL Capture/Compare/PWM 2. CCP6 I/O TTL Capture/Compare/PWM 6. Fault0 I TTL PWM Fault 0. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. SSI1Fss I/O TTL SSI module 1 frame. PH4 I/O TTL GPIO port H bit 4. SSI1Clk I/O TTL SSI module 1 clock. 75 76 a Pin Name TXD1 O TTL Ethernet MII transmit data 1. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI. PC1 I/O TTL GPIO port C bit 1. SWDIO I/O TTL JTAG TMS and SWDIO. TMS I TTL JTAG TMS and SWDIO. PC0 I/O TTL GPIO port C bit 0. SWCLK I TTL JTAG/SWD CLK. TCK I TTL JTAG/SWD CLK. 81 VDD - Power Positive supply for I/O and some logic. 82 GND - Power Ground reference for logic and I/O pins. PH3 I/O TTL GPIO port H bit 3. Fault0 I TTL PWM Fault 0. PhB0 I TTL QEI module 0 phase B. TXD2 O TTL MII transmit data 2. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. PH2 I/O TTL GPIO port H bit 2. C1o O TTL Analog comparator 1 output. Fault3 I TTL PWM Fault 3. IDX1 I TTL QEI module 1 index. TXD3 O TTL Ethernet MII transmit data 3. 77 78 79 80 83 84 PH1 I/O TTL GPIO port H bit 1. CCP7 I/O TTL Capture/Compare/PWM 7. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. 85 July 22, 2011 1123 Texas Instruments-Production Data Signal Tables Table 23-2. Signals by Pin Number (continued) Pin Number Pin Type Buffer Type 88 89 90 91 Description PH0 I/O TTL GPIO port H bit 0. CCP6 I/O TTL Capture/Compare/PWM 6. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. PJ1 I/O TTL GPIO port J bit 1. I2C1SDA I/O OD I2C module 1 data. 86 87 a Pin Name PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. VDDC - Power PB7 I/O TTL GPIO port B bit 7. Positive supply for most of the logic function, including the processor core and most peripherals. NMI I TTL Non-maskable interrupt. RXD1 I TTL MII receive data 1. PB6 I/O TTL GPIO port B bit 6. C0+ I Analog C0o O TTL Analog comparator 0 output. CCP1 I/O TTL Capture/Compare/PWM 1. CCP5 I/O TTL Capture/Compare/PWM 5. CCP7 I/O TTL Capture/Compare/PWM 7. Analog comparator 0 positive input. Fault1 I TTL PWM Fault 1. I2S0TXSCK I/O TTL I2S module 0 transmit clock. IDX0 I TTL QEI module 0 index. VREFA I Analog PB5 I/O TTL AIN11 I Analog C0o O TTL C1- I Analog CAN0Tx O TTL CAN module 0 transmit. CCP0 I/O TTL Capture/Compare/PWM 0. CCP2 I/O TTL Capture/Compare/PWM 2. CCP5 I/O TTL Capture/Compare/PWM 5. CCP6 I/O TTL Capture/Compare/PWM 6. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 1023. The VREFA input is limited to the range specified in Table 25-18 on page 1200. GPIO port B bit 5. Analog-to-digital converter input 11. Analog comparator 0 output. Analog comparator 1 negative input. 1124 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-2. Signals by Pin Number (continued) Pin Number Pin Name Pin Type a Buffer Type Description PB4 I/O TTL AIN10 I Analog Analog-to-digital converter input 10. C0- I Analog Analog comparator 0 negative input. CAN0Rx I TTL CAN module 0 receive. IDX0 I TTL QEI module 0 index. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. 93 VDD - Power Positive supply for I/O and some logic. 94 GND - Power Ground reference for logic and I/O pins. PE2 I/O TTL AIN9 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. PhA0 I TTL QEI module 0 phase A. PhB1 I TTL QEI module 1 phase B. SSI1Rx I TTL SSI module 1 receive. PE3 I/O TTL GPIO port E bit 3. AIN8 I Analog CCP1 I/O TTL Capture/Compare/PWM 1. CCP7 I/O TTL Capture/Compare/PWM 7. PhA1 I TTL QEI module 1 phase A. PhB0 I TTL QEI module 0 phase B. SSI1Tx O TTL SSI module 1 transmit. GPIO port D bit 4. 92 95 96 97 98 GPIO port B bit 4. GPIO port E bit 2. Analog-to-digital converter input 9. Analog-to-digital converter input 8. PD4 I/O TTL AIN7 I Analog CCP0 I/O TTL Capture/Compare/PWM 0. CCP3 I/O TTL Capture/Compare/PWM 3. I2S0RXSD I/O TTL I2S module 0 receive data. TXD3 O TTL Ethernet MII transmit data 3. U1RI I TTL UART module 1 Ring Indicator modem status input signal. PD5 I/O TTL GPIO port D bit 5. AIN6 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. Analog-to-digital converter input 7. Analog-to-digital converter input 6. CCP4 I/O TTL Capture/Compare/PWM 4. I2S0RXMCLK I/O TTL I2S module 0 receive master clock. TXD2 O TTL MII transmit data 2. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. July 22, 2011 1125 Texas Instruments-Production Data Signal Tables Table 23-2. Signals by Pin Number (continued) Pin Number 99 Pin Name Pin Type a Buffer Type Description PD6 I/O TTL AIN5 I Analog GPIO port D bit 6. Fault0 I TTL PWM Fault 0. I2S0TXSCK I/O TTL I2S module 0 transmit clock. TXD1 O TTL Ethernet MII transmit data 1. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PD7 I/O TTL GPIO port D bit 7. AIN4 I Analog C0o O TTL Analog comparator 0 output. Analog-to-digital converter input 5. Analog-to-digital converter input 4. CCP1 I/O TTL Capture/Compare/PWM 1. I2S0TXWS I/O TTL I2S module 0 transmit word select. IDX0 I TTL QEI module 0 index. TXD0 O TTL MII transmit data 0. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. 100 a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 23-3. Signals by Signal Name Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description AIN0 1 PE7 I Analog Analog-to-digital converter input 0. AIN1 2 PE6 I Analog Analog-to-digital converter input 1. AIN2 5 PE5 I Analog Analog-to-digital converter input 2. AIN3 6 PE4 I Analog Analog-to-digital converter input 3. AIN4 100 PD7 I Analog Analog-to-digital converter input 4. AIN5 99 PD6 I Analog Analog-to-digital converter input 5. AIN6 98 PD5 I Analog Analog-to-digital converter input 6. AIN7 97 PD4 I Analog Analog-to-digital converter input 7. AIN8 96 PE3 I Analog Analog-to-digital converter input 8. AIN9 95 PE2 I Analog Analog-to-digital converter input 9. AIN10 92 PB4 I Analog Analog-to-digital converter input 10. AIN11 91 PB5 I Analog Analog-to-digital converter input 11. AIN12 13 PD3 I Analog Analog-to-digital converter input 12. AIN13 12 PD2 I Analog Analog-to-digital converter input 13. AIN14 11 PD1 I Analog Analog-to-digital converter input 14. AIN15 10 PD0 I Analog Analog-to-digital converter input 15. C0+ 90 PB6 I Analog Analog comparator 0 positive input. C0- 92 PB4 I Analog Analog comparator 0 negative input. C0o 24 58 90 91 100 PC5 (3) PF4 (2) PB6 (3) PB5 (1) PD7 (2) O TTL Analog comparator 0 output. 1126 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment PC5 a Pin Type Buffer Type Description I Analog Analog comparator 1 positive input. Analog comparator 1 negative input. C1+ 24 C1- 91 PB5 I Analog C1o 2 22 24 46 84 PE6 (2) PC7 (7) PC5 (2) PF5 (2) PH2 (2) O TTL Analog comparator 1 output. CAN0Rx 10 30 34 92 PD0 (2) PA4 (5) PA6 (6) PB4 (5) I TTL CAN module 0 receive. CAN0Tx 11 31 35 91 PD1 (2) PA5 (5) PA7 (6) PB5 (5) O TTL CAN module 0 transmit. CAN1Rx 47 PF0 (1) I TTL CAN module 1 receive. CAN1Tx 61 PF1 (1) O TTL CAN module 1 transmit. CCP0 13 22 23 39 55 58 66 72 91 97 PD3 (4) PC7 (4) PC6 (6) PJ2 (9) PJ7 (10) PF4 (1) PB0 (1) PB2 (5) PB5 (4) PD4 (1) I/O TTL Capture/Compare/PWM 0. CCP1 24 25 34 43 54 67 90 96 100 PC5 (1) PC4 (9) PA6 (2) PF6 (1) PJ6 (10) PB1 (4) PB6 (1) PE3 (1) PD7 (3) I/O TTL Capture/Compare/PWM 1. CCP2 6 11 25 46 53 67 75 91 95 98 PE4 (6) PD1 (10) PC4 (5) PF5 (1) PJ5 (10) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) I/O TTL Capture/Compare/PWM 2. July 22, 2011 1127 Texas Instruments-Production Data Signal Tables Table 23-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP3 6 23 24 35 41 61 72 74 97 PE4 (1) PC6 (1) PC5 (5) PA7 (7) PG4 (1) PF1 (10) PB2 (4) PE0 (3) PD4 (2) I/O TTL Capture/Compare/PWM 3. CCP4 22 25 35 42 52 95 98 PC7 (1) PC4 (6) PA7 (2) PF7 (1) PJ4 (10) PE2 (1) PD5 (2) I/O TTL Capture/Compare/PWM 4. CCP5 5 12 25 36 40 90 91 PE5 (1) PD2 (4) PC4 (1) PG7 (8) PG5 (1) PB6 (6) PB5 (2) I/O TTL Capture/Compare/PWM 5. CCP6 10 12 50 75 86 91 PD0 (6) PD2 (2) PJ3 (10) PE1 (5) PH0 (1) PB5 (3) I/O TTL Capture/Compare/PWM 6. CCP7 11 13 85 90 96 PD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) I/O TTL Capture/Compare/PWM 7. COL 17 PG2 (3) I TTL MII collision detect. CRS 16 PG3 (3) I TTL MII carrier sense. Fault0 6 16 17 39 58 65 75 83 99 PE4 (4) PG3 (8) PG2 (4) PJ2 (10) PF4 (4) PB3 (2) PE1 (3) PH3 (2) PD6 (1) I TTL PWM Fault 0. Fault1 37 40 41 42 90 PG6 (8) PG5 (5) PG4 (4) PF7 (9) PB6 (4) I TTL PWM Fault 1. Fault2 16 24 63 PG3 (4) PC5 (4) PH5 (10) I TTL PWM Fault 2. 1128 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description PWM Fault 3. Fault3 65 84 PB3 (4) PH2 (4) I TTL GND 9 21 33 45 57 69 82 94 fixed - Power Ground reference for logic and I/O pins. GNDA 4 fixed - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. I2C0SCL 72 PB2 (1) I/O OD I2C module 0 clock. I2C0SDA 65 PB3 (1) I/O OD I2C module 0 data. I2C1SCL 14 19 26 34 PJ0 (11) PG0 (3) PA0 (8) PA6 (1) I/O OD I2C module 1 clock. I2C1SDA 18 27 35 87 PG1 (3) PA1 (8) PA7 (1) PJ1 (11) I/O OD I2C module 1 data. I2S0RXMCLK 16 29 98 PG3 (9) PA3 (9) PD5 (8) I/O TTL I2S module 0 receive master clock. I2S0RXSCK 10 40 PD0 (8) PG5 (9) I/O TTL I2S module 0 receive clock. I2S0RXSD 17 28 97 PG2 (9) PA2 (9) PD4 (8) I/O TTL I2S module 0 receive data. I2S0RXWS 11 37 PD1 (8) PG6 (9) I/O TTL I2S module 0 receive word select. I2S0TXMCLK 43 61 PF6 (9) PF1 (8) I/O TTL I2S module 0 transmit master clock. I2S0TXSCK 30 90 99 PA4 (9) PB6 (9) PD6 (8) I/O TTL I2S module 0 transmit clock. I2S0TXSD 5 47 PE5 (9) PF0 (8) I/O TTL I2S module 0 transmit data. I2S0TXWS 6 31 100 PE4 (9) PA5 (9) PD7 (8) I/O TTL I2S module 0 transmit word select. IDX0 10 40 72 90 92 100 PD0 (3) PG5 (4) PB2 (2) PB6 (5) PB4 (6) PD7 (1) I TTL QEI module 0 index. July 22, 2011 1129 Texas Instruments-Production Data Signal Tables Table 23-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type IDX1 17 61 84 PG2 (8) PF1 (2) PH2 (1) I TTL LDO 7 fixed - Power Description QEI module 1 index. Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). MDC 59 PF3 (3) O TTL MII management clock. MDIO 58 PF4 (3) I/O OD MDIO of the Ethernet PHY. NC 51 fixed - - NMI 89 PB7 (4) I TTL OSC0 48 fixed I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. No connect. Leave the pin electrically unconnected/isolated. Non-maskable interrupt. PA0 26 - I/O TTL GPIO port A bit 0. PA1 27 - I/O TTL GPIO port A bit 1. PA2 28 - I/O TTL GPIO port A bit 2. PA3 29 - I/O TTL GPIO port A bit 3. PA4 30 - I/O TTL GPIO port A bit 4. PA5 31 - I/O TTL GPIO port A bit 5. PA6 34 - I/O TTL GPIO port A bit 6. PA7 35 - I/O TTL GPIO port A bit 7. PB0 66 - I/O TTL GPIO port B bit 0. This pin is not 5-V tolerant. PB1 67 - I/O TTL GPIO port B bit 1. This pin is not 5-V tolerant. PB2 72 - I/O TTL GPIO port B bit 2. PB3 65 - I/O TTL GPIO port B bit 3. PB4 92 - I/O TTL GPIO port B bit 4. PB5 91 - I/O TTL GPIO port B bit 5. PB6 90 - I/O TTL GPIO port B bit 6. PB7 89 - I/O TTL GPIO port B bit 7. PC0 80 - I/O TTL GPIO port C bit 0. PC1 79 - I/O TTL GPIO port C bit 1. PC2 78 - I/O TTL GPIO port C bit 2. PC3 77 - I/O TTL GPIO port C bit 3. PC4 25 - I/O TTL GPIO port C bit 4. PC5 24 - I/O TTL GPIO port C bit 5. PC6 23 - I/O TTL GPIO port C bit 6. PC7 22 - I/O TTL GPIO port C bit 7. PD0 10 - I/O TTL GPIO port D bit 0. PD1 11 - I/O TTL GPIO port D bit 1. 1130 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-3. Signals by Signal Name (continued) Pin Name PD2 Pin Number Pin Mux / Pin Assignment 12 - a Pin Type Buffer Type I/O TTL Description GPIO port D bit 2. PD3 13 - I/O TTL GPIO port D bit 3. PD4 97 - I/O TTL GPIO port D bit 4. PD5 98 - I/O TTL GPIO port D bit 5. PD6 99 - I/O TTL GPIO port D bit 6. PD7 100 - I/O TTL GPIO port D bit 7. PE0 74 - I/O TTL GPIO port E bit 0. PE1 75 - I/O TTL GPIO port E bit 1. PE2 95 - I/O TTL GPIO port E bit 2. PE3 96 - I/O TTL GPIO port E bit 3. PE4 6 - I/O TTL GPIO port E bit 4. PE5 5 - I/O TTL GPIO port E bit 5. PE6 2 - I/O TTL GPIO port E bit 6. PE7 1 - I/O TTL GPIO port E bit 7. PF0 47 - I/O TTL GPIO port F bit 0. PF1 61 - I/O TTL GPIO port F bit 1. PF2 60 - I/O TTL GPIO port F bit 2. PF3 59 - I/O TTL GPIO port F bit 3. PF4 58 - I/O TTL GPIO port F bit 4. PF5 46 - I/O TTL GPIO port F bit 5. PF6 43 - I/O TTL GPIO port F bit 6. PF7 42 - I/O TTL GPIO port F bit 7. PG0 19 - I/O TTL GPIO port G bit 0. PG1 18 - I/O TTL GPIO port G bit 1. PG2 17 - I/O TTL GPIO port G bit 2. PG3 16 - I/O TTL GPIO port G bit 3. PG4 41 - I/O TTL GPIO port G bit 4. PG5 40 - I/O TTL GPIO port G bit 5. PG6 37 - I/O TTL GPIO port G bit 6. PG7 36 - I/O TTL GPIO port G bit 7. PH0 86 - I/O TTL GPIO port H bit 0. PH1 85 - I/O TTL GPIO port H bit 1. PH2 84 - I/O TTL GPIO port H bit 2. PH3 83 - I/O TTL GPIO port H bit 3. PH4 76 - I/O TTL GPIO port H bit 4. PH5 63 - I/O TTL GPIO port H bit 5. PH6 62 - I/O TTL GPIO port H bit 6. PH7 15 - I/O TTL GPIO port H bit 7. July 22, 2011 1131 Texas Instruments-Production Data Signal Tables Table 23-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description PhA0 11 25 43 95 PD1 (3) PC4 (2) PF6 (4) PE2 (4) I TTL QEI module 0 phase A. PhA1 37 96 PG6 (1) PE3 (3) I TTL QEI module 1 phase A. PhB0 22 23 42 47 83 96 PC7 (2) PC6 (2) PF7 (4) PF0 (2) PH3 (1) PE3 (4) I TTL QEI module 0 phase B. PhB1 11 36 95 PD1 (11) PG7 (1) PE2 (3) I TTL QEI module 1 phase B. PHYINT 60 PF2 (3) I TTL PHY interrupt. PJ0 14 - I/O TTL GPIO port J bit 0. PJ1 87 - I/O TTL GPIO port J bit 1. PJ2 39 - I/O TTL GPIO port J bit 2. PJ3 50 - I/O TTL GPIO port J bit 3. PJ4 52 - I/O TTL GPIO port J bit 4. PJ5 53 - I/O TTL GPIO port J bit 5. PJ6 54 - I/O TTL GPIO port J bit 6. PJ7 55 - I/O TTL GPIO port J bit 7. PWM0 10 14 17 19 34 47 PD0 (1) PJ0 (10) PG2 (1) PG0 (2) PA6 (4) PF0 (3) O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 11 16 18 35 61 87 PD1 (1) PG3 (1) PG1 (2) PA7 (4) PF1 (3) PJ1 (10) O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 12 60 66 86 PD2 (3) PF2 (4) PB0 (2) PH0 (2) O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 13 59 67 85 PD3 (3) PF3 (4) PB1 (2) PH1 (2) O TTL PWM 3. This signal is controlled by PWM Generator 1. 1132 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description PWM4 2 19 28 34 60 62 74 86 PE6 (1) PG0 (4) PA2 (4) PA6 (5) PF2 (2) PH6 (10) PE0 (1) PH0 (9) O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 1 15 18 29 35 59 75 85 PE7 (1) PH7 (10) PG1 (4) PA3 (4) PA7 (5) PF3 (2) PE1 (1) PH1 (9) O TTL PWM 5. This signal is controlled by PWM Generator 2. RST 64 fixed I TTL System reset input. RXCK 15 34 47 PH7 (3) PA6 (3) PF0 (4) I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. RXD0 6 41 PE4 (7) PG4 (3) I TTL MII receive data 0. RXD1 42 89 PF7 (3) PB7 (7) I TTL MII receive data 1. RXD2 43 PF6 (3) I TTL MII receive data 2. RXD3 46 PF5 (3) I TTL MII receive data 3. RXDV 10 31 62 PD0 (7) PA5 (3) PH6 (9) I TTL MII receive data valid. RXER 14 35 61 PJ0 (3) PA7 (3) PF1 (4) I TTL MII receive error. SSI0Clk 28 PA2 (1) I/O TTL SSI module 0 clock. SSI0Fss 29 PA3 (1) I/O TTL SSI module 0 frame. SSI0Rx 30 PA4 (1) I TTL SSI module 0 receive. SSI0Tx 31 PA5 (1) O TTL SSI module 0 transmit. SSI1Clk 60 74 76 PF2 (9) PE0 (2) PH4 (11) I/O TTL SSI module 1 clock. SSI1Fss 59 63 75 PF3 (9) PH5 (11) PE1 (2) I/O TTL SSI module 1 frame. SSI1Rx 58 62 95 PF4 (9) PH6 (11) PE2 (2) I TTL SSI module 1 receive. SSI1Tx 15 46 96 PH7 (11) PF5 (9) PE3 (2) O TTL SSI module 1 transmit. SWCLK 80 PC0 (3) I TTL JTAG/SWD CLK. SWDIO 79 PC1 (3) I/O TTL JTAG TMS and SWDIO. July 22, 2011 1133 Texas Instruments-Production Data Signal Tables Table 23-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description SWO 77 PC3 (3) O TTL JTAG TDO and SWO. TCK 80 PC0 (3) I TTL JTAG/SWD CLK. TDI 78 PC2 (3) I TTL JTAG TDI. TDO 77 PC3 (3) O TTL JTAG TDO and SWO. TMS 79 PC1 (3) I TTL JTAG TMS and SWDIO. TXCK 37 PG6 (3) I TTL MII transmit clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. TXD0 30 63 100 PA4 (3) PH5 (9) PD7 (4) O TTL MII transmit data 0. TXD1 29 76 99 PA3 (3) PH4 (9) PD6 (4) O TTL Ethernet MII transmit data 1. TXD2 28 83 98 PA2 (3) PH3 (9) PD5 (4) O TTL MII transmit data 2. TXD3 25 84 97 PC4 (3) PH2 (9) PD4 (4) O TTL Ethernet MII transmit data 3. TXEN 40 PG5 (3) O TTL MII transmit enable. TXER 11 36 PD1 (7) PG7 (3) O TTL MII transmit error. U0Rx 26 PA0 (1) I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 PA1 (1) O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS 2 10 34 50 PE6 (9) PD0 (9) PA6 (9) PJ3 (9) I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD 1 11 35 52 PE7 (9) PD1 (9) PA7 (9) PJ4 (9) I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR 47 53 PF0 (9) PJ5 (9) I TTL UART module 1 Data Set Ready modem output control line. U1DTR 40 55 100 PG5 (10) PJ7 (9) PD7 (9) O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI 37 41 97 PG6 (10) PG4 (10) PD4 (9) I TTL UART module 1 Ring Indicator modem status input signal. U1RTS 43 54 61 PF6 (10) PJ6 (9) PF1 (9) O TTL UART module 1 Request to Send modem flow control output line. 1134 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description U1Rx 10 12 23 26 66 92 PD0 (5) PD2 (1) PC6 (5) PA0 (9) PB0 (5) PB4 (7) I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 11 13 22 27 67 91 PD1 (5) PD3 (1) PC7 (5) PA1 (9) PB1 (5) PB5 (7) O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx 10 19 92 98 PD0 (4) PG0 (1) PB4 (4) PD5 (9) I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx 6 11 18 99 PE4 (5) PD1 (4) PG1 (1) PD6 (9) O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. USB0DM 70 fixed I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP 71 fixed I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. USB0EPEN 19 24 34 72 83 PG0 (7) PC5 (6) PA6 (8) PB2 (8) PH3 (4) O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0ID 66 PB0 I Analog This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side). USB0PFLT 22 23 35 65 74 76 87 PC7 (6) PC6 (7) PA7 (8) PB3 (8) PE0 (9) PH4 (4) PJ1 (9) I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. USB0RBIAS 73 fixed O Analog 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. USB0VBUS 67 PB1 I/O Analog This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing. July 22, 2011 1135 Texas Instruments-Production Data Signal Tables Table 23-3. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description VDD 8 20 32 44 56 68 81 93 fixed - Power Positive supply for I/O and some logic. VDDA 3 fixed - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. VDDC 38 88 fixed - Power Positive supply for most of the logic function, including the processor core and most peripherals. VREFA 90 PB6 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 1023. The VREFA input is limited to the range specified in Table 25-18 on page 1200. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 1136 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-4. Signals by Function, Except for GPIO Function ADC Pin Name Pin Type Buffer Type AIN0 1 I Analog Analog-to-digital converter input 0. AIN1 2 I Analog Analog-to-digital converter input 1. AIN2 5 I Analog Analog-to-digital converter input 2. AIN3 6 I Analog Analog-to-digital converter input 3. AIN4 100 I Analog Analog-to-digital converter input 4. AIN5 99 I Analog Analog-to-digital converter input 5. AIN6 98 I Analog Analog-to-digital converter input 6. AIN7 97 I Analog Analog-to-digital converter input 7. AIN8 96 I Analog Analog-to-digital converter input 8. AIN9 95 I Analog Analog-to-digital converter input 9. AIN10 92 I Analog Analog-to-digital converter input 10. AIN11 91 I Analog Analog-to-digital converter input 11. AIN12 13 I Analog Analog-to-digital converter input 12. AIN13 12 I Analog Analog-to-digital converter input 13. AIN14 11 I Analog Analog-to-digital converter input 14. AIN15 10 I Analog Analog-to-digital converter input 15. VREFA 90 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 1023. The VREFA input is limited to the range specified in Table 25-18 on page 1200. C0+ 90 I Analog Analog comparator 0 positive input. C0- 92 I Analog Analog comparator 0 negative input. C0o 24 58 90 91 100 O TTL C1+ 24 I Analog Analog comparator 1 positive input. C1- 91 I Analog Analog comparator 1 negative input. C1o 2 22 24 46 84 O TTL Analog comparator 1 output. CAN0Rx 10 30 34 92 I TTL CAN module 0 receive. CAN0Tx 11 31 35 91 O TTL CAN module 0 transmit. CAN1Rx 47 I TTL CAN module 1 receive. CAN1Tx 61 O TTL CAN module 1 transmit. Analog Comparators Controller Area Network a Pin Number Description Analog comparator 0 output. July 22, 2011 1137 Texas Instruments-Production Data Signal Tables Table 23-4. Signals by Function, Except for GPIO (continued) Function Ethernet Pin Name a Pin Number Pin Type Buffer Type Description COL 17 I TTL MII collision detect. CRS 16 I TTL MII carrier sense. MDC 59 O TTL MII management clock. MDIO 58 I/O OD MDIO of the Ethernet PHY. PHYINT 60 I TTL PHY interrupt. RXCK 15 34 47 I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. RXD0 6 41 I TTL MII receive data 0. RXD1 42 89 I TTL MII receive data 1. RXD2 43 I TTL MII receive data 2. RXD3 46 I TTL MII receive data 3. RXDV 10 31 62 I TTL MII receive data valid. RXER 14 35 61 I TTL MII receive error. TXCK 37 I TTL MII transmit clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. TXD0 30 63 100 O TTL MII transmit data 0. TXD1 29 76 99 O TTL Ethernet MII transmit data 1. TXD2 28 83 98 O TTL MII transmit data 2. TXD3 25 84 97 O TTL Ethernet MII transmit data 3. TXEN 40 O TTL MII transmit enable. TXER 11 36 O TTL MII transmit error. 1138 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-4. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type CCP0 13 22 23 39 55 58 66 72 91 97 I/O TTL Capture/Compare/PWM 0. CCP1 24 25 34 43 54 67 90 96 100 I/O TTL Capture/Compare/PWM 1. CCP2 6 11 25 46 53 67 75 91 95 98 I/O TTL Capture/Compare/PWM 2. CCP3 6 23 24 35 41 61 72 74 97 I/O TTL Capture/Compare/PWM 3. CCP4 22 25 35 42 52 95 98 I/O TTL Capture/Compare/PWM 4. CCP5 5 12 25 36 40 90 91 I/O TTL Capture/Compare/PWM 5. I/O TTL Capture/Compare/PWM 6. General-Purpose Timers CCP6 Description July 22, 2011 1139 Texas Instruments-Production Data Signal Tables Table 23-4. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Number a Pin Type Buffer Type Description 10 12 50 75 86 91 CCP7 11 13 85 90 96 I/O TTL Capture/Compare/PWM 7. I2C0SCL 72 I/O OD I2C module 0 clock. I2C0SDA 65 I/O OD I2C module 0 data. I2C1SCL 14 19 26 34 I/O OD I2C module 1 clock. I2C1SDA 18 27 35 87 I/O OD I2C module 1 data. I2S0RXMCLK 16 29 98 I/O TTL I2S module 0 receive master clock. I2S0RXSCK 10 40 I/O TTL I2S module 0 receive clock. I2S0RXSD 17 28 97 I/O TTL I2S module 0 receive data. I2S0RXWS 11 37 I/O TTL I2S module 0 receive word select. I2S0TXMCLK 43 61 I/O TTL I2S module 0 transmit master clock. I2S0TXSCK 30 90 99 I/O TTL I2S module 0 transmit clock. I2S0TXSD 5 47 I/O TTL I2S module 0 transmit data. I2S0TXWS 6 31 100 I/O TTL I2S module 0 transmit word select. SWCLK 80 I TTL JTAG/SWD CLK. SWDIO 79 I/O TTL JTAG TMS and SWDIO. SWO 77 O TTL JTAG TDO and SWO. TCK 80 I TTL JTAG/SWD CLK. TDI 78 I TTL JTAG TDI. TDO 77 O TTL JTAG TDO and SWO. TMS 79 I TTL JTAG TMS and SWDIO. I2C I2S JTAG/SWD/SWO 1140 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-4. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type Fault0 6 16 17 39 58 65 75 83 99 I TTL PWM Fault 0. Fault1 37 40 41 42 90 I TTL PWM Fault 1. Fault2 16 24 63 I TTL PWM Fault 2. Fault3 65 84 I TTL PWM Fault 3. PWM0 10 14 17 19 34 47 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 11 16 18 35 61 87 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 12 60 66 86 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 13 59 67 85 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 2 19 28 34 60 62 74 86 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 1 15 18 29 35 59 75 85 O TTL PWM 5. This signal is controlled by PWM Generator 2. PWM Description July 22, 2011 1141 Texas Instruments-Production Data Signal Tables Table 23-4. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type GND 9 21 33 45 57 69 82 94 - Power Ground reference for logic and I/O pins. GNDA 4 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. LDO 7 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). VDD 8 20 32 44 56 68 81 93 - Power Positive supply for I/O and some logic. VDDA 3 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. VDDC 38 88 - Power Positive supply for most of the logic function, including the processor core and most peripherals. Power Description 1142 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-4. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Type Buffer Type IDX0 10 40 72 90 92 100 I TTL QEI module 0 index. IDX1 17 61 84 I TTL QEI module 1 index. PhA0 11 25 43 95 I TTL QEI module 0 phase A. PhA1 37 96 I TTL QEI module 1 phase A. PhB0 22 23 42 47 83 96 I TTL QEI module 0 phase B. PhB1 11 36 95 I TTL QEI module 1 phase B. SSI0Clk 28 I/O TTL SSI module 0 clock. SSI0Fss 29 I/O TTL SSI module 0 frame. SSI0Rx 30 I TTL SSI module 0 receive. SSI0Tx 31 O TTL SSI module 0 transmit. SSI1Clk 60 74 76 I/O TTL SSI module 1 clock. SSI1Fss 59 63 75 I/O TTL SSI module 1 frame. SSI1Rx 58 62 95 I TTL SSI module 1 receive. SSI1Tx 15 46 96 O TTL SSI module 1 transmit. NMI 89 I TTL Non-maskable interrupt. OSC0 48 I Analog Main oscillator crystal input or an external clock reference input. OSC1 49 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 64 I TTL QEI SSI System Control & Clocks a Pin Number Description System reset input. July 22, 2011 1143 Texas Instruments-Production Data Signal Tables Table 23-4. Signals by Function, Except for GPIO (continued) Function UART Pin Name a Pin Number Pin Type Buffer Type Description U0Rx 26 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx 27 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS 2 10 34 50 I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD 1 11 35 52 I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR 47 53 I TTL UART module 1 Data Set Ready modem output control line. U1DTR 40 55 100 O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI 37 41 97 I TTL UART module 1 Ring Indicator modem status input signal. U1RTS 43 54 61 O TTL UART module 1 Request to Send modem flow control output line. U1Rx 10 12 23 26 66 92 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx 11 13 22 27 67 91 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx 10 19 92 98 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx 6 11 18 99 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. 1144 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-4. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type USB0DM 70 I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP 71 I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. USB0EPEN 19 24 34 72 83 O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0ID 66 I Analog This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side). USB0PFLT 22 23 35 65 74 76 87 I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. USB0RBIAS 73 O Analog 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. USB0VBUS 67 I/O Analog This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing. USB Description a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 23-5. GPIO Pins and Alternate Functions a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PA0 26 - U0Rx - - - - - - I2C1SCL U1Rx - - PA1 27 - U0Tx - - - - - - I2C1SDA U1Tx - - PA2 28 - SSI0Clk - TXD2 PWM4 - - - - I2S0RXSD - - PA3 29 - SSI0Fss - TXD1 PWM5 - - - - I2S0RXMCLK - - PA4 30 - SSI0Rx - TXD0 - CAN0Rx - - - I2S0TXSCK - - PA5 31 - SSI0Tx - RXDV - CAN0Tx - - - I2S0TXWS - - PA6 34 - I2C1SCL CCP1 RXCK PWM0 PWM4 CAN0Rx - USB0EPEN U1CTS - - USB0PFLT U1DCD PA7 35 - I2C1SDA CCP4 RXER PWM1 PWM5 CAN0Tx CCP3 PB0 66 USB0ID CCP0 PWM2 - - U1Rx - - - - - - - - PB1 67 USB0VBUS CCP2 PWM3 - CCP1 U1Tx - - - - - - PB2 72 - I2C0SCL IDX0 - CCP3 CCP0 - - USB0EPEN - - - PB3 65 - I2C0SDA Fault0 - Fault3 - - - USB0PFLT - - - PB4 92 AIN10 C0- - - - U2Rx CAN0Rx IDX0 U1Rx - - - - PB5 91 AIN11 C1- C0o CCP5 CCP6 CCP0 CAN0Tx CCP2 U1Tx - - - - July 22, 2011 1145 Texas Instruments-Production Data Signal Tables Table 23-5. GPIO Pins and Alternate Functions (continued) Analog Function a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin 1 2 3 4 5 6 7 8 9 10 11 PB6 90 VREFA C0+ CCP1 CCP7 C0o Fault1 IDX0 CCP5 - - I2S0TXSCK - - PB7 89 - - - - NMI - - RXD1 - - - - PC0 80 - - - TCK SWCLK - - - - - - - - PC1 79 - - - TMS SWDIO - - - - - - - - PC2 78 - - - TDI - - - - - - - - PC3 77 - - - TDO SWO - - - - - - - - PC4 25 - CCP5 PhA0 TXD3 - CCP2 CCP4 - - CCP1 - - PC5 24 C1+ CCP1 C1o C0o Fault2 CCP3 USB0EPEN - - - - - PC6 23 - CCP3 PhB0 - - U1Rx CCP0 USB0PFLT - - - - PC7 22 - CCP4 PhB0 - CCP0 U1Tx USB0PFLT C1o - - - - PD0 10 AIN15 PWM0 CAN0Rx IDX0 U2Rx U1Rx CCP6 RXDV I2S0RXSCK U1CTS PD1 11 AIN14 PWM1 CAN0Tx PhA0 U2Tx U1Tx CCP7 TXER I2S0RXWS U1DCD PD2 12 AIN13 U1Rx CCP6 PWM2 CCP5 - - - - PD3 13 AIN12 U1Tx CCP7 PWM3 CCP0 - - - - PD4 97 AIN7 CCP0 CCP3 - TXD3 - - - I2S0RXSD - - CCP2 PhB1 - - - - - - U1RI - - PD5 98 AIN6 CCP2 CCP4 - TXD2 - - - I2S0RXMCLK U2Rx - - PD6 99 AIN5 Fault0 - - TXD1 - - - I2S0TXSCK U2Tx - - I2S0TXWS U1DTR PD7 100 AIN4 IDX0 C0o CCP1 TXD0 - - - - - PE0 74 - PWM4 SSI1Clk CCP3 - - - - - USB0PFLT - - PE1 75 - PWM5 SSI1Fss Fault0 CCP2 CCP6 - - - - - - PE2 95 AIN9 CCP4 SSI1Rx PhB1 PhA0 CCP2 - - - - - - PE3 96 AIN8 CCP1 SSI1Tx PhA1 PhB0 CCP7 - - - - - - PE4 6 AIN3 CCP3 - - Fault0 U2Tx CCP2 RXD0 - I2S0TXWS - - PE5 5 AIN2 CCP5 - - - - - - - I2S0TXSD - - PE6 2 AIN1 PWM4 C1o - - - - - - U1CTS - - - PE7 1 AIN0 PWM5 - - - - - - U1DCD - - PF0 47 - CAN1Rx PhB0 PWM0 RXCK - - - I2S0TXSD U1DSR - - PF1 61 - CAN1Tx IDX1 PWM1 RXER - - - I2S0TXMCLK CCP3 - U1RTS PF2 60 - - PWM4 PHYINT PWM2 - - - - SSI1Clk - - PF3 59 - - PWM5 MDC PWM3 - - - - SSI1Fss - - PF4 58 - CCP0 C0o MDIO Fault0 - - - - SSI1Rx - - PF5 46 - CCP2 C1o RXD3 - - - - - SSI1Tx - - PF6 43 - CCP1 - RXD2 PhA0 - - - - I2S0TXMCLK U1RTS - PF7 42 - CCP4 - RXD1 PhB0 - - - - Fault1 - - PG0 19 - U2Rx PWM0 I2C1SCL PWM4 - - USB0EPEN - - - - PG1 18 - U2Tx PWM1 I2C1SDA PWM5 - - - - - - - PG2 17 - PWM0 - COL Fault0 - - - IDX1 I2S0RXSD - - 1146 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-5. GPIO Pins and Alternate Functions (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 PG3 16 - PWM1 - CRS Fault2 - - - PG4 41 - CCP3 - RXD0 Fault1 - - - - PG5 40 - CCP5 - TXEN IDX0 Fault1 - - - PG6 37 - PhA1 - TXCK - - - - 8 9 10 11 - - - U1RI - I2S0RXSCK U1DTR - U1RI - Fault0 I2S0RXMCLK Fault1 I2S0RXWS PG7 36 - PhB1 - TXER - - - - CCP5 - - - PH0 86 - CCP6 PWM2 - - - - - - PWM4 - - PH1 85 - CCP7 PWM3 - - - - - - PWM5 - - PH2 84 - IDX1 C1o - Fault3 - - - - TXD3 - - PH3 83 - PhB0 Fault0 - USB0EPEN - - - - TXD2 - - PH4 76 - - - - USB0PFLT - - - - TXD1 - SSI1Clk PH5 63 - - - - - - - - - TXD0 PH6 62 - - - - - - - - - RXDV Fault2 SSI1Fss PWM4 SSI1Rx PH7 15 - - - RXCK - - - - - - PWM5 SSI1Tx PJ0 14 - - - RXER - - - - - - PWM0 I2C1SCL PJ1 87 - - - - - - - - - USB0PFLT PWM1 I2C1SDA PJ2 39 - - - - - - - - - CCP0 Fault0 - PJ3 50 - - - - - - - - - U1CTS CCP6 - PJ4 52 - - - - - - - - - U1DCD CCP4 - PJ5 53 - - - - - - - - - U1DSR CCP2 - PJ6 54 - - - - - - - - - U1RTS CCP1 - PJ7 55 - - - - - - - - - U1DTR CCP0 - a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. July 22, 2011 1147 Texas Instruments-Production Data Signal Tables Table 23-6. Possible Pin Assignments for Alternate Functions # of Possible Assignments one Alternate Function GPIO Function AIN0 PE7 AIN1 PE6 AIN10 PB4 AIN11 PB5 AIN12 PD3 AIN13 PD2 AIN14 PD1 AIN15 PD0 AIN2 PE5 AIN3 PE4 AIN4 PD7 AIN5 PD6 AIN6 PD5 AIN7 PD4 AIN8 PE3 AIN9 PE2 C0+ PB6 C0- PB4 C1+ PC5 C1- PB5 CAN1Rx PF0 CAN1Tx PF1 COL PG2 CRS PG3 I2C0SCL PB2 I2C0SDA PB3 MDC PF3 MDIO PF4 NMI PB7 PHYINT PF2 RXD2 PF6 RXD3 PF5 SSI0Clk PA2 SSI0Fss PA3 SSI0Rx PA4 SSI0Tx PA5 SWCLK PC0 SWDIO PC1 SWO PC3 TCK PC0 TDI PC2 1148 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-6. Possible Pin Assignments for Alternate Functions (continued) # of Possible Assignments Alternate Function GPIO Function TDO PC3 TMS PC1 TXCK PG6 TXEN PG5 U0Rx PA0 U0Tx PA1 USB0ID PB0 USB0VBUS PB1 VREFA PB6 Fault3 PB3 PH2 I2S0RXSCK PD0 PG5 I2S0RXWS PD1 PG6 I2S0TXMCLK PF1 PF6 I2S0TXSD PE5 PF0 PhA1 PE3 PG6 two three RXD0 PE4 PG4 RXD1 PB7 PF7 TXER PD1 PG7 U1DSR PF0 PJ5 Fault2 PC5 PG3 PH5 I2S0RXMCLK PA3 PD5 PG3 I2S0RXSD PA2 PD4 PG2 I2S0TXSCK PA4 PB6 PD6 I2S0TXWS PA5 PD7 PE4 IDX1 PF1 PG2 PH2 PhB1 PD1 PE2 PG7 RXCK PA6 PF0 PH7 RXDV PA5 PD0 PH6 RXER PA7 PF1 PJ0 SSI1Clk PE0 PF2 PH4 SSI1Fss PE1 PF3 PH5 SSI1Rx PE2 PF4 PH6 SSI1Tx PE3 PF5 PH7 TXD0 PA4 PD7 PH5 TXD1 PA3 PD6 PH4 TXD2 PA2 PD5 PH3 TXD3 PC4 PD4 PH2 U1DTR PD7 PG5 PJ7 U1RI PD4 PG4 PG6 U1RTS PF1 PF6 PJ6 July 22, 2011 1149 Texas Instruments-Production Data Signal Tables Table 23-6. Possible Pin Assignments for Alternate Functions (continued) # of Possible Assignments four five six seven Alternate Function GPIO Function CAN0Rx PA4 PA6 PB4 PD0 CAN0Tx PA5 PA7 PB5 PD1 I2C1SCL PA0 PA6 PG0 PJ0 I2C1SDA PA1 PA7 PG1 PJ1 PWM2 PB0 PD2 PF2 PH0 PWM3 PB1 PD3 PF3 PH1 PhA0 PC4 PD1 PE2 PF6 U1CTS PA6 PD0 PE6 PJ3 U1DCD PA7 PD1 PE7 PJ4 U2Rx PB4 PD0 PD5 PG0 U2Tx PD1 PD6 PE4 PG1 C0o PB5 PB6 PC5 PD7 PF4 C1o PC5 PC7 PE6 PF5 PH2 CCP7 PB6 PD1 PD3 PE3 PH1 Fault1 PB6 PF7 PG4 PG5 PG6 USB0EPEN PA6 PB2 PC5 PG0 PH3 CCP6 PB5 PD0 PD2 PE1 PH0 PJ3 IDX0 PB2 PB4 PB6 PD0 PD7 PG5 PWM0 PA6 PD0 PF0 PG0 PG2 PJ0 PWM1 PA7 PD1 PF1 PG1 PG3 PJ1 PhB0 PC6 PC7 PE3 PF0 PF7 PH3 U1Rx PA0 PB0 PB4 PC6 PD0 PD2 U1Tx PA1 PB1 PB5 PC7 PD1 PD3 CCP4 PA7 PC4 PC7 PD5 PE2 PF7 PJ4 CCP5 PB5 PB6 PC4 PD2 PE5 PG5 PG7 USB0PFLT PA7 PB3 PC6 PC7 PE0 PH4 PJ1 PWM4 PA2 PA6 PE0 PE6 PF2 PG0 PH0 PH6 PWM5 PA3 PA7 PE1 PE7 PF3 PG1 PH1 PH7 eight nine CCP1 PA6 PB1 PB6 PC4 PC5 PD7 PE3 PF6 PJ6 CCP3 PA7 PB2 PC5 PC6 PD4 PE0 PE4 PF1 PG4 Fault0 PB3 PD6 PE1 PE4 PF4 PG2 PG3 PH3 PJ2 CCP0 PB0 PB2 PB5 PC6 PC7 PD3 PD4 PF4 PJ2 PJ7 CCP2 PB1 PB5 PC4 PD1 PD5 PE1 PE2 PE4 PF5 PJ5 ten 1150 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 23.2 108-Ball BGA Package Pin Tables Table 23-7. Signals by Pin Number Pin Number A1 Pin Type Buffer Type PE6 I/O TTL AIN1 I Analog C1o O TTL Analog comparator 1 output. A4 GPIO port E bit 6. Analog-to-digital converter input 1. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. I TTL UART module 1 Clear To Send modem flow control input signal. PD7 I/O TTL GPIO port D bit 7. AIN4 I Analog C0o O TTL Analog comparator 0 output. Analog-to-digital converter input 4. CCP1 I/O TTL Capture/Compare/PWM 1. I2S0TXWS I/O TTL I2S module 0 transmit word select. IDX0 I TTL QEI module 0 index. TXD0 O TTL MII transmit data 0. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. PD6 I/O TTL GPIO port D bit 6. AIN5 I Analog Fault0 I TTL PWM Fault 0. I2S0TXSCK I/O TTL I2S module 0 transmit clock. TXD1 O TTL Ethernet MII transmit data 1. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PE2 I/O TTL GPIO port E bit 2. AIN9 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. PhA0 I TTL QEI module 0 phase A. PhB1 I TTL QEI module 1 phase B. SSI module 1 receive. SSI1Rx I TTL GNDA - Power A5 A6 Description U1CTS A2 A3 a Pin Name Analog-to-digital converter input 5. Analog-to-digital converter input 9. The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. PB4 I/O TTL AIN10 I Analog GPIO port B bit 4. Analog-to-digital converter input 10. Analog comparator 0 negative input. C0- I Analog CAN0Rx I TTL CAN module 0 receive. IDX0 I TTL QEI module 0 index. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. July 22, 2011 1151 Texas Instruments-Production Data Signal Tables Table 23-7. Signals by Pin Number (continued) Pin Number A7 A8 A9 A10 A11 a Pin Name Pin Type Buffer Type Description PB6 I/O TTL C0+ I Analog C0o O TTL Analog comparator 0 output. CCP1 I/O TTL Capture/Compare/PWM 1. CCP5 I/O TTL Capture/Compare/PWM 5. GPIO port B bit 6. Analog comparator 0 positive input. CCP7 I/O TTL Capture/Compare/PWM 7. Fault1 I TTL PWM Fault 1. I2S0TXSCK I/O TTL I2S module 0 transmit clock. QEI module 0 index. IDX0 I TTL VREFA I Analog PB7 I/O TTL GPIO port B bit 7. This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 1023. The VREFA input is limited to the range specified in Table 25-18 on page 1200. NMI I TTL Non-maskable interrupt. RXD1 I TTL MII receive data 1. PC0 I/O TTL GPIO port C bit 0. SWCLK I TTL JTAG/SWD CLK. TCK I TTL JTAG/SWD CLK. PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. PB2 I/O TTL GPIO port B bit 2. CCP0 I/O TTL Capture/Compare/PWM 0. CCP3 I/O TTL Capture/Compare/PWM 3. I2C0SCL I/O OD I2C module 0 clock. IDX0 I TTL QEI module 0 index. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. PE1 I/O TTL GPIO port E bit 1. CCP2 I/O TTL Capture/Compare/PWM 2. CCP6 I/O TTL Capture/Compare/PWM 6. Fault0 I TTL PWM Fault 0. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. SSI1Fss I/O TTL SSI module 1 frame. PE7 I/O TTL GPIO port E bit 7. AIN0 I Analog PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. A12 B1 Analog-to-digital converter input 0. 1152 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-7. Signals by Pin Number (continued) Pin Number B2 Pin Name Pin Type B5 B6 Description PE4 I/O TTL AIN3 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. GPIO port E bit 4. Analog-to-digital converter input 3. CCP3 I/O TTL Capture/Compare/PWM 3. Fault0 I TTL PWM Fault 0. I2S0TXWS I/O TTL I2S module 0 transmit word select. RXD0 I TTL MII receive data 0. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PE5 I/O TTL GPIO port E bit 5. AIN2 I Analog CCP5 I/O TTL Capture/Compare/PWM 5. I2S0TXSD I/O TTL I2S module 0 transmit data. GPIO port E bit 3. B3 B4 a Buffer Type Analog-to-digital converter input 2. PE3 I/O TTL AIN8 I Analog CCP1 I/O TTL Capture/Compare/PWM 1. CCP7 I/O TTL Capture/Compare/PWM 7. PhA1 I TTL QEI module 1 phase A. Analog-to-digital converter input 8. PhB0 I TTL QEI module 0 phase B. SSI1Tx O TTL SSI module 1 transmit. PD4 I/O TTL GPIO port D bit 4. AIN7 I Analog CCP0 I/O TTL Capture/Compare/PWM 0. Analog-to-digital converter input 7. CCP3 I/O TTL Capture/Compare/PWM 3. I2S0RXSD I/O TTL I2S module 0 receive data. TXD3 O TTL Ethernet MII transmit data 3. U1RI I TTL UART module 1 Ring Indicator modem status input signal. PJ1 I/O TTL GPIO port J bit 1. I2C1SDA I/O OD I2C module 1 data. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. July 22, 2011 1153 Texas Instruments-Production Data Signal Tables Table 23-7. Signals by Pin Number (continued) Pin Number B7 Pin Name Pin Type PB5 I/O TTL AIN11 I Analog C0o O TTL B10 Description GPIO port B bit 5. Analog-to-digital converter input 11. Analog comparator 0 output. C1- I Analog CAN0Tx O TTL CAN module 0 transmit. CCP0 I/O TTL Capture/Compare/PWM 0. CCP2 I/O TTL Capture/Compare/PWM 2. CCP5 I/O TTL Capture/Compare/PWM 5. CCP6 I/O TTL Capture/Compare/PWM 6. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PC2 I/O TTL GPIO port C bit 2. TDI I TTL JTAG TDI. PC1 I/O TTL GPIO port C bit 1. SWDIO I/O TTL JTAG TMS and SWDIO. TMS I TTL JTAG TMS and SWDIO. PH4 I/O TTL GPIO port H bit 4. SSI1Clk I/O TTL SSI module 1 clock. B8 B9 a Buffer Type Analog comparator 1 negative input. TXD1 O TTL Ethernet MII transmit data 1. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PE0 I/O TTL GPIO port E bit 0. CCP3 I/O TTL Capture/Compare/PWM 3. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. SSI1Clk I/O TTL SSI module 1 clock. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. USB0RBIAS O Analog 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. C1 NC - - No connect. Leave the pin electrically unconnected/isolated. C2 NC - - No connect. Leave the pin electrically unconnected/isolated. VDDC - Power Positive supply for most of the logic function, including the processor core and most peripherals. C4 GND - Power Ground reference for logic and I/O pins. C5 GND - Power Ground reference for logic and I/O pins. PD5 I/O TTL AIN6 I Analog CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. I2S0RXMCLK I/O TTL I2S module 0 receive master clock. TXD2 O TTL MII transmit data 2. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. B11 B12 C3 C6 GPIO port D bit 5. Analog-to-digital converter input 6. 1154 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-7. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type VDDA - Power PH1 I/O TTL GPIO port H bit 1. CCP7 I/O TTL Capture/Compare/PWM 7. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. C7 C8 Description The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. PH0 I/O TTL GPIO port H bit 0. CCP6 I/O TTL Capture/Compare/PWM 6. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. PG7 I/O TTL GPIO port G bit 7. CCP5 I/O TTL Capture/Compare/PWM 5. PhB1 I TTL QEI module 1 phase B. TXER O TTL MII transmit error. USB0DM I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. D1 NC - - No connect. Leave the pin electrically unconnected/isolated. D2 NC - - No connect. Leave the pin electrically unconnected/isolated. VDDC - Power PH3 I/O TTL GPIO port H bit 3. Fault0 I TTL PWM Fault 0. PhB0 I TTL QEI module 0 phase B. C9 C10 C11 C12 D3 D10 D11 Positive supply for most of the logic function, including the processor core and most peripherals. TXD2 O TTL MII transmit data 2. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. PH2 I/O TTL GPIO port H bit 2. C1o O TTL Analog comparator 1 output. Fault3 I TTL PWM Fault 3. IDX1 I TTL QEI module 1 index. TXD3 O TTL Ethernet MII transmit data 3. PB1 I/O TTL GPIO port B bit 1. This pin is not 5-V tolerant. CCP1 I/O TTL Capture/Compare/PWM 1. CCP2 I/O TTL Capture/Compare/PWM 2. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. USB0VBUS I/O Analog This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing. D12 July 22, 2011 1155 Texas Instruments-Production Data Signal Tables Table 23-7. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type E1 NC - - No connect. Leave the pin electrically unconnected/isolated. E2 NC - - No connect. Leave the pin electrically unconnected/isolated. LDO - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). VDD - Power Positive supply for I/O and some logic. PB3 I/O TTL GPIO port B bit 3. Fault0 I TTL PWM Fault 0. Fault3 I TTL PWM Fault 3. I2C0SDA I/O OD I2C module 0 data. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. E3 E10 E11 Description PB0 I/O TTL GPIO port B bit 0. This pin is not 5-V tolerant. CCP0 I/O TTL Capture/Compare/PWM 0. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. USB0ID I Analog This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side). F1 NC - - No connect. Leave the pin electrically unconnected/isolated. F2 NC - - No connect. Leave the pin electrically unconnected/isolated. E12 PJ0 I/O TTL GPIO port J bit 0. I2C1SCL I/O OD I2C module 1 clock. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. RXER I TTL MII receive error. PH5 I/O TTL GPIO port H bit 5. Fault2 I TTL PWM Fault 2. SSI1Fss I/O TTL SSI module 1 frame. TXD0 O TTL MII transmit data 0. F11 GND - Power Ground reference for logic and I/O pins. F12 GND - Power Ground reference for logic and I/O pins. F3 F10 1156 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-7. Signals by Pin Number (continued) Pin Number G1 G2 Pin Name Pin Type a Buffer Type Description PD0 I/O TTL AIN15 I Analog GPIO port D bit 0. CAN0Rx I TTL CAN module 0 receive. Analog-to-digital converter input 15. CCP6 I/O TTL Capture/Compare/PWM 6. I2S0RXSCK I/O TTL I2S module 0 receive clock. IDX0 I TTL QEI module 0 index. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. RXDV I TTL MII receive data valid. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. PD1 I/O TTL GPIO port D bit 1. AIN14 I Analog CAN0Tx O TTL CAN module 0 transmit. CCP2 I/O TTL Capture/Compare/PWM 2. Analog-to-digital converter input 14. CCP7 I/O TTL Capture/Compare/PWM 7. I2S0RXWS I/O TTL I2S module 0 receive word select. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. PhA0 I TTL QEI module 0 phase A. PhB1 I TTL QEI module 1 phase B. TXER O TTL MII transmit error. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PH6 I/O TTL GPIO port H bit 6. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. G3 RXDV I TTL MII receive data valid. SSI1Rx I TTL SSI module 1 receive. G10 VDD - Power Positive supply for I/O and some logic. G11 VDD - Power Positive supply for I/O and some logic. G12 VDD - Power Positive supply for I/O and some logic. H1 PD3 I/O TTL AIN12 I Analog GPIO port D bit 3. CCP0 I/O TTL Capture/Compare/PWM 0. CCP7 I/O TTL Capture/Compare/PWM 7. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. Analog-to-digital converter input 12. July 22, 2011 1157 Texas Instruments-Production Data Signal Tables Table 23-7. Signals by Pin Number (continued) Pin Number H2 Pin Name Pin Type a Buffer Type Description PD2 I/O TTL AIN13 I Analog GPIO port D bit 2. CCP5 I/O TTL Capture/Compare/PWM 5. CCP6 I/O TTL Capture/Compare/PWM 6. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. Analog-to-digital converter input 13. PH7 I/O TTL GPIO port H bit 7. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. RXCK I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. SSI1Tx O TTL SSI module 1 transmit. H10 VDD - Power H11 RST I TTL System reset input. PF1 I/O TTL GPIO port F bit 1. CAN1Tx O TTL CAN module 1 transmit. CCP3 I/O TTL Capture/Compare/PWM 3. I2S0TXMCLK I/O TTL I2S module 0 transmit master clock. IDX1 I TTL QEI module 1 index. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. H3 H12 Positive supply for I/O and some logic. RXER I TTL MII receive error. U1RTS O TTL UART module 1 Request to Send modem flow control output line. PG2 I/O TTL GPIO port G bit 2. COL I TTL MII collision detect. Fault0 I TTL PWM Fault 0. I2S0RXSD I/O TTL I2S module 0 receive data. IDX1 I TTL QEI module 1 index. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. PG3 I/O TTL GPIO port G bit 3. CRS I TTL MII carrier sense. Fault0 I TTL PWM Fault 0. Fault2 I TTL PWM Fault 2. I2S0RXMCLK I/O TTL I2S module 0 receive master clock. PWM 1. This signal is controlled by PWM Generator 0. J1 J2 PWM1 O TTL J3 GND - Power Ground reference for logic and I/O pins. J10 GND - Power Ground reference for logic and I/O pins. J11 PF2 I/O TTL GPIO port F bit 2. PHYINT I TTL PHY interrupt. PWM2 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. SSI1Clk I/O TTL SSI module 1 clock. 1158 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-7. Signals by Pin Number (continued) Pin Number J12 K1 K2 K3 K4 a Pin Name Pin Type Buffer Type Description PF3 I/O TTL GPIO port F bit 3. MDC O TTL MII management clock. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. SSI1Fss I/O TTL SSI module 1 frame. PG0 I/O TTL GPIO port G bit 0. I2C1SCL I/O OD I2C module 1 clock. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. U2Rx I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. PG1 I/O TTL GPIO port G bit 1. I2C1SDA I/O OD I2C module 1 data. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. U2Tx O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. PG4 I/O TTL GPIO port G bit 4. CCP3 I/O TTL Capture/Compare/PWM 3. Fault1 I TTL PWM Fault 1. RXD0 I TTL MII receive data 0. U1RI I TTL UART module 1 Ring Indicator modem status input signal. PF7 I/O TTL GPIO port F bit 7. CCP4 I/O TTL Capture/Compare/PWM 4. Fault1 I TTL PWM Fault 1. PhB0 I TTL QEI module 0 phase B. MII receive data 1. RXD1 I TTL K5 GND - Power PJ2 I/O TTL GPIO port J bit 2. K6 CCP0 I/O TTL Capture/Compare/PWM 0. Fault0 I TTL PWM Fault 0. K7 VDD - Power Positive supply for I/O and some logic. K8 VDD - Power Positive supply for I/O and some logic. K9 VDD - Power Positive supply for I/O and some logic. K10 GND - Power Ground reference for logic and I/O pins. PJ4 I/O TTL GPIO port J bit 4. CCP4 I/O TTL Capture/Compare/PWM 4. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. K11 Ground reference for logic and I/O pins. July 22, 2011 1159 Texas Instruments-Production Data Signal Tables Table 23-7. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type PJ5 I/O TTL GPIO port J bit 5. K12 CCP2 I/O TTL Capture/Compare/PWM 2. U1DSR I TTL UART module 1 Data Set Ready modem output control line. L1 L2 L3 L4 L5 Description PC4 I/O TTL GPIO port C bit 4. CCP1 I/O TTL Capture/Compare/PWM 1. CCP2 I/O TTL Capture/Compare/PWM 2. CCP4 I/O TTL Capture/Compare/PWM 4. CCP5 I/O TTL Capture/Compare/PWM 5. PhA0 I TTL QEI module 0 phase A. TXD3 O TTL Ethernet MII transmit data 3. PC7 I/O TTL GPIO port C bit 7. C1o O TTL Analog comparator 1 output. CCP0 I/O TTL Capture/Compare/PWM 0. CCP4 I/O TTL Capture/Compare/PWM 4. PhB0 I TTL QEI module 0 phase B. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PA0 I/O TTL GPIO port A bit 0. I2C1SCL I/O OD I2C module 1 clock. U0Rx I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. PA3 I/O TTL GPIO port A bit 3. I2S0RXMCLK I/O TTL I2S module 0 receive master clock. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. SSI0Fss I/O TTL SSI module 0 frame. TXD1 O TTL Ethernet MII transmit data 1. PA4 I/O TTL GPIO port A bit 4. CAN0Rx I TTL CAN module 0 receive. I2S0TXSCK I/O TTL I2S module 0 transmit clock. SSI0Rx I TTL SSI module 0 receive. TXD0 O TTL MII transmit data 0. 1160 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-7. Signals by Pin Number (continued) Pin Number L6 L7 L8 a Pin Name Pin Type Buffer Type Description PA6 I/O TTL GPIO port A bit 6. CAN0Rx I TTL CAN module 0 receive. CCP1 I/O TTL Capture/Compare/PWM 1. I2C1SCL I/O OD I2C module 1 clock. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. RXCK I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. PG6 I/O TTL GPIO port G bit 6. Fault1 I TTL PWM Fault 1. I2S0RXWS I/O TTL I2S module 0 receive word select. PhA1 I TTL QEI module 1 phase A. TXCK I TTL MII transmit clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. U1RI I TTL UART module 1 Ring Indicator modem status input signal. PF5 I/O TTL GPIO port F bit 5. C1o O TTL Analog comparator 1 output. CCP2 I/O TTL Capture/Compare/PWM 2. RXD3 I TTL MII receive data 3. SSI1Tx O TTL SSI module 1 transmit. PF4 I/O TTL GPIO port F bit 4. C0o O TTL Analog comparator 0 output. CCP0 I/O TTL Capture/Compare/PWM 0. Fault0 I TTL PWM Fault 0. MDIO I/O OD MDIO of the Ethernet PHY. SSI1Rx I TTL SSI module 1 receive. PJ6 I/O TTL GPIO port J bit 6. L9 CCP1 I/O TTL Capture/Compare/PWM 1. U1RTS O TTL UART module 1 Request to Send modem flow control output line. L11 OSC0 I Analog Main oscillator crystal input or an external clock reference input. PJ7 I/O TTL GPIO port J bit 7. L12 CCP0 I/O TTL Capture/Compare/PWM 0. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. L10 July 22, 2011 1161 Texas Instruments-Production Data Signal Tables Table 23-7. Signals by Pin Number (continued) Pin Number M1 M2 M3 M4 M5 a Pin Name Pin Type Buffer Type Description PC5 I/O TTL GPIO port C bit 5. C0o O TTL Analog comparator 0 output. C1+ I Analog Analog comparator 1 positive input. C1o O TTL Analog comparator 1 output. CCP1 I/O TTL Capture/Compare/PWM 1. CCP3 I/O TTL Capture/Compare/PWM 3. Fault2 I TTL PWM Fault 2. USB0EPEN O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. PC6 I/O TTL GPIO port C bit 6. CCP0 I/O TTL Capture/Compare/PWM 0. CCP3 I/O TTL Capture/Compare/PWM 3. PhB0 I TTL QEI module 0 phase B. U1Rx I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PA1 I/O TTL GPIO port A bit 1. I2C1SDA I/O OD I2C module 1 data. U0Tx O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. PA2 I/O TTL GPIO port A bit 2. I2S0RXSD I/O TTL I2S module 0 receive data. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. SSI0Clk I/O TTL SSI module 0 clock. TXD2 O TTL MII transmit data 2. PA5 I/O TTL GPIO port A bit 5. CAN0Tx O TTL CAN module 0 transmit. I2S0TXWS I/O TTL I2S module 0 transmit word select. RXDV I TTL MII receive data valid. SSI0Tx O TTL SSI module 0 transmit. 1162 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-7. Signals by Pin Number (continued) Pin Number M6 M7 Pin Type Buffer Type M10 M11 M12 Description PA7 I/O TTL GPIO port A bit 7. CAN0Tx O TTL CAN module 0 transmit. CCP3 I/O TTL Capture/Compare/PWM 3. CCP4 I/O TTL Capture/Compare/PWM 4. I2C1SDA I/O OD I2C module 1 data. PWM1 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM5 O TTL PWM 5. This signal is controlled by PWM Generator 2. RXER I TTL MII receive error. U1DCD I TTL UART module 1 Data Carrier Detect modem status input signal. USB0PFLT I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. PG5 I/O TTL GPIO port G bit 5. CCP5 I/O TTL Capture/Compare/PWM 5. Fault1 I TTL PWM Fault 1. I2S0RXSCK I/O TTL I2S module 0 receive clock. IDX0 I TTL QEI module 0 index. TXEN O TTL MII transmit enable. U1DTR O TTL UART module 1 Data Terminal Ready modem status input signal. PF6 I/O TTL GPIO port F bit 6. CCP1 I/O TTL Capture/Compare/PWM 1. I2S0TXMCLK I/O TTL I2S module 0 transmit master clock. PhA0 I TTL QEI module 0 phase A. RXD2 I TTL MII receive data 2. U1RTS O TTL UART module 1 Request to Send modem flow control output line. PF0 I/O TTL GPIO port F bit 0. CAN1Rx I TTL CAN module 1 receive. I2S0TXSD I/O TTL I2S module 0 transmit data. PWM0 O TTL PWM 0. This signal is controlled by PWM Generator 0. PhB0 I TTL QEI module 0 phase B. RXCK I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. U1DSR I TTL UART module 1 Data Set Ready modem output control line. PJ3 I/O TTL GPIO port J bit 3. M8 M9 a Pin Name CCP6 I/O TTL Capture/Compare/PWM 6. U1CTS I TTL UART module 1 Clear To Send modem flow control input signal. OSC1 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. NC - - No connect. Leave the pin electrically unconnected/isolated. a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 22, 2011 1163 Texas Instruments-Production Data Signal Tables Table 23-8. Signals by Signal Name Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description AIN0 B1 PE7 I Analog Analog-to-digital converter input 0. AIN1 A1 PE6 I Analog Analog-to-digital converter input 1. AIN2 B3 PE5 I Analog Analog-to-digital converter input 2. AIN3 B2 PE4 I Analog Analog-to-digital converter input 3. AIN4 A2 PD7 I Analog Analog-to-digital converter input 4. AIN5 A3 PD6 I Analog Analog-to-digital converter input 5. AIN6 C6 PD5 I Analog Analog-to-digital converter input 6. AIN7 B5 PD4 I Analog Analog-to-digital converter input 7. AIN8 B4 PE3 I Analog Analog-to-digital converter input 8. AIN9 A4 PE2 I Analog Analog-to-digital converter input 9. AIN10 A6 PB4 I Analog Analog-to-digital converter input 10. AIN11 B7 PB5 I Analog Analog-to-digital converter input 11. AIN12 H1 PD3 I Analog Analog-to-digital converter input 12. AIN13 H2 PD2 I Analog Analog-to-digital converter input 13. AIN14 G2 PD1 I Analog Analog-to-digital converter input 14. AIN15 G1 PD0 I Analog Analog-to-digital converter input 15. C0+ A7 PB6 I Analog Analog comparator 0 positive input. C0- A6 PB4 I Analog Analog comparator 0 negative input. C0o M1 L9 A7 B7 A2 PC5 (3) PF4 (2) PB6 (3) PB5 (1) PD7 (2) O TTL Analog comparator 0 output. C1+ M1 PC5 I Analog Analog comparator 1 positive input. C1- B7 PB5 I Analog Analog comparator 1 negative input. C1o A1 L2 M1 L8 D11 PE6 (2) PC7 (7) PC5 (2) PF5 (2) PH2 (2) O TTL Analog comparator 1 output. CAN0Rx G1 L5 L6 A6 PD0 (2) PA4 (5) PA6 (6) PB4 (5) I TTL CAN module 0 receive. CAN0Tx G2 M5 M6 B7 PD1 (2) PA5 (5) PA7 (6) PB5 (5) O TTL CAN module 0 transmit. CAN1Rx M9 PF0 (1) I TTL CAN module 1 receive. CAN1Tx H12 PF1 (1) O TTL CAN module 1 transmit. 1164 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP0 H1 L2 M2 K6 L12 L9 E12 A11 B7 B5 PD3 (4) PC7 (4) PC6 (6) PJ2 (9) PJ7 (10) PF4 (1) PB0 (1) PB2 (5) PB5 (4) PD4 (1) I/O TTL Capture/Compare/PWM 0. CCP1 M1 L1 L6 M8 L10 D12 A7 B4 A2 PC5 (1) PC4 (9) PA6 (2) PF6 (1) PJ6 (10) PB1 (4) PB6 (1) PE3 (1) PD7 (3) I/O TTL Capture/Compare/PWM 1. CCP2 B2 G2 L1 L8 K12 D12 A12 B7 A4 C6 PE4 (6) PD1 (10) PC4 (5) PF5 (1) PJ5 (10) PB1 (1) PE1 (4) PB5 (6) PE2 (5) PD5 (1) I/O TTL Capture/Compare/PWM 2. CCP3 B2 M2 M1 M6 K3 H12 A11 B11 B5 PE4 (1) PC6 (1) PC5 (5) PA7 (7) PG4 (1) PF1 (10) PB2 (4) PE0 (3) PD4 (2) I/O TTL Capture/Compare/PWM 3. CCP4 L2 L1 M6 K4 K11 A4 C6 PC7 (1) PC4 (6) PA7 (2) PF7 (1) PJ4 (10) PE2 (1) PD5 (2) I/O TTL Capture/Compare/PWM 4. CCP5 B3 H2 L1 C10 M7 A7 B7 PE5 (1) PD2 (4) PC4 (1) PG7 (8) PG5 (1) PB6 (6) PB5 (2) I/O TTL Capture/Compare/PWM 5. July 22, 2011 1165 Texas Instruments-Production Data Signal Tables Table 23-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description CCP6 G1 H2 M10 A12 C9 B7 PD0 (6) PD2 (2) PJ3 (10) PE1 (5) PH0 (1) PB5 (3) I/O TTL Capture/Compare/PWM 6. CCP7 G2 H1 C8 A7 B4 PD1 (6) PD3 (2) PH1 (1) PB6 (2) PE3 (5) I/O TTL Capture/Compare/PWM 7. COL J1 PG2 (3) I TTL MII collision detect. CRS J2 PG3 (3) I TTL MII carrier sense. Fault0 B2 J2 J1 K6 L9 E11 A12 D10 A3 PE4 (4) PG3 (8) PG2 (4) PJ2 (10) PF4 (4) PB3 (2) PE1 (3) PH3 (2) PD6 (1) I TTL PWM Fault 0. Fault1 L7 M7 K3 K4 A7 PG6 (8) PG5 (5) PG4 (4) PF7 (9) PB6 (4) I TTL PWM Fault 1. Fault2 J2 M1 F10 PG3 (4) PC5 (4) PH5 (10) I TTL PWM Fault 2. Fault3 E11 D11 PB3 (4) PH2 (4) I TTL PWM Fault 3. GND C4 C5 J3 K5 K10 J10 F11 F12 fixed - Power Ground reference for logic and I/O pins. GNDA A5 fixed - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. I2C0SCL A11 PB2 (1) I/O OD I2C module 0 clock. I2C0SDA E11 PB3 (1) I/O OD I2C module 0 data. I2C1SCL F3 K1 L3 L6 PJ0 (11) PG0 (3) PA0 (8) PA6 (1) I/O OD I2C module 1 clock. 1166 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description I2C1SDA K2 M3 M6 B6 PG1 (3) PA1 (8) PA7 (1) PJ1 (11) I/O OD I2C module 1 data. I2S0RXMCLK J2 L4 C6 PG3 (9) PA3 (9) PD5 (8) I/O TTL I2S module 0 receive master clock. I2S0RXSCK G1 M7 PD0 (8) PG5 (9) I/O TTL I2S module 0 receive clock. I2S0RXSD J1 M4 B5 PG2 (9) PA2 (9) PD4 (8) I/O TTL I2S module 0 receive data. I2S0RXWS G2 L7 PD1 (8) PG6 (9) I/O TTL I2S module 0 receive word select. I2S0TXMCLK M8 H12 PF6 (9) PF1 (8) I/O TTL I2S module 0 transmit master clock. I2S0TXSCK L5 A7 A3 PA4 (9) PB6 (9) PD6 (8) I/O TTL I2S module 0 transmit clock. I2S0TXSD B3 M9 PE5 (9) PF0 (8) I/O TTL I2S module 0 transmit data. I2S0TXWS B2 M5 A2 PE4 (9) PA5 (9) PD7 (8) I/O TTL I2S module 0 transmit word select. IDX0 G1 M7 A11 A7 A6 A2 PD0 (3) PG5 (4) PB2 (2) PB6 (5) PB4 (6) PD7 (1) I TTL QEI module 0 index. IDX1 J1 H12 D11 PG2 (8) PF1 (2) PH2 (1) I TTL QEI module 1 index. LDO E3 fixed - Power MDC J12 PF3 (3) O TTL MII management clock. MDIO L9 PF4 (3) I/O OD MDIO of the Ethernet PHY. NC M12 C1 C2 D2 D1 E1 E2 F1 F2 fixed - - NMI A8 PB7 (4) I TTL Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). No connect. Leave the pin electrically unconnected/isolated. Non-maskable interrupt. July 22, 2011 1167 Texas Instruments-Production Data Signal Tables Table 23-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description OSC0 L11 fixed I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 fixed O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. PA0 L3 - I/O TTL GPIO port A bit 0. PA1 M3 - I/O TTL GPIO port A bit 1. PA2 M4 - I/O TTL GPIO port A bit 2. PA3 L4 - I/O TTL GPIO port A bit 3. PA4 L5 - I/O TTL GPIO port A bit 4. PA5 M5 - I/O TTL GPIO port A bit 5. PA6 L6 - I/O TTL GPIO port A bit 6. PA7 M6 - I/O TTL GPIO port A bit 7. PB0 E12 - I/O TTL GPIO port B bit 0. This pin is not 5-V tolerant. PB1 D12 - I/O TTL GPIO port B bit 1. This pin is not 5-V tolerant. PB2 A11 - I/O TTL GPIO port B bit 2. PB3 E11 - I/O TTL GPIO port B bit 3. PB4 A6 - I/O TTL GPIO port B bit 4. PB5 B7 - I/O TTL GPIO port B bit 5. PB6 A7 - I/O TTL GPIO port B bit 6. PB7 A8 - I/O TTL GPIO port B bit 7. PC0 A9 - I/O TTL GPIO port C bit 0. PC1 B9 - I/O TTL GPIO port C bit 1. PC2 B8 - I/O TTL GPIO port C bit 2. PC3 A10 - I/O TTL GPIO port C bit 3. PC4 L1 - I/O TTL GPIO port C bit 4. PC5 M1 - I/O TTL GPIO port C bit 5. PC6 M2 - I/O TTL GPIO port C bit 6. PC7 L2 - I/O TTL GPIO port C bit 7. PD0 G1 - I/O TTL GPIO port D bit 0. PD1 G2 - I/O TTL GPIO port D bit 1. PD2 H2 - I/O TTL GPIO port D bit 2. PD3 H1 - I/O TTL GPIO port D bit 3. PD4 B5 - I/O TTL GPIO port D bit 4. PD5 C6 - I/O TTL GPIO port D bit 5. PD6 A3 - I/O TTL GPIO port D bit 6. PD7 A2 - I/O TTL GPIO port D bit 7. PE0 B11 - I/O TTL GPIO port E bit 0. PE1 A12 - I/O TTL GPIO port E bit 1. PE2 A4 - I/O TTL GPIO port E bit 2. PE3 B4 - I/O TTL GPIO port E bit 3. PE4 B2 - I/O TTL GPIO port E bit 4. 1168 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-8. Signals by Signal Name (continued) Pin Name PE5 Pin Number Pin Mux / Pin Assignment B3 - a Pin Type Buffer Type I/O TTL Description GPIO port E bit 5. PE6 A1 - I/O TTL GPIO port E bit 6. PE7 B1 - I/O TTL GPIO port E bit 7. PF0 M9 - I/O TTL GPIO port F bit 0. PF1 H12 - I/O TTL GPIO port F bit 1. PF2 J11 - I/O TTL GPIO port F bit 2. PF3 J12 - I/O TTL GPIO port F bit 3. PF4 L9 - I/O TTL GPIO port F bit 4. PF5 L8 - I/O TTL GPIO port F bit 5. PF6 M8 - I/O TTL GPIO port F bit 6. PF7 K4 - I/O TTL GPIO port F bit 7. PG0 K1 - I/O TTL GPIO port G bit 0. PG1 K2 - I/O TTL GPIO port G bit 1. PG2 J1 - I/O TTL GPIO port G bit 2. PG3 J2 - I/O TTL GPIO port G bit 3. PG4 K3 - I/O TTL GPIO port G bit 4. PG5 M7 - I/O TTL GPIO port G bit 5. PG6 L7 - I/O TTL GPIO port G bit 6. PG7 C10 - I/O TTL GPIO port G bit 7. PH0 C9 - I/O TTL GPIO port H bit 0. PH1 C8 - I/O TTL GPIO port H bit 1. PH2 D11 - I/O TTL GPIO port H bit 2. PH3 D10 - I/O TTL GPIO port H bit 3. PH4 B10 - I/O TTL GPIO port H bit 4. PH5 F10 - I/O TTL GPIO port H bit 5. PH6 G3 - I/O TTL GPIO port H bit 6. PH7 H3 - I/O TTL GPIO port H bit 7. PhA0 G2 L1 M8 A4 PD1 (3) PC4 (2) PF6 (4) PE2 (4) I TTL QEI module 0 phase A. PhA1 L7 B4 PG6 (1) PE3 (3) I TTL QEI module 1 phase A. PhB0 L2 M2 K4 M9 D10 B4 PC7 (2) PC6 (2) PF7 (4) PF0 (2) PH3 (1) PE3 (4) I TTL QEI module 0 phase B. PhB1 G2 C10 A4 PD1 (11) PG7 (1) PE2 (3) I TTL QEI module 1 phase B. PHYINT J11 PF2 (3) I TTL PHY interrupt. PJ0 F3 - I/O TTL GPIO port J bit 0. July 22, 2011 1169 Texas Instruments-Production Data Signal Tables Table 23-8. Signals by Signal Name (continued) Pin Name PJ1 Pin Number Pin Mux / Pin Assignment B6 - a Pin Type Buffer Type I/O TTL Description GPIO port J bit 1. PJ2 K6 - I/O TTL GPIO port J bit 2. PJ3 M10 - I/O TTL GPIO port J bit 3. PJ4 K11 - I/O TTL GPIO port J bit 4. PJ5 K12 - I/O TTL GPIO port J bit 5. PJ6 L10 - I/O TTL GPIO port J bit 6. PJ7 L12 - I/O TTL GPIO port J bit 7. PWM0 G1 F3 J1 K1 L6 M9 PD0 (1) PJ0 (10) PG2 (1) PG0 (2) PA6 (4) PF0 (3) O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 G2 J2 K2 M6 H12 B6 PD1 (1) PG3 (1) PG1 (2) PA7 (4) PF1 (3) PJ1 (10) O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 H2 J11 E12 C9 PD2 (3) PF2 (4) PB0 (2) PH0 (2) O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 H1 J12 D12 C8 PD3 (3) PF3 (4) PB1 (2) PH1 (2) O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 A1 K1 M4 L6 J11 G3 B11 C9 PE6 (1) PG0 (4) PA2 (4) PA6 (5) PF2 (2) PH6 (10) PE0 (1) PH0 (9) O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 B1 H3 K2 L4 M6 J12 A12 C8 PE7 (1) PH7 (10) PG1 (4) PA3 (4) PA7 (5) PF3 (2) PE1 (1) PH1 (9) O TTL PWM 5. This signal is controlled by PWM Generator 2. RST H11 fixed I TTL System reset input. RXCK H3 L6 M9 PH7 (3) PA6 (3) PF0 (4) I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. RXD0 B2 K3 PE4 (7) PG4 (3) I TTL MII receive data 0. RXD1 K4 A8 PF7 (3) PB7 (7) I TTL MII receive data 1. 1170 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-8. Signals by Signal Name (continued) Pin Name RXD2 Pin Number Pin Mux / Pin Assignment M8 PF6 (3) a Pin Type Buffer Type I TTL Description MII receive data 2. RXD3 L8 PF5 (3) I TTL MII receive data 3. RXDV G1 M5 G3 PD0 (7) PA5 (3) PH6 (9) I TTL MII receive data valid. RXER F3 M6 H12 PJ0 (3) PA7 (3) PF1 (4) I TTL MII receive error. SSI0Clk M4 PA2 (1) I/O TTL SSI module 0 clock. SSI0Fss L4 PA3 (1) I/O TTL SSI module 0 frame. SSI0Rx L5 PA4 (1) I TTL SSI module 0 receive. SSI0Tx M5 PA5 (1) O TTL SSI module 0 transmit. SSI1Clk J11 B11 B10 PF2 (9) PE0 (2) PH4 (11) I/O TTL SSI module 1 clock. SSI1Fss J12 F10 A12 PF3 (9) PH5 (11) PE1 (2) I/O TTL SSI module 1 frame. SSI1Rx L9 G3 A4 PF4 (9) PH6 (11) PE2 (2) I TTL SSI module 1 receive. SSI1Tx H3 L8 B4 PH7 (11) PF5 (9) PE3 (2) O TTL SSI module 1 transmit. SWCLK A9 PC0 (3) I TTL JTAG/SWD CLK. SWDIO B9 PC1 (3) I/O TTL JTAG TMS and SWDIO. SWO A10 PC3 (3) O TTL JTAG TDO and SWO. TCK A9 PC0 (3) I TTL JTAG/SWD CLK. TDI B8 PC2 (3) I TTL JTAG TDI. TDO A10 PC3 (3) O TTL JTAG TDO and SWO. TMS B9 PC1 (3) I TTL JTAG TMS and SWDIO. TXCK L7 PG6 (3) I TTL MII transmit clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. TXD0 L5 F10 A2 PA4 (3) PH5 (9) PD7 (4) O TTL MII transmit data 0. TXD1 L4 B10 A3 PA3 (3) PH4 (9) PD6 (4) O TTL Ethernet MII transmit data 1. TXD2 M4 D10 C6 PA2 (3) PH3 (9) PD5 (4) O TTL MII transmit data 2. TXD3 L1 D11 B5 PC4 (3) PH2 (9) PD4 (4) O TTL Ethernet MII transmit data 3. TXEN M7 PG5 (3) O TTL MII transmit enable. July 22, 2011 1171 Texas Instruments-Production Data Signal Tables Table 23-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description TXER G2 C10 PD1 (7) PG7 (3) O TTL MII transmit error. U0Rx L3 PA0 (1) I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 PA1 (1) O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS A1 G1 L6 M10 PE6 (9) PD0 (9) PA6 (9) PJ3 (9) I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD B1 G2 M6 K11 PE7 (9) PD1 (9) PA7 (9) PJ4 (9) I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR M9 K12 PF0 (9) PJ5 (9) I TTL UART module 1 Data Set Ready modem output control line. U1DTR M7 L12 A2 PG5 (10) PJ7 (9) PD7 (9) O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI L7 K3 B5 PG6 (10) PG4 (10) PD4 (9) I TTL UART module 1 Ring Indicator modem status input signal. U1RTS M8 L10 H12 PF6 (10) PJ6 (9) PF1 (9) O TTL UART module 1 Request to Send modem flow control output line. U1Rx G1 H2 M2 L3 E12 A6 PD0 (5) PD2 (1) PC6 (5) PA0 (9) PB0 (5) PB4 (7) I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx G2 H1 L2 M3 D12 B7 PD1 (5) PD3 (1) PC7 (5) PA1 (9) PB1 (5) PB5 (7) O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx G1 K1 A6 C6 PD0 (4) PG0 (1) PB4 (4) PD5 (9) I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx B2 G2 K2 A3 PE4 (5) PD1 (4) PG1 (1) PD6 (9) O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. USB0DM C11 fixed I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP C12 fixed I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. 1172 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-8. Signals by Signal Name (continued) Pin Name Pin Number Pin Mux / Pin Assignment a Pin Type Buffer Type Description USB0EPEN K1 M1 L6 A11 D10 PG0 (7) PC5 (6) PA6 (8) PB2 (8) PH3 (4) O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0ID E12 PB0 I Analog This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side). USB0PFLT L2 M2 M6 E11 B11 B10 B6 PC7 (6) PC6 (7) PA7 (8) PB3 (8) PE0 (9) PH4 (4) PJ1 (9) I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. USB0RBIAS B12 fixed O Analog 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. USB0VBUS D12 PB1 I/O Analog This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing. VDD K7 G12 K8 K9 H10 G10 E10 G11 fixed - Power Positive supply for I/O and some logic. VDDA C7 fixed - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. VDDC D3 C3 fixed - Power Positive supply for most of the logic function, including the processor core and most peripherals. VREFA A7 PB6 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 1023. The VREFA input is limited to the range specified in Table 25-18 on page 1200. a. The TTL designation indicates the pin has TTL-compatible voltage levels. July 22, 2011 1173 Texas Instruments-Production Data Signal Tables Table 23-9. Signals by Function, Except for GPIO Function ADC Pin Name Pin Type Buffer Type AIN0 B1 I Analog Analog-to-digital converter input 0. AIN1 A1 I Analog Analog-to-digital converter input 1. AIN2 B3 I Analog Analog-to-digital converter input 2. AIN3 B2 I Analog Analog-to-digital converter input 3. AIN4 A2 I Analog Analog-to-digital converter input 4. AIN5 A3 I Analog Analog-to-digital converter input 5. AIN6 C6 I Analog Analog-to-digital converter input 6. AIN7 B5 I Analog Analog-to-digital converter input 7. AIN8 B4 I Analog Analog-to-digital converter input 8. AIN9 A4 I Analog Analog-to-digital converter input 9. AIN10 A6 I Analog Analog-to-digital converter input 10. AIN11 B7 I Analog Analog-to-digital converter input 11. AIN12 H1 I Analog Analog-to-digital converter input 12. Description AIN13 H2 I Analog Analog-to-digital converter input 13. AIN14 G2 I Analog Analog-to-digital converter input 14. AIN15 G1 I Analog Analog-to-digital converter input 15. VREFA A7 I Analog This input provides a reference voltage used to specify the input voltage at which the ADC converts to a maximum value. In other words, the voltage that is applied to VREFA is the voltage with which an AINn signal is converted to 1023. The VREFA input is limited to the range specified in Table 25-18 on page 1200. C0+ A7 I Analog Analog comparator 0 positive input. Analog comparator 0 negative input. C0- A6 I Analog C0o M1 L9 A7 B7 A2 O TTL C1+ M1 I Analog Analog comparator 1 positive input. C1- B7 I Analog Analog comparator 1 negative input. C1o A1 L2 M1 L8 D11 O TTL Analog comparator 1 output. CAN0Rx G1 L5 L6 A6 I TTL CAN module 0 receive. CAN0Tx G2 M5 M6 B7 O TTL CAN module 0 transmit. Analog Comparators Controller Area Network a Pin Number Analog comparator 0 output. CAN1Rx M9 I TTL CAN module 1 receive. CAN1Tx H12 O TTL CAN module 1 transmit. 1174 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-9. Signals by Function, Except for GPIO (continued) Function Ethernet Pin Name a Pin Number Pin Type Buffer Type Description COL J1 I TTL MII collision detect. CRS J2 I TTL MII carrier sense. MDC J12 O TTL MII management clock. MDIO L9 I/O OD MDIO of the Ethernet PHY. PHYINT J11 I TTL PHY interrupt. RXCK H3 L6 M9 I TTL MII receive clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. RXD0 B2 K3 I TTL MII receive data 0. RXD1 K4 A8 I TTL MII receive data 1. RXD2 M8 I TTL MII receive data 2. RXD3 L8 I TTL MII receive data 3. RXDV G1 M5 G3 I TTL MII receive data valid. RXER F3 M6 H12 I TTL MII receive error. TXCK L7 I TTL MII transmit clock. 25 MHz in 100BASE-TX mode. 2.5 MHz in 10BASE-T mode. TXD0 L5 F10 A2 O TTL MII transmit data 0. TXD1 L4 B10 A3 O TTL Ethernet MII transmit data 1. TXD2 M4 D10 C6 O TTL MII transmit data 2. TXD3 L1 D11 B5 O TTL Ethernet MII transmit data 3. TXEN M7 O TTL MII transmit enable. TXER G2 C10 O TTL MII transmit error. July 22, 2011 1175 Texas Instruments-Production Data Signal Tables Table 23-9. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type CCP0 H1 L2 M2 K6 L12 L9 E12 A11 B7 B5 I/O TTL Capture/Compare/PWM 0. CCP1 M1 L1 L6 M8 L10 D12 A7 B4 A2 I/O TTL Capture/Compare/PWM 1. CCP2 B2 G2 L1 L8 K12 D12 A12 B7 A4 C6 I/O TTL Capture/Compare/PWM 2. CCP3 B2 M2 M1 M6 K3 H12 A11 B11 B5 I/O TTL Capture/Compare/PWM 3. CCP4 L2 L1 M6 K4 K11 A4 C6 I/O TTL Capture/Compare/PWM 4. CCP5 B3 H2 L1 C10 M7 A7 B7 I/O TTL Capture/Compare/PWM 5. I/O TTL Capture/Compare/PWM 6. General-Purpose Timers CCP6 Description 1176 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-9. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Number a Pin Type Buffer Type Description G1 H2 M10 A12 C9 B7 CCP7 G2 H1 C8 A7 B4 I/O TTL Capture/Compare/PWM 7. I2C0SCL A11 I/O OD I2C module 0 clock. I2C0SDA E11 I/O OD I2C module 0 data. I2C1SCL F3 K1 L3 L6 I/O OD I2C module 1 clock. I2C1SDA K2 M3 M6 B6 I/O OD I2C module 1 data. I2S0RXMCLK J2 L4 C6 I/O TTL I2S module 0 receive master clock. I2S0RXSCK G1 M7 I/O TTL I2S module 0 receive clock. I2S0RXSD J1 M4 B5 I/O TTL I2S module 0 receive data. I2S0RXWS G2 L7 I/O TTL I2S module 0 receive word select. I2S0TXMCLK M8 H12 I/O TTL I2S module 0 transmit master clock. I2S0TXSCK L5 A7 A3 I/O TTL I2S module 0 transmit clock. I2S0TXSD B3 M9 I/O TTL I2S module 0 transmit data. I2S0TXWS B2 M5 A2 I/O TTL I2S module 0 transmit word select. SWCLK A9 I TTL JTAG/SWD CLK. SWDIO B9 I/O TTL JTAG TMS and SWDIO. SWO A10 O TTL JTAG TDO and SWO. TCK A9 I TTL JTAG/SWD CLK. I2C I2S JTAG/SWD/SWO TDI B8 I TTL JTAG TDI. TDO A10 O TTL JTAG TDO and SWO. TMS B9 I TTL JTAG TMS and SWDIO. July 22, 2011 1177 Texas Instruments-Production Data Signal Tables Table 23-9. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type Fault0 B2 J2 J1 K6 L9 E11 A12 D10 A3 I TTL PWM Fault 0. Fault1 L7 M7 K3 K4 A7 I TTL PWM Fault 1. Fault2 J2 M1 F10 I TTL PWM Fault 2. Fault3 E11 D11 I TTL PWM Fault 3. PWM0 G1 F3 J1 K1 L6 M9 O TTL PWM 0. This signal is controlled by PWM Generator 0. PWM1 G2 J2 K2 M6 H12 B6 O TTL PWM 1. This signal is controlled by PWM Generator 0. PWM2 H2 J11 E12 C9 O TTL PWM 2. This signal is controlled by PWM Generator 1. PWM3 H1 J12 D12 C8 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 A1 K1 M4 L6 J11 G3 B11 C9 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 B1 H3 K2 L4 M6 J12 A12 C8 O TTL PWM 5. This signal is controlled by PWM Generator 2. PWM Description 1178 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-9. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type GND C4 C5 J3 K5 K10 J10 F11 F12 - Power Ground reference for logic and I/O pins. GNDA A5 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. LDO E3 - Power Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDDC pins at the board level in addition to the decoupling capacitor(s). VDD K7 G12 K8 K9 H10 G10 E10 G11 - Power Positive supply for I/O and some logic. VDDA C7 - Power The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be connected to 3.3 V, regardless of system implementation. VDDC D3 C3 - Power Positive supply for most of the logic function, including the processor core and most peripherals. Power Description July 22, 2011 1179 Texas Instruments-Production Data Signal Tables Table 23-9. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Type Buffer Type IDX0 G1 M7 A11 A7 A6 A2 I TTL QEI module 0 index. IDX1 J1 H12 D11 I TTL QEI module 1 index. PhA0 G2 L1 M8 A4 I TTL QEI module 0 phase A. PhA1 L7 B4 I TTL QEI module 1 phase A. PhB0 L2 M2 K4 M9 D10 B4 I TTL QEI module 0 phase B. PhB1 G2 C10 A4 I TTL QEI module 1 phase B. SSI0Clk M4 I/O TTL SSI module 0 clock. SSI0Fss L4 I/O TTL SSI module 0 frame. SSI0Rx L5 I TTL SSI module 0 receive. SSI0Tx M5 O TTL SSI module 0 transmit. SSI1Clk J11 B11 B10 I/O TTL SSI module 1 clock. SSI1Fss J12 F10 A12 I/O TTL SSI module 1 frame. SSI1Rx L9 G3 A4 I TTL SSI module 1 receive. SSI1Tx H3 L8 B4 O TTL SSI module 1 transmit. NMI A8 I TTL Non-maskable interrupt. OSC0 L11 I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 O Analog Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST H11 I TTL QEI SSI System Control & Clocks a Pin Number Description System reset input. 1180 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-9. Signals by Function, Except for GPIO (continued) Function UART Pin Name a Pin Number Pin Type Buffer Type Description U0Rx L3 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. U1CTS A1 G1 L6 M10 I TTL UART module 1 Clear To Send modem flow control input signal. U1DCD B1 G2 M6 K11 I TTL UART module 1 Data Carrier Detect modem status input signal. U1DSR M9 K12 I TTL UART module 1 Data Set Ready modem output control line. U1DTR M7 L12 A2 O TTL UART module 1 Data Terminal Ready modem status input signal. U1RI L7 K3 B5 I TTL UART module 1 Ring Indicator modem status input signal. U1RTS M8 L10 H12 O TTL UART module 1 Request to Send modem flow control output line. U1Rx G1 H2 M2 L3 E12 A6 I TTL UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. U1Tx G2 H1 L2 M3 D12 B7 O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. U2Rx G1 K1 A6 C6 I TTL UART module 2 receive. When in IrDA mode, this signal has IrDA modulation. U2Tx B2 G2 K2 A3 O TTL UART module 2 transmit. When in IrDA mode, this signal has IrDA modulation. July 22, 2011 1181 Texas Instruments-Production Data Signal Tables Table 23-9. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type USB0DM C11 I/O Analog Bidirectional differential data pin (D- per USB specification) for USB0. USB0DP C12 I/O Analog Bidirectional differential data pin (D+ per USB specification) for USB0. USB0EPEN K1 M1 L6 A11 D10 O TTL Optionally used in Host mode to control an external power source to supply power to the USB bus. USB0ID E12 I Analog This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side). USB0PFLT L2 M2 M6 E11 B11 B10 B6 I TTL Optionally used in Host mode by an external power source to indicate an error state by that power source. USB0RBIAS B12 O Analog 9.1-kΩ resistor (1% precision) used internally for USB analog circuitry. USB0VBUS D12 I/O Analog This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing. USB Description a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 23-10. GPIO Pins and Alternate Functions a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 8 9 10 11 PA0 L3 - U0Rx - - - - - - I2C1SCL U1Rx - - PA1 M3 - U0Tx - - - - - - I2C1SDA U1Tx - - PA2 M4 - SSI0Clk - TXD2 PWM4 - - - - I2S0RXSD - - PA3 L4 - SSI0Fss - TXD1 PWM5 - - - - I2S0RXMCLK - - PA4 L5 - SSI0Rx - TXD0 - CAN0Rx - - - I2S0TXSCK - - PA5 M5 - SSI0Tx - RXDV - CAN0Tx - - - I2S0TXWS - - PA6 L6 - I2C1SCL CCP1 RXCK PWM0 PWM4 CAN0Rx - USB0EPEN U1CTS - - USB0PFLT U1DCD PA7 M6 - I2C1SDA CCP4 RXER PWM1 PWM5 CAN0Tx CCP3 PB0 E12 USB0ID CCP0 PWM2 - - U1Rx - - - - - - - - PB1 D12 USB0VBUS CCP2 PWM3 - CCP1 U1Tx - - - - - - PB2 A11 - I2C0SCL IDX0 - CCP3 CCP0 - - USB0EPEN - - - PB3 E11 - I2C0SDA Fault0 - Fault3 - - - USB0PFLT - - - PB4 A6 AIN10 C0- - - - U2Rx CAN0Rx IDX0 U1Rx - - - - PB5 B7 AIN11 C1- C0o CCP5 CCP6 CCP0 CAN0Tx CCP2 U1Tx - - - - 1182 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-10. GPIO Pins and Alternate Functions (continued) Analog Function a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin 1 2 3 4 5 6 7 8 9 10 11 PB6 A7 VREFA C0+ CCP1 CCP7 C0o Fault1 IDX0 CCP5 - - I2S0TXSCK - - PB7 A8 - - - - NMI - - RXD1 - - - - PC0 A9 - - - TCK SWCLK - - - - - - - - PC1 B9 - - - TMS SWDIO - - - - - - - - PC2 B8 - - - TDI - - - - - - - - PC3 A10 - - - TDO SWO - - - - - - - - PC4 L1 - CCP5 PhA0 TXD3 - CCP2 CCP4 - - CCP1 - - PC5 M1 C1+ CCP1 C1o C0o Fault2 CCP3 USB0EPEN - - - - - PC6 M2 - CCP3 PhB0 - - U1Rx CCP0 USB0PFLT - - - - PC7 L2 - CCP4 PhB0 - CCP0 U1Tx USB0PFLT C1o - - - - PD0 G1 AIN15 PWM0 CAN0Rx IDX0 U2Rx U1Rx CCP6 RXDV I2S0RXSCK U1CTS - - PD1 G2 AIN14 PWM1 CAN0Tx PhA0 U2Tx U1Tx CCP7 TXER I2S0RXWS U1DCD CCP2 PhB1 PD2 H2 AIN13 U1Rx CCP6 PWM2 CCP5 - - - - - - - PD3 H1 AIN12 U1Tx CCP7 PWM3 CCP0 - - - - - - - PD4 B5 AIN7 CCP0 CCP3 - TXD3 - - - I2S0RXSD U1RI - - PD5 C6 AIN6 CCP2 CCP4 - TXD2 - - - I2S0RXMCLK U2Rx - - PD6 A3 AIN5 Fault0 - - TXD1 - - - I2S0TXSCK U2Tx - - I2S0TXWS U1DTR PD7 A2 AIN4 IDX0 C0o CCP1 TXD0 - - - - - PE0 B11 - PWM4 SSI1Clk CCP3 - - - - - USB0PFLT - - PE1 A12 - PWM5 SSI1Fss Fault0 CCP2 CCP6 - - - - - - PE2 A4 AIN9 CCP4 SSI1Rx PhB1 PhA0 CCP2 - - - - - - PE3 B4 AIN8 CCP1 SSI1Tx PhA1 PhB0 CCP7 - - - - - - PE4 B2 AIN3 CCP3 - - Fault0 U2Tx CCP2 RXD0 - I2S0TXWS - - PE5 B3 AIN2 CCP5 - - - - - - - I2S0TXSD - - PE6 A1 AIN1 PWM4 C1o - - - - - - U1CTS - - - PE7 B1 AIN0 PWM5 - - - - - - U1DCD - - PF0 M9 - CAN1Rx PhB0 PWM0 RXCK - - - I2S0TXSD U1DSR - - PF1 H12 - CAN1Tx IDX1 PWM1 RXER - - - I2S0TXMCLK U1RTS CCP3 - PF2 J11 - - PWM4 PHYINT PWM2 - - - - SSI1Clk - - PF3 J12 - - PWM5 MDC PWM3 - - - - SSI1Fss - - PF4 L9 - CCP0 C0o MDIO Fault0 - - - - SSI1Rx - - PF5 L8 - CCP2 C1o RXD3 - - - - - SSI1Tx - - PF6 M8 - CCP1 - RXD2 PhA0 - - - - I2S0TXMCLK U1RTS - PF7 K4 - CCP4 - RXD1 PhB0 - - - - Fault1 - - PG0 K1 - U2Rx PWM0 I2C1SCL PWM4 - - USB0EPEN - - - - PG1 K2 - U2Tx PWM1 I2C1SDA PWM5 - - - - - - - PG2 J1 - PWM0 - COL Fault0 - - - IDX1 I2S0RXSD - - July 22, 2011 1183 Texas Instruments-Production Data Signal Tables Table 23-10. GPIO Pins and Alternate Functions (continued) a Digital Function (GPIOPCTL PMCx Bit Field Encoding) IO Pin Analog Function 1 2 3 4 5 6 7 PG3 J2 - PWM1 - CRS Fault2 - - - PG4 K3 - CCP3 - RXD0 Fault1 - - - PG5 M7 - CCP5 - TXEN IDX0 Fault1 - - PG6 L7 - PhA1 - TXCK - - - - 8 9 Fault0 I2S0RXMCLK - - 10 11 - - U1RI - I2S0RXSCK U1DTR Fault1 I2S0RXWS - U1RI - PG7 C10 - PhB1 - TXER - - - - CCP5 - - - PH0 C9 - CCP6 PWM2 - - - - - - PWM4 - - PH1 C8 - CCP7 PWM3 - - - - - - PWM5 - - PH2 D11 - IDX1 C1o - Fault3 - - - - TXD3 - - PH3 D10 - PhB0 Fault0 - USB0EPEN - - - - TXD2 - - PH4 B10 - - - - USB0PFLT - - - - TXD1 - SSI1Clk PH5 F10 - - - - - - - - - TXD0 PH6 G3 - - - - - - - - - RXDV PH7 H3 - - - RXCK - - - - - - PWM5 SSI1Tx PJ0 F3 - - - RXER - - - - - - PWM0 I2C1SCL Fault2 SSI1Fss PWM4 SSI1Rx PJ1 B6 - - - - - - - - - USB0PFLT PWM1 I2C1SDA PJ2 K6 - - - - - - - - - CCP0 Fault0 - PJ3 M10 - - - - - - - - - U1CTS CCP6 - PJ4 K11 - - - - - - - - - U1DCD CCP4 - PJ5 K12 - - - - - - - - - U1DSR CCP2 - PJ6 L10 - - - - - - - - - U1RTS CCP1 - PJ7 L12 - - - - - - - - - U1DTR CCP0 - a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin. 1184 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-11. Possible Pin Assignments for Alternate Functions # of Possible Assignments one Alternate Function GPIO Function AIN0 PE7 AIN1 PE6 AIN10 PB4 AIN11 PB5 AIN12 PD3 AIN13 PD2 AIN14 PD1 AIN15 PD0 AIN2 PE5 AIN3 PE4 AIN4 PD7 AIN5 PD6 AIN6 PD5 AIN7 PD4 AIN8 PE3 AIN9 PE2 C0+ PB6 C0- PB4 C1+ PC5 C1- PB5 CAN1Rx PF0 CAN1Tx PF1 COL PG2 CRS PG3 I2C0SCL PB2 I2C0SDA PB3 MDC PF3 MDIO PF4 NMI PB7 PHYINT PF2 RXD2 PF6 RXD3 PF5 SSI0Clk PA2 SSI0Fss PA3 SSI0Rx PA4 SSI0Tx PA5 SWCLK PC0 SWDIO PC1 SWO PC3 TCK PC0 TDI PC2 July 22, 2011 1185 Texas Instruments-Production Data Signal Tables Table 23-11. Possible Pin Assignments for Alternate Functions (continued) # of Possible Assignments Alternate Function GPIO Function TDO PC3 TMS PC1 TXCK PG6 TXEN PG5 U0Rx PA0 U0Tx PA1 USB0ID PB0 USB0VBUS PB1 VREFA PB6 Fault3 PB3 PH2 I2S0RXSCK PD0 PG5 I2S0RXWS PD1 PG6 I2S0TXMCLK PF6 PF1 I2S0TXSD PE5 PF0 PhA1 PG6 PE3 two three RXD0 PE4 PG4 RXD1 PF7 PB7 TXER PD1 PG7 U1DSR PF0 PJ5 Fault2 PG3 PC5 PH5 I2S0RXMCLK PG3 PA3 PD5 I2S0RXSD PG2 PA2 PD4 I2S0TXSCK PA4 PB6 PD6 I2S0TXWS PE4 PA5 PD7 IDX1 PG2 PF1 PH2 PhB1 PD1 PG7 PE2 RXCK PH7 PA6 PF0 RXDV PD0 PA5 PH6 RXER PJ0 PA7 PF1 SSI1Clk PF2 PE0 PH4 SSI1Fss PF3 PH5 PE1 SSI1Rx PF4 PH6 PE2 SSI1Tx PH7 PF5 PE3 TXD0 PA4 PH5 PD7 TXD1 PA3 PH4 PD6 TXD2 PA2 PH3 PD5 TXD3 PC4 PH2 PD4 U1DTR PG5 PJ7 PD7 U1RI PG6 PG4 PD4 U1RTS PF6 PJ6 PF1 1186 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 23-11. Possible Pin Assignments for Alternate Functions (continued) # of Possible Assignments four five six seven Alternate Function GPIO Function CAN0Rx PD0 PA4 PA6 PB4 CAN0Tx PD1 PA5 PA7 PB5 I2C1SCL PJ0 PG0 PA0 PA6 I2C1SDA PG1 PA1 PA7 PJ1 PWM2 PD2 PF2 PB0 PH0 PWM3 PD3 PF3 PB1 PH1 PhA0 PD1 PC4 PF6 PE2 U1CTS PE6 PD0 PA6 PJ3 U1DCD PE7 PD1 PA7 PJ4 U2Rx PD0 PG0 PB4 PD5 U2Tx PE4 PD1 PG1 PD6 C0o PC5 PF4 PB6 PB5 PD7 C1o PE6 PC7 PC5 PF5 PH2 CCP7 PD1 PD3 PH1 PB6 PE3 Fault1 PG6 PG5 PG4 PF7 PB6 USB0EPEN PG0 PC5 PA6 PB2 PH3 CCP6 PD0 PD2 PJ3 PE1 PH0 PB5 IDX0 PD0 PG5 PB2 PB6 PB4 PD7 PWM0 PD0 PJ0 PG2 PG0 PA6 PF0 PWM1 PD1 PG3 PG1 PA7 PF1 PJ1 PhB0 PC7 PC6 PF7 PF0 PH3 PE3 U1Rx PD0 PD2 PC6 PA0 PB0 PB4 U1Tx PD1 PD3 PC7 PA1 PB1 PB5 CCP4 PC7 PC4 PA7 PF7 PJ4 PE2 PD5 CCP5 PE5 PD2 PC4 PG7 PG5 PB6 PB5 USB0PFLT PC7 PC6 PA7 PB3 PE0 PH4 PJ1 PWM4 PE6 PG0 PA2 PA6 PF2 PH6 PE0 PH0 PWM5 PE7 PH7 PG1 PA3 PA7 PF3 PE1 PH1 eight nine CCP1 PC5 PC4 PA6 PF6 PJ6 PB1 PB6 PE3 PD7 CCP3 PE4 PC6 PC5 PA7 PG4 PF1 PB2 PE0 PD4 Fault0 PE4 PG3 PG2 PJ2 PF4 PB3 PE1 PH3 PD6 CCP0 PD3 PC7 PC6 PJ2 PJ7 PF4 PB0 PB2 PB5 PD4 CCP2 PE4 PD1 PC4 PF5 PJ5 PB1 PE1 PB5 PE2 PD5 ten 23.3 Connections for Unused Signals Table 23-12 on page 1188 show how to handle signals for functions that are not used in a particular system implementation for devices that are in a 100-pin LQFP package. Two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx register. July 22, 2011 1187 Texas Instruments-Production Data Signal Tables Table 23-12. Connections for Unused Signals (100-Pin LQFP) Function Ethernet GPIO No Connects System Control USB Signal Name a Pin Number Acceptable Practice Preferred Practice MDIO 58 NC NC All unused GPIOs - NC GND NC - NC NC OSC0 48 NC GND OSC1 49 NC NC RST 64 Pull up as shown in Figure 5-1 on page 195 Connect through a capacitor to GND as close to pin as possible USB0DM 70 NC GND USB0DP 71 NC GND USB0RBIAS 73 Connect to GND through 10-kΩ resistor. Connect to GND through 10-kΩ resistor. a. Note that the Ethernet PHY is powered up by default. The PHY cannot be powered down unless a clock source is provided and the MDIO pin is pulled up through a 10-kΏ resistor. Table 23-13 on page 1188 show how to handle signals for functions that are not used in a particular system implementation for devices that are in a 108-ball BGA package. Two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx register. Table 23-13. Connections for Unused Signals (108-Ball BGA) Function Ethernet GPIO No Connects System Control USB Signal Name Pin Number Acceptable Practice Preferred Practice MDIO L9 NC NC All unused GPIOs - NC GND NC - NC NC a OSC0 L11 NC GND OSC1 M11 NC NC RST H11 Pull up as shown in Figure 5-1 on page 195 Connect through a capacitor to GND as close to pin as possible USB0RBIAS B12 Connect to GND through 10-kΩ resistor. Connect to GND through 10-kΩ resistor. USB0DM C11 NC GND USB0DP C12 NC GND a. Note that the Ethernet PHY is powered up by default. The PHY cannot be powered down unless a clock source is provided and the MDIO pin is pulled up through a 10-kΏ resistor. 1188 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 24 Operating Characteristics Table 24-1. Temperature Characteristics Characteristic Symbol Value Unit Industrial operating temperature range TA -40 to +85 °C Unpowered storage temperature range TS -65 to +150 °C Table 24-2. Thermal Characteristics Characteristic Symbol Value a Thermal resistance (junction to ambient) ΘJA Unit 35 (100LQFP) °C/W 33 (108BGA) b Junction temperature, -40 to +125 TJ TA + (P • ΘJA) °C a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator. b. Power dissipation is a function of temperature. a Table 24-3. ESD Absolute Maximum Ratings Parameter Name VESDHBM VESDCDM Min Nom Max Unit - - 2.0 kV - - 500 V ® a. All Stellaris parts are ESD tested following the JEDEC standard. July 22, 2011 1189 Texas Instruments-Production Data Electrical Characteristics 25 Electrical Characteristics 25.1 Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings. Table 25-1. Maximum Ratings Parameter Name VDD VDD supply voltage VDDA VDDA supply voltage VIN I VNON Value a Parameter Unit Min Max 0 4 V 0 4 V Input voltage -0.3 5.5 V Input voltage for a GPIO configured as an analog input -0.3 VDD + 0.3 V Input voltage for PB0 and PB1 when configured as GPIO -0.3 VDD + 0.3 V Maximum current per output pin - 25 mA Maximum input voltage on a non-power pin when the microcontroller is unpowered - 300 mV a. Voltages are measured with respect to GND. Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (see “Connections for Unused Signals” on page 1187). 25.2 Recommended Operating Conditions For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. Table 25-2. Recommended DC Operating Conditions Parameter Parameter Name Min Nom Max Unit VDD VDD supply voltage 3.0 3.3 3.6 V VDDA VDDA supply voltage 3.0 3.3 3.6 V VDDC supply voltage VDDC 1.235 1.3 1.365 V VIH High-level input voltage 2.1 - 5.0 V VIL - 1.2 V Low-level input voltage -0.3 a VOH High-level output voltage 2.4 - - V VOLa Low-level output voltage - - 0.4 V 1190 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 25-2. Recommended DC Operating Conditions (continued) Parameter Parameter Name Min Nom Max Unit 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 18 - - mA High-level source current, VOH=2.4 V IOH Low-level sink current, VOL=0.4 V IOL IOHC High-current sink, VOL=1.2 V a. VOL and VOH shift to 1.2 V when using high-current GPIOs. 25.3 Load Conditions Unless otherwise specified, the following conditions are true for all timing measurements. Figure 25-1. Load Conditions CL = 16 pF for EPI0S[31:0] signals 50 pF for other digital I/O signals pin GND 25.4 JTAG and Boundary Scan Table 25-3. JTAG Characteristics Parameter No. Parameter Parameter Name J1 FTCK TCK operational clock frequency J2 TTCK TCK operational clock period a Min Nom Max Unit 0 - 10 MHz 100 - - ns J3 TTCK_LOW TCK clock Low time - tTCK - ns J4 TTCK_HIGH TCK clock High time - tTCK - ns J5 TTCK_R TCK rise time 0 - 10 ns J6 TTCK_F TCK fall time 0 - 10 ns J7 TTMS_SU TMS setup time to TCK rise 20 - - ns J8 TTMS_HLD TMS hold time from TCK rise 20 - - ns J9 TTDI_SU TDI setup time to TCK rise 25 - - ns J10 TTDI_HLD TDI hold time from TCK rise 25 - - ns 23 35 ns 15 26 ns 14 25 ns 18 29 ns TCK fall to Data Valid from High-Z, 2-mA drive TCK fall to Data Valid from High-Z, 4-mA drive J11 TTDO_ZDV TCK fall to Data Valid from High-Z, 8-mA drive TCK fall to Data Valid from High-Z, 8-mA drive with slew rate control July 22, 2011 - 1191 Texas Instruments-Production Data Electrical Characteristics Table 25-3. JTAG Characteristics (continued) Parameter No. Parameter Parameter Name Min Nom Max Unit 21 35 ns 14 25 ns 13 24 ns TCK fall to Data Valid from Data Valid, 8-mA drive with slew rate control 18 28 ns TCK fall to High-Z from Data Valid, 2-mA drive 9 11 ns 7 9 ns 6 8 ns 7 9 ns TCK fall to Data Valid from Data Valid, 2-mA drive TCK fall to Data Valid from Data Valid, 4-mA drive TTDO_DV J12 TCK fall to Data Valid from Data Valid, 8-mA drive - TCK fall to High-Z from Data Valid, 4-mA drive J13 TTDO_DVZ TCK fall to High-Z from Data Valid, 8-mA drive - TCK fall to High-Z from Data Valid, 8-mA drive with slew rate control a. A ratio of at least 8:1 must be kept between the system clock and TCK. Figure 25-2. JTAG Test Clock Input Timing J2 J3 J4 TCK J6 J5 Figure 25-3. JTAG Test Access Port (TAP) Timing TCK J7 TMS TDI J8 TMS Input Valid J9 J9 J10 TDI Input Valid TDO J8 TMS Input Valid J11 25.5 J7 J10 TDI Input Valid J12 TDO Output Valid J13 TDO Output Valid Power and Brown-out Table 25-4. Power Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit P1 VTH Power-On Reset threshold - 2 - V P2 VBTH Brown-Out Reset threshold 2.85 2.9 2.95 V 1192 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 25-4. Power Characteristics (continued) Parameter No. Parameter Parameter Name Min Nom Max Unit P3 TPOR Power-On Reset timeout 6 - 18 ms P4 TBOR Brown-Out timeout - 500 - µs P5 TIRPOR Internal reset timeout after POR - - 2 ms P6 TIRBOR Internal reset timeout after BOR - - 2 ms P7 TVDDRISE Supply voltage (VDD) rise time (0V-3.0V) - - 10 ms P8 TVDD2_3 Supply voltage (VDD) rise time (2.0V-3.0V) - - 6 ms Figure 25-4. Power-On Reset Timing P1 VDD P3 /POR (Internal) P5 /Reset (Internal) Figure 25-5. Brown-Out Reset Timing P2 VDD P4 /BOR (Internal) P6 /Reset (Internal) July 22, 2011 1193 Texas Instruments-Production Data Electrical Characteristics Figure 25-6. Power-On Reset and Voltage Parameters VDD 3.0 P8 2.0 P7 25.6 Reset Table 25-5. Reset Characteristics Parameter No. Parameter Min Nom Max Unit R1 TIRHWR Internal reset timeout after hardware reset (RST pin) - - 2 ms R2 TIRSWR Internal reset timeout after software-initiated system reset - - 2 ms R3 TIRWDR Internal reset timeout after watchdog reset - - 2 ms R4 TIRMFR Internal reset timeout after MOSC failure reset - - 2 ms 2 - - µs R5 Parameter Name a Minimum RST pulse width TMIN a. This specification must be met in order to guarantee proper reset operation. Figure 25-7. External Reset Timing (RST) RST R1 R13 R5 /Reset (Internal) Figure 25-8. Software Reset Timing SW Reset R2 /Reset (Internal) 1194 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 25-9. Watchdog Reset Timing WDOG Reset (Internal) R3 /Reset (Internal) Figure 25-10. MOSC Failure Reset Timing MOSC Fail Reset (Internal) R4 /Reset (Internal) 25.7 On-Chip Low Drop-Out (LDO) Regulator Table 25-6. LDO Regulator Characteristics Parameter 25.8 Parameter Name Min Nom Max Unit CLDO External filter capacitor size for internal power supply 1.0 - 3.0 µF VLDO LDO output voltage 1.235 1.3 1.365 V Clocks The following sections provide specifications on the various clock sources and mode. 25.8.1 PLL Specifications The following tables provide specifications for using the PLL. Table 25-7. Phase Locked Loop (PLL) Characteristics Parameter Parameter Name Min Nom Max Unit FREF_XTAL Crystal reference 3.579545 - 16.384 MHz FREF_EXT External clock referencea 3.579545 - 16.384 MHz 400 - MHz - 1.38 a b FPLL PLL frequency - TREADY PLL lock time 0.562 c d ms a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration (RCC) register. b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. c. Using a 16.384-MHz crystal d. Using 3.5795-MHz crystal Table 25-8 on page 1196 shows the actual frequency of the PLL based on the crystal frequency used (defined by the XTAL field in the RCC register). July 22, 2011 1195 Texas Instruments-Production Data Electrical Characteristics Table 25-8. Actual PLL Frequency 25.8.2 XTAL Crystal Frequency (MHz) PLL Frequency (MHz) Error 0x04 0x05 3.5795 400.904 0.0023% 3.6864 398.1312 0.0047% 0x06 4.0 400 - 0x07 4.096 401.408 0.0035% 0x08 4.9152 398.1312 0.0047% 0x09 5.0 400 - 0x0A 5.12 399.36 0.0016% 0x0B 6.0 400 - 0x0C 6.144 399.36 0.0016% 0x0D 7.3728 398.1312 0.0047% 0x0E 8.0 400 - 0x0F 8.192 398.6773333 0.0033% 0x10 10.0 400 - 0x11 12.0 400 - 0x12 12.288 401.408 0.0035% 0x13 13.56 397.76 0.0056% 0x14 14.318 400.90904 0.0023% 0x15 16.0 400 - 0x16 16.384 404.1386667 0.010% PIOSC Specifications Table 25-9. PIOSC Clock Characteristics Parameter 25.8.3 Min Nom Max Unit FPIOSC25 Parameter Name Internal 16-MHz precision oscillator frequency variance, factory calibrated at 25 °C - ±0.25% ±1% - FPIOSCT Internal 16-MHz precision oscillator frequency variance, factory calibrated at 25 °C, across specified temperature range - - ±3% - FPIOSCUCAL Internal 16-MHz precision oscillator frequency variance, user calibrated at a chosen temperature - ±0.25% ±1% - Internal 30-kHz Oscillator Specifications Table 25-10. 30-kHz Clock Characteristics 25.8.4 Parameter Parameter Name FIOSC30KHZ Internal 30-KHz oscillator frequency Min Nom Max Unit 15 30 45 KHz Main Oscillator Specifications Table 25-11. Main Oscillator Clock Characteristics Parameter FMOSC TMOSC_PER Min Nom Max Unit Main oscillator frequency Parameter Name 1 - 16.384 MHz Main oscillator period 61 - 1000 ns 1196 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 25-11. Main Oscillator Clock Characteristics (continued) Parameter Parameter Name TMOSC_SETTLE a Nom Max Unit 17.5 - 20 ms TREF_XTAL_BYPASS Crystal reference using the main oscillator b (PLL in BYPASS mode) 1 - 16.384 MHz FREF_EXT_BYPASS External clock reference (PLL in BYPASS b mode) 0 - 50 MHz External clock reference duty cycle 45 - 55 % DCMOSC_EXT Main oscillator settling time Min a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance). b. If the ADC is used, the crystal reference must be 16 MHz ± .03% when the PLL is bypassed. a Table 25-12. Supported MOSC Crystal Frequencies Crystal Frequency (MHz) Not Using the PLL Crystal Frequency (MHz) Using the PLL 1.000 MHz reserved 1.8432 MHz reserved 2.000 MHz reserved 2.4576 MHz reserved 3.579545 MHz 3.6864 MHz 4 MHz (USB) 4.096 MHz 4.9152 MHz 5 MHz (USB) 5.12 MHz 6 MHz (reset value)(USB) 6.144 MHz 7.3728 MHz 8 MHz (USB) 8.192 MHz 10.0 MHz (USB) 12.0 MHz (USB) 12.288 MHz 13.56 MHz 14.31818 MHz 16.0 MHz (USB) 16.384 MHz a. Frequencies that may be used with the USB interface are indicated in the table. 25.8.5 System Clock Specification with ADC Operation Table 25-13. System Clock Characteristics with ADC Operation Parameter Fsysadc Parameter Name System clock frequency when the ADC module is operating (when PLL is bypassed) Min Nom Max Unit 15.9952 16 16.0048 MHz July 22, 2011 1197 Texas Instruments-Production Data Electrical Characteristics 25.9 Sleep Modes a Table 25-14. Sleep Modes AC Characteristics Parameter No Parameter D1 TWAKE_S D2 TWAKE_PLL_S D3 TENTER_DS Parameter Name Min Nom Max Unit Time to wake from interrupt in sleep or deep-sleep mode, not using the PLL - - 7 system clocks Time to wake from interrupt in sleep or deep-sleep mode when using the PLL - - TREADY ms Time to enter deep-sleep mode from sleep request - 0 35 b ms a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode. b. Nominal specification occurs 99.9995% of the time. 25.10 Flash Memory Table 25-15. Flash Memory Characteristics Parameter PECYC TRET Parameter Name Number of guaranteed program/erase cycles a before failure Min Nom Max Unit 15,000 - - cycles 10 - - years TPROG Word program time Data retention, -40˚C to +85˚C - - 1 ms TBPROG Buffer program time - - 1 ms TERASE Page erase time - - 12 ms TME Mass erase time - - 16 ms a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 25.11 GPIO Module Note: All GPIOs are 5-V tolerant, except PB0 and PB1. See “Signal Description” on page 391 for more information on GPIO configuration. Table 25-16. GPIO Module Characteristics Parameter Parameter Name Min Nom Max Unit RGPIOPU GPIO internal pull-up resistor 100 - 300 kΩ RGPIOPD GPIO internal pull-down resistor 200 - 500 kΩ ILKG a GPIO input leakage current b GPIO Rise Time, 2-mA drive b TGPIOR GPIO Rise Time, 4-mA drive - b GPIO Rise Time, 8-mA drive b GPIO Rise Time, 8-mA drive with slew rate control 1198 - 2 µA 14 20 ns 7 10 ns 4 5 ns 6 8 ns July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 25-16. GPIO Module Characteristics (continued) Parameter Parameter Name Nom Max Unit c Min 14 21 ns c 7 11 ns 4 6 ns 6 8 ns GPIO Fall Time, 2-mA drive TGPIOF GPIO Fall Time, 4-mA drive - c GPIO Fall Time, 8-mA drive c GPIO Fall Time, 8-mA drive with slew rate control a. The leakage current is measured with GND or VDD applied to the corresponding pin(s). The leakage of digital port pins is measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled. b. Time measured from 20% to 80% of VDD. c. Time measured from 80% to 20% of VDD. 25.12 Analog-to-Digital Converter (ADC) a Table 25-17. ADC Characteristics Parameter VADCIN N FADC Parameter Name Min Nom Max Unit Maximum single-ended, full-scale analog input voltage, using internal reference - - 3.0 V Maximum single-ended, full-scale analog input voltage, using external reference - - VREFA V Minimum single-ended, full-scale analog input voltage 0.0 - - V Maximum differential, full-scale analog input voltage, using internal reference - - 1.5 V Maximum differential, full-scale analog input voltage, using external reference - - VREFA/2 V Minimum differential, full-scale analog input voltage 0.0 - - Resolution 10 b ADC internal clock frequency 15.9952 16 MHz 1 µs c 1000 k samples/s Conversion time FADCCONV Conversion rate TADCSAMP Sample time 187.5 - Latency from trigger to start of conversion - ADC input leakage - RADC ADC equivalent resistance CADC ADC equivalent capacitance IL 16.0048 c TADCCONV TLT V bits - ns 2 - system clocks - 2.0 µA - - 10 kΩ 0.9 1.0 1.1 pF EL Integral nonlinearity (INL) error - - ±3 LSB ED Differential nonlinearity (DNL) error - - ±3 LSB EO Offset error - - ±20 LSB EG Full-scale gain error - - ±30 LSB ETS Temperature sensor accuracy - - ±5 °C d a. The ADC reference voltage is 3.0 V. This reference voltage is internally generated from the 3.3 VDDA supply by a band gap circuit. b. The ADC must be clocked from the PLL or directly from an external clock source to operate properly. c. The conversion time and rate scale from the specified number if the ADC internal clock frequency is any value other than 16 MHz. d. Note that this parameter does not include ADC error. July 22, 2011 1199 Texas Instruments-Production Data Electrical Characteristics Figure 25-11. ADC Input Equivalency Diagram Stellaris® Microcontroller VDD ESD Clamp RADC ESD Clamp VIN 10-bit converter IL CADC Sample and hold ADC converter a Table 25-18. ADC Module External Reference Characteristics Parameter VREFA IL Parameter Name b External voltage reference for ADC Min Nom Max 2.97 - 3.03 V - - 2.0 µA External voltage reference leakage current Unit a. Care must be taken to supply a reference voltage of acceptable quality. b. Ground is always used as the reference level for the minimum conversion value. Table 25-19. ADC Module Internal Reference Characteristics Parameter VREFI 25.13 Parameter Name Internal voltage reference for ADC Min Nom Max Unit - 3.0 - V Synchronous Serial Interface (SSI) Table 25-20. SSI Characteristics Parameter No. Parameter Parameter Name Min S1 TCLK_PER SSIClk cycle time S2 TCLK_HIGH SSIClk high time S3 TCLK_LOW SSIClk low time a Nom Max 100 - - ns - 0.5 - t clk_per - 0.5 - t clk_per b Unit S4 TCLKRF SSIClk rise/fall time - 4 6 ns S5 TDMD Data from master valid delay time 0 - 1 system clocks S6 TDMS Data from master setup time 1 - - system clocks S7 TDMH Data from master hold time 2 - - system clocks S8 TDSS Data from slave setup time 1 - - system clocks S9 TDSH Data from slave hold time 2 - - system clocks a. In master mode, the system clock must be at least twice as fast as the SSIClk; in slave mode, the system clock must be at least 12 times faster than the SSIClk. b. Note that the delays shown are using 8-mA drive strength. 1200 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 25-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement S1 S4 S2 SSIClk S3 SSIFss SSITx SSIRx MSB LSB 4 to 16 bits Figure 25-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer S2 S1 SSIClk S3 SSIFss SSITx MSB LSB 8-bit control SSIRx 0 MSB LSB 4 to 16 bits output data July 22, 2011 1201 Texas Instruments-Production Data Electrical Characteristics Figure 25-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 S1 S4 S2 SSIClk (SPO=1) S3 SSIClk (SPO=0) S6 SSITx (master) S7 MSB S5 SSIRx (slave) S8 LSB S9 MSB LSB SSIFss 25.14 Inter-Integrated Circuit (I2C) Interface Table 25-21. I2C Characteristics Parameter No. Parameter Parameter Name Min Nom Max Unit a TSCH Start condition hold time 36 - - system clocks a TLP Clock Low period 36 - - system clocks b TSRT I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.4 V) - - (see note b) ns a TDH Data hold time 2 - - system clocks c TSFT I2CSCL/I2CSDA fall time (VIH =2.4 V to V IL =0.5 V) - 9 10 ns a THT Clock High time 24 - - system clocks a TDS Data setup time 18 - - system clocks a TSCSR Start condition setup time (for repeated start condition only) 36 - - system clocks a TSCS Stop condition setup time 24 - - system clocks I1 I2 I3 I4 I5 I6 I7 I8 I9 a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above values are minimum values. b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. c. Specified at a nominal 50 pF load. 1202 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Figure 25-15. I2C Timing I2 I6 I5 I2CSCL I1 I4 I7 I8 I3 I9 I2CSDA 25.15 Inter-Integrated Circuit Sound (I2S) Interface Table 25-22. I2S Master Clock (Receive and Transmit) Parameter No. Parameter Parameter Name Min Nom Max Unit M1 TMCLK_PER Cycle time 20.3 - - ns M2 TMCLKRF Rise/fall time See “GPIO Module” on page 1198. ns M3 TMCLK_HIGH High time 10 - - ns M4 TMCLK_LOW Low time 10 - - ns M5 TMDC Duty cycle 48 - 52 % M6 TMJITTER - - 2.5 ns Jitter Table 25-23. I2S Slave Clock (Receive and Transmit) Parameter No. Parameter Parameter Name Min Nom Max Unit M7 TSCLK_PER M8 TSCLK_HIGH Cycle time 80 - - ns High time 40 - - ns M9 TSCLK_LOW Low time 40 - - ns M10 TSDC - 50 - % Duty cycle Table 25-24. I2S Master Mode Parameter No. Parameter Min Nom Max Unit SCK fall to WS valid - - 10 ns TMSD SCK fall to TXSD valid - - 10 ns M13 TMSDS RXSD setup time to SCK rise 10 - - ns M14 TMSDH RXSD hold time from SCK rise 10 - - ns M11 TMSWS M12 Parameter Name Figure 25-16. I2S Master Mode Transmit Timing SCK WS M11 TXSD Data M12 July 22, 2011 1203 Texas Instruments-Production Data Electrical Characteristics Figure 25-17. I2S Master Mode Receive Timing SCK M13 M14 Data RXSD Table 25-25. I2S Slave Mode Parameter No. Parameter Parameter Name Min Nom Max Unit M15 TSCLK_PER Cycle time 80 - - ns M16 TSCLK_HIGH High time 40 - - ns M17 TSCLK_LOW Low time M18 TSDC M19 40 - - ns Duty cycle - 50 - % TSSETUP WS setup time to SCK rise - - 25 ns M20 TSHOLD WS hold time from SCK rise - - 10 ns M21 TSSD SCK fall to TXSD valid - - 20 ns M22 TSLSD Left-justified mode, WS to TXSD - - 20 ns M23 TSSDS RXSD setup time to SCK rise 10 - - ns M24 TSSDH RXSD hold time from SCK rise 10 - - ns Figure 25-18. I2S Slave Mode Transmit Timing SCK M19 M20 WS M22 Data TXSD M21 Figure 25-19. I2S Slave Mode Receive Timing SCK M23 RXSD 25.16 M24 Data Ethernet Controller Table 25-26. Ethernet Station Management Parameter No. Parameter Parameter Name Min Nom Max Unit N1 TMDC MDC cycle time 400 - - ns N2 TMDCH MDC high time 160 - - ns 1204 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 25-26. Ethernet Station Management (continued) Parameter No. Parameter Parameter Name Min Nom Max Unit N3 TMDCL MDC low time 160 - - ns N4 TMDIO_VAL MDIO write data valid time 100 - - ns N5 TMDIO_INV MDIO write data invalid time - - 100 ns N6 TMDIO_SU MDIO read data set up time 10 - - ns N7 TMDIO_H MDIO read data hold time 10 - - ns a Table 25-27. 100BASE-TX Transmitter Characteristics Parameter Name Min Nom Max Unit Peak output amplitude 950 - 1050 mVpk Output amplitude symmetry 98 - 102 % Output overshoot - - 5 % Rise/Fall time 3 - 5 ns Rise/Fall time imbalance - - 500 ps Duty cycle distortion - - ±250 ps Jitter - - 1.4 ns a. Measured at the line side of the transformer. a Table 25-28. 100BASE-TX Transmitter Characteristics (informative) Parameter Name Min Nom Max Unit Return loss 16 - - dB Open-circuit inductance 350 - - µH a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 25-29. 100BASE-TX Receiver Characteristics Parameter Name Min Nom Max Unit Signal detect assertion threshold 600 700 - mVppd Signal detect de-assertion threshold 350 425 - mVppd Differential input resistance - 3.6 - kΩ Jitter tolerance (pk-pk) 4 - - ns -80 - +80 % Signal detect assertion time Baseline wander tracking - - 1000 µs Signal detect de-assertion time - - 4 µs a Table 25-30. 10BASE-T Transmitter Characteristics Parameter Name Min Nom Max Peak differential output signal Harmonic content 2.2 - 2.7 V 27 - - dB Link pulse width - 100 - ns Start-of-idle pulse width, Last bit 0 - 300 - ns July 22, 2011 Unit 1205 Texas Instruments-Production Data Electrical Characteristics Table 25-30. 10BASE-T Transmitter Characteristics (continued) Parameter Name Min Nom Max Unit - 350 - ns Start-of-idle pulse width, Last bit 1 a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. a Table 25-31. 10BASE-T Transmitter Characteristics (informative) Parameter Name Output return loss Min Nom Max Unit 15 - - dB 29-17log(f/10) - - dB Peak common-mode output voltage - - 50 mV Common-mode rejection - - 100 mV Common-mode rejection jitter - - 1 ns Output impedance balance a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 25-32. 10BASE-T Receiver Characteristics Parameter Name Min Nom Max Unit Jitter tolerance (pk-pk) 30 26 - ns Input squelched threshold 340 440 540 mVppd Differential input resistance - 3.6 - kΩ 25 - - V Common-mode rejection a Table 25-33. Isolation Transformers Name Value Condition 1 CT : 1 CT +/- 5% Open-circuit inductance 350 uH (min) @ 10 mV, 10 kHz Leakage inductance 0.40 uH (max) @ 1 MHz (min) Turns ratio Inter-winding capacitance 25 pF (max) DC resistance 0.9 Ohm (max) Insertion loss 0.4 dB (typ) 0-65 MHz 1500 Vrms HIPOT a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics. Note: 25.17 The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. Universal Serial Bus (USB) Controller ® The Stellaris USB controller electrical specifications are compliant with the Universal Serial Bus Specification Rev. 2.0 (full-speed and low-speed support) and the On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. Some components of the USB system are integrated within the LM3S9L71 microcontroller and specific to the Stellaris microcontroller design. An external component resistor is needed as specified in Table 25-34. 1206 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 25-34. USB Controller Characteristics Parameter Parameter Name RUBIAS 25.18 Value of the pull-down resistor on the USB0RBIAS pin Value Unit 9.1K ± 1 % Ω Analog Comparator Table 25-35. Analog Comparator Characteristics Parameter Parameter Name Min Nom Max Unit VOS Input offset voltage - ±10 ±25 mV VCM Input common mode voltage range 0 - VDD-1.5 V CMRR Common mode rejection ratio 50 - - dB TRT Response time - - 1 µs TMC Comparator mode change to Output Valid - - 10 µs Table 25-36. Analog Comparator Voltage Reference Characteristics Parameter 25.19 Min Nom Max Unit RHR Resolution high range Parameter Name - VDD/31 - LSB RLR Resolution low range - VDD/23 - LSB AHR Absolute accuracy high range - - ±1/2 LSB ALR Absolute accuracy low range - - ±1/4 LSB USB Module The Stellaris USB controller electrical specifications are compliant with the Universal Serial Bus Specification Rev. 2.0 (full-speed and low-speed support) and the On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. Some components of the USB system are integrated within the LM3S9L71 microcontroller and specific to the Stellaris microcontroller design. An external component resistor is needed as specified in Table 25-37. Table 25-37. USB Controller DC Characteristics Parameter RUBIAS 25.20 Parameter Name Value of the pull-down resistor on the USB0RBIAS pin Value Unit 9.1K ± 1 % Ω Current Consumption This section provides information on typical and maximum power consumption under various conditions. Unless otherwise indicated, current consumption numbers include use of the on-chip LDO regulator and therefore include IDDC. 25.20.1 Nominal Power Consumption The following table provides nominal figures for current consumption. July 22, 2011 1207 Texas Instruments-Production Data Electrical Characteristics Table 25-38. Nominal Power Consumption Parameter Parameter Name IDD_RUN Run mode 1 (Flash loop) Conditions Nom Unit VDD = 3.3 V a 101 mA Code= while(1){} executed out of Flash 159 b Peripherals = All ON System Clock = 80 MHz (with PLL) Temp = 25°C IDD_DEEPSLEEP Deep-sleep mode Peripherals = All OFF 550 µA System Clock = IOSC30KHZ/64 Temp = 25°C a. Ethernet MAC and PHY powered down by software. b. Auto-negotiate enabled. If an Ethernet cable is attached to the connector, the consumption increases by 7-10 mA. 25.20.2 Maximum Current Consumption The current measurements specified in the table that follows are maximum values under the following conditions: ■ VDD = 3.6 V ■ VDDC = 1.3 V ■ VDDA = 3.6 V ■ Temperature = 25°C ■ Clock source (MOSC) =3.579545-MHz crystal oscillator Table 25-39. Detailed Current Specifications Parameter IDD_RUN Parameter Name Conditions Max Unit Run mode 1 (Flash loop) VDD = 3.6 V a mA Code= while(1){} executed out of Flash 191 b 125 Peripherals = All ON System Clock = 80 MHz (with PLL) Temperature = 25°C IDD_SLEEP Sleep mode VDD = 3.6 V 42 mA 1.7 mA Peripherals = All Clock Gated System Clock = 80 MHz (with PLL) Temperature = 25°C IDD_DEEPSLEEP Deep-Sleep mode VDD = 3.6 V Peripherals = All Clock Gated System Clock = IOSC30/64 Temperature = 25°C a. Auto-negotiate enabled. If an Ethernet cable is attached to the connector, the consumption increases by 7-10 mA. b. Ethernet MAC and PHY powered down by software. 1208 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller Table 25-40. External VDDC Source Current Specifications Parameter IDDC_RUN Parameter Name Conditions Run mode 1 (Flash loop), VDDC VDD = 3.6 V current VDDC = 1.3 V Max Unit 89 mA Code= while(1){} executed out of Flash Peripherals = All ON System Clock = 80 MHz (with PLL) Temperature = 25°C July 22, 2011 1209 Texas Instruments-Production Data Register Quick Reference A Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The Cortex-M3 Processor R0, type R/W, , reset - (see page 78) DATA DATA R1, type R/W, , reset - (see page 78) DATA DATA R2, type R/W, , reset - (see page 78) DATA DATA R3, type R/W, , reset - (see page 78) DATA DATA R4, type R/W, , reset - (see page 78) DATA DATA R5, type R/W, , reset - (see page 78) DATA DATA R6, type R/W, , reset - (see page 78) DATA DATA R7, type R/W, , reset - (see page 78) DATA DATA R8, type R/W, , reset - (see page 78) DATA DATA R9, type R/W, , reset - (see page 78) DATA DATA R10, type R/W, , reset - (see page 78) DATA DATA R11, type R/W, , reset - (see page 78) DATA DATA R12, type R/W, , reset - (see page 78) DATA DATA SP, type R/W, , reset - (see page 79) SP SP LR, type R/W, , reset 0xFFFF.FFFF (see page 80) LINK LINK PC, type R/W, , reset - (see page 81) PC PC 1210 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR, type R/W, , reset 0x0100.0000 (see page 82) N Z C V Q ICI / IT THUMB ICI / IT ISRNUM PRIMASK, type R/W, , reset 0x0000.0000 (see page 86) PRIMASK FAULTMASK, type R/W, , reset 0x0000.0000 (see page 87) FAULTMASK BASEPRI, type R/W, , reset 0x0000.0000 (see page 88) BASEPRI CONTROL, type R/W, , reset 0x0000.0000 (see page 89) ASP TMPL INTEN ENABLE Cortex-M3 Peripherals System Timer (SysTick) Registers Base 0xE000.E000 STCTRL, type R/W, offset 0x010, reset 0x0000.0004 COUNT CLK_SRC STRELOAD, type R/W, offset 0x014, reset 0x0000.0000 RELOAD RELOAD STCURRENT, type R/WC, offset 0x018, reset 0x0000.0000 CURRENT CURRENT Cortex-M3 Peripherals Nested Vectored Interrupt Controller (NVIC) Registers Base 0xE000.E000 EN0, type R/W, offset 0x100, reset 0x0000.0000 INT INT EN1, type R/W, offset 0x104, reset 0x0000.0000 INT INT DIS0, type R/W, offset 0x180, reset 0x0000.0000 INT INT DIS1, type R/W, offset 0x184, reset 0x0000.0000 INT INT PEND0, type R/W, offset 0x200, reset 0x0000.0000 INT INT PEND1, type R/W, offset 0x204, reset 0x0000.0000 INT INT UNPEND0, type R/W, offset 0x280, reset 0x0000.0000 INT INT July 22, 2011 1211 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNPEND1, type R/W, offset 0x284, reset 0x0000.0000 INT INT ACTIVE0, type RO, offset 0x300, reset 0x0000.0000 INT INT ACTIVE1, type RO, offset 0x304, reset 0x0000.0000 INT INT PRI0, type R/W, offset 0x400, reset 0x0000.0000 INTD INTC INTB INTA PRI1, type R/W, offset 0x404, reset 0x0000.0000 INTD INTC INTB INTA PRI2, type R/W, offset 0x408, reset 0x0000.0000 INTD INTC INTB INTA PRI3, type R/W, offset 0x40C, reset 0x0000.0000 INTD INTC INTB INTA PRI4, type R/W, offset 0x410, reset 0x0000.0000 INTD INTC INTB INTA PRI5, type R/W, offset 0x414, reset 0x0000.0000 INTD INTC INTB INTA PRI6, type R/W, offset 0x418, reset 0x0000.0000 INTD INTC INTB INTA PRI7, type R/W, offset 0x41C, reset 0x0000.0000 INTD INTC INTB INTA PRI8, type R/W, offset 0x420, reset 0x0000.0000 INTD INTC INTB INTA PRI9, type R/W, offset 0x424, reset 0x0000.0000 INTD INTC INTB INTA PRI10, type R/W, offset 0x428, reset 0x0000.0000 INTD INTC INTB INTA PRI11, type R/W, offset 0x42C, reset 0x0000.0000 INTD INTC INTB INTA PRI12, type R/W, offset 0x430, reset 0x0000.0000 INTD INTC INTB INTA PRI13, type R/W, offset 0x434, reset 0x0000.0000 INTD INTC INTB INTA 1212 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWTRIG, type WO, offset 0xF00, reset 0x0000.0000 INTID Cortex-M3 Peripherals System Control Block (SCB) Registers Base 0xE000.E000 ACTLR, type R/W, offset 0x008, reset 0x0000.0000 DISFOLD DISWBUF DISMCYC CPUID, type RO, offset 0xD00, reset 0x412F.C230 IMP VAR CON PARTNO REV INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000 NMISET PENDSV UNPENDSV PENDSTSET PENDSTCLR VECPEND ISRPRE ISRPEND VECPEND RETBASE VECACT VTABLE, type R/W, offset 0xD08, reset 0x0000.0000 BASE OFFSET OFFSET APINT, type R/W, offset 0xD0C, reset 0xFA05.0000 VECTKEY PRIGROUP ENDIANESS SYSRESREQ VECTCLRACT VECTRESET SYSCTRL, type R/W, offset 0xD10, reset 0x0000.0000 SEVONPEND SLEEPDEEP SLEEPEXIT CFGCTRL, type R/W, offset 0xD14, reset 0x0000.0200 DIV0 STKALIGN BFHFNMIGN UNALIGNED MAINPEND BASETHR SYSPRI1, type R/W, offset 0xD18, reset 0x0000.0000 USAGE BUS MEM SYSPRI2, type R/W, offset 0xD1C, reset 0x0000.0000 SVC SYSPRI3, type R/W, offset 0xD20, reset 0x0000.0000 TICK PENDSV DEBUG SYSHNDCTRL, type R/W, offset 0xD24, reset 0x0000.0000 USAGE SVC BUSP MEMP USAGEP TICK PNDSV MON SVCA USGA BUS MEM BUSA MEMA INVSTAT UNDEF DERR IERR FAULTSTAT, type R/W1C, offset 0xD28, reset 0x0000.0000 BFARV BSTKE BUSTKE IMPRE DIV0 UNALIGN PRECISE IBUS NOCP MMARV MSTKE MUSTKE INVPC HFAULTSTAT, type R/W1C, offset 0xD2C, reset 0x0000.0000 DBG FORCED VECT MMADDR, type R/W, offset 0xD34, reset ADDR ADDR FAULTADDR, type R/W, offset 0xD38, reset ADDR ADDR July 22, 2011 1213 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cortex-M3 Peripherals Memory Protection Unit (MPU) Registers Base 0xE000.E000 MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800 IREGION DREGION SEPARATE MPUCTRL, type R/W, offset 0xD94, reset 0x0000.0000 PRIVDEFEN HFNMIENA ENABLE MPUNUMBER, type R/W, offset 0xD98, reset 0x0000.0000 NUMBER MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000 ADDR ADDR VALID REGION VALID REGION VALID REGION VALID REGION MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000 ADDR ADDR MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000 ADDR ADDR MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.0000 ADDR ADDR MPUATTR, type R/W, offset 0xDA0, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR1, type R/W, offset 0xDA8, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR2, type R/W, offset 0xDB0, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE MPUATTR3, type R/W, offset 0xDB8, reset 0x0000.0000 XN AP TEX SRD S C SIZE B ENABLE System Control Base 0x400F.E000 DID0, type RO, offset 0x000, reset - (see page 210) VER CLASS MAJOR MINOR PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD (see page 212) BORIOR RIS, type RO, offset 0x050, reset 0x0000.0000 (see page 213) MOSCPUPRIS USBPLLLRIS PLLLRIS BORRIS MOSCPUPIM USBPLLLIM PLLLIM BORIM IMC, type R/W, offset 0x054, reset 0x0000.0000 (see page 215) 1214 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MISC, type R/W1C, offset 0x058, reset 0x0000.0000 (see page 217) MOSCPUPMIS USBPLLLMIS PLLLMIS BORMIS RESC, type R/W, offset 0x05C, reset - (see page 219) MOSCFAIL WDT1 SW WDT0 BOR POR EXT RCC, type R/W, offset 0x060, reset 0x078E.3AD1 (see page 221) ACG PWRDN SYSDIV BYPASS USESYSDIV PWMDIV USEPWMDIV XTAL OSCSRC IOSCDIS MOSCDIS PLLCFG, type RO, offset 0x064, reset - (see page 226) F R GPIOHBCTL, type R/W, offset 0x06C, reset 0x0000.0000 (see page 227) PORTJ PORTH PORTG PORTF PORTE PORTD PORTC PORTB PORTA RCC2, type R/W, offset 0x070, reset 0x07C0.6810 (see page 229) USERCC2 DIV400 USBPWRDN SYSDIV2 PWRDN2 SYSDIV2LSB BYPASS2 OSCSRC2 MOSCCTL, type R/W, offset 0x07C, reset 0x0000.0000 (see page 232) CVAL DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 (see page 233) DSDIVORIDE DSOSCSRC PIOSCCAL, type R/W, offset 0x150, reset 0x0000.0000 (see page 235) UTEN UPDATE UT I2SMCLKCFG, type R/W, offset 0x170, reset 0x0000.0000 (see page 236) RXEN RXI RXF TXEN TXI TXF DID1, type RO, offset 0x004, reset - (see page 238) VER FAM PARTNO PINCOUNT TEMP PKG ROHS QUAL DC0, type RO, offset 0x008, reset 0x00BF.003F (see page 240) SRAMSZ FLASHSZ DC1, type RO, offset 0x010, reset - (see page 241) WDT1 MINSYSDIV CAN1 MAXADC1SPD CAN0 MAXADC0SPD PWM MPU TEMPSNS PLL SSI1 SSI0 ADC0AIN5 ADC0AIN4 PWM5 PWM4 GPIOF GPIOE ADC1 ADC0 WDT0 SWO SWD JTAG TIMER3 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 PWM3 PWM2 PWM1 PWM0 GPIOD GPIOC GPIOB GPIOA PWM3 PWM2 PWM1 PWM0 DC2, type RO, offset 0x014, reset 0x130F.5337 (see page 244) I2C1 I2S0 COMP1 COMP0 I2C0 QEI1 QEI0 CCP1 CCP0 DC3, type RO, offset 0x018, reset 0xBFFF.8FFF (see page 246) 32KHZ CCP5 CCP4 CCP3 C1O PWMFAULT CCP2 C1PLUS C1MINUS C0O ADC0AIN7 ADC0AIN6 C0PLUS C0MINUS DC4, type RO, offset 0x01C, reset 0x1104.F1FF (see page 249) CCP7 CCP6 UDMA EMAC0 E1588 ROM GPIOJ PICAL GPIOH GPIOG DC5, type RO, offset 0x020, reset 0x0F30.003F (see page 251) PWMFAULT3 PWMFAULT2 PWMFAULT1 PWMFAULT0 PWMEFLT PWMESYNC PWM5 July 22, 2011 PWM4 1215 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DC6, type RO, offset 0x024, reset 0x0000.0013 (see page 253) USB0PHY USB0 DC7, type RO, offset 0x028, reset 0xFFFF.FFFF (see page 254) DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16 DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 DMACH3 DMACH2 DMACH1 DMACH0 DC8, type RO, offset 0x02C, reset 0xFFFF.FFFF (see page 258) ADC1AIN15 ADC1AIN14 ADC1AIN13 ADC1AIN12 ADC1AIN11 ADC1AIN10 ADC1AIN9 ADC1AIN8 ADC1AIN7 ADC1AIN6 ADC1AIN5 ADC1AIN4 ADC1AIN3 ADC1AIN2 ADC1AIN1 ADC1AIN0 ADC0AIN15 ADC0AIN14 ADC0AIN13 ADC0AIN12 ADC0AIN11 ADC0AIN10 ADC0AIN9 ADC0AIN8 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0 DC9, type RO, offset 0x190, reset 0x00FF.00FF (see page 261) ADC1DC7 ADC1DC6 ADC1DC5 ADC1DC4 ADC1DC3 ADC1DC2 ADC1DC1 ADC1DC0 ADC0DC7 ADC0DC6 ADC0DC5 ADC0DC4 ADC0DC3 ADC0DC2 ADC0DC1 ADC0DC0 NVMSTAT, type RO, offset 0x1A0, reset 0x0000.0001 (see page 263) FWB RCGC0, type R/W, offset 0x100, reset 0x00000040 (see page 264) WDT1 CAN1 MAXADC1SPD CAN0 PWM MAXADC0SPD ADC1 ADC0 ADC1 ADC0 ADC1 ADC0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 WDT0 SCGC0, type R/W, offset 0x110, reset 0x00000040 (see page 267) WDT1 CAN1 MAXADC1SPD CAN0 PWM MAXADC0SPD WDT0 DCGC0, type R/W, offset 0x120, reset 0x00000040 (see page 270) WDT1 CAN1 CAN0 PWM WDT0 RCGC1, type R/W, offset 0x104, reset 0x00000000 (see page 272) I2C1 I2S0 COMP1 COMP0 I2C0 QEI1 QEI0 I2S0 COMP1 COMP0 I2C0 QEI1 QEI0 I2S0 COMP1 COMP0 I2C0 QEI1 QEI0 TIMER3 SSI1 SSI0 SSI1 SSI0 SSI1 SSI0 SCGC1, type R/W, offset 0x114, reset 0x00000000 (see page 275) I2C1 TIMER3 DCGC1, type R/W, offset 0x124, reset 0x00000000 (see page 278) I2C1 TIMER3 RCGC2, type R/W, offset 0x108, reset 0x00000000 (see page 281) EMAC0 USB0 UDMA GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOJ GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA ADC1 ADC0 TIMER2 TIMER1 TIMER0 UART2 UART1 UART0 GPIOC GPIOB GPIOA SCGC2, type R/W, offset 0x118, reset 0x00000000 (see page 284) EMAC0 USB0 UDMA DCGC2, type R/W, offset 0x128, reset 0x00000000 (see page 287) EMAC0 USB0 UDMA SRCR0, type R/W, offset 0x040, reset 0x00000000 (see page 290) WDT1 CAN1 CAN0 PWM WDT0 SRCR1, type R/W, offset 0x044, reset 0x00000000 (see page 292) I2C1 I2S0 COMP1 COMP0 I2C0 QEI1 QEI0 TIMER3 SSI1 SSI0 GPIOF GPIOE SRCR2, type R/W, offset 0x048, reset 0x00000000 (see page 295) EMAC0 UDMA USB0 GPIOJ GPIOH GPIOG 1216 GPIOD July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Internal Memory Flash Memory Registers (Flash Control Offset) Base 0x400F.D000 FMA, type R/W, offset 0x000, reset 0x0000.0000 OFFSET OFFSET FMD, type R/W, offset 0x004, reset 0x0000.0000 DATA DATA FMC, type R/W, offset 0x008, reset 0x0000.0000 WRKEY COMT MERASE ERASE WRITE PRIS ARIS PMASK AMASK PMISC AMISC FCRIS, type RO, offset 0x00C, reset 0x0000.0000 FCIM, type R/W, offset 0x010, reset 0x0000.0000 FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000 FMC2, type R/W, offset 0x020, reset 0x0000.0000 WRKEY WRBUF FWBVAL, type R/W, offset 0x030, reset 0x0000.0000 FWB[n] FWB[n] FCTL, type R/W, offset 0x0F8, reset 0x0000.0000 USDACK USDREQ FWBn, type R/W, offset 0x100 - 0x17C, reset 0x0000.0000 DATA DATA Internal Memory Memory Registers (System Control Offset) Base 0x400F.E000 RMCTL, type R/W1C, offset 0x0F0, reset - BA FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE BOOTCFG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE NW PORT PIN POL EN DBG1 DBG0 USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF NW DATA DATA July 22, 2011 1217 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF NW DATA DATA USER_REG2, type R/W, offset 0x1E8, reset 0xFFFF.FFFF NW DATA DATA USER_REG3, type R/W, offset 0x1EC, reset 0xFFFF.FFFF NW DATA DATA FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE2, type R/W, offset 0x208, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPRE3, type R/W, offset 0x20C, reset 0x0000.0000 READ_ENABLE READ_ENABLE FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE2, type R/W, offset 0x408, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE FMPPE3, type R/W, offset 0x40C, reset 0x0000.0000 PROG_ENABLE PROG_ENABLE Micro Direct Memory Access (μDMA) μDMA Channel Control Structure (Offset from Channel Control Table Base) Base n/a DMASRCENDP, type R/W, offset 0x000, reset ADDR ADDR DMADSTENDP, type R/W, offset 0x004, reset ADDR ADDR DMACHCTL, type R/W, offset 0x008, reset DSTINC DSTSIZE SRCINC SRCSIZE ARBSIZE ARBSIZE XFERSIZE NXTUSEBURST XFERMODE Micro Direct Memory Access (μDMA) μDMA Registers (Offset from μDMA Base Address) Base 0x400F.F000 DMASTAT, type RO, offset 0x000, reset 0x001F.0000 DMACHANS STATE MASTEN DMACFG, type WO, offset 0x004, reset - MASTEN DMACTLBASE, type R/W, offset 0x008, reset 0x0000.0000 ADDR ADDR 1218 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAALTBASE, type RO, offset 0x00C, reset 0x0000.0200 ADDR ADDR DMAWAITSTAT, type RO, offset 0x010, reset 0xFFFF.FFC0 WAITREQ[n] WAITREQ[n] DMASWREQ, type WO, offset 0x014, reset SWREQ[n] SWREQ[n] DMAUSEBURSTSET, type R/W, offset 0x018, reset 0x0000.0000 SET[n] SET[n] DMAUSEBURSTCLR, type WO, offset 0x01C, reset CLR[n] CLR[n] DMAREQMASKSET, type R/W, offset 0x020, reset 0x0000.0000 SET[n] SET[n] DMAREQMASKCLR, type WO, offset 0x024, reset CLR[n] CLR[n] DMAENASET, type R/W, offset 0x028, reset 0x0000.0000 SET[n] SET[n] DMAENACLR, type WO, offset 0x02C, reset CLR[n] CLR[n] DMAALTSET, type R/W, offset 0x030, reset 0x0000.0000 SET[n] SET[n] DMAALTCLR, type WO, offset 0x034, reset CLR[n] CLR[n] DMAPRIOSET, type R/W, offset 0x038, reset 0x0000.0000 SET[n] SET[n] DMAPRIOCLR, type WO, offset 0x03C, reset CLR[n] CLR[n] DMAERRCLR, type R/W, offset 0x04C, reset 0x0000.0000 ERRCLR DMACHASGN, type R/W, offset 0x500, reset 0x0000.0000 CHASGN[n] CHASGN[n] DMAPeriphID0, type RO, offset 0xFE0, reset 0x0000.0030 PID0 DMAPeriphID1, type RO, offset 0xFE4, reset 0x0000.00B2 PID1 July 22, 2011 1219 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAPeriphID2, type RO, offset 0xFE8, reset 0x0000.000B PID2 DMAPeriphID3, type RO, offset 0xFEC, reset 0x0000.0000 PID3 DMAPeriphID4, type RO, offset 0xFD0, reset 0x0000.0004 PID4 DMAPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 DMAPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 DMAPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 DMAPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 General-Purpose Input/Outputs (GPIOs) GPIO Port A (APB) base: 0x4000.4000 GPIO Port A (AHB) base: 0x4005.8000 GPIO Port B (APB) base: 0x4000.5000 GPIO Port B (AHB) base: 0x4005.9000 GPIO Port C (APB) base: 0x4000.6000 GPIO Port C (AHB) base: 0x4005.A000 GPIO Port D (APB) base: 0x4000.7000 GPIO Port D (AHB) base: 0x4005.B000 GPIO Port E (APB) base: 0x4002.4000 GPIO Port E (AHB) base: 0x4005.C000 GPIO Port F (APB) base: 0x4002.5000 GPIO Port F (AHB) base: 0x4005.D000 GPIO Port G (APB) base: 0x4002.6000 GPIO Port G (AHB) base: 0x4005.E000 GPIO Port H (APB) base: 0x4002.7000 GPIO Port H (AHB) base: 0x4005.F000 GPIO Port J (APB) base: 0x4003.D000 GPIO Port J (AHB) base: 0x4006.0000 GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 (see page 406) DATA GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 (see page 407) DIR GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 (see page 408) IS GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 (see page 409) IBE GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 (see page 410) IEV GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 (see page 411) IME 1220 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIORIS, type RO, offset 0x414, reset 0x0000.0000 (see page 412) RIS GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 (see page 413) MIS GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 (see page 415) IC GPIOAFSEL, type R/W, offset 0x420, reset - (see page 416) AFSEL GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF (see page 418) DRV2 GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 (see page 419) DRV4 GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 (see page 420) DRV8 GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 (see page 421) ODE GPIOPUR, type R/W, offset 0x510, reset - (see page 422) PUE GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 424) PDE GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 426) SRL GPIODEN, type R/W, offset 0x51C, reset - (see page 427) DEN GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 (see page 429) LOCK LOCK GPIOCR, type -, offset 0x524, reset - (see page 430) CR GPIOAMSEL, type R/W, offset 0x528, reset 0x0000.0000 (see page 432) GPIOAMSEL GPIOPCTL, type R/W, offset 0x52C, reset - (see page 434) PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 436) PID4 July 22, 2011 1221 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 437) PID5 GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 438) PID6 GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 439) PID7 GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 (see page 440) PID0 GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 441) PID1 GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 442) PID2 GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 443) PID3 GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 444) CID0 GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 445) CID1 GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 446) CID2 GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 447) CID3 General-Purpose Timers Timer 0 base: 0x4003.0000 Timer 1 base: 0x4003.1000 Timer 2 base: 0x4003.2000 Timer 3 base: 0x4003.3000 GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 (see page 465) GPTMCFG GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 (see page 466) TASNAPS TAWOT TAMIE TACDIR TAAMS TACMR TAMR TBSNAPS TBWOT TBMIE TBCDIR TBAMS TBCMR TBMR TAPWML TAOTE RTCEN GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 (see page 468) GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 (see page 470) TBPWML TBOTE TBEVENT TBSTALL TBEN TAEVENT TASTALL TAEN CAMIM TATOIM GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 (see page 473) TBMIM CBEIM CBMIM TBTOIM 1222 TAMIM RTCIM CAEIM July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAMRIS RTCRIS CAERIS CAMRIS TATORIS TAMMIS RTCMIS CAEMIS CAMMIS TATOMIS GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 475) TBMRIS CBERIS CBMRIS TBTORIS GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 (see page 478) TBMMIS CBEMIS CBMMIS TBTOMIS GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 (see page 481) TBMCINT CBECINT CBMCINT TBTOCINT TAMCINT RTCCINT CAECINT CAMCINT TATOCINT GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF (see page 483) TAILR TAILR GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 484) TBILR TBILR GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF (see page 485) TAMR TAMR GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF (see page 486) TBMR TBMR GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 (see page 487) TAPSR GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 (see page 488) TBPSR GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 (see page 489) TAPSMR GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 (see page 490) TBPSMR GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF (see page 491) TAR TAR GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (see page 492) TBR TBR GPTMTAV, type RW, offset 0x050, reset 0xFFFF.FFFF (see page 493) TAV TAV GPTMTBV, type RW, offset 0x054, reset 0x0000.FFFF (see page 494) TBV TBV Watchdog Timers WDT0 base: 0x4000.0000 WDT1 base: 0x4000.1000 WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF (see page 499) WDTLOAD WDTLOAD July 22, 2011 1223 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESEN INTEN WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF (see page 500) WDTVALUE WDTVALUE WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 (WDT0) and 0x8000.0000 (WDT1) (see page 501) WRC WDTICR, type WO, offset 0x00C, reset - (see page 503) WDTINTCLR WDTINTCLR WDTRIS, type RO, offset 0x010, reset 0x0000.0000 (see page 504) WDTRIS WDTMIS, type RO, offset 0x014, reset 0x0000.0000 (see page 505) WDTMIS WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 (see page 506) STALL WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 (see page 507) WDTLOCK WDTLOCK WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 508) PID4 WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 509) PID5 WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 510) PID6 WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 511) PID7 WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 (see page 512) PID0 WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 (see page 513) PID1 WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 514) PID2 WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 515) PID3 WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 516) CID0 WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 517) CID1 1224 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASEN3 ASEN2 ASEN1 ASEN0 INR3 INR2 INR1 WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0006 (see page 518) CID2 WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 519) CID3 Analog-to-Digital Converter (ADC) ADC0 base: 0x4003.8000 ADC1 base: 0x4003.9000 ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000 (see page 542) ADCRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 543) INRDC INR0 ADCIM, type R/W, offset 0x008, reset 0x0000.0000 (see page 545) DCONSS3 DCONSS2 DCONSS1 DCONSS0 MASK3 MASK2 MASK1 MASK0 ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000 (see page 547) DCINSS3 DCINSS2 DCINSS1 DCINSS0 IN3 IN2 IN1 IN0 OV3 OV2 OV1 OV0 UV1 UV0 ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000 (see page 550) ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000 (see page 552) EM3 EM2 EM1 EM0 ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000 (see page 557) UV3 UV2 ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210 (see page 558) SS3 SS2 SS1 SS0 ADCSPC, type R/W, offset 0x024, reset 0x0000.0000 (see page 560) PHASE ADCPSSI, type R/W, offset 0x028, reset - (see page 562) GSYNC SYNCWAIT SS3 SS2 SS1 SS0 ADCSAC, type R/W, offset 0x030, reset 0x0000.0000 (see page 564) AVG ADCDCISC, type R/W1C, offset 0x034, reset 0x0000.0000 (see page 565) DCINT7 DCINT6 DCINT5 DCINT4 DCINT3 DCINT2 DCINT1 DCINT0 ADCCTL, type R/W, offset 0x038, reset 0x0000.0000 (see page 567) VREF ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000 (see page 568) MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 July 22, 2011 1225 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000 (see page 570) TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 ADCSSFIFO0, type RO, offset 0x048, reset - (see page 573) DATA ADCSSFIFO1, type RO, offset 0x068, reset - (see page 573) DATA ADCSSFIFO2, type RO, offset 0x088, reset - (see page 573) DATA ADCSSFIFO3, type RO, offset 0x0A8, reset - (see page 573) DATA ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100 (see page 574) FULL EMPTY HPTR TPTR EMPTY HPTR TPTR EMPTY HPTR TPTR EMPTY HPTR TPTR ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100 (see page 574) FULL ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100 (see page 574) FULL ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100 (see page 574) FULL ADCSSOP0, type R/W, offset 0x050, reset 0x0000.0000 (see page 576) S7DCOP S6DCOP S5DCOP S4DCOP S3DCOP S2DCOP S1DCOP S0DCOP ADCSSDC0, type R/W, offset 0x054, reset 0x0000.0000 (see page 578) S7DCSEL S6DCSEL S5DCSEL S4DCSEL S3DCSEL S2DCSEL S1DCSEL S0DCSEL MUX1 MUX0 MUX1 MUX0 ADCSSMUX1, type R/W, offset 0x060, reset 0x0000.0000 (see page 580) MUX3 MUX2 ADCSSMUX2, type R/W, offset 0x080, reset 0x0000.0000 (see page 580) MUX3 MUX2 ADCSSCTL1, type R/W, offset 0x064, reset 0x0000.0000 (see page 581) TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 ADCSSCTL2, type R/W, offset 0x084, reset 0x0000.0000 (see page 581) TS3 IE3 END3 D3 TS2 IE2 END2 ADCSSOP1, type R/W, offset 0x070, reset 0x0000.0000 (see page 583) S3DCOP S2DCOP S1DCOP S0DCOP S2DCOP S1DCOP S0DCOP ADCSSOP2, type R/W, offset 0x090, reset 0x0000.0000 (see page 583) S3DCOP 1226 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCSSDC1, type R/W, offset 0x074, reset 0x0000.0000 (see page 584) S3DCSEL S2DCSEL S1DCSEL S0DCSEL S1DCSEL S0DCSEL ADCSSDC2, type R/W, offset 0x094, reset 0x0000.0000 (see page 584) S3DCSEL S2DCSEL ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 586) MUX0 ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002 (see page 587) TS0 IE0 END0 D0 ADCSSOP3, type R/W, offset 0x0B0, reset 0x0000.0000 (see page 588) S0DCOP ADCSSDC3, type R/W, offset 0x0B4, reset 0x0000.0000 (see page 589) S0DCSEL ADCDCRIC, type R/W, offset 0xD00, reset 0x0000.0000 (see page 590) DCTRIG7 DCTRIG6 DCTRIG5 DCTRIG4 DCTRIG3 DCTRIG2 DCTRIG1 DCTRIG0 DCINT7 DCINT6 DCINT5 DCINT4 DCINT3 DCINT2 DCINT1 DCINT0 ADCDCCTL0, type R/W, offset 0xE00, reset 0x0000.0000 (see page 595) CTE CTC CTM CIE CIC CIM CTM CIE CIC CIM CTM CIE CIC CIM CTM CIE CIC CIM CTM CIE CIC CIM CTM CIE CIC CIM CTM CIE CIC CIM CTM CIE CIC CIM ADCDCCTL1, type R/W, offset 0xE04, reset 0x0000.0000 (see page 595) CTE CTC ADCDCCTL2, type R/W, offset 0xE08, reset 0x0000.0000 (see page 595) CTE CTC ADCDCCTL3, type R/W, offset 0xE0C, reset 0x0000.0000 (see page 595) CTE CTC ADCDCCTL4, type R/W, offset 0xE10, reset 0x0000.0000 (see page 595) CTE CTC ADCDCCTL5, type R/W, offset 0xE14, reset 0x0000.0000 (see page 595) CTE CTC ADCDCCTL6, type R/W, offset 0xE18, reset 0x0000.0000 (see page 595) CTE CTC ADCDCCTL7, type R/W, offset 0xE1C, reset 0x0000.0000 (see page 595) CTE CTC ADCDCCMP0, type R/W, offset 0xE40, reset 0x0000.0000 (see page 598) COMP1 COMP0 ADCDCCMP1, type R/W, offset 0xE44, reset 0x0000.0000 (see page 598) COMP1 COMP0 July 22, 2011 1227 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OE BE PE FE BUSY DCD DSR CTS ADCDCCMP2, type R/W, offset 0xE48, reset 0x0000.0000 (see page 598) COMP1 COMP0 ADCDCCMP3, type R/W, offset 0xE4C, reset 0x0000.0000 (see page 598) COMP1 COMP0 ADCDCCMP4, type R/W, offset 0xE50, reset 0x0000.0000 (see page 598) COMP1 COMP0 ADCDCCMP5, type R/W, offset 0xE54, reset 0x0000.0000 (see page 598) COMP1 COMP0 ADCDCCMP6, type R/W, offset 0xE58, reset 0x0000.0000 (see page 598) COMP1 COMP0 ADCDCCMP7, type R/W, offset 0xE5C, reset 0x0000.0000 (see page 598) COMP1 COMP0 Universal Asynchronous Receivers/Transmitters (UARTs) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UARTDR, type R/W, offset 0x000, reset 0x0000.0000 (see page 613) OE BE PE FE DATA UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Read-Only Status Register) (see page 615) UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Write-Only Error Clear Register) (see page 615) DATA UARTFR, type RO, offset 0x018, reset 0x0000.0090 (see page 618) RI TXFE RXFF TXFF RXFE UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 (see page 621) ILPDVSR UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 (see page 622) DIVINT UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 (see page 623) DIVFRAC UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 (see page 624) SPS WLEN FEN STP2 EPS PEN BRK EOT SMART SIRLP SIREN UARTEN UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 (see page 626) CTSEN RTSEN RTS DTR RXE TXE LBE LIN HSE UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 (see page 630) RXIFLSEL 1228 TXIFLSEL July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BEIM PEIM FEIM RTIM TXIM RXIM DSRIM DCDIM CTSIM RIIM PERIS FERIS RTRIS TXRIS RXRIS DSRRIS DCDRIS CTSRIS RIRIS PEMIS FEMIS RTMIS TXMIS RXMIS DSRMIS DCDMIS CTSMIS RIMIS PEIC FEIC RTIC TXIC RXIC DSRMIC DCDMIC CTSMIC RIMIC UARTIM, type R/W, offset 0x038, reset 0x0000.0000 (see page 632) LME5IM LME1IM LMSBIM OEIM UARTRIS, type RO, offset 0x03C, reset 0x0000.000F (see page 636) LME5RIS LME1RIS LMSBRIS OERIS BERIS UARTMIS, type RO, offset 0x040, reset 0x0000.0000 (see page 639) LME5MIS LME1MIS LMSBMIS OEMIS BEMIS UARTICR, type W1C, offset 0x044, reset 0x0000.0000 (see page 642) LME5IC LME1IC LMSBIC OEIC BEIC UARTDMACTL, type R/W, offset 0x048, reset 0x0000.0000 (see page 644) DMAERR TXDMAE RXDMAE UARTLCTL, type R/W, offset 0x090, reset 0x0000.0000 (see page 645) BLEN MASTER UARTLSS, type RO, offset 0x094, reset 0x0000.0000 (see page 646) TSS UARTLTIM, type RO, offset 0x098, reset 0x0000.0000 (see page 647) TIMER UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 648) PID4 UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 649) PID5 UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 650) PID6 UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 651) PID7 UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0060 (see page 652) PID0 UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 653) PID1 UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 654) PID2 UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 655) PID3 UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 656) CID0 July 22, 2011 1229 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 657) CID1 UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 658) CID2 UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 659) CID3 Synchronous Serial Interface (SSI) SSI0 base: 0x4000.8000 SSI1 base: 0x4000.9000 SSICR0, type R/W, offset 0x000, reset 0x0000.0000 (see page 675) SCR SPH SPO FRF DSS SSICR1, type R/W, offset 0x004, reset 0x0000.0000 (see page 677) EOT SOD MS SSE LBM BSY RFF RNE TNF TFE TXIM RXIM RTIM RORIM TXRIS RXRIS RTRIS RORRIS TXMIS RXMIS RTMIS RORMIS RTIC RORIC SSIDR, type R/W, offset 0x008, reset 0x0000.0000 (see page 679) DATA SSISR, type RO, offset 0x00C, reset 0x0000.0003 (see page 680) SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 (see page 682) CPSDVSR SSIIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 683) SSIRIS, type RO, offset 0x018, reset 0x0000.0008 (see page 684) SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 686) SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 688) SSIDMACTL, type R/W, offset 0x024, reset 0x0000.0000 (see page 689) TXDMAE RXDMAE SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 690) PID4 SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 691) PID5 SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 692) PID6 1230 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 693) PID7 SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 (see page 694) PID0 SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 695) PID1 SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 696) PID2 SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 697) PID3 SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 698) CID0 SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 699) CID1 SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 700) CID2 SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 701) CID3 Inter-Integrated Circuit (I2C) Interface I2C Master I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2CMSA, type R/W, offset 0x000, reset 0x0000.0000 SA R/S I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Read-Only Status Register) BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY ACK STOP START RUN I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Write-Only Control Register) I2CMDR, type R/W, offset 0x008, reset 0x0000.0000 DATA I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001 TPR I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000 IM I2CMRIS, type RO, offset 0x014, reset 0x0000.0000 RIS July 22, 2011 1231 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CMMIS, type RO, offset 0x018, reset 0x0000.0000 MIS I2CMICR, type WO, offset 0x01C, reset 0x0000.0000 IC I2CMCR, type R/W, offset 0x020, reset 0x0000.0000 SFE Inter-Integrated Circuit (I2C) MFE LPBK Interface I2C Slave I2C 0 base: 0x4002.0000 I2C 1 base: 0x4002.1000 I2CSOAR, type R/W, offset 0x800, reset 0x0000.0000 OAR I2CSCSR, type RO, offset 0x804, reset 0x0000.0000 (Read-Only Status Register) FBR TREQ RREQ I2CSCSR, type WO, offset 0x804, reset 0x0000.0000 (Write-Only Control Register) DA I2CSDR, type R/W, offset 0x808, reset 0x0000.0000 DATA I2CSIMR, type R/W, offset 0x80C, reset 0x0000.0000 STOPIM STARTIM DATAIM I2CSRIS, type RO, offset 0x810, reset 0x0000.0000 STOPRIS STARTRIS DATARIS I2CSMIS, type RO, offset 0x814, reset 0x0000.0000 STOPMIS STARTMIS DATAMIS I2CSICR, type WO, offset 0x818, reset 0x0000.0000 STOPIC Inter-Integrated Circuit Sound (I2S) STARTIC DATAIC CSS LRS Interface Base 0x4005.4000 I2STXFIFO, type WO, offset 0x000, reset 0x0000.0000 (see page 752) TXFIFO TXFIFO I2STXFIFOCFG, type R/W, offset 0x004, reset 0x0000.0000 (see page 753) I2STXCFG, type R/W, offset 0x008, reset 0x1400.7DF0 (see page 754) JST DLY SCP LRP SSZ WM FMT MSL SDSZ I2STXLIMIT, type R/W, offset 0x00C, reset 0x0000.0000 (see page 756) LIMIT 1232 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2STXISM, type R/W, offset 0x010, reset 0x0000.0000 (see page 757) FFI FFM I2STXLEV, type RO, offset 0x018, reset 0x0000.0000 (see page 758) LEVEL I2SRXFIFO, type RO, offset 0x800, reset 0x0000.0000 (see page 759) RXFIFO RXFIFO I2SRXFIFOCFG, type R/W, offset 0x804, reset 0x0000.0000 (see page 760) FMM CSS LRS I2SRXCFG, type R/W, offset 0x808, reset 0x1400.7DF0 (see page 761) JST DLY SCP LRP SSZ RM MSL SDSZ I2SRXLIMIT, type R/W, offset 0x80C, reset 0x0000.7FFF (see page 764) LIMIT I2SRXISM, type R/W, offset 0x810, reset 0x0000.0000 (see page 765) FFI FFM I2SRXLEV, type RO, offset 0x818, reset 0x0000.0000 (see page 766) LEVEL I2SCFG, type R/W, offset 0xC00, reset 0x0000.0000 (see page 767) RXSLV TXSLV RXEN TXEN RXREIM RXSRIM TXWEIM TXSRIM I2SIM, type R/W, offset 0xC10, reset 0x0000.0000 (see page 769) I2SRIS, type RO, offset 0xC14, reset 0x0000.0000 (see page 771) RXRERIS RXSRRIS TXWERIS TXSRRIS RXREMIS RXSRMIS TXWEMIS TXSRMIS I2SMIS, type RO, offset 0xC18, reset 0x0000.0000 (see page 773) I2SIC, type WO, offset 0xC1C, reset 0x0000.0000 (see page 775) RXREIC TXWEIC Controller Area Network (CAN) Module CAN0 base: 0x4004.0000 CAN1 base: 0x4004.1000 CANCTL, type R/W, offset 0x000, reset 0x0000.0001 (see page 798) TEST CCE DAR BOFF EWARN EPASS EIE SIE IE INIT CANSTS, type R/W, offset 0x004, reset 0x0000.0000 (see page 800) RXOK TXOK LEC CANERR, type RO, offset 0x008, reset 0x0000.0000 (see page 803) RP REC TEC July 22, 2011 1233 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATAA DATAB DATAA DATAB CANBIT, type R/W, offset 0x00C, reset 0x0000.2301 (see page 804) TSEG2 TSEG1 SJW BRP CANINT, type RO, offset 0x010, reset 0x0000.0000 (see page 805) INTID CANTST, type R/W, offset 0x014, reset 0x0000.0000 (see page 806) RX TX LBACK SILENT BASIC CANBRPE, type R/W, offset 0x018, reset 0x0000.0000 (see page 808) BRPE CANIF1CRQ, type R/W, offset 0x020, reset 0x0000.0001 (see page 809) BUSY MNUM CANIF2CRQ, type R/W, offset 0x080, reset 0x0000.0001 (see page 809) BUSY MNUM CANIF1CMSK, type R/W, offset 0x024, reset 0x0000.0000 (see page 810) WRNRD MASK ARB CONTROL CLRINTPND WRNRD MASK ARB CONTROL CLRINTPND NEWDAT / TXRQST CANIF2CMSK, type R/W, offset 0x084, reset 0x0000.0000 (see page 810) NEWDAT / TXRQST CANIF1MSK1, type R/W, offset 0x028, reset 0x0000.FFFF (see page 813) MSK CANIF2MSK1, type R/W, offset 0x088, reset 0x0000.FFFF (see page 813) MSK CANIF1MSK2, type R/W, offset 0x02C, reset 0x0000.FFFF (see page 814) MXTD MDIR MSK CANIF2MSK2, type R/W, offset 0x08C, reset 0x0000.FFFF (see page 814) MXTD MDIR MSK CANIF1ARB1, type R/W, offset 0x030, reset 0x0000.0000 (see page 816) ID CANIF2ARB1, type R/W, offset 0x090, reset 0x0000.0000 (see page 816) ID CANIF1ARB2, type R/W, offset 0x034, reset 0x0000.0000 (see page 817) MSGVAL XTD DIR ID CANIF2ARB2, type R/W, offset 0x094, reset 0x0000.0000 (see page 817) MSGVAL XTD DIR ID CANIF1MCTL, type R/W, offset 0x038, reset 0x0000.0000 (see page 819) NEWDAT MSGLST INTPND UMASK TXIE RXIE RMTEN TXRQST EOB 1234 DLC July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXRQST EOB CANIF2MCTL, type R/W, offset 0x098, reset 0x0000.0000 (see page 819) NEWDAT MSGLST INTPND UMASK TXIE RXIE RMTEN DLC CANIF1DA1, type R/W, offset 0x03C, reset 0x0000.0000 (see page 822) DATA CANIF1DA2, type R/W, offset 0x040, reset 0x0000.0000 (see page 822) DATA CANIF1DB1, type R/W, offset 0x044, reset 0x0000.0000 (see page 822) DATA CANIF1DB2, type R/W, offset 0x048, reset 0x0000.0000 (see page 822) DATA CANIF2DA1, type R/W, offset 0x09C, reset 0x0000.0000 (see page 822) DATA CANIF2DA2, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 822) DATA CANIF2DB1, type R/W, offset 0x0A4, reset 0x0000.0000 (see page 822) DATA CANIF2DB2, type R/W, offset 0x0A8, reset 0x0000.0000 (see page 822) DATA CANTXRQ1, type RO, offset 0x100, reset 0x0000.0000 (see page 823) TXRQST CANTXRQ2, type RO, offset 0x104, reset 0x0000.0000 (see page 823) TXRQST CANNWDA1, type RO, offset 0x120, reset 0x0000.0000 (see page 824) NEWDAT CANNWDA2, type RO, offset 0x124, reset 0x0000.0000 (see page 824) NEWDAT CANMSG1INT, type RO, offset 0x140, reset 0x0000.0000 (see page 825) INTPND CANMSG2INT, type RO, offset 0x144, reset 0x0000.0000 (see page 825) INTPND CANMSG1VAL, type RO, offset 0x160, reset 0x0000.0000 (see page 826) MSGVAL CANMSG2VAL, type RO, offset 0x164, reset 0x0000.0000 (see page 826) MSGVAL July 22, 2011 1235 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHYINT MDINT RXER FOV TXEMP TXER RXINT RXERM FOVM TXEMPM TXERM RXINTM PRMS AMUL RXEN CRC PADEN TXEN WRITE START Ethernet Controller Base 0x4004.8000 MACRIS/MACIACK, type R/W1C, offset 0x000, reset 0x0000.0000 (see page 840) MACIM, type R/W, offset 0x004, reset 0x0000.007F (see page 843) PHYINTM MDINTM MACRCTL, type R/W, offset 0x008, reset 0x0000.0008 (see page 845) RSTFIFO BADCRC MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000 (see page 847) DUPLEX MACDATA, type RO, offset 0x010, reset 0x0000.0000 (Reads) (see page 849) RXDATA RXDATA MACDATA, type WO, offset 0x010, reset 0x0000.0000 (Writes) (see page 849) TXDATA TXDATA MACIA0, type R/W, offset 0x014, reset 0x0000.0000 (see page 851) MACOCT4 MACOCT3 MACOCT2 MACOCT1 MACIA1, type R/W, offset 0x018, reset 0x0000.0000 (see page 852) MACOCT6 MACOCT5 MACTHR, type R/W, offset 0x01C, reset 0x0000.003F (see page 853) THRESH MACMCTL, type R/W, offset 0x020, reset 0x0000.0000 (see page 855) REGADR MACMDV, type R/W, offset 0x024, reset 0x0000.0080 (see page 856) DIV MACMADD, type RO, offset 0x028, reset 0x0000.0000 (see page 857) PHYADR MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000 (see page 858) MDTX MACMRXD, type R/W, offset 0x030, reset 0x0000.0000 (see page 859) MDRX MACNP, type RO, offset 0x034, reset 0x0000.0000 (see page 860) NPR MACTR, type R/W, offset 0x038, reset 0x0000.0000 (see page 861) NEWTX MACTS, type R/W, offset 0x03C, reset 0x0000.0000 (see page 862) TSEN 1236 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Universal Serial Bus (USB) Controller Base 0x4005.0000 USBFADDR, type R/W, offset 0x000, reset 0x00 (see page 891) FUNCADDR USBPOWER, type R/W, offset 0x001, reset 0x20 (OTG A / Host Mode) (see page 892) RESET RESUME SUSPEND PWRDNPHY RESET RESUME SUSPEND PWRDNPHY USBPOWER, type R/W, offset 0x001, reset 0x20 (OTG B / Device Mode) (see page 892) ISOUP SOFTCONN USBTXIS, type RO, offset 0x002, reset 0x0000 (see page 895) EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 DISCON CONN SOF BABBLE RESUME SOF RESET SOF BABBLE RESUME SOF RESET EP0 USBRXIS, type RO, offset 0x004, reset 0x0000 (see page 897) EP15 EP14 EP13 EP12 EP11 EP10 USBTXIE, type R/W, offset 0x006, reset 0xFFFF (see page 899) EP15 EP14 EP13 EP12 EP11 EP10 EP0 USBRXIE, type R/W, offset 0x008, reset 0xFFFE (see page 901) EP15 EP14 EP13 EP12 EP11 EP10 USBIS, type RO, offset 0x00A, reset 0x00 (OTG A / Host Mode) (see page 903) VBUSERR SESREQ USBIS, type RO, offset 0x00A, reset 0x00 (OTG B / Device Mode) (see page 903) DISCON RESUME SUSPEND USBIE, type R/W, offset 0x00B, reset 0x06 (OTG A / Host Mode) (see page 906) VBUSERR SESREQ DISCON CONN USBIE, type R/W, offset 0x00B, reset 0x06 (OTG B / Device Mode) (see page 906) DISCON RESUME SUSPEND USBFRAME, type RO, offset 0x00C, reset 0x0000 (see page 909) FRAME USBEPIDX, type R/W, offset 0x00E, reset 0x00 (see page 910) EPIDX USBTEST, type R/W, offset 0x00F, reset 0x00 (OTG A / Host Mode) (see page 911) FORCEH FIFOACC FORCEFS USBTEST, type R/W, offset 0x00F, reset 0x00 (OTG B / Device Mode) (see page 911) FIFOACC FORCEFS USBFIFO0, type R/W, offset 0x020, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO1, type R/W, offset 0x024, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO2, type R/W, offset 0x028, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO3, type R/W, offset 0x02C, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO4, type R/W, offset 0x030, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO5, type R/W, offset 0x034, reset 0x0000.0000 (see page 913) EPDATA EPDATA July 22, 2011 1237 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEV FSDEV LSDEV USBFIFO6, type R/W, offset 0x038, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO7, type R/W, offset 0x03C, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO8, type R/W, offset 0x040, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO9, type R/W, offset 0x044, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO10, type R/W, offset 0x048, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO11, type R/W, offset 0x04C, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO12, type R/W, offset 0x050, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO13, type R/W, offset 0x054, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO14, type R/W, offset 0x058, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBFIFO15, type R/W, offset 0x05C, reset 0x0000.0000 (see page 913) EPDATA EPDATA USBDEVCTL, type R/W, offset 0x060, reset 0x80 (see page 915) VBUS HOST HOSTREQ SESSION USBTXFIFOSZ, type R/W, offset 0x062, reset 0x00 (see page 917) DPB SIZE DPB SIZE USBRXFIFOSZ, type R/W, offset 0x063, reset 0x00 (see page 917) USBTXFIFOADD, type R/W, offset 0x064, reset 0x0000 (see page 918) ADDR USBRXFIFOADD, type R/W, offset 0x066, reset 0x0000 (see page 918) ADDR USBCONTIM, type R/W, offset 0x07A, reset 0x5C (see page 919) WTCON WTID USBVPLEN, type R/W, offset 0x07B, reset 0x3C (see page 920) VPLEN USBFSEOF, type R/W, offset 0x07D, reset 0x77 (see page 921) FSEOFG USBLSEOF, type R/W, offset 0x07E, reset 0x72 (see page 922) LSEOFG USBTXFUNCADDR0, type R/W, offset 0x080, reset 0x00 (see page 923) ADDR USBTXFUNCADDR1, type R/W, offset 0x088, reset 0x00 (see page 923) ADDR 1238 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBTXFUNCADDR2, type R/W, offset 0x090, reset 0x00 (see page 923) ADDR USBTXFUNCADDR3, type R/W, offset 0x098, reset 0x00 (see page 923) ADDR USBTXFUNCADDR4, type R/W, offset 0x0A0, reset 0x00 (see page 923) ADDR USBTXFUNCADDR5, type R/W, offset 0x0A8, reset 0x00 (see page 923) ADDR USBTXFUNCADDR6, type R/W, offset 0x0B0, reset 0x00 (see page 923) ADDR USBTXFUNCADDR7, type R/W, offset 0x0B8, reset 0x00 (see page 923) ADDR USBTXFUNCADDR8, type R/W, offset 0x0C0, reset 0x00 (see page 923) ADDR USBTXFUNCADDR9, type R/W, offset 0x0C8, reset 0x00 (see page 923) ADDR USBTXFUNCADDR10, type R/W, offset 0x0D0, reset 0x00 (see page 923) ADDR USBTXFUNCADDR11, type R/W, offset 0x0D8, reset 0x00 (see page 923) ADDR USBTXFUNCADDR12, type R/W, offset 0x0E0, reset 0x00 (see page 923) ADDR USBTXFUNCADDR13, type R/W, offset 0x0E8, reset 0x00 (see page 923) ADDR USBTXFUNCADDR14, type R/W, offset 0x0F0, reset 0x00 (see page 923) ADDR USBTXFUNCADDR15, type R/W, offset 0x0F8, reset 0x00 (see page 923) ADDR USBTXHUBADDR0, type R/W, offset 0x082, reset 0x00 (see page 925) MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR USBTXHUBADDR1, type R/W, offset 0x08A, reset 0x00 (see page 925) USBTXHUBADDR2, type R/W, offset 0x092, reset 0x00 (see page 925) USBTXHUBADDR3, type R/W, offset 0x09A, reset 0x00 (see page 925) USBTXHUBADDR4, type R/W, offset 0x0A2, reset 0x00 (see page 925) USBTXHUBADDR5, type R/W, offset 0x0AA, reset 0x00 (see page 925) USBTXHUBADDR6, type R/W, offset 0x0B2, reset 0x00 (see page 925) USBTXHUBADDR7, type R/W, offset 0x0BA, reset 0x00 (see page 925) USBTXHUBADDR8, type R/W, offset 0x0C2, reset 0x00 (see page 925) USBTXHUBADDR9, type R/W, offset 0x0CA, reset 0x00 (see page 925) USBTXHUBADDR10, type R/W, offset 0x0D2, reset 0x00 (see page 925) USBTXHUBADDR11, type R/W, offset 0x0DA, reset 0x00 (see page 925) July 22, 2011 1239 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBTXHUBADDR12, type R/W, offset 0x0E2, reset 0x00 (see page 925) MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR USBTXHUBADDR13, type R/W, offset 0x0EA, reset 0x00 (see page 925) USBTXHUBADDR14, type R/W, offset 0x0F2, reset 0x00 (see page 925) USBTXHUBADDR15, type R/W, offset 0x0FA, reset 0x00 (see page 925) USBTXHUBPORT0, type R/W, offset 0x083, reset 0x00 (see page 927) PORT USBTXHUBPORT1, type R/W, offset 0x08B, reset 0x00 (see page 927) PORT USBTXHUBPORT2, type R/W, offset 0x093, reset 0x00 (see page 927) PORT USBTXHUBPORT3, type R/W, offset 0x09B, reset 0x00 (see page 927) PORT USBTXHUBPORT4, type R/W, offset 0x0A3, reset 0x00 (see page 927) PORT USBTXHUBPORT5, type R/W, offset 0x0AB, reset 0x00 (see page 927) PORT USBTXHUBPORT6, type R/W, offset 0x0B3, reset 0x00 (see page 927) PORT USBTXHUBPORT7, type R/W, offset 0x0BB, reset 0x00 (see page 927) PORT USBTXHUBPORT8, type R/W, offset 0x0C3, reset 0x00 (see page 927) PORT USBTXHUBPORT9, type R/W, offset 0x0CB, reset 0x00 (see page 927) PORT USBTXHUBPORT10, type R/W, offset 0x0D3, reset 0x00 (see page 927) PORT USBTXHUBPORT11, type R/W, offset 0x0DB, reset 0x00 (see page 927) PORT USBTXHUBPORT12, type R/W, offset 0x0E3, reset 0x00 (see page 927) PORT USBTXHUBPORT13, type R/W, offset 0x0EB, reset 0x00 (see page 927) PORT USBTXHUBPORT14, type R/W, offset 0x0F3, reset 0x00 (see page 927) PORT USBTXHUBPORT15, type R/W, offset 0x0FB, reset 0x00 (see page 927) PORT USBRXFUNCADDR1, type R/W, offset 0x08C, reset 0x00 (see page 929) ADDR USBRXFUNCADDR2, type R/W, offset 0x094, reset 0x00 (see page 929) ADDR USBRXFUNCADDR3, type R/W, offset 0x09C, reset 0x00 (see page 929) ADDR USBRXFUNCADDR4, type R/W, offset 0x0A4, reset 0x00 (see page 929) ADDR USBRXFUNCADDR5, type R/W, offset 0x0AC, reset 0x00 (see page 929) ADDR USBRXFUNCADDR6, type R/W, offset 0x0B4, reset 0x00 (see page 929) ADDR 1240 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBRXFUNCADDR7, type R/W, offset 0x0BC, reset 0x00 (see page 929) ADDR USBRXFUNCADDR8, type R/W, offset 0x0C4, reset 0x00 (see page 929) ADDR USBRXFUNCADDR9, type R/W, offset 0x0CC, reset 0x00 (see page 929) ADDR USBRXFUNCADDR10, type R/W, offset 0x0D4, reset 0x00 (see page 929) ADDR USBRXFUNCADDR11, type R/W, offset 0x0DC, reset 0x00 (see page 929) ADDR USBRXFUNCADDR12, type R/W, offset 0x0E4, reset 0x00 (see page 929) ADDR USBRXFUNCADDR13, type R/W, offset 0x0EC, reset 0x00 (see page 929) ADDR USBRXFUNCADDR14, type R/W, offset 0x0F4, reset 0x00 (see page 929) ADDR USBRXFUNCADDR15, type R/W, offset 0x0FC, reset 0x00 (see page 929) ADDR USBRXHUBADDR1, type R/W, offset 0x08E, reset 0x00 (see page 931) MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR MULTTRAN ADDR USBRXHUBADDR2, type R/W, offset 0x096, reset 0x00 (see page 931) USBRXHUBADDR3, type R/W, offset 0x09E, reset 0x00 (see page 931) USBRXHUBADDR4, type R/W, offset 0x0A6, reset 0x00 (see page 931) USBRXHUBADDR5, type R/W, offset 0x0AE, reset 0x00 (see page 931) USBRXHUBADDR6, type R/W, offset 0x0B6, reset 0x00 (see page 931) USBRXHUBADDR7, type R/W, offset 0x0BE, reset 0x00 (see page 931) USBRXHUBADDR8, type R/W, offset 0x0C6, reset 0x00 (see page 931) USBRXHUBADDR9, type R/W, offset 0x0CE, reset 0x00 (see page 931) USBRXHUBADDR10, type R/W, offset 0x0D6, reset 0x00 (see page 931) USBRXHUBADDR11, type R/W, offset 0x0DE, reset 0x00 (see page 931) USBRXHUBADDR12, type R/W, offset 0x0E6, reset 0x00 (see page 931) USBRXHUBADDR13, type R/W, offset 0x0EE, reset 0x00 (see page 931) USBRXHUBADDR14, type R/W, offset 0x0F6, reset 0x00 (see page 931) USBRXHUBADDR15, type R/W, offset 0x0FE, reset 0x00 (see page 931) USBRXHUBPORT1, type R/W, offset 0x08F, reset 0x00 (see page 933) PORT USBRXHUBPORT2, type R/W, offset 0x097, reset 0x00 (see page 933) PORT July 22, 2011 1241 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBRXHUBPORT3, type R/W, offset 0x09F, reset 0x00 (see page 933) PORT USBRXHUBPORT4, type R/W, offset 0x0A7, reset 0x00 (see page 933) PORT USBRXHUBPORT5, type R/W, offset 0x0AF, reset 0x00 (see page 933) PORT USBRXHUBPORT6, type R/W, offset 0x0B7, reset 0x00 (see page 933) PORT USBRXHUBPORT7, type R/W, offset 0x0BF, reset 0x00 (see page 933) PORT USBRXHUBPORT8, type R/W, offset 0x0C7, reset 0x00 (see page 933) PORT USBRXHUBPORT9, type R/W, offset 0x0CF, reset 0x00 (see page 933) PORT USBRXHUBPORT10, type R/W, offset 0x0D7, reset 0x00 (see page 933) PORT USBRXHUBPORT11, type R/W, offset 0x0DF, reset 0x00 (see page 933) PORT USBRXHUBPORT12, type R/W, offset 0x0E7, reset 0x00 (see page 933) PORT USBRXHUBPORT13, type R/W, offset 0x0EF, reset 0x00 (see page 933) PORT USBRXHUBPORT14, type R/W, offset 0x0F7, reset 0x00 (see page 933) PORT USBRXHUBPORT15, type R/W, offset 0x0FF, reset 0x00 (see page 933) PORT USBTXMAXP1, type R/W, offset 0x110, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP2, type R/W, offset 0x120, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP3, type R/W, offset 0x130, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP4, type R/W, offset 0x140, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP5, type R/W, offset 0x150, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP6, type R/W, offset 0x160, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP7, type R/W, offset 0x170, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP8, type R/W, offset 0x180, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP9, type R/W, offset 0x190, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP10, type R/W, offset 0x1A0, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP11, type R/W, offset 0x1B0, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP12, type R/W, offset 0x1C0, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP13, type R/W, offset 0x1D0, reset 0x0000 (see page 935) MAXLOAD 1242 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERROR SETUP STALLED TXRDY RXRDY SETEND DATAEND STALLED TXRDY RXRDY DT FLUSH USBTXMAXP14, type R/W, offset 0x1E0, reset 0x0000 (see page 935) MAXLOAD USBTXMAXP15, type R/W, offset 0x1F0, reset 0x0000 (see page 935) MAXLOAD USBCSRL0, type W1C, offset 0x102, reset 0x00 (OTG A / Host Mode) (see page 937) NAKTO STATUS REQPKT USBCSRL0, type W1C, offset 0x102, reset 0x00 (OTG B / Device Mode) (see page 937) SETENDC RXRDYC STALL USBCSRH0, type W1C, offset 0x103, reset 0x00 (OTG A / Host Mode) (see page 941) DTWE USBCSRH0, type W1C, offset 0x103, reset 0x00 (OTG B / Device Mode) (see page 941) FLUSH USBCOUNT0, type RO, offset 0x108, reset 0x00 (see page 943) COUNT USBTYPE0, type R/W, offset 0x10A, reset 0x00 (see page 944) SPEED USBNAKLMT, type R/W, offset 0x10B, reset 0x00 (see page 945) NAKLMT USBTXCSRL1, type R/W, offset 0x112, reset 0x00 (OTG A / Host Mode) (see page 946) NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY NAKTO CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY USBTXCSRL2, type R/W, offset 0x122, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL3, type R/W, offset 0x132, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL4, type R/W, offset 0x142, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL5, type R/W, offset 0x152, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL6, type R/W, offset 0x162, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL7, type R/W, offset 0x172, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL8, type R/W, offset 0x182, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL9, type R/W, offset 0x192, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL10, type R/W, offset 0x1A2, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL11, type R/W, offset 0x1B2, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL12, type R/W, offset 0x1C2, reset 0x00 (OTG A / Host Mode) (see page 946) NAKTO USBTXCSRL13, type R/W, offset 0x1D2, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL14, type R/W, offset 0x1E2, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL15, type R/W, offset 0x1F2, reset 0x00 (OTG A / Host Mode) (see page 946) USBTXCSRL1, type R/W, offset 0x112, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL2, type R/W, offset 0x122, reset 0x00 (OTG B / Device Mode) (see page 946) July 22, 2011 1243 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY CLRDT STALLED STALL FLUSH UNDRN FIFONE TXRDY AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT AUTOSET MODE DMAEN FDT DMAMOD DTWE DT MODE DMAEN FDT DMAMOD DTWE DT MODE DMAEN FDT DMAMOD DTWE DT MODE DMAEN FDT DMAMOD DTWE DT MODE DMAEN FDT DMAMOD DTWE DT USBTXCSRL3, type R/W, offset 0x132, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL4, type R/W, offset 0x142, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL5, type R/W, offset 0x152, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL6, type R/W, offset 0x162, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL7, type R/W, offset 0x172, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL8, type R/W, offset 0x182, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL9, type R/W, offset 0x192, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL10, type R/W, offset 0x1A2, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL11, type R/W, offset 0x1B2, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL12, type R/W, offset 0x1C2, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL13, type R/W, offset 0x1D2, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL14, type R/W, offset 0x1E2, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRL15, type R/W, offset 0x1F2, reset 0x00 (OTG B / Device Mode) (see page 946) USBTXCSRH1, type R/W, offset 0x113, reset 0x00 (OTG A / Host Mode) (see page 951) USBTXCSRH2, type R/W, offset 0x123, reset 0x00 (OTG A / Host Mode) (see page 951) USBTXCSRH3, type R/W, offset 0x133, reset 0x00 (OTG A / Host Mode) (see page 951) USBTXCSRH4, type R/W, offset 0x143, reset 0x00 (OTG A / Host Mode) (see page 951) USBTXCSRH5, type R/W, offset 0x153, reset 0x00 (OTG A / Host Mode) (see page 951) USBTXCSRH6, type R/W, offset 0x163, reset 0x00 (OTG A / Host Mode) (see page 951) USBTXCSRH7, type R/W, offset 0x173, reset 0x00 (OTG A / Host Mode) (see page 951) USBTXCSRH8, type R/W, offset 0x183, reset 0x00 (OTG A / Host Mode) (see page 951) USBTXCSRH9, type R/W, offset 0x193, reset 0x00 (OTG A / Host Mode) (see page 951) USBTXCSRH10, type R/W, offset 0x1A3, reset 0x00 (OTG A / Host Mode) (see page 951) AUTOSET USBTXCSRH11, type R/W, offset 0x1B3, reset 0x00 (OTG A / Host Mode) (see page 951) AUTOSET USBTXCSRH12, type R/W, offset 0x1C3, reset 0x00 (OTG A / Host Mode) (see page 951) AUTOSET USBTXCSRH13, type R/W, offset 0x1D3, reset 0x00 (OTG A / Host Mode) (see page 951) AUTOSET 1244 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE DMAEN FDT DMAMOD DTWE DT MODE DMAEN FDT DMAMOD DTWE DT ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD ISO MODE DMAEN FDT DMAMOD USBTXCSRH14, type R/W, offset 0x1E3, reset 0x00 (OTG A / Host Mode) (see page 951) AUTOSET USBTXCSRH15, type R/W, offset 0x1F3, reset 0x00 (OTG A / Host Mode) (see page 951) AUTOSET USBTXCSRH1, type R/W, offset 0x113, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH2, type R/W, offset 0x123, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH3, type R/W, offset 0x133, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH4, type R/W, offset 0x143, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH5, type R/W, offset 0x153, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH6, type R/W, offset 0x163, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH7, type R/W, offset 0x173, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH8, type R/W, offset 0x183, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH9, type R/W, offset 0x193, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH10, type R/W, offset 0x1A3, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH11, type R/W, offset 0x1B3, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH12, type R/W, offset 0x1C3, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH13, type R/W, offset 0x1D3, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH14, type R/W, offset 0x1E3, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBTXCSRH15, type R/W, offset 0x1F3, reset 0x00 (OTG B / Device Mode) (see page 951) AUTOSET USBRXMAXP1, type R/W, offset 0x114, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP2, type R/W, offset 0x124, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP3, type R/W, offset 0x134, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP4, type R/W, offset 0x144, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP5, type R/W, offset 0x154, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP6, type R/W, offset 0x164, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP7, type R/W, offset 0x174, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP8, type R/W, offset 0x184, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP9, type R/W, offset 0x194, reset 0x0000 (see page 955) MAXLOAD July 22, 2011 1245 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY ERROR FULL RXRDY USBRXMAXP10, type R/W, offset 0x1A4, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP11, type R/W, offset 0x1B4, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP12, type R/W, offset 0x1C4, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP13, type R/W, offset 0x1D4, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP14, type R/W, offset 0x1E4, reset 0x0000 (see page 955) MAXLOAD USBRXMAXP15, type R/W, offset 0x1F4, reset 0x0000 (see page 955) MAXLOAD USBRXCSRL1, type R/W, offset 0x116, reset 0x00 (OTG A / Host Mode) (see page 957) CLRDT STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH STALLED REQPKT FLUSH STALLED REQPKT FLUSH STALLED REQPKT FLUSH STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH CLRDT STALLED REQPKT FLUSH DATAERR / NAKTO USBRXCSRL2, type R/W, offset 0x126, reset 0x00 (OTG A / Host Mode) (see page 957) DATAERR / NAKTO USBRXCSRL3, type R/W, offset 0x136, reset 0x00 (OTG A / Host Mode) (see page 957) DATAERR / NAKTO USBRXCSRL4, type R/W, offset 0x146, reset 0x00 (OTG A / Host Mode) (see page 957) DATAERR / NAKTO USBRXCSRL5, type R/W, offset 0x156, reset 0x00 (OTG A / Host Mode) (see page 957) DATAERR / NAKTO USBRXCSRL6, type R/W, offset 0x166, reset 0x00 (OTG A / Host Mode) (see page 957) DATAERR / NAKTO USBRXCSRL7, type R/W, offset 0x176, reset 0x00 (OTG A / Host Mode) (see page 957) DATAERR / NAKTO USBRXCSRL8, type R/W, offset 0x186, reset 0x00 (OTG A / Host Mode) (see page 957) DATAERR / NAKTO USBRXCSRL9, type R/W, offset 0x196, reset 0x00 (OTG A / Host Mode) (see page 957) DATAERR / NAKTO USBRXCSRL10, type R/W, offset 0x1A6, reset 0x00 (OTG A / Host Mode) (see page 957) CLRDT DATAERR / NAKTO USBRXCSRL11, type R/W, offset 0x1B6, reset 0x00 (OTG A / Host Mode) (see page 957) CLRDT DATAERR / NAKTO USBRXCSRL12, type R/W, offset 0x1C6, reset 0x00 (OTG A / Host Mode) (see page 957) CLRDT DATAERR / NAKTO USBRXCSRL13, type R/W, offset 0x1D6, reset 0x00 (OTG A / Host Mode) (see page 957) CLRDT DATAERR / NAKTO USBRXCSRL14, type R/W, offset 0x1E6, reset 0x00 (OTG A / Host Mode) (see page 957) DATAERR / NAKTO USBRXCSRL15, type R/W, offset 0x1F6, reset 0x00 (OTG A / Host Mode) (see page 957) 1246 DATAERR / NAKTO July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLRDT STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY STALLED STALL FLUSH DATAERR OVER FULL RXRDY USBRXCSRL1, type R/W, offset 0x116, reset 0x00 (OTG B / Device Mode) (see page 957) USBRXCSRL2, type R/W, offset 0x126, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL3, type R/W, offset 0x136, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL4, type R/W, offset 0x146, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL5, type R/W, offset 0x156, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL6, type R/W, offset 0x166, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL7, type R/W, offset 0x176, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL8, type R/W, offset 0x186, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL9, type R/W, offset 0x196, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL10, type R/W, offset 0x1A6, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL11, type R/W, offset 0x1B6, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL12, type R/W, offset 0x1C6, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL13, type R/W, offset 0x1D6, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL14, type R/W, offset 0x1E6, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRL15, type R/W, offset 0x1F6, reset 0x00 (OTG B / Device Mode) (see page 957) CLRDT USBRXCSRH1, type R/W, offset 0x117, reset 0x00 (OTG A / Host Mode) (see page 962) AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT DMAEN PIDERR DMAMOD DTWE DT DMAEN PIDERR DMAMOD DTWE DT USBRXCSRH2, type R/W, offset 0x127, reset 0x00 (OTG A / Host Mode) (see page 962) USBRXCSRH3, type R/W, offset 0x137, reset 0x00 (OTG A / Host Mode) (see page 962) USBRXCSRH4, type R/W, offset 0x147, reset 0x00 (OTG A / Host Mode) (see page 962) USBRXCSRH5, type R/W, offset 0x157, reset 0x00 (OTG A / Host Mode) (see page 962) USBRXCSRH6, type R/W, offset 0x167, reset 0x00 (OTG A / Host Mode) (see page 962) USBRXCSRH7, type R/W, offset 0x177, reset 0x00 (OTG A / Host Mode) (see page 962) USBRXCSRH8, type R/W, offset 0x187, reset 0x00 (OTG A / Host Mode) (see page 962) USBRXCSRH9, type R/W, offset 0x197, reset 0x00 (OTG A / Host Mode) (see page 962) USBRXCSRH10, type R/W, offset 0x1A7, reset 0x00 (OTG A / Host Mode) (see page 962) AUTOCL AUTORQ USBRXCSRH11, type R/W, offset 0x1B7, reset 0x00 (OTG A / Host Mode) (see page 962) AUTOCL AUTORQ July 22, 2011 1247 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBRXCSRH12, type R/W, offset 0x1C7, reset 0x00 (OTG A / Host Mode) (see page 962) AUTOCL AUTORQ DMAEN PIDERR DMAMOD DTWE DT DMAEN PIDERR DMAMOD DTWE DT DMAEN PIDERR DMAMOD DTWE DT DMAEN PIDERR DMAMOD DTWE DT USBRXCSRH13, type R/W, offset 0x1D7, reset 0x00 (OTG A / Host Mode) (see page 962) AUTOCL AUTORQ USBRXCSRH14, type R/W, offset 0x1E7, reset 0x00 (OTG A / Host Mode) (see page 962) AUTOCL AUTORQ USBRXCSRH15, type R/W, offset 0x1F7, reset 0x00 (OTG A / Host Mode) (see page 962) AUTOCL AUTORQ USBRXCSRH1, type R/W, offset 0x117, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN ISO DMAEN DISNYET / PIDERR DMAMOD USBRXCSRH2, type R/W, offset 0x127, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH3, type R/W, offset 0x137, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH4, type R/W, offset 0x147, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH5, type R/W, offset 0x157, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH6, type R/W, offset 0x167, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH7, type R/W, offset 0x177, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH8, type R/W, offset 0x187, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH9, type R/W, offset 0x197, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH10, type R/W, offset 0x1A7, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH11, type R/W, offset 0x1B7, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH12, type R/W, offset 0x1C7, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH13, type R/W, offset 0x1D7, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH14, type R/W, offset 0x1E7, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCSRH15, type R/W, offset 0x1F7, reset 0x00 (OTG B / Device Mode) (see page 962) AUTOCL DISNYET / PIDERR DMAMOD USBRXCOUNT1, type RO, offset 0x118, reset 0x0000 (see page 967) COUNT USBRXCOUNT2, type RO, offset 0x128, reset 0x0000 (see page 967) COUNT 1248 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBRXCOUNT3, type RO, offset 0x138, reset 0x0000 (see page 967) COUNT USBRXCOUNT4, type RO, offset 0x148, reset 0x0000 (see page 967) COUNT USBRXCOUNT5, type RO, offset 0x158, reset 0x0000 (see page 967) COUNT USBRXCOUNT6, type RO, offset 0x168, reset 0x0000 (see page 967) COUNT USBRXCOUNT7, type RO, offset 0x178, reset 0x0000 (see page 967) COUNT USBRXCOUNT8, type RO, offset 0x188, reset 0x0000 (see page 967) COUNT USBRXCOUNT9, type RO, offset 0x198, reset 0x0000 (see page 967) COUNT USBRXCOUNT10, type RO, offset 0x1A8, reset 0x0000 (see page 967) COUNT USBRXCOUNT11, type RO, offset 0x1B8, reset 0x0000 (see page 967) COUNT USBRXCOUNT12, type RO, offset 0x1C8, reset 0x0000 (see page 967) COUNT USBRXCOUNT13, type RO, offset 0x1D8, reset 0x0000 (see page 967) COUNT USBRXCOUNT14, type RO, offset 0x1E8, reset 0x0000 (see page 967) COUNT USBRXCOUNT15, type RO, offset 0x1F8, reset 0x0000 (see page 967) COUNT USBTXTYPE1, type R/W, offset 0x11A, reset 0x00 (see page 969) SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP USBTXTYPE2, type R/W, offset 0x12A, reset 0x00 (see page 969) USBTXTYPE3, type R/W, offset 0x13A, reset 0x00 (see page 969) USBTXTYPE4, type R/W, offset 0x14A, reset 0x00 (see page 969) USBTXTYPE5, type R/W, offset 0x15A, reset 0x00 (see page 969) USBTXTYPE6, type R/W, offset 0x16A, reset 0x00 (see page 969) USBTXTYPE7, type R/W, offset 0x17A, reset 0x00 (see page 969) USBTXTYPE8, type R/W, offset 0x18A, reset 0x00 (see page 969) USBTXTYPE9, type R/W, offset 0x19A, reset 0x00 (see page 969) USBTXTYPE10, type R/W, offset 0x1AA, reset 0x00 (see page 969) USBTXTYPE11, type R/W, offset 0x1BA, reset 0x00 (see page 969) USBTXTYPE12, type R/W, offset 0x1CA, reset 0x00 (see page 969) USBTXTYPE13, type R/W, offset 0x1DA, reset 0x00 (see page 969) July 22, 2011 1249 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBTXTYPE14, type R/W, offset 0x1EA, reset 0x00 (see page 969) SPEED PROTO TEP SPEED PROTO TEP USBTXTYPE15, type R/W, offset 0x1FA, reset 0x00 (see page 969) USBTXINTERVAL1, type R/W, offset 0x11B, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL2, type R/W, offset 0x12B, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL3, type R/W, offset 0x13B, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL4, type R/W, offset 0x14B, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL5, type R/W, offset 0x15B, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL6, type R/W, offset 0x16B, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL7, type R/W, offset 0x17B, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL8, type R/W, offset 0x18B, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL9, type R/W, offset 0x19B, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL10, type R/W, offset 0x1AB, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL11, type R/W, offset 0x1BB, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL12, type R/W, offset 0x1CB, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL13, type R/W, offset 0x1DB, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL14, type R/W, offset 0x1EB, reset 0x00 (see page 971) TXPOLL / NAKLMT USBTXINTERVAL15, type R/W, offset 0x1FB, reset 0x00 (see page 971) TXPOLL / NAKLMT USBRXTYPE1, type R/W, offset 0x11C, reset 0x00 (see page 973) SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP USBRXTYPE2, type R/W, offset 0x12C, reset 0x00 (see page 973) USBRXTYPE3, type R/W, offset 0x13C, reset 0x00 (see page 973) USBRXTYPE4, type R/W, offset 0x14C, reset 0x00 (see page 973) USBRXTYPE5, type R/W, offset 0x15C, reset 0x00 (see page 973) USBRXTYPE6, type R/W, offset 0x16C, reset 0x00 (see page 973) USBRXTYPE7, type R/W, offset 0x17C, reset 0x00 (see page 973) USBRXTYPE8, type R/W, offset 0x18C, reset 0x00 (see page 973) USBRXTYPE9, type R/W, offset 0x19C, reset 0x00 (see page 973) 1250 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBRXTYPE10, type R/W, offset 0x1AC, reset 0x00 (see page 973) SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP SPEED PROTO TEP USBRXTYPE11, type R/W, offset 0x1BC, reset 0x00 (see page 973) USBRXTYPE12, type R/W, offset 0x1CC, reset 0x00 (see page 973) USBRXTYPE13, type R/W, offset 0x1DC, reset 0x00 (see page 973) USBRXTYPE14, type R/W, offset 0x1EC, reset 0x00 (see page 973) USBRXTYPE15, type R/W, offset 0x1FC, reset 0x00 (see page 973) USBRXINTERVAL1, type R/W, offset 0x11D, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL2, type R/W, offset 0x12D, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL3, type R/W, offset 0x13D, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL4, type R/W, offset 0x14D, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL5, type R/W, offset 0x15D, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL6, type R/W, offset 0x16D, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL7, type R/W, offset 0x17D, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL8, type R/W, offset 0x18D, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL9, type R/W, offset 0x19D, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL10, type R/W, offset 0x1AD, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL11, type R/W, offset 0x1BD, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL12, type R/W, offset 0x1CD, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL13, type R/W, offset 0x1DD, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL14, type R/W, offset 0x1ED, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRXINTERVAL15, type R/W, offset 0x1FD, reset 0x00 (see page 975) TXPOLL / NAKLMT USBRQPKTCOUNT1, type R/W, offset 0x304, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT2, type R/W, offset 0x308, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT3, type R/W, offset 0x30C, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT4, type R/W, offset 0x310, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT5, type R/W, offset 0x314, reset 0x0000 (see page 977) COUNT July 22, 2011 1251 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 USBRQPKTCOUNT6, type R/W, offset 0x318, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT7, type R/W, offset 0x31C, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT8, type R/W, offset 0x320, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT9, type R/W, offset 0x324, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT10, type R/W, offset 0x328, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT11, type R/W, offset 0x32C, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT12, type R/W, offset 0x330, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT13, type R/W, offset 0x334, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT14, type R/W, offset 0x338, reset 0x0000 (see page 977) COUNT USBRQPKTCOUNT15, type R/W, offset 0x33C, reset 0x0000 (see page 977) COUNT USBRXDPKTBUFDIS, type R/W, offset 0x340, reset 0x0000 (see page 979) EP15 EP14 EP13 EP12 EP11 EP10 EP9 USBTXDPKTBUFDIS, type R/W, offset 0x342, reset 0x0000 (see page 981) EP15 EP14 EP13 EP12 EP11 EP10 EP9 USBEPC, type R/W, offset 0x400, reset 0x0000.0000 (see page 983) PFLTACT PFLTAEN PFLTSEN PFLTEN EPENDE EPEN USBEPCRIS, type RO, offset 0x404, reset 0x0000.0000 (see page 986) PF USBEPCIM, type R/W, offset 0x408, reset 0x0000.0000 (see page 987) PF USBEPCISC, type R/W, offset 0x40C, reset 0x0000.0000 (see page 988) PF USBDRRIS, type RO, offset 0x410, reset 0x0000.0000 (see page 989) RESUME USBDRIM, type R/W, offset 0x414, reset 0x0000.0000 (see page 990) RESUME USBDRISC, type W1C, offset 0x418, reset 0x0000.0000 (see page 991) RESUME USBGPCS, type R/W, offset 0x41C, reset 0x0000.0001 (see page 992) DEVMODOTG DEVMOD USBVDC, type R/W, offset 0x430, reset 0x0000.0000 (see page 993) VBDEN 1252 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USBVDCRIS, type RO, offset 0x434, reset 0x0000.0000 (see page 994) VD USBVDCIM, type R/W, offset 0x438, reset 0x0000.0000 (see page 995) VD USBVDCISC, type R/W, offset 0x43C, reset 0x0000.0000 (see page 996) VD USBIDVRIS, type RO, offset 0x444, reset 0x0000.0000 (see page 997) ID USBIDVIM, type R/W, offset 0x448, reset 0x0000.0000 (see page 998) ID USBIDVISC, type R/W1C, offset 0x44C, reset 0x0000.0000 (see page 999) ID USBDMASEL, type R/W, offset 0x450, reset 0x0033.2211 (see page 1000) DMABTX DMABRX DMACTX DMACRX DMAATX DMAARX Analog Comparators Base 0x4003.C000 ACMIS, type R/W1C, offset 0x000, reset 0x0000.0000 (see page 1008) IN1 IN0 IN1 IN0 IN1 IN0 ACRIS, type RO, offset 0x004, reset 0x0000.0000 (see page 1009) ACINTEN, type R/W, offset 0x008, reset 0x0000.0000 (see page 1010) ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000 (see page 1011) EN RNG VREF ACSTAT0, type RO, offset 0x020, reset 0x0000.0000 (see page 1012) OVAL ACSTAT1, type RO, offset 0x040, reset 0x0000.0000 (see page 1012) OVAL ACCTL0, type R/W, offset 0x024, reset 0x0000.0000 (see page 1013) TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV TSLVAL TSEN ISLVAL ISEN CINV ACCTL1, type R/W, offset 0x044, reset 0x0000.0000 (see page 1013) TOEN ASRCP Pulse Width Modulator (PWM) PWM0 base: 0x4002.8000 PWMCTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 1030) GLOBALSYNC2 GLOBALSYNC1 GLOBALSYNC0 July 22, 2011 1253 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYNC2 SYNC1 SYNC0 PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000 (see page 1031) PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000 (see page 1032) PWM5EN PWM4EN PWM3EN PWM2EN PWM1EN PWM0EN PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000 (see page 1034) PWM5INV PWM4INV PWM3INV PWM2INV PWM1INV PWM0INV PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000 (see page 1036) FAULT5 FAULT4 FAULT3 FAULT2 FAULT1 FAULT0 PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000 (see page 1038) INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0 INTPWM2 INTPWM1 INTPWM0 PWMRIS, type RO, offset 0x018, reset 0x0000.0000 (see page 1040) INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0 INTPWM2 INTPWM1 INTPWM0 PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000 (see page 1042) INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0 INTPWM2 INTPWM1 INTPWM0 PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000 (see page 1044) FAULT3 FAULT2 FAULT1 FAULT0 PWM3 PWM2 PWM1 PWM0 PWMFAULTVAL, type R/W, offset 0x024, reset 0x0000.0000 (see page 1046) PWM5 PWM4 PWMENUPD, type R/W, offset 0x028, reset 0x0000.0000 (see page 1048) ENUPD5 ENUPD4 ENUPD3 ENUPD2 ENUPD1 ENUPD0 LATCH MINFLTPER FLTSRC GENBUPD GENAUPD CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE LATCH MINFLTPER FLTSRC GENAUPD CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE LATCH MINFLTPER FLTSRC GENAUPD CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000 (see page 1051) DBFALLUPD DBRISEUPD DBCTLUPD PWM1CTL, type R/W, offset 0x080, reset 0x0000.0000 (see page 1051) DBFALLUPD DBRISEUPD DBCTLUPD GENBUPD PWM2CTL, type R/W, offset 0x0C0, reset 0x0000.0000 (see page 1051) DBFALLUPD DBRISEUPD DBCTLUPD GENBUPD PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000 (see page 1056) TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO PWM1INTEN, type R/W, offset 0x084, reset 0x0000.0000 (see page 1056) TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO PWM2INTEN, type R/W, offset 0x0C4, reset 0x0000.0000 (see page 1056) TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO PWM0RIS, type RO, offset 0x048, reset 0x0000.0000 (see page 1059) INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO 1254 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM1RIS, type RO, offset 0x088, reset 0x0000.0000 (see page 1059) INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO PWM2RIS, type RO, offset 0x0C8, reset 0x0000.0000 (see page 1059) INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000 (see page 1061) INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO PWM1ISC, type R/W1C, offset 0x08C, reset 0x0000.0000 (see page 1061) INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO PWM2ISC, type R/W1C, offset 0x0CC, reset 0x0000.0000 (see page 1061) INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO PWM0LOAD, type R/W, offset 0x050, reset 0x0000.0000 (see page 1063) LOAD PWM1LOAD, type R/W, offset 0x090, reset 0x0000.0000 (see page 1063) LOAD PWM2LOAD, type R/W, offset 0x0D0, reset 0x0000.0000 (see page 1063) LOAD PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000 (see page 1064) COUNT PWM1COUNT, type RO, offset 0x094, reset 0x0000.0000 (see page 1064) COUNT PWM2COUNT, type RO, offset 0x0D4, reset 0x0000.0000 (see page 1064) COUNT PWM0CMPA, type R/W, offset 0x058, reset 0x0000.0000 (see page 1065) COMPA PWM1CMPA, type R/W, offset 0x098, reset 0x0000.0000 (see page 1065) COMPA PWM2CMPA, type R/W, offset 0x0D8, reset 0x0000.0000 (see page 1065) COMPA PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000 (see page 1066) COMPB PWM1CMPB, type R/W, offset 0x09C, reset 0x0000.0000 (see page 1066) COMPB PWM2CMPB, type R/W, offset 0x0DC, reset 0x0000.0000 (see page 1066) COMPB July 22, 2011 1255 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM0GENA, type R/W, offset 0x060, reset 0x0000.0000 (see page 1067) ACTCMPBD ACTCMPBU ACTCMPAD ACTCMPAU ACTLOAD ACTZERO ACTCMPAD ACTCMPAU ACTLOAD ACTZERO ACTCMPAD ACTCMPAU ACTLOAD ACTZERO ACTCMPAD ACTCMPAU ACTLOAD ACTZERO ACTCMPAD ACTCMPAU ACTLOAD ACTZERO ACTCMPAD ACTCMPAU ACTLOAD ACTZERO PWM1GENA, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 1067) ACTCMPBD ACTCMPBU PWM2GENA, type R/W, offset 0x0E0, reset 0x0000.0000 (see page 1067) ACTCMPBD ACTCMPBU PWM0GENB, type R/W, offset 0x064, reset 0x0000.0000 (see page 1070) ACTCMPBD ACTCMPBU PWM1GENB, type R/W, offset 0x0A4, reset 0x0000.0000 (see page 1070) ACTCMPBD ACTCMPBU PWM2GENB, type R/W, offset 0x0E4, reset 0x0000.0000 (see page 1070) ACTCMPBD ACTCMPBU PWM0DBCTL, type R/W, offset 0x068, reset 0x0000.0000 (see page 1073) ENABLE PWM1DBCTL, type R/W, offset 0x0A8, reset 0x0000.0000 (see page 1073) ENABLE PWM2DBCTL, type R/W, offset 0x0E8, reset 0x0000.0000 (see page 1073) ENABLE PWM0DBRISE, type R/W, offset 0x06C, reset 0x0000.0000 (see page 1074) RISEDELAY PWM1DBRISE, type R/W, offset 0x0AC, reset 0x0000.0000 (see page 1074) RISEDELAY PWM2DBRISE, type R/W, offset 0x0EC, reset 0x0000.0000 (see page 1074) RISEDELAY PWM0DBFALL, type R/W, offset 0x070, reset 0x0000.0000 (see page 1075) FALLDELAY PWM1DBFALL, type R/W, offset 0x0B0, reset 0x0000.0000 (see page 1075) FALLDELAY PWM2DBFALL, type R/W, offset 0x0F0, reset 0x0000.0000 (see page 1075) FALLDELAY PWM0FLTSRC0, type R/W, offset 0x074, reset 0x0000.0000 (see page 1076) FAULT3 FAULT2 FAULT1 FAULT0 FAULT3 FAULT2 FAULT1 FAULT0 PWM1FLTSRC0, type R/W, offset 0x0B4, reset 0x0000.0000 (see page 1076) 1256 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FAULT3 FAULT2 FAULT1 FAULT0 PWM2FLTSRC0, type R/W, offset 0x0F4, reset 0x0000.0000 (see page 1076) PWM0FLTSRC1, type R/W, offset 0x078, reset 0x0000.0000 (see page 1078) DCMP7 DCMP6 DCMP5 DCMP4 DCMP3 DCMP2 DCMP1 DCMP0 DCMP7 DCMP6 DCMP5 DCMP4 DCMP3 DCMP2 DCMP1 DCMP0 DCMP7 DCMP6 DCMP5 DCMP4 DCMP3 DCMP2 DCMP1 DCMP0 FAULT3 FAULT2 FAULT1 FAULT0 FAULT3 FAULT2 FAULT1 FAULT0 FAULT3 FAULT2 FAULT1 FAULT0 FAULT3 FAULT2 FAULT1 FAULT0 FAULT3 FAULT2 FAULT1 FAULT0 FAULT3 FAULT2 FAULT1 FAULT0 FAULT3 FAULT2 FAULT1 FAULT0 PWM1FLTSRC1, type R/W, offset 0x0B8, reset 0x0000.0000 (see page 1078) PWM2FLTSRC1, type R/W, offset 0x0F8, reset 0x0000.0000 (see page 1078) PWM0MINFLTPER, type R/W, offset 0x07C, reset 0x0000.0000 (see page 1081) MFP PWM1MINFLTPER, type R/W, offset 0x0BC, reset 0x0000.0000 (see page 1081) MFP PWM2MINFLTPER, type R/W, offset 0x0FC, reset 0x0000.0000 (see page 1081) MFP PWM0FLTSEN, type R/W, offset 0x800, reset 0x0000.0000 (see page 1082) PWM1FLTSEN, type R/W, offset 0x880, reset 0x0000.0000 (see page 1082) PWM2FLTSEN, type R/W, offset 0x900, reset 0x0000.0000 (see page 1082) PWM3FLTSEN, type R/W, offset 0x980, reset 0x0000.0000 (see page 1082) PWM0FLTSTAT0, type -, offset 0x804, reset 0x0000.0000 (see page 1083) PWM1FLTSTAT0, type -, offset 0x884, reset 0x0000.0000 (see page 1083) PWM2FLTSTAT0, type -, offset 0x904, reset 0x0000.0000 (see page 1083) PWM0FLTSTAT1, type -, offset 0x808, reset 0x0000.0000 (see page 1085) DCMP7 DCMP6 DCMP5 DCMP4 DCMP3 DCMP2 DCMP1 DCMP0 DCMP7 DCMP6 DCMP5 DCMP4 DCMP3 DCMP2 DCMP1 DCMP0 DCMP7 DCMP6 DCMP5 DCMP4 DCMP3 DCMP2 DCMP1 DCMP0 PWM1FLTSTAT1, type -, offset 0x888, reset 0x0000.0000 (see page 1085) PWM2FLTSTAT1, type -, offset 0x908, reset 0x0000.0000 (see page 1085) July 22, 2011 1257 Texas Instruments-Production Data Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWAP ENABLE DIRECTION ERROR Quadrature Encoder Interface (QEI) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 QEICTL, type R/W, offset 0x000, reset 0x0000.0000 (see page 1095) FILTCNT FILTEN STALLEN INVI INVB INVA VELDIV VELEN RESMODE CAPMODE SIGMODE QEISTAT, type RO, offset 0x004, reset 0x0000.0000 (see page 1098) QEIPOS, type R/W, offset 0x008, reset 0x0000.0000 (see page 1099) POSITION POSITION QEIMAXPOS, type R/W, offset 0x00C, reset 0x0000.0000 (see page 1100) MAXPOS MAXPOS QEILOAD, type R/W, offset 0x010, reset 0x0000.0000 (see page 1101) LOAD LOAD QEITIME, type RO, offset 0x014, reset 0x0000.0000 (see page 1102) TIME TIME QEICOUNT, type RO, offset 0x018, reset 0x0000.0000 (see page 1103) COUNT COUNT QEISPEED, type RO, offset 0x01C, reset 0x0000.0000 (see page 1104) SPEED SPEED QEIINTEN, type R/W, offset 0x020, reset 0x0000.0000 (see page 1105) INTERROR INTDIR INTTIMER INTINDEX INTERROR INTDIR INTTIMER INTINDEX INTERROR INTDIR INTTIMER INTINDEX QEIRIS, type RO, offset 0x024, reset 0x0000.0000 (see page 1107) QEIISC, type R/W1C, offset 0x028, reset 0x0000.0000 (see page 1109) 1258 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller B Ordering and Contact Information B.1 Ordering Information LM3Snnnn–gppss–rrm Part Number nnn = Sandstorm-class parts nnnn = All other Stellaris® parts Shipping Medium T = Tape-and-reel Omitted = Default shipping (tray or tube) Temperature E = –40°C to +105°C I = –40°C to +85°C Revision Speed 20 = 20 MHz 25 = 25 MHz 50 = 50 MHz 80 = 80 MHz Package BZ = 108-ball BGA QC = 100-pin LQFP QN = 48-pin LQFP QR = 64-pin LQFP GZ = 48-pin QFN Table B-1. Part Ordering Information B.2 Orderable Part Number Description LM3S9L71-IQC80-C5 Stellaris LM3S9L71 Microcontroller Industrial Temperature 100-pin LQFP LM3S9L71-IBZ80-C5 Stellaris LM3S9L71 Microcontroller Industrial Temperature 108-ball BGA LM3S9L71-IQC80-C5T Stellaris LM3S9L71 Microcontroller Industrial Temperature 100-pin LQFP Tape-and-reel LM3S9L71-IBZ80-C5T Stellaris LM3S9L71 Microcontroller Industrial Temperature 108-ball BGA Tape-and-reel ® Part Markings The Stellaris microcontrollers are marked with an identifying number. This code contains the following information: ■ The first line indicates the part number. In the example figure below, this is the LM3S9B90. ■ In the second line, the first seven characters indicate the temperature, package, speed, and revision. In the example below, this is an Industrial temperature (I), 100-pin LQFP package (QC), 80-MHz (80), revision C0 (C0) device. ■ The remaining characters contain internal tracking numbers. July 22, 2011 1259 Texas Instruments-Production Data Ordering and Contact Information B.3 Kits The Stellaris Family provides the hardware and software tools that engineers need to begin development quickly. ■ Reference Design Kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files ■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers before purchase ■ Development Kits provide you with all the tools you need to develop and prototype embedded applications right out of the box See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor. B.4 Support Information For support on Stellaris products, contact the TI Worldwide Product Information Center nearest you: http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm. 1260 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller C Package Information C.1 100-Pin LQFP Package C.1.1 Package Dimensions Figure C-1. 100-Pin LQFP Package Dimensions Note: The following notes apply to the package drawing. 1. All dimensions shown in mm. 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane. July 22, 2011 1261 Texas Instruments-Production Data Package Information Body +2.00 mm Footprint, 1.4 mm package thickness Symbols Leads 100L A Max. 1.60 A1 - 0.05 Min./0.15 Max. A2 ±0.05 1.40 D ±0.20 16.00 D1 ±0.05 14.00 E ±0.20 16.00 E1 ±0.05 14.00 L +0.15/-0.10 0.60 e Basic 0.50 b +0.05 0.22 θ - 0˚-7˚ ddd Max. 0.08 ccc Max. 0.08 JEDEC Reference Drawing MS-026 Variation Designator BED 1262 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller C.1.2 Tray Dimensions Figure C-2. 100-Pin LQFP Tray Dimensions C.1.3 Tape and Reel Dimensions Note: In the figure that follows, pin 1 is located in the top right corner of the device. July 22, 2011 1263 Texas Instruments-Production Data Package Information Figure C-3. 100-Pin LQFP Tape and Reel Dimensions THIS IS A COMPUTER GENERATED UNCONTROLLED DOCUMENT PRINTED ON 06.01.2003 06.01.2003 06.01.2003 MUST NOT BE REPRODUCED WITHOUT WRITTEN PERMISSION FROM SUMICARRIER (S) PTE LTD 06.01.2003 06.01.2003 1264 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller C.2 108-Ball BGA Package C.2.1 Package Dimensions Figure C-4. 108-Ball BGA Package Dimensions July 22, 2011 1265 Texas Instruments-Production Data Package Information Note: The following notes apply to the package drawing. Symbols MIN NOM MAX A 1.22 1.36 1.50 A1 0.29 0.34 0.39 A3 0.65 0.70 0.75 c 0.28 0.32 0.36 D 9.85 10.00 10.15 D1 E 8.80 BSC 9.85 E1 b 10.00 8.80 BSC 0.43 0.48 bbb 0.53 .20 ddd .12 e 0.80 BSC f 10.15 - 0.60 M 12 n 108 - REF: JEDEC MO-219F 1266 July 22, 2011 Texas Instruments-Production Data ® Stellaris LM3S9L71 Microcontroller C.2.2 Tray Dimensions Figure C-5. 108-Ball BGA Tray Dimensions July 22, 2011 1267 Texas Instruments-Production Data Package Information C.2.3 Tape and Reel Dimensions Figure C-6. 108-Ball BGA Tape and Reel Dimensions C-PAK PTE LTD 1268 July 22, 2011 Texas Instruments-Production Data PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) LM3S9L71-IBZ80-C1 PREVIEW NFBGA ZCR 108 TBD Call TI Call TI LM3S9L71-IBZ80-C1T PREVIEW NFBGA ZCR 108 TBD Call TI Call TI LM3S9L71-IBZ80-C3 ACTIVE NFBGA ZCR 108 184 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR LM3S9L71-IBZ80-C3T ACTIVE NFBGA ZCR 108 1500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR LM3S9L71-IBZ80-C5 ACTIVE NFBGA ZCR 108 184 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR LM3S9L71-IBZ80-C5T ACTIVE NFBGA ZCR 108 1500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR LM3S9L71-IQC80-C0 PREVIEW LQFP PZ 100 TBD Call TI Call TI LM3S9L71-IQC80-C0T PREVIEW LQFP PZ 100 TBD Call TI Call TI LM3S9L71-IQC80-C1 PREVIEW LQFP PZ 100 TBD Call TI Call TI LM3S9L71-IQC80-C1T PREVIEW LQFP PZ 100 TBD Call TI Call TI LM3S9L71-IQC80-C3 ACTIVE LQFP PZ 100 90 LM3S9L71-IQC80-C3T ACTIVE LQFP PZ 100 1000 TBD LM3S9L71-IQC80-C5 ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) Level-3-260C-168 HR LM3S9L71-IQC80-C5T ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) Level-3-260C-168 HR Green (RoHS & no Sb/Br) Samples Level-3-260C-168 HR Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2011 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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