LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
LM4846
Output Capacitor-less Audio Subsystem with
Programmable National 3D
Check for Samples: LM4846
FEATURES
1
•
•
•
2
•
•
•
•
I2C/SPI Control Interface
I2C/SPI programmable National 3D Audio
I2C/SPI controlled 32 step digital volume
control (-54dB to +18dB)
Three independent volume channels (Left,
Right, Mono)
Eight distinct output modes
micro SMD surface mount packaging
“Click and Pop” suppression circuitry
•
•
Thermal shutdown protection
Low shutdown current (0.1µA, typ)
APPLICATIONS
•
•
Mobile Phones
PDAs
DESCRIPTION
The LM4846 is an audio power amplifier capable of delivering 500mW of continuous average power into a mono
8Ω bridged-tied load (BTL) with 1% THD+N, 25mW per channel of continuous average power into stereo 32Ω
single-ended (SE) loads with 1% THD+N, or an output capacitor-less (OCL) configuration with identical
specification as the SE configuration, from a 3.3V power supply.
The LM4846 features a 32-step digital volume control and eight distinct output modes. The digital volume control,
3D enhancement, and output modes (mono/SE/OCL) are programmed through a two-wire I2C or a three-wire SPI
compatible interface that allows flexibility in routing and mixing audio channels. The LM4846 has three input
channels: one pair for a two-channel stereo signal and the third for a single-channel mono input.
The LM4846 is designed for cellular phone, PDA, and other portable handheld applications. It delivers high
quality output power from a surface-mount package and requires only seven external components in the OCL
mode (two additional components in SE mode).
Table 1. Key Specifications
VALUE
THD+N at 1kHz, 500mW
into 8Ω BTL (3.3V)
UNIT
1.0% (typ)
THD+N at 1kHz, 30mW into 32Ω SE (3.3V)
1.0% (typ)
Single Supply Operation (VDD)
2.7 to 5.5
V
I2C/SPI Single Supply Operation
2.2 to 5.5
V
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Typical Application
VDD
CS
+
1 PF
AUDIO
INPUT
Handsfree
Speaker
CIN3
Mono+
Phone In
+
Volume Control
-54 dB to +18 dB
6 dB
AUDIO
INPUT
8:
Mono-
0.22 PF
ROUT
CIN2
RIN
+
Volume Control
-54 dB to +18 dB
Mixer &
Output
Mode
Select
0 dB
32:
0.22 PF
AUDIO
INPUT
0 dB
National
3D
LOUT
CIN1
LIN
+
Volume Control
-54 dB to +18 dB
32:
0 dB
0.22 PF
2
I CSPI_VDD
Bypass
I CSPI_SEL
LHP3D2
LHP3D1
2
C3DL
+
Bias
ID_ENB
RHP3D2
SCL
CB
2
I C/SPI
Interface
RHP3D1
SDA
2.2 PF
C3DR
Figure 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less
2
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
VDD
CS
+
1 PF
AUDIO
INPUT
Handsfree
Speaker
CIN3
MONO+
Phone In
+
Volume Control
-54 dB to +18 dB
6 dB
0.22 PF
8:
MONOCO
RIN
+
Volume Control
-54 dB to +18 dB
0.22 PF
AUDIO
INPUT
Mixer &
Output
Mode
Select
32:
100 PF
National
3D
0 dB
CIN1
LIN
ROUT
0 dB
+
CIN2
CO
+
Volume Control
-54 dB to +18 dB
LOUT
0 dB
32:
+
AUDIO
INPUT
100 PF
0.22 PF
2
I CSPI_VDD
Bypass
C3DL
2.2 PF
RHP3D2
I CSPI_SEL
RHP3D1
2
+
Bias
LHP3D2
SCL
ID_ENB
CB
2
I C/SPI
Interface
LHP3D1
SDA
C3DR
Figure 2. Typical Audio Amplifier Application Circuit-Single Ended
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
3
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Connection Diagram
A
B
C
D
E
5
VOC
NC
GND
ROUT
LOUT
4
RHP3D1
MONO_IN
VDD
RIN
LIN
3
RHP3D2
ID_ENB
VDD
LHP3D1
LHP3D2
2
I2CSPI_VDD
SCL
VDD
NC
CBYPASS
1
SDA
MONO-
GND
MONO+
I2CSPI_SEL
Figure 3. 25-Bump micro SMD - Top View
XYTT
GG5
Bump A1
Figure 4. Top View
XY - Date Code
TT - Die Traceability
G - Boomer Family
G5 - LM4846TL
Table 2. Pin Descriptions
1
4
Bump
Name
A1
SDA
Description
I2C or SPI Data
2
I2C or SPI Interface Power
Supply
2
A2
I CSPI_VDD
3
A3
RHP3D2
Right Headphone 3D Input 2
4
A4
RHP3D1
Right Headphone 3D Input 1
5
A5
VOC
6
B1
MONO-
Submit Documentation Feedback
Center Amplifier Output
Loudspeaker Negative Output
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Table 2. Pin Descriptions (continued)
Bump
Name
7
B2
SCL
8
B3
ID_ENB
9
B4
Phone_In
Mono Input
10
B5
NC
No Connect
11
C1
GND
Ground
12
C2
VDD
Power Supply
13
C3
VDD
Power Supply
14
C4
VDD
Power Supply
15
C5
GND
GND
16
D1
MONO+
17
D2
NC
18
D3
LHP3D1
19
D4
RIN
20
D5
ROUT
2
21
E1
I C SPI_SEL
22
E2
CBYPASS
23
E3
LHP3D2
24
E4
LIN
25
E5
LOUT
Description
I2C or SPI Clock
Address Identification/Enable Bar
Loudspeaker Positive Output
No Connect
Left Headphone 3D Input 1
Right Input Channel
Right Headphone Output
I2C or SPI Select
Half-Supply Bypass
Left Headphone 3D Input 2
Left Input Channel
Left Headphone Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
Supply Voltage
6.0V
Storage Temperature
−65°C to +150°C
Input Voltage
−0.3 to VDD +0.3
ESD Susceptibility
(2)
ESD Machine model
2.0kV
(3)
200V
Junction Temperature (TJ)
Solder Information
150°C
(4)
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
Thermal Resistance
θJA (typ) - TLA25CBA
(1)
(2)
(3)
(4)
(5)
65°C/W
(5)
Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For
guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test
conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then
discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).
See AN-450 "Surface Mounting and their effects on Product Reliability" for other methods of soldering surface mount devices.
The given θJA for an LM4846ITL mounted on a demonstration board with a 9in2 area of 1oz printed circuit board copper ground plane.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
5
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Operating Ratings
www.ti.com
(1)
−40°C to 85°C
Temperature Range
Supply Voltage (VDD)
2.7V ≤ VDD ≤ 5.5V
Supply Voltage (I2C/SPI)
2.2V ≤ VDD ≤ 5.5V
(1)
6
Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For
guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test
conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Electrical Characteristics 3.3V
(1) (2)
The following specifications apply for VDD = 3.3V, TA = 25°C unless otherwise specified. [AV = 2 (BTL), AV = 1 (SE)]
Symbol
Parameter
Conditions
LM4846
Typical
IDD
Supply Current
Output Modes 2, 4, 6
VIN = 0V; No load,
OCL = 0 (Table 2)
Output Modes 1, 3, 5, 7
VIN = 0V; No load, BTL,
OCL = 0 (Table 2)
(3)
Limits
(4)
Units
(Limits)
mA (max)
3.3
6.5
6
11
mA (max)
ISD
Shutdown Current
Output Mode 0
0.1
1
µA (max)
VOS
Output Offset Voltage
VIN = 0V, Mode 5 (Note 10)
10
50
mV (max)
MONO OUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
500
400
mW (min)
ROUT and LOUT; RL = 32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4
42
20
mW (min)
MONOOUT
f = 20Hz to 20kHz
POUT = 250mW; RL = 8Ω, BTL, Mode
1
0.5
%
ROUT and LOUT
f = 20Hz to 20kHz
POUT = 12mW; RL = 32Ω, SE, Mode 4
0.5
%
26
µV
Output Mode 1,7
71
dB
Output Mode 3
68
dB
Output Mode 5
63
dB
Output Mode 2
88
dB
Output Mode 4
76
dB
Output Mode 6, 7
76
dB
Input referred maximum attenuation
-54
–53.25
–54.75
dB (min)
dB (max)
Input referred maximum gain
18
17.25
18.75
dB (min)
dB (max)
Output Mode 1, 3, 5
80
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
PO
Output Power
THD+N
NOUT
Total Harmonic Distortion
Plus Noise
Output Noise
Power Supply Rejection
Ratio
MONOOUT
PSRR
Power Supply Rejection
Ratio
ROUT and LOUT
Digital Volume Range
(RIN and LIN)
Mute Attenuation
TWU
(1)
(2)
(3)
(4)
A-weighted (Note 9), Mode 5, BTL
input referred
VRIPPLE = 200mVPP; f = 217Hz,
CB = 2.2µF, BTL
All audio inputs terminated into 50Ω;
output referred gain = 6dB (BTL)
VRIPPLE = 200mVPP; f = 217Hz
CB = 2.2µF, SE, CO = 100μF
All audio inputs terminated into 50Ω;
output referred gain,
OCL = 0 (Table 2)
dB
MONO_IN Input Impedance Maximum gain setting
RIN and LIN Input
Impedance
Maximum attenuation setting
11
8
14
100
75
125
Wake-Up Time from
Shutdown
90
138
CB = 2.2μF, OCL
CB = 2.2μF, SE
ms
Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For
guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test
conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to the ground pin, unless otherwise specified.
Typical specifications are specified at +25°C and represent the most likely parametric norm.
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
7
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Electrical Characteristics 5.0V
www.ti.com
(1) (2)
The following specifications apply for VDD = 5.0V, TA = 25°C unless otherwise specified. [AV = 2 (BTL), AV = 1 (SE)].
Symbol
Parameter
Conditions
LM4846
Typical
IDD
Supply Current
Output Modes 2, 4, 6
VIN = 0V; No load,
OCL = 0 (Table 2)
3.6
Output Modes 1, 3, 5, 7
VIN = 0V; No Load,
OCL = 0 (Table 2)
6.8
Output Mode 0
0.1
VOS
Output Offset Voltage
VIN = 0V, Mode 5 (Note 10)
THD+N
NOUT
Total Harmonic Distortion
Plus Noise
Output Noise
Power Supply Rejection
Ratio
MONOOUT
PSRR
Power Supply Rejection
Ratio
ROUT and LOUT
Digital Volume Range
(RIN and LIN)
Mute Attenuation
TWU
(1)
(2)
(3)
(4)
(5)
(6)
8
Units
(Limits)
mA
Shutdown Current
Output Power
Limits
(4) (5)
mA
ISD
PO
(3)
.5
µA
10
mV
MONOOUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
1.15
W
ROUT and LOUT; RL = 32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4
75
mW
MONOOUT
f = 20Hz to 20kHz
POUT = 500mW; RL = 8Ω, BTL, Mode 1
0.5
%
ROUT and LOUT
f = 20Hz to 20kHz
POUT = 30mW; RL = 32Ω,SE, Mode 4
0.5
%
A-weighted (6), Mode 5, BTL
input referred
26
µV
Output Mode 1, 7
71
dB
Output Mode 3
68
dB
Output Mode 5
63
dB
Output Mode 2
88
dB
Output Mode 4
76
dB
Output Mode 6, 7
76
VRIPPLE = 200mVPP; f = 217Hz,
CB = 2.2µF, BTL
All audio inputs terminated into 50Ω;
output referred gain = 6dB (BTL)
VRIPPLE = 200mVPP; f = 217Hz,
CB = 2.2µF, SE, CO = 100μF
All audio inputs terminated into 50Ω;
output referred gain,
OCL = 0 (Table 2)
dB
Input referred maximum attenuation
-54
–53.25
–54.75
dB
dB
Input referred maximum gain
18
17.25
18.75
dB
dB
Output Mode 1, 3, 5
80
dB
MONO_IN Input Impedance Maximum gain setting
RIN and LIN Input
Impedance
Minimum gain setting
11
kΩ
kΩ
100
kΩ
kΩ
Wake-Up Time from
Shutdown
122
184
ms
CB = 2.2μF, OCL
CB = 2.2μF, SE
Human body model, 100pF discharged through a 1.5kΩ resistor.
All voltages are measured with respect to the ground pin, unless otherwise specified.
Typical specifications are specified at +25°C and represent the most likely parametric norm.
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Potentially worse case: All three input stages are DC coupled to the BTL output stage.
Datasheet min/max specifications are guaranteed by design, test, or statistical analysis.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
I2C/SPI
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
(1) (2)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C unless otherwise specified.
Symbol
Parameter
Conditions
LM4846
Typical
(3)
Limits
(4) (5)
Units
(Limits)
t1
I2C Clock Period
2.5
µs (max)
t2
I2C Clock Setup Time
100
ns (min)
t3
I2C Data Hold Time
100
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
fSPI
Maximum SPI Frequency
1000
kHz (max)
tEL
SPI ENB Low Time
100
ns (min)
tDS
SPI Data Setup Time
100
µs (max)
tES
SPI ENB Setup Time
100
ns (min)
tDH
SPI Data Hold Time
100
ns (min)
tEH
SPI Enable Hold Time
100
ns (min)
tCL
SPI Clock Low Time
500
ns (min)
tCH
SPI Clock High Time
500
ns (min)
tCS
SPI Clock Transition Time
100
ns (min)
VIH
I2C/SPI Input Voltage High
0.7xI2CSPI
VDD
V (min)
VIL
I2C/SPI Input Voltage Low
0.3xI2CSPI
VDD
V (max)
(1)
(2)
(3)
(4)
(5)
Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For
guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test
conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to the ground pin, unless otherwise specified.
Typical specifications are specified at +25°C and represent the most likely parametric norm.
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Potentially worse case: All three input stages are DC coupled to the BTL output stage.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
9
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Typical Performance Characteristics
10
1
1
0.1
1k
0.01
20
10k 20k
100
1k
10k 20k
FREQUENCY (Hz)
THD+N
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 6, OCL
THD+N
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 4, SE
10
10
1
1
THD + N (%)
THD + N (%)
100
0.1
FREQUENCY (Hz)
0.1
0.01
20
THD + N (%)
THD + N (%)
10
0.01
20
100
1k
0.1
0.01
20
10k 20k
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
THD+N
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 6, SE
THD+N
vs
Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
Mode 5
10
10
1
1
0.1
0.01
20
100
1k
10k 20k
FREQUENCY (Hz)
10
THD+N
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 4, OCL
THD + N (%)
THD + N (%)
THD+N
vs
Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
Mode 1, BTL
0.1
0.01
20
100
1k
10k 20k
FREQUENCY (Hz)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Typical Performance Characteristics (continued)
10
1
1
THD + N (%)
10
0.1
100
1k
0.1
0.01
20
10k 20k
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
THD+N
vs
Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 4, SE
THD+N
vs
Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 6, OCL
10
10
1
1
THD + N (%)
THD + N (%)
0.01
20
0.1
0.01
20
THD + N (%)
THD+N
vs
Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 4, OCL
100
1k
0.1
0.01
20
10k 20k
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
THD+N
vs
Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 6, SE
THD+N
vs
Frequency
VDD = 5V, RL = 8Ω, PO = 500mW
Mode 5
10
10
1
1
THD + N (%)
THD + N (%)
THD+N
vs
Frequency
VDD = 5V, RL = 8Ω, PO = 500mW
Mode 1, BTL
0.1
0.01
20
0.1
0.01
100
1k
10k 20k
FREQUENCY (Hz)
20
100
1k
10k 20k
FREQUENCY (Hz)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
11
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Typical Performance Characteristics (continued)
THD+N
vs
Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
Mode 1, BTL
THD+N
vs
Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
Mode 5, BTL
10
1
1
THD + N (%)
THD + N (%)
10
0.1
0.1
0.01
10m
100m
0.01
10m
1
1
OUTPUT POWER (W)
OUTPUT POWER (W)
THD+N
vs
Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 4, OCL
THD+N
vs
Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 4, SE
10
1
1
THD + N (%)
THD + N (%)
10
0.1
0.1
0.01
10m
0.01
10m
100m
100m
OUTPUT POWER (W)
OUTPUT POWER (W)
THD+N
vs
Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 6, OCL
THD+N
vs
Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 6, SE
10
1
1
THD + N (%)
THD + N (%)
10
0.1
0.1
0.01
10m
100m
OUTPUT POWER (W)
12
100m
0.01
10m
100m
OUTPUT POWER (W)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Typical Performance Characteristics (continued)
THD+N
vs
Output Power
VDD = 5V, RL = 8Ω, f = 1kHz
Mode 1, BTL
THD+N
vs
Output Power
VDD = 5V, RL = 8Ω, f = 1kHz
Mode 5, BTL
10
1
1
THD + N (%)
THD + N (%)
10
0.1
0.1
0.01
20m
200m
0.01
20m
2
OUTPUT POWER (W)
200m
2
OUTPUT POWER (W)
THD+N
vs
Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 4, OCL
THD+N
vs
Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 4, SE
10
1
1
THD + N (%)
THD + N (%)
10
0.1
0.1
0.01
10m
0.01
100m
10m
100m
OUTPUT POWER (W)
OUTPUT POWER (W)
THD+N
vs
Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 6, OCL
THD+N
vs
Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 6, SE
10
1
1
THD + N (%)
THD + N (%)
10
0.1
0.1
0.01
0.01
10m
100m
10m
100m
OUTPUT POWER (W)
OUTPUT POWER (W)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
13
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Typical Performance Characteristics (continued)
PSRR
vs
Frequency
VDD = 3.3V, 0dB
Mode 4, SE
POWER SUPPLY REJECTION RATIO (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
200
2k
20k
-60
-70
-80
-90
-100
20
200
2k
PSRR
vs
Frequency
VDD = 3.3V, 0dB
Mode 6, SE
POWER SUPPLY REJECTION RATIO (dB)
-20
-30
-40
-50
-60
-70
-80
-90
200
2k
20k
0
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
200
2k
FREQUENCY (Hz)
PSRR
vs
Frequency
VDD = 3.3V, 6dB
Mode 1, BTL
PSRR
vs
Frequency
VDD = 3.3V, 6dB
Mode 5, BTL
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
200
2k
20k
20k
-10
FREQUENCY (Hz)
20k
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
200
2k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
14
-40
-50
PSRR
vs
Frequency
VDD = 3.3V, 0dB
Mode 6, OCL
0
-100
20
-20
-30
FREQUENCY (Hz)
-10
-100
20
0
-10
FREQUENCY (Hz)
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
PSRR
vs
Frequency
VDD = 3.3V, 0dB
Mode 4, OCL
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Typical Performance Characteristics (continued)
100
Noise
VDD = 3.3V, Mode 4, OCL
100
90
90
80
80
70
NOISE (PV)
NOISE (PV)
70
60
50
40
30
20
10
10
200
2k
0
20
20k
Noise
VDD = 3.3V, Mode 5, BTL
100
90
80
70
NOISE (PV)
60
50
40
60
50
40
30
30
20
20
10
10
200
2k
0
20
20k
200
2k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Noise
VDD = 3.3V, Mode 1, BTL
Power Dissipation
vs
Output Power
VDD = 3.3V, RL = 8Ω
f = 1kHz, Mode 1, BTL
350
POWER DISSIPATION (mW)
90
80
70
60
50
40
30
20
300
250
200
150
100
50
10
0
20
20k
Noise
VDD = 3.3V, Mode 6, SE
80
100
2k
FREQUENCY (Hz)
90
0
20
200
FREQUENCY (Hz)
70
NOISE (PV)
50
40
30
100
NOISE (PV)
60
20
0
20
Noise
VDD = 3.3V, Mode 4, SE
0
200
2k
20k
FREQUENCY (Hz)
0
100
200
300
400
500
600
OUTPUT POWER (mW)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
15
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Typical Performance Characteristics (continued)
Power Dissipation
vs
Output Power
VDD = 3.3V, RL = 8Ω
f = 1kHz, BTL, Mode 5
Power Dissipation
vs
Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, OCL, Mode 4
60
300
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
350
250
200
150
100
50
0
50
40
30
20
10
0
0
100
200
300
400
500
600
0
2
OUTPUT POWER (mW)
10
12
60
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
8
Power Dissipation
vs
Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, SE, Mode 4
25
20
15
10
5
50
40
30
20
10
0
0
0
10
20
30
40
50
0
2
4
6
8
10
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Power Dissipation
vs
Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, SE, Mode 6
Power Dissipation
vs
Output Power
VDD = 5V, RL = 8Ω
f = 1kHz, BTL, Mode 1
30
700
25
600
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
6
OUTPUT POWER (mW)
Power Dissipation
vs
Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, OCL, Mode 6
20
15
10
5
12
500
400
300
200
100
0
0
0
10
20
30
40
50
OUTPUT POWER (mW)
16
4
0
0.5
1.0
1.5
OUTPUT POWER (mW)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Typical Performance Characteristics (continued)
Power Dissipation
vs
Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, OCL, Mode 4
700
700
600
600
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
Power Dissipation
vs
Output Power
VDD = 5V, RL = 8Ω
f = 1kHz, BTL, Mode 5
500
400
300
200
100
0
0.5
0
1.0
400
300
200
100
0
1.5
0
0.5
1.0
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Power Dissipation
vs
Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, OCL, Mode 6
Power Dissipation
vs
Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, SE, Mode 4
450
1.5
140
POWER DISSIPATION (mW)
400
POWER DISSIPATION (mW)
500
350
300
250
200
150
100
50
0
120
100
80
60
40
20
0
0
20
40
60
80
0
100
5
10
15
20
25
30
35
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Power Dissipation
vs
Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, SE, Mode 6
Crosstalk
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Right-Left, OCL, Mode 4
60
0
50
-20
CROSSTALK (dB)
POWER DISSIPATION (mW)
-10
40
30
20
-30
-40
-50
-60
-70
-80
10
-90
0
0
2
4
6
8
10
-100
20
12
200
2k
20k
FREQUENCY (Hz)
OUTPUT POWER (mW)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
17
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Typical Performance Characteristics (continued)
Crosstalk
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Right-Left, SE, Mode 4
0
0
-10
-10
-20
-20
-30
CROSSTALK (dB)
CROSSTALK (dB)
Crosstalk
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Right-Left, OCL, Mode 6
-40
-50
-60
-70
-30
-40
-50
-60
-70
-80
-80
-90
-90
-100
20
-100
200
2k
20k
20
0
450
-10
400
-20
350
-30
300
-40
IDD (mA)
CROSSTALK (dB)
Crosstalk
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Right-Left, SE, Mode 6
-50
-60
Supply Current
vs
Supply Voltage
RL = 8Ω, Mode 1
250
200
50
-90
20
200
2k
0
20k
3
4
Supply Current
vs
Supply Voltage
RL = 8Ω, Mode 5
0
6
Supply Current
vs
Supply Voltage
RL = 32Ω, OCL, Mode 4
90
-10
80
-20
70
-30
60
-40
IDD (mA)
CROSSTALK (dB)
5
VDD (V)
FREQUENCY (Hz)
-50
-60
50
40
30
-70
20
-80
10
-90
20
200
2k
20k
0
b
4
5
6
VDD (V)
FREQUENCY (Hz)
18
20k
100
-80
-100
2k
150
-70
-100
200
FREQUENCY (Hz)
FREQUENCY (Hz)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Typical Performance Characteristics (continued)
Supply Current
vs
Supply Voltage
RL = 32Ω, OCL, Mode 6
90
Supply Current
vs
Supply Voltage
RL = 32Ω, SE, Mode 4
60
80
50
70
40
IDD (mA)
IDD (mA)
60
50
40
30
30
20
20
10
10
0
0
3
4
5
6
3
4
VDD (V)
Supply Current
vs
Supply Voltage
RL = 32Ω, SE, Mode 6
60
1.4
OUTPUT POWER (W)
40
IDD (mA)
6
Output Power
vs
Supply Voltage
RL = 8Ω, Mode 1
1.6
50
30
20
10
1.2
1.0
0.8
0.6
0.4
0.2
0
0
3
4
5
3
6
4
Output Power
vs
Supply Voltage
RL = 8Ω, Mode 5
1.6
5
6
VDD (V)
VDD (V)
Output Power
vs
Supply Voltage
RL = 32Ω, Mode 4
90
1.4
80
1.2
70
OUTPUT POWER (mW)
OUTPUT POWER (W)
5
VDD (V)
1.0
0.8
0.6
0.4
0.2
60
50
40
30
20
10
0
0
3
4
5
6
3
VDD (V)
4
5
6
VDD (V)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
19
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Typical Performance Characteristics (continued)
Output Power
vs
Supply Voltage
RL = 32Ω, OCL, Mode 6
60
Output Power
vs
Supply Voltage
RL = 32Ω, SE, Mode 4
90
80
OUTPUT POWER (mW)
OUTPUT POWER (mW)
50
40
30
20
70
60
50
40
30
20
10
10
0
0
3
4
5
6
3
VDD (V)
4
5
6
VDD (V)
Output Power
vs
Supply Voltage
RL = 32Ω, SE, Mode 6
90
OUTPUT POWER (mW)
80
70
60
50
40
30
20
10
0
3
4
5
6
VDD (V)
Application Information
I2C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I2CSPI_SEL: This is tied LOW for I2C mode.
I2C COMPATIBLE INTERFACE
The LM4846 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4846.
The I2C address for the LM4846 is determined using the ID_ENB pin. The LM4846's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ENB is logic LOW; and X1 = 1, if ID_ENB is
logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4846's chip address can
be changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 3. The bus format diagram is broken up into six major
sections:
20
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will
alert all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is HIGH.
For I2C interface operation, the I2CSPI_SEL pin needs to be tied LOW (and tied high for SPI operation).
After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM4846 has received the address correctly, then it
holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock
pulse, then the master should abort the rest of the data transfer to the LM4846.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable HIGH.
After the data byte is sent, the master must check for another acknowledge to see if the LM4846 received the
data.
If the master has more data bytes to send to the LM4846, then the master can repeat the previous two steps
until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH.
The data line should be held HIGH when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM4846's I2C interface is powered up through the I2CVDD pin. The LM4846's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
Figure 5. I2C Bus Format
Figure 6. I2C Timing Diagram
SPI DESCRIPTION
0. I2CSPI_SEL: This pin is tied HIGH for SPI mode.
1. The data bits are transmitted with the MSB first.
2. The maximum clock rate is 1MHz for the CLK pin.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
21
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
3. CLK must remain HIGH for at least 500ns (tCH ) after the rising edge of CLK, and CLK must remain LOW for at
least 500ns (tCL) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 100ns
(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 100ns (tDH) after the rising
edge of CLK and stabilize before the next rising edge of CLK.
5.ID_ENB should be LOW only during serial data transmission.
6. ID_ENB must be LOW at least 100ns (tES ) before the first rising edge of CLK, and ID_ENB has to remain
LOW at least 100ns (tEH) after the eighth rising edge of CLK.
7. If ID_ENB remains HIGH for more than 100ns before all 8 bits are transmitted then the data latch will be
aborted.
8. If ID_ENB is LOW for more than 8 CLK pulses then only the first 8 data bits will be latched and activated when
ID_ENB transitions to logic-high.
9. ID_ENB must remain HIGH for at least 100ns (tEL ) to latch in the data.
10. Coincidental rising or falling edges of CLK and ID_ENB are not allowed. If CLK is to be held HIGH after the
data transmission, the falling edge of CLK must occur at least 100ns (tCS) before ID_ENB transitions to LOW for
the next set of data.
ID_ENB
tCS
tES
tCH
tCL
tEH
tEL
CLK
tDS
tDH
Data 7
DATA
Data 6
Data 1
Data 0
Figure 7. SPI Timing Diagram
Table 3. Chip Address
A7
A6
A5
A4
A3
A2
A1
A0
Chip Address
1
1
1
1
1
0
EC
0
ID_ENB = 0
1
1
1
1
1
0
0
0
ID_ENB = 1
1
1
1
1
1
0
1
0
Table 4. Control Registers
D7
D6
D5
D4
D3
D2
D1
D0
Mode Control
0
0
0
0
OCL
MC2
MC1
MC0
Programmable 3D
0
1
0
0
N3D3
N3D2
N3D1
N3D0
Mono Volume Control
1
0
0
MVC4
MVC3
MVC2
MVC1
MVC0
Left Volume Control
1
1
0
LVC4
LVC3
LVC2
LVC1
LVC0
Right Volume Control
1
1
1
RVC4
RVC3
RVC2
RVC1
RVC0
Table 5. Programmable National 3D Audio
22
N3D3
N3D2
Low
0
0
Medium
0
1
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Table 5. Programmable National 3D Audio (continued)
N3D3
N3D2
High
1
0
Maximum
1
1
Table 6. Output Mode Selection
Output
Mode
Number
MC2
MC1
MC0
Handsfree Speaker
Output
Right HP Output
Left HP Output
0
0
0
0
SD
SD
SD
1
0
0
1
2 x GP x P
MUTE
MUTE
2
0
1
0
SD
GP x P
GP x P
3
0
1
1
2 x (GL x L + GR x R)
MUTE
MUTE
4
1
0
0
SD
GR x R
GL x L
5
1
0
1
2 x (GL x L + GR x R + GP x
P)
MUTE
MUTE
6
1
1
0
SD
GR x R + GP x P
GL x L + GP x P
7
1
1
1
2 x (GR x R + GL x L)
GR x R
GL x L
Table 7. Volume Control Table
Volume Step
xVC4
xVC3
xVC2
xVC1
xVC0
Headphone
Gain, dB
Speaker Gain,
dB (BTL)
1
0
0
0
0
0
–54.00
–48.00
2
0
0
0
0
1
–46.50
–40.50
3
0
0
0
1
0
–40.50
–34.50
4
0
0
0
1
1
–34.50
–28.50
5
0
0
1
0
0
–30.00
–24.00
6
0
0
1
0
1
–27.00
–21.00
7
0
0
1
1
0
–24.00
–18.00
8
0
0
1
1
1
–21.00
–15.00
9
0
1
0
0
0
–18.00
–12.00
10
0
1
0
0
1
–15.00
–9.00
11
0
1
0
1
0
–13.50
–7.50
12
0
1
0
1
1
–12.00
–6.00
13
0
1
1
0
0
–10.50
–4.50
14
0
1
1
0
1
–9.00
–3.00
15
0
1
1
1
0
–7.50
–1.50
16
0
1
1
1
1
–6.00
0.00
17
1
0
0
0
0
–4.50
1.50
18
1
0
0
0
1
–3.00
3.00
19
1
0
0
1
0
–1.50
4.50
20
1
0
0
1
1
0.00
6.00
21
1
0
1
0
0
1.50
7.50
22
1
0
1
0
1
3.00
9.00
23
1
0
1
1
0
4.50
10.50
24
1
0
1
1
1
6.00
12.00
25
1
1
0
0
0
7.50
13.50
26
1
1
0
0
1
9.00
15.00
27
1
1
0
1
0
10.50
16.50
28
1
1
0
1
1
12.00
18.00
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
23
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Table 7. Volume Control Table (continued)
Volume Step
xVC4
xVC3
xVC2
xVC1
xVC0
Headphone
Gain, dB
Speaker Gain,
dB (BTL)
29
1
1
1
0
0
13.50
19.50
30
1
1
1
0
1
15.00
21.00
31
1
1
1
1
0
16.50
22.50
32
1
1
1
1
1
18.00
24.00
NATIONAL 3D ENHANCEMENT
The LM4846 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage
from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo
headphone listening. The LM4846 can be programmed for a “narrow” or “wide” soundstage perception. The
narrow soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial,
theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed:
low, medium, high, and maximum (Table 2), each level with an ever increasing aural effect, respectively. The
difference between each level is 3dB.
The external capacitors, shown in Figure 6, are required to enable the 3D effect. The value of the capacitors set
the cutoff frequency of the 3D effect, as shown by Equations 1 and 2. Note that the internal 20kΩ resistor is
nominal (±25%).
RHP3D1
LHP3D2
LHP3D1
C3DL
RHP3D2
20 k: (internal resistor)
LM4846
C3DR
Figure 8. External 3D Effect Capacitors
f3DL(-3dB) = 1 / 2π * 20kΩ * C3DL
(1)
f3DR(-3dB) = 1 / 2π * 20kΩ * C3DR
(2)
Optional resistors R3DL and R3DR can also be added (Figure 7) to affect the -3dB frequency and 3D magnitude.
RHP3D1
LHP3D2
LHP3D1
C3DL
RHP3D2
20 k: (internal resistor)
LM4846
C3DR
R3DL
R3DR
Figure 9. External RC Network with Optional R3DL and R3DR Resistors
24
f3DL(-3dB) = 1 / 2π * (20kΩ + R3DL) * C3DL
(3)
f3DR(-3dB) = 1 / 2π * 20kΩ + R3DR) * C3DR
(4)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
ΔAV (change in AC gain) = 1 / 1 + M, where M represents some ratio of the nominal internal resistor, 20kΩ (see
example below).
f3dB (3D) = 1 / 2π (1 + M)(20kΩ * C3D)
(5)
CEquivalent (new) = C3D / 1 + M
(6)
Table 8. Pole Locations
R3D (kΩ)
(optional)
C3D (nF)
0
68
1
68
ΔAV (dB)
f-3dB (3D)
(Hz)
0
0
117
0.05
–0.4
M
Value of C3D
to keep same
pole location
(nF)
new Pole
Location
(Hz)
111
64.8
117
5
68
0.25
–1.9
94
54.4
117
10
68
0.50
–3.5
78
45.3
117
20
68
1.00
–6.0
59
34.0
117
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8Ω LOAD
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by an 8Ω load from 158.3mW to 156.4mW. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
The LM4846 drives a load, such as a speaker, connected between outputs, MONO+ and MONO-.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage
of this phase difference, a load is placed between MONO- and MONO+ and driven differentially (commonly
referred to as ”bridge mode”). This results in a differential or BTL gain of:
AVD = 2(Rf / Ri) = 2
(7)
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
25
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing MONO- and MONO+ outputs at half-supply. This eliminates the coupling capacitor that single supply,
single-ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration
forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power
dissipation and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM4846 has a pair of bridged-tied amplifiers driving a handsfree speaker, MONO. The maximum
internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation
(8), assuming a 5V power supply and an 8Ω load, the maximum MONO power dissipation is 634mW.
PDMAX-SPKROUT = 4(VDD)2/ (2π2 RL): Bridge Mode
(8)
The LM4846 also has a pair of single-ended amplifiers driving stereo headphones, ROUT and LOUT. The maximum
internal power dissipation for ROUT and LOUT is given by equation (9) and (10). From Equations (9) and (10),
assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 40mW, or
80mW total.
PDMAX-LOUT = (VDD)2 / (2π2 RL): Single-ended Mode
(9)
PDMAX-ROUT = (VDD)2 / (2π2 RL): Single-ended Mode
(10)
The maximum internal power dissipation of the LM4846 occurs when all 3 amplifiers pairs are simultaneously on;
and is given by Equation (11).
PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT
(11)
The maximum power dissipation point given by Equation (11) must not exceed the power dissipation given by
Equation (12):
PDMAX = (TJMAX - TA) / θJA
(12)
The LM4846's TJMAX = 150°C. In the ITL package, the LM4846's θJA is 65°C/W. At any given ambient
temperature TA, use Equation (12) to find the maximum internal power dissipation supported by the IC
packaging. Rearranging Equation (12) and substituting PDMAX-TOTAL for PDMAX' results in Equation (13). This
equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without
violating the LM4846's maximum junction temperature.
TA = TJMAX - PDMAX-TOTAL θJA
(13)
For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 104°C
for the ITL package.
TJMAX = PDMAX-TOTAL θJA + TA
(14)
Equation (14) gives the maximum junction temperature TJMAX. If the result violates the LM4846's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
26
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation (11) is greater than that of Equation
(12), then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If
these measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using
additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output
pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power
dissipation. When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal
impedance, θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance). Refer
to the Typical Performance Characteristics curves for power dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.1µF tantalum bypass capacitance connected
between the LM4846's supply pins and ground. Keep the length of leads and traces that connect capacitors
between the LM4846's power supply pin and ground as short as possible. Connecting a 2.2µF capacitor, CB,
between the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's
PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however,
increases turn-on time and can compromise the amplifier's click and pop performance. The selection of bypass
capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as
explained in the section, Proper Selection of External Components), system cost, and size constraints.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figures 1 & 2). A high
value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases,
however, the speakers used in portable systems, whether internal or external, have little ability to reproduce
signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by
using large input capacitor.
The internal input resistor (Ri), nominal 20kΩ, and the input capacitor (Ci) produce a high pass filter cutoff
frequency that is found using Equation (15).
fc = 1 / (2πRiCi)
(15)
As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation (15) is 0.053µF.
The 0.22µF Ci shown in Figure 1 allows the LM4846 to drive high efficiency, full range speaker whose response
extends below 40Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS bump. Since CB determines how fast the LM4846 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4846's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 1.0µF along with a small value of Ci
(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 5 times to 7 times the value of Ci. This ensures that output transients are eliminated
when power is first applied or the LM4846 resumes operation after shutdown.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
27
LM4846
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
www.ti.com
LM4846 TL DEMO BOARD ARTWORK
Figure 10. Top Overlay
Figure 11. Top Layer
28
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
LM4846
www.ti.com
SNAS342C – NOVEMBER 2005 – REVISED JULY 2006
Figure 12. Bottom Layer
Revision History
Rev
Date
Description
1.0
11/10/05
1st WEB released.
1.1
12/21/05
Edited the X1, X2, and X3 in the mktg
ouline, then re-released D/S to the
WEB.
1.2
01/13/06
Added the Typ. Perf. curves, then
released D/S to the WEB.
1.3
07/06/06
Added the Twu row on the 3.3V and
5.0V EC tables (per Allan S.), then rereleased D/S to the WEB.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM4846
29
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Samples
(3)
(Requires Login)
LM4846TL/NOPB
ACTIVE
DSBGA
YZR
25
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
LM4846TLX/NOPB
ACTIVE
DSBGA
YZR
25
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM4846TL/NOPB
DSBGA
YZR
25
250
178.0
8.4
LM4846TLX/NOPB
DSBGA
YZR
25
3000
178.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.69
2.69
0.76
4.0
8.0
Q1
2.69
2.69
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM4846TL/NOPB
DSBGA
YZR
LM4846TLX/NOPB
DSBGA
YZR
25
250
203.0
190.0
41.0
25
3000
206.0
191.0
90.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0025xxx
TLA25XXX (Rev D)
D: Max = 2.601 mm, Min = 2.5 mm
E: Max = 2.581 mm, Min = 2.48 mm
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
LM4846TL/NOPB LM4846TLX/NOPB
