LM48510
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SNAS275E – NOVEMBER 2006 – REVISED APRIL 2013
LM48510
Boosted Class D Audio Power Amplifier
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FEATURES
DESCRIPTION
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The LM48510 integrates a boost converter with a
high efficiency mono, Class D audio power amplifier
to provide 1.2W continuous power into an 8Ω
speaker when operating on a 3.3V power supply with
boost voltage (PV1) of 5.0V. When operating on a
3.3V power supply, the LM48510 is capable of driving
a 4Ω speaker load at a continuous average output of
1.7W with less than 1% THD+N. The Class D
amplifier is a low noise, filterless PWM architecture
that eliminates the output filter, reducing external
component count, board area consumption, system
cost, and simplifying design.
1
2
Click and Pop Suppression
Low 0.01μA Shutdown Current
76% Efficiency
Filterless Class D
2.7V - 5.0V operation (VDD)
Externally Configurable Gain on Class D
Very Fast Turn on Time: 17μs
Independent Boost and Amplifier Shutdown
Pins
The LM48510's switching regulator is a current-mode
boost converter operating at a fixed frequency of
0.6MHz.
APPLICATIONS
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Mobile Phones
PDAs
Portable Media
Cameras
Handheld Games
The LM48510 is designed for use in mobile phones
and other portable communication devices. The high
(76%) efficiency extends battery life when compared
to Boosted Class AB amplifiers. The LM48510
features a low-power consumption shutdown mode.
Shutdown may be enabled by driving the Shutdown
pin to a logic low (GND).
KEY SPECIFICATIONS
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Quiescent Power Supply Current: 6mA (typ)
Output Power
(RL = 8Ω, THD+N ≤ 1%, VDD = 3.3V,
PV1 = 5.0V): 1.2 W (typ)
Shutdown Current: 0.01μA (typ)
The gain of the Class D is externally configurable
which allows independent gain control from multiple
sources by summing the signals. Output short circuit
and Thermal shutdown protection prevent the device
from damage during fault conditions. Superior click
and pop suppression eliminates audible transients
during power-up and shutdown.
Typical Application
L1
CS1
2.2 PF
VDD
D1
4.7 PH
Cf1
470 pF
VDD
GND2
SW
SDAMP
SDBOOST
SDAMP
1 PF 150 k:
INPUT
Co
10 PF
FB
R2
13.3 k:
GND3
SDBOOST
R1
41.2 k:
PV1
V1
CS2
4.7 PF
GND1
-IN
Ci
Ri
1PF 150 k:
Ci
+IN
VO1
VO2
Ri
Figure 1. Typical LM48510 Audio Amplifier Application Circuit
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM48510
SNAS275E – NOVEMBER 2006 – REVISED APRIL 2013
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Connection Diagram
Top View
VO1
1
16
SDAMP
GND1
2
15
V1
PV1
3
14
IN-
VO2
4
13
IN+
NC
5
12
NC
SDBOOST
6
11
VDD
GND2
7
10
GND3
FB
8
9
SW
Figure 2. WSON Package
See Package Number NHR0016B
Pin Description
WSON-14 Pin
Name
Function
1
VO1
2
GND1
3
PV1
Amplifier Power Input
4
VO2
Amplifier Output
5
NC1
No Connect
6
SDBOOST
7
GND2
8
FB
Feedback point that connects to external resistive divider
9
SW
Drain of the Internal FET Switch
10
GND3
11
VDD
Power Supply
12
NC2
No Connect
13
IN+
Amplifier Non-Inverting Input
14
IN-
Amplifier Inverting Input
15
V1
Amplifier Power Input
16
SDAMP
DAP
Amplifier Output
Ground
Boost Regulator Active Low Shutdown
Signal Ground (Booster)
Power Ground (Booster)
Amplifier Active Low Shutdown
To be soldered to board for enhanced thermal dissipation.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (1) (2)
Supply Voltage (VDD, V1)
6V
−65°C to +150°C
Storage Temperature
−0.3V to VDD + 0.3V
Input Voltage
Power Dissipation (3)
Internally limited
(4)
2000V
ESD Susceptibility
ESD Susceptibility (5)
200V
Junction Temperature
150°C
θJA (SD)
Thermal Resistance
37°C/W
See AN-1187 Leadless Leadframe Packaging (LLP) SNOA401
(1)
(2)
(3)
(4)
(5)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX − TA) / θJA or the given in Absolute Maximum Ratings, whichever is
lower.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF–240pF discharged through all pins.
Operating Ratings
Temperature Range (TMIN ≤ TA ≤ TMAX)
−40°C ≤ TA ≤ +85°C
2.7V ≤ VDD ≤ 5.0V
Supply Voltage (VDD)
4.5V ≤ V1 ≤ 5.5V
Supply Voltage (V1)
Electrical Characteristics VDD = 3.3V (1) (2)
The following specifications apply for VDD = 3.3V, PV1 = V1 = 5.0V, AV = 6dB (Ri = 150kΩ), RL = 15µH + 8Ω +15µH, fIN =
1kHz, unless otherwise specified. Limits apply for TA = 25°C.
Parameter
IDD
Quiescent Power Supply Current
Test Conditions
VIN = 0, RLOAD = ∞
(6)
LM48510
Typ (3)
Limit (4) (5)
Units
(Limits)
6.06
8.75
mA (max)
Shutdown Current
SDAMP = SDBOOST = GND
1
μA (max)
VSDIH
Shutdown Voltage Input High
SD1 Boost
SD2 Amplifier
1.5
1.4
V (min)
V (min)
VSDIL
Shutdown Voltage Input Low
SD1 Boost
SD2 Amplifier
0.5
0.4
V (max)
V (max)
TWU
Wake-up Time
17
μs
VOS
Output Offset Voltage
10
mV
ISD
(1)
(2)
(3)
(4)
(5)
(6)
0.01
All voltages are measured with respect to the GND pin, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Shutdown current is measured with components R1 and R2 removed.
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Electrical Characteristics VDD = 3.3V(1)(2) (continued)
The following specifications apply for VDD = 3.3V, PV1 = V1 = 5.0V, AV = 6dB (Ri = 150kΩ), RL = 15µH + 8Ω +15µH, fIN =
1kHz, unless otherwise specified. Limits apply for TA = 25°C.
Parameter
PO
Output Power
THD+N
εOS
Total Harmonic Distortion + Noise
Output Noise
AV
LM48510
Test Conditions
Typ (3)
Power Supply Rejection Ratio
Units
(Limits)
RL = 15μH + 4Ω + 15μH
THD+N = 1% (max),
f = 1kHz, 22kHz, BW
VDD = 3.3V
1.7
RL = 15μH + 8Ω + 15μH
THD+N = 1% (max),
f = 1kHz, 22kHz, BW
VDD = 3.3V
1.2
RL = 15μH + 4Ω + 15μH
THD+N = 10% (max),
f = 1kHz, 22kHz, BW
VDD = 2.7V
VDD = 3.3V
1.11
1.9
W
W
RL = 15μH + 8Ω + 15μH
THD+N = 10% (max),
f = 1kHz, 22kHz, BW
VDD = 2.7V
VDD = 3.3V
0.98
1.55
W
W
PO = 500mW, f = 1kHz,
RL = 15μH + 8Ω + 15μH,
VDD = 2.7V
0.06
%
PO = 500mW, f = 1kHz,
RL = 15μH + 8Ω + 15μH,
VDD = 3.3V
0.07
%
VDD = 3.3V, f = 20Hz – 20kHz
Inputs to AC GND, No weighting
input referred
67
µVRMS
VDD = 3.3V, f = 20Hz – 20kHz
Inputs to AC GND, A weighted
input referred
47
µVRMS
300kΩ/Ri
V/V
VRIPPLE = 200mVP-P Sine,
fRIPPLE = = 217Hz
89
dB
VRIPPLE = 200mVP-P Sine,
fRIPPLE = = 1kHz
83
dB
VRIPPLE = 200mVP-P Sine,
fRIPPLE = = 10kHz
55
dB
Gain
PSRR
Limit (4) (5)
W
0.9
W (min)
CMRR
Common Mode Rejection Ratio
VRIPPLE = 1VP-P, fRIPPLE = 217Hz
70
dB
η
Efficiency
PO = 1W, f = 1kHz,
RL = 15μH + 8Ω + 15μH, VDD = 3.3V
76
%
1.23
V
VFB
(7)
4
Feedback Pin Reference Voltage
See
(7)
Feedback pin reference voltage is measured with the Audio Amplifier disconnected from the Boost converter (the Boost converter is
unloaded).
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Typical Performance Characteristics
THD+N vs Frequency
VDD = 2.7V, RL = 15μH + 4Ω + 15μH
THD+N vs Frequency
VDD = 2.7V, RL = 15μH + 8Ω + 15μH
10
1
1
THD+N (%)
THD+N (%)
10
0.1
0.1
0.01
20
100
1k
0.01
20
10k 20k
100
1k
10k 20k
FREQUENCY (Hz)
Figure 3.
Figure 4.
THD+N vs Frequency
VDD = 3.3V, RL = 15μH + 4Ω + 15μH
THD+N vs Frequency
VDD = 3.3V, RL = 15μH + 8Ω + 15μH
10
10
1
1
THD + N (%)
THD+N (%)
FREQUENCY (Hz)
0.1
0.01
20
0.1
0.01
20
FREQUENCY (Hz)
1k
FREQUENCY (Hz)
Figure 5.
Figure 6.
THD+N vs Output Power
VDD = 2.7V, RL = 15μH + 4Ω + 15μH
THD+N vs Output Power
VDD = 2.7V, RL = 15μH + 8Ω + 15μH
100
1k
10k 20k
10
100
10k 20k
10
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.01
10m
100m
1
2
0.001
10m
100m
1
2
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 3.3V, RL = 15μH + 4Ω + 15μH
THD+N vs Output Power
VDD = 3.3V, RL = 15μH + 8Ω + 15μH
10
1
1
THD+N (%)
THD+N (%)
10
0.1
0.1
0.01
10m
1
100m
0.01
10m
2
2
Figure 9.
Figure 10.
Power Dissipation vs Output Power
VDD = 2.7V
Power Dissipation vs Output Power
VDD = 3.3V
1
0.7
POWER DISSIPATION (W)
0.6
POWER DISSIPATION (W)
1
100m
OUTPUT POWER (W)
OUTPUT POWER (W)
0.5
RL = 4:
0.4
0.3
RL = 8:
0.2
0.8
RL = 4:
0.6
0.4
RL = 8:
0.2
0.1
0
0
0
0.2
0.4
0.6
0.8
1.0
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 11.
Figure 12.
Power Dissipation vs Output Power
VDD = 4.2V
Power Supply Current vs Output Power
VDD = 2.7V
0.7
1.8
1.6
1.4
RL = 4:
1.2
1.0
0.8
RL = 8:
0.6
0.4
POWER SUPPLY CURRENT (mA)
2.0
POWER DISSIPATION (W)
0.2
0.6
0.5
RL = 4:
0.4
0.3
RL = 8:
0.2
0.1
0.2
0
0 0.2
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0.0
0.0
OUTPUT POWER (W)
0.4
0.6
0.8
1.0
OUTPUT POWER (W)
Figure 13.
6
0.2
Figure 14.
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Typical Performance Characteristics (continued)
Power Supply Current vs Output Power
VDD = 3.3V
Power Supply Current vs Output Power
VDD = 4.2V
0.7
RL = 4:
0.6
0.5
0.4
RL = 8:
0.3
0.2
0.1
0.0
0.0
0.2
0.4
0.6 0.8 1.0
1.2
0.8
POWER SUPPLY CURRENT (mA)
POWER SUPPLY CURRENT (mA)
0.8
RL = 4:
0.6
0.5
0.4
RL = 8:
0.3
0.2
0.1
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
1.6
1.4
0.7
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 16.
PSRR vs. Frequency
VDD = 3.3V, RL = 15μH + 8Ω + 15μH
CMRR vs Frequency
VDD = 3.3V, RL = 15μH + 8Ω + 15μH
+0
-10
-10
-20
-20
-30
-30
-40
CMRR (dB)
PSRR (dB)
0
Figure 15.
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
10
100
1k
10k 20k
T
100
FREQUENCY (Hz)
Figure 17.
10k 20k
Figure 18.
Supply Current vs. Supply Voltage
RL = no load
SW Current vs. Duty Cycle
3000
8
2500
7
SW CURRENT LIMIT (mA)
POWER SUPPLY CURRENT (mA)
9
1k
FREQUENCY (Hz)
6
5
4
3
2
2000
VDD = 3.3V
1500
1000
VDD = 2.7V
500
1
0
2.7
VDD = 5V
VDD = 3V
3.0 3.3
3.6
3.9
4.2
4.5 4.8
5.0
0
20
30
40
50
60
70
POWER SUPPLY VOLTAGE (V)
DUTY CYCLE (%)
Figure 19.
Figure 20.
80
90
100
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Typical Performance Characteristics (continued)
Feedback Bias Current vs. Temperature
1.231
0.09
1.23
0.08
FEEDBACK BIAS CURRENT (PA)
FEEDBACK VOLTAGE (V)
Feedback Voltage vs. Temperature
1.229
1.228
1.227
1.226
1.225
1.224
1.223
0.07
0.06
0.05
0.04
0.03
0.02
0.01
1.222
-40
0
-25
25
50
0
-50
75 100 125
0
-25
TEMPERATURE ( C)
Figure 21.
Max Duty Cycle vs. Temperature
75 100 125 150
RDS(ON) vs. Temperature
0.5
96.7
0.45
0.4
96.6
VDD = 3.3V
0.35
96.5
RDS(ON) (:)
MAX DUTY CYCLE (%)
50
Figure 22.
96.8
VDD = 3.3V
96.4
96.3
96.2
VDD = 5V
0.3
VDD = 5V
0.25
0.2
0.15
96.1
0.1
96
0.05
95.9
-50
25
TEMPERATURE (oC)
o
0
-25
0
25
50
75 100 125 150
-40
TEMPERATURE (°C)
-25
0
25
50
75 100 125
TEMPERATURE (°C)
Figure 23.
Figure 24.
RDS(ON) vs. VIN
Output Power vs. Efficiency
RL = 4Ω
350
100
300
90
VDD = 5.0V
EFFICIENCY (%)
RDS(ON) (m:)
80
250
200
150
100
70
60
50
VDD = 2.7V
VDD = 3.3V
40
30
20
50
10
0
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
VIN (V)
0.75
1.25
1.75
2.25
OUTPUT POWER (W)
Figure 25.
8
0
0 0.25
Figure 26.
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Typical Performance Characteristics (continued)
Output Power vs. Efficiency
RL = 8Ω
Boost Converter Max. Load Current vs. VDD
1200
100
VDD = 5.0V
80
EFFICIENCY (%)
70
60
VDD = 2.7V
50
VDD = 3.3V
40
30
20
MAX LOAD CURRENT (mA)
90
1000
800
VOUT = 5V
600
VOUT = 8V
400
VOUT = 10V
VOUT = 12V
200
10
0
0
0
0.25
0.50
0.75
1.00
1.25 1.50
2
3
4
5
6
7
8
OUTPUT POWER (W)
VDD (V)
Figure 27.
Figure 28.
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APPLICATION INFORMATION
GENERAL AMPLIFIER FUNCTION
The audio amplifier portion of LM48510 is a Class D featuring a filterless modulation scheme. The differential
outputs of the device switch at 300kHz from PV1 to GND. When there is no input signal applied, the two outputs
(VO1 and VO2) switch with a 50% duty cycle, with both outputs in phase. Because the outputs of the Class D
are differential, the two signals cancel each other. This results in no net voltage across the speaker, thus there is
no load current during an idle state, conserving power.
With an input signal applied, the duty cycle (pulse width) of the Class D outputs changes. For increasing output
voltages, the duty cycle of VO1 increases, while the duty cycle of VO2 decreases. For decreasing output
voltages, the converse occurs, the duty cycle of VO2 increases while the duty cycle of VO1 decreases. The
difference between the two pulse widths yields the differential output voltage.
OPERATING RATINGS
The LM48510 has independent power supplies for the Class D audio power amplifier (PV1, V1) and the Boost
Converter (VDD). The Class D amplifier operating rating is 2.4V≤(PV1, V1)≤5.5V when being used without the
Boost.
Note the output voltage (PV1, V1) has to be more than VDD.
DIFFERENTIAL AMPLIFIER EXPLANATION
As logic supply voltages continue to shrink, designers are increasingly turning to differential analog signal
handling to preserve signal to noise ratios with restricted voltage swing. The amplifier portion of the LM48510 is a
fully differential amplifier that features differential input and output stages. A differential amplifier amplifies the
difference between the two input signals. Traditional audio power amplifiers have typically offered only singleended inputs resulting in a 6dB reduction in signal to noise ratio relative to differential inputs. The amplifier also
offers the possibility of DC input coupling which eliminates the two external AC coupling, DC blocking capacitors.
The amplifier can be used, however, as a single ended input amplifier while still retaining it's fully differential
benefits. In fact, completely unrelated signals may be placed on the input pins. The amplifier portion of the
LM48510 simply amplifies the difference between the signals. A major benefit of a differential amplifier is the
improved common mode rejection ratio (CMRR) over single input amplifiers. The common-mode rejection
characteristic of the differential amplifier reduces sensitivity to ground offset related noise injection, especially
important in high noise applications.
AMPLIFIER DISSIPATION
In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required
to produce it with the difference being the power dissipated, typically, in the IC. The key here is “useful” work. For
audio systems, the energy delivered in the audible bands is considered useful including the distortion products of
the input signal. Sub-sonic (DC) and super-sonic components (>22kHz) are not useful. The difference between
the power flowing from the power supply and the audio band power being transduced is dissipated in the
LM48510 and in the transducer load. The amount of power dissipation in the LM48510 is very low. This is
because the ON resistance of the switches used to form the output waveforms is typically less than 0.25Ω. This
leaves only the transducer load as a potential "sink" for the small excess of input power over audio band output
power. The amplifier dissipates only a fraction of the excess power requiring no additional PCB area or copper
plane to act as a heat sink.
BOOST CONVERTER POWER DISSIPATION
At higher duty cycles, the increased ON time of the FET means the maximum output current will be determined
by power dissipation within the boost converter FET switch. The switch power dissipation from ON-state
conduction is calculated by Equation (1).
PDMAX(SWITCH) = DC x IIND(AVE)2 x RDS(ON)
(1)
Where DC is the duty cycle.
There will be some switching losses as well, so some derating needs to be applied when calculating IC power
dissipation.
10
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SHUTDOWN FUNCTION
To reduce power consumption while not in use, the amplifier of LM48510 contains shutdown circuitry that
reduces current draw to less than 0.01µA. It is best to switch between ground and supply (PV1, V1) for minimum
current usage while in the shutdown state. While the LM48510 may be disabled with shutdown voltages in
between ground and supply, the idle current will be greater than the typical 0.01µA value. Increased THD may
also be observed with voltages less than VDD on the SDAMP pin when in PLAY mode.
The amplifier has an internal resistor connected between GND and SDAMP pins. The purpose of this resistor is to
eliminate any unwanted state changes when the SDAMP pin is floating. The amplifier will enter the shutdown state
when the SDAMP pin is left floating or if not floating, when the shutdown voltage has crossed the threshold. To
minimize the supply current while in the shutdown state, the SDAMP pin should be driven to GND or left floating. If
the SDAMP pin is not driven to GND, the amount of additional resistor current due to the internal shutdown
resistor can be found by Equation (2) below.
(VSD - GND) / 300kΩ
(2)
With only a 0.5V difference, an additional 1.7µA of current will be drawn while in the shutdown state.
In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry to
provide a quick, smooth transition into shutdown. Another solution is to use a single-pole, single-throw switch,
and a pull-up resistor. One terminal of the switch is connected to GND. The other side is connected to the two
shutdown pins and the terminal of the pull-up resistor. The remaining resistance terminal is connected to VDD. If
the switch is open, then the external pull-up resistor connected to VDD will enable the LM48510. This scheme
ensures that the shutdown pins will not float thus preventing unwanted state changes.
PROPER SELECTION OF EXTERNAL COMPONENTS
Proper selection of external components in applications using integrated power amplifiers, and switching DC-DC
converters, is critical for optimizing device and system performance. Consideration to component values must be
used to maximize overall system quality.
The best capacitors for use with the switching converter portion of the LM48510 are multi-layer ceramic
capacitors. They have the lowest ESR (equivalent series resistance) and highest resonance frequency, which
makes them optimum for high frequency switching converters.
When selecting a ceramic capacitor, only X5R and X7R dielectric types should be used. Other types such as
Z5U and Y5F have such severe loss of capacitance due to effects of temperature variation and applied voltage,
they may provide as little as 20% of rated capacitance in many typical applications. Always consult capacitor
manufacturer’s data curves before selecting a capacitor. High-quality ceramic capacitors can be obtained from
Taiyo-Yuden, AVX, and Murata.
The gain of the amplifier is set by the external resistors, Ri in Figure 1. The gain is given by Equation (3) below.
Best THD+N performance is achieved with a gain of 2V/V (6dB).
AV = 2 * 150kΩ / Ri (V/V)
(3)
It is recommended that resistors with 1% tolerance or better be used to set the gain of the amplifier. The Ri
resistors should be placed close to the input pins of the amplifier. Keeping the input traces close to each other
and of the same length in a high noise environment will aid in noise rejection due to the good CMRR of the Class
D. Noise coupled onto input traces which are physically close to each other will be common mode and easily
rejected by the amplifier.
Input capacitors may be needed for some applications or when the source is single-ended (see Figure 1). Input
capacitors are needed to block any DC voltage at the source so that the DC voltage seen between the input
terminals of the Class D is 0V. Input capacitors create a high-pass filter with the input resistors, Ri. The –3dB
point of the high-pass filter is found using Equation (4) below.
fC = 1 / (2πRi Ci ) (Hz)
(4)
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The input capacitors may also be used to remove low audio frequencies. Small speakers cannot reproduce low
bass frequencies so filtering may be desired . When the Class D is using a single-ended source, power supply
noise on the ground is seen as an input signal by the +IN input pin that is capacitor coupled to ground. Setting
the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, will
filter out this noise so it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are
recommended for impedance matching.
POWER SUPPLY BYPASSING FOR AMPLIFIER
As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. The capacitor (Cs2, see Figure 1) location on both PV1 and V1 pin should be as close to the device as
possible.
SELECTING INPUT CAPACITOR FOR AUDIO AMPLIFIER
One of the major considerations is the closedloop bandwidth of the amplifier. To a large extent, the bandwidth is
dictated by the choice of external components shown in Figure 1. The input coupling capacitor, Ci, forms a first
order high pass filter which limits low frequency response. This value should be chosen based on needed
frequency response for a few distinct reasons.
High value input capacitors are both expensive and space hungry in portable designs. Clearly, a certain value
capacitor is needed to couple in low frequencies without severe attenuation. But ceramic speakers used in
portable systems, whether internal or external, have little ability to reproduce signals below 100Hz to 150Hz.
Thus, using a high value input capacitor may not increase actual system performance.
In addition to system cost and size, click and pop performance is affected by the value of the input coupling
capacitor, Ci. A high value input coupling capacitor requires more charge to reach its quiescent DC voltage
(nominally 1/2 VDD). This charge comes from the output via the feedback and is apt to create pops upon device
enable. Thus, by minimizing the capacitor value based on desired low frequency response, turn-on pops can be
minimized.
SELECTING OUTPUT CAPACITOR (CO) FOR BOOST CONVERTER
A single 4.7µF to 10µF ceramic capacitor will provide sufficient output capacitance for most applications. If larger
amounts of capacitance are desired for improved line support and transient response, tantalum capacitors can
be used. Aluminum electrolytics with ultra low ESR such as Sanyo Oscon can be used, but are usually
prohibitively expensive. Typical electrolytic capacitors are not suitable for switching frequencies above 500 kHz
because of significant ringing and temperature rise due to self-heating from ripple current. An output capacitor
with excessive ESR can also reduce phase margin and cause instability.
In general, if electrolytics are used, it is recommended that they be paralleled with ceramic capacitors to reduce
ringing, switching losses, and output voltage ripple.
SELECTING INPUT CAPACITOR (Cs1) FOR BOOST CONVERTER
An input capacitor is required to serve as an energy reservoir for the current which must flow into the coil each
time the switch turns ON. This capacitor must have extremely low ESR, so ceramic is the best choice. A nominal
value of 4.7µF is recommended, but larger values can be used. Since this capacitor reduces the amount of
voltage ripple seen at the input pin, it also reduces the amount of EMI passed back along that line to other
circuitry.
SETTING THE OUTPUT VOLTAGE (V1) OF BOOST CONVERTER
The output voltage is set using the external resistors R1 and R2 (see Figure 1). A value of approximately 13.3kΩ
is recommended for R2 to establish a divider current of approximately 92µA. R1 is calculated using the formula:
R1 = R2 X (V1/1.23 − 1)
12
(5)
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FEED-FORWARD COMPENSATION FOR BOOST CONVERTER
Although the LM48510's internal Boost converter is internally compensated, the external feed-forward capacitor
Cf1 is required for stability (see Figure 1). Adding this capacitor puts a zero in the loop response of the converter.
The recommended frequency for the zero fz should be approximately 6kHz. Cf1 can be calculated using the
formula:
Cf1 = 1 / (2π X R1 X fz)
(6)
SELECTING DIODES FOR BOOST
The external diode used in Figure 1 should be a Schottky diode. A 20V diode such as the MBR0520 is
recommended.
The MBR05XX series of diodes are designed to handle a maximum average current of 0.5A. For applications
exceeding 0.5A average but less than 1A, a Microsemi UPS5817 can be used.
DUTY CYCLE
The maximum duty cycle of the boost converter determines the maximum boost ratio of output-to-input voltage
that the converter can attain in continuous mode of operation. The duty cycle for a given boost application is
defined as:
Duty Cycle = V1 + VDIODE - VDD/ V1 + VDIODE - VSW
This applies for continuous mode operation.
INDUCTANCE VALUE
The inductor is the largest sized component and usually the most costly. “How small can the inductor be?” The
answer is not simple and involves trade-offs in performance. Larger inductors mean less inductor ripple current,
which typically means less output voltage ripple (for a given size of output capacitor). Larger inductors also mean
more load power can be delivered because the energy stored during each switching cycle is:
E = L/2 X (lp)2
(7)
Where lp is the peak inductor current. An important point to observe is that the LM48510 will limit its switch
current based on peak current. This means that since lp(max) is fixed, increasing L will increase the maximum
amount of power available to the load. Conversely, using too little inductance may limit the amount of load
current which can be drawn from the output.
Best performance is usually obtained when the converter is operated in “continuous” mode at the load current
range of interest, typically giving better load regulation and less output ripple. Continuous operation is defined as
not allowing the inductor current to drop to zero during the cycle. It should be noted that all boost converters shift
over to discontinuous operation as the output load is reduced far enough, but a larger inductor stays “continuous”
over a wider load current range.
To better understand these trade-offs, a typical application circuit (5V to 12V boost with a 10µH inductor) will be
analyzed. We will assume:
VIN = 5V, VOUT = 12V, VDIODE = 0.5V, VSW = 0.5V
(8)
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Since the frequency is 0.6MHz (nominal), the period is approximately 1.66µs. The duty cycle will be 62.5%,
which means the ON-time of the switch is 1.04µs. It should be noted that when the switch is ON, the voltage
across the inductor is approximately 4.5V. Using Equation (9):
V = L (di/dt)
(9)
We can then calculate the di/dt rate of the inductor which is found to be 0.17 A/µs during the ON-time. Using
these facts, we can then show what the inductor current will look like during operation:
0.176A
ILOAD
1 - DC
0
1.04 Ps
0.425 Ps
Figure 29. 10μH Inductor Current
5V - 12V Boost (LM48510)
During the 1.04µs ON-time, the inductor current ramps up 0.176A and ramps down an equal amount during the
OFF-time. This is defined as the inductor “ripple current”. A similar analysis can be performed on any boost
converter, to make sure the ripple current is reasonable and continuous operation will be maintained at the
typical load current values.
MAXIMUM SWITCH CURRENT
The maximum FET switch current available before the current limiter cuts in is dependent on duty cycle of the
application. This is illustrated in a graph in the typical performance characterization section which shows typical
values of switch current as a function of effective (actual) duty cycle.
CALCULATING OUTPUT CURRENT OF BOOST CONVERTER (IAMP)
As shown in Figure 29 which depicts inductor current, the load current is related to the average inductor current
by the relation:
ILOAD = IIND(AVG) x (1 - DC)
(10)
Where "DC" is the duty cycle of the application. The switch current can be found by:
ISW = IIND(AVG) + 1/2 (IRIPPLE)
14
(11)
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Inductor ripple current is dependent on inductance, duty cycle, input voltage and frequency:
IRIPPLE = DC x (VIN-VSW) / (f x L)
(12)
combining all terms, we can develop an expression which allows the maximum available load current to be
calculated:
ILOAD(max) = (1–DC)x(ISW(max)–DC(VIN-VSW))/2fL
(13)
The equation shown to calculate maximum load current takes into account the losses in the inductor or turn-OFF
switching losses of the FET and diode.
DESIGN PARAMETERS VSW AND ISW
The value of the FET ON voltage (referred to as VSW in Equations (10) thru (13)) is dependent on load current. A
good approximation can be obtained by multiplying the RDS(ON) of the FET times the average inductor current.
FET on resistance increases at VIN values below 5V, since the internal N-FET has less gate voltage in this input
voltage range (see Typical Performance Characteristics curves). Above VIN = 5V, the FET gate voltage is
internally clamped to 5V.
The maximum peak switch current the device can deliver is dependent on duty cycle. For higher duty cycles, see
Typical Performance Characteristics curves.
INDUCTOR SUPPLIERS
Recommended suppliers of inductors for the LM48510 include, but are not limited to Taiyo-Yuden, Sumida,
Coilcraft, Panasonic, TDK and Murata. When selecting an inductor, make certain that the continuous current
rating is high enough to avoid saturation at peak currents. A suitable core type must be used to minimize core
(switching) losses, and wire power losses must be considered when selecting the current rating.
PCB LAYOUT GUIDELINES
High frequency boost converters require very careful layout of components in order to get stable operation and
low noise. All components must be as close as possible to the LM48510 device. It is recommended that a four
layer PCB be used so that internal ground planes are available.
Some additional guidelines to be observed:
1. Keep the path between L1, D1, and Co extremely short. Parasitic trace inductance in series with D1 and Co
will increase noise and ringing.
2. The feedback components R1, R2 and Cf1 must be kept close to the FB pin to prevent noise injection on the
FB pin trace.
3. If internal ground planes are available (recommended) use vias to connect directly to ground at pin 2 of U1, as
well as the negative sides of capacitors Cs1 and Co.
GENERAL MIXED-SIGNAL LAYOUT RECOMMENDATION
This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power
and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual
results will depend heavily on the final layout.
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Power and Ground Circuits
For two layer mixed signal design, it is important to isolate the digital power and ground trace paths from the
analog power and ground trace paths. Star trace routing techniques (bringing individual traces back to a central
point rather than daisy chaining traces together in a serial manner) can have a major impact on low level signal
performance. Star trace routing refers to using individual traces to feed power and ground to each circuit or even
device. This technique will take require a greater amount of design time but will not increase the final price of the
board. The only extra parts required may be some jumpers.
Single-Point Power / Ground Connection
The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can
be helpful in minimizing high frequency noise coupling between the analog and digital sections. It is further
recommended to place digital and analog power traces over the corresponding digital and analog ground traces
to minimize noise coupling.
Placement of Digital and Analog Components
All digital components and high-speed digital signals traces should be located as far away as possible from
analog components and circuit traces.
Avoiding Typical Design / Layout Problems
Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB
layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90
degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise
coupling and crosstalk.
VDD
D1
L1
JP1
4.7 PH
CS1
2.2 PF
VDD
Cf1
470 pF
SW
VDD
1
2
VDD
JP2
1
2
3
R1
41.2k
CO
10 PF
FB
R2
13.3k
SDAMP
PV1
VDD
JP5
1
2
3
1 PF
150 k:
CINB
1 PF
RINB
150 k:
CINA
RINA
SDREG
INPUTS
JP3
OUTPUTS
-IN
1
2
CS2
4.7 PF
V1
VO1
VO2
1
2
JP4
GND3
EP
GND2
GND1
+IN
Figure 30. Demo Board Schematic Reference
16
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Demonstration Board Layout
Figure 31. Top Layer Silkscreen
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Figure 32. Top Trace Layer
18
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Figure 33. GND Layer (middle 1)
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Figure 34. Power Trace Layer (middle 2)
20
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Figure 35. Bottom Layer
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Figure 36. Bottom Silkscreen
Build Of Material
Designator
Description
Footprint
Quantity
Value
Cf1
CHIP CAPACITOR GENERIC
CAP 0805
1
470pF
CINA
CHIP CAPACITOR GENERIC
CAP 1210
1
1μF
CINB
CHIP CAPACITOR GENERIC
CAP 1210
1
1μF
Co
CHIP CAPACITOR GENERIC
CAP 1210
1
10μF
Cs1
CHIP CAPACITOR GENERIC
CAP 1210
1
2.2μF
Cs2
CHIP CAPACITOR GENERIC
CAP 1210
1
4.7μF
D1
SCHOTTKY DIO
DIODE MBR0520 IR
1
IND_COILCRAFT-DO1813P
1
4.7μH
R1
L1
CHIP RESISTOR GENERIC
RES 0805
1
41.2K
R2
CHIP RESISTOR GENERIC
RES 0805
1
13.3K
RINA
CHIP RESISTOR GENERIC
RES 0805
1
150K
RINB
CHIP RESISTOR GENERIC
RES 0805
1
150K
Revision History
22
Rev
Date
Description
1.0
11/16/06
Initial release.
1.1
03/07/07
Changed the Limit value on the VSDIH and VSDIL to 1.5 and 0.5 respectively.
1.2
10/15/07
Changed the typical value of Vfb = 1.24 to 1.23
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E
04/08/13
Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM48510SDE/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WSON
NHR
16
250
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
CU SN
Level-1-260C-UNLIM
(4/5)
L48510
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM48510SDE/NOPB
Package Package Pins
Type Drawing
WSON
NHR
16
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
12.4
Pack Materials-Page 1
4.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.3
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM48510SDE/NOPB
WSON
NHR
16
250
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NHR0016B
SDA16B (Rev A)
www.ti.com
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