LM4853LD/NOPB

LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 LM4853 Mono 1.5 W / Stereo 300mW Power Amplifier Check for Samples: LM4853 FEATURES DESCRIPTION • • • • • • • The LM4853 is an audio power amplifier capable of delivering 1.5W (typ) of continuous average power into a mono 4Ω bridged-tied load (BTL) with 1% THD+N or 95mW per channel of continuous average power into stereo 32Ω single-ended (SE) loads with 1% THD+N, using a 5V power supply. 1 2 Mono 1.5W BTL or Stereo 300mW Output Headphone Sense “Click and Pop” Suppression Circuitry No Bootstrap Capacitors Required Thermal Shutdown Protection Unity-Gain Stable Available in Space-Saving VSSOP and WSON Packaging APPLICATIONS • • • • Portable Computers Desktop Computers PDA's Handheld Games KEY SPECIFICATIONS • • • • Output Power at 1% THD+N, 1kHz: – LM4853LD 3Ω BTL 1.9W (typ) – LM4853LD 4Ω BTL 1.7W (typ) – LM4853MM 4Ω BTL 1.5W (typ) – LM4853MM,LD 8Ω BTL 1.1W (typ) – LM4853MM,LD 8Ω SE 300mW (typ) – LM4853MM,LD 32Ω SE 95mW (typ) THD+N at 1kHz, 95mW into 32Ω SE 1% (typ) Single Supply Operation 2.4 to 5.5V Shutdown Current 18µA (typ) The LM4853 can automatically switch between mono BTL and stereo SE modes utilizing a headphone sense pin. It is ideal for any system that provides both a monaural speaker output and a stereo line or headphone output Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. Since the LM4853 does not require bootstrap capacitors or snubber networks, it is optimally suited for low-power portable systems. The LM4853 features an externally controlled, micropower consumption shutdown mode and thermal shutdown protection. The unity-gain stable LM4853's gain is set by external gain-setting resistors Connection Diagram Figure 1. 10 Lead VSSOP – Top View See Package Number DGS Figure 2. 14 Lead WSON – Top View See Package Number NHE0014A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2013, Texas Instruments Incorporated LM4853 SNAS155E – JANUARY 2002 – REVISED MAY 2013 www.ti.com Typical Application Figure 3. Typical Audio Amplifier Application Circuit 2 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage 6.0V −65°C to +150°C Storage Temperature ESD Susceptibility (3) ESD Machine model 3.5kV (4) 250V Junction Temperature (TJ) Solder Information 150°C Small Outline Package Vapor Phase (60 sec.) 215°C Infrared (15 sec.) 220°C θJA (typ)—DGS 194°C/W θJC (typ)—DGS Thermal Resistance 52°C/W θJA (typ)—NHE0014A (5) 56°C/W θJC (typ)—NHE0014A (1) (2) (3) (4) (5) 4.3°C/W Absolute Maximum Rating indicate limits beyond which damage to the device may occur. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Human body model, 100pF discharged through a 1.5kΩ resistor. Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω). The given θJA is for an LM4853LD with the Exposed-DAP soldered to an exposed 1in2 area of 1oz printed circuit board copper. Operating Ratings (1) Temperature Range −40°C ≤ to 85°C Supply Voltage VDD 2.4V ≤ VDD ≤ 5.5V (1) Absolute Maximum Rating indicate limits beyond which damage to the device may occur. Electrical Characteristics (1) (2) The following specifications apply for VDD= 5.0V, TA= 25°C unless otherwise specified. Symbol Parameter Conditions LM4853 Typical VDD IDD Supply Voltage Supply Current (3) Limit (4) (5) Units (Limits) 2.4 V (min) 5.5 V (max) BTL Mode; VIN = 0V; IO = 0A 2.4 7.0 mA SE Mode; VIN = 0V; IO = 0A 2.4 7.0 mA ISD Shutdown Current SD Mode; VSHUTDOWN = VDD 18 VOS Output Offset Voltage BTL Mode; AV = 2 5.0 µA 40 mV BTL OUT+ to BTL OUT− (1) (2) (3) (4) (5) Absolute Maximum Rating indicate limits beyond which damage to the device may occur. All voltages are measured with respect to the ground pin, unless otherwise specified. Typical specifications are specified at +25°C and represent the most likely parametric norm. Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Limits are specified to TI's AOQL ( Average Outgoing Quality Level ). Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 3 LM4853 SNAS155E – JANUARY 2002 – REVISED MAY 2013 www.ti.com Electrical Characteristics(1)(2) (continued) The following specifications apply for VDD= 5.0V, TA= 25°C unless otherwise specified. Symbol Parameter Conditions LM4853 Typical PO Output Power (3) Limit (4) (5) Units (Limits) BTL Mode; RL = 3Ω THD+N = 1%; LM4853LD 1.9 W BTL Mode; RL = 4Ω THD+N = 1%; LM4853LD 1.7 W BTL Mode; RL = 4Ω THD+N = 1%; LM4853MM 1.5 W BTL Mode; RL = 8Ω THD+N = 1%; LM4853MM, LD 1.1 W SE Mode; RL = 8Ω THD+N = 1%; LM4853MM, LD 300 mW SE Mode; RL = 32Ω THD+N = 1%; LM4853MM, LD 95 mW VIH Shutdown Input Voltage High Is < 80µA 2.0 V (min) VIL Shutdown Input Voltage Low Is > 0.5mA 0.8 V (max) Crosstalk Channel Seperation SE Mode, RL = 32Ω; f = 1kHz 73 dB Electrical Characteristics (1) (2) The following specifications apply for VDD= 3.3V, TA= 25°C unless otherwise specified. Symbol Parameter Conditions LM4853 Typical IDD Supply Current (3) Limit (4) (5) Units (Limits) BTL Mode; VIN = 0V; IO = 0A 2.0 mA SE Mode; VIN = 0V; IO = 0A 2.0 mA ISD Shutdown Current SD Mode; VSHUTDOWN = VDD 12 VOS Output Offset Voltage BTL Mode; AV = 2 BTL OUT+ to BTL OUT− 5.0 µA PO Output Power BTL Mode; RL = 8Ω THD+N = 1% 440 mW SE Mode; RL = 32Ω THD+N = 1% 40 mW 40 mV VIH Shutdown Input Voltage High Is < 80µA 2.0 V (min) VIL Shutdown Input Voltage Low Is > 0.5mA 0.8 V (max) (1) (2) (3) (4) (5) 4 Absolute Maximum Rating indicate limits beyond which damage to the device may occur. All voltages are measured with respect to the ground pin, unless otherwise specified. Typical specifications are specified at +25°C and represent the most likely parametric norm. Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Limits are specified to TI's AOQL ( Average Outgoing Quality Level ). Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 Electrical Characteristics (1) (2) The following specifications apply for VDD= 2.7V, TA= 25°C unless otherwise specified. Symbol Parameter Conditions LM4853 Typical IDD Supply Current (3) Limit (4) (5) Units (Limits) BTL Mode; VIN = 0V; IO = 0A 1.8 mA SE Mode; VIN = 0V; IO = 0A 1.8 mA µA ISD Shutdown Current SD Mode; VSHUTDOWN = VDD 10 VOS Output Offset Voltage BTL Mode; AV = 2 BTL OUT+ to BTL OUT− 5.0 PO Output Power BTL Mode; RL = 8Ω THD+N = 1% 300 mW SE Mode; RL = 32Ω THD+N = 1% 25 mW 40 mV VIH Shutdown Input Voltage High Is < 80 µA 2.0 V (min) VIL Shutdown Input Voltage Low Is > 0.5mA 0.8 V (max) (1) (2) (3) (4) (5) Absolute Maximum Rating indicate limits beyond which damage to the device may occur. All voltages are measured with respect to the ground pin, unless otherwise specified. Typical specifications are specified at +25°C and represent the most likely parametric norm. Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Limits are specified to TI's AOQL ( Average Outgoing Quality Level ). External Components Description See Figure 3. Components Functional Description 1. Ri Inverting input resistance which sets the closed-loop gain in conjunction with Rf. This resistor also forms a high pass filter with Ci at fc = 1/(2πRiCi). 2. Ci Input coupling capacitor which blocks the DC voltage at the amplifier's input terminals. Also creates a highpass filter with Ri at fc = 1/(2πRiCi). Refer to the section, PROPER SELECTION OF EXTERNAL COMPONENTS, for an explanation of how to determine the value of Ci. 3. Rf Feedback resistance which sets the closed-loop gain in conjunction with Ri. 4. Cs Supply bypass capacitor which provides power supply filtering. Refer to the POWER SUPPLY BYPASSING section for information concerning proper placement and selection of the supply bypass capacitor. 5. CB Bypass pin capacitor which provides half-supply filtering. Refer to the section, PROPER SELECTION OF EXTERNAL COMPONENTS, for information concerning proper placement and selection of CB. 6. CO Output coupling capacitor which blocks the DC voltage at the amplifier's output. Forms a high pass filter with the singleended load RL at fO = 1/(2π RLCO). Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 5 LM4853 SNAS155E – JANUARY 2002 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics LD Specific Characteristics 6 LM4853LD THD+N vs Frequency LM4853LD THD+N vs Frequency Figure 4. Figure 5. LM4853LD THD+N vs Output Power LM4853LD THD+N vs Output Power Figure 6. Figure 7. LM4853LD Power Dissipation vs Output Power LM4853LD Power Derating Curve Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 Typical Performance Characteristics THD+N vs Frequency THD+N vs Frequency Figure 10. Figure 11. THD+N vs Frequency THD+N vs Frequency Figure 12. Figure 13. THD+N vs Frequency THD+N vs Frequency Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 7 LM4853 SNAS155E – JANUARY 2002 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) 8 THD+N vs Frequency THD+N vs Output Power Figure 16. Figure 17. THD+N vs Output Power THD+N vs Output Power Figure 18. Figure 19. THD+N vs Output Power THD+N vs Output Power Figure 20. Figure 21. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 Typical Performance Characteristics (continued) THD+N vs Output Power THD+N vs Output Power Figure 22. Figure 23. THD+N vs Output Power Output Power vs Load Resistance Figure 24. Figure 25. Output Power vs Load Resistance Output Power vs Supply Voltage Figure 26. Figure 27. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 9 LM4853 SNAS155E – JANUARY 2002 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) 10 Output Power vs Supply Voltage Dropout Voltage vs Supply Voltage Figure 28. Figure 29. Power Dissipation vs Output Power Power Dissipation vs Output Power Figure 30. Figure 31. Power Derating Curve Channel Separation Figure 32. Figure 33. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 Typical Performance Characteristics (continued) Noise Floor Open Loop Frequency Response Figure 34. Figure 35. Supply Current vs Supply Voltage Power Supply Rejection Ratio Figure 36. Figure 37. Power Supply Rejection Ratio Figure 38. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 11 LM4853 SNAS155E – JANUARY 2002 – REVISED MAY 2013 www.ti.com APPLICATION INFORMATION BRIDGED AND SINGLE-ENDED OPERATION As shown in Typical Application, the LM4853 contains three operational amplifiers (A1-A3). These amplifiers can be configured for SE or BTL modes. In the SE mode, the LM4853 operates as a high current output dual op amp. A1 and A3 are independent amplifiers with an externally configured gain of AV = - RF/RI. The outputs of A1 and A3 are used to drive an external set of headphones plugged into the headphone jack. Amplifier A2 is shut down to a high output impedance state in SE mode. This prevents any current flow into the mono bridge-tied load, thereby muting it. In BTL mode, A3 is shut down to a high impedance state. The audio signal from the RIGHT IN pin is directed to the inverting input of A1. As a result, the LEFT IN and RIGHT IN audio signals, VINL and VINR, are summed together at the input of A1. A2 is then activated with a closed-loop gain of AV = -1 fixed by two internal 20kΩ resistors. The outputs of A1 and A2 are then used to drive the mono bridged-tied load. EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATION The LM4853's exposed-DAP (die attach paddle) package (LD) provides a low thermal resistance between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper traces, ground plane, and surrounding air. The result is a low voltage audio power amplifier that produces 1.7W at ≤ 1% THD+N with a 4Ω load. This high power is achieved through careful consideration of necessary thermal design. Failing to optimize thermal design may compromise the LM4853's high power performance and activate unwanted, though necessary, thermal shutdown protection. The LD package must have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad is connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink, and radiation area. Place the heat sink area on either outside plane in the case of a two-sided PCB, or on an inner layer of a board with more than two layers. Connect the DAP copper pad to the inner layer or backside copper heat sink area with 4(2x2) vias. The via diameter should be 0.012in-0.013in with a 1.27mm pitch. Ensure efficient thermal conductivity by plating through the vias. Best thermal performance is achieved with the largest practical heat sink area. If the heatsink and amplifier share the same PCB layer, a nominal 2.5in2 area is necessary for 5V operation with a 4Ω load. Heatsink areas not placed on the same PCB layer as the LM4853 should be 5in2 (min) for the same supply voltage and load resistance. The last two area recommendations apply for 25°C ambient temperature. Increase the area to compensate for ambient temperatures above 25°C. The LM4853's power de-rating curve in the Typical Performance Characteristics LD Specific Characteristics shows the maximum power dissipation versus temperature. An example PCB layout for the LD package is shown in the Demonstration Board Layout section. For further detailed and specific information concerning PCB layout, fabrication, and mounting an NHE (WSON) package, see TI's AN-1187 Application Report. BRIDGE CONFIGURATION EXPLANATION When the LM4853 is in BTL mode, the output of amplifier A1 serves as the input to amplifier A2, which results in both amplifiers producing signals identical in magnitude, but out of phase by 180°. Consequently, the differential gain for the mono channel is: AVD = VOUT / (VINL + VINR) = 2 × (RF / RI) (1) Driving a load differentially through the BTL OUT- and BTL OUT+ outputs is an amplifier configuration commonly referred to as "bridged mode". Bridged mode operation is different from the classical single-ended amplifier configuration where one side of its load is connected to ground. A bridge amplifier design has a few distinct advantages over the single-ended configuration. It drives a load differentially, which doubles output swing for a specified supply voltage. This produces four times the output power as that produced by a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closed-loop gain without causing excessive output signal clipping, please refer to the AUDIO POWER AMPLIFIER DESIGN section. 12 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 A bridge configuration, such as the one used in LM4853, also creates a second advantage over single-ended amplifiers. Since the differential outputs, BTL OUT- and BTL OUT+, are biased at half-supply, no net DC voltage exists across the load. This eliminates the need for the output coupling capacitor that a single supply, singleended amplifier configuration requires. Eliminating an output coupling capacitor in a single-ended configuration forces the half-supply bias voltage across the load. This increases internal IC power dissipation and may cause permanent loudspeaker damage. POWER DISSIPATION Whether the power amplifier is bridged or single-ended, power dissipation is a major concern when designing the amplifier. Equation 2 states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and driving a specified load. PDMAX = (VDD)2/(2π2 RL): Single-Ended (2) However, a direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation.Equation 3 states the maximum power dissipation point for a bridge amplifier operating at the same given conditions. PDMAX = 4 × (VDD)2/(2π2 RL): Bridge Mode (3) The LM4853 is designed to drive either two single-ended loads simultaneously or one mono bridged-tied load. In SE mode, the maximum internal power dissipation is 2 times that of Equation 2. In BTL mode, the maximum internal power dissipation is the result of Equation 3. Even with this substantial increase in power dissipation, the LM4853 does not require heatsinking. The power dissipation from Equation 3 must not be greater than the power dissipation predicted by Equation 4: PDMAX = (TJMAX - TA)/ θJA (4) For the package DGS, θJA = 194°C/W. TJMAX = 150°C for the LM4853. Depending on the ambient temperature, TA, of the surroundings, Equation 4 can be used to find the maximum internal power dissipation supported by the IC packaging. If the result of Equation 3 is greater than that of Equation 4, then either the supply voltage must be decreased, the load impedance increased, or the ambient temperature reduced. For the typical application of a 5V power supply, and an 8Ω bridged load, the maximum ambient temperature possible without violating the maximum junction temperature is approximately 27°C for package DGS. This assumes the device operates at maximum power dissipation and uses surface mount packaging. Internal power dissipation is a function of output power. If typical operation is not around the maximum power dissipation point, operation at higher ambient temperatures is possible. Refer to the Typical Performance Characteristics curves for power dissipation information for different output power levels. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. The value of the pin bypass capacitor, CB, directly affects the LM4853's half-supply voltage stability and PSRR. The stability and supply rejection increase as the bypass capacitor's value increases Typical applications employ a 5V regulator with a 10µF and a 0.1µF bypass capacitors which aid in supply filtering. This does not eliminate the need for bypassing the supply nodes of the LM4853. The selection of bypass capacitors, especially CB, is thus dependent upon desired PSRR requirements, click and pop performance, system cost, and size constraints. SHUTDOWN FUNCTION In order to reduce power consumption while not in use, the LM4853 features amplifier bias circuitry shutdown. This shutdown function is activated by applying a logic high to the SHUTDOWN pin. The trigger point is 2.0V minimum for a logic high level, and 0.8V maximum for a logic low level. It is best to switch between ground and the supply, VDD, to ensure correct shutdown operation. By switching the SHUTDOWN pin to VDD, the LM4853 supply current draw will be minimized in idle mode. Whereas the device will be disabled with shutdown voltages less than VDD, the idle current may be greater than the typical value of 18µA. In either case, the SHUTDOWN pin should be tied to a fixed voltage to avoid unwanted state changes. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 13 LM4853 SNAS155E – JANUARY 2002 – REVISED MAY 2013 www.ti.com In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry. This provides a quick, smooth shutdown transition. Another solution is to use a single-pole, single-throw switch in conjunction with an external pull-up resistor. When the switch is closed, the SHUTDOWN pin is connected to ground and enables the amplifier. If the switch is open, the external pull-up resistor, RPU2 will disable the LM4853. This scheme ensures that the SHUTDOWN pin will not float, thus preventing unwanted state changes. HP-IN FUNCTION The LM4853 features a headphone control pin, HP-IN, that enables the switching between BTL and SE modes. A logic-low to HP-IN activates the BTL mode, while a logic-high activates the SE mode. Figure 39 shows the implementation of the LM4853's headphone control. The voltage divider formed by RPU1 and RD1 sets the voltage at HP-IN to be approximately 50mV with no headphones plugged into the system. This logic-low voltage at the HP-IN pin enables the BTL mode When a set of headphones is plugged into the system, the headphone jack's contact pin is disconnected from the signal pin. This also interrupts the voltage divider set up by the resistors RPU1 and RD1. Resistor RPU1 applies VDD to the HP-IN pin, switching the LM4853 out of BTL mode and into SE mode. The amplifier then drives the headphones, whose impedance is in parallel with resistors RD1 and RD2. Resistors RD1 and RD2 have negligible effect on the output drive capability since the typical impedance of headphones is 32Ω. Figure 39. Headphone Control Circuit Also shown in Figure 39 are the electrical connections for the headphone jack and plug. A 3-wire plug consists of a Tip, Ring, and Sleave, where the Tip and Ring are audio signal conductors and the Sleave is the common ground return. One control pin for each headphone jack is sufficient to indicate to the control inputs that a user has inserted a plug into the jack and that the headphone mode of operation is desired. To ensure smooth transition from BTL to SE operation, it is important to connect HP-IN and RPU1 to the control pin on the Right Output of the headphone jack. The control pin on the Left Output of the headphone jack should be left open. Connecting the node between the HP-IN and RPU1 to the Left Output control pin may cause unwanted state changes to the HP-IN pin. PROPER SELECTION OF EXTERNAL COMPONENTS Proper selection of external components in applications using integrated power amplifiers is critical for optimum device and system performance. While the LM4853 is tolerant to a variety of external component combinations, consideration must be given to the external component values that maximize overall system quality. The LM4853's unity-gain stability allows a designer to maximize system performance. The LM4853's gain should be set no higher than necessary for any given application. A low gain configuration maximizes signal-to-noise performance and minimizes THD+N. However, a low gain configuration also requires large input signals to obtain a given output power. Input signals equal to or greater than 1VRMS are available from sources such as audio codecs. Please refer to the section, AUDIO POWER AMPLIFIER DESIGN, for a more complete explanation of proper gain selection. 14 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 Selecting Input and Output Capacitor Values Besides gain, one of the major considerations is the closed-loop bandwidth of the amplifier. To a large extent, the bandwidth is dictated by the choice of external components shown in Figure 3. The input coupling capacitor CI and resistor RI form a first order high pass filter that limits low frequency response. CI's value should be based on the desired frequency response weighed against the following: Large value input and output capacitors are both expensive and space consuming for portable designs. Clearly a certain sized capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Thus, large value input and output capacitors may not increase system performance. AUDIO POWER AMPLIFIER DESIGN Design a 1W / 8Ω Bridged Audio Amplifier Given: • Power Output: 1WRMS • Load Impedance 8Ω • Input Level: 1VRMS • Input Impedance: 20kΩ • Bandwidth: 100Hz - 20kHz ± 0.25dB A designer must first determine the minimum supply voltage needed to obtain the specified output power. By extrapolating from the Output Power vs Supply Voltage graphs in the Typical Performance Characteristics section, the supply rail can be easily found. A second way to determine the minimum supply rail is to calculate the required VOPEAK using Equation 5 and add the dropout voltage. This results in Equation 6, where VODTOP and VODBOT are extrapolated from the Dropout Voltage vs Supply Voltage curve in the Typical Performance Characteristics section. (5) (6) VDD ≥ (VOPEAK + (VODTOP + VODBOT)) Using the Output Power vs Supply Voltage graph for an 8Ω load, the minimum supply rail is 4.7V. But since 5V is a standard supply voltage in most applications, it is chosen for the supply rail. Extra supply voltage creates headroom that allows the LM4853 to reproduce peaks in excess of 1W without producing audible distortion. However, the designer must make sure that the chosen power supply voltage and output load does not violate the conditions explained in the POWER DISSIPATION section. Once the power dissipation equations have been addressed, the required differential gain can be determined from Equation 7. (7) (8) RF / RI = AVD / 2 From Equation 6, the minimum AVD is 2.83; use AVD = 3. The desired input impedance was 20kΩ, and with an AVD of 3, using Equation 8 results in an allocation of RI = 20kΩ and RF = 30kΩ. The final design step is to set the amplifier's −3dB frequency bandwidth. To achieve the desired ± 0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one−fifth the lower bandwidth limit and the high frequency response must extend o at least five times the upper bandwidth limit. The variation for both response limits is 0.17dB, well within the ± 0.25dB desired limit. This results in: fL = 100Hz / 5 = 20Hz fH = 20kHz x 5 = 100kHz (9) (10) As stated in the External Components Description section, RI in conjunction with CI create a highpass filter. Find the coupling capacitor's value using Equation 11. CI ≥ 1 / (2πRIfL) CI ≥ 1 / ( 2π × 20kΩ × 20Hz) = 0.397µF (11) (12) Use a 0.39µF capacitor, the closest standard value. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 15 LM4853 SNAS155E – JANUARY 2002 – REVISED MAY 2013 www.ti.com The high frequency pole is determined by the product of the desired high frequency pole, fH, and the differential gain, AVD. With AVD = 3 and fH = 100kHz, the resulting GBWP = 150kHz which is much smaller than the LM4853 GBWP of 10MHz. This difference indicates that a designer can still use the LM4853 at higher differential gains without bandwidth limitations. PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependant on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω trace resistance reduces the output power dissipated by a 4Ω load from 2.0W to 1.95W. This problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. Demonstration Board Layout Figure 40. Recommended MM PC Board Layout: Component-Side SilkScreen 16 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 Figure 41. Recommended MM PC Board Layout: Component-Side Layout Figure 42. Recommended MM PC Board Layout: Bottom-Side Layout Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 17 LM4853 SNAS155E – JANUARY 2002 – REVISED MAY 2013 18 www.ti.com Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 LM4853 www.ti.com SNAS155E – JANUARY 2002 – REVISED MAY 2013 REVISION HISTORY Changes from Revision D (May 2013) to Revision E • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 17 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LM4853 19 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM4853LD/NOPB ACTIVE WSON NHE 14 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 L4853LD LM4853MM/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 G53 LM4853MMX/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 G53 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of