OBSOLETE
LM4854
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LM4854
1.9W Monaural, 85mW Stereo Headphone
Audio Amplifier
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FEATURES
1
•
2
•
•
•
•
•
Fast 0.1ms (typ) and 1.0ms (max) turn-on and
turn-off time
Eliminates SE amplifier output coupling
capacitors
Advanced "click and pop" suppression
circuitry
Stereo headphone amplifier mode
Low-power standby and ultra-low current
micropower shutdown modes
Thermal shutdown protection circuitry
•
•
•
•
2.4V to 5.5V operation
Unity-gain stable
Gain set with external resistors
Space-saving micro SMD package, exposedDAP LLP, and TSSOP
APPLICATIONS
•
•
•
•
PDAs
Notebook computers
Cellular phones
Handheld portable electronic devices
DESCRIPTION
The unity-gain stable LM4854 is both a mono differential output (for bridge-tied loads, or BTL) audio power
amplifier and a single-ended (SE) stereo headphone amplifier. Operating on a single 5V supply, the mono BTL
mode delivers 1.1W (typ) to an 8Ω load, 1.7W (typ) to a 4Ω load (Note 1) at 1% THD+N. In SE stereo mode, the
amplifier will deliver 85mW to 32Ω loads. The LM4854 features a new circuit topology that suppresses output
transients ('click and pops') and eliminates SE-mode output coupling capacitors, saving both component and
board space costs. The LM4854 has three inputs: one pair for a two-channel stereo signal and the third for a
single-channel mono input.
The LM4854 is designed for PDA, cellular telephone, notebook, and other handheld portable applications. It
delivers high quality output power from a surface-mount package and requires few external components. Other
features include an active-low micropower shutdown mode, an "instant-on" low power standby mode, and
thermal shutdown protection.
The LM4854 is available in the very space-efficient 12-lead micro SMD, exposed-DAP LLP for higher power
applications, and TSSOP packages.
NOTE
An LM4854LD that has been properly mounted to a circuit board will deliver 1.7W (typ)
into a 4Ω load.
Table 1. Key Specifications
LLP BTL output power (RL = 3.2Ω and THD+N = 1%)
LLP BTL output power (RL = 4Ω and THD+N = 1%)
LLP BTL output power (RL = 8Ω and THD+N = 1%)
SE output power (RL = 32Ω and THD+N = 1.0%)
VALUE
UNIT
VDD = 3.0V
1.0
W (typ)
VDD = 5.0V
1.9
W (typ)
VDD = 3.0V
900
mW (typ)
VDD = 5.0V
1.7
W (typ)
VDD = 3.0V
380
mW (typ)
VDD = 5.0V
1.1
W (typ)
32
mW (typ)
93
mW (typ)
VDD = 3.0V
VDD = 5.0V
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
OBSOLETE
LM4854
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Table 1. Key Specifications (continued)
Micropower shutdown supply current
Standby supply current
PSRR (f = 1kHz, 3.0V ≤ VDD ≤ 5.0V, Figure 1)
VALUE
UNIT
VDD = 3.0V
0.005
µA (typ)
VDD = 5.0V
0.05
µA (typ)
VDD = 3.0V
16
µA (typ)
VDD = 5.0V
27
µA (typ)
BTL
60
dB (typ)
SE
66
dB (typ)
Typical Application
Figure 1. Typical Audio Amplifier Application Circuit
(Pin out shown for the 12-pin large bump micro SMD IBL package. Consult the "Connection Diagrams"
for the LLP or MT package pin out.)
Connection Diagram
Figure 2. Top View (Bump-side down)
2
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Figure 3. Micro SMD Marking (Top View)
X - Date Code
T - Die Traceability
G - Boomer Family
54 - LM4854IBL
Figure 4. Top View
Figure 5. Top View
U - Fab Code
Z - Plant Code
XY - Date Code
TT - Die Tracebility
Bottom Line - Part Number
Figure 6. Top View
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Figure 7. Top View
Z - Plant Code
XY - Date Code
TT - Die Traceability
Bottom 2 lines - Part Number
Table 2. LM4854IBL Pin Designation
Pin (Bump) Number
Pin Function
A1
L-IN
B1
GND
C1
R-IN
D1
MONO-IN
A2
L-OUT
B2
BYPASS
C2
HP-SENSE
D2
R-OUT
A3
SHUTDOWN
B3
VDD
C3
BTL-OUT
D3
STANDBY
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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Absolute Maximum Ratings
(1) (2)
Supply Voltage
6.0V
−65°C to +150°C
Storage Temperature
−0.3V to VDD + 0.3V
Input Voltage
Power Dissipation (3)
Internally Limited
(4)
ESD Susceptibility
All pins except Pin C3 (IBL), Pin11 (LD/MT)
2000V
Pin C3 (IBL), Pin 11 (LD/MT)
8000V
ESD Susceptibility
(5)
200V
Junction Temperature (TJ)
150°C
Solder Information
Small Outline Package
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
See AN-540 "Surface Mounting and their Effects on Product Reliability" for other methods
of soldering surface-mount devices.
Thermal Resistance
θJA (typ)—BLA12BAB
121°C/W
θJC (typ)—LDA14A
3°C/W
θJA (typ)—LDA14A
(1)
(2)
(3)
(4)
(5)
(6)
42°C/W
(6)
θJC (typ)—MTC14
40°C/W
θJA (typ)—MTC14
109°C/W
All voltages are measured with respect to the GND pin unless other wise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions that guarantee specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good
indication of device performance.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA)/θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4854, see power derating currents for more information.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF-240pF discharged through all pins.
The given θJA is for an LM4854 packaged in an LDA14A with the Exposed-DAP soldered to an exposed 2in2 area of 1oz printed circuit
board copper.
Operating Ratings
(1)
Temperature Range
TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +85°C
2.4V ≤ VDD ≤ 5.5V
Supply Voltage
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions that guarantee specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good
indication of device performance.
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Electrical Characteristics for Entire Amplifier (VDD = 5V)
The following specifications apply for circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4854
Typical
IDD
Quiescent Power Supply Current
(1)
Limit
(2) (3)
Units
(Limits)
VIN = 0V; IO = 0A, No Load
5.0
12
mA max)
VIN = 0V; IO = 0A, 8Ω Load
6.5
15
mA (max)
27
35
µA (max)
ISTBY
Standby Quiescent Power Supply
Current
VSTANDBY = GND
ISD
Shutdown Quiescent Power Supply
Current
VSHUTDOWN = GND
0.05
0.2
µA (max)
VOS
Output Offset Voltage
8Ω Load
2.0
40
mV (max)
PSRR
Power Supply Rejection Ratio
CBYPASS = 1.0µF, RSOURCE = 10Ω
VRIPPLE = 200mVp-p sinewave
BTL, RL = 8Ω, RIN = 10Ω
fIN = 217Hz
fIN = 1kHz
SE, RL = 32Ω, RIN = 10Ω
fIN = 217Hz
fIN = 1kHz
61
63
dB
dB
68
71
dB
dB
CBYPASS = 1.0µF
200
tRSH
Return-from-Shutdown Time
tRST
Return-from-Standby Time
VIH
VIL
(1)
(2)
(3)
6
0.1
ms
1.0
ms(max)
Shutdown or Standby Logic High
Treshold
1.4
V (min)
Shutdown or Standby Logic Low
Treshold
0.4
V (max)
Typicals are measured at 25°C and represent the parametric norm.
Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Datasheet minimum and maximum specification limits are guaranteed by design, test, or statistical analysis.
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Electrical Characteristics Bridged-Mode Operation (VDD = 5V)
The following specifications apply for for the circuit shown in Figure 1 and a measurement bandwith of 20Hz to 80kHz, unless
otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4854
Typical
PO
Output Power (Note 11)
THD+N
S/N
(1)
(2)
(3)
Total Harmonic Distortion+Noise
Signal-to-Noise Ratio
(1)
Limit
(2) (3)
Units
(Limits)
THD = 1% (max); f = 1kHz (Note12)
RL = 3.2Ω (LM4854LD)
RL = 4Ω (LM4854LD)
RL = 8Ω
1.9
1.7
1.1
THD = 10% (max); f = 1kHz (Note12)
RL = 3.2Ω (LM4854LD)
RL = 4Ω (LM4854LD)
RL = 8Ω
2.3
2.1
1.3
W
W
W
20Hz ≤ fIN ≤ 20kHz
RL = 4Ω, PO = 1.0W (LM4854LD)
RL = 8Ω, PO = 400mW
0.3
0.18
%
%
fIN = 1kHz
RL = 4Ω, PO = 1.5W (LM4854LD)
RL = 8Ω, PO = 50mW
0.1
0.08
%
%
90
dB
fIN = 1kHz, CBYPASS = 1.0µF
PO = 900mW, RL = 8Ω
1.0
W
W
W (min)
Typicals are measured at 25°C and represent the parametric norm.
Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Datasheet minimum and maximum specification limits are guaranteed by design, test, or statistical analysis.
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Electrical Characteristics : SE Operation (VDD = 5V)
The following specifications apply for for the circuit shown in Figure 1 and a measurement bandwith of 20Hz to 80kHz, unless
otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4854
Typical
PO
Output Power (Note 11)
THD+N
THD+N
THD+N
THD+N
= 1.0%, f = 1kHz, RL = 32Ω
= 10%, f = 1kHz, RL = 32Ω
= 1.0%, f = 1kHz, RL = 16Ω
= 10%, f = 1kHz, RL = 16Ω
(1)
Limit
93
105
170
200
(2) (3)
85
140
Units
(Limits)
mW(min)
mW
mW(min)
mW
THD+N
Total Harmonic Distortion+Noise
20Hz ≤ fIN ≤ 20kHz
RL = 32Ω, PO = 50mW
0.3
%
VOUT
Output Voltage Swing
THD = 1.0%, RL = 5kΩ
4.0
VP-P
XTALK
Channel Separation
fIN = 1kHz, CBYPASS = 1.0µF, RL = 32Ω
55
dB
S/N
Signal-to-Noise Ratio
fIN = 1kHz, CBYPASS = 1.0µF
PO = 50mW, RL = 32Ω
90
dB
(1)
(2)
(3)
8
Typicals are measured at 25°C and represent the parametric norm.
Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Datasheet minimum and maximum specification limits are guaranteed by design, test, or statistical analysis.
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Electrical Characteristics for Entire Amplifier (VDD = 3.0V)
The following specifications apply for circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4854
Typical
(1)
Limit
(2) (3)
Units
(Limits)
IDD
Quiescent Power Supply Current
VIN = 0V, IO = 0A, 8Ω Load
4.0
10
mA (max)
ISTBY
Standby Quiescent Power Supply
Current
VSTANDBY = GND
16.0
20.0
µA (max)
ISD
Shutdown Current
VSHUTDOWN = GND
0.005
0.02
µA (max)
VOS
Output Offset Voltage
8 Ω Load
2.0
40
mV (max)
PSRR
Power Supply Rejection Ratio
CBYPASS = 1.0µF, RSOURCE = 10Ω
VRIPPLE = 200mVp-p sinewave
BTL, RL = 8Ω, RIN = 10Ω
fIN = 217Hz
fIN = 1kHz
SE, RL = 32Ω, RIN = 10Ω
fIN = 217Hz
fIN = 1kHz
62
62
dB
dB
68
72
dB
dB
CBYPASS = 1.0µF
200
ms
tRSH
Return-from-Shutdown Time
tRST
Return-from-Standby Time
1.0
ms(max)
VIH
Shutdown or Standby Logic High
Treshold
1.4
V (min)
VIL
Shutdown or Standby Logic Low
Treshold
0.4
V (max)
(1)
(2)
(3)
0.1
Typicals are measured at 25°C and represent the parametric norm.
Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Datasheet minimum and maximum specification limits are guaranteed by design, test, or statistical analysis.
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Electrical Characteristics : Bridged-Mode Operation (VDD = 3.0V)
(1) (2)
The following specifications apply for for the circuit shown in Figure 1 and a measurement bandwith of 20Hz to 80kHz, unless
otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4854
Typical
PO
Output Power (Note11)
THD+N
S/N
(1)
(2)
(3)
(4)
10
Total Harmonic Distortion+Noise
Signal-to-Noise Ratio
(3)
Limit
(2) (4)
Units
(Limits)
THD = 1% (max); f = 1kHz (Note11)
RL = 4Ω (LM4854LD)
RL = 8Ω
1.0
380
THD = 10% (max); f = 1kHz (Note11)
RL = 4Ω (LM4854LD)
RL = 8Ω
1.1
530
W
mW
20Hz ≤ fIN ≤ 20kHz
RL = 4Ω, PO = 800mW (LM4854LD)
RL = 8Ω, PO = 150mW
0.3
0.21
%
%
fIN = 1kHz
RL = 4Ω, PO = 500mW (LM4854LD)
RL = 8Ω, PO = 150mW
0.1
0.075
%
%
90
dB
fIN = 1kHz, CBYPASS = 1.0µF
PO = 900mW, RL = 8Ω
350
W
mW (min)
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA)/θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4854, see power derating currents for more information.
Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Typicals are measured at 25°C and represent the parametric norm.
Datasheet minimum and maximum specification limits are guaranteed by design, test, or statistical analysis.
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Electrical Characteristics : SE Operation (VDD = 3.0V)
(1) (2)
The following specifications apply for for the circuit shown in Figure 1 and a measurement bandwith of 20Hz to 80kHz, unless
otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4854
Typical
PO
Output Power (Note 11)
THD+N
THD+N
THD+N
THD+N
= 1.0%, f = 1kHz, RL = 32Ω
= 10%, f = 1kHz, RL = 32Ω
= 1.0%, f = 1kHz, RL = 16Ω
= 10%, f = 1kHz, RL = 16Ω
32
60
57
100
(3)
Limit
Units
(Limits)
(2) (4)
27
38
mW(min)
mW
mW (min)
mW
THD+N
Total Harmonic Distortion+Noise
20Hz ≤ fIN = ≤ 20kHz
RL = 32Ω, PO = 30mW
0.3
%
VOUT
Output Voltage Swing
THD = 0.5%, RL = 5kΩ
2.4
VP-P
XTALK
Channel Separation
fIN = 1kHz, CBYPASS = 1.0µF, RL = 32Ω
55
dB
S/N
Signal-to-Noise Ratio
fIN = 1kHz, CBYPASS = 1.0µF
PO = 30mW, RL = 32Ω
TBD
dB
(1)
(2)
(3)
(4)
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA)/θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4854, see power derating currents for more information.
Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Typicals are measured at 25°C and represent the parametric norm.
Datasheet minimum and maximum specification limits are guaranteed by design, test, or statistical analysis.
External Components Description
See Figure 1.
Components
Functional Description
1.
Ri
This is the inverting input resistance that, along with Rf, sets the closed-loop gain. Input resistance Ri and input
capacitance Ci form a high pass filter. The filter's cutoff frequency is fc = 1/2πRiCi.
2.
Ci
This is the input coupling capacitor. It blocks DC voltage at the amplifier's inverting input. Ci and Ri create a highpass filter.
The filter's cutoff frequency is fc = 1/2πRiCi. Refer to the Application Information section, SELECTING EXTERNAL
COMPONENTS, for an explanation of determining Ci's value.
3.
Rf
This is the feedback resistance that, along with Ri, sets the closed-loop gain.
4.
Cs
The supply bypass capacitor. Refer to the POWER SUPPLY BYPASSING section for information about properly placing,
and selecting the value of, this capacitor.
5.
CB
This capacitor filters the half-supply voltage present on the BYPASS pin. Refer to the Application Information section,
SELECTING EXTERNAL COMPONENTS, for information about properly placing, and selecting the value of, this
capacitor..
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Typical Performance Characteristics
12
THD+N
vs
Frequency
THD+N
vs
Frequency
Figure 8. LM4854LD
VDD = 5V, RL = 4Ω (BTL),
POUT = 1000mW
Figure 9. LM4854LD
VDD = 5V, RL = 4Ω (BTL),
POUT = 400mW
THD+N
vs
Frequency
THD+N
vs
Frequency
Figure 10.
VDD = 5V, RL = 8Ω (BTL),
POUT = 400mW
Figure 11.
VDD = 5V, RL = 16Ω (SE),
POUT = 50mW
THD+N
vs
Frequency
THD+N
vs
Frequency
Figure 12.
VDD = 5V, RL = 32Ω (SE),
POUT = 50mW
Figure 13. LM4854LD
VDD = 3V, RL = 4Ω (BTL),
POUT = 150mW
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Typical Performance Characteristics (continued)
THD+N
vs
Frequency
THD+N
vs
Frequency
Figure 14. VDD = 3V, RL = 8Ω (BTL),
POUT = 150mW
Figure 15. VDD = 3V, RL = 16Ω (SE),
POUT = 30mW
THD+N
vs
Frequency
THD+N
vs
Output Power
Figure 16. VDD = 3V, RL = 32Ω (SE),
POUT = 30mW
Figure 17. LM4854LD
VDD = 5V, RL = 4Ω (BTL),
at (from top to bottom at 200mW)
20kHZ, 20Hz, 1kHz
THD+N
vs
Output Power
THD+N
vs
Output Power
Figure 18.
VDD = 5V, RL = 8Ω (BTL),
at (from top to bottom at 0.2W)
20kHz, 20Hz, 1kHz
Figure 19.
VDD = 5V, RL = 16Ω (SE),
at (from top to bottom at 30mW)
20kHz, 20Hz, 1kHz
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Typical Performance Characteristics (continued)
14
THD+N
vs
Output Power
THD+N
vs
Output Power
Figure 20.
VDD = 5V, RL = 32Ω (SE),
at (from top to bottom at 20mW)
20kHz, 20Hz, 1kHz
Figure 21. LM4854LD
VDD = 3V, RL = 4Ω (BTL),
at (from top to bottom at 200mW)
20kHz, 20Hz, 1kHz
THD+N
vs
Output Power
THD+N
vs
Output Power
Figure 22.
VDD = 3V, RL = 8Ω (BTL),
at (from top to bottom at 0.02W)
20kHz, 20Hz, 1kHz
Figure 23. VDD = 3V, RL = 16Ω (SE),
at (from top to bottom at 20mW)
20kHz, 20Hz, 1kHz
THD+N
vs
Output Power
Output Power
vs Power Supply Voltage
Figure 24. VDD = 3V, RL = 32Ω (SE),
at (from top to bottom at 20mW)
20kHz, 20Hz, 1kHz
Figure 25. RL = 8Ω (BTL), fIN = 1kHz,
at (from top to bottom at 4V)
10% THD+N, 1% THD+N
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Typical Performance Characteristics (continued)
Output Power
vs Power Supply Voltage
PSRR
vs
Frequency
Figure 26. RL = 16Ω (BTL), fIN = 1kHz,
at (from top to bottom at 4V):
10% THD+N, 1% THD+N
Figure 27. LM4854LD
VDD = 5V, RL = 4Ω (BTL),
RSOURCE = 10Ω
PSRR
vs
Frequency
PSRR
vs
Frequency
Figure 28.
VDD = 5V, RL = 8Ω (BTL),
RSOURCE = 10Ω
Figure 29.
VDD = 5V, RL = 16Ω (SE),
RSOURCE = 10Ω
PSRR
vs
Frequency
PSRR
vs
Frequency
Figure 30.
VDD = 5V, RL = 32Ω (SE),
RSOURCE = 10Ω
Figure 31. LM4854LD
VDD = 3V, RL = 4Ω (BTL),
RSOURCE = 10Ω
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Typical Performance Characteristics (continued)
16
PSRR
vs
Frequency
PSRR
vs
Frequency
Figure 32. VDD = 3V, RL = 8Ω (BTL),
RSOURCE = 10Ω
Figure 33. VDD = 3V, RL = 16Ω (SE),
RSOURCE = 10Ω
PSRR
vs
Frequency
Amplifier Power Dissipation
vs Load Power Dissipation
Figure 34. VDD = 3V, RL = 32Ω (SE),
RSOURCE = 10Ω
Figure 35. LM4854IBL/MT, VDD = 5V,
RL = 8Ω (BTL), fIN = 1kHz
Amplifier Power Dissipation
vs Load Power Dissipation
Amplifier Power Dissipation
vs Load Power Dissipation
Figure 36. LM4854IBL/MT, VDD = 5V,
(from top to bottom at 0.04W):
RL = 16Ω (SE), RL = 32Ω (SE), fIN = 1kHz,
both channels driven and loaded
Figure 37. LM4854IBL/MT, VDD = 3V,
RL = 8Ω (BTL), fIN = 1kHz
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Typical Performance Characteristics (continued)
Power Dissipation
Derating Curves
Power Dissipation
Derating Curve
Figure 38. LM4854LD, VDD = 5V,
RL = 8Ω (BTL), fIN = 1kHz,
(from top to bottom at 120°C):
4in2 copper plane heatsink area
1in2 copper plane heatsink area
Figure 39. LM4854IBL, VDD = 5V,
RL = 8Ω (BTL), fIN = 1kHz
Power Dissipation
Derating Curve
Amplifier Power Dissipation
vs Load Power Dissipation
Figure 40. LM4854MT, VDD = 5V,
RL = 8Ω (BTL), fIN = 1kHz
Figure 41. LM4854IBL/MT, VDD = 3V,
(from top to bottom at 0.02W):
RL = 16Ω (SE), RL = 32Ω (SE), fIN = 1kHz,
both channels driven and loaded
Output Power
vs Load Resistance
Output Power
vs Load Resistance
Figure 42. LM4854IBL/MT, BTL Load,
(from top to bottom at 12Ω):
VDD = 5V, THD+N = 10%;
VDD = 5V, THD+N = 1%
VDD = 3V, THD+N = 10%
VDD = 3V, THD+N = 1%
Figure 43. LM4854IBL/MT, SE Load (both channels driven
and loaded),
fIN = 1kHz, (from top to bottom at 12Ω):
VDD = 5V, THD+N = 10%;
VDD = 5V, THD+N = 1%
VDD = 3V, THD+N = 10%
VDD = 3V, THD+N = 1%
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Typical Performance Characteristics (continued)
Channel-to-Channel Crosstalk
vs Frequency
Channel-to-Channel Crosstalk
vs Frequency
Figure 44. VDD = 5V, RL = 16Ω (SE)
A = Left channel driven, right channel measured
B = Right channel driven, left channel measured
Figure 45. VDD = 5V, RL = 32Ω (SE)
A = Left channel driven, right channel measured
B = Right channel driven, left channel measured
Channel-to-Channel Crosstalk
vs Frequency
Channel-to-Channel Crosstalk
vs Frequency
Figure 46. VDD = 3V, RL = 16Ω (SE)
A = Left channel driven, right channel measured
B = Right channel driven, left channel measured
Figure 47. VDD = 3V, RL = 32Ω (SE)
A = Left channel driven, right channel measured
B = Right channel driven, left channel measured
Application Information
ELIMINATING OUTPUT COUPLING CAPACITORS
Typical single-supply audio amplifiers that can switch between driving bridge-tied-load (BTL) speakers and
single-ended (SE) headphones use a coupling capacitor on each SE output. This capacitor blocks the half-supply
voltage to which the output amplifiers are typically biased and couples the audio signal to the headphones. The
signal returns to circuit ground through the headphone jack's sleeve.
The LM4854 eliminates these coupling capacitors. When the LM4854 is configured to drive SE loads, AMP2 is
internally configured to apply VDD/2 to a stereo headphone jack's sleeve. This voltage equals the quiescent
voltage present on the Amp1 and Amp3 outputs that drive the headphones. Headphones driven by the LM4854
operate in a manner very similar to a BTL load. The same DC voltage is applied to each input terminal on a
headphone speaker. This results in no net DC current flow through the speaker. AC current flows through a
headphone speaker as an audio signal's output amplitude increases on one of the speaker's terminal.
When operating as a headphone amplifier, the headphone jack sleeve is not connected to circuit ground, but to
VDD/2. Using the headphone output jack as a line-level output will place the LM4854's one-half supply voltage on
a plug's sleeve connection. Driving a portable notebook computer or audio-visual display equipment is possible.
This presents no difficulty when the external equipment uses capacitively coupled inputs. For the very small
minority of equipment that is DC-coupled, the LM4854 monitors the current supplied by the amplifier that drives
the headphone jack's sleeve. If this current exceeds 500mAPK, the amplifier is shutdown, protecting the LM4854
and the external equipment. For more information, see the section titled 'Single-Ended Output Power
Performance and Measurement Considerations'.
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Figure 48. Typical Audio Amplifier Application Circuit
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4854's exposed-DAP (die attach paddle) package (LD) provides a low thermal resistance between the die
and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the
surrounding PCB copper area heatsink, copper traces, ground plane, and finally, surrounding air. The result is a
low voltage audio power amplifier that produces 1.7W dissipation in a 4Ω load at ≤ 1% THD+N and over 1.9W in
a 3Ω load at 10% THD+N. This high power is achieved through careful consideration of necessary thermal
design. Failing to optimize thermal design may compromise the LM4854's high power performance and activate
unwanted, though necessary, thermal shutdown protection.
The LD package must have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad is then,
ideally, connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink,
and radiation area. Place the heat sink area on either outside plane in the case of a two-sided or multi-layer
PCB. (The heat sink area can also be placed on an inner layer of a multi-layer board. The thermal resistance,
however, will be higher.) Connect the DAP copper pad to the inner layer or backside copper heat sink area with
6 (3 X 2) (LD) vias. The via diameter should be 0.012in - 0.013in with a 1.27mm pitch. Ensure efficient thermal
conductivity by plugging and tenting the vias with plating and solder mask, respectively.
Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and
amplifier share the same PCB layer, a nominal 2.5in2 (min) area is necessary for 5V operation with a 4Ω load.
Heatsink areas not placed on the same PCB layer as the LM4854 should be 5in2 (min) for the same supply
voltage and load resistance. The last two area recommendations apply for 25°C ambient temperature. Increase
the area to compensate for ambient temperatures above 25°C. In all circumstances and under all conditions, the
junction temperature must be held below 150°C to prevent activating the LM4854's thermal shutdown protection.
The LM4854's power de-rating curve in the Typical Performance Characteristics shows the maximum power
dissipation versus temperature. Example PCB layouts for the exposed-DAP TSSOP and LD packages are shown
in the Demonstration Board Layout section. Further detailed and specific information concerning PCB layout
and fabrication and mounting an LD (LLP) is found in National Semiconductor's AN1187.
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PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by a 4Ω load from 1.7W to 1.6W. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 2, the LM4854 consists of three operational amplifiers. In mono mode, AMP1 and AMP2
operate in series to drive a speaker connected between their outputs. In stereo mode, AMP1 and AMP3 are used
to drive stereo headphones or other SE load.
In mono mode, external resistors RfL and RiL set the closed-loop gain of AMP1, whereas two internal 20kΩ
resistors set AMP2's gain at -1. The LM4854 drives a load, such as a speaker, connected between the two
amplifier outputs, L-OUT and BTL-OUT.
Figure 2 shows that AMP1's output serves as AMP2's input. This results in both amplifiers producing signals
identical in magnitude, but 180° out of phase. Taking advantage of this phase difference, a load is placed
between L-OUT and BTL-OUT and driven differentially (commonly referred to as "bridge mode"). This results in a
differential,or BTL, gain of:
AVD = 2(Rf/Ri)
(1)
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped. To ensure minimum output signal clipping when choosing an amplifier's closed-loop gain, refer to the
Audio Power Amplifier Design section.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing AMP1's and AMP2's outputs at half-supply. This eliminates the coupling capacitor that single supply,
single-ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration
forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power
dissipation and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. Equation 2
states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and
driving a specified output load.
PDMAX-SE = (VDD)2/(2π2 RL): Single-Ended
20
(2)
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However, a direct consequence of the increased power delivered to the load by a bridge amplifier is higher
internal power dissipation for the same conditions. The LM4854 has two operational amplifiers driving a mono
bridge load. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended
amplifier. From Equation 3, assuming a 5V power supply and an 8Ω load, the maximum BTL-mode power
dissipation is 317mW.
PDMAX-MONOBTL = 4(VDD)2/(2π2 RL): Bridge Mode
(3)
The maximum power dissipation point given by Equation 3 must not exceed the power dissipation given by
Equation 4:
PDMAX' = (TJMAX - TA)/ θJA
(4)
The LM4854's TJMAX = 150°C. In the IBL package, the LM4854's θJA is 121°C/W. The LM4854's TJMAX = 150°C.
In the LD package soldered to a DAP pad that expands to a copper area of 2.0in2 on a PCB, the LM4854's θJA is
42°C/W. In the MT package, the LM4854's θJA is 109°C/W. At any given ambient temperature TA, use
Equation 4to find the maximum internal power dissipation supported by the IC packaging. Rearranging
Equation 4 and substituting PDMAX for PDMAX' results in Equation 5. This equation gives the maximum ambient
temperature that still allows maximum stereo power dissipation without violating the LM4854's maximum junction
temperature.
TA = TJMAX - PDMAX-MONOBTLθJA
(5)
For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 73°C
for the IBL package.
TJMAX = PDMAX-MONOBTLθJA + TA
(6)
Equation 6 gives the maximum junction temperature TJMAX. If the result violates the LM4854's 150°C, reduce the
maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further
allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 3 is greater than that of Equation 4,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance.) Refer to the
Typical Performance Characteristics curves for power dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected
between the LM4854's supply pins and ground. Do not substitute a ceramic capacitor for the tantalum. Doing so
may cause oscillation. Keep the length of leads and traces that connect capacitors between the LM4854's power
supply pin and ground as short as possible. Connecting a 1µF capacitor, CB, between the BYPASS pin and
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ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The PSRR
improvements increase as the bypass pin capacitor value increases. Too large, however, increases turn-on time
and can compromise the amplifier's click and pop performance. The selection of bypass capacitor values,
especially CB, depends on desired PSRR requirements, click and pop performance (as explained in the section,
Proper Selection of External Components), system cost, and size constraints.
STANDBY
The LM4854 features a low-power, fast turn-on standby mode. Applying a logic-low to the STANDBY pin act
actives the standby mode. When this mode is active, the power supply current decreases to a nominal value of
30µA and the amplifier outputs are muted. Fast turn-on is assured because all bias points remain at the same
voltage as when the part is in fully active operation. The LM4854 returns to fully active operation in 100µs (typ)
after the input voltage on the STANDBY pin switches from a logic low to a logic high.
MICRO-POWER SHUTDOWN
The LM4854 features an active-low micro-power shutdown mode. When active, the LM4854's micro-power
shutdown feature turns off the amplifier's bias circuitry, reducing the supply current. The logic threshold is
typically VDD/2. The low 0.1µA typical shutdown current is achieved by applying a voltage to the SHUTDOWN pin
that is as near to GND as possible. A voltage that is greater than GND may increase the shutdown current.
CONTROLLING STANDBY AND MICROPOWER SHUTDOWN
There are a few methods to control standby or micro-power shutdown. These include using a single-pole, singlethrow switch (SPST), a microprocessor, or a microcontroller. When using a switch, connect a 100kΩ pull-up
resistor between the STANDBY or SHUTDOWN pin and VDD and the SPST switch between the STANDBY or
SHUTDOWN pin and GND. Select normal amplifier operation by opening the switch. Closing the switch applies
GND to the STANDBY or SHUTDOWN pins, activating micro-power shutdown. The switch and resistor
guarantee that the STANDBY or SHUTDOWN pins will not float. This prevents unwanted state changes. In a
system with a microprocessor or a microcontroller, use a digital output to apply the active-state voltage to the
STANDBY or SHUTDOWN pin.
HEADPHONE (SINGLE-ENDED) AMPLIFIER OPERATION
Previous single-supply amplifiers that were designed to drive both BTL and SE loads used a SE (or headphone)
"sense" input. This input typically required two external resistors to bias the sense input to a preset voltage that
selected BTL operation.
The LM4854 has a unique headphone sense circuit that eliminates the external resistors. The amplifier has an
internal comparator that monitors the voltage present on the R-OUT pin. It compares this voltage against the
voltage on the HP-SENSE pin. When these voltages are equal, BTL mode is selected and AMP3 is shutdown
and its output has a very high impedance. When the comparator's input signals are different, (a typical ΔV of
200mV), the comparator's output switches and activates the SE (headphone) mode. AMP3 changes from
shutdown state to an active state and, along with AMP1, drives a stereo load. AMP2 drives the headphone jack
sleeve.
Figure 3 shows the suggested headphone jack electrical connections. The jack is designed to mate with a threewire plug. The plug's tip should carry a stereo signal's left-channel information. The ring adjacent to the tip should
each carry the right-channel signal and the ring furthest from the tip provides the return to AMP2. A switch can
replace the headphone jack contact pin. When the switch shorts the HP-SENSE pin to R-OUT, the bridgeconnected speaker is driven by AMP1 and AMP2. AMP3 is shutdown, its output in a high-impedance state.
When the switch opens, the LM4854 operates in SE stereo mode. If headphone drive is not needed, short the
HP-SENSE pin to the R-OUT pin.
The LM4854's unique headphone sense circuit requires a dual switch headphone jack. A five-terminal
headphone jack, such as the Switchcraft 35RAPC4BH3, is shown in Figure 2. For applications that require an
SPDIF interface in the stereo headphone jack, use a Foxconn 2F1138-TJ-TR.
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Figure 49. Headphone Circuit
Figure 4 shows an optional resistor connected between the amplifier output that drives the headphone jack
sleeve and ground. This resistor provides a ground path that supressed power supply hum. This hum may occur
in applications such as notebook computers in a shutdown condition and connected to an external powered
speaker. The resistor's 100Ω value is a suggested starting point. Its final value must be determined based on the
tradeoff between the amount of noise suppression that may be needed and minimizing the additional current
drawn by the resistor (25mA for a 100Ω resistor and a 5V supply).
Single-Ended Output Power Performance and Measurement Considerations
The LM4854 delivers clean, low distortion SE output power into loads that are greater than 10Ω. As an example,
output power for 16Ω and 32Ω loads are shown in the Typical Performance Characteristic curves. For loads less
than 10Ω, the LM4854 can typically supply 180mW of low distortion power. However, when higher dissipation is
desired in loads less than 10Ω, a dramatic increase in THD+N may occur. This is normal operation and does not
indicate that proper functionality has ceased. When a jump from moderate to excessively high distortion is seen,
simply reducing the output voltage swing will restore the clean, low distortion SE operation.
The dramatic jump in distortion for loads less than 10Ω occurs when current limiting circuitry activates. During SE
operation, AMP2 (refer to Figure 2) drives the headphone sleeve. An on-board circuit monitors this amplifier's
output current. The sudden increase in THD+N is caused by the current limit circuitry forcing AMP2 into a highimpedance output mode. When this occurs, the output waveform has discontinuities that produce large amounts
of distortion. It has been observed that as the output power is steadily increased, the distortion may jump from
5% to greater than 35%. Indeed, 10% THD+N may not actually be achievable.
ESD Protection
As stated in the Absolute Maximum Ratings, the AMP2 output pin has a maximum ESD susceptibility rating of
8000V. For higher ESD voltages, the addition of a PCDN042 dual transil (from California Micro Devices), as
shown in Figure 4, will provide additional protection.
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Figure 50. The PCDN042 provides additional ESD protection beyond the 8000V shown in the Absolute
Maximum Ratings for the AMP2 output
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figure 2). A high value
capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however,
the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below
150Hz. Applications using speakers with this limited frequency response reap little improvement by using large
input capacitor.
The LM4854's advanced output transient suppression circuitry has eliminated the need to select the input
capacitor's value in relation to the BYPASS capacitor's value as was necessary in some previous Boomer
amplifiers. The value of CI is now strictly determined by the desired low frequency response.
As shown in Figure 2, the input resistor (Ri) and the input capacitor (Ci) produce a high pass filter cutoff
frequency that is found using Equation 7.
fc = 1 / (2πRiCi)
(7)
As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation 7 is 0.063µF. The
1.0µF Ci shown in Figure 2 allows the LM4854 to drive high efficiency, full range speaker whose response
extends below 30Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how fast the LM4854 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4854's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 1.0µF along with a small value of Ci
(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 5 times to 7 times the value of Ci. This ensures that output transients are eliminated
when power is first applied or the LM4854 resumes operation after shutdown.
OPTIMIZING CLICK AND POP REDUCTION PERFORMANCE
The LM4854 contains circuitry that eliminates turn-on and shutdown transients ("clicks and pops") and transients
that could occur when switching between BTL speakers and single-ended headphones. For this discussion, turnon refers to either applying the power supply voltage or when the micro-power shutdown mode is deactivated.
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As the VDD/2 voltage present at the BYPASS pin ramps to its final value, the LM4854's internal amplifiers are
configured as unity gain buffers and are disconnected from the L-OUT, BTL-OUT, and R-OUT pins. An internal
current source charges the capacitor connected between the BYPASS pin and GND in a controlled, linear
manner. Ideally, the input and outputs track the voltage applied to the BYPASS pin. The gain of the internal
amplifiers remains unity until the voltage on the bypass pin reaches VDD/2. Once the voltage on the bypass pin is
stable and after a fixed nominal delay of 120ms, the device becomes fully operational and the amplifier outputs
are reconnected to their respective output pins. Although the BYPASS pin current cannot be modified, changing
the size of CB alters the device's turn-on time. There is a linear relationship between the size of CB and the turnon time. Here are some typical turn-on times for various values of CB:
CB (µF)
TON (ms)
0.01
120
0.1
130
0.22
140
0.47
160
1.0
200
2.2
300
In order eliminate "clicks and pops", all capacitors must be discharged before turn-on. Rapidly switching VDD may
not allow the capacitors to fully discharge, which may cause "clicks and pops".
AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 1W into an 8Ω Load
The following are the desired operational parameters:
• Power Output: 1WRMS
• Load Impedance 8Ω
• Input Level: 1VRMS
• Input Impedance: 20kΩ
• Bandwidth: 100Hz - 20kHz ± 0.25dB
The design begins by specifying the minimum supply voltage necessary to obtain the specified output power.
One way to find the minimum supply voltage is to use the Output Power vs Supply Voltage curve in the Typical
Performance Characteristics section. Another way, using Equation 8, is to calculate the peak output voltage
necessary to achieve the desired output power for a given load impedance. To account for the amplifier's dropout
voltage, two additional voltages, based on the Dropout Voltage vs Supply Voltage in the Typical Performance
Characteristics curves, must be added to the result obtained by Equation 8. The result is Equation 9.
(8)
VDD = VOUTPEAK + VODTOP + VODBOT
(9)
The Output Power vs. Supply Voltage graph for an 8Ω load indicates a minimum supply voltage of 4.6V. The
commonly used 5V supply voltage easily meets this. The additional voltage creates the benefit of headroom,
allowing the LM4854 to produce peak output power in excess of 1W without clipping or other audible distortion.
The choice of supply voltage must also not create a situation that violates of maximum power dissipation as
explained above in the Power Dissipation section. After satisfying the LM4854's power dissipation requirements,
the minimum differential gain needed to achieve 1W dissipation in an 8Ω load is found using Equation 10.
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(10)
Thus, a minimum gain of 2.83 allows the LM4854's to reach full output swing and maintain low noise and THD+N
performance. For this example, let AVD = 3. The amplifier's overall gain is set using the input (Ri) and feedback
(Rf) resistors. With the desired input impedance set at 20kΩ, the feedback resistor is found using Equation (11).
Rf / Ri = AVD / 2
(11)
The value of Rf is 30kΩ. The nominal output power is 1.13W.
TThe last step in this design example is setting the amplifier's -3dB frequency bandwidth. To achieve the desired
±0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the
lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth
limit. The gain variation for both response limits is 0.17dB, well within the ±0.25dB-desired limit. The results are
an
fL = 100Hz / 5 = 20Hz
(12)
and an
fL = 20kHz x 5 = 100kHz
(13)
As mentioned in the SELECTING EXTERNAL COMPONENTS section, Ri and Ci create a highpass filter that
sets the amplifier's lower bandpass frequency limit. Find the coupling capacitor's value using Equation (14).
Ci = 1 / (2πRifL)
(14)
The result is
1 / ( 2π × 20kΩ × 20Hz) = 0.397µF
(15)
Use a 0.39µF capacitor, the closest standard value.
The product of the desired high frequency cutoff (100kHz in this example) and the differential gain AVD,
determines the upper passband response limit. With AVD = 3 and fH = 100kHz, the closed-loop gain bandwidth
product (GBWP) is 300kHz. This is less than the LM4854's 3.5MHz GBWP. With this margin, the amplifier can
be used in designs that require more differential gain while avoiding performance restricting bandwidth
limitations.
RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT
Figure 51 through Figure 54 show the recommended four-layer PC board layout that is optimized for the micro
SMD-packaged LM4854 and associated external components. Figure 56 through Figure 55 show the
recommended two-layer PC board layout that is optimized for the TSSOP-packaged LM4854 and associated
external components.Figure 60 through Figure 63 show the recommended four-layer PC board layout that is
optimized for the LLP-packaged LM4854 and associate external components.
These circuits are designed for use with an external 5V supply and 8Ω(min) speakers. These circuit boards are
easy to use. Apply 5V and ground to the board's VDD and GND pads, respectively. Connect a speaker between
the board's L-OUT and BTL-OUT or headphones to the headphone jack (L-OUT and R-OUT outputs).
26
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Product Folder Links: LM4854
OBSOLETE
LM4854
www.ti.com
SNAS160F – MAY 2004 – REVISED MAY 2004
Demonstration Board Layout
Figure 51. Recommended microSMD PC Board Layout:
Component-Side SilkScreen
Figure 52. Recommended microSMD PC Board Layout:
Component-Side Layout
Figure 53. Recommended microSMD PC Board Layout:
Upper Inner-Layer Layout
Figure 54. Recommended microSMD PC Board Layout:
Lower Inner-Layout Layer
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Product Folder Links: LM4854
27
OBSOLETE
LM4854
SNAS160F – MAY 2004 – REVISED MAY 2004
www.ti.com
Figure 55. Recommended MM PC Board Layout:
Bottom_Side Layout
Figure 56. Recommended MT PC Board Layout:
Component-Side SilkScreen
Figure 57. Recommended MT PC Board Layout:
Component-Side Layout
Figure 58. Recommended MT PC Board Layout:
Bottom-Side Layout
28
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Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LM4854
OBSOLETE
LM4854
www.ti.com
SNAS160F – MAY 2004 – REVISED MAY 2004
Figure 59. Recommended LD PC Board Layout:
Component-Side SilkScreen
Figure 60. Recommended LD PC Board Layout:
Component-Side Layout
Figure 61. Recommended LD PC Board Layout:
Upper Inner-Layer Layout
Figure 62. Recommended LD PC Board Layout:
Lower Inner-Layer Layout
Submit Documentation Feedback
Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LM4854
29
OBSOLETE
LM4854
SNAS160F – MAY 2004 – REVISED MAY 2004
www.ti.com
Figure 63. Recommended LD PC Board Layout:
Bottom-Side Layout
30
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Copyright © 2004, Texas Instruments Incorporated
Product Folder Links: LM4854
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