LM4855
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LM4855
Integrated Audio Amplifier System
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FEATURES
DESCRIPTION
•
The LM4855 is an audio power amplifier system
capable of delivering 1.1W (typ) of continuous
average power into a mono 8Ω bridged-tied load
(BTL) with 1% THD+N and 115mW (typ) per channel
of continuous average power into stereo 32Ω BTL
loads with 0.5% THD+N, using a 5V power supply.
1
2
•
•
•
•
•
•
•
1.1W (Typ) Output Power with 8Ω Mono BTL
Load
115mW (Typ) Output Power with Stereo 32Ω
BTL Loads
SPI Programmable 32 Step Digital Volume
Control
Eight Distinct Output Modes
DSBGA and WQFN Surface Mount Packaging
"Click and Pop" Suppression Circuitry
Thermal Shutdown Protection
Low Shutdown Current (0.1uA, Typ)
KEY SPECIFICATIONS
•
•
•
THD+N at 1kHz, 1.1W into 8Ω BTL: 1.0% (Typ)
THD+N at 1kHz, 115mW into 32Ω BTL: 0.5%
(Typ)
Single Supply Operation: 2.6 to 5.0V
The LM4855 features a 32 step digital volume control
and eight distinct output modes. The digital volume
control and output modes are programmed through a
three-wire SPI serial control interface, that allows
flexibility in routing and mixing audio channels.
The LM4855 is designed for cellular phone, PDA, and
other portable handheld applications. It delivers high
quality output power from a surface-mount package
and requires only six external components.
The industry leading DSBGA package only utilizes
2mm x 2.3mm of PCB space, making the LM4855 the
most space efficient audio sub system available
today.
APPLICATIONS
•
•
Moblie Phones
PDAs
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
LM4855
SNAS164C – JUNE 2002 – REVISED MAY 2013
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Typical Application
Figure 1. Typical Audio Amplifier Application Circuit
2
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Connection Diagrams
Figure 3. Top View (Bump-Side Down)
See Package Number YZR0018AAA
Figure 2. WQFN Package Top View
See Package Number NHW0024A
for Exposed-DAP WQFN
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Supply Voltage
6.0V
−65°C to +150°C
Storage Temperature
ESD Susceptibility (3)
2.0kV
ESD Machine model (4)
200V
Junction Temperature (TJ)
Solder Information
150°C
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
θJA (typ) - NHW0024A
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
θJC (typ) - NHW0024A
220°C
42°C/W
3.0°C/W
θJA (typ) - YZR0018AAA
48°C/W (5)
θJC (typ) - YZR0018AAA
23°C/W (5)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then
discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).
The given θJA and θJC are for an LM4855 mounted on a demonstration board with a 4in2 area of 1oz printed circuit board copper ground
plane.
Operating Ratings (1)
Temperature Range
−40°C to 85°C
Supply Voltage VDD
2.6V ≤ VDD ≤ 5.0V
(1)
Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
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5V Electrical Characteristics (1) (2)
The following specifications apply for VDD= 5.0V, TA= 25°C unless otherwise specified.
Symbol
Parameter
Conditions
LM4855
Typical
IDD
Supply Current
(3)
Limits
(4)
Units
(Limits)
Output mode 1
VIN = 0V; No loads
5.7
8
mA (max)
Output mode 1
VIN = 0V; Loaded (Fig.1)
6.7
9
mA (max)
Output modes 2, 3, 4, 5, 6, 7
VIN = 0V; No loads
7.5
11
mA (max)
Output modes 2, 3, 4, 5, 6, 7
VIN = 0V; Loaded (Fig. 1)
8.5
12
mA (max)
ISD
Shutdown Current
Output mode 0
0.1
2.0
µA (max)
VOS
Output Offset Voltage
VIN = 0V
5.0
40
mV (max)
SPKROUT; RL = 4Ω
THD+N = 1%; f = 1kHz, LM4855LQ
1.5
SPKROUT; RL = 8Ω
THD+N = 1%; f = 1kHz
1.1
0.8
W (min)
ROUT and LOUT; RL = 32Ω
THD+N = 0.5%; f = 1kHz
115
70
mW (min)
PO
Output Power
W
SPKROUT
f = 20Hz to 20kHZ
POUT = 400mW; RL = 8Ω
0.5
%
ROUT and LOUT
f = 20Hz to 20kHZ
POUT = 50mW; RL = 32Ω
0.5
%
THD+N
Total Harmonic Distortion Plus Noise
NOUT
Output Noise
A-weighted (5)
29
57
54
dB (min)
Power Supply Rejection Ratio
SPKROUT
VRIPPLE = 200mVPP; f = 217Hz, CB = 1.0µF
All audio inputs terminated into 50Ω;
Output referred Gain (BTL) = 12dB
Output Mode 1, 3, 5, 7
Output Mode 2, 3
62
59
dB (min)
Output Mode 4, 5
57
54
dB (min)
Output Mode 6, 7
54
PSRR
Power Supply Rejection Ratio
ROUTand LOUT
µV
VRIPPLE = 200mVPP; f = 217Hz, CB = 1.0µF
All audio inputs terminated into 50Ω;
Output referred Maximum gain setting
51
dB (min)
VIH
Logic High Input Voltage
1.4
VDD
V (min)
V (max)
VIL
Logic Low Input Voltage
0.4
GND
V (max)
V (min)
(1)
(2)
(3)
(4)
(5)
4
Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to the ground pin, unless otherwise specified.
Typical specifications are specified at +25°C and represent the most likely parametric norm.
Tested limits are ensured to AOQL (Average Outgoing Quality Level).
Please refer to the Output Noise vs Output Mode table in the Typical Performance Characteristics section for more details.
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5V Electrical Characteristics(1)(2) (continued)
The following specifications apply for VDD= 5.0V, TA= 25°C unless otherwise specified.
Symbol
Parameter
Conditions
LM4855
Typical
Digital Volume Range (RIN and LIN)
(3)
Limits
(4)
Units
(Limits)
Input referred minimum gain
-34.5
-35.1
-33.9
dB (min)
dB (max)
Input referred maximum gain
12.0
11.4
12.6
dB (min)
dB (max)
Digital Volume Stepsize
1.5
Digital Volume Stepsize Error
±0.1
±0.6
dB ( max)
dB
dB (min)
dB (max)
Phone_In_IHF Volume
BTL gain from Phone_In _IHF to SPKROUT
12
11.4
12.6
Phone _In_IHF Mute Attenuation
Output Mode 2, 4, 6
80
72
dB (min)
20
15
25
kΩ (min)
kΩ (max)
Maximum gain setting
50
37.5
62.5
kΩ (min)
kΩ (max)
Mininum gain setting
100
75
125
kΩ (min)
kΩ (max)
Maximum gain setting
33.5
25
42
kΩ (min)
kΩ (max)
Mininum gain setting
100
75
125
kΩ (min)
kΩ (max)
170
Phone_In_IHF Input Impedance
Phone_In_HS Input Impedance
RIN and LIN Input Impedance
tSD
Thermal Shutdown Temperature
150
°C (min)
tES
Enable Setup Time (ENB)
20
ns (min)
tEH
Enable Hold Time (ENB)
20
ns (min)
tEL
Enable Low Time (ENB)
30
ns (min)
tDS
Data Setup Time (DATA)
20
ns (min)
tDH
Data Hold Time (DATA)
20
ns (min)
tCS
Clock Setup Time (CLK)
20
ns (min)
tCH
Clock Logic High Time (CLK)
50
ns (min)
tCL
Clock Logic Low Time (CLK)
50
ns (min)
fCLK
Clock Frequency
DC
10
(min)
MHz (max)
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3V Electrical Characteristics (1) (2)
The following specifications apply for VDD= 3.0V, TA= 25°C unless otherwise specified.
Symbol
Parameter
Conditions
LM4855
Typical
Limits
Output mode 1
VIN = 0V; No loads
4.5
7
mA (max)
Output mode 1
VIN = 0V; Loaded (Fig.1)
5.0
8
mA (max)
Output modes 2, 3, 4, 5, 6, 7
VIN = 0V; No loads
6.5
10
mA (max)
Output modes 2, 3, 4, 5, 6, 7
VIN = 0V; Loaded (Fig. 1)
7
11
mA (max)
0.1
2.0
µA (max)
40
mV (max)
(3)
IDD
Supply Current
Units
(Limits)
(4)
ISD
Shutdown Current
Output mode 0
VOS
Output Offset Voltage
VIN = 0V
5.0
SPKROUT; RL = 4Ω
THD+N = 1%; f = 1kHz, LM4855LQ
430
SPKROUT; RL = 8Ω
THD+N = 1%; f = 1kHz
340
300
mW (min)
ROUT and LOUT; RL = 32Ω
THD+N = 0.5%; f = 1kHz
25
20
mW (min)
SPKROUT
f = 20Hz to 20kHZ
POUT = 250mW; RL = 8Ω
0.5
%
ROUT and LOUT
f = 20Hz to 20kHZ
POUT = 20mW; RL = 32Ω
0.5
%
PO
Output Power
mW
THD+N
Total Harmonic Distortion Plus Noise
NOUT
Output Noise
A-weighted (5)
29
58
55
dB (min)
Power Supply Rejection Ratio
SPKROUT
VRIPPLE = 200mVPP; f = 217Hz, CB = 1.0µF
All audio inputs terminated into 50Ω;
Output referred Gain (BTL) = 12dB
Output Mode 1, 3, 5, 7
Power Supply Rejection Ratio
ROUTand LOUT
VRIPPLE = 200mVPP; f = 217Hz, CB = 1.0µF
All audio inputs terminated into 50Ω;
Output referred Maximum gain setting
Output Mode 2, 3
63
60
dB (min)
Output Mode 4, 5
58
55
dB (min)
Output Mode 6, 7
55
52
dB (min)
PSRR
µV
VIH
Logic High Input Voltage
1.4
VDD
V (min)
V (max)
VIL
Logic Low Input Voltage
0.4
GND
V (max)
V (min)
(1)
(2)
(3)
(4)
(5)
6
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
All voltages are measured with respect to the ground pin, unless otherwise specified.
Typical specifications are specified at +25°C and represent the most likely parametric norm.
Tested limits are ensured to AOQL (Average Outgoing Quality Level).
Please refer to the Output Noise vs Output Mode table in the Typical Performance Characteristics section for more details.
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3V Electrical Characteristics(1)(2) (continued)
The following specifications apply for VDD= 3.0V, TA= 25°C unless otherwise specified.
Symbol
Parameter
Conditions
LM4855
Typical
Limits
Input referred minimum gain
-34.5
-35.1
-33.9
dB (min)
dB (max)
Input referred maximum gain
12.0
11.4
12.6
dB (min)
dB (max)
(3)
Digital Volume Range (RIN and LIN)
Units
(Limits)
(4)
Digital Volume Stepsize
1.5
Digital Volume Stepsize Error
±0.1
±0.6
dB ( max)
dB
Phone_In_IHF Volume
BTL gain from Phone_In _IHF to SPKROUT
12
11.4
12.6
dB (min)
dB (max)
Phone _In_IHF Mute Attenuation
Output Mode 2, 4, 6
80
72
dB (min)
20
15
25
kΩ (min)
kΩ (max)
Maximum gain setting
50
37.5
62.5
kΩ (min)
kΩ (max)
Mininum gain setting
100
75
125
kΩ (min)
kΩ (max)
Maximum gain setting
33.5
25
42
kΩ (min)
kΩ (max)
Mininum gain setting
100
75
125
kΩ (min)
kΩ (max)
170
150
°C (min)
Phone_In_IHF Input Impedance
Phone_In_HS Input Impedance
RIN and LIN Input Impedance
tSD
Thermal Shutdown Temperature
tES
Enable Setup Time (ENB)
20
ns (min)
tEH
Enable Hold Time (ENB)
20
ns (min)
tEL
Enable Low Time (ENB)
30
ns (min)
tDS
Data Setup Time (DATA)
20
ns (min)
tDH
Data Hold Time (DATA)
20
ns (min)
tCS
Clock Setup Time (CLK)
20
ns (min)
tCH
Clock Logic High Time (CLK)
50
ns (min)
tCL
Clock Logic Low Time (CLK)
50
ns (min)
fCLK
Clock Frequency
DC
10
(min)
MHz (max)
External Components Description
Components
Functional Description
1.
CIN
This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the amplifier's input terminals.
CIN also creates a highpass filter with the internal resistor Ri (Input Impedance) at fc = 1/(2πRiCIN).
2.
CS
This is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps maintain the LM4855's
PSRR.
3.
CB
This is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4855's PSRR.
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Typical Performance Characteristics
8
THD+N vs Frequency LM4855LQ
THD+N vs Frequency LM4855LQ
Figure 4.
Figure 5.
THD+N vs Frequency
THD+N vs Frequency
Figure 6.
Figure 7.
THD+N vs Frequency
THD+N vs Frequency
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
THD+N vs Frequency
THD+N vs Frequency
Figure 10.
Figure 11.
THD+N vs Frequency
THD+N vs Frequency
Figure 12.
Figure 13.
THD+N vs Output Power LM4855LQ
THD+N vs Output Power LM4855LQ
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
10
THD+N vs Output Power
THD+N vs Output Power
Figure 16.
Figure 17.
THD+N vs Output Power
THD+N vs Output Power
Figure 18.
Figure 19.
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Figure 22.
Figure 23.
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Figure 24.
Figure 25.
Output Power vs Supply Voltage
Output Power vs Supply Voltage
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
12
Output Power vs Load Resistance
Output Power vs Load Resistance
Figure 28.
Figure 29.
Power Dissipation vs Output Power
Power Dissipation vs Output Power
Figure 30.
Figure 31.
Supply Current vs Supply Voltage
Channel Separation
Figure 32.
Figure 33.
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Typical Performance Characteristics (continued)
Frequency Response
Frequency Response
Figure 34.
Figure 35.
Frequency Response
Figure 36.
Table 1. Output Noise vs Output Mode (VDD = 3V, 5V) (1) (2) (3)
Output Mode
SPKROUT
Output Noise (µV)
LOUT/ROUT
Output Noise (µV)
1
29
X
2
X
28 (G1 = 0dB)
31 (G1 = 6dB)
3
29
28 (G1 = 0dB)
31 (G1 = 6dB)
4
X
28 (G2 = 0dB)
38 (G2 = 12dB)
5
29
28(G2 = 0dB)
38 (G2 = 12dB)
6
X
38 (G2 = 0dB)
41 (G1 = 0dB)
48 (G1 = 6dB)
7
29
38 (G2 = 0dB)
41 (G1 = 0dB)
48 (G1 = 6dB)
(1)
(2)
(3)
G1 = gain from PHS to LOUT/ROUT
G2 = gain from LIN/RIN to LOUT/ROUT
A - weighted filter used
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APPLICATION INFORMATION
SPI PIN DESCRIPTION
DATA: This is the serial data input pin.
CLK: This is the clock input pin.
ENB: This is the SPI enable pin and is active-high.
SPI OPERATION DESCRIPTION
The serial data bits are organized into a field which contains 8 bits of data defined by Table 2. The Data 0 to
Data 2 bits determine the output mode of the LM4855 as shown in Table 3. The Data 3 to Data 7 bits determine
the volume level setting as illustrated by Table 4. For each SPI transfer, the data bits are written to the DATA pin
with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the CLK signal. Once all
the data bits have been sampled, ENB transitions from logic-high to logic-low to complete the SPI sequence. All
8 bits must be received before any data latch can occur. Any excess CLK and DATA transitions will be ignored
after the eighth rising clock edge has occurred. For any data sequence longer than 8 bits, only the first 8 bits will
get loaded into the shift register and the rest of the bits will be disregarded.
Table 2. Bit Allocation
Data 0
Mode Select
Data 1
Mode Select
Data 2
Mode Select
Data 3
Volume Control
Data 4
Volume Control
Data 5
Volume Control
Data 6
Volume Control
Data 7
Volume Control
Table 3. Output Mode Selection (1)
Output Mode #
Data 2
Data 1
Data 0
SPKROUT
ROUT
LOUT
0
0
0
0
SD
SD
SD
1
0
0
1
12dB x PIHF
SD
SD
2
0
1
0
MUTE
G1 x PHS
G1 x PHS
3
0
1
1
12dB x PIHF
G1 x PHS
G1 x PHS
4
1
0
0
MUTE
G2 x R
G2 x L
5
1
0
1
12dB x PIHF
G2 x R
G2 x L
6
1
1
0
MUTE
(G1 x PHS) + (G2
x R)
(G1 x PHS) + (G2
x L)
7
1
1
1
12dB x PIHF
(G1 x PHS) + (G2
x R)
(G1 x PHS) + (G2
x L)
(1)
14
R = Rin
L = Lin
PIHF = Phone_In_IHF
PHS = Phone_In_HS
SD = Shutdown Mode
MUTE = Mute Mode
G1 = gain from PHS to LOUT/ROUT
G2 = gain from LIN/ RIN to LOUT/ROUT
Default Mode upon device power-up is Output Mode 0
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Table 4. Volume Control Settings
Gain (dB)
G2
G1
RIN, LIN
to
ROUT, LOUT
Phone_In_HS
to
ROUT, LOUT
-34.5
Data 7
Data 6
Data 5
Data 4
Data 3
-40.5
0
0
0
0
0
-33.0
-39.0
0
0
0
0
1
-31.5
-37.5
0
0
0
1
0
-30.0
-360
0
0
0
1
1
-28.5
-34.5
0
0
1
0
0
-27.0
-33.0
0
0
1
0
1
-25.5
-31.5
0
0
1
1
0
-24.0
-30.0
0
0
1
1
1
-22.5
-28.5
0
1
0
0
0
-21.0
-27.0
0
1
0
0
1
-19.5
-25.5
0
1
0
1
0
-18.0
-24.0
0
1
0
1
1
-16.5
-22.5
0
1
1
0
0
-15.0
-21.0
0
1
1
0
1
-13.5
-19.5
0
1
1
1
0
-12.0
-18.0
0
1
1
1
1
-10.5
-16.5
1
0
0
0
0
-9.0
-15.0
1
0
0
0
1
-7.5
-13.5
1
0
0
1
0
-6.0
-12.0
1
0
0
1
1
-4.5
-10.5
1
0
1
0
0
-3.0
-9.0
1
0
1
0
1
-1.5
-7.5
1
0
1
1
0
0.0
-6.0
1
0
1
1
1
1.5
-4.5
1
1
0
0
0
3.0
-3.0
1
1
0
0
1
4.5
-1.5
1
1
0
1
0
6.0
0
1
1
0
1
1
7.5
1.5
1
1
1
0
0
9.0
3.0
1
1
1
0
1
10.5
4.5
1
1
1
1
0
12.0
6.0
1
1
1
1
1
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SPI OPERATIONAL REQUIREMENTS
1. The data bits are transmitted with the LSB first.
2. The maximum clock rate is 10MHz for the CLK pin.
3. CLK must remain logic-high for at least 50ns (tCH ) after the rising edge of CLK, and CLK must remain logiclow for at least 50ns (tCL) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 20ns
(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 20ns (tDH) after the rising
edge of CLK and stabilize before the next rising edge of CLK.
5. ENB should be logic-high only during serial data transmission.
6. ENB must be logic-high at least 20ns (tES ) before the first rising edge of CLK, and ENB has to remain logichigh at least 20ns (tEH) after the eighth rising edge of CLK.
7. If ENB remains logic-low for more than 10ns before all 8 bits are transmitted then the data latch will be
aborted.
8. If ENB is logic-high for more than 8 CLK pulses then only the first 8 data bits will be latched and activated
when ENB transitions to logic-low.
9. ENB must remain logic-low for at least 30ns (tEL ) to latch in the data.
10. Coincidental rising or falling edges of CLK and ENB are not allowed. If CLK is to be held logic-high after the
data transmission, the falling edge of CLK must occur at least 20ns (tCS) before ENB transitions to logic-high for
the next set of data.
Figure 37. SPI Timing Diagram
16
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EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4855's exposed-DAP (die attach paddle) package (NHW) provides a low thermal resistance between the
die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the
surrounding PCB copper area heatsink, copper traces, ground plane, and finally, surrounding air. The result is a
low voltage audio power amplifier that produces 1.1W dissipation in a 8Ω load at ≤ 1% THD+N. This high power
is achieved through careful consideration of necessary thermal design. Failing to optimize thermal design may
compromise the LM4855's high power performance and activate unwanted, though necessary, thermal shutdown
protection.
The NHW package must have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad is
then, ideally, connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat
sink, and radiation area. Place the heat sink area on either outside plane in the case of a two-sided or multi-layer
PCB. (The heat sink area can also be placed on an inner layer of a multi-layer board. The thermal resistance,
however, will be higher.) Connect the DAP copper pad to the inner layer or backside copper heat sink area with
6 (3 X 2) (NHW) vias. The via diameter should be 0.012in - 0.013in with a 1.27mm pitch. Ensure efficient thermal
conductivity by plugging and tenting the vias with plating and solder mask, respectively.
Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and
amplifier share the same PCB layer, a nominal 2.5in2 (min) area is necessary for 5V operation with a 4Ω load.
Heatsink areas not placed on the same PCB layer as the LM4855 should be 5in2 (min) for the same supply
voltage and load resistance. The last two area recommendations apply for 25°C ambient temperature. Increase
the area to compensate for ambient temperatures above 25°C. In all circumstances and under all conditions, the
junction temperature must be held below 150°C to prevent activating the LM4855's thermal shutdown protection.
Further detailed and specific information concerning PCB layout and fabrication and mounting an NHW (WQFN)
is found in TI's AN1187.
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω
LOADS
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by a 4Ω load from 1.7W to 1.6W. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 1, the LM4855 consists of three pairs of output amplifier blocks (A4-A6). A4, A5, and A6
consist of bridged-tied amplifier pairs that drive LOUT, ROUT, and SPKROUT respectively. The LM4855 drives a
load, such as a speaker, connected between outputs, SPKROUT+ and SPKROUT-. In the amplifier block A6, the
output of the amplifier that drives SPKROUT- serves as the input to the unity gain inverting amplifier that drives
SPKROUT+.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage
of this phase difference, a load is placed between SPKROUT- and SPKROUT+ and driven differentially
(commonly referred to as 'bridge mode'). This results in a differential or BTL gain of:
AVD = 2(Rf/Ri) = 2
(1)
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Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing SPKROUT- and SPKROUT+ outputs at half-supply. This eliminates the coupling capacitor that single
supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended
configuration forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC
power dissipation and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM4855 has a pair of bridged-tied amplifiers driving a handsfree speaker, SPKROUT. The
maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From
Equation (2), assuming a 5V power supply and an 8Ω load, the maximum SPKROUT power dissipation is
634mW.
PDMAX-SPKROUT = 4(VDD)2/(2π2 RL): Bridge Mode
(2)
The LM4855 also has 2 pairs of bridged-tied amplifiers driving stereo headphones, ROUT and LOUT. The
maximum internal power dissipation for ROUT and LOUT is given by equation (3) and (4). From Equations (3)
and (4), assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is
158mW, or 316mW total.
PDMAX-LOUT = 4(VDD)2/(2π2 RL): Bridge Mode
PDMAX-ROUT = 4(VDD)2/(2π2 RL): Bridge Mode
(3)
(4)
The maximum internal power dissipation of the LM4855 occurs when all 3 amplifiers pairs are simultaneously on;
and is given by Equation (5).
PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT
(5)
The maximum power dissipation point given by Equation (5) must not exceed the power dissipation given by
Equation (6):
PDMAX' = (TJMAX - TA)/ θJA
(6)
The LM4855's TJMAX = 150°C. In the YZR package, the LM4855's θJA is 48°C/W. In the NHW package soldered
to a DAP pad that expands to a copper area of 2.5in2 on a PCB, the LM4855's θJA is 42°C/W. At any given
ambient temperature TA, use Equation (6) to find the maximum internal power dissipation supported by the IC
packaging. Rearranging Equation (6) and substituting PDMAX-TOTAL for PDMAX' results in Equation (7). This
equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without
violating the LM4855's maximum junction temperature.
TA = TJMAX - PDMAX-TOTALθJA
(7)
For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 104°C
for the YZR package.
TJMAX = PDMAX-TOTAL θJA + TA
(8)
Equation (8) gives the maximum junction temperature TJMAX. If the result violates the LM4855's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation (5) is greater than that of Equation (6),
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
18
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copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance.) Refer to the
Typical Performance Characteristics curves for power dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected
between the LM4855's supply pins and ground. Keep the length of leads and traces that connect capacitors
between the LM4855's power supply pin and ground as short as possible. Connecting a 1µF capacitor, CB,
between the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's
PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however,
increases turn-on time and can compromise the amplifier's click and pop performance. The selection of bypass
capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as
explained in the section Selecting External Components) system cost, and size constraints.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figure 1). A high value
capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however,
the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below
150Hz. Applications using speakers with this limited frequency response reap little improvement by using large
input capacitor.
The internal input resistor (Ri) and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found
using Equation (9).
fc = 1 / (2πRiCi)
(9)
As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation (9) is 0.063µF. The
0.22µF Ci shown in Figure 1 allows the LM4855 to drive high efficiency, full range speaker whose response
extends below 40Hz.
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Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how fast the LM4855 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4855's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 1.0µF along with a small value of Ci
(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 5 times to 7 times the value of Ci. This ensures that output transients are eliminated
when power is first applied or the LM4855 resumes operation after shutdown.
Demonstration Board Layout
20
Figure 38. Recommended YZR PC Board Layout:
Top Silkscreen
Figure 39. Recommended YZR PC Board Layout:
Top Layer
Figure 40. Recommended YZR PC Board Layout:
Middle Layer
Figure 41. Recommended YZR PC Board Layout:
Bottom Layer
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Figure 42. Recommended NHW PC Board Layout:
Top Silkcreen Layer
Figure 43. Recommended NHW PC Board Layout:
Top Layer
Figure 44. Recommended NHW PC Board Layout:
Inner Layer 1
Figure 45. Recommended NHW PC Board Layout:
Inner Layer 2
Figure 46. Recommended NHW PC Board Layout:
Bottom Layer
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REVISION HISTORY
Changes from Revision B (May 2013) to Revision C
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM4855LQ/NOPB
ACTIVE
WQFN
NHW
24
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L4855LQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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