LM4859
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LM4859
SNAS256E – MAY 2004 – REVISED MAY 2013
Stereo 1.2W Audio Sub-system with 3D
Enhancement
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FEATURES
KEY SPECIFICATIONS
•
•
•
•
1
2
•
•
•
•
•
•
•
Stereo Speaker Amplifier
Stereo Headphone Amplifier
Independent Left, Right, and Mono Volume
Controls
Texas Instruments 3D Enhancement
I2C Compatible Interface
Ultra Low Shutdown Current
Click and Pop Suppression Circuit
10 Distinct Output Modes
Thermal Shutdown Protection
Available in DSBGA and UQFN packages
APPLICATIONS
•
•
•
•
•
Cell Phones
PDAs
Portable Gaming Devices
Internet Appliances
Portable DVD/CD/AAC/MP3 Players
•
•
•
•
•
POUT, Stereo Loudspeakers, 4Ω, 5V,
1% THD+N (LM4859SP), 1.6W (Typ)
POUT, Stereo Loudspeakers, 8Ω, 5V,
1% THD+N, 1.2W (Typ)
POUT, Stereo Headphones, 32Ω, 5V,
1% THD+N, 75mW (typ)
POUT, Stereo Loudspeakers, 8Ω, 3.3V,
1% THD+N, 495mW (typ)
POUT, Stereo Headphones, 32Ω, 3.3V,
1% THD+N, 33mW (typ)
Shutdown Current, 0.06μA (typ)
DESCRIPTION
The LM4859 is an integrated audio sub-system
designed for stereo cell phone applications.
Operating on a 3.3V supply, it combines a stereo
speaker amplifier delivering 495mW per channel into
an 8Ω load and a stereo headphone amplifier
delivering 33mW per channel into a 32Ω load. It
integrates the audio amplifiers, volume control, mixer,
power management control, and Texas Instruments
3D enhancement all into a single package. In
addition, the LM4859 routes and mixes the stereo
and mono inputs into 10 distinct output modes. The
LM4859 is controlled through an I2C compatible
interface. Other features include an ultra-low current
shutdown mode and thermal shutdown protection.
Boomer audio power amplifiers are designed
specifically to provide high quality output power with a
minimal amount of external components.
The LM4859 is available in a 30–bump TL package
and a 28–lead UQFN package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LM4859
SNAS256E – MAY 2004 – REVISED MAY 2013
www.ti.com
Typical Application
Figure 1. Typical Audio Amplifier Application Circuit
Connection Diagram
Figure 2. 30 Bump DSBGA Package
Top View
(Bump-side down)
See Package Number YZR0030
2
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PIN CONNECTIONS (DSBGA)
Pin
Name
Pin Description
A1
RLS+
Right Loudspeaker Positive Output
A2
VDD
Power Supply
A3
SDA
Data
A4
RHP3D
Right Headphone 3D
A5
RHP
Right Headphone Output
B1
GND
Ground
B2
I2CVDD
I2C Interface Power Supply
B3
ADR
I2C Address Select
B4
LHP3D
Left Headphone 3D
B5
VDD
Power Supply
C1
RLS-
Right Loudspeaker Negative Output
C2
NC
No Connect
C3
SCL
Clock
C4
NC
No Connect
C5
GND
Ground
D1
LLS-
Left Loudspeaker Negative Output
D2
VDD
Power Supply
D3
MIN
Mono Input
D4
NC
No Connect
D5
NC
No Connect
E1
GND
Ground
E2
BYPASS
Half-supply bypass
E3
LLS3D
Left Loudspeaker 3D
E4
RIN
Right Stereo Input
E5
NC
No Connect
F1
LLS+
Left Loudspeaker Positive Output
F2
VDD
Power Supply
F3
RLS3D
Right Loudspeaker 3D
F4
LIN
Left Stereo Input
F5
LHP
Left Headphone Output
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ADR
SDA
26
25
24
3
19
RLS-
GND
4
18
VDD
NC
5
17
LLS-
NC
6
16
GND
LHP
7
15
14
LLS+
RIN
9
10
11
12
13
VDD
GND
NC
BYPASS
VDD
20
LLS3D
RLS+
2
RLS3D
22
21
LIN
1
MIN
RHP
8
23
VDD
SCL
27
2
RHP3D
28
I CVDD
LHP3D
Connection Diagram
Figure 3. 28 – Lead UQFN Package, Top View
See Package Number NJD0028A
PIN CONNECTIONS (UQFN)
Pin
Name
Pin Description
1
RHP
Right Headphone Output
2
VDD
Power Supply
3
NC
No Connect
4
GND
Ground
5
NC
No Connect
6
NC
No Connect
7
LHP
Left Headphone Output
8
RIN
Right Stereo Input
9
LIN
Left Stereo Input
10
MIN
Mono Input
11
LLS3D
Left Loudspeaker 3D
12
RLS3D
Right Loudspeaker 3D
13
BYPASS
Half-supply bypass
14
VDD
Power Supply
15
LLS+
Left Loudspeaker Positive Output
16
GND
Ground
17
LLS-
Left Loudspeaker Negative Output
18
VDD
Power Supply
19
RLS-
Right Loudspeaker Negative Output
20
GND
Ground
21
RLS+
Right Loudspeaker Positive Output
22
VDD
Power Supply
23
I CVDD
I2C Interface Power Supply
24
SDA
Data
25
ADR
I2C Address Select
26
SCL
Clock
27
RHP3D
Right Headphone 3D
28
LHP3D
Left Headphone 3D
4
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Supply Voltage
6.0V
−65°C to +150°C
Storage Temperature
−0.3V to VDD +0.3V
Input Voltage
(3)
Internally Limited
ESD Susceptibility (4)
2000V
ESD Susceptibility (5)
200V
Power Dissipation
Junction Temperature (TJ)
150°C
θJA (NJD0028A) (6)
Thermal Resistance
θJC (NJD0028A)
θJA (YZR0030)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
42°C/W
(7)
3°C/W
62°C/W
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4859 operating in Mode 3, 8, or 13 with VDD = 5V, 8Ω stereo loudspeakers and 32Ω stereo headphones,
the total power dissipation is 1.348W. θJA = 62°C/W.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF-240pF discharged through all pins.
The given θJA is for an LM4859SP mounted on a PCB with a 2in2 area of 10oz printed circuit board ground plane.
The given θJA is for an LM4859TL mounted on a PCB with a 2in2 area of 10oz printed circuit board ground plane.
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ +85°C
2.7V ≤ VDD ≤ 5.5V
Supply Voltage
2.5V ≤ I2CVDD ≤ 5.5V
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Audio Amplifier Electrical Characteristics VDD = 5.0V (1)
(2)
The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4859
Typical
(3)
Limits
(4) (5)
Units
(Limits)
VIN = 0V, No load;
LD5 = RD5 = 0 (6)
IDD
Supply Current
ISD
Shutdown Current
PO
Output Power
Mode 4, 9, 14
5
8
mA (max)
Mode 2, 3, 7, 8, 12, 13
13
21
mA (max)
Output mode 0 (6)
0.2
3
µA (max)
LM4859SP
Speaker; THD+N = 1%;
f = 1kHz; 4Ω BTL
1.6
Speaker; THD+N = 1%;
f = 1kHz; 8Ω BTL
1.2
0.9
W (min)
Headphone; THD+N = 1%;
f = 1kHz; 32Ω SE
75
60
mW (min)
W
LD5 = RD5 = 0
THD+N
VOS
Total Harmonic Distortion Plus
Noise
Offset Voltage
Speaker; PO = 400mW;
f = 1kHz; 8Ω BTL
0.05
%
Headphone; PO = 15mW;
f = 1kHz; 32Ω SE
0.04
%
Speaker; LD5 = RD5 = 0
5
40
mV (max)
A-weighted, 0dB gain; (7)
LD5 = RD5 = 0; Audio Inputs Terminated
NOUT
Output Noise
Speaker; Mode 2, 3, 7, 8
27
µV
Speaker; Mode 12, 13
38
µV
Headphone; Mode 3, 4, 8, 9
10
µV
Headphone; Mode 13, 14
14
µV
Speaker; Mode 2, 3, 7, 8
70
dB
Speaker; Mode 12, 13,
64
Headphone; Mode 3, 4, 8, 9
86
Headphone; Mode 13, 14
73
f = 217Hz; Vrip = 200mVpp; CB = 2.2µF;
0dB gain; (7)
LD5 = RD5 = 0; Audio Inputs Terminated
PSRR
Power Supply Rejection Ratio
54
dB (min)
60
dB (min)
dB
LD5 = RD5 = 0
Xtalk
TWU
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
Crosstalk
Wake-up Time
Loudspeaker; PO = 400mW;
f = 1kHz
85
dB
Headphone; PO = 15mW;
f = 1kHz
85
dB
CD5 = 0; CB = 2.2µF
120
ms
CD5 = 1; CB = 2.2µF
230
ms
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are ensured to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I2CVDD.
“0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
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Audio Amplifier Electrical Characteristics VDD = 3.0V (1) (2)
The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4859
Typical
(3)
Limits
(4) (5)
Units
(Limits)
VIN = 0V, No load;
LD5 = RD5 = 0 (6)
IDD
Supply Current
ISD
Shutdown Current
Output Power
PO
PO
Output Power
Mode 4, 9, 14
4.5
7.5
mA (max)
Mode 2, 3, 7, 8, 12, 13
Mode 0 (6)
11.2
19
mA (max)
0.06
2.5
LM4859SP
Speaker; THD+N = 1%;
f = 1kHz; 4Ω BTL
µA (max)
530
Speaker; THD+N = 1%;
f = 1kHz; 8Ω BTL
400
320
mW (min)
Headphone; THD+N = 1%;
f = 1kHz; 32Ω SE
25
20
mW (min)
mW
LD5 = RD5 = 0
THD+N
VOS
Total Harmonic Distortion Plus
Noise
Offset Voltage
Speaker; PO = 200mW;
f = 1kHz; 8Ω BTL
0.05
%
Headphone; PO = 10mW;
f = 1kHz; 32Ω SE
0.04
%
Speaker; LD5 = RD5 = 0
5
40
mV (max)
A-weighted; 0dB gain; (7)
LD5 = RD5 = 0; All Inputs Terminated
NOUT
Output Noise
Speaker; Mode 2, 3, 7, 8
27
µV
Speaker; Mode 12, 13
38
µV
Headphone; Mode 3, 4, 8, 9
10
µV
Headphone; Mode 13, 14
14
µV
Speaker; Mode 2, 3, 7, 8
70
dB
Speaker; Mode 12, 13,
65
Headphone; Mode 3, 4, 8, 9
87
Headphone; Mode 13, 14
75
f = 217Hz, Vrip = 200mVpp; CB = 2.2µF;
0dB gain; (7)
LD5 = RD5 = 0; All Audio Inputs Terminated
PSRR
Power Supply Rejection Ratio
55
dB (min)
62
dB (min)
dB
LD5 = RD5 = 0
Xtalk
TWU
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Crosstalk
Wake-up Time
Loudspeaker; PO = 200mW;
f = 1kHz
82
dB
Headphone; PO = 10mW;
f = 1kHz
82
dB
CD5 = 0; CB = 2.2µF
80
ms
CD5 = 1; CB = 2.2µF
140
ms
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are ensured to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I2CVDD.
“0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
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Volume Control Electrical Characteristics (1) (2)
The following specifications apply for VDD = 5.0V and VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4859
Typical
(3)
Limits
6
5.5
6.5
dB (min)
dB (max)
minimum gain setting
-40.5
-41
-40
dB (min)
dB (max)
maximum gain setting
12
11.5
12.5
dB (min)
dB (max)
minimum gain setting
-34.5
-35
-34
dB (min)
dB (max)
+/-0.5
dB (max)
Mono Volume Control Range
Volume Control Step Size
1.5
dB
Volume Control Step Size Error
+/-0.2
Stereo Channel to Channel Gain
Mismatch
0.3
dB
85
dB
Mute Attenuation
Mode 12, Vin = 1VRMS
Headphone
maximum gain setting
33.5
25
42
kΩ (min)
kΩ (max)
minimum gain setting
100
75
125
kΩ (min)
kΩ (max)
maximum gain setting
20
15
25
kΩ (min)
kΩ (max)
minimum gain setting
98
73
123
kΩ (min)
kΩ (max)
LIN and RIN Input Impedance
MIN Input Impedance
(3)
(4)
(5)
Units
(Limits)
maximum gain setting
Stereo Volume Control Range
(1)
(2)
(4) (5)
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are ensured to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Control Interface Electrical Characteristics (1) (2)
The following specifications apply for VDD = 5V and VDD = 3V and 2.5V ≤ I2CVDD ≤ 5.5V, unless otherwise specified. Limits
apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4859
Typical
(3)
Limits
(4) (5)
Units
(Limits)
t1
SCL period
2.5
µs (min)
t2
SDA Set-up Time
100
ns (min)
t3
SDA Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition time
100
ns (min)
VIH
Digital Input High Voltage
0.7 x I2CVDD
V (min)
Digital Input Low Voltage
2
V (max)
VIL
(1)
(2)
(3)
(4)
(5)
8
0.3 x I CVDD
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are ensured to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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External Components Description
Components
Functional Description
1.
CIN
This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the amplifier's input
terminals. CIN also creates a high pass filter with the internal resistor Ri (Input Impedance) at fC = 1/(2πRiCIN).
2.
CS
This is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps reduce the noise at
the VDD pin.
3.
CB
This is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4859's PSRR.
4.
COUT
5.
R3D
This resistor sets the gain of the Texas Instruments 3D effect. Please refer to the Texas Instruments 3D
Enhancement section for information on selecting the value of R3D.
6.
C3D
This capacitor sets the frequency at which the Texas Instruments 3D effect starts to occur. Please refer to the Texas
Instruments 3D Enhancement section for information on selecting the value of C3D.
This is the output coupling capacitor. It blocks the DC voltage and couples the output signal to the speaker load RL.
COUT also creates a high pass filter with RL at fO = 1/(2πRLCOUT).
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Typical Performance Characteristics (1)
LM4859SP THD+N vs Frequency
10
5
5
2
2
1
THD+N (%)
1
THD+N (%)
LM4859SP THD+N vs Frequency
10
0.5
0.2
0.5
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01
20
100
1k
0.01
20
10k 20k
100
FREQUENCY (Hz)
VDD = 5V; LLS, RLS; PO = 400mW;
RL = 4Ω; Mode 7; 0dB Gain
Figure 4.
LM4859SP THD+N vs Output Power
10
5
5
2
2
1
1
THD+N (%)
THD+N (%)
LM4859SP THD+N vs Output Power
0.5
0.2
0.5
0.2
0.1
0.1
0.05
0.05
0.02
0.02
50m 100m 200m 500m
1
2
0.01
10m 20m
OUTPUT POWER (W)
VDD = 5V; LLS, RLS; f = 1kHz;
RL = 4Ω; Mode 7; 0dB Gain
(1)
10
Figure 6.
10k 20k
VDD = 3V; LLS, RLS; PO = 200mW;
RL = 4Ω; Mode 7; 0dB Gain
Figure 5.
10
0.01
10m 20m
1k
FREQUENCY (Hz)
50m 100m 200m 500m
1
2
OUTPUT POWER (W)
VDD = 3V; LLS, RLS; f = 1kHz;
RL = 4Ω; Mode 7; 0dB Gain
Figure 7.
“0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
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Typical Performance Characteristics(1) (continued)
THD+N vs Frequency
VDD = 5V; LLS, RLS; PO = 400mW;
RL = 8Ω; Mode 7; 0dB Gain
Figure 8.
THD+N vs Frequency
VDD = 3V; LLS, RLS; PO = 200mW;
RL = 8Ω; Mode 7; 0dB Gain
Figure 9.
THD+N vs Frequency
VDD = 5V; LHP, RHP; PO = 15mW;
RL = 32Ω; Mode 9; 0dB Gain
Figure 10.
THD+N vs Frequency
VDD = 3V; LHP, RHP; PO = 10mW;
RL = 32Ω; Mode 9; 0dB Gain
Figure 11.
THD+N vs Output Power
VDD = 5V; LLS, RLS; f = 1kHz;
RL = 8Ω; Mode 7; 0dB Gain
Figure 12.
THD+N vs Output Power
VDD = 3V; LLS, RLS; f = 1kHz;
RL = 8Ω; Mode 7; 0dB Gain
Figure 13.
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Typical Performance Characteristics(1) (continued)
THD+N vs Output Power
VDD = 5V; LHP, RHP; f = 1kHz;
RL = 32Ω; Mode 9; 0dB Gain
Figure 14.
THD+N vs Output Power
VDD = 3V; LHP, RHP; f = 1kHz;
RL = 32Ω; Mode 9; 0dB Gain
Figure 15.
PSRR vs Frequency
PSRR vs Frequency
VDD = 5V; LLS, RLS; RL = 8Ω; 0db Gain;
All audio inputs terminated
Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8
Figure 16.
VDD = 3V; LLS, RLS; RL = 8Ω; 0db Gain;
All audio inputs terminated
Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8
Figure 17.
PSRR vs Frequency
PSRR vs Frequency
VDD = 5V; LHP, RHP; RL = 32Ω; 0db Gain;
All audio inputs terminated
Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9
Figure 18.
VDD = 3V; LHP, RHP; RL = 32Ω; 0db Gain;
All audio inputs terminated
Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9
Figure 19.
12
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Typical Performance Characteristics(1) (continued)
Crosstalk vs Frequency
Crosstalk vs Frequency
VDD = 5V; LLS, RLS; PO = 400mW; RL = 8Ω;
Mode 7; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
Figure 20.
VDD = 3V; LLS, RLS; PO = 200mW; RL = 8Ω;
Mode 7; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
Figure 21.
Crosstalk vs Frequency
Crosstalk vs Frequency
= 3V; LHP, RHP; PO = 10mW; RL = 32Ω;
Mode 9; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
Figure 23. V
+21
+20
+19
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
20
DD
Frequency vs Response
Frequency vs Response
GAIN (dB)
GAIN (dB)
VDD = 5V; LHP, RHP; PO = 15mW; RL = 32Ω;
Mode 9; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
Figure 22.
50 100 200 500 1k 2k
+14
+13.5
+13
+12.5
+12
+11.5
+11
+10.5
+10
+9.5
+9
+8.5
+8
+7.5
+7
+6.5
+6
20
5k 10k 20k
FREQUENCY (Hz)
5k 10k 20k
FREQUENCY (Hz)
50 100 200 500 1k 2k
LLS, RLS; RL = 8Ω;
Mode 7; Full Gain
LLS, RLS; RL = 8Ω;
Mode 2; Full Gain
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Typical Performance Characteristics(1) (continued)
Figure 24.
Figure 25.
Frequency vs Response
Frequency vs Response
LHP, RHP; RL = 32Ω; CO = 100μF
Mode 4; Full Gain
Figure 26.
LHP, RHP; RL = 32Ω; CO = 100μF
Mode 9; Full Gain
Figure 27.
Power Dissipation vs Output Power
Power Dissipation vs Output Power
HP, RHP; RL = 32Ω; THD+N ≤ 1%
Top-VDD = 5V; Bot-VDD = 3V
per channel
Figure 29. L
LLS, RLS; RL = 8Ω; THD+N ≤ 1%
Top-VDD = 5V; Bot-VDD = 3V
per channel
Figure 28.
Output Power vs Load Resistance
LLS, RLS; RL = 8Ω;
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N;
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
Figure 30.
14
Output Power vs Load Resistance
LHP, RHP; RL = 32Ω;
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N;
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
Figure 31.
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Typical Performance Characteristics(1) (continued)
Output Power vs Supply Voltage
LLS, RLS; RL = 8Ω;
Top–10% THD+N; Bot–1% THD+N
Figure 32.
Output Power vs Supply Voltage
LHP, RHP; RL = 32Ω;
Top–10% THD+N; Bot–1% THD+N
Figure 33.
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APPLICATION INFORMATION
Figure 34. I2C Bus Format
Figure 35. I2C Timing Diagram
Table 1. Chip Address (1)
A7
A6
A5
A4
A3
A2
A1
A0
Chip Address
1
1
1
1
1
0
EC
0
ADR = 0
1
1
1
1
1
0
0
0
ADR = 1
1
1
1
1
1
0
1
0
(1)
EC - externally configured by ADR pin
Table 2. Control Registers
D7
D6
D5
D4
D3
D2
D1
D0
Mono Volume control
0
0
0
MD4
MD3
MD2
MD1
MD0
Left Volume control
0
1
LD5
LD4
LD3
LD2
LD1
LD0
Right Volume control
1
0
RD5
RD4
RD3
RD2
RD1
RD0
Mode control
1
1
CD5
0
CD3
CD2
CD1
CD0
Table 3. Mono Volume Control
16
MD4
MD3
MD2
MD1
MD0
Gain (dB)
0
0
0
0
0
-34.5
0
0
0
0
1
-33.0
0
0
0
1
0
-31.5
0
0
0
1
1
-30.0
0
0
1
0
0
-28.5
0
0
1
0
1
-27.0
0
0
1
1
0
-25.5
0
0
1
1
1
-24.0
0
1
0
0
0
-22.5
0
1
0
0
1
-21.0
0
1
0
1
0
-19.5
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Table 3. Mono Volume Control (continued)
MD4
MD3
MD2
MD1
MD0
Gain (dB)
0
1
0
1
1
-18.0
0
1
1
0
0
-16.5
0
1
1
0
1
-15.0
0
1
1
1
0
-13.5
0
1
1
1
1
-12.0
1
0
0
0
0
-10.5
1
0
0
0
1
-9.0
1
0
0
1
0
-7.5
1
0
0
1
1
-6.0
1
0
1
0
0
-4.5
1
0
1
0
1
-3.0
1
0
1
1
0
-1.5
1
0
1
1
1
0.0
1
1
0
0
0
1.5
1
1
0
0
1
3.0
1
1
0
1
0
4.5
1
1
0
1
1
6.0
1
1
1
0
0
7.5
1
1
1
0
1
9.0
1
1
1
1
0
10.5
1
1
1
1
1
12.0
Table 4. Stereo Volume Control
LD4//RD4
LD3//RD3
LD2//RD2
LD1//RD1
LD0//RD0
Gain (dB)
0
0
0
0
0
-40.5
0
0
0
0
1
-39.0
0
0
0
1
0
-37.5
0
0
0
1
1
-36.0
0
0
1
0
0
-34.5
0
0
1
0
1
-33.0
0
0
1
1
0
-31.5
0
0
1
1
1
-30.0
0
1
0
0
0
-28.5
0
1
0
0
1
-27.0
0
1
0
1
0
-25.5
0
1
0
1
1
-24.0
0
1
1
0
0
-22.5
0
1
1
0
1
-21.0
0
1
1
1
0
-19.5
0
1
1
1
1
-18.0
1
0
0
0
0
-16.5
1
0
0
0
1
-15.0
1
0
0
1
0
-13.5
1
0
0
1
1
-12.0
1
0
1
0
0
-10.5
1
0
1
0
1
-9.0
1
0
1
1
0
-7.5
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Table 4. Stereo Volume Control (continued)
LD4//RD4
LD3//RD3
LD2//RD2
LD1//RD1
LD0//RD0
Gain (dB)
1
0
1
1
1
-6.0
1
1
0
0
0
-4.5
1
1
0
0
1
-3.0
1
1
0
1
0
-1.5
1
1
0
1
1
0.0
1
1
1
0
0
1.5
1
1
1
0
1
3.0
1
1
1
1
0
4.5
1
1
1
1
1
6.0
Table 5. Mixer and Output Mode
Mode
CD3
CD2
CD1
CD0
Loudspeaker L
Loudspeaker R
Headphone L
Headphone R
0
0
0
0
0
SD
SD
SD
SD
1
0
0
0
1
2
0
0
1
0
2(GM x M)
2(GM x M)
MUTE
MUTE
3
0
0
1
1
2(GM x M)
2(GM x M)
(GM x M)
(GM x M)
4
0
1
0
0
SD
SD
(GM x M)
(GM x M)
5
0
1
0
1
RESERVED
6
0
1
1
0
RESERVED
7
0
1
1
1
2(GL x L)
2(GR x R)
MUTE
MUTE
8
1
0
0
0
2(GL x L)
2(GR x R)
(GL x L)
(GR x R)
SD
SD
(GL x L)
(GR x R)
RESERVED
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
12
1
1
0
0
2(GL x L) + 2(GM
x M)
2(GRx R) + 2(GM
x M)
MUTE
MUTE
13
1
1
0
1
2(GL x L) + 2(GM
x M)
2(GR x R) + 2(GM
x M)
(GL x L) +
(GM x M)
(GR x R) +
(GM x M)
14
1
1
1
0
SD
SD
(GL x L) +
(GM x M)
(GR x R) +
(GM x M)
15
1
1
1
1
RESERVED
RESERVED
RESERVED
M - MIN Input Level
L - LIN Input Level
R - RIN Input Level
GM - Mono Volume Control Gain
GL - Left Stereo Volume Control Gain
GR - Right Stereo Volume Control Gain
SD - Shutdown
MUTE - Mute
Table 6. Texas Instruments 3D Enhancement
LD5
RD5
18
0
Loudspeaker Texas Instruments 3D Off
1
Loudspeaker Texas Instruments 3D On
0
Headphone Texas Instruments 3D Off
1
Headphone Texas Instruments 3D On
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Table 7. Wake-up Time Select
CD5
0
Fast Wake-up Setting
1
Slow Wake-up Setting
I2C COMPATIBLE INTERFACE
The LM4859 uses a serial bus, which conforms to the I2C protocol, to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4859.
The I2C address for the LM4859 is determined using the ADR pin. The LM4859's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1 = 0, if ADR is logic low; and X1 = 1, if ADR is logic high.
If the I2C interface is used to address a number of chips in a system, the LM4859's chip address can be changed
to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 34. The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert
all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM4859 has received the address correctly, then it
holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse,
then the master should abort the rest of the data transfer to the LM4859.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable high.
After the data byte is sent, the master must check for another acknowledge to see if the LM4859 received the
data.
If the master has more data bytes to send to the LM4859, then the master can repeat the previous two steps
until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The
data line should be held high when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM4859's I2C interface is powered up through the I2CVDD pin. The LM4859's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
TEXAS INSTRUMENTS 3D ENHANCEMENT
The LM4859 features a 3D audio enhancement effect that widens the perceived soundstage from a stereo audio
signal. The 3D audio enhancement improves the apparent stereo channel separation whenever the left and right
speakers are too close to one another, due to system size constraints or equipment limitations.
An external RC network, shown in Figure 1, is required to enable the 3D effect. There are separate RC networks
for both the stereo loudspeaker outputs as well as the stereo headphone outputs, so the 3D effect can be set
independently for each set of stereo outputs.
The amount of the 3D effect is set by the R3D resistor. Decreasing the value of R3D will increase the 3D effect.
The C3D capacitor sets the low cutoff frequency of the 3D effect. Increasing the value of C3D will decrease the
low cutoff frequency at which the 3D effect starts to occur, as shown by Equation 1.
f3D(-3dB) = 1 / 2π(R3D)(C3D)
(1)
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Activating the 3D effect will cause an increase in gain by a multiplication factor of (1 + 9kΩ/R3D). Setting R3D to
9kΩ will result in a gain increase by a multiplication factor of (1+ 9kΩ/9kΩ) = 2 or 6dB whenever the 3D effect is
activated. The volume control can be programmed through the I2C compatible interface to compensate for the
extra 6dB increase in gain. For example, if the stereo volume control is set at 0dB (11011 from Table 4) before
the 3D effect is activated, the volume control should be programmed to –6dB (10111 from Table 4) immediately
after the 3D effect has been activated. Setting R3D = 20kΩ and C3D = 0.22μF allows the LM4859 to produce a
pronounced 3D effect with a minimal increase in output noise.
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4859's exposed-DAP (die attach paddle) package (SP) provides a low thermal resistance between the
die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the
surrounding PCB copper area heatsink, copper traces, ground plane, and finally, surrounding air. The result is a
low voltage audio power amplifier that produces 1.6W dissipation in a 4Ω load at ≤ 1% THD+N and over 1.8W in
a 3Ω load at 10% THD+N. This high power is achieved through careful consideration of necessary thermal
design. Failing to optimize thermal design may compromise the LM4859's high power performance and activate
unwanted, though necessary, thermal shutdown protection.
The SP package must have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad is then,
ideally, connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink,
and radiation area. Place the heat sink area on either outside plane in the case of a two-sided or multi-layer
PCB. (The heat sink area can also be placed on an inner layer of a multi-layer board. The thermal resistance,
however, will be higher.) Connect the DAP copper pad to the inner layer or backside copper heat sink area with
9 (3 X 3) (SP) vias. The via diameter should be 0.012in - 0.013in with a 1.27mm pitch. Ensure efficient thermal
conductivity by plugging and tenting the vias with plating and solder mask, respectively.
Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and
amplifier share the same PCB layer, a nominal 2in2 area is necessary for 5V operation with a 4Ω load. Heatsink
areas not placed on the same PCB layer as the LM4859 should be 4in2 for the same supply voltage and load
resistance. The last two area recommendations apply for 25°C ambient temperature. Increase the area to
compensate for ambient temperatures above 25°C. In all circumstances and under all conditions, the junction
temperature must be held below 150°C to prevent activating the LM4859's thermal shutdown protection. An
example PCB layout for the exposed-DAP SP package is shown in the Demonstration Board Layout section.
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω
LOADS
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by a 4Ω load from 1.6W to 1.5W. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
The LM4859 consists of two sets of bridged-tied amplifier pairs that drive the left loudspeaker (LLS) and the right
loudspeaker (RLS). For this discussion, only the LLS bridge-tied amplifier pair will be referred to. The LM4859
drives a load, such as a speaker, connected between outputs, LLS+ and LLS-. In the LLS amplifier block, the
output of the amplifier that drives LLS- serves as the input to the unity gain inverting amplifier that drives LLS+.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage
of this phase difference, a load is placed between LLS- and LLS+ and driven differentially (commonly referred to
as 'bridge mode'). This results in a differential or BTL gain of:
20
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AVD = 2(Rf / Ri) = 2
(2)
Both the feedback resistor, Rf, and the input resistor, Ri, are internally set.
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing LLS- and LLS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, singleended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a
single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation
and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM4859 has 2 sets of bridged-tied amplifier pairs driving LLS and RLS. The maximum internal
power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation 3 and
Equation 4, assuming a 5V power supply and an 8Ω load, the maximum power dissipation for LLS and RLS is
634mW per channel.
PDMAX-LLS = 4(VDD)2/ (2π2 RL): Bridged
PDMAX-RLS = 4(VDD)2/ (2π2 RL): Bridged
(3)
(4)
The LM4859 also has a pair of single-ended amplifiers driving LHP and RHP. The maximum internal power
dissipation for ROUT and LOUT is given by Equation 5 and Equation 6. From Equation 5 and Equation 6,
assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 40mW per
channel.
PDMAX-LHP = (VDD)2 / (2π2 RL): Single-ended
PDMAX-RHP = (VDD)2 / (2π2 RL): Single-ended
(5)
(6)
The maximum internal power dissipation of the LM4859 occurs during output modes 3, 8, and 13 when both
loudspeaker and headphone amplifiers are simultaneously on; and is given by Equation 7.
PDMAX-TOTAL = PDMAX-LLS + PDMAX-RLS + PDMAX-LHP + PDMAX-RHP
(7)
The maximum power dissipation point given by Equation 7 must not exceed the power dissipation given by
Equation 8:
PDMAX' = (TJMAX - TA) / θJA
(8)
The LM4859's TJMAX = 150°C. In the SP package, the LM4859's θJA is 42°C/W. At any given ambient
temperature TA, use Equation 8 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 8 and substituting PDMAX-TOTAL for PDMAX' results in Equation 9. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4859's
maximum junction temperature.
TA = TJMAX - PDMAX-TOTAL θJA
(9)
For a typical application with a 5V power supply, stereo 8Ω loudspeaker load, and the stereo 32Ω headphone
load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the
maximum junction temperature is approximately 93.4°C for the SP package.
TJMAX = PDMAX-TOTAL θJA + TA
(10)
Equation 10 gives the maximum junction temperature TJMAX. If the result violates the LM4859's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
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The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 7 is greater than that of Equation 8,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance.) Refer to the
Typical Performance Characteristics (1) curves for power dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected
between the LM4859's supply pins and ground. Keep the length of leads and traces that connect capacitors
between the LM4859's power supply pin and ground as short as possible.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires a high value input coupling capacitor (Ci in Figure 1). In many
cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 50Hz. Applications using speakers with this limited frequency response reap little
improvement; by using a large input capacitor.
The internal input resistor (Ri) and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found
using Equation 11.
fc = 1 / (2πRiCi)
(11)
As an example when using a speaker with a low frequency limit of 50Hz and Ri = 20kΩ, Ci, using Equation 11 is
0.19µF. The 0.22µF Ci shown in Figure 36 allows the LM4859 to drive high efficiency, full range speaker whose
response extends below 40Hz.
Output Capacitor Value Selection
Amplifying the lowest audio frequencies also requires the use of a high value output coupling capacitor (CO in
Figure 1). A high value output capacitor can be expensive and may compromise space efficiency in portable
design.
The speaker load (RL) and the output capacitor (CO) form a high pass filter with a low cutoff frequency
determined using Equation 12.
fc = 1 / (2πRLCO)
(12)
When using a typical headphone load of RL = 32Ω with a low frequency limit of 50Hz, CO is 99µF.
The 100µF CO shown in Figure 36 allows the LM4859 to drive a headphone whose frequency response extends
below 50Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how fast the LM4859 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4859's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 2.2µF along with a small value of Ci
(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 5 times to 10 times the value of Ci. This ensures that output transients are eliminated
(1)
22
“0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
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when the LM4859 transitions in and out of shutdown mode. Connecting a 2.2µF capacitor, CB, between the
BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The
PSRR improvements increase as the bypass pin capacitor value increases. However, increasing the value of CB
will increase wake-up time. The selection of bypass capacitor value, CB, depends on desired PSRR
requirements, click and pop performance, wake-up time, system cost, and size constraints.
C3DHP
VDD
P1
C3DLS
Ci1
MIN
4.7 k:
4.7 k:
RHP3D
VDD
0.22 PF
R3DLS
RLS3D
1 PF
Audio Input
100 k:
0.22 PF
LHP3D
+
LLS3D
CS
P2
100 k:
R 3DHP
Mono Input
-34.5 dB to
+12 dB
+
0.22 PF
LLS+
8:
LLS-
Audio Input
Ci2
LIN
Left Stereo
Input
-40.5 dB to +6 dB
+
0.22 PF
RLS+
Audio Input
Ci3
National
3D
Right Stereo
Input
-40.5 dB to +6 dB
RIN
+
0.22 PF
8:
Mixer
&
Mode Select
RLS-
LHP
BYPASS
+
CB
Bias
Click/Pop
Suppression
Co1
+
RHP +
2.2 PF
100 PF
VD
I2 C V D
D
D
32:
100 PF
32:
Co2
I2 C V D
D
J2
2
I C
Interface
SCL
SDA
ext VDD
I2 C Interface
6 Pin Header
ADR
VDD
RPU
J1
GND
100 k:
Figure 36. Reference Design Board Schematic
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23
LM4859
SNAS256E – MAY 2004 – REVISED MAY 2013
www.ti.com
Demonstration Board Layout
24
Figure 37. Recommended SP PCB Layout:
Silkscreen Layer
Figure 38. Recommended SP PCB Layout:
Top Layer
Figure 39. Recommended SP PCB Layout:
Mid Layer
Figure 40. Recommended SP PCB Layout:
Bottom Layer
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Product Folder Links: LM4859
LM4859
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SNAS256E – MAY 2004 – REVISED MAY 2013
Revision History
Rev
Date
Description
1.1
6/02/05
Added Modes 9 and 14 into Mode 4 (Conditions)
for the Idd under Elect.Char tables 5V and 3V, then
re-released D/S to the WEB (per Alvin Fok). (MC)
1.2
06/06/06
Edited the DSBGA markings (per Alvin F.), then rereleased D/S to the WEB.
E
5/2/2013
Changed layout of National Data Sheet to TI format
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM4859SP/NOPB
ACTIVE
UQFN
NJD
28
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
L4859SP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
