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LM4891MX/NOPB

LM4891MX/NOPB

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC-8

  • 描述:

    IC AMP AUDIO PWR 1W MONO 8SOIC

  • 数据手册
  • 价格&库存
LM4891MX/NOPB 数据手册
OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 LM4891 Boomer® Audio Power Amplifier Series 1 Watt Audio Power Amplifier Check for Samples: LM4891 FEATURES DESCRIPTION • The LM4891 is an audio power amplifier primarily designed for demanding applications in mobile phones and other portable communication device applications. It is capable of delivering 1 watt of continuous average power to an 8Ω BTL load with less than 1% distortion (THD+N) from a 5VDC power supply. 1 23 • • • • • • • • Available in Space-Saving Packages: Micro SMD, VSSOP, SOIC, and WSON Ultra Low Current Shutdown Mode BTL Output Can Drive Capacitive Loads Improved Pop and Click Circuitry Eliminates Noises During Turn-On and Turn-Off Transitions 2.2 to 5.5V Operation No Output Coupling Capacitors, Snubber Networks or Bootstrap Capacitors Required Thermal Shutdown Protection Unity-Gain Stable External Gain Configuration Capability APPLICATIONS • • • Mobile Phones PDAs Portable Electronic Devices KEY SPECIFICATIONS • • • • PSRR at 217Hz, VDD = 5V, 8Ω Load: 62dB (typ) Power Output at 5.0V & 1% THD: 1.0W (typ) Power Output at 3.3V & 1% THD: 400mW (typ) Shutdown Current: 0.1μA (typ) Boomer® audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. The LM4891 does not require output coupling capacitors or bootstrap capacitors, and therefore is ideally suited for mobile phone and other low voltage applications where minimal power consumption is a primary requirement. The LM4891 features a low-power consumption shutdown mode, which is achieved by driving the shutdown pin with logic high. Additionally, the LM4891 features an internal thermal shutdown protection mechanism. The LM4891 contains advanced pop & click circuitry which eliminates noises which would otherwise occur during turn-on and turn-off transitions. The LM4891 is unity-gain stable and can be configured by external gain-setting resistors. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Boomer is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2013, Texas Instruments Incorporated OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 www.ti.com TYPICAL APPLICATION Figure 1. Typical Audio Amplifier Application Circuit CONNECTION DIAGRAM Figure 2. 8 Bump micro SMD (Top View) Package Number BPA08DDB 2 Figure 3. Small Outline (SOIC) Package (Top View) Package Number D Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 Figure 4. Mini Small Outline (VSSOP) Package (Top View) Package Number NGZ Figure 5. WSON Package (Top View) Package Number NGZ These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 3 OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage (3) 6.0V −65°C to +150°C Storage Temperature −0.3V to VDD +0.3V Input Voltage Power Dissipation (4) (5) ESD Susceptibility Internally Limited (6) 2000V ESD Susceptibility (7) 250V Junction Temperature 150°C Thermal Resistance θJC (SOIC) 35°C/W θJA (SOIC) 150°C/W θJA (micro SMD) 220°C/W θJC (VSSOP) 56°C/W θJA (VSSOP) 190°C/W θJA (WSON) 220°C/W Soldering Information See AN-1112 "DSBGA Wafer Level Chip Scale Package ". See AN-1187 "Leadlesss Leadframe Package (LLP)". (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. If the product is in shutdown mode and VDD exceeds 6V (to a max of 8V VDD), then most of the excess current will flow through the ESD protection circuits. If the source impedance limits the current to a max of 10 mA, then the part will be protected. If the part is enabled when VDD is greater than 5.5V and less than 6.5V, no damage will occur, although operational life will be reduced. Operation above 6.5V with no current limit will result in permanent damage. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4891, see TYPICAL PERFORMANCE CHARACTERISTICS curves for additional information. Maximum power dissipation (PDMAX) in the device occurs at an output power level significantly below full output power. PDMAX can be calculated using Equation 1 shown in the Application section. It may also be obtained from the power dissipation graphs. Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine Model, 220 pF–240 pF discharged through all pins. (2) (3) (4) (5) (6) (7) OPERATING RATINGS Temperature Range TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ 85°C 2.2V ≤ VDD ≤ 5.5V Supply Voltage ELECTRICAL CHARACTERISTICS VDD = 5V (1) (2) (3) The following specifications apply for VDD = 5V, AV = 2, and 8Ω load unless otherwise specified. Limits apply for TA = 25°C. LM4891 Symbol Parameter Conditions Typical (4) IDD (1) (2) (3) (4) (5) 4 Quiescent Power Supply Current VIN = 0V, Io = 0A 4 Limit (5) 10 Units (Limits) mA (max) All voltages are measured with respect to the ground pin, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. For micro SMD only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a maximum of 2µA. Typicals are measured at 25°C and represent the parametric normal. Limits are specified to AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS VDD = 5V(1)(2)(3) (continued) The following specifications apply for VDD = 5V, AV = 2, and 8Ω load unless otherwise specified. Limits apply for TA = 25°C. LM4891 Symbol Parameter Conditions Typical Limit (4) (5) Units (Limits) ISD Shutdown Current Vshutdown = VDD PO Output Power THD = 2% (max); f = 1 kHz THD+N Total Harmonic Distortion+Noise Po = 0.4 Wrms; f = 1kHz 0.1 % PSRR (6) Power Supply Rejection Ratio Vripple = 200mV sine p-p 62 (f = 217Hz) 66 (f = 1kHz) dB (6) 0.1 µA (max) 1 W PSRR is a function of system gain. Specifications apply to the circuit in Figure 1 where AV = 2. Higher system gains will reduce PSRR value by the amount of gain increase. A system gain of 10 represents a gain increase of 14dB. PSRR will be reduced by 14dB and applies to all operating voltages. ELECTRICAL CHARACTERISTICS VDD = 3.3V (1) (2) (3) The following specifications apply for VDD = 5V, AV = 2, and 8Ω load unless otherwise specified. Limits apply for TA = 25°C. LM4891 Symbol Parameter Conditions Typical Limit (4) (5) Units (Limits) IDD Quiescent Power Supply Current VIN = 0V, Io = 0A 3.5 mA (max) ISD Shutdown Current Vshutdown = VDD 0.1 µA (max) PO Output Power THD = 1% (max); f = 1kHz 0.4 W THD+N Total Harmonic Distortion+Noise Po = 0.15Wrms; f = 1kHz 0.1 % Power Supply Rejection Ratio Vripple = 200mV sine p-p 60 (f = 217Hz) 62 (f = 1kHz) dB PSRR (1) (2) (3) (4) (5) (6) (6) All voltages are measured with respect to the ground pin, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. For micro SMD only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a maximum of 2µA. Typicals are measured at 25°C and represent the parametric normal. Limits are specified to AOQL (Average Outgoing Quality Level). PSRR is a function of system gain. Specifications apply to the circuit in Figure 1 where AV = 2. Higher system gains will reduce PSRR value by the amount of gain increase. A system gain of 10 represents a gain increase of 14dB. PSRR will be reduced by 14dB and applies to all operating voltages. ELECTRICAL CHARACTERISTICS VDD = 2.6V (1) (2) (3) The following specifications apply for VDD = 2.6V, AV = 2, and 8Ω Load unless otherwise specified. Limits apply for TA = 25°C. LM4891 Symbol Parameter Conditions Typical (4) Limit (5) Units (Limits) IDD Quiescent Power Supply Current VIN = 0V, Io = 0A 2.6 mA (max) ISD Shutdown Current Vshutdown = VDD 0.1 µA (max) (1) (2) (3) (4) (5) All voltages are measured with respect to the ground pin, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. For micro SMD only, shutdown current is measured in a Normal Room Environment. Exposure to direct sunlight will increase ISD by a maximum of 2µA. Typicals are measured at 25°C and represent the parametric normal. Limits are specified to AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 5 OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS VDD = 2.6V(1)(2)(3) (continued) The following specifications apply for VDD = 2.6V, AV = 2, and 8Ω Load unless otherwise specified. Limits apply for TA = 25°C. LM4891 Symbol Parameter Conditions Typical (4) (5) Units (Limits) PO Output Power ( 8Ω ) Output Power ( 4Ω ) THD = 1% (max); f = 1 kHz THD = 1% (max); f = 1 kHz THD+N Total Harmonic Distortion+Noise Po = 0.1Wrms; f = 1kHz 0.08 % PSRR (6) Power Supply Rejection Ratio Vripple = 200mV sine p-p 44 (f = 217Hz) 44 (f = 1kHz) dB (6) 0.25 0.28 Limit W W PSRR is a function of system gain. Specifications apply to the circuit in Figure 1 where AV = 2. Higher system gains will reduce PSRR value by the amount of gain increase. A system gain of 10 represents a gain increase of 14dB. PSRR will be reduced by 14dB and applies to all operating voltages. EXTERNAL COMPONENTS DESCRIPTION Components (1) (1) 6 Functional Description 1. Ri Inverting input resistance which sets the closed-loop gain in conjunction with Rf. This resistor also forms a high pass filter with Ci at fC= 1/(2π RiCi). 2. Ci Input coupling capacitor which blocks the DC voltage at the amplifiers input terminals. Also creates a highpass filter with Ri at fc = 1/(2π RiCi). Refer to the section, PROPER SELECTION OF EXTERNAL COMPONENTS, for an explanation of how to determine the value of Ci. 3. Rf Feedback resistance which sets the closed-loop gain in conjunction with Ri. 4. CS Supply bypass capacitor which provides power supply filtering. Refer to the POWER SUPPLY BYPASSING section for information concerning proper placement and selection of the supply bypass capacitor. 5. CB Bypass pin capacitor which provides half-supply filtering. Refer to the section, PROPER SELECTION OF EXTERNAL COMPONENTS, for information concerning proper placement and selection of CB. ROUT is measured from each of the output pins to ground. This value represents the parallel combination of the 10k ohm output resistors and the two 20k ohm resistors. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS THD+N vs Frequency at VDD = 5V, 8Ω RL, and PWR = 250mW THD+N vs Frequency at VDD = 3.3V, 8Ω RL, and PWR = 150mW Figure 6. Figure 7. THD+N vs Frequency at VDD = 2.6V, 8Ω RL, and PWR = 100mW THD+N vs Frequency at VDD = 2.6V, 4Ω RL, and PWR = 100mW Figure 8. Figure 9. THD+N vs Power Out @ VDD = 5V, 8Ω RL, 1kHz THD+N vs Power Out @ VDD = 3.3V, 8Ω RL, 1kHz Figure 10. Figure 11. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 7 OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) THD+N vs Power Out @ VDD = 2.6V, 8Ω RL, 1kHz THD+N vs Power Out @ VDD = 2.6V, 4Ω RL, 1kHz Figure 12. Figure 13. Power Supply Rejection Ratio (PSRR) @ VDD = 5V Power Supply Rejection Ratio (PSRR) @ VDD = 5V Input terminated with 10Ω R Input Floating Figure 14. Figure 15. Power Supply Rejection Ratio (PSRR) @ VDD = 2.6V Power Supply Rejection Ratio (PSRR) @ VDD = 3.3V Input terminated with 10Ω R Input terminated with 10Ω R Figure 16. 8 Figure 17. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Power Dissipation vs Output Power VDD = 3.3V Power Dissipation vs Output Power @ VDD = 5V, 1kHz, 8Ω, THD ≤ 1.0% Figure 18. Figure 19. Output Power vs Load Resistance Power Dissipation vs Output Power VDD = 2.6V Figure 20. Figure 21. Supply Current vs Shutdown Voltage Clipping (Dropout) Voltage vs Supply Voltage Figure 22. Figure 23. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 9 OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10 Open Loop Frequency Response VDD = 5V No Load Open Loop Frequency Response VDD = 3V No Load Figure 24. Figure 25. Power Derating Curves (PDMAX = 670mW) Power Derating Curves for 8 Bump microSMD (PDMAX = 670mW) Figure 26. Figure 27. Power Derating - 10 Pin LD Pkg PDMAX = 670mW, 5V, 8Ω Frequency Response vs Input Capacitor Size Figure 28. Figure 29. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Noise Floor Figure 30. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 11 OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION BRIDGE CONFIGURATION EXPLANATION As shown in Figure 1, the LM4891 has two operational amplifiers internally, allowing for a few different amplifier configurations. The first amplifier's gain is externally configurable, while the second amplifier is internally fixed in a unity-gain, inverting configuration. The closed-loop gain of the first amplifier is set by selecting the ratio of Rf to Ri while the second amplifier's gain is fixed by the two internal 20 kΩ resistors. Figure 1 shows that the output of amplifier one serves as the input to amplifier two which results in both amplifiers producing signals identical in magnitude, but out of phase by 180°. Consequently, the differential gain for the IC is AVD= 2 *(Rf/Ri) By driving the load differentially through outputs Vo1 and Vo2, an amplifier configuration commonly referred to as “bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier configuration where one side of the load is connected to ground. A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closedloop gain without causing excessive clipping, please refer to the AUDIO POWER AMPLIFIER DESIGN section. A bridge configuration, such as the one used in LM4891, also creates a second advantage over single-ended amplifiers. Since the differential outputs, Vo1 and Vo2, are biased at half-supply, no net DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, singleended amplifier configuration. Without an output coupling capacitor, the half-supply bias across the load would result in both increased internal IC power dissipation and also possible loudspeaker damage. EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATIONS FOR THE LM4891LD The LM4891LD's exposed-DAP (die attach paddle) package (NGZ) provides a low thermal resistance between the die and the PCB to which the part is mounted and soldered. The LM4891LD package should have its DAP soldered to the grounded copper pad (heatsink) under the NGZ (the NC pins, no connect, and ground pins should also be directly connected to this copper pad-heatsink area). The area of the copper pad (heatsink) can be determined from the NGZ Power Derating graph. If the multiple layer copper heatsink areas are used, then these inner layer or backside copper heatsink areas should be connected to each other with 4 (2 x 2) vias. The diameter for these vias should be between 0.013 inches and 0.02 inches with a 0.050 inch pitch-spacing. Ensure efficient thermal conductivity by plating through and solder-filling the vias. Further detailed information concerning PCB layout, fabrication, and mounting an WSON package is available from Texas Instrument's Package Engineering Group under application note AN1187. POWER DISSIPATION Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. Since the LM4891 has two operational amplifiers in one package, the maximum internal power dissipation is 4 times that of a single-ended amplifier. The maximum power dissipation for a given application can be derived from the power dissipation graphs or from Equation 1. PDMAX = 4*(VDD)2/(2π2RL) (1) It is critical that the maximum junction temperature (TJMAX) of 150°C is not exceeded. TJMAX can be determined from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the thermal resistance of the application can be reduced from a free air value of 150°C/W, resulting in higher PDMAX. Additional copper foil can be added to any of the leads connected to the LM4891. It is especially effective when connected to VDD, GND, and the output pins. Refer to the application information on the LM4891 reference design board for an example of good heat sinking. If TJMAX still exceeds 150°C, then additional changes must be made. These changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of output power. Refer to the TYPICAL PERFORMANCE CHARACTERISTICS curves for power dissipation information for different output powers and output loading. 12 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 POWER SUPPLY BYPASSING As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. Typical applications employ a 5V regulator with 10 µF tantalum or electrolytic capacitor and a ceramic bypass capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of the LM4891. The selection of a bypass capacitor, especially CB, is dependent upon PSRR requirements, click and pop performance (as explained in the section, PROPER SELECTION OF EXTERNAL COMPONENTS), system cost, and size constraints. SHUTDOWN FUNCTION In order to reduce power consumption while not in use, the LM4891 contains a shutdown pin to externally turn off the amplifier's bias circuitry. This shutdown feature turns the amplifier off when a logic high is placed on the shutdown pin. By switching the shutdown pin to VDD, the LM4891 supply current draw will be minimized in idle mode. While the device will be disabled with shutdown pin voltages more than 1.0VDC, the idle current may be greater than the typical value of 0.1µA. (Idle current is measured with the shutdown pin tied to VDD). In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry to provide a quick, smooth transition into shutdown. Another solution is to use a single-pole, single-throw switch in conjunction with an external pull-up resistor. When the switch is closed, the shutdown pin is connected to ground which enables the amplifier. If the switch is open, then the external pull-up resistor to VDD will disable the LM4891. This scheme guarantees that the shutdown pin will not float thus preventing unwanted state changes. PROPER SELECTION OF EXTERNAL COMPONENTS Proper selection of external components in applications using integrated power amplifiers is critical to optimize device and system performance. While the LM4891 is tolerant of external component combinations, consideration to component values must be used to maximize overall system quality. The LM4891 is unity-gain stable which gives the designer maximum system flexibility. The LM4891 should be used in low gain configurations to minimize THD+N values, and maximize the signal to noise ratio. Low gain configurations require large input signals to obtain a given output power. Input signals equal to or greater than 1 Vrms are available from sources such as audio codecs. Please refer to the section, AUDIO POWER AMPLIFIER DESIGN, for a more complete explanation of proper gain selection. Besides gain, one of the major considerations is the closed-loop bandwidth of the amplifier. To a large extent, the bandwidth is dictated by the choice of external components shown in Figure 1. The input coupling capacitor, Ci, forms a first order high pass filter which limits low frequency response. This value should be chosen based on needed frequency response for a few distinct reasons. SELECTION OF INPUT CAPACITOR SIZE Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 100 Hz to 150 Hz. Thus, using a large input capacitor may not increase actual system performance. In addition to system cost and size, click and pop performance is effected by the size of the input coupling capacitor, Ci. A larger input coupling capacitor requires more charge to reach its quiescent DC voltage (nominally 1/2 VDD). This charge comes from the output via the feedback and is apt to create pops upon device enable. Thus, by minimizing the capacitor size based on necessary low frequency response, turn-on pops can be minimized. Besides minimizing the input capacitor size, careful consideration should be paid to the bypass capacitor value. Bypass capacitor, CB, is the most critical component to minimize turn-on pops since it determines how fast the LM4891 turns on. The slower the LM4891's outputs ramp to their quiescent DC voltage (nominally 1/2 VDD), the smaller the turn-on pop. Choosing CB equal to 1.0 µF along with a small value of Ci (in the range of 0.1 µF to 0.39 µF), should produce a virtually clickless and popless shutdown function. While the device will function properly, (no oscillations or motorboating), with CB equal to 0.1 µF, the device will be much more susceptible to turn-on clicks and pops. Thus, a value of CB equal to 1.0 µF is recommended in all but the most cost sensitive designs. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 13 OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 www.ti.com AUDIO POWER AMPLIFIER DESIGN A 1W/8Ω AUDIO AMPLIFIER Given: Power Output 1 Wrms Load Impedance 8Ω Input Level 1 Vrms Input Impedance 20 kΩ Bandwidth 100 Hz–20 kHz ± 0.25 dB A designer must first determine the minimum supply rail to obtain the specified output power. By extrapolating from the Output Power vs Supply Voltage graphs in the TYPICAL PERFORMANCE CHARACTERISTICS section, the supply rail can be easily found. A second way to determine the minimum supply rail is to calculate the required Vopeak using Equation 2 and add the output voltage. Using this method, the minimum supply voltage would be (Vopeak + (VODTOP + VODBOT)), where VODBOT and VODTOP are extrapolated from the Dropout Voltage vs Supply Voltage curve in the TYPICAL PERFORMANCE CHARACTERISTICS section. (2) 5V is a standard voltage, in most applications, chosen for the supply rail. Extra supply voltage creates headroom that allows the LM4891 to reproduce peaks in excess of 1W without producing audible distortion. At this time, the designer must make sure that the power supply choice along with the output impedance does not violate the conditions explained in the POWER DISSIPATION section. Once the power dissipation equations have been addressed, the required differential gain can be determined from Equation 3. (3) AVD = (Rf/Ri) 2 From Equation 3, the minimum AVD is 2.83; use AVD = 3. Since the desired input impedance was 20 kΩ, and with a AVD of 3, a ratio of 1.5:1 of Rf to Ri results in an allocation of Ri = 20 kΩ and Rf = 30 kΩ. The final design step is to address the bandwidth requirements which must be stated as a pair of −3 dB frequency points. Five times away from a −3 dB point is 0.17 dB down from passband response which is better than the required ±0.25 dB specified. fL = 100 Hz/5 = 20 Hz fH = 20 kHz * 5 = 100 kHz As stated in the EXTERNAL COMPONENTS DESCRIPTION section, Ri in conjunction with Ci create a highpass filter. Ci ≥ 1/(2π*20 kΩ*20 Hz) = 0.397 µF; use 0.39 µF The high frequency pole is determined by the product of the desired frequency pole, fH, and the differential gain, AVD. With a AVD = 3 and fH = 100 kHz, the resulting GBWP = 300 kHz which is much smaller than the LM4891 GBWP of 2.5 MHz. This figure displays that if a designer has a need to design an amplifier with a higher differential gain, the LM4891 can still be used without running into bandwidth limitations. 14 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 Figure 31. Higher Gain Audio Amplifier The LM4891 is unity-gain stable and requires no external components besides gain-setting resistors, an input coupling capacitor, and proper supply bypassing in the typical application. However, if a closed-loop differential gain of greater than 10 is required, a feedback capacitor (C4) may be needed as shown in Figure 31 to bandwidth limit the amplifier. This feedback capacitor creates a low pass filter that eliminates possible high frequency oscillations. Care should be taken when calculating the -3dB frequency in that an incorrect combination of R3 and C4 will cause rolloff before 20kHz. A typical combination of feedback resistor and capacitor that will not produce audio band high frequency rolloff is R3 = 20kΩ and C4 = 25pf. These components result in a -3dB point of approximately 320 kHz. Figure 32. Differential Amplifier Configuration for LM4891 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 15 OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 www.ti.com Figure 33. Reference Design Board and Layout - micro SMD LM4891 MICRO SMD BOARD ARTWORK 16 Figure 34. Silk Screen Figure 35. Top Layer Figure 36. Bottom Layer Figure 37. Inner Layer Ground Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 Figure 38. Inner Layer VDD Figure 39. Reference Design Board and PCB Layout Guidelines - VSSOP & SOIC Boards Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 17 OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 LM4891 SOIC DEMO BOARD ARTWORK www.ti.com LM4891 VSSOP DEMO BOARD ARTWORK Figure 40. Silk Screen Figure 43. Silk Screen Figure 41. Top Layer Figure 44. Top Layer Figure 42. Bottom Layer 18 Figure 45. Bottom Layer Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 OBSOLETE LM4891 www.ti.com SNAS122E – MAY 2001 – REVISED APRIL 2013 Table 1. Mono LM4891 Reference Design Boards Bill of Material for all 3 Demo Boards Item Part Number Part Description Qty 1 551011208-001 LM4891 Mono Reference Design Board 1 Ref Designator 10 482911183-001 LM4891 Audio AMP 1 U1 20 151911207-001 Tant Cap 1uF 16V 10 1 C1 21 151911207-002 Cer Cap 0.39uF 50V Z5U 20% 1210 1 C2 25 152911207-001 Tant Cap 1uF 16V 10 1 C3 30 472911207-001 Res 20K Ohm 1/10W 5 3 R1, R2, R3 35 210007039-002 Jumper Header Vertical Mount 2X1 0.100 2 J1, J2 PCB LAYOUT GUIDELINES This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual results will depend heavily on the final layout. GENERAL MIXED SIGNAL LAYOUT RECOMMENDATION POWER AND GROUND CIRCUITS For 2 layer mixed signal design, it is important to isolate the digital power and ground trace paths from the analog power and ground trace paths. Star trace routing techniques (bringing individual traces back to a central point rather than daisy chaining traces together in a serial manner) can have a major impact on low level signal performance. Star trace routing refers to using individual traces to feed power and ground to each circuit or even device. This technique will take require a greater amount of design time but will not increase the final price of the board. The only extra parts required may be some jumpers. SINGLE-POINT POWER / GROUND CONNECTIONS The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can be helpful in minimizing high frequency noise coupling between the analog and digital sections. It is further recommended to put digital and analog power traces over the corresponding digital and analog ground traces to minimize noise coupling. PLACEMENT OF DIGITAL AND ANALOG COMPONENTS All digital components and high-speed digital signals traces should be located as far away as possible from analog components and circuit traces. AVOIDING TYPICAL DESIGN / LAYOUT PROBLEMS Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90 degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise coupling and cross talk. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 19 OBSOLETE LM4891 SNAS122E – MAY 2001 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision D (April 2013) to Revision E • 20 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 19 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: LM4891 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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