LM49100GREVAL

User's Guide SNAA043A – October 2007 – Revised May 2013 AN-1622 LM49100 Evaluation Board» 1 Quick Start Guide 1. Connect the I2C signal generation and interface board to a computer’s parallel port. 2. Apply 2.7V to 5.5V power supply’s positive output to the “VDD” pin on jumper “VDD GND”. Connect the power supply’s ground return to the “GND” pin also on the aforementioned jumper. 3. Connect the supplied 6-wire (one pin is a No Connect) cable between the I2C signal generation and interface board and the 6-pin connector (I2C Interface; one pin is a No Connect) on the LM49100 demonstration board. If logic levels other than those set by VDD are required, jumper J1 needs to be connected and a separate supply applied to the 2–pin header with the I2CVDD pin, with respect to ground. 4. Headphone amplifier output mode: Apply a stereo input audio signal to jumpers Left Input and Right Input. Apply the sources’ +input pins and GND pins, respectively, to the demonstration board. 5. Connect a load (≥16Ω) to header HPL (left headphone) and another load (≥16Ω) to header HPR (right headphone). The HPL pin and HPR pin carries the output signals from the two amplifiers, and each of the other pins connecting to ground making this configuration single-ended connections. 6. Differential mono amplifier output mode: Apply a mono differential input audio signal to jumper Mono Input. Apply the sources’ +input and –input to the middle two pins of the 4-pin jumper. The two outer pins are connected to ground, which are used when the mono input is configured as single-ended instead of differential. 7. Connect the 32Ω load across the two pins (differential) of the Speaker jumper on the demonstration board. 8. Apply power. Make measurements. Enjoy the sound. 2 Introduction To help you investigate and evaluate the LM49100's performance and capabilities, a fully populated demonstration board is available from the Texas Instruments Audio Products Group. This board is shown in Figure 1. Connected to an external power supply (2.7V to 5.5V), a signal source and an I2C controller (or signal source), the LM49100 demonstration board easily demonstrate the amplifier's features. All trademarks are the property of their respective owners. SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback AN-1622 LM49100 Evaluation Board» Copyright © 2007–2013, Texas Instruments Incorporated 1 General Description www.ti.com Figure 1. LM49100 Demonstration Board 3 General Description The LM49100 is a fully integrated audio subsystem capable of delivering 1.275W of continuous average power into a mono 8Ω bridged-tied load (BTL) with 1% THD + N and with a 5V power supply. The LM49100 also has a stereo true-ground headphone amplifier capable of 50mW per channel of continuous average power into a 32Ω single-ended (SE) loads with 1% THD + N. The LM49100 has three input channels. One pair of SE inputs can be used with a stereo signal. The other input channel is fully differential and may be used with a mono input signal. The LM49100 features a 32step digital volume control and ten distinct output modes. The mixer, volume control, and device mode select are controlled through an I2C compatible interface. Thermal overload protection prevent the device from being damaged during fault conditions. Superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. 4 Operating Conditions Temperature Range TMIN ≤ TA ≤ TMAX 2 −40°C ≤ TA ≤ +85°C Supply Voltage VDDLS 2.7V ≤ VDDLS ≤ 5.5V Supply Voltage VDDHP 2.4 V ≤ VDDHP ≤ 2.9V I2C Voltage (VDDI2C ) 1.7V ≤ VDDI2C ≤ 5.5V VDDHP ≤ VDDLS VDDI2C ≤ VDDLS Temperature Range –40°C ≤ TA ≤ 85°C AN-1622 LM49100 Evaluation Board» SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Board Features www.ti.com 5 Board Features The LM49100 demonstration board has all of the necessary connections, using 0.100” headers, to apply the power supply voltage, the audio input signals, and the I2C signal inputs. The amplified audio signal is available on both a stereo headphone jack and auxiliary output connections. Also included with the demonstration board is an I2C signal generation board and software. With this board and the software, the user can easily control the LM49100’s, shutdown function, mute, and stereo volume control. Figure 2 shows the software’s graphical user interface. Figure 2. LM49100 Software User's Interface 6 Schematic Figure 3 shows the LM49100 Demonstration Board schematic. Refer to Table 1 for a list of the connections and their functions. SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback AN-1622 LM49100 Evaluation Board» Copyright © 2007–2013, Texas Instruments Incorporated 3 Connections www.ti.com VDD + VDD Audio Input CIN 1 PF CIN 1 PF Audio Input Class AB +6 dB Mono Input -60 dB - +12 dB MINN 0.22 PF LIN RIN 2 VDDI C LS- GND Mixer & Mode Select Left Input -54 dB - +18 dB 0 dB -12 dB -18 dB -24 dB HPL Right Input -54 dB - +18 dB 0 dB -12 dB -18 dB -24 dB Bias Click/Pop Suppresion BYPASS + VDDLS LS+ 0.22 PF CIN 0.1 PF MINP Audio Input CIN 2.2 PF CB HPR GNDS VDDHP 2.2 PF VDDCP 2 VDDI C VDDCP 2 SDA I2C BUS Charge Pump I C Interface SCL ADDR VIH GND VSSHP VSSCP C1N C1 + C1P 4.7 PF 0.1 PF GNDCP CAVSS VIL 2.2 PF 2.2 PF Figure 3. LM49100 Demonstration Board Schematic 7 Connections Connecting to the world is accomplished through the 0.100” headers on the LM49100 demonstration board. The functions of the different headers are detailed in Table 1. Table 1. LM49100 Demonstration Board Connections Header or Jumper Designation VDD/GND VDDHP/GND Headphone power supply for the headphone amplifier which creates split supplies: for the positive voltage is converted by switch capacitor creating a negative voltage of equal magnitude. J1 A shorted J1 connects VDD directly to I2CVDD. An opened J1 disconnects VDD and I2CVDD. If open, a separate power supply connected to I2CVDD/GND header must be applied. I2CVDD Right Input Left Input Mono Input Address Setting 4 Function or Use Main power supply and ground for the demonstration board. AN-1622 LM49100 Evaluation Board» Header to apply an independent I2C power supply when J1 is open. This is the connection to the amplifier’s single-ended right channel input. This is the connection to the amplifier’s single-ended left channel input. This is the connection to the amplifier’s differential or single-ended left/right mono input. The center two pins are the differential inputs, or single-ended inputs, while the outside pins are the grounds. Used to set the address of the device. Normally set at “Low” on the demonstration board. SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Power Supply Sequencing www.ti.com Table 1. LM49100 Demonstration Board Connections (continued) Header or Jumper Designation 8 Function or Use I2C Interface This is the input connection for the I2C serial clock and serial data signals. The demonstration board has an adjacent I2C label identifying each pin. Speaker Two-pin header used to connect the “+” and “-“ terminals of the mono speaker. HPR This is the connection to the amplifier’s single-ended, ground referenced right channel output. The “HPR” label refers to the output pin and “GND” is the corresponding ground. HPL This is the connection to the amplifier’s single-ended, ground referenced left channel output. The “HPL” label refers to the output pin and “GND” is the corresponding ground. Power Supply Sequencing The LM49100 uses two power supply voltages: VDD for the analog circuitry and I2CVDD, which defines the digital control logic high voltage level. To ensure proper functionality, apply VDD first, followed by I2CVDD. If one power supply is used, VDD and I2CVDD can be connected together. The part will power-up with both channels shutdown, the volume control set to minimum, and the mute function active. 9 I2C Signal Generation Board and Software The I2C signal generation and interface board, along with the LM49100 software, will generate the address byte and the data byte used in the I2C control data transaction. To use the I2C signal generation and interface board, please plug it into a PC’s parallel port (on either a notebook or a desktop computer). The software comes with an installer. To install, unzip the file titled “LM49100_Software.” After the file unzips, double-click the “setup.exe” file. After it launches, follow the installer’s instructions. Setup will create a folder named “LM49100” in the “Program” folder on the “C” disk (if the default is used) along with a shortcut of the same name in the “Programs” folder in the “Start” menu. The LM49100 program includes controls for the amplifier’s volume control, individual channel shutdown, and the mute function. The control program's on-screen user interface is shown in Figure 2. The Default button is used to return the LM49100 to its power-on reset state: minimum volume setting, shutdown on both amplifiers active, and mute active. The LM49100’s stereo VOLUME CONTROL has 32 steps and a gain range of –76dB to 18dB. It is controlled using the slider located at the bottom of the program’s window. Each time the slider is moved from one tick mark to another, the program updates the amplifier’s volume control. LEFT CHANNEL, BOTH CHANNELS, and RIGHT CHANNEL controls each have two buttons. For the left and right channel control, the “ON” button activates its respective channel, whereas the “OFF” button places its respective channel in shutdown mode. Selecting the BOTH CHANNELS “ON” button simultaneously activates both channels, whereas selecting the “OFF” button places channels in shutdown mode. 10 PCB Layout Guidelines This section provides general practical guidelines for PCB layouts that use various power and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual results are predicated on the final layout. 10.1 Power and Ground Circuits Star trace routing techniques (returning individual traces back to a central point rather than daisy chaining traces together in a serial manner) can have a major positive impact on low-level signal performance. Star trace routing refers to using individual traces that radiate from a signal point to feed power and ground to each circuit or even device. This technique may require greater design time, but should not increase the final price of the board. For good THD + N and low noise performance and to ensure correct power-on behavior at the maximum allowed supply voltage, a local 2.2μF power supply bypass capacitor should be connected as physically close as possible to the VDDLS pin. SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback AN-1622 LM49100 Evaluation Board» Copyright © 2007–2013, Texas Instruments Incorporated 5 Bill of Materials www.ti.com 10.2 Avoiding Typical Design/Layout Problems Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB layer. When traces must cross over each other, do so at 90 degrees. Running digital and analog traces at 90 degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise coupling and crosstalk. 11 Bill of Materials Designator Part Description Value Package Type C1 Tantalum Capacitor 2.2μF 1206 CAVSS Tantalum Capacitor 2.2μF 1206 CBYPASS Tantalum Capacitor 2.2μF 1206 CCPUMP1 Tantalum Capacitor 4.7μF 1206 CCPUMP2 Multilayer Ceramic Capacitor 0.1μF 0805 CINL Multilayer Ceramic Capacitor 0.22μF 0805 CINR Multilayer Ceramic Capacitor 2.2μF 0805 CMINN Multilayer Ceramic Capacitor 1μF 0805 CMINP Multilayer Ceramic Capacitor 1μF 0805 1206 CSUPPLY1 Tantalum Capacitor 2.2μF CSUPPLY2 Multilayer Ceramic Capacitor 0.1μF Manufacturer Manufacturer's Part Number Texas Instruments LM49100 0805 HPL 2–pin header, 100 mil pitch 1x2 Header HPR 2–pin header, 100 mil pitch 1x2 Header I2C 6–pin Header 6–pin header, 100 mil pitch 2x3 Header Left Input 2–pin header, 100 mil pitch 1x2 Header Mono Input 4–pin header, 100 mil pitch 1x2 Header Right Input 2–pin header, 100 mil pitch 1x2 Header Speaker 2–pin header, 100 mil pitch 1x2 Header Stereo Headphone Jack Headphone Jack 12 VDD 2–pin header, 100 mil pitch U1 Mono Class AB Audio Subsystem with a True-Ground Headphone Amplifier 1x2 Header Demonstration Board PCB Layout NOTE: The LM49100 is controlled through an I2C compatible interface. The I2C chip address is 0xF8 (ADR pin = 0) or 0xFAh (ADDR pin = 1). Figure 4 through Figure 9 show the different layers used to create the LM49100 four-layer demonstration board. Figure 4 is the silkscreen that shows parts location, Figure 5 is the top layer, Figure 6 is the upper inner layer, Figure 7 is the lower middle layer, Figure 8 is the bottom layer, and Figure 9 is the bottom silkscreen layer. 6 AN-1622 LM49100 Evaluation Board» SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Demonstration Board PCB Layout www.ti.com Figure 4. Top Overlay Figure 5. Top Layer SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback AN-1622 LM49100 Evaluation Board» Copyright © 2007–2013, Texas Instruments Incorporated 7 Demonstration Board PCB Layout www.ti.com Figure 6. Upper Inner Layer Figure 7. Lower Middle Layer 8 AN-1622 LM49100 Evaluation Board» SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Demonstration Board PCB Layout www.ti.com Figure 8. Bottom Layer Figure 9. Bottom Overlay SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback AN-1622 LM49100 Evaluation Board» Copyright © 2007–2013, Texas Instruments Incorporated 9 Typical Demonstration Board Audio Performance 13 www.ti.com Typical Demonstration Board Audio Performance Typical THD + N versus Frequency performance curves at VDD = 3.6V, 3V, and 5V for 8Ω and 32Ω are shown in Figure 10 through Figure 15, respectively. Typical THD + N versus Output Power performance curves at VDD = 3V, 3.6V, and 5V for 32Ω and 8Ω are shown in Figure 16 and Figure 17, respectively. 10 10 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 0.01 0.001 20 200 2k 0.001 20 20k FREQUENCY (Hz) 10 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 0.01 0.001 200 2k 20 20k FREQUENCY (Hz) 2k 20k Figure 13. THD+N vs Frequency VDD = 3V, RL = 32Ω, PO = 25mW BW = 22kHz, HP, Mode 4, 7 10 10 1 1 THD+N (%) THD+N (%) 200 FREQUENCY (Hz) Figure 12. THD+N vs Frequency VDD = 3V, RL = 8Ω, PO = 215mW BW = 22kHz, LS, Mode 1 0.1 0.01 0.1 0.01 200 2k 20k 0.001 20 Figure 14. THD+N vs Frequency VDD = 5V, RL = 8Ω, PO = 630mW BW = 22kHz, Loudspeaker, Mode 1 AN-1622 LM49100 Evaluation Board» 200 2k 20k FREQUENCY (Hz) FREQUENCY (Hz) 10 20k Figure 11. THD+N vs Frequency VDD = 3.6V, RL = 32Ω, PO = 25mW BW = 22kHz, HP, Mode 4, 7 10 0.001 20 2k FREQUENCY (Hz) Figure 10. THD+N vs Frequency VDD = 3.6V, RL = 8Ω, PO = 320mW BW = 22kHz, LS, Mode 1 0.001 20 200 Figure 15. THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 25mW BW = 22kHz, Headphone, Mode 4, 7 SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Typical Demonstration Board Audio Performance www.ti.com 10 10 +3.6V +3V +5V +3V +3.6V 1 +5V 0.1 THD+N (%) THD+N (%) 1 0.1 0.01 1 2 5 10 20 50 100 0.01 10 Figure 16. THD+N vs Output Power RL = 32Ω, f = 1kHz BW = 22kHz, HP, Mode 4 SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback 100 1000 10000 OUTPUT POWER (mW) OUTPUT POWER (mW) Figure 17. THD+N vs Output Power RL = 8Ω, f = 1kHz BW = 22kHz, LS , Mode 1 AN-1622 LM49100 Evaluation Board» Copyright © 2007–2013, Texas Instruments Incorporated 11 LM49100 Control Tables 14 www.ti.com LM49100 Control Tables NOTE: The LM49100 is controlled through an I2C compatible interface. The I2C chip address is 0xF8 (ADR pin = 0) or 0xFAh (ADDR pin = 1). Table 2. I2C Control Register Table D7 D6 D5 D4 D3 D2 D1 D0 Modes Control 0 0 1 1 MC3 MC2 MC1 MC0 HP Volume (Gain) Control 0 1 INPUT_MUTE 0 0 HPR_SD HPVC1 HPVC0 Mono Volume Control 1 0 0 MV4 MV3 MV2 MV1 MV0 Left Volume (Gain) Control 1 1 0 LV4 LV3 LV2 LV1 LV0 Right Volume (Gain) Control 1 1 1 RV4 RV3 RV2 RV1 RV0 Table 3. Headphone Attenuation Control (1) (1) Gain Select HPVC1 HPVC0 Gain, dB 0 0 0 0 1 0 1 −12 2 1 0 −18 3 1 1 −24 These bits have added for extra headphone output attenuation. Table 4. Output Mode Selection (1) (1) 12 Output Mode Number MC3 MC2 MC1 MC0 0 0 0 0 1 0 0 0 2 0 0 1 3 0 0 1 4 0 1 5 0 6 7 Handsfree Mono Output Right HP Output Left HP Output 0 SD SD SD 1 2 × GM × M SD SD 0 SD GHP × (GM × M) GHP × (GM × M) 1 2 × (GL × L + GR × R) SD SD 0 0 SD GHP × (GR × R) GHP × (GL × L) 1 0 1 2 × (GL × L + GR × R + GM × M) SD SD 0 1 1 0 SD GHP × (GR × R + GM × M) GHP × (GL × L + GM × M) 0 1 1 1 2 × (GL × L + GR × R) GHP × (GR × R) GHP × (GL × L) 10 1 0 1 0 2 × (GL × L + GR × R) GHP × (GM × M) GHP × (GM × M) 14 1 1 1 0 2 × (GL × L + GR × R) GHP × (GR × R + GM × M) GHP × (GL × L + GM × M) GL= Left channel gain; GR = Right channel gain; GM = Mono channel gain; GHP = Headphone Amplifier gain; R = Right input signal; L = Left input signal; SD = Shutdown; M = Mono input signal AN-1622 LM49100 Evaluation Board» SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated LM49100 Control Tables www.ti.com Table 5. Mono/Stereo Left/Stereo Right Input Gain Control Volume Step MV4/LV4/RV4 MV3/LV3/RV3 MV2/LV2/RV2 MV1/LV1/RV1 MV0/LV0/RV0 R/L Gain (dB) MonoGain (dB) 1 0 0 0 0 0 −54 −60 2 0 0 0 0 1 −47 −53 3 0 0 0 1 0 −40.5 −46.5 4 0 0 0 1 1 −34.5 −40.5 5 0 0 1 0 0 −30.0 −36 6 0 0 1 0 1 −27 −33 7 0 0 1 1 0 −24 −30 8 0 0 1 1 1 −21 −27 9 0 1 0 0 0 −18 −24 10 0 1 0 0 1 −15 −21 11 0 1 0 1 0 −13.5 −19.5 12 0 1 0 1 1 −12 −18 13 0 1 1 0 0 −10.5 −16.5 14 0 1 1 0 1 −9 −15 15 0 1 1 1 0 −7.5 −13.5 16 0 1 1 1 1 −6 −12 17 1 0 0 0 0 −4.5 −10.5 18 1 0 0 0 1 −3 −9 19 1 0 0 1 0 −1.5 −7.5 20 1 0 0 1 1 0 −6 21 1 0 1 0 0 1.5 −4.5 22 1 0 1 0 1 3 −3 23 1 0 1 1 0 4.5 −1.5 24 1 0 1 1 1 6 0 25 1 1 0 0 0 7.5 1.5 26 1 1 0 0 1 9 3 27 1 1 0 1 0 10.5 4.5 28 1 1 0 1 1 12 6 29 1 1 1 0 0 13.5 7.5 30 1 1 1 0 1 15 9 31 1 1 1 1 0 16.5 10.5 32 1 1 1 1 1 18 12 SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback AN-1622 LM49100 Evaluation Board» Copyright © 2007–2013, Texas Instruments Incorporated 13 Application Information 15 www.ti.com Application Information 15.1 Minimizing Click and Pop To minimize the audible click and pop heard through a headphone, maximize the input signal through the corresponding volume (gain) control registers and adjust the output amplifier gain accordingly to achieve the your desired signal gain. For example, setting the output of the headphone amplifier to -24dB and setting the input volume control gain to 24dB will reduce the output offset from 7mV (typical) to 2.2mV (typical). This will reduce the audible click and pop noise significantly while maintaining a 0dB signal gain. 15.2 Signal Ground Noise The LM49100 has proprietary suppression circuitry, which provides an additional -50dB (typical) attenuation of the headphone ground noise and its incursion into the headphone. For optimum utilization of this feature, the headphone jack ground should connect to the AGND (E3) bump. HPL HPR AGND Figure 18. Suppression Circuitry 15.3 I2C Pin Description SDA: This is the serial data input pin. SCL: This is the clock input pin. ADDR: This is the address select input pin. 15.4 I2C Compatible Interface The LM49100 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (opencollector). The LM49100's I2C compatible interface supports standard (100kHz) and fast (400kHz) I2C modes. In this discussion, the master is the controlling microcontroller and the slave is the LM49100. The I2C address for the LM49100 is determined using the ADDR pin. The LM49100's two possible I2C chip addresses are of the form 111110X10 (binary), where X1 = 0, if ADDR pin is logic LOW; and X1 = 1, if ADDR pin is logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM49100's chip address can be changed to avoid any possible address conflicts. The bus format for the I2C interface is shown in Figure 19 and the timing diagram is shown in Figure 20. The bus format diagram is broken up into six major sections: • The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. • The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is HIGH. • After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM49100 has received the address correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM49100. • The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable HIGH. 14 AN-1622 LM49100 Evaluation Board» SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Application Information www.ti.com • • • After the data byte is sent, the master must check for another acknowledge to determine if the LM49100 received the data. If the master has more data bytes to send to the LM49100, then the master can repeat the previous two steps until all data bytes have been sent. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH. The data line should be held HIGH when not in use. Figure 19. I2C Bus Format Figure 20. I2C Timing Diagram 15.5 I2C Interface Power Supply Pin (VDDI2C) The LM49100's I2C interface is powered up through theVDD I2C pin. The LM49100's I2C interface operates at a voltage level set by the VDD I2C pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback AN-1622 LM49100 Evaluation Board» Copyright © 2007–2013, Texas Instruments Incorporated 15 Application Information www.ti.com 15.6 PCB Layout and Supply Regulation Considerations for Driving 8Ω Load Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω trace resistance reduces the output power dissipated by an 8Ω load from 158.3mW to 156.4mW. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. 15.7 Bridge Configuration Explanation The LM49100 drives a load, such as a loudspeaker, connected between outputs, LS+ and LS-. This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase difference, a load is placed between LS- and LS+ and driven differentially (commonly referred to as ”bridge mode”). Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited and that the output signal is not clipped. Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing LS- and LS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a typical singleended configuration forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as loudspeakers. 15.8 Power Dissipation Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM49100 has a pair of bridged-tied amplifiers driving a handsfree loudspeaker, LS. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation 1, assuming a 5V power supply and an 8Ω load, the maximum MONO power dissipation is 634mW. PDMAX-LS = 4(VDD)2/ (2π2 RL): Bridge Mode (1) The LM49100 also has a pair of single-ended amplifiers driving stereo headphones, HPR and HPL. The maximum internal power dissipation for HPR and HPL is given by Equation 2. Assuming a 2.8V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 49mW, or 99mW total. PDMAX-HPL = 4(VDDHP)2 / (2π2 RL): Single-ended Mode (2) The maximum internal power dissipation of the LM49100 occurs when all three amplifiers pairs are simultaneously on; and is given by: PDMAX-TOTAL = PDMAX-LS + PDMAX-HPL + PDMAX-HPR 16 AN-1622 LM49100 Evaluation Board» (3) SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Application Information www.ti.com The maximum power dissipation point given by Equation 3 must not exceed the power dissipation given by: PDMAX = (TJMAX - TA) / θJA (4) The LM49100's TJMAX = 150°C. In the csBGA package, the LM49100's θJA is 50.2°C/W. At any given ambient temperature TA, use Equation 4 to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation 4 and substituting PDMAX-TOTAL for PDMAX results in Equation 5. This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM49100's maximum junction temperature. TA = TJMAX - PDMAX-TOTAL θJA (5) For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows maximum mono power dissipation without exceeding the maximum junction temperature is approximately 114°C for the csBGA package. Equation 6 gives the maximum junction temperature TJMAX. If the result violates the LM49100's 150°C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. TJMAX = PDMAX-TOTAL θJA + TA (6) The previous examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of Equation 3 is greater than that of Equation 4, then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. 15.9 Power Supply Bypassing As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response. However, their presence does not eliminate the need for a local 4.7µF tantalum bypass capacitor and a parallel 0.1µF ceramic capacitor connected between the LM49100's supply pin and ground. Keep the length of leads and traces that connect capacitors between the LM49100's power supply pin and ground as short as possible. 15.10 Selecting External Components 15.10.1 Input Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input coupling capacitor (CIN in Figure 1). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the loudspeakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using loudspeakers and headphones with this limited frequency response reap little improvement by using large input capacitor. The internal input resistor (Ri), typical 12.5kΩ, and the input capacitor (CIN) produce a high pass filter cutoff frequency that is found using: fc = 1 / (2πRiCIN) (7) SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback AN-1622 LM49100 Evaluation Board» Copyright © 2007–2013, Texas Instruments Incorporated 17 Micro SMD Wafer Level Chip Scale Package: PCB, Layout, and Mounting Considerations www.ti.com 15.10.2 Bypass Capacitor Value Selection Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS pin. Since CB determines how fast the LM49100 settles to quiescent operation, its value is critical when minimizing turn-on pops. Choosing CB equal to 2.2µF along with a small value of Ci (in the range of 0.1µF to 0.33µF), produces a click-less and pop-less shutdown function. As discussed above, choosing CIN no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value should be in the range of 4 to 5 times the value of CIN . This ensures that output transients are eliminated when power is first applied or the LM49100 resumes operation after shutdown. 16 Micro SMD Wafer Level Chip Scale Package: PCB, Layout, and Mounting Considerations Please refer to AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009) for possible updates to the μSMD package information. 17 Demo Board Schematic 18 AN-1622 LM49100 Evaluation Board» SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Revision History www.ti.com 18 Revision History Rev Date 1.0 10/1907 Description SNAA043A – October 2007 – Revised May 2013 Submit Documentation Feedback Initial release. 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