LM49101, LM49101TMEVAL
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LM49101
SNAS475A – MARCH 2009 – REVISED APRIL 2013
Mono Class AB Audio Subsystem with a True
Ground Headphone Amplifier and Earpiece Switch
Check for Samples: LM49101, LM49101TMEVAL
FEATURES
APPLICATIONS
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Differential Mono Input and Stereo SingleEnded Input
Separate Earpiece (Receiver) Differential Input
Analog Switch for a Separate Earpiece Path
32-Step Digital Volume Control (-80 to +18dB)
Three Independent Volume Channels (Left,
Right, Mono)
Separate Headphone Volume Control
Flexible Output for Speaker and Headphone
Output
True Ground Headphone Amplifier Eliminates
Large DC Blocking Capacitors Reducing PCB
Space and Cost
Hardware Reset Function
RF Immunity Topology
“Click and Pop” Suppression Circuitry
Thermal Shutdown Protection
Micro-Power Shutdown
I2C Control Interface
Available in Space-Saving DSBGA Package
KEY SPECIFICATIONS
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Supply Voltage (VDDLS): 2.7V ≤ VDDLS ≤ 5.5V
Supply Voltage (VDDHP): 1.8V ≤ VDDHP ≤ 2.9V
I2C Supply Voltage: 1.7V ≤ I2CVDD ≤ 5.5V
Output Power, VDDLS = 5V, VDDHP = 2.75V, 1%
THD+N
– RL = 8Ω Speaker 1.3W (Typ)
– RL = 32Ω Headphone 45mW (Typ)
Output Power VDDLS = 3.3V, VDDHP = 2.75V,
1% THD+N
– RL = 8Ω Speaker 540W (Typ)
– RL = 32Ω Headphone 40mW (Typ)
PSRR: VDD = 3.3V, 217Hz Ripple, Mono In:
90dB (Typ)
Shutdown Power Supply Current: 0.01μA (Typ)
Portable Electronic Devices
Mobile Phones
PDAs
DESCRIPTION
The LM49101 is a fully integrated audio subsystem
with a mono power amplifier capable of delivering
540mW of continuous average power into an 8Ω BTL
speaker load with 1% THD+N using a 3.3V supply.
The LM49101 includes a separate stereo headphone
amplifier that can deliver 44mW per channel into 32Ω
loads using a 2.75V supply.
The LM49101 has four input channels. A pair of
single-ended inputs and a fully differential input
channel with volume control and amplification stages.
Additionally, a bypass differential input is available
that connects directly to the mono speaker outputs
through an analog switch without any amplification or
volume control stages. The LM49101 features a
32–step digital volume control on the input stage and
an 8–step digital volume control on the headphone
output stage.
The digital volume control and output modes,
programmed through a two-wire I2C compatible
interface, allows flexibility in routing and mixing audio
channels.
The LM49101 is designed for cellular phones, PDAs,
and other portable handheld applications. The high
level of integration minimizes external components.
The True Ground headphone amplifier eliminates the
physically large DC blocking output capacitors
reducing required board space and reducing cost.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LM49101, LM49101TMEVAL
SNAS475A – MARCH 2009 – REVISED APRIL 2013
www.ti.com
Typical Application
Figure 1. Typical Audio Application Circuit
Connection Diagram
Top View
Figure 2. 25 Bump DSBGA Package
See Package Number YFQ0025BCA
2
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SNAS475A – MARCH 2009 – REVISED APRIL 2013
Table 1. Bump Descriptions
Bump
Name
A1
CPGND
Charge pump ground terminal
Pin Function
A2
VSSCP
Negative charge pump power supply
Power Output
A3
HPR
Right headphone output
Analog Output
A4
VDDHP
Headphone amplifier power supply
Power Input
A5
MIN+
Positive input pin for the mono, differential input
Analog Input
B1
C1N
Negative terminal of the charge pump flying capacitor
Analog Output
B2
C1P
Positive terminal of the charge pump flying capacitor
Analog Output
B3
HPL
Left headphone output
Analog Output
B4
HPGND
B5
MIN-
C1
VDDCP
Headphone signal ground
Type
Ground
Ground
Negative input pin for the mono, differential input
Analog Input
Charge pump power supply
Power Input
2
C2
SDA
I C data
C3
GND
Ground
C4
RIN
Single-ended input for the right channel
Analog Input
C5
LIN
Single-ended input for the left channel
Analog Input
D1
BYPASS_IN-
Earpiece negative input, bypass volume control and amplifier
Analog Input
D2
I2CVDD
I2C power supply
Power Input
D3
SCL
I2C clock
Digital Input
D4
HW RESET
Hardware reset function, active low. When pin is low (1.6V) and is activated by I2C
control. When reset all registers are set to the default value of 0.
Digital Input
D5
BYPASS_IN+
E1
MONO+
E2
VDDLS
E3
GND
E4
MONO-
E5
BIAS
Digital Input
Ground
Earpiece positive input, bypass volume control and amplifier
Positive loudspeaker output
Main power supply
Ground
Analog Input
Analog Output
Power Input
Ground
Negative loudspeaker output
Analog Output
Half-supply bias, capacitor bypassed
Analog Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2) (3) (4)
Supply Voltage (Loudspeaker, VDDLS)
6.0V
Supply Voltage (Headphone, VDDHP)
3.0V
−65°C to +150°C
Storage Temperature
GND − 0.3 to VDD LS + 0.3
Voltage at Any Input Pin
Power Dissipation
(5)
Internally Limited
ESD Rating (6)
2000V
ESD Rating (7)
200V
Junction Temperature (TJMAX)
Soldering Information
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
150°C
Vapor Phase (60sec.)
215°C
Infrared (15sec.)
220°C
θJA
(8)
51°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
See AN-1112 “Micro SMD Wafer Level Chip Scale Package" ().
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever
Human body model, applicable std. JESD22-A114C.
Machine model, applicable std. JESD22-A115-A.
The given θJA is for an LM49101 mounted on a demonstration board.
Operating Ratings
Temperature Range (TMIN ≤ TA ≤ TMAX)
−40°C ≤ TA ≤ 85°C
Supply Voltage (VDDLS)
2.7V ≤ VDDLS ≤ 5.5V
Supply Voltage (VDDHP)
1.8V ≤ VDDHP ≤ 2.9V
VDDHP ≤ VDDLS
Supply Voltage (VDDCP)
VDDCP = VDD HP
1.7V ≤ I2CVDD ≤ 5.5V
Supply Voltage (I2CVDD)
4
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I2CVDD ≤ VDDLS
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Electrical Characteristics VDDLS = 3.3V, VDDHP = 2.75V (1) (2)
The following specifications apply for VDDLS = 3.3V, VDDHP = 2.75V, TA = 25°C, all volume controls set to 0dB, unless
otherwise specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Parameter
LM49101
Typ (3)
Limits (4)
Units
(Limits)
0.03
0.045
mA (max)
LS only (Mode 1), GAMP_SD = 0
VDDLS
VDDHP
2.5
0
4.2
mA (max)
mA
LS only (Mode 1), GAMP_SD = 1
VDDLS
VDDHP
2
0
Test Conditions
VIN = 0, No Load
EP Receiver
(Output Mode Bit EP Bypass = 1)
IDD
HP only (Mode 8), GAMP_SD = 0
VDDLS
VDDHP
VDDLS +VDDHP
Quiescent Power Supply Current
HP only (Mode 8), GAMP_SD = 1
VDDLS
VDDHP
ISD
VOS
PO
SNR
(1)
(2)
(3)
(4)
2.0
4.5
6.45
2.8
3.3
mA (max)
mA (max)
mA (max)
mA
mA
LS+HP (Mode 10), GAMP_SD = 0
VDDLS
VDDHP
VDDLS +VDDHP
2.8
3.1
3.8
4.5
8
mA (max)
mA (max)
mA (max)
Shutdown Current
Power_On = 0
0.01
2
µA (max)
Output Offset Voltage
VIN = 0V, Mode 10
LS output, RL = 8Ω BTL
HP output, RL = 32Ω SE
2.5
0.5
22
5
mV (max)
mV (max)
LS output, Mode 1, RL = 8Ω BTL
THD+N = 1%, f = 1kHz, LS_Gain = 6dB
540
480
mW (min)
HP output, Mode 8, RL = 32Ω SE
THD+N = 1%, f = 1kHz
44
40
mW (min)
Output Power
THD+N
1.6
3.1
mA
mA
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
LS output, f = 1kHz, RL = 8Ω BTL
PO = 250mW, Mode 1, LS_Gain = 6dB
0.065
%
HP output, f = 1kHz, RL = 32Ω SE
PO = 20mW, Mode 8
0.015
%
LS output, f = 1kHz, Mode 1
VREF = VOUT (1%THD+N)
Vol. Gain & LS_GAIN = 0dB
A-Wtg, LIN & RIN AC terminated
105
dB
HP output, f = 1kHz, Mode 8
VREF = VOUT (1%THD+N)
Vol. Gain = 0dB, A-weighted
LIN & RIN AC terminated
100
dB
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are specified by test or statistical analysis.
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Electrical Characteristics VDDLS = 3.3V, VDDHP = 2.75V(1)(2) (continued)
The following specifications apply for VDDLS = 3.3V, VDDHP = 2.75V, TA = 25°C, all volume controls set to 0dB, unless
otherwise specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Parameter
LM49101
Test Conditions
Typ (3)
Limits (4)
Units
(Limits)
VRIPPLE on VDDLS = 200mVPP, fRIPPLE = 217Hz, CB = 2.2μF
All inputs AC terminated to GND, output referred
PSRR
Power Supply Rejection Ratio
LS: Mode 1, 5, 9, 13, RL = 8Ω BTL
90
dB (max)
LS: Mode 2, 6, 10 ,14, RL = 8Ω BTL
75
dB (max)
HP: Mode 4, 5, 6, 7, RL = 32Ω SE
85
dB (max)
HP: Mode 8, 9, 10, 11, RL = 32Ω SE
81
dB (max)
60
60
dB
dB
72
dB
CMRR
Common-Mode Rejection Ratio
f = 217Hz, VCM = 1VP-P
LS: RL = 8Ω BTL, Mode 1
HP: RL = 32Ω SE, Mode 4
XTALK
Crosstalk
HP PO = 20mW
f = 1kHz, Mode 8
Maximum Gain setting
12.5
10
15
KΩ (min)
KΩ (max)
Maximum Attenuation setting
110
90
130
KΩ (min)
KΩ (max)
On Resistance
Analog Switch On
3.4
Ω
VOL
Digital Volume Control Range
Maximum Gain
Maximum Attenuation
18
–80
dB
dB
VOL
Volume Control Step Size Error
ZIN
RON
TWU
6
MIN, LIN, and RIN Input Impedance
Wake-Up Time from Shutdown
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±0.02
dB
CB = 2.2μF, HP, Normal Turn-On Mode
30
ms
CB = 2.2μF, HP, Fast Turn-On Mode
15
ms
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Electrical Characteristics VDDLS = 5.0V, VDDHP = 2.75V (1) (2)
The following specifications apply for VDDLS = 5.0V, VDDHP = 2.75V, TA = 25°C, all volume controls set to 0dB, unless
otherwise specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Parameter
LM49101
Typ (3)
Limits (4)
Units
(Limits)
0.05
0.07
mA (max)
LS only (Mode 1), GAMP_SD = 0
VDDLS
VDDHP
2.9
0
4.4
mA (max)
mA
LS only (Mode 1), GAMP_SD = 1
VDDLS
VDDHP
2.1
0
Test Conditions
VIN = 0, No Load
EP Receiver
(Output Mode Bit EP Bypass = 1)
IDD
HP only (Mode 8), GAMP_SD = 0
VDDLS
VDDHP
VDDLS+VDDHP
Quiescent Power Supply Current
HP only (Mode 8), GAMP_SD = 1
VDDLS
VDDHP
ISD
VOS
PO
SNR
(1)
(2)
(3)
(4)
2.15
4.5
6.6
1.3
3.1
mA (max)
mA (max)
mA (max)
mA
mA
LS+HP only (Mode 10), GAMP_SD = 0
VDDLS
VDDHP
VDDLS+VDDHP
3
3.1
4.1
4.5
8.35
mA (max)
mA (max)
mA (max)
Shutdown Current
Power_On = 0
0.01
2
µA (max)
Output Offset Voltage
VIN = 0V, Mode 10
LS output, RL = 8Ω BTL
HP output, RL = 32Ω SE
2.5
0.5
22
5
mV (max)
mV (max)
LS output, Mode 1, RL = 8Ω BTL
THD+N = 1%, f = 1kHz, LS_Gain = 6dB
1.3
W
HP output, Mode 8, RL = 32Ω SE
THD+N = 1%, f = 1kHz
45
mW
LS output, f = 1kHz, RL = 8Ω BTL
PO = 600mW, Mode 1, LS_Gain = 6dB
0.055
%
HP output, f = 1kHz, RL = 32Ω SE
PO = 20mW, Mode 8
0.015
%
LS output, f = 1kHz, Mode 1
VREF = VOUT (1%THD+N)
Vol. Gain & LS_GAIN = 0dB
A-Wtg, LIN & RIN AC terminated
108
dB
HP output, f = 1kHz, Mode 8
VREF = VOUT (1%THD+N)
Vol. Gain = 0dB, A-weighted
LIN & RIN AC terminated
100
dB
Output Power
THD+N
1.8
3.1
mA
mA
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are specified by test or statistical analysis.
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Electrical Characteristics VDDLS = 5.0V, VDDHP = 2.75V(1)(2) (continued)
The following specifications apply for VDDLS = 5.0V, VDDHP = 2.75V, TA = 25°C, all volume controls set to 0dB, unless
otherwise specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece.
Parameter
LM49101
Test Conditions
Typ (3)
Limits (4)
Units
(Limits)
VRIPPLE on VDDLS = 200mVPP, fRIPPLE = 217Hz, CB = 2.2μF
All inputs AC terminated to GND, output referred
PSRR
Power Supply Rejection Ratio
LS: Mode 1, 5, 9, 13, RL = 8Ω BTL
90
dB
LS: Mode 2, 6, 10, 14, RL = 8Ω BTL
74
dB
HP: Mode 4, 5, 6, 7, RL = 32Ω SE
84
dB
HP: Mode 8, 9, 10, 11, RL = 32Ω SE
79
dB
60
60
dB
dB
72
CMRR
Common-Mode Rejection Ratio
f = 217Hz, VCM = 1VP-P
LS: RL = 8Ω BTL, Mode 1
HP: RL = 32Ω SE, Mode 4
XTALK
Crosstalk
HP PO = 20mW, f = 1kHz, Mode 8
ZIN
RON
Maximum Gain setting
12.5
Maximum Attenuation setting
110
90
130
MIN, LIN, and RIN Input Impedance
KΩ (min)
KΩ (max)
2
Ω
dB
dB
±0.02
dB
CB = 2.2μF, HP, Normal Turn-On Mode
30
ms
CB = 2.2μF, HP, Fast Turn-On Mode
15
ms
Analog Switch On
VOL
Digital Volume Control Range
Maximum Gain
Maximum Attenuation
VOL
Volume Control Step Size Error
TWU
Wake-Up Time from Shutdown
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KΩ (min)
KΩ (max)
18
–80
On Resistance
8
dB
10
15
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I2C Interface 2.2V ≤ I2C_VDD ≤ 5.5V (1) (2)
The following specifications apply for VDDLS = 5.0V and 3.3V, 2.2V ≤ I2C_VDD ≤ 5.5V, TA = 25°C, unless otherwise specified.
Parameter
(1)
(2)
(3)
(4)
(5)
Test Conditions
LM49101
Typ
(3)
Limits (4) (5)
Units
(Limits)
t1
I2C Clock Period
2.5
µs (min)
t2
I2C Data Setup Time
100
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
t6
I2C Data Hold Time
100
ns (min)
2
2
VIH
I C Input Voltage High
0.7xI CVDD
V (min)
VIL
I2C Input Voltage Low
0.3xI2CVDD
V (max)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Human body model, applicable std. JESD22-A114C.
Datasheet min/max specification limits are specified by test or statistical analysis.
Refer to the I2C timing diagram, Figure 39.
I2C Interface 1.7V ≤ I2C_VDD ≤ 2.2V (1) (2)
The following specifications apply for VDDLS = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2C_VDD ≤ 2.2V, unless otherwise specified.
Parameter
(1)
(2)
(3)
(4)
(5)
Test Conditions
LM49101
Typ
(3)
Limits (4) (5)
Units
(Limits)
t1
I2C Clock Period
2.5
µs (min)
t2
I2C Data Setup Time
250
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
250
ns (min)
t5
Stop Condition Time
250
ns (min)
t6
I2C Data Hold Time
250
ns (min)
2
2
VIH
I C Input Voltage High
0.7xI CVDD
V (min)
VIL
I2C Input Voltage Low
0.3xI2CVDD
V (max)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are specified by test or statistical analysis.
Refer to the I2C timing diagram, Figure 39.
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Typical Performance Characteristics
10
THD+N vs Frequency
VDDLS = 3.3V, RL = 8Ω BTL, PO = 250mW
Mode 1 (Mono), 80kHz BW
THD+N vs Frequency
VDDLS = 3.3V, RL = 8Ω BTL, PO = 250mW
Mode 2 (Left + Right), 80kHz BW
Figure 3.
Figure 4.
THD+N vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, RL = 32Ω SE,
PO = 5mW/Ch, Mode 4 (Mono), 80kHz BW
THD+N vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, RL = 32Ω SE,
PO = 5mW/Ch, Mode 8 (Left/Right ), 80kHz BW
Figure 5.
Figure 6.
THD+N vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, RL = 8Ω BTL, RL = 32Ω SE,
PO = 250mW BTL, PO = 5mW/Ch SE, Mode 5 (Mono)
LS (EP Mode) = 0, 80kHz BW
THD+N vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, RL = 8Ω BTL, RL = 32Ω SE,
PO = 250mW BTL, PO = 5mW/Ch SE, Mode 10 (L/R)
LS (EP Mode) = 0, 80kHz BW
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
THD+N vs Frequency
VDDLS = 5V, RL = 8Ω BTL, PO = 600mW,
Mode 1 (Mono), 80kHz BW
THD+N vs Frequency
VDDLS = 5V, RL = 8Ω BTL, PO = 600mW,
Mode 2 (Let + Right), 80kHz BW
Figure 9.
Figure 10.
THD+N vs Frequency
VDDLS = 5V, VDDHP = 2.75V, RL = 32Ω SE,
PO = 20mW/Ch, Mode 4 (Mono), 80kHz BW
THD+N vs Frequency
VDDLS = 5V, VDDHP = 2.75V, RL = 32Ω SE,
PO = 20mW/Ch, Mode 8 (Left/Right), 80kHz BW
20
10
20
10
1
THD + N (%)
THD + N (%)
1
0.1
0.010
0.001
20
0.1
0.010
100
1k
10k 20k
0.001
20
FREQUENCY (Hz)
100
1k
10k 20k
FREQUENCY (Hz)
Figure 11.
Figure 12.
THD+N vs Frequency
VDDLS = 5V, VDDHP = 2.75V, RL = 8Ω BTL, RL = 32Ω SE,
PO = 600mW BTL, PO = 20mW/Ch SE, Mode 5 (Mono)
LS (EP Mode) = 0, 80kHz BW
THD+N vs Frequency
VDDLS = 5V, VDDHP = 2.75V, RL = 8Ω BTL, RL = 32Ω SE,
PO = 600mW BTL, PO = 20mW/Ch SE, Mode 10 (L/R)
LS (EP Mode) = 0, 80kHz BW
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDDLS = 3.3V & 5V, f = 1kHz, RL = 8Ω BTL
Mode 1 (Mono), 80kHz BW
THD+N vs Output Power
VDDLS = 3.3V & 5V, f = 1kHz, RL = 8Ω BTL
Mode 2 (Left + Right), 80kHz BW
10
10
5
5
3.3V
2
1
3.3V
0.5
5V
1
THD+N (%)
THD+N (%)
2
0.2
5V
0.5
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01
1m
10m
1
100m
0.01
1m
2
10m
OUTPUT POWER (W)
100m
1
2
OUTPUT POWER (W)
Figure 15.
Figure 16.
THD+N vs Output Power
VDDLS = 3.3V, VDDHP = 1.8V & 2.75V, f = 1kHz,
RL = 32Ω SE, Mode 4 (Mono), 80kHz BW
THD+N vs Output Power
VDDLS = 3.3V, VDDHP = 1.8V & 2.75V, f = 1kHz,
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
10
10
5
5
2
1
2
1
1.8V
0.2
0.1
THD+N (%)
THD+N (%)
1.8V
0.5
0.5
2.75V
0.05
0.02
2.75V
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.001
1m
0.002
0.001
1m
2m
5m
10m
60m
20m
2m
OUTPUT POWER (W)
5m
10m
20m
60m
OUTPUT POWER (W)
Figure 17.
Figure 18.
THD+N vs Output Power
VDDLS = 3.3V & 5V, VDDHP = 2.75V, f = 1kHz,
RL = 8Ω BTL, Mode 5 (Mono), 80kHz BW
THD+N vs Output Power
VDDLS = 3.3V, VDDHP = 1.8V & 2.75V, f = 1kHz,
RL = 32Ω SE, Mode 10 (Left/Right), 80kHz BW
10
10
5
5
2
1
3.3V
2
THD+N (%)
THD+N (%)
1.8V
0.5
1
5V
0.5
0.2
0.1
2.75V
0.2
0.1
0.05
0.02
0.01
0.05
0.005
0.02
0.01
1m
10m
100m
1
2
0.002
0.001
1m
OUTPUT POWER (W)
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5m
10m
20m
60m
OUTPUT POWER (W)
Figure 19.
12
2m
Figure 20.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
VDDLS = 3.3V, VRIPPLELS = 200mVPP, RL = 8Ω BTL,
Mode 1 (Mono), 80kHz BW
PSRR vs Frequency
VDDLS = 3.3V, VRIPPLELS = 200mVPP, RL = 8Ω BTL,
Mode 2 (Left + Right), 80kHz BW
Figure 21.
Figure 22.
PSRR vs Frequency
VDDLS = 5V, VRIPPLELS = 200mVPP, RL = 8Ω BTL,
Mode 1 (Mono), 80kHz BW
PSRR vs Frequency
VDDLS = 5V, VRIPPLELS = 200mVPP, RL = 8Ω BTL,
Mode 2 (Left + Right), 80kHz BW
Figure 23.
Figure 24.
PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, VRIPPLEHP = 200mVPP,
RL = 32Ω SE, Mode 4 (Mono), 80kHz BW
PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, VRIPPLEHP = 200mVPP,
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 2.75V, VRIPPLEHP = 200mVPP,
RL = 32Ω SE, Mode 4 (Mono), 80kHz BW
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 2.75V, VRIPPLEHP = 200mVPP,
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
50 100 200 500 1k 2k
5k 10k 20k
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
Figure 27.
Figure 28.
Power Dissipation vs Output Power
VDDLS = 3.3V & 5V, VDDHP = 2.75V, RL = 8Ω BTL,
Mode 3 (Mono + Left + Right), 80kHz BW
Power Dissipation vs Output Power
VDDLS = 5V, VDDHP = 1.8V & 2.75V, RL = 32Ω SE,
Mode 12 (Mono + Left/ Right), 80kHz BW
700
160
600
140
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
FREQUENCY (Hz)
5V
500
400
300
200
3.3V
0
120
100
2.75V
80
60
40
1.8V
20
100
0
200 400
600
0
0
800 1000 1200
5 10 15 20 25 30 35 40 45 50
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 29.
Figure 30.
Crosstalk vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, VIN = 1VPP,
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
Crosstalk vs Frequency
VDDLS = 3.3V, VDDHP = 2.75V, VIN = 1VPP,
RL = 32Ω SE, Mode 8 (Left/Right), 80kHz BW
0
0
-10
CHANNEL SEPARATION (dB)
CHANNEL SEPARATION (dB)
-10
14
5k 10k 20k
FREQUENCY (Hz)
-20
-30
-40
-50
-60
-70
-80
-20
-30
-40
-50
-60
-70
-80
-90
-90
-100
20
-100
20
50 100 200 500 1k 2k
5k 10k 20k
50 100 200 500 1k 2k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 31.
Figure 32.
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Typical Performance Characteristics (continued)
Supply Current vs Supply Voltage (VDDLS)
VDDHP = 2.75V, No Load, Gain_SD = 0 & 1
LS (EP_Mode) = 0 & 1, Mode 1
Supply Current vs Supply Voltage (VDDLS)
VDDHP = 2.75V, No Load, Gain_SD = 0 & 1
LS (EP_Mode) = 0 & 1, Mode 2
4
Gain_SD = 0
EP_mode = 0
3.5
POWER SUPPLY CURRENT (mA)
POWER SUPPLY CURRENT (mA)
4
3
Gain_SD = 0
EP_mode = 1
2.5
2
1.5
Gain_SD = 1
EP_mode = 0
1
0.5
Gain_SD = 1
EP_mode = 1
0
0
1
3
2
5
4
3.5
Gain_SD = 0
EP_mode = 0
3
2.5
1.5
Gain_SD = 0
EP_mode = 1
1
0.5
Gain_SD = 1
EP_mode = 1
0
6
Gain_SD = 1
EP_mode = 0
2
0
1
POWER SUPPLY VOLTAGE (V)
5
6
Figure 34.
Supply Current vs Supply Voltage (VDDHP)
VDDLS = 3.3V, No Load, Gain_SD = 0 or 1
HPR_SD = 0 & 1, Modes 4, 8, 15
Supply Current vs Supply Voltage (VDDLS)
VDDHP = 2.75V, No Load, Gain_SD = 0 or 1
LS (EP_Mode) = 0 & 1, Mode 15
4.5
HPR_SD = 0
3
POWER SUPPLY CURRENT (mA)
POWER SUPPLY CURRENT (mA)
4
Figure 33.
3.5
2.5
2
1.5
1
HPR_SD = 1
0.5
0
0
0.5
1.5
1
2
2.5
3
4.0
EP_mode = 0
3.5
3
2.5
2
1.5
EP_mode = 1
1
0.5
0
3.5
0
1
POWER SUPPLY VOLTAGE (V)
3
2
4
5
6
POWER SUPPLY VOLTAGE (V)
Figure 35.
Figure 36.
Output Power vs Supply Voltage (VDDLS)
VDDHP = 2.75V, RL = 8Ω BTL, Mode 1
Output Power vs Supply Voltage (VDDHP)
VDDLS = 3.3V, RL = 32Ω SE, Mode 4
60
2500
50
2000
OUTPUT POWER (mW)
OUTPUT POWER (mW)
3
2
POWER SUPPLY VOLTAGE (V)
THD+N = 10%
1500
THD+N = 1%
1000
500
0
0
THD+N = 10%
40
THD+N = 1%
30
20
10
1
2
3
4
5
POWER SUPPLY VOLTAGE (V)
6
0
0
0.5
1
1.5
2
2.5
3
3.5
POWER SUPPLY VOLTAGE (V)
Figure 37.
Figure 38.
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APPLICATION INFORMATION
I2C COMPATIBLE INTERFACE
The LM49101 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM49101
and the master can communicate at clock rates up to 400kHz. Figure 39 shows the I2C interface timing diagram.
Data on the SDA line must be stable during the HIGH period of SCL. The LM49101 is a transmit/receive slaveonly device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a
START condition and a STOP condition (Figure 40). Each data word, device address and data, transmitted over
the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 41). The LM49101 device address
is 11111000.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM49101's I2C interface is powered up through the I2CVDD pin. The LM49101's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDDLS.
This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the VDDLS voltage.
I2C BUS FORMAT
The I2C bus format is shown in Figure 41. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0
indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the
slave device. Set R/W = 0; the LM49101 is a WRITE-ONLY device and will not respond to the R/W = 1. The data
is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last
address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is
generated by the slave device. If the LM49101 receives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data word is sent, the LM49101 sends another ACK bit. Following the
acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is
high.
Figure 39. I2C Timing Diagram
SDA
SCL
S
P
START condition
STOP condition
Figure 40. Start and Stop Diagram
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SCL
SDA
START
MSB
DEVICE ADDRESS
LSB
R/W
ACK
MSB
REGISTER DATA
LSB
ACK
STOP
Figure 41. Start and Stop Diagram
Table 2. Chip Address
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
1
1
0
0
0
Chip Address
Table 3. Control Registers (1)
Register
D7
D6
D5
D4
D3
D2
D1
D0
LS
(EP_Mode) (3)
0
Turn_On _Time (4)
Power_On (5)
General Control
0
0
1
GAMP_SD (2)
Output Mode Control
0
1
EP
Bypass (6)
HPR_SD (6)
Output Gain Control
1
0
0
Input_Mute (8)
Mono Input Volume
Control
1
0
1
Left Input Volume
Control
1
1
0
Right Input Volume
Control
1
1
1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Mode_ Control (7)
LS_Gain (9)
HP_Gain (10)
Mono_Vol
(11)
Left_Vol (11)
Right_Vol (11)
All registers default to 0 on initial power-up.
GAMP_SD: Is used to shut down gain amplifiers not in use and reduce current consumption. See Table 4.
LS (EP_Mode): Loudspeaker power amplifier bias current reduction. See Table 4.
Turn_On_Time: Reduces the turn on time for faster activation. See Table 4.
Power_On: Master Power on bit. See Table 4.
EP Bypass: Earpiece bypass mode to allow BYPASS inputs to drive speaker outputs. See Table 5.
Mode_Control: Sets the output mode. See Table 5.
Input Mute: Controls muting of the inputs except the BYPASS inputs. See Table 6.
LS_Gain: Sets the gain of the loudspeaker amplifier to 0dB or 6dB. See Table 6.
HP_Gain: Sets the headphone amplifier output gain. See Table 6.
Mono_Vol/Left_Vol/Right_Vol: Sets the input volume for Mono, Left and Right inputs. See Table 7.
Table 4. General Control Register
Bit
Name
Value
Description
This bit is a master shutdown control bit and sets the device to be on or off.
0
Value
Power_On
Status
0
Master power off, device disable.
1
Master power on, device enable.
This bit sets the turn on time of the device.
1
Value
Turn_On_Time
Status
0
Normal Turn-on time
1
Fast Turn-on time
This bit enables EP Mode reducing loudspeaker output stage bias current by 500μA.
Value
3
LS (EP Mode)
Status
0
Normal loudspeaker power amplifier operation.
1
Enables EP Mode reducing loudspeaker output stage bias current by
500μA.
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Table 4. General Control Register (continued)
Bit
Name
Value
Description
This bit is used to reduce IDD by shutting down gain amplifiers not in use.
4
GAMP_SD
0
Normal operation of all gain amplifiers.
1
Disables the input gain amplifiers that are not in use to reduce current
from VDDLS. Recommended for Output Modes 1, 2, 4, 5, 8, 10.
Table 5. Output Mode Control Register (1)
Bits
Field
3:0
Mode_Control
Description
These bits determine how the input signals are mixed and routed to the outputs.
D3
D2
D1
Headphone
D0
Loudspeaker
D3D2D1D0
Mode
Left Headphone
Right Headphone
0000
0
SD
SD
SD
0001
1
SD
SD
GM x M
0010
2
SD
SD
2 x (GL x L + GR x R)
0011
3
SD
SD
2 x (GL x L + GR x R)
+ GM x M
0100
4
GM x M/2
GM x M/2
SD
0101
5
GM x M/2
GM x M/2
GM x M
0110
6
GM x M/2
GM x M/2
2 x (GL x L + GR x R)
0111
7
GM x M/2
GM x M/2
2 x (GL x L + GR x R)
+ GM x M
1000
8
GL x L
GR x R
SD
1001
9
GL x L
GR x R
GM x M
1010
10
GL x L
GR x R
2 x (GL x L + GR x R)
1011
11
GL x L
GR x R
2 x (GL x L + GR x R)
+ GM x M
1100
12
GL x L + GM x
M/2
GR x R + GM x
M/2
SD
1101
13
GL x L + GM x
M/2
GR x R + GM x
M/2
GM x M
1110
14
GL x L + GM x
M/2
GR x R + GM x
M/2
2 x (GL x L + GR x R)
1111
15
GL x L + GM x
M/2
GR x R + GM x
M/2
2 x (GL x L + GR x R)
+ GM x M
This bit sets the headphone amplifiers to normal mode or mono mode.
4
HPR_SD
Value
Status
0
Normal stereo headphone operation.
1
Disable right headphone output.
This bit is used to control the analog switch to have the BYPASS inputs drive the loudspeaker outputs.
Value
5
(1)
18
EP Bypass
Status
0
Normal output mode operation with analog switch off.
1
Loudspeaker and headphone amplifiers go into shutdown mode and Bypass (Receiver) path enable
with the analog switch on.
M : MIN, Mono differential input
L : LIN, Left single-ended input
R : RIN, Right single-ended input
SD : Shutdown
GM : Mono_Vol setting determined by the Mono Input Volume Control register, See Table 7.
GL : Left_Vol setting determined by the Left Input Volume Control register, See Table 7.
GR : Right_Vol setting determined by the Right Input Volume Control register, See Table 7.
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Table 6. Output Gain Control Register
Bits
Field
Description
These bits set the gain of the headphone output amplifiers.
Value
2:0
HP_GAIN
Gain (dB)
000
0
001
–1.2
010
–2.5
011
–4.0
100
–6.0
101
–8.5
110
–12
111
–18
This bit sets the loudspeaker output amplifier gain.
3
Value
LS_GAIN
Status
0
Loudspeaker output amplifier gain is set to 0dB.
1
Loudspeaker output amplifier gain is set to 6dB.
This bit will set all the inputs except the BYPASS inputs to be in Mute mode.
Value
4
Status
0
Normal operation of all inputs.
1
Mutes all inputs except BYPASS with over 80dB of attenuation
with out adjusting the volume settings. This bit can be used to
mute the inputs to eliminate noise or transients from other
systems and ICs. See INPUT MUTE BIT for a detailed
explanation.
INPUT MUTE
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Table 7. Input Volume Control Registers
Bits
Fields
4:0
Mono_Vol
Right_Vol
Left_Vol
Description
These bits set the input volume for each input volume register listed.
Volume Step
Value
Gain (dB)
1
00000
–80.0
2
00001
–46.5
3
00010
–40.5
4
00011
–34.5
5
00100
–30.0
6
00101
–27.0
7
00110
–24.0
8
00111
–21.0
9
01000
–18.0
10
01001
–15.0
11
01010
–13.5
12
01011
–12.0
13
01100
–10.5
14
01101
–9.0
15
01110
–7.5
16
01111
–6.0
17
10000
–4.5
18
10001
–3.0
19
10010
–1.5
20
10011
0.0
21
10100
1.5
22
10101
3.0
23
10110
4.5
24
10111
6.0
25
11000
7.5
26
11001
9.0
27
11010
10.5
28
11011
12.0
29
11100
13.5
30
11101
15.0
31
11110
16.5
32
11111
18.0
HW RESET FUNCTION
The LM49101 can be globally reset without using the I2C controls. When the HW RESET pin is set to a logic low
the LM49101 will enter into shutdown, the mode control bits of the Output Mode Control register, volume control
registers and Power_On bits will be set to the default value of zero. The other bits will retain their values. The
LM49101 cannot be activated until the HW RESET pin is set to a logic high voltage. When the HW RESET is set
to a logic high then the I2C controls can activate and set the register control bits.
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GAMP_SD BIT
The GAMP_SD bit allows for reduced power consumption. When set to '1' the gain amplifiers on unused inputs
will be shutdown saving approximately 0.4mA per input in shutdown. For example, in Mode 1 only the mono
inputs are in use. Setting GAMP_SD to '1' will shut down the gain amplifiers for the left and right inputs reducing
current draw from the VDDLS supply by approximately 0.8mA. The GAMP_SD bit does not need to be set each
time when changing modes as the LM49101 will automatically activate and deactivate the needed inputs based
on the mode selected.
When operating with GAMP_SD set to '1', a transient may be observed on the outputs when changing modes.
During power up, the LM49101 uses a start up sequence to eliminate any pops and clicks on the outputs. The
volume control circuitry is powered up first followed by the other internal circuitry with the output amplifiers being
powered up last. If a mode change requires a gain amplifier to turn on then a potential transient may be created
that is amplified on the already active outputs. To eliminate unwanted noise on the outputs the Power_On bit
should be used to turn off the LM49101 before changing modes, perform a mode change, then turn the LM49101
back on. This procedure will cause the LM49101 to follow the start up sequence.
LS (EP_MODE) BIT
The LS (EP_Mode) bit selects the amount of bias current in the loudspeaker amplifier. Setting the LS (EP_Mode)
bit to a '1' will reduce the amount of current from the VDDLS supply by approximately 0.5mA. The THD
performance of the loudspeaker amplifier will be reduced as a result of lower bias current. See the performance
graphs in Typical Performance Characteristics.
TURN_ON_TIME BIT
The Turn_On_Time bit determines the delay time from the Power_On bit set to '1' and the internal circuits ready.
For input capacitor values up to 0.47μF the Turn_On_Time bit can be set to fast mode by setting the bit to a '1'.
When the input capacitor values are larger than 0.47μF then the Turn_On_Time bit should be set to '0' for normal
turn-on time and higher delay. This allows sufficient time to charge the input capacitors to the ½ VDDLS bias
voltage.
POWER_ON BIT
The Power_On bit is the master control bit to activate or deactivate the LM49101. All registers can be loaded
independent of the Power_On bit setting as long as the IC is powered correctly. Cycling the Power_On bit does
not change the values of any registers nor return all bits to the default power on value of zero. The Power_On bit
only determines whether the IC is on or off.
EP BYPASS BIT
The EP Bypass bit is used to set the LM49101 to earpiece mode. When this bit is set the analog switch is
activated and the rest of the IC blocks except for the I2C circuitry will go into shutdown for minimal current
consumption.
HPR_SD BIT
The HPR_SD bit will deactivate the right headphone output amplifier. This bit is provided to reduce power
consumption when only one headphone output is needed.
MODE_CONTROL BITS
The LM49101 includes a comprehensive mixer multiplexer controlled through the I2C interface. The
mixer/multiplexer allows any input combination to appear on any output of LM49101. Multiple input paths can be
selected simultaneously. Under these conditions, the selected inputs are mixed together and output on the
selected channel. Table 5 shows how the input signals are mixed together for each possible input selection.
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INPUT MUTE BIT
The Input Mute bit will mute all inputs except the Bypass inputs when set to a '1'. This allows complete and quick
mute of the Mono, Left, and Right inputs without changing the Volume Control registers or HP_Gain bits. The
volume and HP_Gain bits retain their values when the Input Mute is enabled or disabled.
The Input Mute bit can be used to mute all the inputs when other chips in a system, such as the baseband IC,
create transients causing unwanted noise on the outputs of the LM49101. This added feature eliminates the
need for power cycling the LM49101.
LS_GAIN BIT
The loudspeaker amplifier can have an additional gain of 0dB or 6dB by using the LS_Gain bit. The Mono input
has 6dB of attenuation before the volume control (see Figure 1) while the Left and Right inputs do not. The
LS_Gain bit is used to account for the different attenuation levels for each input and to achieve maximum output
power. To obtain maximum output power on the loudspeaker outputs, the LS_Gain bit should be se to '1' for
Modes 1, 5, 9, 13.
HP_GAIN BITS
The headphone outputs have an additional, single volume control set by the three HP_Gain bits in the Output
Gain Control register. The HP_Gain volume setting controls the output level for both the left and the right
headphone outputs.
VOLUME CONTROL BITS
The LM49101 has three independent 32-step volume controls, one for each of the inputs. The five bits of the
Volume Control registers sets the volume for the specified input channel.
SHUTDOWN FUNCTION
The LM49101 features the following shutdown controls.
Bit D4 (GAMP_SD) of the GENERAL CONTROL register controls the gain amplifiers. When GAMP_SD = 1, it
disables the gain amplifiers that are not in use. For example, in Modes 1, 4 and 5, the Mono inputs are in use, so
the Left and Right input gain amplifiers are disabled, causing the IDD to be minimized.
Bit D0 (Power_On) of the GENERAL CONTROL register is the global shutdown control for the entire device. Set
Power_On = 0 for normal operation. Power_On = 1 overrides any other shutdown control bit.
DIFFERENTIAL AMPLIFIER EXPLANATION
The LM49101 features a differential input stage, which offers improved noise rejection compared to a singleended input amplifier. Because a differential input amplifier amplifies the difference between the two input
signals, any component common to both signals is cancelled. An additional benefit of the differential input
structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to
both inputs, and thus cancelled by the amplifier, the LM49101 can be used without input coupling capacitors
when configured with a differential input signal.
BRIDGE CONFIGURATION EXPLAINED
By driving the load differentially through the MONO outputs, an amplifier configuration commonly referred to as
“bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier
configuration where one side of the load is connected to ground.
A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides
differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output
power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable
output power assumes that the amplifier is not current limited or clipped.
22
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A bridge configuration, such as the one used in LM49101, also creates a second advantage over single-ended
amplifiers. Since the differential outputs are biased at half-supply, no net DC voltage exists across the load. This
eliminates the need for an output coupling capacitor which is required in a single supply, single-ended amplifier
configuration. Without an output coupling capacitor, the half-supply bias across the load would result in both
increased internal IC power dissipation and also possible loudspeaker damage.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or
single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an
increase in internal power dissipation. The power dissipation of the LM49101 varies with the mode selected. The
maximum power dissipation occurs in modes where all inputs and outputs are active (Modes 6, 7, 8, 9, 10, 11,
13, 14, 15). The power dissipation is dominated by the Class AB amplifier. The maximum power dissipation for a
given application can be derived from the power dissipation graphs or from Equation 1.
PDMAX = 4*(VDD)2/(2π2RL)
(1)
It is critical that the maximum junction temperature (TJMAX) of 150°C is not exceeded. TJMAX can be determined
from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the
thermal resistance of the application can be reduced from the free air value, resulting in higher PDMAX. Additional
copper foil can be added to any of the leads connected to the LM49101. It is especially effective when connected
to VDD, GND, and the output pins. Refer to Demonstration Board for an example of good heat sinking. If TJMAX
still exceeds 150°C, then additional changes must be made. These changes can include reduced supply voltage,
higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of output power.
Refer to the Typical Performance Characteristics curves for power dissipation information for different output
powers and output loading.
POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as
possible. Typical applications employ a 5V regulator with 10µF tantalum or electrolytic capacitor and a ceramic
bypass capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of
the LM49101. The selection of a bypass capacitor, especially CB, is dependent upon PSRR requirements, click
and pop performance, system cost, and size constraints.
GROUND REFERENCED HEADPHONE AMPLIFIER
The LM49101 features a low noise inverting charge pump that generates an internal negative supply voltage.
This allows the headphone outputs to be biased about GND instead of a nominal DC voltage, like traditional
headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220μF)
are not necessary. The coupling capacitors are replaced by two small ceramic charge pump capacitors, saving
board space and cost. Eliminating the output coupling capacitors also improves low frequency response. In
traditional headphone amplifiers, the headphone impedance and the output capacitor from a high-pass filter that
not only blocks the DC component of the output, but also attenuates low frequencies, impacting the bass
response. Because the LM49101 does not require the output coupling capacitors, the low frequency response of
the device is not degraded by external components. In addition to eliminating the output coupling capacitors, the
ground referenced output nearly doubles the available dynamic range of the LM49101 headphone amplifiers
when compared to a traditional headphone amplifier operating from the same supply voltage.
HEADPHONE & CHARGE PUMP SUPPLY VOLTAGE (VDDHP & VDDCP)
The headphone outputs are centered at ground by using dual supply voltages for the headphone amplifier. The
positive power supply is set by the voltage on the VDDHP pin while the negative supply is created with an internal
charge pump. The negative supply voltage is equal in magnitude but opposite in voltage to the voltage on the
VDDCP pin.
INPUT CAPACITOR SELECTION
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM49101. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high-pass filter is found using Equation 2 below.
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f = 1 / 2πRINCIN (Hz)
(2)
Where the value of RIN is given in Electrical Characteristics VDDLS = 3.3V, VDDHP = 2.75V and Electrical
Characteristics VDDLS = 5.0V, VDDHP = 2.75V as ZIN.
When the LM49101 is using a single-ended source, power supply noise on the ground is seen as an input signal.
Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example,
filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or
better are recommended for impedance matching and improved CMRR and PSRR.
CHARGE PUMP FLYING CAPACITOR (C1)
The flying capacitor (C1), see Figure 1, affects the load regulation and output impedance of the charge pump. A
C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued
C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2μF, the RDS(ON)
of the charge pump switches and the ESR of C1 and Cs3 dominate the output impedance. A lower value capacitor
can be used in systems with low maximum output power requirements.
CHARGE PUMP HOLD CAPACITOR (CS3)
The value and ESR of the hold capacitor Cs3 directly affects the ripple on VSSCP. Increasing the value of Cs3
reduces output ripple. Decreasing the ESR of Cs3 reduces both output ripple and charge pump output
impedance. A lower value capacitor can be used in systems with low maximum output power requirements.
SELECTION OF INPUT RESISTORS
The Bypass_In inputs connect to the loudspeaker output through an FET switch when EP Bypass is active (see
Figure 42). Because THD through this path is mainly dominated by the switch impedance variation, adding input
resistors (R3 and R4 in Figure 42) will help reduce impedance effects resulting in improved THD. For example, a
change in the switch impedance from 2Ω to 3Ω is a 67% change in impedance. If 10Ω input resistors are used
then the impedance change is from 12Ω to 13Ω, only 7.7% impedance variation. The analog switch impedance is
typically 2Ω to 3.4Ω. The switch impedance change is a result of heating and the increase in RDS(ON) of the FETs.
The value of the input resistors must be balanced against the amount of output current and the load impedance
on the loudspeaker outputs. A higher value input resistor reduces the effects of switch impedance variation but
also causes voltage drop and reduced power to the load on the loudspeaker outputs.
The current through the FET switch should not exceed 500mA or die heating may cause thermal shut down
activation and potential IC damage.
MINIMUM POWER OPERATION
The LM49101 has several options to reduce power consumption and is designed to conserve power when
possible. When a speaker only mode is selected the headphone sections are shutdown and the current drawn
from the VDDHP/VDDCP power supply will be zero. When a headphone mode is selected the current drawn from
the VDDLS supply is also reduced by shutting down unused circuitry. See the various Supply Current vs Supply
Voltage graphs in Typical Performance Characteristics.
To reduce power consumption further, the additional control bits GAMP_SD, LS (EP Mode), and HPR_SD are
provided. When low power consumption is more important than the THD performance of the loudspeaker the LS
(EP_mode) bit should be set to '1' saving approximately 0.5mA from the VDDLS supply. The GAMP_SD bit
should be set on to save approximately 0.4mA for each input shut down. For modes where only the mono input
is used, up to 0.8mA can be saved from the VDDLS supply. Also, the HPR_SD bit can be used to shut down the
right headphone channel reducing power consumption when only one amplifier headphone output is needed.
Additionally, the supply voltages for the different VDD pins (VDDLS, VDDHP, and VDDCP) can be set to the
minimum needed values to obtain the output power levels required by the design. By reducing the supply voltage
the total power consumption will be reduced.
For best system efficiency, a DC-DC converter (buck) can be used to power the VDDHP and VDDCP voltages
from the VDDLS supply instead of a linear regulator. DC-DC converters achieve much higher efficiency (> 90%)
than even a low dropout regulator (LDO).
24
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Demo Board Circuit
Figure 42. Demo Board Circuit
Demonstration Board
The demonstration board (see Figure 42) has connection and jumper options to be powered partially from the
USB bus or from external power supplies. Additional options are to power the I2C logic and loudspeaker amplifier
(VDDLS) from a single power supply or separate power supplies. The headphone amplifier and charge pump can
also be powered from the same supply as long as the voltage limits for each power supply are not exceeded,
although the option is not built into the board. See Operating Ratings for each supply's range limit. When
powered from the USB bus the I2CVDD will be set to 3.3V and the VDDLS will be set to 5V. Jumper headers J13
and J12 must be set accordingly. If a single power supply for I2CVDD and VDDLS is desired then header J5 should
be used with a jumper added to header J11 to connect I2CVDD to the external supply voltage connected to J5 (see
Figure 42).
Connection headers J1 and J2 are provided along with the stereo headphone jack J4 for easily connection and
monitoring of the headphone outputs.
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LM49101 DSBGA Demo Board Views
26
Figure 43. Composite View
Figure 44. Silk Screen
Figure 45. Top Layer
Figure 46. Internal Layer 1
Figure 47. Internal Layer 2
Figure 48. Bottom Layer
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LM49101 Reference Demo Board Bill Of Materials
Table 8. Bill Of Materials
Designator
Vlaue
Tolerance
Part Description
R1, R2
5.1kΩ
5%
1/10W, 0603 Resistors
R3, R4
10Ω
1%
1/10W, 0603 Resistors
R5
100kΩ
5%
1/10W, 0805 Resistor
CIN1, CIN2
CIN3, CIN4
1μF
10%
1206, X7R Ceramic Capacitor
CS1, CS4
CS5, CB
2.2μF
10%
Size A, Tantalum Capacitor
CS2
0.1μF
10%
0805, 16V, X7R Ceramic Capacitor
CS3, C1
2.2μF
10%
0603, 10V, X7R Ceramic Capacitor
Comment
U1
LM49101TM
J1, J2, J3
J5, J7, J8
J9, J10, J14
0.100" 1x2 header, vertical mount
Input, Output, VDD, GND
J11, J12, J13
0.100" 1x3 header, vertical mount
VDD Selects, VDD, I2CVDD, GND
J6
16 pin header
I2C Connector
J4
Headphone Jack
SW1
Momentary Push Switch
RESET function
PCB Layout Guidelines
This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power
and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual
results will depend heavily on the final layout.
General Mixed Signal Layout Recommendations
SINGLE-POINT POWER AND GROUND CONNECTIONS
The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can
be helpful in minimizing high frequency noise coupling between the analog and digital sections. It is further
recommended to put digital and analog power traces over the corresponding digital and analog ground traces to
minimize noise coupling.
PLACEMENT OF DIGITAL AND ANALOG COMPONENTS
All digital components and high-speed digital signals traces should be located as far away as possible from
analog components and circuit traces.
AVOIDING TYPICAL DESIGN AND LAYOUT PROBLEMS
Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB
layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90
degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise
coupling and cross talk.
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Revision History
28
Rev
Date
0.01
10/18/08
Initial released.
A
04/08/13
Changed layout of National Data Sheet to TI format.
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Description
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM49101TM/NOPB
ACTIVE
DSBGA
YFQ
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GL4
LM49101TMX/NOPB
ACTIVE
DSBGA
YFQ
25
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GL4
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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