LM49120, LM49120TLEVAL
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LM49120
SNAS431C – JUNE 2008 – REVISED MAY 2013
Audio Sub-System with Mono Class AB
Loudspeaker Amplifier and Stereo OCL/SE Headphone Amplifier
Check for Samples: LM49120, LM49120TLEVAL
FEATURES
DESCRIPTION
•
•
•
•
•
The LM49120 is a compact audio subsystem
designed for portable handheld applications such as
cellular phones. The LM49120 combines a mono
1.3W speaker amplifier, stereo 85mW/ch output
capacitorless headphone amplifier, 32 step volume
control, and an input mixer/multiplexer into a single
16–bump DSBGA package.
1
2
•
•
•
•
•
•
•
RF Immunity
Selectable OCL/SE Headphone Drivers
32 Step Volume Control
Click and Pop Suppression
Independent Speaker and Headphone Gain
Settings
Minimum External Components
Thermal Over Load Protection
Micro-power Shutdown
Space Saving 16–bump DSBGA Package
Thermal Shutdown Protection
Micro-power Shutdown
I2C Control Interface
The LM49120 has three input channels: two singleended stereo inputs and a differential mono input.
Each input features a 32-step digital volume control.
The headphone output stage features an 8 step (18dB – 0dB) attenuator, while the speaker output
stage has two selectable (0dB/+6dB) gain settings.
The digital volume control and mode control are
programmed through a two-wire I2C compatible
interface.
APPLICATIONS
•
•
•
Mobile Phones
PDAs
Portable Electronics
KEY SPECIFICATIONS
•
•
•
Output Power at VDD = 5V:
– Speaker: RL = 8Ω BTL, THD+N ≤ 1%: 1.3W
(typ)
– Headphone: RL = 32Ω, SE, THD+N ≤ 1%:
85mW (typ)
Output Power at VDD = 3.6V:
– Speaker: RL = 8Ω, BTL, THD+N ≤ 1%:
632mW (typ)
Output Power at VDD = 3.3V:
– Speaker: RL = 8Ω, BTL, THD+N ≤ 1%:
540mW (typ)
– Headphone: RL = 32Ω, OCL/SE, THD+N ≤
1%: 35mW (typ)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LM49120, LM49120TLEVAL
SNAS431C – JUNE 2008 – REVISED MAY 2013
www.ti.com
Typical Application
VDD
1 PF
0.1 PF ceramic
+
CS1
CIN4
CS2
Handsfree
Speaker
MONO_IN+
+
+
1 PF
CIN3
MONO_IN-
Class AB
+6 dB
8:
-
MONO -
+
1 PF
MONO +
+0
Volume Control
Mute to +18 dB
CIN2
RIN
Volume Control
Mute to +18 dB
+
AUDIO
INPUT
0.22 PF
CIN1
LIN
-18 ± 0 dB
(8 steps)
32:
VOC
LOUT
Volume Control
Mute to +18 dB
+
AUDIO
INPUT
ROUT
Mixer
and
Output
Mode
Select
32:
-18 ± 0 dB
(8 steps)
0.22 PF
CB
2
I CVDD
2
I C
Interface
+
SDA
Bias
Bypass
SCL
2.2 P F
GND
Figure 1. Output Capacitor-Less Configuration
VDD
0.1 PF ceramic
1 PF
+
CS1
CIN4
MONO_IN+
+
1 PF
CIN3
MONO_IN-
MONO +
+0
Volume Control
Mute to +18 dB
Class AB
8:
+6 dB
-
MONO -
+
1 PF
+
Handsfree
Speaker
CS2
RIN
Volume Control
Mute to +18 dB
+
0.22 PF
CO
32:
100 PF
VOC
LIN
+
Volume Control
Mute to +18 dB
LOUT
-18 ± 0 dB
(8 steps)
CO
+
CIN1
AUDIO
INPUT
ROUT
-18 ± 0 dB
(8 steps)
0.22 P F
2
I CVDD
SDA
32:
100 PF
CB
2
I C
Interface
Bias
Bypass
SCL
+
AUDIO
INPUT
Mixer
and
Output
Mode
Select
+
CIN2
2.2 P F
GND
The 6dB speaker gain applies only to the differential input path.
Figure 2. Single-Ended Configuration
2
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SNAS431C – JUNE 2008 – REVISED MAY 2013
Connection Diagram
Top View
1
2
3
4
A
VOC
VDD
ROUT
LOUT
B
MONO_IN+
BYPASS
LIN
RIN
C
MONO_IN-
I CVDD
SCL
SDA
D
MONO-
GND
VDD
MONO+
2
Figure 3. 16 Bump DSBGA Package
(Bump-Side Down)
See Package Number YZR0016
PIN DESCRIPTIONS
Bump
Name
A1
VOC
Headphone Center Amplifier Output
Description
A2
VDD
Headphone Power Supply
A3
ROUT
Right Channel Headphone Output
A4
LOUT
Left Channel Headphone Output
B1
MONO_IN+
B2
BYPASS
B3
LIN
Left Channel Input
B4
RIN
Right Channel Input
C1
MONO_IN-
Mono Inverting Input
C2
I2CVDD
C3
SCL
I2C Clock Input
C4
SDA
I2C Data Input
D1
MONO-
D2
GND
Ground
D3
VDD
Power Supply
D4
MONO+
Mono Non-inverting Input
Bias Bypass
I2C Interface Power Supply
Loudspeaker Inverting Output
Loudspeaker Non-inverting Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49120 LM49120TLEVAL
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LM49120, LM49120TLEVAL
SNAS431C – JUNE 2008 – REVISED MAY 2013
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Absolute Maximum Ratings (1) (2) (3)
Supply Voltage (1)
6.0V
−65°C to +150°C
Storage Temperature
Input Voltage
−0.3 to VDD +0.3
Power Dissipation (4)
Internally Limited
ESD Rating (5)
2000V
ESD Rating (6)
200V
Junction Temperature
Solder Information
150°C
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
(6)
220°C
θJA (typ) - YZR0016
62.3°C/W
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
The Electrical Characteristics tables list spacified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
Human body model, applicable std. JESD22-A114C.
Machine model, applicable std. JESD22-A115-A.
Operating Ratings
−40°C to 85°C
Temperature Range
2.7V ≤ VDD ≤ 5.5V
Supply Voltage (VDD)
Supply Voltage (I2CVDD)
4
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1.7V ≤ I2CVDD ≤ 5.5V
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49120 LM49120TLEVAL
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SNAS431C – JUNE 2008 – REVISED MAY 2013
Electrical Characteristics 3.3V (1) (2)
The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Parameter
Test Conditions
LM49120
Typ
(3)
Limits (4)
Units
(Limits)
8.0
mA (max)
VIN = 0, No Load
IDD
Supply Current
ISD
Shutdown Current
VOS
Output Offset Voltage
PO
Output Power
THD+N
Total Harmonic Distortion + Noise
Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15
OCL Headphone
6.2
Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15
SE Headphone
5.5
Output mode 1, 2, 3
OCL Headphone
4.1
Output mode 1, 2, 3
SE Headphone
5.5
Output mode 4, 8, 12
OCL Headphone
3.7
Output mode 4, 8, 12
SE Headphone
3.0
Shutdown Mode 0
0.01
mA
5.3
mA (max)
mA
4.7
mA (max)
mA
1
µA
VIN = 0V, Output Mode 10, LS output
10
VIN = 0V, Output Mode 10, HP output,
(OCL), 0dB (HP Output Gain)
mV
1.5
5
mV (max)
LSOUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
540
500
mW (min)
LOUT and ROUT; RL = 32Ω
THD+N = 1%; f = 1kHz, OCL, Mode 8
35
30
mW (min)
MONOOUT
f = 1kHz
POUT = 250mW; RL = 8Ω, BTL, Mode 1
0.05
%
LOUT and ROUT, f = 1kHz
POUT = 12mW; RL = 32Ω, SE, Mode 8
0.015
%
LOUT and ROUT, f = 1kHz
POUT = 12mW; RL = 32Ω, OCL, Mode 8
0.015
%
Speaker Amplifier; Mode 1
15
μV
Speaker Amplifier; Mode 2
24
μV
Speaker Amplifier; Mode 3
29
μV
Headphone Amplifier; SE, Mode 4
8
μV
Headphone Amplifier; SE, Mode 8
8
μV
Headphone Amplifier; SE, Mode 12
11
μV
Headphone Amplifier; OCL, Mode 4
8
μV
Headphone Amplifier; OCL, Mode 8
9
μV
Headphone Amplifier; OCL, Mode 12
12
μV
A-weighted,
inputs terminated to GND, Output referred
eOUT
(1)
(2)
(3)
(4)
Output Noise
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
The Electrical Characteristics tables list spacified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49120 LM49120TLEVAL
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LM49120, LM49120TLEVAL
SNAS431C – JUNE 2008 – REVISED MAY 2013
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Electrical Characteristics 3.3V(1)(2) (continued)
The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Parameter
LM49120
Test Conditions
Typ
(3)
Limits (4)
Units
(Limits)
VRIPPLE = 200mVPP; fRIPPLE = 217Hz, RL = 8Ω (Speaker); RL = 32Ω (Headphone)
CB = 2.2µF, BTL
All audio inputs terminated to GND; output referred
Speaker Output; Speaker Output Gain 6dB
Speaker Amplifier; Mode 1
79
dB
Speaker Amplifier; Mode 2
63
dB
Speaker Amplifier; Mode 3
62
dB
Speaker Amplifier Output; Speaker Output Gain 0dB
PSRR
Power Supply Rejection Ratio
Speaker Amplifier; Mode 1
84
dB
Speaker Amplifier; Mode 2
63
dB
Speaker Amplifier; Mode 3
62
dB
Headphone Amplifier; SE, Mode 4
83
dB
Headphone Amplifier; SE, Mode 8
84
dB
Headphone Amplifier; SE, Mode 12
78
dB
Headphone Amplifier; OCL, Mode 4
83
dB
Headphone Amplifier; OCL, Mode 8
80
dB
Headphone Amplifier; OCL, Mode 12
77
dB
Headphone Amplifier Output
VOL∈
Volume Control Step Size Error
VOLRANGE
Au(HP)
ZIN
CMRR
XTALK
TWU
6
±0.2
Maximum Attenuation
–86
Maximum Gain
18
17.4
18.6
dB (min)
dB (max)
Output Mode 1, 2, 3
96
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
Digital Volume Control Range
HP (SE) Mute Attenuation
MONO_IN Input Impedance
LIN and RIN Input Impedance
Common-Mode Rejection Ratio
Crosstalk
Wake-Up Time from Shutdown
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dB
–91
–81
dB (min)
dB (max)
dB
Maximum gain setting
12.5
10
15
Maximum attenuation setting
110
90
130
f = 217Hz, VCM = 1VPP,
Speaker, BTL, Mode 1,
RL = 8Ω
Differential Input
61
dB
f = 217Hz, VCM = 1VPP,
Headphone, OCL, Mode 4,
RL = 32Ω
Stereo Input
66
dB
Headphone; POUT = 12mW
f = 1kHz, OCL. Mode 8
–60
dB
Headphone; POUT = 12mW
f = 1kHz, SE, Mode 8
–72
dB
CB = 4.7μF, OCL
35
ms
CB = 2.2μF, SE,
Normal Turn On Mode
Turn_On_Time = 1
120
ms
CB = 2.2μF, OCL
30
ms
CB = 4.7μF, SE,
Fast Turn On Mode
Turn_On_Time = 0
130
ms
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49120 LM49120TLEVAL
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SNAS431C – JUNE 2008 – REVISED MAY 2013
Electrical Characteristics 5.0V (1) (2)
The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Parameter
Test Conditions
LM49120
Typ
(3)
Limits (4)
Units
(Limits)
VIN = 0, No Load
IDD
Supply Current
ISD
Shutdown Current
VOS
Output Offset Voltage
PO
Output Power
THD+N
Total Harmonic Distortion + Noise
Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15
OCL Headphone
7.2
mA
Output mode 5, 6, 7, 9, 10, 11, 13, 14, 15
SE Headphone
6.4
mA
Output mode 1, 2, 3
OCL Headphone
6.4
mA
Output mode 1, 2, 3
SE Headphone
4.8
mA
Output mode 4, 8, 12
OCL Headphone
4.4
mA
Output mode 4, 8, 12
SE Headphone
3.5
mA
Shutdown Mode 0
0.01
µA
VIN = 0V, Output Mode 10, LS output
10
mV
VIN = 0V, Output Mode 10, HP output,
(OCL), 0dB (HP Output Gain)
1.5
mV
LS OUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
1.3
W
LOUT and ROUT; RL = 32Ω
THD+N = 1%; f = 1kHz, OCL, Mode 8
85
mW
LSOUT
f = 1kHz
POUT = 250mW; RL = 8Ω, BTL, Mode 1
0.05
%
LOUT and ROUT, f = 1kHz
POUT = 12mW; RL = 32Ω, SE, Mode 8
0.015
%
LOUT and ROUT, f = 1kHz
POUT = 12mW; RL = 32Ω, OCL, Mode 8
0.015
%
Speaker Amplifier; Mode 1
17
μV
Speaker Amplifier; Mode 2
27
μV
Speaker Amplifier; Mode 3
33
μV
Headphone Amplifier; SE, Mode 4
8
μV
Headphone Amplifier; SE, Mode 8
8
μV
Headphone Amplifier; SE, Mode 12
12
μV
Headphone Amplifier; OCL, Mode 4
9
μV
Headphone Amplifier; OCL, Mode 8
9
μV
Headphone Amplifier; OCL, Mode 12
12
μV
A-weighted,
inputs terminated to GND, Output referred
eOUT
(1)
(2)
(3)
(4)
Output Noise
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
The Electrical Characteristics tables list spacified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49120 LM49120TLEVAL
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www.ti.com
Electrical Characteristics 5.0V(1)(2) (continued)
The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Parameter
LM49120
Test Conditions
Typ
(3)
Limits (4)
Units
(Limits)
VRIPPLE = 200mVPP; fRIPPLE = 217Hz, RL = 8Ω
(Speaker); RL = 32Ω (Headphone)
CB = 2.2µF, BTL
All audio inputs terminated to GND; output referred
Speaker Output; Speaker Output Gain 6dB
Speaker Amplifier; Mode 1
69
dB
Speaker Amplifier; Mode 2
60
dB
Speaker Amplifier; Mode 3
58
dB
Speaker Amplifier Output; Speaker Output Gain 0dB
PSRR
Power Supply Rejection Ratio
Speaker Amplifier; Mode 1
84
dB
Speaker Amplifier; Mode 2
63
dB
Speaker Amplifier; Mode 3
62
dB
Headphone Amplifier; SE, Mode 4
75
dB
Headphone Amplifier; SE, Mode 8
75
dB
Headphone Amplifier; SE, Mode 12
72
dB
Headphone Amplifier; OCL, Mode 4
75
dB
Headphone Amplifier; OCL, Mode 8
75
dB
Headphone Amplifier; OCL, Mode 12
72
dB
±0.2
dB
Headphone Amplifier Output
VOL∈
Volume Control Step Size Error
VOLRANGE
Au(HP)
ZIN
CMRR
XTALK
TWU
8
MONO_IN Input Impedance
LIN and RIN Input Impedance
Common-Mode Rejection Ratio
Crosstalk
Wake-Up Time from Shutdown
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dB
dB
–86
Maximum Gain
18
Output Mode 1, 2, 3
96
dB
Maximum gain setting
12.5
kΩ
kΩ
Maximum attenuation setting
110
kΩ
kΩ
f = 217Hz, VCM = 1VPP,
Speaker, BTL, Mode 1,
RL = 8Ω
Differential Input
61
dB
f = 217Hz, VCM = 1VPP,
Headphone, OCL, Mode 4,
RL = 32Ω
Stereo Input
66
dB
Headphone; POUT = 12mW
f = 1kHz, OCL, Mode 8
–54
dB
Headphone; POUT = 12mW
f = 1kHz, SE, Mode 8
–72
dB
CB = 4.7μF, OCL
28
ms
CB = 2.2μF, SE,
Normal Turn On Mode
Turn_On_Time = 1
151
ms
CB = 2.2μF, OCL
25
ms
CB = 4.7μF, SE,
Fast Turn On Mode
Turn_On_Time = 0
168
ms
Digital Volume Control Range
HP (SE) Mute Attenuation
–91
–81
Maximum Attenuation
dB
dB
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49120 LM49120TLEVAL
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SNAS431C – JUNE 2008 – REVISED MAY 2013
I2C Timing Characteristics 2.2V ≤ I2C_VDD ≤ 5.5V (1) (2)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ I2C_VDD ≤ 5.5V, unless otherwise specified.
Parameter
Test Conditions
LM49120
Typ
(3)
Limits
(4)
Units
(Limits)
t1
I2C Clock Period
2.5
µs (min)
t2
I2C Data Setup Time
100
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
t6
I2C Data Hold Time
100
ns (min)
2
2
VIH
I C Input Voltage High
0.7xI CVDD
V (min)
VIL
I2C Input Voltage Low
0.3xI2CVDD
V (max)
(1)
(2)
(3)
(4)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
The Electrical Characteristics tables list spacified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
I2C Timing Characteristics 1.7V ≤ I2C_VDD ≤ 2.2V (1) (2)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2C_VDD ≤ 2.2V, unless otherwise specified.
Parameter
Test Conditions
LM49120
Typ
(3)
Limits
(4)
Units
(Limits)
t1
I2C Clock Period
2.5
µs (min)
t2
I2C Data Setup Time
250
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
250
ns (min)
t5
Stop Condition Time
250
ns (min)
t6
I2C Data Hold Time
250
ns (min)
2
2
VIH
I C Input Voltage High
0.7xI CVDD
V (min)
VIL
I2C Input Voltage Low
0.3xI2CVDD
V (max)
(1)
(2)
(3)
(4)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
The Electrical Characteristics tables list spacified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM49120 LM49120TLEVAL
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Typical Performance Characteristics
Filter BW = 22kHz
Crosstalk
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW,
f = 1kHz, Mode 8, SE
0
0
-10
-10
-20
-20
-30
-30
CROSSTALK (dB)
CROSSTALK (dB)
Crosstalk
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW,
f = 1kHz, Mode 8, OCL
-40
-50
Right to Left
-60
Left to Right
-70
-50
Right to Left
-60
Left to Right
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
200
2k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4.
Figure 5.
Crosstalk
vs
Frequency
VDD = 5V, RL = 32Ω, PO = 30mW,
f = 1kHz, Mode 8, OCL
Crosstalk
vs
Frequency
VDD = 5V, RL = 32Ω, PO = 30mW,
f = 1kHz, Mode 8, SE
0
0
-10
-10
-20
-20
-30
-30
CROSSTALK (dB)
CROSSTALK (dB)
-40
-40
-50
Right to Left
-60
Left to Right
-70
-40
-50
Right to Left
-60
Left to Right
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
FREQUENCY (Hz)
20k
200
2k
FREQUENCY (Hz)
20k
Figure 6.
Figure 7.
Output Power
vs
Supply Voltage
VDD = 3.3V, RL = 32Ω
f = 1kHz, Mode 8, OCL
Output Power
vs
Supply Voltage
VDD = 5V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
140
2500
OUTPUT POWER (mW)
OUTPUT POWER (mW)
120
100
THD+N = 10%
60
40
20
THD+N = 1%
2000
1500
THD+N = 10%
1000
THD+N = 1%
500
10
0
2.5
10
3.0
3.5
4.0
4.5
5.0
5.5
0
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 8.
Figure 9.
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5.5
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Typical Performance Characteristics (continued)
Filter BW = 22kHz
Power Dissipation
vs
Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, Mode 8, OCL
Power Dissipation
vs
Output Power
VDD = 3.3V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
200
300
250
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
180
160
140
120
100
80
60
40
200
150
100
50
20
0
0
5
0
10 15 20 25 30 35 40 45 50
0
50
100
150
200
250
OUTPUT POWER/ CHANNEL (mW)
OUTPUT POWER/ CHANNEL (mW)
Figure 10.
Figure 11.
Power Dissipation
vs
Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, Mode 8, OCL
Power Dissipation
vs
Output Power
VDD =5V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
450
300
300
250
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
400
350
300
250
200
150
100
200
150
100
50
50
0
0
20
40
60
100
80
0
120
50
100
150
200
250
300
OUTPUT POWER/ CHANNEL (mW)
Figure 12.
Figure 13.
Supply Current
vs
Supply Voltage
VIN= GND, No load
THD+N
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
f = 22kHz, Mode 8, OCL
10
7.5
7.0
1
6.5
THD+N (%)
SUPPLY CURRENT (mA)
0
OUTPUT POWER/ CHANNEL (mW)
6.0
0.1
0.01
5.5
5.0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0.001
20
SUPPLY VOLTAGE (V)
Figure 14.
200
2k
20k
FREQUENCY (Hz)
Figure 15.
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Typical Performance Characteristics (continued)
Filter BW = 22kHz
THD+N
vs
Frequency
VDD = 3.3V, RL = 64Ω, PO = 24mW
f = 22kHz, Mode 4, BTL
10
10
1
1
THD+N (%)
THD+N (%)
THD+N
vs
Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
f = 22kHz, Mode 8, SE
0.1
0.01
0.01
200
2k
0.001
20
20k
FREQUENCY (Hz)
200
2k
FREQUENCY (Hz)
Figure 16.
Figure 17.
THD+N
vs
Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
f = 1kHz, Mode 1, Speaker
THD+N
vs
Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
f = 22kHz, Mode 8, OCL
10
10
1
1
THD+N (%)
THD+N (%)
0.001
20
0.1
0.01
200
2k
FREQUENCY (Hz)
0.1
0.001
20
20k
200
2k
20k
FREQUENCY (Hz)
Figure 18.
Figure 19.
THD+N
vs
Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
f = 22kHz, Mode 8, SE
THD+N
vs
Frequency
VDD = 5V, RL = 64Ω, PO = 72mW
f = 22kHz, Mode 4, BTL
10
10
1
1
THD+N (%)
THD+N (%)
20k
0.01
0.001
20
0.1
0.01
0.001
20
12
0.1
0.1
0.01
200
2k
20k
0.001
20
200
2k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
Filter BW = 22kHz
THD+N
vs
Frequency
VDD = 5V, RL = 8Ω, PO = 500mW
f = 1kHz, Mode 1, Speaker
THD+N
vs
Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, Mode 8, OCL
10
10
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.001
20
200
2k
0.01
10
20k
20
30
40 50 60
80 100
OUTPUT POWER (mW)
FREQUENCY (Hz)
Figure 22.
Figure 23.
THD+N
vs
Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, Mode 8, SE
THD+N
vs
Output Power
VDD = 3.3V, RL = 64Ω
f = 1kHz, Mode 4, BTL
10
1
1
THD+N (%)
THD+N (%)
10
0.1
0.1
0.01
10
20
30
40 50 60
0.01
10
80 100
20
30
40 50 60
80 100
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 24.
Figure 25.
THD+N
vs
Output Power
VDD = 3.3V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
THD+N
vs
Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, Mode 8, OCL
10
1
1
THD+N (%)
THD+N (%)
10
0.1
0.01
10
0.1
20
50
100
200
500
1k
0.01
10
OUTPUT POWER (mW)
20
40
60 80 100
200
OUTPUT POWER (mW)
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
Filter BW = 22kHz
THD+N
vs
Output Power
VDD = 5V, RL = 64Ω
f = 1kHz, Mode 4, BTL
10
10
1
1
THD+N (%)
THD+N (%)
THD+N
vs
Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, Mode 8, SE
0.1
0.01
0.1
0.01
0.001
10
20
40
60 80 100
200
0.001
10
20
40
60
100
200 300
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 28.
Figure 29.
THD+N
vs
Output Power
VDD = 5V, RL = 8Ω
f = 1kHz, Mode 1, Speaker
PSRR
vs
Frequency
VDD = 3.3V, RL = 8Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 1
0
10
-10
-20
-30
PSRR (dB)
THD+N (%)
1
0.1
-40
-50
-60
-70
-80
-90
14
20
50
100 200
500
1k
-100
20
2k
200
2k
20k
OUTPUT POWER (mW)
FREQUENCY (Hz)
Figure 30.
Figure 31.
PSRR
vs
Frequency
VDD = 3.3V, RL = 8Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 1
PSRR
vs
Frequency
VDD = 3.3V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 8, OCL
0
0
-10
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
PSRR (dB)
0.01
10
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
FREQUENCY (Hz)
200
2k
FREQUENCY (Hz)
Figure 32.
Figure 33.
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Typical Performance Characteristics (continued)
Filter BW = 22kHz
PSRR
vs
Frequency
VDD = 3.3V, RL = 32Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 8, OCL
0
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
0
-10
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
200
2k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 34.
Figure 35.
PSRR
vs
Frequency
VDD = 3.3V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 4, BTL
PSRR
vs
Frequency
VDD = 3.3V, RL = 64Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 4, BTL
0
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
0
-10
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
200
2k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 36.
Figure 37.
PSRR
vs
Frequency
VDD = 3.3V, RL = 8Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 1
PSRR
vs
Frequency
VDD = 5V, RL = 8Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 1
0
0
-10
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
PSRR (dB)
PSRR (dB)
PSRR (dB)
PSRR
vs
Frequency
VDD = 3.3V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 8, SE
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
FREQUENCY (Hz)
20k
Figure 38.
200
2k
FREQUENCY (Hz)
20k
Figure 39.
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Typical Performance Characteristics (continued)
Filter BW = 22kHz
16
PSRR
vs
Frequency
VDD = 5V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 8, SE
0
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
0
-10
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
FREQUENCY (Hz)
200
2k
FREQUENCY (Hz)
Figure 40.
Figure 41.
PSRR
vs
Frequency
VDD = 5V, RL = 64Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 4, BTL
PSRR
vs
Frequency
VDD = 5V, RL = 32Ω, CBYP = 4.7μF
VRIPPLE = 200mVP-P, MODE 8, SE
200
2k
20k
0
0
-10
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
PSRR (dB)
PSRR (dB)
PSRR
vs
Frequency
VDD = 5V, RL = 32Ω, CBYP = 2.2μF
VRIPPLE = 200mVP-P, MODE 8, OCL
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
FREQUENCY (Hz)
200
2k
FREQUENCY (Hz)
Figure 42.
Figure 43.
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APPLICATION INFORMATION
I2C COMPATIBLE INTERFACE
The LM49120 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM49120
and the master can communicate at clock rates up to 400kHz. Figure 44 shows the I2C interface timing diagram.
Data on the SDA line must be stable during the HIGH period of SCL. The LM49120 is a transmit/receive slaveonly device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a
START condition and a STOP condition (Figure 45). Each data word, device address and data, transmitted over
the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 46). The LM49120 device address
is 1111100.
I2C BUS FORMAT
The I2C bus format is shown in Figure 46. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0
indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the
slave device. Set R/W = 0; the LM49120 is a WRITE-ONLY device and will not respond the R/W = 1. The data is
latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last
address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is
generated by the slave device. If the LM49120 receives the correct address, the device pulls the SDA line low,
generating and acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data word is sent, the LM49120 sends another ACK bit. Following the
acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is
high.
Figure 44. I2C Timing Diagram
SDA
SCL
S
P
START condition
STOP condition
Figure 45. Start and Stop Diagram
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SCL
SDA
START
MSB
DEVICE ADDRESS
ACK
R/W
LSB
MSB
REGISTER DATA
ACK
LSB
STOP
Figure 46. Example Write Sequence
Table 1. Device Address
B7
B6
B5
B4
B3
B2
B1
B0 (R/W)
1
1
1
1
1
0
0
0
Device
Address
Table 2. Control Registers
B7
B6
B5
B4
B3
B2
B1
B0
2
PWR_On
Shutdown Control
0
0
0
OCL/SE
HP/BTL
SD_I CVDD
Turn_On _Time
Output Mode Control
0
1
0
0
MC3
MC2
MC1
MC0
Output Gain Control
1
0
0
0
LS_GAIN
HP_GAIN2
HP_GAIN1
HP_GAIN0
Mono Input Volume
Control
1
0
1
MG4
MG3
MG2
MG1
MG0
Left Input Volume
Control
1
1
0
LG4
LG3
LG2
LG1
LG0
Right Input Volume
Control
1
1
1
RG4
RG3
RG2
RG1
RG0
Table 3. Shutdown Control Register
Bit
Name
B4
OSC/SE
B3
Value
HP/BTL
SD_I2CVDD
B2
B1
TURN_ON_TIME
B0
PWR_ON
Description
0
Single-Ended headphone mode (Capacitively Coupled)
1
Output Capacitor-less (OCL) headphone mode
0
Single-ended stereo headphone output mode
1
Mono, BTL output mode.
0
I2CVDD acts as an active low RESET input. If I2CVDD drops below 1.1V,
the device is reset and the I2C registers are restored to their default
state.
1
Normal Operation. I2CVDD voltage does not reset the device
0
Fast turn on time (120ms)
1
Normal turn on time (130ms)
0
Device Disabled
1
Device Enabled
Table 4. Output Mode Control (HP/BTL = 0)
18
Output
Mode
Number
MC3
MC2
MC1
MC0
0
0
0
0
0
SD
SD
SD
1
0
0
0
1
GM x M
Mute
Mute
2
0
0
1
0
2 x (GL x L + GR x R)
Mute
Mute
3
0
0
1
1
2 x (GL x L + GR x R)
+ GM x M
Mute
Mute
4
0
1
0
0
SD
GM x M/2
GM x M/2
5
0
1
0
1
GM x M
GM x M/2
GM x M/2
6
0
1
1
0
2 x (GL x L + GR x R)
GM x M/2
GM x M/2
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HP R Output
HP L Output
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Table 4. Output Mode Control (HP/BTL = 0) (continued)
Output
Mode
Number
MC3
MC2
MC1
MC0
LS Output
HP R Output
HP L Output
7
0
1
1
1
2 x (GL x L + GR x R)
+ GM x M
GM x M/2
GM x M/2
8
1
0
0
0
SD
GR x R
GL x L
9
1
0
0
1
GM x M
GR x R
GL x L
10
1
0
1
0
2 x (GL x L + GR x R)
GR x R
GL x L
2 x (GL x L + GR x R)
+ GM x M
GR x R
GL x L
11
1
0
1
1
12
1
1
0
0
SD
GR x R + GM x M/2
GL x L + GM x M/2
13
1
1
0
1
GM x M
GR x R + GM x M/2
GL x L + GM x M/2
14
1
1
1
0
2 x (GL x L + GR x R)
GR x R + GM x M/2
GL x L + GM x M/2
1
2 x (GL x L + GR x R)
+ GM x M
GR x R + GM x M/2
GL x L + GM x M/2
15
1
1
1
Table 5. Output Mode Control (HP/BTL = 1)
Output
Mode
Number
MC3
MC2
MC1
MC0
LS Output
HP R Output
HP L Output
4
0
1
0
0
SD
GM x M+/2
GM x M-/2
5
0
1
0
1
GM x M
GM x M+/2
GM x M-/2
6
0
1
1
0
2 x (GL x L + GR x R)
GM x M /2
GM x M-/2
7
0
1
1
1
2 x (GL x L + GR x R)
+ GP x P
GM x M+/2
GM x M-/2
12
1
1
0
0
SD
GR x R + GM x M+/2
13
1
1
0
1
+
GM x M
GL x L + GM x M-/2
+
GL x L + GM x M-/2
+
GR x R + GM x M /2
14
1
1
1
0
2 x (GL x L + GR x R)
GR x R + GM x M /2
GL x L + GM x M-/2
15
1
1
1
1
2 x (GL x L + GR x R)
+ GM x M
GR x R + GM x M+/2
GL x L + GM x M-/2
Table 6. Volume Control Table
Volume Step
_G4
_G3
_G2
_G1
_G0
Gain (dB)
1
0
0
0
0
0
Mute
2
0
0
0
0
1
–46.50
3
0
0
0
1
0
–40.50
4
0
0
0
1
1
–34.50
5
0
0
1
0
0
–30.00
6
0
0
1
0
1
–27.00
7
0
0
1
1
0
–24.00
8
0
0
1
1
1
–21.00
9
0
1
0
0
0
–18.00
10
0
1
0
0
1
–15.00
11
0
1
0
1
0
–13.50
12
0
1
0
1
1
–12.00
13
0
1
1
0
0
–10.50
14
0
1
1
0
1
–9.00
15
0
1
1
1
0
–7.50
16
0
1
1
1
1
–6.00
17
1
0
0
0
0
–4.50
18
1
0
0
0
1
–3.00
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Table 6. Volume Control Table (continued)
Volume Step
_G4
_G3
_G2
_G1
_G0
Gain (dB)
19
1
0
0
1
0
–1.50
20
1
0
0
1
1
0.00
21
1
0
1
0
0
1.50
22
1
0
1
0
1
3.00
23
1
0
1
1
0
4.50
24
1
0
1
1
1
6.00
25
1
1
0
0
0
7.50
26
1
1
0
0
1
9.00
27
1
1
0
1
0
10.50
28
1
1
0
1
1
12.00
29
1
1
1
0
0
13.50
30
1
1
1
0
1
15.00
31
1
1
1
1
0
16.50
32
1
1
1
1
1
18.00
Table 7. Output Gain Control (Headphone)
HP_GAIN2
HP_GAIN1
HP_GAIN0
0
0
0
GAIN (dB)
0
0
0
1
–1.2
0
1
0
–2.5
0
1
1
–4.0
1
0
0
–6.0
1
0
1
–8.5
1
1
0
–12
1
1
1
–18
Table 8. Output Gain Control (Loudspeaker)
Bit
LS_GAIN
Value
Gain (dB)
Differential Input
Gain (dB)
Single-Ended Input
0
0
+6
1
+6
+12
BRIDGE CONFIGURATION EXPLAINED
The LM49120 loudspeaker amplifier is designed to drive a load differentially, a configuration commonly referred
to as a bridge-tied load (BTL). The BTL configuration differs from the single-ended configuration, where one side
of the load is connected to ground. A BTL amplifier offers advantages over a single-ended device. By driving the
load differentially, the output voltage is doubled, compared to a single-ended amplifier under similar conditions.
This doubling of the output voltage leads to a quadrupling of the output power, for example, the theoretical
maximum output power for a single-ended amplifier driving 8Ω and operating from a 5V supply is 390mW, while
the theoretical maximum output power for a BTL amplifier operating under the same conditions is 1.56W. Since
the amplifier outputs are both biased about VDD/2, there is no net DC voltage across the load, eliminating the DC
blocking capacitors required by single-ended, single-supply amplifiers.
Headphone Amplifier
The LM49120 headphone amplifier features two different operating modes, output capacitor-less (OCL) and
single-ended (SE) capacitor coupled mode.
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The OCL architecture eliminates the bulky, expensive output coupling capacitors required by traditional
headphone amplifiers. In OCL mode, the LM49120 headphone section uses three amplifiers. Two amplifiers
drive the headphones, while the third (VOC) is set to the internally generated bias voltage (typically VDD/2). The
third amplifier is connected to the return terminal of the headphone jack (Figure 1). In this configuration, the
signal side of the headphone is biased to VDD/2, the return is biased to VDD/2, thus there is no net DC voltage
across the headphone, eliminating the need for an output coupling capacitor. Removing the output coupling
capacitors from the headphone signal path reduces component count, reducing system cost and board space
consumption, as well as improving low frequency performance.
In OCL mode, the headphone return sleeve is biased to VDD/2. When driving headphones, the voltage on the
return sleeve is not an issue. However, if the headphone output is used as a line out, the VDD/2 can conflict with
the GND potential that the line-in would expect on the return sleeve. When the return of the headphone jack is
connected to GND the VOC amplifier of the LM49120 detects an output short circuit condition and is disabled,
preventing damage to the LM49120, and allowing the headphone return to be biased at GND.
Single-Ended, Capacitor Coupled Mode
In single-ended mode, the VOC amplifier is disabled, and the headphone outputs are coupled to the jack through
series capacitors, allowing the headphone return to be connected to GND (Figure 2). In SE mode, the LM49120
requires output coupling capacitors to block the DC component of the amplifier output, preventing DC current
from flowing to the load. The output capacitor and speaker impedance form a high pass filter with a -3dB roll-off
determined by:
f–3dB = 1 / 2πRLCO
(Hz)
(1)
Where RL is the headphone impedance, and CO is the value of the output coupling capacitor. Choose CO such
that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high results in poor low frequency
performance. Select capacitor dielectric types with low ESR to minimize signal loss due to capacitor series
resistance and maximize power transfer to the load.
Headphone Amplifier BTL Mode
The LM49120 headphone amplifiers feature a BTL mode where the two headphone outputs, LOUT and ROUT are
configured to drive a mono speaker differentially. In BTL mode, the amplifier accepts audio signals from either
the differential MONO inputs, or the single-ended stereo inputs, and converts them to a mono BTL output.
However, if the stereo inputs are 180° out of phase, no audio will be present at the amplifier outputs. Bit B3
(HP/BTL) in the Shutdown Control Register determines the headphone output mode. Set HP/BTL = 0 for stereo
headphone mode, set HP/BTL = 1 for BTL mode.
Input Mixer/Multiplexer
The LM49120 includes a comprehensive mixer multiplexer controlled through the I2C interface. The
mixer/multiplexer allows any input combination to appear on any output of the LM49120. Multiple input paths can
be selected simultaneously. Under these conditions, the selected inputs are mixed together and output on the
selected channel. Table 4 and Table 5 show how the input signals are mixed together for each possible input
selection.
Audio Amplifier Gain Setting
Each channel of the LM49120 has two separate gain stages. Each input stage features a 32-step volume control
with a range of -46dB to +18dB (Table 6). The loudspeaker output stage has two additional gain settings: 0dB
and +6dB (Table 8) when the differential MONO input is selected, and +6dB and +12dB when the single-ended
stereo inputs are selected. The headphone gain is not affected by the input mode. Each headphone output stage
has 8 gain settings (Table 7). This allows for a maximum separation of 22dB between the speaker and
headphone outputs when both are active.
Calculate the total gain of the given signal path as follows:
AVOL + AVOS = AVTOTAL (dB)
where
•
•
AVOL is the volume control level, AVOS is the output stage gain setting
AVTOTAL is the total gain for the signal path.
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POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM49120 has a pair of bridged-tied amplifiers driving a handsfree speaker, MONO. The
maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From
Equation 2, assuming a 5V power supply and an 8Ω load, the maximum MONO power dissipation is 633mW.
PDMAX-SPKROUT = 4(VDD)2/ (2π2 RL): Bridge Mode
(3)
The LM49120 also has a pair of single-ended amplifiers driving stereo headphones, ROUT and LOUT. The
maximum internal power dissipation for ROUT and LOUT is given by Equation 3 and Equation 4. From Equation 3
and Equation 4, assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT
is 40mW, or 80mW total.
PDMAX-LOUT = (VDD)2 / (2π2 RL): Single-ended Mode
PDMAX-ROUT = (VDD)2 / (2π2 RL): Single-ended Mode
(4)
(5)
The maximum internal power dissipation of the LM49120 occurs when all three amplifiers pairs are
simultaneously on; and is given by Equation 5.
PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT
(6)
The maximum power dissipation point given by Equation 5 must not exceed the power dissipation given by
Equation 6:
PDMAX = (TJMAX - TA) / θJA
(7)
The LM49120's TJMAX = 150°C. In the SQ package, the LM49120's θJA is 46°C/W. At any given ambient
temperature TA, use Equation 6 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 6 and substituting PDMAX-TOTAL for PDMAX' results in Equation 7. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the
LM49120's maximum junction temperature.
TA = TJMAX - PDMAX-TOTAL θJA
(8)
For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows
maximum mono power dissipation without exceeding the maximum junction temperature is approximately 121°C
for the SQ package.
TJMAX = PDMAX-TOTAL θJA + TA
(9)
Equation 8 gives the maximum junction temperature TJMAX. If the result violates the LM49120's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 5 is greater than that of Equation 6,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance). Refer to the
Typical Performance Characteristics curves for power dissipation information at lower output power levels.
PROPER SELECTION OF EXTERNAL COMPONENTS
Power Supply Bypassing/Filtering
Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass
capacitors as close to the device as possible. Place a 1μF ceramic capacitor from VDD to GND. Additional bulk
capacitance may be added as required.
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Input Capacitor Selection
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM49120. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high pass filter is found using Equation 10 below.
f = 1 / (2πRINCIN)
(Hz)
(10)
Where the value of RIN is given in the Electrical Characteristics Table.
High pass filtering the audio signal helps protect the speakers. When the LM49120 is using a single-ended
source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the
power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not
amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance
matching and improved CMRR and PSRR.
Bias Capacitor Selection
The LM49120 internally generates a VDD/2 common-mode bias voltage. The BIAS capacitor CBIAS, improves
PSRR and THD+N by reducing noise at the BIAS node. Use a 2.2µF ceramic placed as close to the device as
possible.
PCB LAYOUT GUIDELINES
Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due
to trace resistance between the LM49120 and the load results in decreased output power and efficiency. Trace
resistance between the power supply and ground has the same effect as a poorly regulated supply, increased
ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize
losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio
performance, minimizes crosstalk between channels and prevents digital noise from interfering with the audio
signal. Use of power and ground planes is recommended.
Place all digital components and route digital signal traces as far as possible from analog components and
traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines
must cross either over or under each other, ensure that they cross in a perpendicular fashion.
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REVISION HISTORY
24
Rev
Date
1.0
06/26/08
Initial release.
1.01
07/15/08
Edited the Ordering Information table.
C
05/03/13
Changed layout of National Data Sheet to TI format.
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Description
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Product Folder Links: LM49120 LM49120TLEVAL
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM49120TL/NOPB
ACTIVE
DSBGA
YZR
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GK2
LM49120TLX/NOPB
ACTIVE
DSBGA
YZR
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GK2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
