LM4921
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LM4921
SNAS178E – JULY 2003 – REVISED MAY 2013
Low Voltage I2S 16-Bit Stereo DAC with Stereo
Headphone Power Amplifiers and Volume Control
Check for Samples: LM4921
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
2
•
•
•
•
•
16-Bit Resolution Stereo DAC
I2S Digital Audio Data Serial Interface
SPI Serial Interface (Control Register)
Volume Control (32 steps; 1.5 dB Increments)
Up to 50mW/Channel Stereo Headphone
Amplifier
Zero Crossing Detection for Silent Attenuation
Steps
2.6VDC to 5.0VDC Digital Supply Voltage Range
2.6VDC to 5.5VDC Analog Supply Voltage Range
(See (1))
Unity-Gain Stable Headphone Amplifiers
Available in the 20-bump DSBGA Package
KEY SPECIFICATIONS
•
•
•
•
(1)
PSRR at 217Hz, A/DVDD = 3V, (See Figure 1):
52dB (typ)
POUT at AVDD = 3.0V, 32Ω
– < 0.05% THD: 13mW (typ)
– < 0.05% THD: 26mW (typ)
Supply Voltage Range
– DVDD: 2,6V to 5.0V
– AVDD: (See (1)) 2.6V to 5.5V
Shutdown Current: 1µA (typ)
Mobile Phones
PDAs
Portable Electronic Devices
DESCRIPTION
The LM4921 combines a 16-bit resolution stereo I2S
input digital-to-analog converter (DAC) with a stereo
headphone audio power amplifier. It is primarily
designed for demanding applications in mobile
phones and other portable communication device
applications. The LM4921 features an I2S serial
interface for the digital audio information and a 16-bit
SPI serial interface for internal register control and
communication. With AVDD and DVDD = 3.0VDC and
driving a 32Ω single-ended load to a 26mWRMS
output level the distortion (THD+N) of the LM4921 will
be less than 0.5%. The LM4921 also features a
programmable 32-step digital volume control
accessed through an SPI interface.
Boomer audio power amplifiers were designed
specifically to provide high quality output power with a
minimal amount of external components. It is,
therefore, ideally suited for mobile phone and other
low voltage applications where minimal power
consumption is a primary requirement.
The LM4921 features a low-power consumption
shutdown mode, and also has an internal thermal
shutdown protection mechanism.
Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0V
and 3.0V ≤ DVDD ≤ 5.0V.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LM4921
SNAS178E – JULY 2003 – REVISED MAY 2013
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Typical Application
DVDD
1PF
GNDD
DV DD
NC
+
32:
Control
Filter
32:
LPF
1 - Bit DAC
R - Amp
+
Serial
Interface
HP_R
100 PF
+
V REF
Clock Logic
SPI Control
V DD X
MCLK/XTAL_IN
SPI_ENABLE
100 PF
Digital Volume
Interpolation
SPI_CLK
SPI_DATA
HP_L
Digital
Generator
BYPASS
I2S_LRCLK
I2S_CLK
L - Amp
+
GNDX
I2S_DATA
LPF
1 - Bit DAC
XTAL_OUT
NC
I 2 S Digital Audio Serial Interface
NC
AVDD
AGND
2 PF
1 PF
AV DD
Figure 1. Typical Audio Amplifier Application Circuit
2
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Connection Diagrams
(1)
4
HP_R
AVDD
BYPASS
NC
SPI_
DATA
3
AGND
HP_L
NC
SPI_
ENABLE
SPI_
CLK
2
NC
OPEN
I2S_
LRCLK
I2S_
DATA
XTAL_
OUT
MCLK/
XTAL_
IN
1
GNDD
I2S_
CLK
DVDD
VDDX
GNDX
A
B
C
D
E
NC - No Connection
Figure 2. LM4921 20-Bump DSBGA Pin Configuration – Top View
See Package Number YZR0020
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LM4921
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LM4921 I/O PIN DESCRIPTIONS
4
PIN # (ITL)
PIN NAME
PIN TYPE
Input-I, Output-O,
Power-P, No ConnectNC
PIN DESCRIPTION
B1
I2S_CLK
I/O
I2S Clock
C2
I2S_DATA
I
I2S data
B2
I2S_WS
I/O
E3
SPI_CLK
I
SPI clcock
I2S L/R word select
E4
SPI_DATA
I
SPI data
D3
SPI_ENABLE
I
SPI Enable
E2
MCLK/XTAL_IN
I
Master Clock / Xtal input
D2
XTAL_OUT
O
Xtal output
C4
BYPASS
I/O
Analog VDD/2 bypass capacitor connection point
B4
AVDD
P
Analog supply
A3
AGND
P
Analog Ground
C1
DVDD
P
Digital Supply
A1
GNDD
P
Digital ground
D1
VDDX
P
XTAL Oscillator circuit supply
E1
GNDX
P
XTAL Oscillator circuit ground
B3
HP_L
O
HP left output
A4
HP_R
O
HP right output
A2
No Connect
O
Must let float
C3
No Connect
NC
NC
D4
No Connect
NC
NC
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Supply Voltage
6.0V
−65°C to +150°C
Storage Temperature
Input Voltage
Power Dissipation
-0.3V to VDD + 0.3V
(3)
ESD Susceptibility
Internally Limited
Human body model (4)
2000V
Machine model (5)
200V
Junction Temperature
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
150°C
θJA
60°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
All voltages are measured with respect to the GND pin, unless otherwise specified.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever
is lower.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF – 240pF discharged through all pins.
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
Supply Voltage
−40°C ≤ TA ≤ 85°C
DVDD
2.6V ≤ DVDD ≤ 5.0V
AVDD
2.6V ≤ AVDD ≤ 5.5V
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Electrical Characteristics DVDD = 3.0V, AVDD = 5.0V, RL = 32Ω (1) (2)
The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for TA = 25°C.
Symbol
DVDD
Parameter
Digital Power Supply Voltage
Conditions
LM4921
Typical
See
(6)
3.0
(6)
5.0
AVDD
Analog Power Supply Voltage
See
DIDD
Digital Power Supply Quiescent
Current
RLoad = ∞, fMLCK = 11.2896MHz
AIDD
Analog Power Supply Quiescent
Current
ISD
(3)
Limit (4) (5)
Units
(Limits)
V
V
3.5
7.5
mA (max)
RLoad = ∞, fMCLK = 0MHz
6
10
mA (max)
Total Shutdown Power Supply
Current
SHUTDOWN SPI bits 1 & 2 set to
logic 0,
SPI, MCLK and I2S inputs at GND
1
5
uA(max)
ISB
Standby Current
Analog and Digital together
All clocks off
25
uA
VFS
Full-Scale Output Voltage
Gain set at max
3.5
VP-P
THD+N
Total Harmonic Distortion + Noise
fIN = 1kHz, POUT = 12mW
(Vol Control = 11111, I2S input adj to
get 12mW at output)
0.03
%
PO
Headphone Amplifier Output Power
THD = (0.5%), fOUT = 1kHz
50
40
mW (min)
PSRR
Power Supply Rejection Ratio
AVDD CBYPASS = 2.0µF
VRIPPLE = 200mVP-P 217Hz
62
45
dB (min)
SNR
Signal-to-Noise Ratio
fIN = 1kHz sinewave at -60dBFS,
A-weighted-fCONV = 44.1kHz
82
dB
DR
Dynamic Range
fIN = 1kHz sinewave at -60dBFS,
A-weighted
84
dB
ΔACH-CH
Channel-to-Channel Gain Mismatch
fIN = 1kHz
0.06
dB
XTALK
Channel-to-Channel Crosstalk
fCONV = 44.1kHz,
fIN = 1kHz sinewave at -3dBFS
72
dB
Volume Control Range
Minimum Attenuation
Maximum Attenuation
+3.0
-43.5
dB
dB
1.5
dB
-102
dB
Volume Control Control Step Size
Mute Attenuation
(1)
(2)
(3)
(4)
(5)
(6)
6
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
All voltages are measured with respect to the GND pin, unless otherwise specified.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0V and 3.0V ≤ DVDD ≤ 5.0V.
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Electrical Characteristics DVDD = 3.0V, AVDD = 3.0V, RL = 32Ω (1) (2)
The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for TA = 25°C.
Symbol
DVDD
Parameter
Digital Power Supply Voltage
Conditions
LM4921
Typical
See
(6)
3.0
(6)
3.0
AVDD
Analog Power Supply Voltage
See
DIDD
Digital Power Supply Quiescent
Current
RLoad = ∞, fMLCK = 11.2896MHz
AIDD
Analog Power Supply Quiescent
Current
ISD
(3)
Limit (4) (5)
Units
(Limits)
V
V
3.5
7.5
mA (max)
RLoad = ∞, fMCLK = 0MHz
5
9.0
mA (max)
Total Shutdown Power Supply
Current
SHUTDOWN SPI bits 1 & 2 set to
logic 0,
SPI, MCLK and I2S inputs at GND
1
uA(max)
ISB
Standby Current
Analog and Digital together
All clocks off
15
uA
VFS
Full-Scale Output Voltage
Gain set at max
2.6
VP-P
THD+N
Total Harmonic Distortion + Noise
fIN = 1kHz, POUT = 12mW
(Vol Cont = 11011, I2S input adj to
get 12mW at output)
0.05
%
PO
Headphone Amplifier Output Power
THD = (0.5%), fOUT = 1kHz
26
mW (min)
PSRR
Power Supply Rejection Ratio
AVDD CBYPASS = 2.0µF
VRIPPLE = 200mVP-P 217Hz
52
dB (min)
SNR
Signal-to-Noise Ratio
fIN = 1kHz sinewave at -60dBFS,
A-weighted-fCONV = 44.1kHz
79
dB
DR
Dynamic Range
fIN = 1kHz sinewave at -60dBFS,
A-weighted
81
dB
ΔACH-CH
Channel-to-Channel Gain Mismatch
fIN = 1kHz
0.06
dB
XTALK
Channel-to-Channel Crosstalk
fCONV = 44.1kHz,
fIN = 1kHz sinewave at -3dBFS
72
dB
Volume Control Range
Minimum Attenuation
Maximum Attenuation
0
-43.5
dB
dB
1.5
dB
-100
dB
Volume Control Control Step Size
Mute Attenuation
(1)
(2)
(3)
(4)
(5)
(6)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
All voltages are measured with respect to the GND pin, unless otherwise specified.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0V and 3.0V ≤ DVDD ≤ 5.0V.
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Electrical Characteristics-Digital Inputs DVDD = 3.0V (1) (2)
The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
Resolution
LM4921
Typical
(3)
Limit (4) (5)
Units
(Limits)
16
Bits
11.2896
(256FS)
MHz
I2S
Audio Data Interface Format
Standard, I2S, Left Justified
fMCLK
Master Clock Frequency
fCONV
Sampling Clock Frequency Range
48
kHz
VIL
Digital Input: Logic Low Voltage
Level
0.3 X DVDD
V (max)
VIH
Digital Input: Logic High Voltage
Level
0.7 X DVDD
V (min)
tES
SPI_ENB Setup Time
20
ns (min)
tEH
SPI_ENB Hold Time
20
ns (min)
tEL
SPI_ENB Low Time
30
ns (min)
tDS
SPI_Data Setup Time
20
ns (min)
tDH
SPI_Data Hold Time
20
ns (min)
tCS
SPI_CLK Setup Time
20
ns (min)
tCH
SPI_CLK High Pulse Width
100
ns (min)
tCL
SPI_CLK Low Pulse Width
100
ns (min)
fCLK
SPI_CLK Frequency
5
MHz (max)
tCLKI2S
I2S_CLK Period
50
ns (min)
tHII2S
I2S_CLK High Pulse Width
20
ns (min)
20
ns (min)
44.1
2
tLOI2S
I S_CLK Low Pulse Width
I2S_LRCLK Duty Cycle
50
%
tSLRCLK
I2S_LRCLK to I2S_CLK Setup Time
20
ns (min)
tHLRCLK
I2S_LRCLK to I2S_CLK Hold Time
20
ns (min)
tSDI S
I2S_Data to I2S_CLK Setup Time
20
ns (min)
tHDI2S
I2S_Data to I2S_CLK Hold Time
20
ns (min)
2
(1)
(2)
(3)
(4)
(5)
8
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
All voltages are measured with respect to the GND pin, unless otherwise specified.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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Typical Performance Characteristics
THD+N vs Output Power
THD+N vs Output Power
10
TOTAL HARMONIC DISTORTION (%)
TOTAL HARMONIC DISTORTION (%)
10
1.0
.1
.01
1m
5m
10m 20m
1.0
.1
.01
1m
50m 100m
5m
POWER (W)
1. Analog VDD = 5V, Digital VDD = 3V
RL = 32Ω, 44.1 kHz Sample Rate
R & L Channels, Vol = 3dB, Frequency in = 1kHz
Figure 3.
50m 100m
Analog VDD = 3V, Digital VDD = 3V
RL = 32Ω, 44.1 kHz Sample Rate R & L Channels Shown
Vol = 3dB, Frequency in = 1kHz
Figure 4.
THD+N vs Output Power
THD+N vs Frequency
10
TOTAL HARMONIC DISTORTION (%)
10
TOTAL HARMONIC DISTORTION (%)
10m 20m
POWER (W)
1.0
.1
.01
1m
1.0
.1
.01
5m
10m 20m
50m 100m
20
100
POWER (W)
1k
10k 20k
FREQUENCY (Hz)
Analog VDD = 2.6V, Digital VDD = 2.6V
RL = 32Ω, 4.1 kHz Sample Rate
R & L Channels Shown, Vol = 3dB, Frequency in = 1kHz
Figure 5.
Analog VDD = 5V, Digital VDD = 3V
RL = 32Ω, Power Level = 50mW,
R & L Channels Shown , 44.1kHz Sample Rate
Figure 6.
THD+N vs Frequency
THD+N vs Frequency
10
TOTAL HARMONIC DISTORTION (%)
TOTAL HARMONIC DISTORTION (%)
10
1.0
.1
1.0
.1
.01
.01
20
20
100
1k
10k 20k
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Analog VDD = 3V, Digital VDD = 3V
RL = 32Ω, Power Level = 12mW
R & L Channels Shown, 44.1kHz Sample Rate
Figure 7.
Analog VDD = 2.6V, Digital VDD = 2.6V
RL = 32Ω, Power Level = 12mW
R & L Channels Shown, 44.1kHz Sample Rate
Figure 8.
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Typical Performance Characteristics (continued)
Crosstalk
Frequency Response
0
10
-10
0
-30
AMPLITUDE (dB)
CROSSTALK (dB)
-20
-40
-50
-60
-70
-80
-20
-40
-60
-80
-90
-100
20
-100
100
1k
20
10k 20k
100
1k
Analog VDD = 5V, Digital VDD = 3V
RL = 32Ω, Vol = 0dB
44.1kHz Sample Rate, 0dB FFS
Figure 10.
Analog VDD = 3V, Digital VDD = 3V
RL = 32Ω, Vol = 3dB
44.1kHz Sample Rate, -3dB FFS
Figure 9.
Linearity
ANALOG OUTPUT SIGNAL AMPLITUDE (dB)
ANALOG OUTPUT SIGNAL AMPLITUDE (dB)
Linearity
10
0
-20
-40
-60
-80
-100
-90 -80 -70 -60 -50 -40 -30 -20 -10
0
10
0
-20
-40
-60
-80
-100
-90 -80 -70 -60 -50 -40 -30 -20 -10
DIGITAL INPUT SIGNAL AMPLITUDE (dB)
Analog VDD = 3V, Digital VDD = 3V
RL = 32Ω, 44.1kHz Sample Rate
Figure 12.
Noise Floor
Noise Floor
0
0
-20
-20
-40
-40
AMPLITUDE (dB)
AMPLITUDE (dB)
0
DIGITAL INPUT SIGNAL AMPLITUDE (Db)
Analog VDD = 5V, Digital VDD = 3V
RL = 32Ω, 44.1kHz Sample Rate
Figure 11.
-60
-80
-100
-60
-80
-100
-130
-130
20
100
1k
10k 20k
20
FREQUENCY (Hz)
Analog VDD = 5V, Digital VDD = 3V
RL = 32Ω, Vol = 3dB
44.1kHz Sample Rate
Figure 13.
10
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
100
1k
10k 20k
FREQUENCY (Hz)
Analog VDD = 3V, Digital VDD = 3V
RL = 32Ω, Vol = 0dB
44.1kHz Sample Rate
Figure 14.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
0
0
-20
-20
AMPLITUDE (dB)
AMPLITUDE (dB)
PSRR vs Frequency
-40
-60
-80
-40
-60
-80
-100
-100
20
100
1k
10k 20k
20
FREQUENCY (HZ)
100
1k
10k 20k
FREQUENCY (Hz)
Analog VDD = 5V, Digital VDD = 3V
RL = 32Ω, Vol = 3dB
44.1kHz Sample Rate
Figure 15.
Analog VDD = 3V, Digital VDD = 3V
RL = 32Ω, Vol = 0dB
44.1kHz Sample Rate
Figure 16.
FFT @ 1kHz -60dB
FFT @ 1kHz 0dB
0
0
-40
AMPLITUDE (dB)
AMPLITUDE (dB)
-20
-60
-80
-100
-40
-70
-100
-130
-130
20
100
1k
10k 20k
20
FREQUENCY (Hz)
100
1k
10k 20k
FREQUENCY (Hz)
Analog VDD = 5V, Digital VDD = 3V
RL = 32Ω, Vol = 3dB
44.1kHz Sample Rate
Figure 17.
Analog VDD = 5V, Digital VDD = 3V
RL = 32Ω, Vol = 3dB
44.1 kHz Sample Rate
Figure 18.
FFT @ 1kHz -60dB
FFT @ 1kHz 0dB
0
0
-40
AMPLITUDE (dB)
AMPLITUDE (dB)
-20
-60
-80
-100
-40
-70
-100
-130
-130
20
100
1k
10k 20k
20
FREQUENCY (Hz)
Analog VDD = 3V, Digital VDD = 3V
RL = 32Ω, Vol = 0dB
44.1kHz Sample Rate
Figure 19.
100
1k
10k 20k
FREQUENCY (Hz)
Analog VDD = 3V, Digital VDD = 3V
RL = 32Ω, Vol = 0dB
44.1kHz Sample Rate
Figure 20.
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APPLICATION INFORMATION
SPI OPERATIONAL DESCRIPTION
The serial data bits are organized into a field which contains 16 bits of data defined by Table 1. Bits 1 & 2
determine the output mode of the LM4921 as shown in Table 2. Bits 7 through 11 determine the volume level
setting as illustrated by Table 3. Bit 12 sets the Bypass capacitor charging time.
Table 1. Bit Allocation
BIT #
Default Val
Function
Description
0 (LSB)
0
RESET_B
RESET_B = 0, Resets the DAC
Must be high for the part to run.
1
0
2
0
MODE CONTROL
See Table 2
3
0
MASTER/SLAVE
0 = SLAVE, 1 = MASTER
4
0
RESOLUTION
0 = 16 bit, 1 = 32 bit
5
0
RESERVED
Should always be set to '1'
6
0
ZERO CROSSING SET
0 = ZXD ENABLE, 1 = ZXD DISABLE
7
0
VOLUME CONTROL
See Table 3
8
0
9
0
10
0
11
0
12
0
BYP CHARGE RATE
0 = 1X, 1 = 2X
13
0
RESERVED
14
0
RESERVED
15 (MSB)
0
RESERVED
Should always be set to '0'
MODE CONTROL
Sets the modes as outlined in Table 2.
Table 2. Output Mode Selection (Bits 1 & 2 above)
Output Mode #
BIT 2
BIT 1
0
0
0
MODE
SD
1
0
1
STANDBY
2
1
0
MUTE
3
1
1
ACTIVE
Shutdown turns off the part completely for maximum power savings. The Standby mode turns off the clock but
still consumes more power than the shutdown mode. However, coming out of standby mode allows the part to
turn back on faster than from shutdown. In Mute mode the clocks remain on which uses more power but allows
faster recovery and the ability to supply clock signals to other devices which is important when the part is used in
master mode. Active mode turns the part on for normal operation.
MASTER/SLAVE SELECT
Allows the part to act as a master and supply the clock for the rest of the system or be a slave to the system
clock.
RESOLUTION SET
Sets the resolution to be either 16 or 32 bits of stereo audio information. For most applications this will be set at
16 bits.
12
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ZERO CROSSING DETECT SET
This pin turns on the zero crossing detection circuit. With this circuit enabled the part will not allow a volume step
change, or shutdown mode, or standby mode to occur until the audio input signal passes through zero. This pin
should be set to on for most applications.
VOLUME CONTROL
The internal Stereo Volume Control is set by changing bits 7 through 11 in the SPI interface, as shown in Table 3
below. The zero dB setting is for 3V VDD operation and the +3dB is for 5V VDD.
Table 3. Volume Control Settings
Gain (dB)
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
-43.5
0
0
0
0
0
-42.0
0
0
0
0
1
-40.5
0
0
0
1
0
-39.0
0
0
0
1
1
-37.5
0
0
1
0
0
-36.0
0
0
1
0
1
-34.5
0
0
1
1
0
-33.0
0
0
1
1
1
-31.5
0
1
0
0
0
-30.0
0
1
0
0
1
-28.5
0
1
0
1
0
-27.0
0
1
0
1
1
-25.5
0
1
1
0
0
-24.0
0
1
1
0
1
-22.5
0
1
1
1
0
-21.0
0
1
1
1
1
-19.5
1
0
0
0
0
-18.0
1
0
0
0
1
-16.5
1
0
0
1
0
-15.0
1
0
0
1
1
-13.5
1
0
1
0
0
-12.0
1
0
1
0
1
-10.5
1
0
1
1
0
-9.0
1
0
1
1
1
-7.5
1
1
0
0
0
-6.0
1
1
0
0
1
-4.5
1
1
0
1
0
-3.0
1
1
0
1
1
-1.5
1
1
1
0
0
0.0
1
1
1
0
1
1.5
1
1
1
1
0
3.0
1
1
1
1
1
HP_L & HP_R
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BYPASS CHARGE RATE BIT 12
This control pin allows the user to change the Bypass Capacitor's charge rate by a factor of two. Setting this bit
at zero will set the circuit to it's normal 1x rate. Setting the bit to High will double the charge rate and allow the
part to turn on faster with a slight degradation in turn on click/pop noise.
BITS 5, 13, 14, and 15
Bits 13, 14, and 15 are all reserve bits and must be set to low/zero/ground.
Bit 5 must be set High.
SPI CONTROL INTERFACE BUS (J1)
SPI DATA: This is the serial data pin.
SPI CLK: This is the clock input pin.
SPI ENABLE: This is the SPI enable pin.
SPI TIMING DIAGRAM
SPI OPERATIONAL REQUIREMENTS
1. The maximum clock rate is 5MHz for the CLK pin.
2. CLK must remain logic-high for at least 100ns (tCH ) after the rising edge of CLK, and CLK must remain logiclow for at least 100ns (tCL ) after the falling edge of CLK.
3. Data bits are written to the DATA pin with the least significant bit (LSB) first.
4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 20ns
(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 20ns (tDH) after the rising
edge of CLK and stabilize before the next rising edge of CLK.
5. ENABLE should be logic-high only during serial data transmission.
6. ENABLE must be logic-high at least 20ns (tES ) before the first rising edge of CLK, and ENABLE has to remain
logic-high at least 20ns (tEH ) after the sixteenth rising edge of CLK.
7. If ENABLE remains logic-low for more than 10ns before all 16 bits are transmitted then the data latch will be
aborted.
8. If ENABLE is logic-high for more than 16 CLK pulses then only the first 16 data bits will be latched and
activated at rising edge of sixteenth CLK.
9. ENABLE must remain logic-low for at least 30ns (tEL ).
10. Coincidental rising or falling edges of CLK and ENABLE are not allowed. If CLK is to be held logic-high after
the data transmission, the falling edge of CLK must occur at least 20ns (tCS ) before ENABLE transitions to logichigh for the next set of data.
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I2S INTERFACE BUS (J2 - See Figure 21 )
The I2S standard provides a uni-directional serial interface designed specifically for digital audio. For the
LM4921, the interface provides access to a 48kHz, 16 bit full-range stereo audio DAC. This interface uses a
three wire system of clock (I2S_CLK), data (I2S_DATA), and word select (I2S_WS, sometimes called Right/Left
Select).
A bit clock (I2S_CLK) at 32 or 64 times the sample frequency is established by the I2S system master and the
word select (I2S_WS) line is driven at a frequency equal to the sampling rate of the audio data, in this case
48kHz. The word line is registered to change on the positive edge of the bit clock. The serial data (I2S_DATA) is
sent MSB first, again registers on the positive edge of the bit clock, delayed by 1 bit clock cycle relative to the
changing of the word line (typical I2S format).
MCLK/XTAL_IN (S1 MCLK SEL - See Figure 21)
This is the input for an external Master Clock. The jumper at S1 must be removed (disconnecting the onboard
crystal from the circuit) when using an external Master Clock.
STEREO HEADPHONE OUTPUT JACK (J3 - See Figure 21)
This is the stereo headphone output. Each channel is single-ended, with 100uF DC output blocking capacitors
mounted on the demo board (C6 and C7). These capacitors are necessary to block the 1/2 VDD DC bias and
prevent it from flowing through the headphone speakers (DC current will destroy most audio speakers) while
allowing the audio ac signal to pass through. The jack features a typical stereo headphone pinout.
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LM4921ITL DEMO BOARD OPERATION
The LM4921ITL demo board is a complete evaluation platform (Parallel Port SPI Interface Card and control
software available), designed to give easy access to the control pins of the part and comprise all the necessary
external passive components. There are separate analog and digital supply connectors, SPI interface bus (J1)
for the control lines, I2S interface bus (J2) for full-range digital audio, stereo headphone output (J3), and an
external MCLK input (P1) for use in place of the crystal on the demoboard.
Red Banana
Plug
C3
1 PF
VDDD
E
4
D3
E
3
NC KEY
SPI_DAT
A
SPI_ENABL
E
SPI_CL
K
HP
R
B
3
C6
A
4
C7
C4
BYPAS
S
HEADPHONE
JACK
J3
100 PF
100 PF
Right Out Test Jack
Ground
Black
Banana
Plug
I2S_DAT
A
I2S_CL
KI2S_WS
(LRCLK)
GND
X
GND
D
C2
B
1
B
2
10
9
8
7
6
5
4
3
2
1
C8
2.2 PF
Analo
g
Ground
Black Banana
Plug
(1)
HP
L
U1
LM4921ITL
J2
I2S
Interface
C5
1 PF
N
C
N
C
N
C
A
2
D4
C3
N
C
N
C
N
C
Right Out Test
RedJack
Banana
Plug
E
1
A
1
6
5
4
3
2
1
GND
A
J1
MCLK/XTAL
IN
XTAL
OUT
VDDX D1
C1
CA
P
E
2
D2
1
2
C4
1 PF
Left Out Test Jack
Ground
Black
Banana
Plug
C2
VDDD
CA
P
Digital VDD
VDDD
Red Banana
Plug
B
4
CRYSTA
L
C1
MCLK
IN
P
1
SPI
Interface
1M
Y
1
VDDA
VDDA
MCL
K
SE
L
Analog VDD
A
3
S
1
R1
Left Out Test
RedJack
Banana
Plug
Digita
l
Ground
Black Banana
Plug
Parallel Port SPI Interface Card and control software available.
Figure 21. LM4921ITL Demo Board Schematic
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DEMO BOARD BILL OF MATERIALS
Texas Instruments Bill of Material
Analog Audio LM4921ITL20 Eval Board
Assembly Part Number: 980011973-100
Revision A
Item
Part Number
Part Description
Qty
1
551011973-001
LM4921 Eval Board PCB etch 001
1
Ref Designator
2
LM4921 ITL20 DSBGA 20 Bumps
1
U1
3
Cer Cap 22pF 50V 10%, size 1206
2
C1, C2
4
Cer Cap 0.1pF 50V 10%, size 1206
1
C4
5
Tant Cap 1µF 16V 10%, 3216
3
C3, C5, C8
6
Tant Cap 220µF 16V 10%, 7243
2
C6, C7
7
1 meg ohm
1
R1
8
Crystal 11.2896MHz
1
Y1
9
Phone Jack 3.5mm Stereo
1
J3
10
Jumper Header 1X2
2
P1, S1
11
Jumper Header 1X3
2
J1
12
Jumper Header 1X5
2
J2
13
PCB Banana Jack,
Black-Mouser 164-6218
4
A GND, D GND, GND (2)
14
PCB Banana Jack,
Red-Mouser 164-6219
4
A VDD, D VDD, HP L, HP R
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DEMO BOARD ARTWORKS
Figure 22. Silkscreen Layer
Figure 23. Top Layer
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Figure 24. Mid Layer 1
Figure 25. Mid Layer 2
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Figure 26. Bottom Layer
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SNAS178E – JULY 2003 – REVISED MAY 2013
REVISION HISTORY
Changes from Revision D (May 2013) to Revision E
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM4921ITL/NOPB
ACTIVE
DSBGA
YZR
20
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
G
B9
LM4921ITLX/NOPB
ACTIVE
DSBGA
YZR
20
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
G
B9
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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