LM4926TL/NOPB

NRND LM4926 www.ti.com LM4926 SNAS266C – JUNE 2005 – REVISED MAY 2013 Ground-Referenced, Ultra Low Noise, Fixed Gain, 80mW Stereo Headphone Amplifier Check for Samples: LM4926 FEATURES DESCRIPTION • • • • • The LM4926 is a ground referenced, fixed-gain audio power amplifier capable of delivering 80mW of continuous average power into a 16Ω single-ended load with less than 1% THD+N from a 3V power supply. 1 2 • • Ground Referenced Outputs High PSRR Available in Space-Saving DSBGA Package Ultra Low Current Shutdown Mode Improved Pop & Click Circuitry Eliminates Noises Suring Turn-On and Turn-Fff Transitions No Output Coupling Capacitors, Snubber Networks, Bootstrap Capacitors, or GainSetting Resistors Required Shutdown Either Channel Independently APPLICATIONS • • • • • Notebook PCs Mobile Phone PDAs Portable Electronic Devices MP3 Players KEY SPECIFICATIONS • • • • • Improved PSRR at 217Hz, 70dB (Typ) Power Output at VDD = 3V RL = 16Ω, THD ≦ 1%, 80mW (Typ) Shutdown Current, 0.01µA (Typ) Internal Fixed Gain, 1.5V/V (Typ) Operating Voltage, 1.6V to 4.2V The LM4926 features a new circuit technology that utilizes a charge pump to generate a negative reference voltage. This allows the outputs to be biased about ground, thereby eliminating outputcoupling capacitors typically used with normal singleended loads. The LM4926 features an Automatic Standby Mode circuitry (patent pending). In the absence of an input signal, after approximately 12 seconds, the LM4926 goes into low current standby mode. The LM4926 recovers into full power operating mode immediately after a signal is applied to either the left or right input pins. This feature saves power supply current in battery operated applications. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. The LM4926 does not require output coupling capacitors or bootstrap capacitors, and therefore is ideally suited for mobile phone and other low voltage applications where minimal power consumption is a primary requirement. The LM4926 features a low-power consumption shutdown mode selectable for either channel separately. This is accomplished by driving either the SD_RC (Shutdown Right Channel) or SD_LC (Shutdown Left Channel) (or both) pins with logic low, depending on which channel is desired shutdown. Additionally, the LM4926 features an internal thermal shutdown protection mechanism. The LM4926 contains advanced pop & click circuitry that eliminates noises which would otherwise occur during turn-on and turn-off transitions. The LM4926 has an internal fixed gain of 1.5V/V. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated NRND LM4926 SNAS266C – JUNE 2005 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Typical Application CPVDD C3 D1 + C4 4.7 PF 0.1 PF ceramic A3 30 k: 0.39 PF + Rf 20 k: C1 + B2 VIN1 D2 Ri Ci SD_LC Shutdown Control B1 SD_RC Headphone Jack Click/Pop Suppression A4 C1 Charge Pump 2.2 PF C4 0.39 PF + + 20 k: A1 C2 Ri Ci 30 k: VIN2 Rf D4 D3 B4 A2 C2 2.2 PF Figure 1. Typical Audio Amplifier Application Circuit 1 2 3 4 A R_IN SGND CPVDD CCP+ B SD_RC SD_LC PGND C L_IN R_OUT CCP- D AVDD L_OUT -AVDD VCP_OUT DSBGA Package Top View See Package Number YZE0014 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 NRND LM4926 www.ti.com SNAS266C – JUNE 2005 – REVISED MAY 2013 PIN FUNCTIONS Pin Name Function A1 R_IN Right Channel Input A2 SGND Signal Ground A3 CPVDD Charge Pump Power Supply A4 CCP+ Positive Terminal - Charge Pump Flying Capacitor B1 SD_RC Active-Low Shutdown, Right Channel B2 SD_LC Active-Low Shutdown, Left Channel B4 PGND Power Ground C1 L_IN Left Channel Input C2 R_OUT Right Channel Input C4 CCP- Negative Terminal - Charge Pump Flying Capacitor D1 +AVDD Positive Power Supply - Amplifier D2 L_OUT Left Channel Output D3 -AVDD Negative Power Supply - Amplifier D4 VCP_OUT Charge Pump Power Output Absolute Maximum Ratings (1) Supply Voltage 4.5V −65°C to +150°C Storage Temperature Input Voltage -0.3V to VDD + 0.3V Power Dissipation (2) Internally Limited ESD Susceptibility (3) 2000V ESD Susceptibility (4) 200V Junction Temperature Thermal Resistance (1) (2) (3) (4) (5) 150°C θJA (typ) YZE0014 (5) 86°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions that specify performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given; however, the typical value is a good indication of device performance. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4926, see power de-rating currents for more information. Human body model, 100pF discharged through a 1.5kΩ resistor. Machine Model, 220pF - 240pF discharged through all pins. θJA value is measured with the device mounted on a PCB with a 3” x 1.5”, 1oz copper heatsink. Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ 85°C 1.6V ≤ VDD ≤ 4.2V Supply Voltage (VDD) Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 3 NRND LM4926 SNAS266C – JUNE 2005 – REVISED MAY 2013 www.ti.com Electrical Characteristics VDD = 3V (1) The following specifications apply for VDD = 3V and 16Ω load unless otherwise specified. Limits apply to TA = 25°C. Symbol Parameter Quiescent Power Supply Current Auto Standby Mode IDD Quiescent Power Supply Current Full Power Mode Typ (2) VIN = 0V, inputs terminated both channels enabled 2.3 VIN = 0V, inputs terminated both channels enabled 7 VIN = 0V, inputs terminated one channel enabled 5 ISD Shutdown Current VSD_LC = VSD_RC = GND VOS Output Offset Voltage RL = 32Ω, VIN = 0V AV Voltage Gain ΔAV RIN PO LM4926 Conditions Limit (3) (4) Units (Limits) mA 10 mA (max) mA 0.1 1.8 µA (max) 0.7 5 mV (max) –1.5 V/V Gain Match 1 % Input Resistance 20 Output Power THD+N Total Harmonic Distortion + Noise PSRR Power Supply Rejection Ratio Full Power Mode 15 25 kΩ (min) kΩ (max) THD+N = 1% (max); f = 1kHz, RL = 16Ω, one channel 80 mW THD+N = 1% (max); f = 1kHz, RL = 32Ω, one channel 65 mW THD+N = 1% (max); f = 1kHz, RL = 16Ω, (two channels in phase) 43 38 mW (min) THD+N = 1% (max); f = 1kHz, RL = 32Ω, (two channels in phase) 50 45 mW (min) PO = 60mW, f = 1kHz, RL = 16Ω single channel 0.04 PO = 50mW, f = 1kHz, RL = 32Ω single channel 0.03 % VRIPPLE = 200mVp-p, Input Referred SNR Signal-to-Noise Ratio VIH Shutdown Input Voltage High f = 217Hz 70 f = 1kHz 65 f = 20kHz 50 RL = 32Ω, POUT = 20mW, (A-weighted) f = 1kHz, BW = 20Hz to 22kHz dB 100 dB VIH = 0.7*CPVD V D VIL VIL = 0.3*CPVD Shutdown Input Voltage Low V D TWU Wake Up Time From Shutdown 5 µs 60 dB ∞ 60 kΩ XTALK Crosstalk RL = 16Ω, PO = 1.6mW, f = 1kHz ZOUT Output Impedance Input Terminated Input not terminated IL Input Leakage ±0.1 nA Input Voltage Threshold 2.8 mVp VIN (1) (2) (3) (4) 4 THRESH All voltages are measured with respect to the GND pin unless otherwise specified. Typicals are measured at 25°C and represent the parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 NRND LM4926 www.ti.com SNAS266C – JUNE 2005 – REVISED MAY 2013 External Components Description (See Figure 1) Components Functional Description 1. Ci Input coupling capacitor which blocks the DC voltage at the amplifier's input terminals. Also creates a high-pass filter with Ri at fC = 1/(2πRiCi). Refer to the section Proper Selection of External Components, for an explanation of how to determine the value of Ci. 2. C1 Flying capacitor. Low ESR ceramic capacitor (≤100mΩ) 3. C2 Output capacitor. Low ESR ceramic capacitor (≤100mΩ) 4. C3 Tantalum capacitor. Supply bypass capacitor which provides power supply filtering. Refer to the POWER SUPPLY BYPASSING section for information concerning proper placement and selection of the supply bypass capacitor. 5. C4 Ceramic capacitor. Supply bypass capacitor which provides power supply filtering. Refer to the POWER SUPPLY BYPASSING section for information concerning proper placement and selection of the supply bypass capacitor. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 5 NRND LM4926 SNAS266C – JUNE 2005 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics 20 10 10 1 1 THD + N (%) THD + N (%) 20 THD+N vs Frequency VDD = 1.6V, RL = 16Ω, PO = 1mW 0.1 0.1 0.01 0.001 20 0.01 100 1k 0.001 20 10k 20k Figure 3. THD+N vs Frequency VDD = 1.8V, RL = 16Ω, PO = 5mW THD+N vs Frequency VDD = 1.8V, RL = 32Ω, PO = 5mW 20 1 1 0.1 0.1 0.01 100 1k 0.001 20 10k 20k 1k 10k 20k FREQUENCY (Hz) Figure 4. Figure 5. THD+N vs Frequency VDD = 3V, RL = 16Ω, PO = 50mW THD+N vs Frequency VDD = 3V, RL = 32Ω, PO = 50mW 20 10 1 1 0.1 0.1 0.01 6 100 FREQUENCY (Hz) THD + N (%) THD + N (%) 0.01 10 0.001 20 10k 20k Figure 2. 10 20 1k FREQUENCY (Hz) 10 0.001 20 100 FREQUENCY (Hz) THD + N (%) THD + N (%) 20 THD+N vs Frequency VDD = 1.6V, RL = 32Ω, PO = 1mW 0.01 100 1k 10k 20k 0.001 20 100 1k FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Figure 7. Submit Documentation Feedback 10k 20k Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 NRND LM4926 www.ti.com SNAS266C – JUNE 2005 – REVISED MAY 2013 Typical Performance Characteristics (continued) 20 10 10 1 1 THD + N (%) THD + N (%) 20 THD+N vs Frequency VDD = 3.6V, RL = 16Ω, PO = 100mW 0.1 0.1 0.01 0.01 0.001 20 100 1k 0.001 20 10k 20k 1k 10k 20k FREQUENCY (Hz) Figure 8. Figure 9. THD+N vs Frequency VDD = 4.2V, RL = 16Ω, PO = 150mW THD+N vs Frequency VDD = 4.2V, RL = 32Ω, PO = 150mW 20 10 10 1 1 0.1 0.1 0.01 0.01 0.001 20 100 1k 0.001 20 10k 20k 1k 10k 20k FREQUENCY (Hz) Figure 10. Figure 11. THD+N vs Output Power VDD = 1.6V, RL = 16Ω, f = 1kH One channel enabled THD+N vs Output Power VDD = 1.6V, RL = 32Ω, f = 1kHz One channel enabled 20 10 20 10 1 1 0.1 0.1 0.01 0.001 100µ 100 FREQUENCY (Hz) THD + N (%) THD + N (%) 100 FREQUENCY (Hz) THD + N (%) THD + N (%) 20 THD+N vs Frequency VDD = 3.6V, RL = 32Ω, PO = 100mW 0.01 1m 10m 0.001 10µ 100µ 1m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 7 NRND LM4926 SNAS266C – JUNE 2005 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) 20 10 THD+N vs Output Power VDD = 1.6V, RL = 16Ω, f = 1kHz Two channels in phase THD+N vs Output Power VDD = 1.6V, RL = 32Ω, f = 1kHz Two channels in phase 20 10 1 THD + N (%) THD + N (%) 1 0.1 0.1 0.01 0.01 0.001 100µ 1m 0.001 10µ 10m 10m 20m Figure 15. THD+N vs Output Power VDD = 1.8V, RL = 16Ω, f = 1kHz One channel enabled THD+N vs Output Power VDD = 1.8V, RL = 32Ω, f = 1kHz One channel enabled 20 10 20 10 1 1 0.1 0.1 0.01 0.01 0.001 1m 10m 0.001 10µ 20m 100µ 1m 10m 20m OUTPUT POWER (W) OUTPUT POWER (W) Figure 16. Figure 17. THD+N vs Output Power VDD = 1.8V, RL = 16Ω, f = 1kHz Two channels in phase THD+Nvs Output Power VDD = 1.8V, RL = 32Ω, f = 1kHz Two channels in phase 20 10 20 10 1 1 THD + N (%) THD + N (%) 1m Figure 14. THD + N (%) THD + N (%) OUTPUT POWER (W) 0.1 0.1 0.01 0.01 0.001 1m 8 100µ OUTPUT POWER (W) 10m 20m 0.001 10µ 100µ 1m OUTPUT POWER (W) OUTPUT POWER (W) Figure 18. Figure 19. Submit Documentation Feedback 10m 20m Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 NRND LM4926 www.ti.com SNAS266C – JUNE 2005 – REVISED MAY 2013 Typical Performance Characteristics (continued) 20 10 THD+N vs Output Power VDD = 3.0V, RL = 16Ω, f = 1kHz One channel enabled 20 10 1 THD + N (%) THD + N (%) 1 0.1 0.1 0.01 0.01 0.001 1m 10m 0.001 10µ 100m 100m 200m THD+N vs Output Power VDD = 3.0V, RL = 16Ω, f = 1kHz Two channels in phase THD+N vs Output Power VDD = 3.0V, RL = 32Ω, f = 1kHz Two channels in phase 20 10 1 1 THD + N (%) THD + N (%) 10m Figure 21. 0.1 0.1 0.01 0.01 10m 0.001 10µ 100m OUTPUT POWER (W) 100µ 1m 10m 100m 200m OUTPUT POWER (W) Figure 22. Figure 23. THD+N vs Output Power VDD = 3.6V, RL = 16Ω, f = 1kHz One channel enabled THD+N vs Output Power VDD = 3.6V, RL = 32Ω, f = 1kHz One channel enabled 20 20 10 10 1 1 THD + N (%) THD + N (%) 1m Figure 20. 20 10 0.1 0.1 0.01 0.01 0.001 1m 100µ OUTPUT POWER (W) OUTPUT POWER (W) 0.001 1m THD+N vs Output Power VDD = 3.0V, RL = 32Ω, f = 1kHz One channel enabled 10m 100m 200m 0.001 1m 10m OUTPUT POWER (W) OUTPUT POWER (W) Figure 24. Figure 25. 100m 200m Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 9 NRND LM4926 SNAS266C – JUNE 2005 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) THD+N vs Output Power VDD = 3.6V, RL = 32Ω, f = 1kHz two channels in phase 20 20 10 10 1 1 THD + N (%) THD + N (%) THD+N vs Output Power VDD = 3.6V, RL = 16Ω, f = 1kHz Two channels in phase 0.1 0.1 0.01 0.01 0.001 1m 20 10 10m 100m 200m 0.001 1m OUTPUT POWER (W) OUTPUT POWER (W) Figure 26. Figure 27. THD+N vs Output Power VDD = 4.2V, RL = 16Ω, f = 1kHz One channel enabled THD+N vs Output Power VDD = 4.2V, RL = 32Ω, f = 1kHz One channel enabled 20 10 1 THD + N (%) THD + N (%) 1 0.1 0.01 0.1 0.01 0.001 10m 100m 0.001 1m 1 10m 100m Figure 29. THD+N vs Output Power VDD = 4.2V, RL = 16Ω, f = 1kHz Two channels in phase THD+N vs Output Power VDD = 4.2V, RL = 32Ω, f = 1kHz Two channels in phase 20 10 20 10 1 1 0.1 0.1 0.01 0.01 0.001 10m 1 OUTPUT POWER (W) Figure 28. THD + N (%) THD + N (%) OUTPUT POWER (W) 100m 1 OUTPUT POWER (W) 0.001 1m 10m 100m 1 OUTPUT POWER (W) Figure 30. 10 100m 200m 10m Figure 31. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 NRND LM4926 www.ti.com SNAS266C – JUNE 2005 – REVISED MAY 2013 Typical Performance Characteristics (continued) PSRR vs Frequency VDD = 1.6V, RL = 16Ω 0 PSRR vs Frequency VDD = 1.6V, RL = 32Ω 0 -20 -20 Full Power Mode -60 -80 -100 -120 -80 -100 -140 Auto Standby Mode -160 Auto Standby Mode -160 20 100 1k 10k 20k 20 100 1k FREQUENCY (Hz) FREQUENCY (Hz) Figure 32. Figure 33. PSRR vs Frequency VDD = 3V, RL = 16Ω 0 10k 20k PSRR vs Frequency VDD = 3V, RL = 32Ω 0 -20 -20 Full Power Mode -40 Full Power Mode -40 -60 LEVEL (dB) LEVEL (dB) -60 -120 -140 -80 -100 -120 -60 -80 -100 -120 -140 -140 Auto Standby Mode Auto Standby Mode -160 -160 20 100 1k 10k 20k 20 100 1k FREQUENCY (Hz) FREQUENCY (Hz) Figure 34. Figure 35. PSRR vs Frequency VDD = 4.2V, RL = 16Ω PSRR vs Frequency VDD = 4.2V, RL = 32Ω 10k 20k 0 0 -20 -20 Full Power Mode -40 -40 -60 -60 LEVEL (dB) LEVEL (dB) Full Power Mode -40 LEVEL (dB) LEVEL (dB) -40 -80 -100 Full Power Mode -80 -100 -120 -120 -140 -140 Auto Standby Mode Auto Standby Mode -160 -160 20 100 1k 10k 20k 20 100 1k FREQUENCY (Hz) FREQUENCY (Hz) Figure 36. Figure 37. 10k 20k Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 11 NRND LM4926 SNAS266C – JUNE 2005 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) 300 Output Power vs Supply Voltage RL = 16Ω, one channel 250 OUTPUT POWER (mW) OUTPUT POWER (mW) 250 10% THD+N 200 150 100 0 1.4 10% THD+N 150 100 50 1% THD+N 2.0 3.2 2.6 3.8 0 1.4 4.4 2.6 2.0 3.2 3.8 4.4 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 38. Figure 39. Output Power vs Supply Voltage RL = 16Ω, 2 channels in phase Output Power vs Supply Voltage RL = 32Ω, 2 channels in phase 250 OUTPUT POWER (mW) 250 OUTPUT POWER (mW) 200 1% THD+N 50 300 Output Power vs Supply Voltage RL = 32Ω, one channel 200 10% THD+N 150 100 200 150 10% THD+N 100 50 50 1% THD+N 0 1.4 12 2.6 3.2 3.8 1% THD+N 0 1.4 4.4 2.6 3.2 3.8 4.4 SUPPLY VOLTAGE (V) Figure 40. Figure 41. Supply Current vs Supply Voltage RL = 16Ω Representation of Automatic Standby Mode Behavior VDD = 3V Full Power Mode (2-ch) 4 10 3 8 6 2 VIN (mVp) 6 Auto Standby Mode 1 2 0 0 -1 -2 4 IDD (mA) 4 8 -4 -2 -6 2 0 1.4 1.95 2.45 2.95 3.45 3.95 -3 -8 -4 -10 4.5 0 5 10 15 20 25 30 35 40 TIME (s) SUPPLY VOLTAGE (V) Figure 42. 12 2.0 SUPPLY VOLTAGE (V) 10 SUPPLY CURRENT (mA) 2.0 Figure 43. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 NRND LM4926 www.ti.com SNAS266C – JUNE 2005 – REVISED MAY 2013 APPLICATION INFORMATION SUPPLY VOLTAGE SEQUENCING It is a good general practice to first apply the supply voltage to a CMOS device before any other signal or supply on other pins. This is also true for the LM4926 audio amplifier which is a CMOS device. Before applying any signal to the inputs or shutdown pins of the LM4926, it is important to apply a supply voltage to the VDD pins. After the device has been powered, signals may be applied to the shutdown pins (see MICRO POWER SHUTDOWN) and input pins. ELIMINATING THE OUTPUT COUPLING CAPACITOR The LM4926 features a low noise inverting charge pump that generates an internal negative supply voltage. This allows the outputs of the LM4926 to be biased about GND instead of a nominal DC voltage, like traditional headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220µF) are not necessary. The coupling capacitors are replaced by two, small ceramic charge pump capacitors, saving board space and cost. Eliminating the output coupling capacitors also improves low frequency response. In traditional headphone amplifiers, the headphone impedance and the output capacitor form a high pass filter that not only blocks the DC component of the output, but also attenuates low frequencies, impacting the bass response. Because the LM4926 does not require the output coupling capacitors, the low frequency response of the device is not degraded by external components. In addition to eliminating the output coupling capacitors, the ground referenced output nearly doubles the available dynamic range of the LM4926 when compared to a traditional headphone amplifier operating from the same supply voltage. OUTPUT TRANSIENT ('CLICK AND POPS') ELIMINATED The LM4926 contains advanced circuitry that virtually eliminates output transients ('clicks and pops'). This circuitry prevents all traces of transients when the supply voltage is first applied or when the part resumes operation after coming out of shutdown mode. AMPLIFIER CONFIGURATION EXPLANATION As shown in Figure 1, the LM4926 has two internal operational amplifiers. The two amplifiers have internally configured gain, the closed loop gain is set by selecting the ratio of Rf to Ri. Consequently, the gain for each channel of the IC is AV = -(Rf / Ri) = 1.5 V/V (1) where RF = 30kΩ and Ri = 20kΩ. Since this is an output ground-referenced amplifier, by driving the headphone through ROUT (Pin C2) and LOUT (Pin D2), the LM4926 does not require output coupling capacitors. The typical single-ended amplifier configuration requires large, expensive output capacitors. POWER DISSIPATION Power dissipation is a major concern when using any power amplifier and must be thoroughly understood to ensure a successful design. Equation 2 states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and driving a specified output load. PDMAX = (VDD) 2 / (2π2RL) (2) Since the LM4926 has two operational amplifiers in one package, the maximum internal power dissipation point is twice that of the number which results from Equation 2. Even with large internal power dissipation, the LM4926 does not require heat sinking over a large range of ambient temperatures. From Equation 2, assuming a 3V power supply and a 16Ω load, the maximum power dissipation point is 28mW per amplifier. Thus the maximum package dissipation point is 56mW. The maximum power dissipation point obtained must not be greater than the power dissipation that results from Equation 3: PDMAX = (TJMAX - TA) / (θJA) (3) Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4926 13 NRND LM4926 SNAS266C – JUNE 2005 – REVISED MAY 2013 www.ti.com For the DSBGA package, θJA = 105°C/W. TJMAX = 150°C for the LM4926. Depending on the ambient temperature, TA, of the system surroundings, Equation 3 can be used to find the maximum internal power dissipation supported by the IC packaging. If the result of Equation 2 is greater than that of Equation 3, then either the supply voltage must be decreased, the load impedance increased or TA reduced. For the typical application of a 3V power supply, with a 16Ω load, the maximum ambient temperature possible without violating the maximum junction temperature is approximately 144°C provided that device operation is around the maximum power dissipation point. Power dissipation is a function of output power and thus, if typical operation is not around the maximum power dissipation point, the ambient temperature may be increased accordingly. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 3V power supply typically use a 4.7µF capacitor in parallel with a 0.1µF ceramic filter capacitor to stabilize the power supply's output, reduce noise on the supply line, and improve the supply's transient response. Keep the length of leads and traces that connect capacitors between the LM4926's power supply pin and ground as short as possible. AUTOMATIC STANDBY MODE The LM4926 features Automatic Standby Mode circuitry (patent pending). In the absence of an input signal, after approximately 12 seconds, the LM4926 goes into low current standby mode. The LM4926 recovers into full power operating mode immediately after a signal, which is greater than the input threshold voltage, is applied to either the left or right input pins. The input threshold voltage is not a static value, as the supply voltage increases, the input threshold voltage decreases. This feature reduces power supply current consumption in battery operated applications. Please see also the graph entitled Representation of Automatic Standby Mode Behavior in the Typical Performance Characteristics section. To ensure correct operation of Automatic Standby Mode, proper layout techniques should be implemented. Separating PGND and SGND can help reduce noise entering the LM4926 in noisy environments. Auto Standby mode works best when output impedance of the audio source driving LM4926 is equal or less than 50 Ohms. While Automatic Standby Mode reduces power consumption very effectively during silent periods, maximum power saving is achieved by putting the device into shutdown when it is not in use. MICRO POWER SHUTDOWN The voltage applied to the SD_LC (shutdown left channel) pin and the SD_RC (shutdown right channel) pin controls the LM4926’s shutdown function. When active, the LM4926’s micropower shutdown feature turns off the amplifiers’ bias circuitry, reducing the supply current. The trigger point is 0.3*CPVDD for a logic-low level, and 0.7 x CPVDD for logic-high level. The low 0.01µA (typ) shutdown current is achieved by applying a voltage that is as near as ground a possible to the SD_LC/SD_RC pins. A voltage that is higher than ground may increase the shutdown current. There are a few ways to control the micro-power shutdown. These include using a single-pole, single-throw switch, a microprocessor, or a microcontroller. When using a switch, connect an external 100kΩ pull-up resistor between the SD_LC/SD_RC pins and VDD. Connect the switch between the SD_LC/SD_RC pins and ground. Select normal amplifier operation by opening the switch. Closing the switch connects the SD_LC/SD_RC pins to ground, activating micro-power shutdown. The switch and resistor specify that the SD_LC/SD_RC pins will not float. This prevents unwanted state changes. In a system with a microprocessor or microcontroller, use a digital output to apply the control voltage to the SD_LC/SD_RC pins. Driving the SD_LC/SD_RC pins with active circuitry eliminates the pull-up resistor. SELECTING PROPER EXTERNAL COMPONENTS Optimizing the LM4926's performance requires properly selecting external components. Though the LM4926 operates well when using external components with wide tolerances, best performance is achieved by optimizing component values. Charge Pump Capacitor Selection Use low ESR (equivalent series resistance) (