LM4982
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SNAS332B – FEBRUARY 2006 – REVISED APRIL 2013
LM4982 Boomer™ Audio Power Amplifier Series Ground-Referenced, Ultra Low Noise,
80mW Stereo Headphone Amplifier with IntelliSense and I2C Volume Control
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FEATURES
DESCRIPTION
•
•
•
•
•
The LM4982 is a ground referenced, variable gain
audio power amplifier capable of delivering 80mW of
continuous average power into a 16Ω single-ended
load with less than 1% THD+N from a 3V power
supply. The I2C volume control allows +18 to -76 dB
gain settings.
1
23
•
•
•
Ground Referenced Outputs
I2C Volume and Mode Controls
Available in Space-Saving DSBGA Package
Ultra Low Current Shutdown Mode
Advanced Pop & Click Circuitry Eliminates
Noises During Turn-On and Turn-Off
Transitions
1.6 – 4.0V Operation
No Output Coupling Capacitors, Snubber
Networks, Bootstrap Capacitors or GainSetting Resistors Required
Mono/Stereo Headphone Detect
APPLICATIONS
•
•
•
•
•
•
Notebook PCs
Desktop PCs
Mobile Phones
PDAs
Portable Electronic Devices
MP3 Players
KEY SPECIFICATIONS
•
•
•
Improved PSRR at 217Hz, 66dB
Stereo Output Power at VDD = 3V,
RL = 32Ω, THD+N = 1%, 51mW (Typ)
Shutdown Current, 0.1µA (Typ)
The LM4982 utilizes advanced charge pump
technology to generate the LM4982’s negative supply
voltage. This eliminates the need for output-coupling
capacitors typically used with single-ended loads.
IntelliSense is a new circuit technology that allows the
LM4982 to detect whether a mono or stereo
headphone plug has been inserted into the output
jack.
Boomer audio power amplifiers were designed
specifically to provide high quality output power with a
minimal amount of external components. The
LM4982 does not require output coupling capacitors
or bootstrap capacitors, and therefore is ideally suited
for mobile phone and other low voltage applications
where minimal power consumption is a primary
requirement.
The LM4982 incorporates selectable low-power
consumption shutdown and channel select modes.
The LM4982 contains advanced pop & click circuitry
that eliminates noises which would otherwise occur
during turn-on and turn-off transitions.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Boomer is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM4982
SNAS332B – FEBRUARY 2006 – REVISED APRIL 2013
www.ti.com
Typical Application
VDD
2
4.7 PF
I C
VDD
0.1 PF
PVDD
SVDD
SCL
2
I C
Control
Interface
Right In
+ IN_R
2
I C
BUS
SDA
0.39 PF
-
OUT_R
+
Headphone
Jack
Intellisense
Auto Stereo Mono
HPS
HP Enable
and
Left In
Click / Pop
+
IN_L
Suppression
0.39 PF
OUT_L
+
Charge
Pump
Ccp- Ccp+
2.2 PF
out
CPOUT
SVSS
PGND
GND
2.2 PF
Figure 1. Typical Audio Amplifier Application Circuit
2
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Connection Diagram
CCP-
CPOUT
I CVDD
SCL
SDA
HPS
IN
L
IN
R
SVDD
SGND
OUT
L
SVSS
OUT
R
A
B
C
D
4
CCP+
PGND
3
PVDD
2
1
2
Figure 2. DSBGA Package
Top View
PIN DESCRIPTIONS
Pin Designator
Pin Name
Pin Function
A1
SGND
Amplifier ground
A2
HPE
Headphone sende input
A3
PVDD
Charge pump / digital power supply
A4
CCP+
Charge pump fly capacitor positive side
B1
OUT_L
Left channel output
B2
IN_L
Left channel input
B3
I2C_VDD
I2C power supply
B4
PGND
Charge pump / digital ground
C1
SVSS
Amplifier negative supply
C2
IN_R
Right channel input
C3
SCL
I2C SCL line
C4
CCP-
Charge pump fly capacitor negative side
D1
OUT_R
Right channel output
D2
SVDD
Amplifier positive supply
D3
SDA
I2C SDA line
D4
CPOUT
Charge pump power output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1)
Supply Voltage
4.5V
−65°C to +150°C
Storage Temperature
−0.3V to VDD +0.3V
Input Voltage
Power Dissipation (2)
Internally Limited
(3)
2000V
ESD Susceptibility
ESD Susceptibility (4)
200V
Junction Temperature
150°C
θJA (typ) - (YZR0016)
Thermal Resistance
(1)
(2)
(3)
(4)
105°C/W (note X)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4982, see power derating currents for more information.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF - 240pF discharged through all pins.
Operating Ratings
TMIN ≤ TA ≤ TMAX
Temperature Range
−40°C ≤ TA ≤ +85°C
1.6V ≤ VDD ≤ 4.0V
Supply Voltage
Audio Amplifier Electrical Characteristics VDD = 3V (1) (2)
The following specifications apply for VDD = 3V, RL = 16Ω, AV = 0dB, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Quiescent Power Supply Current
Full Power Mode
IDD
Conditions
LM4982
Limits (4) (5)
VIN = 0V, inputs terminated,
both channels enabled
8.1
11.5
mA (max)
VIN = 0V, inputs terminated,
one channel enabled
5.1
7.3
mA
VIN = 0V, inputs terminated,
No headphone inserted
2.15
0.1
1.5
µA (max)
4.5
mV (max)
ISD
Shutdown Current
With SD enabled
VOS
Output Offset Voltage
RL = 32Ω
0.7
[B0:B4] = 00000
–70
[B0:B4] = 11111
+18
AV
Gain Max and Min settings
RIN
Input Resistance
POUT
(1)
(2)
(3)
(4)
(5)
4
Stereo Output Power
Units
(Limits)
Typical (3)
gain setting 18dB
22
gain setting –76dB
200
THD+N = 1% (max); f = 1kHz,
RL = 16Ω, per channel
47
THD+N = 1% (max); f = 1kHz,
RL = 32Ω, per channel
51
mA
dB
dB
15
29
kΩ (min)
kΩ (max)
40
mW (min)
kΩ
mW
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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Audio Amplifier Electrical Characteristics VDD = 3V(1)(2) (continued)
The following specifications apply for VDD = 3V, RL = 16Ω, AV = 0dB, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4982
Typical
THD+N
Total Harmonic Distortion +
Noise
PO = 50mW, f = 1kHz
RL = 16Ω, single channel
0.05
PO = 50mW, f = 1kHz
RL = 32Ω, single channel
0.025
(3)
Limits
(4) (5)
Units
(Limits)
%
VRIPPLE = 200mVP-P, input referred
PSRR
Power Supply Rejection Ratio
Full Power Mode
f = 217Hz
66
f = 1kHz
55
f = 20kHz
40
56
dB
SNR
Signal-to-Noise-Ratio
RL = 32Ω, POUT = 20mW,
f = 1kHz, BW = 20Hz to 22kHz
100
TWU
Wake Up Time From Shutdown
Charge Pump Wake-Up Time
300
μs
TWU
Wake Up Time
Headphone Sense Debounce Time
200
ms
XTALK
Crosstalk
RL = 16Ω, POUT = 1.6mW,
f = 1kHz, A-weighted filter
70
dB
ZOUT
Output Impedance
In Shutdown Mode
180
kΩ
IL
Input Leakage
Vih
HPS in threshold
0.9 x VDD [min]
Vil
HPS in threshold
0.7 x VDD [max]
V
3
9
Ω (min)
Ω (max)
RINT
dB
±0.1
Intellisense Threshold Resistance
nA
6
V
Control Interface Electrical Characteristics (1) (2)
The following specifications apply for 1.6V < VDD < 4.0V, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4982
Typical (3)
Limits (4) (5)
Units
(Limits)
t1
SCL period
2.5
μs (min)
t2
SDA Setup Time
100
ns (min)
t3
SDA Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
VIH
0.7 x I2CVDD
V (min)
VIL
0.3 x I2CVDD
V (max)
(1)
(2)
(3)
(4)
(5)
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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Typical Performance Characteristics
THD+N vs Frequency
VDD = 1.8V, RL = 16Ω,
PO = 7mW, Mono
10
5
5
2
1
2
1
0.5
0.5
THD+N (%)
THD+N (%)
10
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
.005
0.005
.002
0.002
.001
THD+N vs Frequency
VDD = 1.8V, RL = 16Ω,
PO = 2mW, Stereo
20
50 100 200 500 1k 2k
0.001
20
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4.
THD+N vs Frequency
VDD = 1.8V, RL = 32Ω,
PO = 7mW, Mono
THD+N vs Frequency
VDD = 1.8V, RL = 32Ω,
PO = 2mW, Stereo
10
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
.005
.005
.002
.002
.001
20
50 100 200 500 1k 2k
.001
20
5k 10k 20k
Figure 6.
THD+N vs Frequency
VDD = 3V, RL = 16Ω,
PO = 50mW, Mono
THD+N vs Frequency
VDD = 3V, RL = 16Ω,
PO = 25mW, Stereo
10
5
5
2
1
2
1
0.5
0.5
THD+N (%)
THD+N (%)
5k 10k 20k
Figure 5.
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
.005
.005
.002
.002
.001
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
.001
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 7.
6
50 100 200 500 1k 2k
FREQUENCY (Hz)
FREQUENCY (Hz)
10
5k 10k 20k
Figure 3.
THD+N (%)
THD+N (%)
10
50 100 200 500 1k 2k
Figure 8.
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Typical Performance Characteristics (continued)
THD+N vs Frequency
VDD = 3V, RL = 32Ω,
PO = 50mW, Mono
10
5
5
2
1
2
1
0.5
0.5
THD+N (%)
THD+N (%)
10
THD+N vs Frequency
VDD = 3V, RL = 32Ω,
PO = 25mW, Stereo
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
.005
.005
.002
.002
.001
.001
20
50 100 200 500 1k 2k
5k 10k 20k
20
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10.
THD+N vs Frequency
VDD = 3.6V, RL = 16Ω,
PO = 100mW, Mono
THD+N vs Frequency
VDD = 3.6V, RL = 16Ω,
PO = 60mW, Stereo
10
5
5
2
1
2
1
0.5
0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
.005
.005
.002
.002
.001
.001
20
50 100 200 500 1k 2k
20
5k 10k 20k
10
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11.
Figure 12.
THD+N vs Frequency
VDD = 3.6V, RL = 32Ω,
PO = 100mW, Mono,
THD+N vs Frequency
VDD = 3.6V, RL = 32Ω,
PO = 60mW, Stereo
10
5
5
2
1
2
1
0.5
THD+N (%)
0.5
THD+N (%)
5k 10k 20k
Figure 9.
THD+N (%)
THD+N (%)
10
50 100 200 500 1k 2k
0.2
0.1
0.05
0.2
0.1
0.05
0.02
0.01
0.02
.005
0.01
.002
.005
.001
.002
20
.001
20
50 100 200 500 1k 2k
5k 10k 20k
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 1.8V, RL = 16Ω,
f = 1kHz, Stereo
10
10
5
5
2
2
1
1
THD+N (%)
THD+N (%)
THD+N vs Output Power
VDD = 1.8V, RL = 16Ω,
f = 1kHz, Mono
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
0.01
5
0
10
15
20
0
25
5
Figure 16.
THD+N vs Output Power
VDD = 1.8V, RL = 32Ω,
f = 1kHz, Mono
THD+N vs Output Power
VDD = 1.8V, RL = 32Ω,
f = 1kHz, Stereo
10
5
5
2
2
THD+N (%)
THD+N (%)
25
1
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
0.01
0
5
10
15
20
5
0
25
OUTPUT POWER (mW)
10
15
20
25
OUTPUT POWER (mW)
Figure 17.
Figure 18.
THD+N vs Output Power
VDD = 3V, RL = 16Ω,
f = 1kHz, Mono
THD+N vs Output Power
VDD = 3V, RL = 16Ω,
f = 1kHz, Stereo
10
10
5
5
2
2
1
THD+N (%)
1
THD+N (%)
20
Figure 15.
1
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
0.01
0
25
50
75 100 125 150 175 200
0
25
50
75 100 125 150 175 200
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 19.
8
15
OUTPUT POWER (mW)
OUTPUT POWER (mW)
10
10
Figure 20.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 3V, RL = 32Ω,
f = 1kHz, Mono
10
5
5
2
2
1
1
THD+N (%)
THD+N (%)
10
THD+N vs Output Power
VDD = 3V, RL = 32Ω,
f = 1kHz, Stereo
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
0.01
0
25
50
75 100 125 150 175 200
0
25
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 22.
THD+N vs Output Power
VDD = 3.6V, RL = 16Ω,
f = 1kHz, Mono
THD+N vs Output Power
VDD = 3.6V, RL = 16Ω,
f = 1kHz, Stereo
10
5
5
2
2
1
1
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
0.01
0
25
50
75 100 125 150 175 200
0
25
OUTPUT POWER (mW)
50
75 100 125 150 175 200
OUTPUT POWER (mW)
Figure 23.
Figure 24.
THD+N vs Output Power
VDD = 3.6V, RL = 32Ω,
f = 1kHz, Mono
THD+N vs Output Power
VDD = 3.6V, RL = 32Ω,
f = 1kHz, Stereo
10
10
5
5
2
2
1
1
THD+N (%)
THD+N (%)
75 100 125 150 175 200
Figure 21.
THD+N (%)
THD+N (%)
10
50
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
0.01
0
25
50
75 100 125 150 175 200
OUTPUT POWER (mW)
0
25
50
75 100 125 150 175 200
OUTPUT POWER (mW)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
Power Dissipation vs Output Power
VDD = 1.8V, RL = 32Ω, f = 1kHz
70
60
60
50
50
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
Power Dissipation vs Output Power
VDD = 1.8V, RL = 16Ω, f = 1kHz
Stereo
40
30
Mono
20
10
0
0
5
10
15
25
20
40
Stereo
30
20
Mono
10
0
30
0
5
15
25
20
30
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 27.
Figure 28.
vs Output Power
VDD = 3V, RL = 16Ω, f = 1kHz
Power Dissipation vs Output Power
VDD = 3V, RL = 32Ω, f = 1kHz
300
250
250
200
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
10
Stereo
150
100
Mono
50
200
150
Stereo
100
50
Mono
0
0
20
40
60
80
100 120
0
140
0
80
100 120
140
Figure 29.
Figure 30.
Power Dissipation vs Output Power
VDD = 3.6V, RL = 16Ω, f = 1kHz
Power Dissipation vs Output Power
VDD = 3.6V, RL = 32Ω, f = 1kHz
350
500
POWER DISSIPATION (mW)
450
POWER DISSIPATION (mW)
60
40
OUTPUT POWER (mW)
OUTPUT POWER (mW)
400
350
300
Stereo
250
200
150
100
Mono
50
0
0
50
100
150
200
250
300
250
200
Stereo
150
100
Mono
50
0
0
50
100
150
200
250
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 31.
10
20
Figure 32.
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Typical Performance Characteristics (continued)
Output Power vs Power Supply Voltage
RL = 16Ω, f = 1kHz, Mono
Output Power vs Power Supply Voltage
RL = 16Ω, f = 1kHz, Stereo
160
300
140
OUTPUT POWER (mW)
OUTPUT POWER (mW)
250
THD+N = 10%
200
150
100
THD+N = 1%
120
THD+N = 10%
100
80
60
40
THD+N = 1%
50
20
0
0
0
1
2
4
3
5
0
POWER SUPPLY VOLTAGE (V)
1
2
4
3
5
POWER SUPPLY VOLTAGE (V)
Figure 33.
Figure 34.
Output Power vs Power Supply Voltage
RL = 32Ω, f = 1kHz, Mono
Output Power vs Power Supply Voltage
RL = 32Ω, f = 1kHz, Stereo
250
180
160
THD+N = 10%
OUTPUT POWER (mW)
OUTPUT POWER (mW)
200
150
100
THD+N = 1%
50
140
120
THD+N = 10%
100
80
60
40
THD+N = 1%
20
0
0
0
1
2
4
3
5
0
POWER SUPPLY VOLTAGE (V)
1
2
4
3
5
POWER SUPPLY VOLTAGE (V)
Figure 35.
Figure 36.
Power Supply Current vs Power Supply Voltage
VIN = 0V, Mono
Power Supply Current vs Power Supply Voltage
VIN = 0V, Stereo
12
POWER SUPPLY CURRENT (mA)
POWER SUPPLY CURRENT (mA)
12
10
8
6
4
2
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
POWER SUPPLY VOLTAGE (V)
10
8
6
4
2
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
POWER SUPPLY VOLTAGE (V)
Figure 37.
Figure 38.
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0
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
Typical Performance Characteristics (continued)
PSRR vs Frequency
VDD = 1.8V, Vripple = 200mVp-p
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
PSRR vs Frequency
VDD = 3V, Vripple = 200mVp-p
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
50 100 200 500 1k 2k
20
5k 10k 20k
FREQUENCY (Hz)
Figure 39.
Figure 40.
PSRR vs Frequency
VDD = 3.6V, Vripple = 200mVp-p
Crosstalk
VDD = 3V, RL = 16Ω, PO= 50mW
0
-10
-10
CHANNEL SEPERATION (dB)
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (Hz)
0
5k 10k 20k
-20
-30
-40
-50
-60
-70
-80
-20
-30
-40
-50
-60
-70
-80
-90
-90
-100
-100
20
50 100 200 500 1k 2k
5k 10k 20k
20
FREQUENCY (Hz)
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 41.
Figure 42.
Crosstalk
VDD = 3V, RL = 32Ω, PO= 50mW
0
CHANNEL SEPERATION (dB)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 43.
12
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APPLICATION INFORMATION
Figure 44. I2C Bus Format
Figure 45. I2C Timing Diagram
Table 1. Chip Address
Chip Address
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
1
0
0
Table 2. Control Registers
D7
D6
D5
D4
D3
D2
D1
D0
Mode Control
0
0
Volume Control
1
0
0
0
CD3
CD2
CD1
CD0
0
VD4
VD3
VD2
VD1
VD0
Table 3. Mode Control
CD3
CD2
CD1
CD0
1
Intellisense Enabled
0
Intellisense Disabled
1
Mute Enabled
0
Mute Disabled
1
Stereo
0
Mono *
1
Normal Operation
0
Shutdown Enabled
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I2C VOLUME CONTROL
The LM4982 can be configured in 32 different gain steps by forcing I2C volume control bits to a desired gain
according to the table below:
Table 4. Volume Control
VD4
VD3
VD2
VD1
VD0
Gain (dB)
0
0
0
0
0
–70
0
0
0
0
1
–60
0
0
0
1
0
–52
0
0
0
1
1
–44
0
0
1
0
0
–38
0
0
1
0
1
–34
0
0
1
1
0
–30
0
0
1
1
1
–27
0
1
0
0
0
–24
0
1
0
0
1
–21
0
1
0
1
0
–18
0
1
0
1
1
–16
0
1
1
0
0
–14
0
1
1
0
1
–12
0
1
1
1
0
–10
0
1
1
1
1
–8
1
0
0
0
0
–6
1
0
0
0
1
–4
1
0
0
1
0
–2
1
0
0
1
1
0
1
0
1
0
0
2
1
0
1
0
1
4
1
0
1
1
0
6
1
0
1
1
1
8
1
1
0
0
0
10
1
1
0
0
1
12
1
1
0
1
0
13
1
1
0
1
1
14
1
1
1
0
0
15
1
1
1
0
1
16
1
1
1
1
0
17
1
1
1
1
1
18
HP SENSE FUNCTION
Connecting headphones to the headphone jack disconnects the headphone jack contact pin from OUT_L and
allows Rpu to pull the HP Sense pin up to VDD. This enables the device. A microprocessor or a switch can
replace the headphone jack contact pin.
Shutdown
(Bit CD0)
14
HPS pin
Operational Mode
Logic High
Logic Low
Standby Mode
Logic High
Logic High
Full Power Mode
Logic Low
Logic Low
Micro-Power Shutdown
Logic Low
Logic High
Micro-Power Shutdown
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VDD
Rpu
200 k:
Headphone
Jack
HPS
OUT_L
+
Rpd
178 k:
INTELLISENSE
Texas Instruments' Intellisense technology allows the LM4982 to detect whether a mono or stereo headphone
has been insterted in to the headphone jack. If a mono headphone is inserted into a device that is designed for a
stereo headphone, one of the amplifiers will be shorted to ground. Without Intellisense, this may damage the
device or, best case, the device will draw excessive current, shortening battery life.
Intellisense works by first waiting for one of the following events:
• When the device powers up, if a headphone is already inserted
• When a headphone is inserted, if the device is already powered up
• After the thermal shutdown circuitry is activated.
The occurrence of one of these events triggers the Intellisense circuitry to apply a small voltage on both left and
right outputs and sense the resulting current through the load. If the load connected to the amplifier is greater
than 9Ω, the amplifier driving it will be in full power mode. If the load is less than 3Ω, the LM4982 will assume a
short to ground and shutdown the driving amplifier. Intellisense puts the LM4982 in mono mode when the right
channel is shorted. For extra protection both amplifiers will be shutdown when the left channel is shorted to
ground. The Intellisense feature can be enabled and disabled through an I2C command.
This Intellisense feature is designed for headphones with a nominal impedance of 16Ω or greater, using lower
impedance loads may cause this feature to operate incorrectly.
Un-Defined
Region
Short
Assumed
3:
Load
Assumed
9:
Rload
MONO/STEREO OPERATION
When Intellisense is disabled the value of the CD1 bit of the mode control determines if the LM4982 is in mono
or stereo mode. When the LM4982 is in mono mode the left and right input signals are mixed to the left channel
amplifier and attenuated by -6dB. The right channel amplifier is put in shutdown to save power. The mixing
function allows full reproduction of a stereo input signal in a mono headphone and optimum headroom is kept by
attenuating by a factor of two.
I2C COMPATIBLE INTERFACE
The LM4982 uses a serial bus, which conforms to the I2C protocol, to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4982.
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The bus format for the I2C interface is shown in Figure 44. The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert
all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM4982 has received the address correctly, then it
holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse,
then the master should abort the rest of the data transfer to the LM4982.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable high.
After the data byte is sent, the master must check for another acknowledge to see if the LM4982 received the
data.
If the master has more data bytes to send to the LM4982, then the master can repeat the previous two steps
until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The
data line should be held high when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM4982's I2C interface is powered up through the I2CVDD pin. The LM4982's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected
between the LM4982's supply pins and ground. Keep the length of leads and traces that connect capacitors
between the LM4982's power supply pins and ground as short as possible.
ELIMINATING THE OUTPUT COUPLING CAPACITOR
The LM4982 features a low noise inverting charge pump that generates an internal negative supply voltage. This
allows the outputs of the LM4982 to be biased about GND instead of a nominal DC voltage, like traditional
headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220µF)
are not necessary. The coupling capacitors are replaced by two, small ceramic charge pump capacitors, saving
board space and cost.
Eliminating the output coupling capacitors also improves low frequency response. In traditional headphone
amplifiers, the headphone impedance and the output capacitor form a high pass filter that not only blocks the DC
component of the output, but also attenuates low frequencies, impacting the bass response. Because the
LM4982 does not require the output coupling capacitors, the low frequency response of the device is not
degraded by external components.
In addition to eliminating the output coupling capacitors, the ground referenced output nearly doubles the
available dynamic range of the LM4982 when compared to a traditional headphone amplifier operating from the
same supply voltage.
OUTPUT TRANSIENT ('CLICK AND POPS') ELIMINATED
The LM4982 contains advanced circuitry that virtually eliminates output transients ('clicks and pops'). This
circuitry prevents all traces of transients when the supply voltage is first applied or when the part resumes
operation after coming out of shutdown mode.
16
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POWER DISSIPATION
Power dissipation is a major concern when using any power amplifier and must be thoroughly understood to
ensure a successful design. Equation 1 states the maximum power dissipation point for a single-ended amplifier
operating at a given supply voltage and driving a specified output load.
PDMAX = (2VDD) 2 / (2π2RL)
(1)
Since the LM4982 has two operational amplifiers in one package, the maximum internal power dissipation point
is twice that of the number which results from Equation 1. Even with large internal power dissipation, the LM4982
does not require heat sinking over a large range of ambient temperatures. The maximum power dissipation point
obtained must not be greater than the power dissipation that results from Equation 2:
PDMAX = (TJMAX - TA) / (θJA)
(2)
For the DSBGA package, θJA = 105°C/W. TJMAX = 150°C for the LM4982. Depending on the ambient
temperature, TA, of the system surroundings, Equation 2 can be used to find the maximum internal power
dissipation supported by the IC packaging. If the result of Equation 1 is greater than that of Equation 2, then
either the supply voltage must be decreased, the load impedance increased or TA reduced. Power dissipation is
a function of output power and thus, if typical operation is not around the maximum power dissipation point, the
ambient temperature may be increased accordingly.
SELECTING PROPER EXTERNAL COMPONENTS
Optimizing the LM4982's performance requires properly selecting external components. Though the LM4982
operates well when using external components with wide tolerances, best performance is achieved by optimizing
component values.
Charge Pump Capacitor Selection
Use low ESR (equivalent series resistance) (
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