LM5002
SNVS496F – JANUARY 2007 – REVISED LM5002
MAY 2021
SNVS496F – JANUARY 2007 – REVISED MAY 2021
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LM5002 Wide Input Voltage Switch Mode Regulator
1 Features
3 Description
•
•
The LM5002 high voltage switch mode regulator
features all of the functions necessary to implement
efficient high voltage boost, flyback, SEPIC and
forward converters, using few external components.
This easy to use regulator integrates a 75-V
N-Channel MOSFET with a 0.5-A peak current limit.
Current mode control provides inherently simple
loop compensation and line-voltage feed-forward for
superior rejection of input transients. The switching
frequency is set with a single resistor and is
programmable up to 1.5 MHz. The oscillator can
also be synchronized to an external clock. Additional
protection features include: current limit, thermal
shutdown, undervoltage lockout and remote shutdown
capability. The device is available in both 8-pin SOIC
and 8-pin WSON packages. To create a custom
regulator design, use the LM5002 with WEBENCH®
Power Designer.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated 75-V N-channel MOSFET
Ultra-wide input voltage range from 3.1 V to
75 V
Integrated high voltage bias regulator
Adjustable output voltage
1.5% output voltage accuracy
Current mode control with selectable
compensation
Wide bandwidth error amplifier
Integrated current sensing and limiting
Integrated slope compensation
85% maximum duty cycle limit
Single resistor oscillator programming
Oscillator synchronization capability
Enable and undervoltage lockout (UVLO) pin
8-pin SOIC package
8-pin WSON package
Thermal shutdown with hysteresis
2 Applications
•
•
Device Information
DC-DC power supplies for industrial,
communications, and automotive applications
Boost, flyback, SEPIC, and forward converter
topologies
PART NUMBER
LM5002
(1)
PACKAGE(1)
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
WSON (8)
4.00 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................12
8 Application and Implementation.................................. 13
8.1 Application Information............................................. 13
8.2 Typical Applications.................................................. 15
9 Power Supply Recommendations................................25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Receiving Notification of Documentation Updates.. 27
11.2 Support Resources................................................. 27
11.3 Trademarks............................................................. 27
11.4 Electrostatic Discharge Caution.............................. 27
11.5 Glossary.................................................................. 27
12 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (December 2016) to Revision F (May 2021)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document. .................1
• Changed LM5005 to LM5002............................................................................................................................. 1
Changes from Revision D (March 2013) to Revision E (December 2016)
Page
• Added Applications section, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section............ 1
• Changed Junction to Ambient, RθJA, values in Thermal Information table From: 140 To: 105.7 (SOIC) and
From: 40 To: 37.1 (WSON)................................................................................................................................. 4
• Changed Junction to Case, θJC, values in Thermal Information table From: 32 To: 50.8 (SOIC) and From: 4.5
To: 25.8 (WSON)................................................................................................................................................ 4
Changes from Revision C (March 2013) to Revision D (March 2013)
Page
• Changed layout of National Semiconductor Data Sheet to TI format................................................................. 1
2
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5 Pin Configuration and Functions
SW
1
8
EN
VIN
2
7
COMP
VCC
3
6
FB
GND
4
5
RT
COMP
1
EN
2
8
FB
7
RT
EP
SW
3
6
GND
VIN
4
5
VCC
Not to scale
Figure 5-1. D Package 8-Pin SOIC Top View
Not to scale
Figure 5-2. NGT Package 8-Pin WSON Top View
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
SOIC
WSON
COMP
7
1
O
Open-drain output of the internal error amplifier: the loop compensation network must be
connected between the COMP pin and the FB pin. COMP pullup is provided by an internal
5-kΩ resistor which can be used to bias an opto-coupler transistor (while FB is grounded) for
isolated ground applications.
EN
8
2
I
Enable and undervoltage lockout or shutdown input: an external voltage divider can be used
to set the line undervoltage lockout threshold. If the EN pin is left unconnected, a 6-µA pullup
current source pulls the EN pin high to enable the regulator.
EP
—
EP
—
FB
6
8
I
Feedback input from the regulated output voltage: this pin is connected to the inverting input
of the internal error amplifier. The 1.26-V reference is internally connected to the non-inverting
input of the error amplifier.
GND
4
6
G
Ground: internal reference for the regulator control functions and the power MOSFET current
sense resistor connection.
I
Oscillator frequency programming and optional synchronization pulse input: the internal
oscillator is set with a resistor, between this pin and the GND pin. The recommended frequency
range is 50 KHz to 1.5 MHz. The RT pin can accept synchronization pulses from an external
clock. A 100-pF capacitor is recommended for coupling the synchronizing clock to the RT pin.
Exposed pad (WSON only): exposed metal pad on the underside of the package with a
resistive connection to pin 6. It is recommended to connect this pad to the PCB ground plane to
improve heat dissipation.
RT
5
7
SW
1
3
I
Switch pin: the drain terminal of the internal power MOSFET
VIN
2
4
P
Input supply pin: nominal operating range is 3.1 V to 75 V.
VCC
3
5
P
Bias regulator output, or input for external bias supply: VCC tracks VIN up to 6.9 V. Above
VIN = 6.9 V, VCC is regulated to 6.9 V. A 0.47-µF or greater ceramic decoupling capacitor is
required. An external voltage (7 V to 12 V) can be applied to this pin which disables the internal
VCC regulator to reduce internal power dissipation and improve converter efficiency.
(1)
G = Ground, I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VIN to GND
SW to GND (steady state)
–0.3
VCC, EN to GND
COMP, FB, RT to GND
–0.3
Maximum junction temperature, TJ-MAX
Storage temperature, Tstg
(1)
–65
MAX
UNIT
76
V
76
V
14
V
7
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN
3.1
75
V
Operating junction temperature
–40
125
°C
6.4 Thermal Information
LM5002
THERMAL METRIC(1)
NGT (WSON)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
105.7
37.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50.8
25.8
°C/W
RθJB
Junction-to-board thermal resistance
46.1
14.2
°C/W
ψJT
Junction-to-top characterization parameter
8.2
0.2
°C/W
ψJB
Junction-to-board characterization parameter
45.6
14.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
3.8
°C/W
(1)
4
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Typical values at TJ = 25°C, minimum and maximum values at TJ = –40°C to 125°C, VVIN = 10 V, and RRT = 48.7 kΩ (unless
otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7.15
UNIT
STARTUP REGULATOR
VVCC-REG
VCC regulator output
6.55
6.85
VCC current limit
VVCC = 6 V
15
20
VCC UVLO threshold
VVCC increasing
2.6
2.8
VCC undervoltage hysteresis
V
mA
3
0.1
V
V
IIN
Bias current
VFB = 1.5 V
3.1
4.5
mA
IQ
Shutdown current (IIN)
VEN = 0 V
95
130
µA
0.65
V
1.32
V
EN THRESHOLDS
EN shutdown threshold
VEN increasing
0.25
0.45
VEN increasing
1.2
1.26
EN shutdown hysteresis
EN standby threshold
0.1
EN standby hysteresis
EN current source
V
0.1
V
6
µA
MOSFET CHARACTERISTICS
MOSFET RDS(ON) plus
current sense resistance
ID = 0.25 A
850
1600
mΩ
MOSFET leakage current
VSW = 75 V
0.05
5
µA
MOSFET gate charge
VVCC = 6.9 V
2.4
nC
CURRENT LIMIT
ILIM
Cycle by cycle current limit
0.4
Cycle by cycle current limit delay
0.5
0.6
A
100
200
ns
OSCILLATOR
FSW1
Frequency1
RRT = 48.7 kΩ
225
260
295
KHz
FSW2
Frequency2
RRT = 15.8 kΩ
660
780
900
KHz
VRT-SYNC
SYNC threshold
2.2
2.6
3.2
SYNC pulse width minimum
VRT > VRT-SYNC + 0.5 V
15
V
ns
PWM COMPARATOR
Maximum duty cycle
VCOMP-OS
80%
85%
90%
Minimum ON-time
VCOMP > VCOMP-OS
25
ns
Minimum ON-time
VCOMP < VCOMP-OS
0
ns
COMP to PWM comparator offset
0.9
1.3
1.55
1.241
1.26
1.279
V
ERROR AMPLIFIER
VFB-REF
Feedback reference voltage
Internal reference and VFB = VCOMP
FB bias current
10
DC gain
COMP sink current
V
nA
72
dB
VCOMP = 250 mV
2.5
COMP short circuit current
VFB = 0 V and VCOMP = 0 V
0.9
1.2
1.5
mA
COMP open circuit voltage
VFB = 0 V
4.8
5.5
6.2
V
COMP to SW delay
Unity gain bandwidth
mA
42
ns
3
MHz
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
165
°C
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Typical values at TJ = 25°C, minimum and maximum values at TJ = –40°C to 125°C, VVIN = 10 V, and RRT = 48.7 kΩ (unless
otherwise noted)(1)
PARAMETER
TEST CONDITIONS
Thermal shutdown hysteresis
(1)
6
MIN
TYP
20
MAX
UNIT
°C
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).
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6.6 Typical Characteristics
Figure 6-1. Efficiency, Boost Converter
Figure 6-2. VFB vs Temperature
Figure 6-3. IQ (Non-Switching) vs VIN
Figure 6-4. VCC vs VIN
Figure 6-5. RDS(ON) vs VCC
Figure 6-6. RDS(ON) vs Temperature
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8
Figure 6-7. ILIM vs VCC
Figure 6-8. ILIM vs VCC vs Temperature
Figure 6-9. FSW vs RRT
Figure 6-10. FSW vs Temperature
Figure 6-11. FSW vs VCC
Figure 6-12. IEN vs VVIN vs Temperature
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7 Detailed Description
7.1 Overview
The LM5002 high-voltage switching regulator features all the functions necessary to implement an efficient
boost, flyback, SEPIC or forward current-mode power converter. The operation can be best understood by
referring to the block diagram. At the start of each cycle, the oscillator sets the driver logic and turns on the
power MOSFET to conduct current through the inductor or transformer. The peak current in the MOSFET is
controlled by the voltage at the COMP pin. The COMP voltage increases with larger loads and decrease with
smaller loads. This voltage is compared with the sum of a voltage proportional to the power MOSFET current
and an internally generated slope compensation ramp. Slope compensation is used in current mode PWM
architectures to eliminate subharmonic current oscillation that occurs with static duty cycles greater than 50%.
When the summed signal exceeds the COMP voltage, the PWM comparator resets the driver logic, turning off
the power MOSFET. The driver logic is then set by the oscillator at the end of the switching cycle to initiate the
next power period.
The LM5002 has dedicated protection circuitry to protect the IC from abnormal operating conditions. Cycle-bycycle current limiting prevents the power MOSFET current from exceeding 0.5A. This feature can also be used
to soft start the regulator. Thermal shutdown circuitry holds the driver logic in reset when the die temperature
reaches 165°C, and returns to normal operation when the die temperature drops by approximately 20°C. The EN
pin can be used as an input voltage undervoltage lockout (UVLO) during start-up to prevent operation with less
than the minimum desired input voltage.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 High Voltage VCC Regulator
The LM5002 VCC low dropout (LDO) regulator allows the LM5002 to operate at the lowest possible input
voltage. The VCC pin voltage is very nearly equal to the input voltage from 2.8 V up to approximately 6.9 V.
As the input voltage continues to increase, the VCC voltage is regulated at the 6.9 V set-point. The total input
operating range of the VCC LDO regulator is 3.1 V to 75 V.
The output of the VCC regulator is current limited to 20 mA. During power-up, the VCC regulator supplies current
into the required decoupling capacitor (0.47 µF or greater ceramic capacitor) at the VCC pin. When the VCC
voltage exceeds the VCC UVLO threshold of 2.8 V and the EN pin is greater than 1.26 V the PWM controller
is enabled and switching begins. The controller remains enabled until VCC falls below 2.7 V or the EN pin falls
below 1.16 V.
An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary
voltage is greater than 6.9 V, the internal regulator essentially shuts-off, and internal power dissipation is
decreased by the VIN voltage times the operating current. The overall converter efficiency also improves if the
VIN voltage is much higher than the auxiliary voltage. Do not exceed 14 V with an externally applied VCC
voltage. The VCC regulator series pass MOSFET includes a body diode (see Section 7.2) between VCC and
VIN that must not be forward biased in normal operation. Therefore, the auxiliary VCC voltage must never
exceed the VIN voltage.
In high voltage applications take extra care to ensure the VIN pin does not exceed the absolute maximum
voltage rating of 76 V. Voltage ringing on the VIN line during line transients that exceeds the Absolute Maximum
Ratings can damage the IC. Both careful PCB layout and the use of quality bypass capacitors placed close to
the VIN and GND pins are essential.
7.3.2 Oscillator
A single external resistor connected between RT and GND pins sets the LM5002 oscillator frequency. To set a
desired oscillator frequency (FSW), the necessary value for the RT resistor can be calculated with Equation 1.
9
RT = 13.1 x 10 x
1
- 83 ns
FSW
(1)
The tolerance of the external resistor and the frequency tolerance indicated in the Section 6.5 must be taken into
account when determining the worst case frequency range.
7.3.3 External Synchronization
The LM5002 can be synchronized to the rising edge of an external clock. The external clock must have a higher
frequency than the free running oscillator frequency set by the RT resistor. The clock signal must be coupled
through a 100-pF capacitor into the RT pin. A peak voltage level greater than 2.6 V at the RT pin is required for
detection of the sync pulse. The DC voltage across the RT resistor is internally regulated at 1.5 V. The negative
portion of the AC voltage of the synchronizing clock is clamped to this 1.5 V by an amplifier inside the LM5002
with approximately 100-Ω output impedance. Therefore, the AC pulse superimposed on the RT resistor must
have positive pulse amplitude of 1.1 V or greater to successfully synchronize the oscillator. The sync pulse width
measured at the RT pin must have a duration greater than 15 ns and less than 5% of the switching period. The
sync pulse rising edge initiates the internal CLK signal rising edge, which turns off the power MOSFET. The
RT resistor is always required, whether the oscillator is free running or externally synchronized. Place the RT
resistor very close to the device and connected directly to the RT and GND pins of the LM5002.
7.3.4 Enable and Standby
The LM5002 contains a dual level Enable circuit. When the EN pin voltage is below 450 mV, the IC is in a low
current shutdown mode with the VCC LDO disabled. When the EN pin voltage is raised above the shutdown
threshold but below the 1.26-V standby threshold, the VCC LDO regulator is enabled, while the remainder of the
IC is disabled. When the EN pin voltage is raised above the 1.26-V standby threshold, all functions are enabled
10
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and normal operation begins. An internal 6-µA current source pulls up the EN pin to activate the IC when the EN
pin is left disconnected.
7.3.5 Error Amplifier and PWM Comparator
An internal high-gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision reference. The output of the error amplifier is connected
to the COMP pin allowing the user to add loop compensation, typically a Type-II network, as illustrated in Figure
7-1. This network creates a low-frequency pole that rolls off the high DC gain of the amplifier, which is necessary
to accurately regulate the output voltage. FDC_POLE is the closed-loop unity gain (0 dB) frequency of this pole.
A zero provides phase boost near the closed-loop unity gain frequency, and a high-frequency pole attenuates
switching noise. The PWM comparator compares the current sense signal from the current sense amplifier to the
error amplifier output voltage at the COMP pin.
Figure 7-1. Type II Compensator
When isolation between primary and secondary circuits is required, the Error Amplifier is usually disabled by
connecting the FB pin to GND. This allows the COMP pin to be driven directly by the collector of an opto-coupler.
In isolated designs the external error amplifier is placed on the secondary circuit and drives the opto-coupler
LED. The compensation network is connected to the secondary side error amplifier. An example of an isolated
regulator with an opto-coupler is shown in Figure 8-6.
7.3.6 Current Amplifier and Slope Compensation
The LM5002 employs peak current-mode control that also provides a cycle-by-cycle overcurrent protection
feature. An internal 100-mΩ current sense resistor measures the current in the power MOSFET source. The
sense resistor voltage is amplified 30 times to provide a 3 V/A signal into the current limit comparator. Current
limiting is initiated if the internal current limit comparator input exceeds the 1.5-V threshold, corresponding to
0.5 A. When the current limit comparator is triggered, the SW output pin immediately switches to a high
impedance state.
The current sense signal is reduced to a scale factor of 2.1 V/A for the PWM comparator signal. The signal
is then summed with a 450-mV peak slope compensation ramp. The combined signal provides the PWM
comparator with a control signal that reaches 1.5 V when the MOSFET current is 0.5 A. For duty cycles greater
than 50%, current mode control circuits are subject to subharmonic oscillation (alternating between short and
long PWM pulses every other cycle). Adding a fixed slope voltage ramp signal (slope compensation) to the
current sense signal prevents this oscillation. The 450-mV ramp (zero volts when the power MOSFET turns
on, and 450 mV at the end of the PWM clock cycle) adds a fixed slope to the current sense ramp to prevent
oscillation.
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To prevent erratic operation at low duty cycle, a leading edge blanking circuit attenuates the current sense signal
when the power MOSFET is turned on. When the MOSFET is initially turned on, current spikes from the power
MOSFET drain-source and gate-source capacitances flow through the current sense resistor. These transient
currents normally cease within 50 ns with proper selection of rectifier diodes and proper PCB layout.
7.3.7 Power MOSFET
The LM5002 switching regulator includes an N-Channel MOSFET with 850-mΩ ON-resistance. The ONresistance of the LM5002 MOSFET varies with temperature as shown in Section 6.6. The typical total gate
charge for the MOSFET is 2.4 nC which is supplied from the VCC pin when the MOSFET is turned on.
7.4 Device Functional Modes
7.4.1 Thermal Protection
Internal thermal shutdown circuitry is provided to protect the IC in the event the maximum junction temperature
is exceeded. When the 165°C junction temperature threshold is reached, the regulator is forced into a low power
standby state, disabling all functions except the VCC regulator. Thermal hysteresis allows the IC to cool down
before it is re-enabled. Note that because the VCC regulator remains functional during this period, the soft-start
circuit shown in Figure 8-4 must be augmented if soft start from thermal shutdown state is required.
12
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The following information is intended to provide guidelines for the power supply designer using the LM5002.
8.1.1 VIN
The voltage applied to the VIN pin can vary within the range of 3.1 V to 75 V. The current into the VIN pin
depends primarily on the gate charge of the power MOSFET, the switching frequency, and any external load on
the VCC pin. It is recommended to use the filter shown in Figure 8-1 to suppress transients that may occur at
the input supply. This is particularly important when VIN is operated close to the maximum operating rating of the
LM5002.
When power is applied and the VIN voltage exceeds 2.8 V with the EN pin voltage greater than 0.45 V, the
VCC regulator is enabled, supplying current into the external capacitor connected to the VCC pin. When the
VIN voltage is between 2.8 V and 6.9 V, the VCC voltage is approximately equal to the VIN voltage. When the
voltage on the VCC pin exceeds 6.9 V, the VCC pin voltage is regulated at 6.9 V. In typical flyback applications,
an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the
VCC voltage above 6.9 V to shut off the internal start-up regulator. The current requirements from this winding
are relatively small, typically less than 20 mA. If the VIN voltage is much higher than the auxiliary voltage, the
auxiliary winding significantly improves the conversion efficiency. It also reduces the power dissipation within the
LM5002. The externally applied VCC voltage must never exceed 14 V. Also the applied VCC must never exceed
the VIN voltage to avoid reverse current through the internal VCC to VIN diode shown in the LM5002 Section
7.2.
Figure 8-1. Input Transient Protection
8.1.2 SW PIN
Attention must be given to the PCB layout for the SW pin that connects to the power MOSFET drain. Energy can
be stored in parasitic inductance and capacitance that causes switching spikes that negatively affect efficiency,
and conducted and radiated emissions. These connections must be as short as possible to reduce inductance
and as wide as possible to reduce resistance. The loop area, defined by the SW and GND pin connections, the
transformer or inductor terminals, and their respective return paths, must be minimized.
8.1.3 EN or UVLO Voltage Divider Selection
An external setpoint resistor divider from VIN to GND can be used to determine the minimum operating input
range of the regulator. The divider must be designed such that the EN pin exceeds the 1.26-V standby threshold
when VIN is in the desired operating range. The internal 6-µA current source must be included when determining
the resistor values. The shutdown and standby thresholds have 100-mV hysteresis to prevent noise from
toggling between modes. When the VIN voltage is below 3.5 VDC during start-up and the operating temperature
is below –20°C, the EN pin must have a pullup resistor that provides 2 µA or greater current. The EN pin is
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internally protected by a 6-V Zener diode through a 1-kΩ resistor. The enabling voltage may exceed the Zener
voltage, however the Zener current must be limited to less than 4 mA.
Two dedicated comparators connected to the EN pin are used to detect undervoltage and shutdown conditions.
When the EN pin voltage is below 0.45 V, the controller is in a low-current shutdown mode where the VIN current
is reduced to 95 µA. For an EN pin voltage greater than 0.45 V but less than 1.26 V, the controller is in standby
mode, with all internal circuits operational, but the PWM gate driver signal is blocked. Once the EN pin voltage is
greater than 1.26 V, the controller is fully enabled. Two external resistors can be used to program the minimum
operational voltage for the power converter as shown in Figure 8-2. When the EN pin voltage falls below the
1.26 V threshold, an internal 100 mV threshold hysteresis prevents noise from toggling the state, so the voltage
must be reduced to 1.16 V to transition to standby. Resistance values for R1 and R2 can be determined from
Equation 2 and Equation 3.
VPWR - 1.26V
R1 =
R2 =
IDIVIDER
(2)
1.26V
IDIVIDER + 6 PA
(3)
where:
•
•
VPWR is the desired turnon voltage
IDIVIDER is an arbitrary current through R1 and R2
For example, if the LM5002 is to be enabled when VPWR reaches 16 V, IDIVIDER could be chosen as 501 µA that
sets R1 to 29.4 kΩ and R2 to 2.49 kΩ. The voltage at the EN pin must not exceed 10 V unless the current into
the 6 V protection Zener diode is limited below 4 mA. The EN pin voltage must not exceed 14 V at any time. Be
sure to check both the power and voltage rating (some 0603 resistors are rated as low as 50 V) for the selected
R1 resistor.
Figure 8-2. Basic EN (UVLO) Configuration
Remote configuration of the LM5002's operational modes can be accomplished with open drain device(s)
connected to the EN pin as shown in Figure 8-3. A MOSFET or an NPN transistor connected to the EN pin can
force the regulator into the low power off state. Adding a PN diode in the drain (or collector) provides the offset to
achieve the standby state. The advantage of standby is that the VCC LDO is not disabled and external circuitry
powered by VCC remains functional.
14
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Figure 8-3. Remote Standby and Disable Control
8.1.4 Soft Start
Soft start (SS) can be implemented with an external capacitor connected to COMP through a diode as shown in
Figure 8-4. The COMP discharge MOSFET conducts during Shutdown and Standby modes to keep the COMP
voltage below the PWM offset (1.3 V), which inhibits PWM pulses. The error amplifier attempts to raise the
COMP voltage after the EN pin exceeds the 1.26 V standby threshold. Because the error amplifier output can
only sink current, the internal COMP pullup resistor (approximately 5 kΩ) supplies the charging current to the SS
capacitor. The SS capacitor causes the COMP voltage to gradually increase until the output voltage achieves
regulation and FB assumes control of the COMP and the PWM duty cycle. The SS capacitor continues charging
through a large resistance, RSS, preventing the SS circuit from interfering with the normal error amplifier function.
During shutdown, the VCC diode discharges the SS capacitor.
Figure 8-4. Soft-Start Circuit
8.2 Typical Applications
Figure 8-5, Figure 8-6, Figure 8-7, and Figure 8-8 present examples of a non-isolated flyback, isolated flyback,
boost, 24-V SEPIC, and a 12-V automotive range SEPIC converters utilizing the LM5002 switching regulator.
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8.2.1 Non-Isolated Flyback Regulator
Figure 8-5. Non-Isolated Flyback Schematic
8.2.1.1 Design Requirements
The non-isolated flyback converter shown in Figure 8-5 uses the internal voltage reference for the regulation
setpoint. The output is 5 V at 500 mA while the input voltage can vary from 16 V to 42 V. The switching
frequency is set to 250 kHz. An auxiliary winding on transformer (T1) provides 7.5 V to power the LM5002 when
the output is in regulation. This disables the internal high-voltage VCC LDO regulator and improves efficiency.
The input undervoltage threshold is 13.9 V. The converter can be shut down by driving the EN input below
1.26 V with an open-collector or open-drain transistor. An external synchronizing frequency can be applied to
the SYNC input. An optional soft-start circuit is connected to the COMP pin input. When power is applied, the
soft-start capacitor (C7) is discharged and limits the voltage applied to the PWM comparator by the internal error
amplifier. The internal approximate 5-kΩ COMP pullup resistor charges the soft-start capacitor until regulation
is achieved. The VCC pullup resistor (R7) continues to charge C7 so that the soft-start circuit does not affect
the compensation network in normal operation. If the output capacitance is small, the soft-start circuit can
be adjusted to limit the power-on output voltage overshoot. If the output capacitance is sufficiently large, no
soft-start circuit is required because the LM5002 gradually charges the output capacitor by current limiting at
approximately 500 mA (ILIM) until regulation is achieved.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Switching Frequency
The RT (R3) can be found using Equation 1. For 250-kHz operation, a value of 51.3 kΩ was calculated. A
52.3-kΩ resistor is selected as the closest available value.
8.2.1.2.2 Flyback Transformer
Two things require consideration when specifying a flyback transformer. First, the turns ratio to determine the
duty cyle D (MOSFET on-time compared to the switching period). Second, the primary inductance (LPRI) to
determine the current sense ramp for current-mode control.
To start, the primary inductance in continous current mode (CCM) is designed to provide a ramp during the
MOSFET on-time of around 30% of the full load MOSFET current. This produces a good signal-to-noise ratio for
current mode control.
16
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The transfer function of a flyback power stage is Equation 4.
VOUT
VIN
NSEC
1 D NPRI
D
x
(4)
where:
•
•
•
•
•
VIN is the input voltage
VOUT is the secondary output voltage
D is the duty cycle of the MOSFET for one switching cycle
NPRI is the number of turns on the primary winding of the transformer
NSEC is the number of turns on the secondary winding of the transformer
The duty cycle can be derived as shown in Equation 5.
D
VOUT
VOUT
VINu NSEC
NPRI
(5)
And the approximate turns ratio is given by Equation 6.
NSEC
NPRI
VOUT u (1 D)
VIN u D
(6)
The primary inducance (LPRI) is calculated using Equation 7.
1
fsw
N
RR u IOUT(MAX) u SEC
NPRI
VIN u D u
LPRI
(7)
where:
•
•
LPRI is the transformer inductance referenced to the primary side
RR is the ripple ratio of the reflected secondary output current (ypically between 30% and 40%)
The auxillary winding turns ratio can be found with Equation 8.
NAUX
NSEC u
VAUX
VOUT
(8)
where:
•
•
NAUX is the number of turns on the auxiliary winding of the transformer
VAUX is the desired VCC voltage
The CCM duty cycle can be designed for 50% with minimum input voltage. Using Equation 6, the turns ratio of
the secondary winding to the primay winding can be found to be 0.313. Rounding to a whole number of turns
results in a turns ratio of 0.375. The auxillary winding of the transformer can be used to supply the VCC voltage
to the LM5002, resulting in better total efficiency by disabling the internal high voltage VCC regulator. To disable
the VCC regulator the exteranlly supplied voltage must be greater than 7 V, thus a target voltage of 8 V is
selected. The number of turns on the auxillary winding can be found with Equation 8, resulting in a turns ratio of
the auxillary winding to the secondary winding of 0.6.
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The primary inductance can now be solved for using Equation 7. Assuming that VIN is at the minimum specified
value and the ripple ratio (RR) is 35% the primary inductance is calculated to be 217 µH. Based on avaliable
transformers a 300 µH primary inductance was selected.
18
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8.2.1.2.3 Peak MOSFET Current
The peak MOSFET current is determined with Equation 9.
VIN u D u
IPRI(PEAK)
1
fsw
2 u LPRI
VOUT u IOUT
VIN u Ku D
(9)
where:
•
•
fsw is the switching frequency
ƞ is the efficiency of the converter
The maximum peak MOSFET current occurs when VIN is at its minimum specified voltage. Equation 9 is used to
calculate the peak MOSFET current. Assuming η is 90% the peak MOSFET current is calculated as 430 mA.
The internal power MOSFET must withstand the input voltage plus the output voltage multiplied by the turns ratio
during the off-time. This is determined with Equation 10.
VSW
§
N ·
VIN ¨ VOUT u PRI ¸
NSEC ¹
©
(10)
In addition, any leakage inductance of the transformer causes a turnoff voltage spike in addition to Equation 10.
This voltage spike is related to the MOSFET drain-to-source capacitance as well as other parasitic capacitances.
To limit the spike magnitude, use a RCD termination or a Diode-Zener clamp.
8.2.1.2.4 Output Capacitance
The necessary output capacitance of the secondary side can be found using Equation 11.
COUT
IOUT _ MAX u
DMAX
fSW u 'VOUT
(11)
where:
•
DMAX is the maximum duty cycle, which occurs at the minimum input voltage
Assuming that an output ripple of 15 mV is specified, states that a 60.60 µF output capacitance must be
selected. Accounting for capacitance equivalent series resistance (ESR) ripple, a 100 µF capacitor is selected.
8.2.1.2.5 Output Diode Rating
The average diode current equals the output current under normal circumstances, but the diode must be
designed to handle a continuous current limit condition for the worst case:
ID(WORST
CASE)
ILIMIT(MOSFET) u
NPRI
NSEC
(12)
where:
•
ILIMIT(MOSFET) is the peak current limit of the interal MOSFET of the LM5002
The maximum reverse voltage applied to the diode occurs during the MOSFET on time in Equation 13.
VD(REVERSE)
VIN(MAX) u
NSEC
NPRI
(13)
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The diode's reverse capacitance resonates with the transformer inductance (and other parasitic elements) to
some degree and causing ringing that may affect conducted and ratiated emissions compliance. Usually an RC
snubber network across the diode anode and cathode cam eliminate the ringing.
8.2.1.2.6 Power Stage Analysis
In any switch-mode topology that has the power MOSFET between the inductor and the output capacitor (boost,
buck-boost, Flyback, SEPIC, and so on) a Right Half-Plane Zero (RHPZ) is produced by the power stage in the
loop transfer function during Continuous Conduction Mode (CCM). If the topology is operated in Discontinuous
Conduction Mode (DCM), the RHPZ does not exist. It is a function of the duty cycle, load and inductance, and
causes an increase in loop gain while reducing the loop phase margin. A common practice is to determine the
worst case RHPZ frequency and set the loop unity gain frequency below one-third of the RHPZ frequency
In the Flyback topology, the equation for the RHPZ is given by Equation 14.
VOUT
u (1 D)2
IOUT
ª § N ·2
º
2Su «¨ SEC ¸ u LPRI »
«¬© NPRI ¹
»¼
fRHPZ
(14)
The worst case RHPZ frequency is at the maximum load where IOUT is the highest and at minimum input voltage
where the duty cycle D is the highest. Assuming these conditions fRHPZ is 24.6 kHz.
The LM5002 uses slope compensation to ensure stability when the duty cycle exceeds 45%. This has the affect
of adding some Voltage Mode control to this current-mode IC. The effect on the power stage (Plant) transfer
function is calculated in the following equations:
Inductor current slope during MOSFET ON time (Equation 15)
sn
VIN
LPRI
(15)
Slope compensation ramp (Equation 16)
se
450mV u fSW
(16)
Current-mode sampling gain (Equation 17)
fMOD
VIN u
NSEC
1
u
NPRI s s u 1
n
e
fSW
(17)
The control-to-output transfer function (GVC) using low ESR ceramic capacitors is Equation 18.
D u L SEC
V
2
1 D u OUT
IOUT
1 D
u
u
VOUT
1 D
u COUT
IOUT
1 j2Sf u
2
1 D
1 j2Sf u
GVC (f)
VOUT
IOUT
(18)
where:
20
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LSEC is the transformer inductance referenced to the secondary side and is equal to:
2
L SEC
§ NSEC ·
¨
¸ u LPRI
N
© PRI ¹
(19)
If high ESR capacitors (for example, aluminum electrolytic) are used for the output capacitance, an additional
zero appears at frequency in Equation 20, which increases the gain slope by +20 dB per decade of frequency
and boosts the phase 45° at FZERO(ESR) and 90° at 10 × FZERO(ESR).
fZERO(ESR)
1
2Su ESR u COUT
(20)
where:
•
•
ESR is the series resistance of the output capacitor
COUT is the output capacitance
With these calculations, an approximate power stage Bode plot can be constructed with Equation 21.
GVC (f)
2
20 u log §¨ fMOD ª¬Re GVC (f) º¼
©
2
ª¬Im GVC (f) º¼ ·¸
¹
(21)
where:
•
•
[Re(GVC(f))] is the real portion of
[Im(GVC(f))] is the imaginary portion of
TGVC (f)
§ Im GVC (f) ·
180
u arctan ¨¨
¸¸
S
© Re GVC (f) ¹
(22)
Because these equations don’t take into account the various parasitic resistances and reactances present in
all power converters, there is some difference between the calculated Bode plot and the gain and phase of
the actual circuit. It is therefore important to measure the converter using a network analyzer to quantify the
implementation and adjust where appropriate.
8.2.1.2.7 Loop Compensation
The loop bandwidth and phase margin determines the response to load transients, while ensuring that the
output noise level meets the requirements. A common choice of loop unity gain frequency is 5% of the
switching frequency. This is simple to compensate, low noise and provides sufficient transient response for most
applications. The plant bode plot is examined for gain and phase at the desired loop unity-gain frequency and
the compensator is designed to adjust the loop gain and phase to meet the intended loop unity gain frequency
and phase margin (typically about 55°). When gain is required, the ratio of RCOMP and RFB_TOP sets the error
amplifier to provide the correct amount.
A V(xo)
RCOMP
RFB _ TOP
(23)
where (in reference to Figure 8-5):
•
•
RCOMP is R4
RFB_TOP is R5
The phase margin is boosted by a transfer function zero at frequency given by Equation 23 and a pole at
frequency given by Equation 24.
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fZERO
1
2Su RCOMP u CCOMP
(24)
where (in reference to ):
•
CCOMP is C6
fPOLE(HIGH)
1
§C
uC ·
2Su RCOMP u ¨ COMP HF ¸
© CCOMP CHF ¹
(25)
where (in reference to Figure 8-5):
•
CHF is C5
The low frequency pole is determined with Equation 26.
fPOLE(LOW)
1
2Su RFB _ TOP u CCOMP
u
CHF
1
A VOL
(26)
where (in reference to Figure 8-5):
•
AVOL is the open loop gain of the error amplifier
Optimal regulation is achieved by setting FPOLE(LOW) as high as possible, but still permitting FZERO to insure the
desired phase margin. The feedback resistors (RFB_TOP and RFB_BOTTOM) are chosen to be 10.2 kΩ and 3.4
kΩ respectively. These values produce a feedback signal that has a desirable signal to noise ratio. FZERO and
FPOLE(HIGH) are set to be 450 Hz and 25.5 kHz respectively. Based on these values, RCOMP, CCOMP, and CHF
are chosen to be 7.5 kΩ, 0.47 µF, and 820 pF respectively. These values produce a crossover frequency of
approximately 3 kHz with a phase margin of 60°.
8.2.2 Isolated Flyback Regulator
T1
D1
VCC
VIN = 16V ± 42V
LPRI = 160 éH
8:3:2
D2
VOUT = 5V
C1
4.7 éF
R6
47
C4
1 éF
R2
6.04k
VIN
EN
RT
GND
R3
52.3k
LM5002
R1
60.4k
SW
COMP
FB
VCC
VCC
C2
1 éF
R5
560
C6
100éF
R7
10k
R4
249
C3
1 éF
C5
0.1 PF
LM431
R8
4.99k
IOUT = 500mA
R9
2.20k
R10
2.20k
Figure 8-6. Isolated Flyback Schematic
8.2.2.1 Design Requirements
The isolated flyback converter shown in Figure 8-6 uses a 2.5-V voltage reference (LM431) placed on the
isolated secondary side for the regulation setpoint. The LM5002 internal error amplifier is disabled by grounding
the FB pin. The LM431 controls the current through the opto-coupler LED, which sets the COMP pin voltage.
The R4 and C3 network boosts the phase response of the opto-coupler to increase the loop bandwidth. The
output is 5 V at 500 mA and the input voltage ranges from 16 V to 42 V. The switching frequency is set to 250
kHz.
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8.2.3 Boost Regulator
Figure 8-7. Boost Schematc
8.2.3.1 Design Requirements
The boost converter shown in Figure 8-7 uses the internal voltage reference for the regulation setpoint. The
output is 48 V at 125 mA, while the input voltage can vary from 16 V to 36 V. The switching frequency is
set to 250 kHz. The internal VCC regulator provides 6.9-V bias power, because there is not a simple method
for creating an auxiliary voltage with the boost topology. Note that the boost topology does not provide output
short-circuit protection because the power MOSFET cannot interrupt the path between the input and the output.
8.2.4 24-V SEPIC Regulator
L1
470 PH
VIN = 16 V ± 48 V
C3
10 PF
D2
V OUT = 24 V
I OUT = 125 mA
C1
4.7 PF
L2
470 PH
C4
150 pF
R3
52.3 k
VIN
EN
RT
GND
LM5 002
R1
60.4k
R2
6.04 k
C6
22 µF
C5
R4
0.015 PF 11.5 k
SW
COMP
FB
VCC
C2
1 PF
R5
11.5 k
R6
634
Figure 8-8. 24-V SEPIC Schematic
8.2.4.1 Design Requirements
The 24-V SEPIC converter shown in Figure 8-8 uses the internal voltage reference for the regulation setpoint.
The output is 24 V at 125 mA while the input voltage can vary from 16 V to 48 V. The switching frequency is set
to 250 kHz. The internal VCC regulator provides 6.9-V bias power for the LM5002. An auxiliary voltage can be
created by adding a winding on L2 and a diode into the VCC pin.
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8.2.5 12-V Automotive SEPIC Regulator
Figure 8-9. 12-V SEPIC Schematic
8.2.5.1 Design Requirements
The 12-V automotive SEPIC converter shown in Figure 8-9 uses the internal bandgap voltage reference for the
regulation setpoint. The output is 12 V at 25 mA while the input voltage can vary from 3.1 V to 60 V. The output
current rating can be increased if the minimum VIN voltage requirement is increased. The switching frequency
is set to 750 kHz. The internal VCC regulator provides 6.9-V bias power for the LM5002. The output voltage
can be used as an auxiliary voltage if the nominal VIN voltage is greater than 12 V by adding a diode from the
output into the VCC pin. In this configuration, the minimum input voltage must be greater than 12 V to prevent
the internal VCC to VIN diode from conducting. If the applied VCC voltage exceeds the minimum VIN voltage,
then an external blocking diode is required between the VIN pin and the power source to block current flow from
VCC to the input supply.
24
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9 Power Supply Recommendations
The LM5002 is a power management device. The power supply for the device is any DC voltage source within
the specified input voltage range (see Section 8.2.1.1).
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10 Layout
10.1 Layout Guidelines
The LM5002 current sense and PWM comparators are very fast and may respond to short duration noise pulses.
The components at the SW, COMP, EN and the RT pins must be as physically close as possible to the IC,
thereby minimizing noise pickup on the PCB tracks.
The SW pin of the LM5002 must have a short, wide conductor to the power path inductors, transformers and
capacitors to minimize parasitic inductance that reduces efficiency and increases conducted and radiated noise.
Ceramic decoupling capacitors are recommended between the VIN and GND pins and between the VCC and
GND pins. Use short, direct connections to avoid clock jitter due to ground voltage differentials. Small package
surface mount X7R or X5R capacitors are preferred for high-frequency performance and limited variation over
temperature and applied voltage.
If an application using the LM5002 results high junction temperatures during normal operation, multiple vias from
the GND pin to a PCB ground plane help conduct heat away from the IC. Judicious positioning of the PCB within
the end product, along with use of any available air flow helps reduce the junction temperatures. If using forced
air cooling, avoid placing the LM5002 in the air flow shadow of large components, such as input capacitors,
inductors or transformers.
10.2 Layout Example
Figure 10-1. Layout Example for Figure 8-5
26
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5002MA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5002
MA
LM5002MAX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5002
MA
LM5002SD/NOPB
ACTIVE
WSON
NGT
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5002
LM5002SDX/NOPB
ACTIVE
WSON
NGT
8
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5002
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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