LM5008AEVAL/NOPB

User's Guide SNVA380C – March 2009 – Revised April 2013 AN-1925 LM5008A Evaluation Board 1 Introduction The LM5008AEVAL evaluation board provides the design engineer with a fully functional buck regulator, employing the constant on-time (COT) operating principle. This evaluation board provides a 5V output over an input range of 8V to 75V. The circuit delivers load currents to 300 mA, with current limit set at a nominal 440 mA. The board’s specification are: • Input Voltage: 8V to 75V • Output Voltage: 5V • Maximum load current: 300 mA • Minimum load current: 0A • Current Limit: 440 mA (nominal) • Measured Efficiency: 92.4% (VIN = 8V, IOUT = 100 mA) • Nominal Switching Frequency: 130 kHz • Size: 2.6 in. x 1.6 in. Figure 1. Evaluation Board - Top Side All trademarks are the property of their respective owners. SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated AN-1925 LM5008A Evaluation Board 1 Theory of Operation 2 www.ti.com Theory of Operation Refer to the evaluation board schematic in Figure 5. When the circuit is in regulation, the buck switch is on each cycle for a time determined by R1 and VIN according to the equation: tON = 1.385 x 10 -10 x R1 VIN (1) The on-time of this evaluation board ranges from ≊4.85 µs at VIN = 8V, to ≊517 ns at VIN = 75V. The ontime varies inversely with VIN to maintain a nearly constant switching frequency. At the end of each ontime the Minimum Off-Timer ensures the buck switch is off for at least 300 ns. In normal operation, the offtime is much longer. During the off-time, the load current is supplied by the output capacitor (C2). When the output voltage falls sufficiently that the voltage at FB is below 2.5V, the regulation comparator initiates a new on-time period. For stable, fixed frequency operation, a minimum of 25 mV of ripple is required at FB to switch the regulation comparator. The current limit threshold is ≊470 mA at Vin = 8V, and ≊415 mA at Vin = 75V. Refer to the LM5008A 100V, 350 mA Constant On-Time Buck Switching Regulator (SNVS583) data sheet for a more detailed block diagram, and a complete description of the various functional blocks. 3 Board Layout and Probing The pictorial in Figure 1 shows the placement of the circuit components. The following should be kept in mind when the board is powered: • When operating at high input voltage and high load current, forced air flow may be necessary. • The LM5008A, and diode D1 may be hot to the touch when operating at high input voltage and high load current. • Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible damage to the circuit. • At maximum load current, the wire size and length used to connect the load becomes important. Ensure there is not a significant drop in the wires between this evaluation board and the load 4 Board Connection/Start-up The input connections are made to the J1 connector. The load is connected to the J2 (OUT) and J3 (GND) terminals. Ensure the wires are adequately sized for the intended load current. Before start-up a voltmeter should be connected to the input terminals, and to the output terminals. The load current should be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased gradually to 8V, at which time the output voltage should be 5V. If the output voltage is correct with 8V at VIN, then increase the input voltage as desired and proceed with evaluating the circuit. DO NOT EXCEED 75V AT VIN. 5 Output Ripple Control The LM5008A requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform at the SW pin, for proper operation. The required ripple can be supplied from ripple at VOUT, through the feedback resistors as described in Option A below. Options B and C provide lower output ripple with one or two additional components. Option A) Lowest Cost Configuration: In this configuration R5 is installed in series with the output capacitance (C2). Since ≥25 mVp-p are required at the FB pin, R5 must be chosen to generate ≥50 mVpp at VOUT, knowing that the minimum ripple current in this circuit is ≊66 mAp-p at minimum VIN. Using 0.82Ω for R5, the ripple at VOUT ranges from ≊54 mVp-p to ≊135 mVp-p over the input voltage range. If the application can accept this ripple level, this is the most economical solution. The circuit is shown in Figure 2 and Figure 8. 2 AN-1925 LM5008A Evaluation Board SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Output Ripple Control www.ti.com 8V to 75V Input VIN VCC VIN C1 1 PF C5 0.1 PF C3 0.47 PF LM5008A GND R1 280k BST SW RT/SD SHUTDOWN (TP1SD) C4 0.1 PF L1 220 PH VOUT 5V D1 RCL R6 0: R3 3.01k R5 0.82: FB R2 715k R4 3.01k C2 22 PF RTN GND Figure 2. Lowest Cost Configuration Option B) Intermediate Ripple Configuration: This configuration generates less ripple at VOUT than option A above by the addition of one capacitor (Cff) across R3, as shown in Figure 3. 8V to 75V Input VIN VCC VIN C1 1 PF C5 0.1 PF C3 0.47 PF LM5008A GND R1 280k BST SW RT/SD SHUTDOWN (TP1SD) D1 RCL C4 0.1 PF L1 220 PH R6 0: VOUT 5V Cff 0.01 PF R3 3.01k R5 0.39: FB R2 715k R4 3.01k RTN C2 22 PF GND Figure 3. Intermediate Ripple Configuration Since the output ripple is passed by Cff to the FB pin with little or no attenuation, R5 can be reduced so the minimum ripple at VOUT is ≊25 mVp-p. The minimum value for Cff is calculated from: Cff t 3 x tON (max) (R3//R4) (2) where tON(max) is the maximum on-time (at minimum VIN), and R3//R4 is the parallel equivalent of the feedback resistors. The ripple at VOUT ranges from 26 mVp-p to 64 mVp-p over the input voltage range. See Figure 8. Option C) Minimum Ripple Configuration: To obtain minimum ripple at VOUT, R5 is set to 0Ω, and RA, CA, and CB are added to generate the required ripple for the FB pin. In this configuration, the output ripple is determined primarily by the characteristics of the output capacitance and the inductor’s ripple current. See Figure 4. SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated AN-1925 LM5008A Evaluation Board 3 Output Ripple Control www.ti.com The ripple voltage required by the FB pin is generated by RA, and CA since the SW pin switches from -1V to VIN, and the right end of CA is a virtual ground. The values for RA and CA are chosen to generate a 50100 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through CB. The following procedure is used to calculate values for RA, CA and CB: 1) Calculate the voltage VA: VA = VOUT – (VSW x (1 – (VOUT/VIN))) (3) where VSW is the absolute value of the voltage at the SW pin during the off-time (typically 0.6V), and VIN is the minimum input voltage. For this circuit, VA calculates to 4.78V. This is the approximate DC voltage at the RA/CA junction, and is used in the next equation. 2) Calculate the RA x CA product: RA x CA = (VIN ± VA) x tON 'V (4) where tON is the maximum on-time (≊4.85 µs), VIN is the minimum input voltage, and ΔV is the desired ripple amplitude at the RA/CA junction, 50 mVp-p for this example. RA x CA = (8V - 4.78V) x 4.85 Ps 0.05V = 3.12 x 10-4 (5) RA and CA are then chosen from standard value components to satisfy the above product. Typically CA is 3000 to 10000 pF, and RA is 10 kΩ to 300 kΩ. CB is chosen large compared to CA, typically 0.1 µF. The ripple at VOUT is typically less than 10 mVp-p. See Figure 4 and Figure 8. 8V to 75V Input VIN VIN C1 1 PF GND VCC R1 280k BST RT/SD SHUTDOWN (TP1SD) C3 0.47 PF LM5008A C5 0.1 PF SW L1 C4 220 PH 0.1 PF VOUT 5V R6 0: D1 RCL RA 64.9k FB R2 715k CA 4700 pF CB 0.1 PF R4 3.01k RTN R3 3.01k R5 0: C2 22 PF GND Figure 4. Minimum Output Ripple Configuration 4 AN-1925 LM5008A Evaluation Board SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Current Limit Off-Time www.ti.com 6 Current Limit Off-Time When current limit is detected the on-time period is immediately terminated, and the off-time forced by the LM5008A must be greater than the maximum normal off-time, which occurs at maximum input voltage. The longer-than-normal off-time is necessary to allow the inductor current to decrease at least as much, if not more, than the current increase which occurred during the on-time leading to the current limit detection. The forced off-time is determined by the resistor at the RCL pin (R2), and is calculated from the following: TOFF = 10-5/(0.285 + (VFB/6.35 x 10-6 x R2)) (6) where VFB is the voltage at the FB pin at the time of the current limit detection. In this evaluation board, the maximum normal off-time is approximately 7.2 µs (at 75V). Due to the 25% tolerance of the on-time, the off-time tolerance is also 25%, yielding a maximum possible off-time of 9 µs. Allowing for the response time of the current limit detection circuit (350 ns) the maximum off-time, for the purpose of this calculation, is increased to 9.35 µs. This is increased an additional 25% to 11.7 µs to allow for the tolerances of the above equation. Using the above equation, R2 calculates to 691 kΩ at VFB = 2.5V. A standard value 715 kΩ resistor is used. 7 Monitor The Inductor Current The inductor’s current can be monitored or viewed on a scope with a current probe. Remove R6, and install an appropriate current loop across the two large pads where R6 was located. In this way the inductor’s ripple current and peak current can be accurately determined. 8 Scope Probe Adapters Scope probe adapters are provided on this evaluation board for monitoring the waveform at the SW pin, and at the circuit’s output (VOUT), without using the probe’s ground lead which can pick up noise from the switching waveforms. The probe adapters are suitable for Tektronix P6137 or similar probes, with a 0.135” diameter. 8V to 75V Input VIN VCC VIN C1 1 PF C3 0.47 PF LM5008A C5 0.1 PF SW GND R1 280k BST C4 SW RT/SD SHUTDOWN (TP1SD) 0.1 PF L1 220 PH 5V D1 RCL VOUT R6 0: R3 3.01k R5 0.82: VOUT FB R2 715k R4 3.01k C2 22 PF RTN GND Figure 5. Complete Evaluation Board Schematic (As Supplied) SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated AN-1925 LM5008A Evaluation Board 5 Scope Probe Adapters www.ti.com Table 1. Bill of Materials 6 Item Description Mfg., Part Number Package Value C1 C2 Ceramic Capacitor TDK C3216X7R2A105M or Murata GRM31CR72A105KA01L 1206 1 µF, 100V Ceramic Capacitor TDK C3225X7R1C226M or Murata GRM32ER71C226KE18L 1210 22 µF, 16V C3 Ceramic Capacitor TDK C1608X7R1C474M or TDK C1608X7R1C474K 0603 0.47 µF, 16V C4 Ceramic Capacitor TDK C1608X7R1H103M 0603 0.01 µF, 50V C5 Ceramic Capacitor TDK C2012X7R2A104M or Murata GRM188R72A104KA35D 0805 0.1 µF, 100V D1 Schottky Diode Diodes Inc. DFLS1100 or Central Semi CMMSH1-100 Power DI123 100V, 1A L1 Power Inductor Coiltronics DR1050-221-R or TDK SLF10145T-221MR65 10mm x 10mm 220 µH R1 Resistor Vishay CRCW06032803F 0603 280k R2 Resistor Vishay CRCW06037153F 0603 715k R3, R4 Resistor Vishay CRCW06033011F 0603 3.01k R5 Resistor Panasonic ERJ-3RQFR82V 0603 0.82 ohms R6 Resistor Vishay CRCW08050000Z 0805 0Ω Jumper U1 Switching Regulator Texas Instruments LM5008 VSSOP-8 AN-1925 LM5008A Evaluation Board SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Circuit Performance www.ti.com 9 Circuit Performance Figure 6. Efficiency vs Load Current Figure 7. Efficiency vs Input Voltage Figure 8. Output Voltage Ripple SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated AN-1925 LM5008A Evaluation Board 7 Circuit Performance www.ti.com Figure 9. Switching Frequency vs. Input Voltage Figure 10. Current Limit vs Input Voltage Figure 11. Line Regulation 8 AN-1925 LM5008A Evaluation Board SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Typical Waveforms www.ti.com Figure 12. Load Regulation 10 Typical Waveforms Trace 1 = SW Pin Trace 3 = VOUT Trace 4 = Inductor Current Vin = 12V, Iout = 200 mA Figure 13. Continuous Conduction Mode Trace 1 = SW Pin Trace 3 = VOUT Trace 4 = Inductor Current Vin = 12V, Iout = 0 mA Figure 14. Discontinuous Conduction Mode SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated AN-1925 LM5008A Evaluation Board 9 Typical Waveforms www.ti.com Trace 1 = SW Pin Trace 3 = VOUT Trace 4 = Inductor Current Vin = 12V, Iout = 0 mA Figure 15. Discontinuous Conduction Mode 10 AN-1925 LM5008A Evaluation Board SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated PC Board Layout www.ti.com 11 PC Board Layout Figure 16. Board Silkscreen Figure 17. Board Top Layer Figure 18. Board Bottom Layer (Viewed from Top) SNVA380C – March 2009 – Revised April 2013 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated AN-1925 LM5008A Evaluation Board 11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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