LM5013DDAR

LM5013 SNVSCB3 – OCTOBER 2022 LM5013 100-V Input, 3.5-A Non-Synchronous Buck DC/DC Converter with Ultra-Low IQ 1 Features 3 Description • The LM5013 non-synchronous buck converter is designed to regulate over a wide input voltage range, minimizing the need for external surge suppression components. A minimum controllable on time of 50 ns facilitates large step-down conversion ratios, enabling the direct step-down from a 48-V nominal input to low-voltage rails for reduced system complexity and solution cost. The LM5013 operates during input voltage dips as low as 6 V, at nearly 100% duty cycle if needed, making it an excellent choice for highperformance industrial applications. • • • • Designed for reliable and rugged applications – Wide input voltage range of 6 V to 100 V – –40°C to +125°C junction temperature range – Fixed 3.5-ms internal soft-start timer – Peak current-limit protection – Input UVLO and thermal shutdown protection – Functional Safety-Capable • Documentation available to aid functional safety system design Optimized for ultra-low EMI requirements – Meets CISPR 25 class 5 standard Suited for scalable Industrial power supplies – Pin-to-pin compatible with the LM5163-Q1 and LM5164-Q1 (100 V, 0.5 A or 1 A), and LM5013Q1 (100 V, 3.5 A) – 50-ns low minimum on times and off times – 10-µA no-load sleep current – 3.1-µA shutdown quiescent current Integration reduces solution size and cost – COT mode control architecture – Integrated 100-V 0.25-Ω high-side power MOSFET – 1.2-V internal voltage reference – No loop compensation components – Internal VCC bias regulator and boot diode Create a custom regulator design using WEBENCH® Power Designer With an integrated high-side power MOSFET, the LM5013 delivers up to 3.5 A of output current. A constant on-time (COT) control architecture provides nearly constant switching frequency with excellent load and line transient response. Additional features of the LM5013 include ultra-low IQ and a innovative peak overcurrent protection, integrated VCC bias supply and bootstrap diode, precision enable and input UVLO, and thermal shutdown protection with automatic recovery. An open-drain PGOOD indicator provides sequencing, fault reporting, and output voltage monitoring. The LM5013 is available in a 8-pin SO PowerPAD™ integrated circuit package. The device 1.27-mm pin pitch provides adequate spacing for high-voltage applications. 2 Applications • • • Package Information Hybrid, electric and powertrain systems Inverter and motor control Industrial transport (1) VIN H Body Size (NOM) LM5013 DDA (SO PowerPAD, 8) 4.89 mm × 3.90 mm For all available packages, see the orderable addendum at the end of the data sheet. SW CBST 2.2 nF LM5013 CIN 2 × 2.2 µF Package(1) VOUT = 12 V IOUT = 3.5 A LO U1 VIN = 6 V...100 V Part Number EN/UVLO DSW RA 453 k CA 3.3 nF RFB1 453 k BST CB 56 pF RON FB GND PGOOD RRON 100 k COUT 22 F RFB2 49.9 k Typical Application, VIN(nom) = 48 V, VOUT = 12 V, IOUT(max) = 3.5 A, fSW(nom) = 300 kHz Typical Application Efficiency, VOUT = 12 V An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings_Catalog................................................. 5 7.3 Recommended Operating Conditions.........................6 7.4 Thermal Information....................................................6 7.5 Electrical Characteristics.............................................6 7.6 Typical Characteristivcs.............................................. 8 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 11 8.3 Feature Description...................................................11 8.4 Device Functional Modes..........................................16 9 Application and Implementation.................................. 17 9.1 Application Information............................................. 17 9.2 Typical Application.................................................... 17 9.3 Power Supply Recommendations.............................23 9.4 Layout....................................................................... 23 10 Device and Documentation Support..........................28 10.1 Device Support....................................................... 28 10.2 Documentation Support.......................................... 28 10.3 Receiving Notification of Documentation Updates..29 10.4 Support Resources................................................. 29 10.5 Trademarks............................................................. 29 10.6 Electrostatic Discharge Caution..............................29 10.7 Glossary..................................................................29 11 Mechanical, Packaging, and Orderable Information.................................................................... 29 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES October 2022 * Initial release Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 5 Device Comparison Table Device Description Orderable Part Number Package VIN IOUT LM5163-Q1 Automotive 100-V input, 0.5-A synchronous buck converter LM5163QDDARQ1 SO PowerPAD (8) integrated circuit package 100 V 0.5 A LM5164-Q1 Automotive 100-V input, 1-A synchronous buck converter LM5164QDDARQ1 SO PowerPAD (8) integrated circuit package 100 V 1A LM5012-Q1 Automotive 100-V, 2.5-A nonsynchronous buck converter LM5012QDDARQ1 SO PowerPAD (8) integrated circuit package 100 V 2.5 A LM5012 100-V input, 2.5-A nonsynchronous buck converter LM5012DDAR SO PowerPAD (8) integrated circuit package 100 V 2.5 A LM5013-Q1 Automotive, 100-V, 3.5-A nonsynchronous buck converter LM5013QDDARQ1 SO PowerPAD (8) integrated circuit package 100 V 3.5 A LM5013 100-V, 3.5-A non-synchronous buck converter LM5013DDAR SO PowerPAD (8) integrated circuit package 100 V 3.5 A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 3 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 6 Pin Configuration and Functions GND 1 8 SW VIN 2 7 BST 3 6 PGOOD 4 5 FB EP RON Figure 6-1. 8-Pin SO PowerPAD™ DDA Integrated Circuit Package (Top View) Table 6-1. Pin Functions Pin DESCRIPTION NO. GND 1 G Ground connection for internal circuits VIN 2 P/I Regulator supply input pin to high-side power MOSFET and internal bias regulator. Connect directly to the input supply of the buck converter with short, low impedance paths. EN/UVLO 3 I Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is below 1.1 V, the converter is in shutdown mode with all functions disabled. If the UVLO voltage is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal VCC regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up sequence begins. RON 4 I On-time programming pin. A resistor between this pin and GND sets the buck switch on time. FB 5 I Feedback input of voltage regulation comparator PGOOD 6 O Power-good indicator. This pin is an open-drain output pin. Connect to a source voltage through an external pullup resistor between 10 kΩ to 100 kΩ. BST 7 P/I Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF, 50-V X7R ceramic capacitor between BST and SW to bias the internal high-side gate driver. SW 8 P Switching node that is internally connected to the source of the high-side NMOS buck switch. Connect to the switch node of the power supply inductor and Schottky diode. EP — — Exposed pad of the package. No internal electrical connection. Connect the EP to the GND pin and connect to a large copper plane to reduce thermal resistance. (1) 4 Type(1) Name G = Ground, I = Input, O = Output, P = Power Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 7 Specifications 7.1 Absolute Maximum Ratings Over operating junction temperature range (unless otherwise noted) (1) MIN MAX UNIT Pin voltage VIN to GND –0.3 100 V Pin voltage SW to GND –1.5 100 V Pin voltage SW to GND, tSW Figure 8-1. Current Limit Timing Diagram 8.3.7 N-Channel Buck Switch and Driver The LM5013 integrates an N-channel buck switch and associated floating high-side gate driver. The gate-driver circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage bootstrap diode. A high-quality 2.2-nF, 50-V X7R ceramic capacitor connected between the BST and SW pins provides the voltage to the high-side driver during the buck switch on time. During the off time, the SW pin is pulled down to approximately 0 V, and the bootstrap capacitor charges from the internal VCC through the internal bootstrap diode. The minimum off timer, set to 50 ns (typical), ensures a minimum time each cycle to recharge the bootstrap capacitor. When the on time is less than 300 ns, the minimum off timer is forced to 250 ns to ensure that the BST capacitor is charged in a single cycle, which is vital during wake-up from sleep mode when the BST capacitor is most likely discharged. 8.3.8 Schottky Diode Selection A Schottky diode is required for all LM5013 applications to re-circulate the energy in the output inductor when the high-side MOSFET is off. The reverse breakdown rating of the diode must be greater than the maximum VIN plus a 25% safety margin, as specified in Schotttky Diode applicatio section. The current rating of the diode must exceed the maximum DC output current and support the peak current limit (IPEAK current limit) for the best reliability. In this case, the diode carries the maximum load current. 8.3.9 Enable and Undervoltage Lockout (EN/UVLO) The LM5013 contains a dual-level EN/UVLO circuit. When the EN/UVLO voltage is below 1.1 V (typical), the converter is in a low-current shutdown mode and the input quiescent current (IQ) is dropped down to 3 µA. When the voltage is greater than 1.1 V but less than 1.5 V (typical), the converter is in standby mode. In standby mode, the internal bias regulator is active while the control circuit is disabled. When the voltage exceeds the rising threshold of 1.5 V (typical), normal operation begins. Install a resistor divider from VIN to GND to set the minimum operating voltage of the regulator. Use Equation 5 and Equation 6 to calculate the input UVLO turn-on and turn-off voltages, respectively. VIN(on) VIN(off) 14 § RUV1 · 1.5 V ˜ ¨ 1 ¸ © RUV2 ¹ (5) § RUV1 · 1.4 V ˜ ¨ 1 ¸ R UV2 ¹ © (6) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 TI recommends selecting RUV1 in the range of 1 MΩ for most applications. A larger RUV1 consumes less DC current, which is mandatory if light-load efficiency is critical. If input UVLO is not required, the power-supply designer can either drive EN/UVLO as an enable input driven by a logic signal or connect it directly to VIN. If EN/UVLO is directly connected to VIN, the regulator begins switching as soon as the internal bias rails are active. 8.3.10 Power Good (PGOOD) The LM5013 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level. Use the PGOOD signal for start-up sequencing of downstream converters or for fault protection and output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 14 V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the voltage from a higher voltage pullup rail. When the FB voltage exceeds 95% of the internal reference VREF, the internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls below 90% of VREF, an internal 25-Ω PGOOD switch turns on and PGOOD is pulled low to indicate that the output voltage is out of regulation. The rising edge of PGOOD has a built-in deglitch delay of 5 µs. 8.3.11 Thermal Protection The LM5013 includes an internal junction temperature monitor to protect the device in the event of a higher than normal junction temperature. If the junction temperature exceeds 175°C (typical), thermal shutdown occurs to prevent further power dissipation and temperature rise. The LM5013 initiates a restart sequence when the junction temperature falls to 165°C, based on a typical thermal shutdown hysteresis of 10°C, which is a non-latching protection, so the device cycles into and out of thermal shutdown if the fault persists. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 15 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 8.4 Device Functional Modes 8.4.1 Shutdown Mode EN/UVLO provides ON and OFF control for the LM5013. When VEN/UVLO is below approximately 1.1 V, the device is in shutdown mode. Both the internal linear regulator and the switching regulator are off. The quiescent current in shutdown mode drops to 3.1 µA at VIN = 24 V. The LM5013 also employs internal bias rail undervoltage protection. If the internal bias supply voltage is below the UV threshold, the regulator remains off. 8.4.2 Standby Mode The LM5013 enter standby mode during light or no-load on the output. The LM5013 enters standby mode to prevent draining the input power supply. All internal controller circuits are turned off to reduce the current consumption. The quiescent current in standby mode is 25 μA (typical). 8.4.3 Active Mode The LM5013 is in active mode when VEN/UVLO is above the precision enable threshold and the internal bias rail is above its UV threshold. In COT active mode, the LM5013 is in one of three modes depending on the load current: • • • CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple The LM5013 enters discontinuous conduction mode when the load current is less than half of the peak-topeak inductor current in CCM operation. Current limit CCM with peak current limit protection when an overcurrent condition is applied at the output 8.4.4 Sleep Mode During discontinuous conduction mode, the load current is lower than half of the peak-to-peak inductor current ripple and the switching frequency decreases when the load is further decreased in pulse skipping mode. A switching pulse is set when VFB drops below 1.2 V. As the frequency of operation decreases and VFB remains above 1.2 V (VREF) with the output capacitor sourcing the load current for greater than 15 µs, the converter enters an ultra-low IQ sleep mode to prevent draining the input power supply. The input quiescent current (IQ) required by the LM5013 decreases to 10 µA in sleep mode, improving the light-load efficiency of the regulator. In this mode, all internal controller circuits are turned off to ensure very low current consumption by the device. Such low IQ renders the LM5013 as the best option to extend operating lifetime for off-battery applications. The FB comparator and internal bias rail are active to detect when the FB voltage drops below the internal reference VREF and the converter transitions out of sleep mode into active mode. There is a 9-µs wake-up delay from sleep to active states. 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The LM5013 requires only a few external components to step down from a wide range of supply voltages to a fixed output voltage. Several features are integrated to meet system design requirements, including the following: • • • • • Precision enable Input voltage UVLO Internal soft start Programmable switching frequency A PGOOD indicator To expedite the process of designing with LM5013, a LM5013 design calculator is available on the product folder "tool" section. This calculator is complemented by an evaluation module for order, PSPICE models, as well as TI's WEBENCH® Power Designer. 9.2 Typical Application Figure 9-1 shows the schematic for 48-V to 12-V conversion. H VIN SW CBST 2.2 nF LM5013 CIN 2 × 2.2 µF VOUT = 12 V IOUT = 3.5 A LO U1 VIN = 6 V...100 V EN/UVLO DSW RA 453 k CA 3.3 nF RFB1 453 k BST CB 56 pF RON RRON 100 k GND COUT 22 F FB RFB2 49.9 k PGOOD Figure 9-1. Typical Application, VIN(nom) = 48 V, VOUT = 12 V, IOUT(max) = 3.5 A, fSW(nom) = 300 kHz Note This and subsequent design examples are provided herein to showcase the LM5013 converter in several different applications. Depending on the source impedance of the input supply bus, an electrolytic capacitor can be required at the input to ensure stability, particularly at low input voltage and high output current operating conditions. See the Power Supply Recommendations section for more details. 9.2.1 Design Requirements The target full-load efficiency is 92% based on a nominal input voltage of 48 V and an output voltage of 12 V. The required input voltage range is 15 V to 100 V. The switching frequency is set by resistor RON at 300 kHz. The output voltage soft-start time is 3 ms. Refer to LM5013-Q1 EVM user's guide for more detail on component selection. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 17 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 9.2.2 Detailed Design Procedure 9.2.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the LM5013 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 9.2.2.2 Switching Frequency (RRON) The switching frequency of the LM5013 is set by the on-time programming resistor placed at RON. As shown by Equation 7, a standard 100-kΩ, 1% resistor sets the switching frequency at 300 kHz. RRON (k:) VOUT (V) ˜ 2500 FSW (kHz) (7) Note that at very low duty cycles, the 50-ns minimum controllable on time of the high-side MOSFET, tON(min), limits the maximum switching frequency. In CCM, tON(min) limits the voltage conversion step-down ratio for a given switching frequency. Use Equation 8 to calculate the minimum controllable duty cycle. DMIN t ON(min) ˜ FSW (8) Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range, solution size, and efficiency. Use Equation 9 to calculate the maximum supply voltage for a given tON(min) before switching frequency reduction occurs. VIN(max) VOUT t ON(min) ˜ FSW (9) 9.2.2.3 Buck Inductor (LO) Use Equation 10 and Equation 11 to calculate the inductor ripple current (assuming CCM operation) and peak inductor current, respectively. 'IL VOUT § VOUT · ˜ ¨1 ¸ FSW ˜ LO © VIN ¹ IL(peak) IOUT(max) (10) 'IL 2 (11) For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 50% of the rated load current at nominal input voltage. Use Equation 12 to calculate the inductance. 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com LO SNVSCB3 – OCTOBER 2022 VOUT FSW ˜ 'IL § VOUT ˜ ¨1 ¨ VIN(nom) © · ¸ ¸ ¹ (12) For applications in which the device must support input transients exceeding 72 V, select the inductor to be at least 22 μH, which ensures that excessive current rise does not occur in the power stage due to the potential large inductor current slew that can occur in an output short-circuit condition. Choosing a 22-μH inductor in this design results in 1.36-A peak-to-peak ripple current at a nominal input voltage of 48 V, equivalent to 39% of the 3.5-A rated load current. For designs which must operate up to the maximum input voltage at the full-rated load current of 3.5 A, the inductance needs to increase to ensure current limit (IPEAK current limit) is not hit. Check the inductor data sheet to make sure the saturation current of the inductor is well above the current limit setting of the LM5013. TI recommends a saturation current greater than 7 A. Ferrite-core inductors have relatively lower core losses and are preferred at high switching frequencies, but exhibit a hard saturation characteristic – the inductance collapses abruptly when the saturation current is exceeded. This collapse results in an abrupt increase in inductor ripple current, higher output voltage ripple, and reduced efficiency, and in turn compromising reliability. Note that inductor saturation current levels generally decrease as the core temperature increases. 9.2.2.4 Schottky Diode (DSW) The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. In the target application, the power rating for the diode must exceed the maximum DC output current and support the peak current limit (IPEAK current limit) for best reliability in most applications. 9.2.2.5 Output Capacitor (COUT) Select a ceramic output capacitor to limit the capacitive voltage ripple at the converter output, which is the sinusoidal ripple voltage that is generated from the triangular inductor current ripple flowing into and out of the capacitor. Select an output capacitance using Equation 13 to limit the voltage ripple component to 0.5% of the output voltage. COUT t 'IL 8 ˜ FSW ˜ VOUT(ripple) (13) Substituting ΔIL(nom) of 1.36 A gives COUT greater than 10 μF. With voltage coefficients of ceramic capacitors taken in consideration, a 22-µF, 25-V rated capacitor with X7R dielectric is selected. 9.2.2.6 Input Capacitor (CIN) An input capacitor is necessary to limit the input ripple voltage while providing AC current to the buck power stage at every switching cycle. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the VIN and GND pins of the LM5013. The input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The device follows that the resultant capacitive component of AC ripple voltage is a triangular waveform. Along with the ESR-related ripple component, use Equation 14 to calculate the peak-to-peak ripple voltage amplitude. VIN(ripple) IOUT ˜ D ˜ 1 D FSW ˜ CIN IOUT ˜ RESR (14) Use Equation 15 to calculate the input capacitance required for a load current, based on an input voltage ripple specification (ΔVIN). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 19 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 CIN t IOUT ˜ D ˜ 1 D FSW ˜ VIN(ripple) IOUT ˜ RESR (15) The recommended high-frequency input capacitance is 4.4 µF or higher. Ensure the input capacitor is a highquality X7S or X7R ceramic capacitor with sufficient voltage rating for CIN. Based on the voltage coefficient of ceramic capacitors, choose a voltage rating preferably twice the maximum input voltage. Additionally, some bulk capacitance can be required for large input loop inductance or long wire harnesses used in the system. This capacitor provides parallel damping to the resonance associated with parasitic inductance of the supply lines and high-Q ceramics. See the Power Supply Recommendations section for more detail. 9.2.2.7 Type 3 Ripple Network A Type 3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT to generate a triangular ramp that is in phase with the inductor current. This triangular ramp is then AC-coupled into the feedback node using capacitor CB as shown in Figure 9-1. Type 3 ripple injection is suited for applications where low output voltage ripple is crucial. Use Equation 16 and Equation 17 to calculate RA and CA to provide the required ripple amplitude at the FB pin. CA t 10 FSW ˜ RFB1 RFB2 (16) For the feedback resistor RFBT = 453 kΩ and RFBB = 49.9 kΩ values shown in Figure 9-1, Equation 16 dictates a minimum CA of 742 pF. In this design, a 3300-pF capacitance is chosen. This value is chosen to keep RA within practical limits between 100 kΩ and 1 MΩ when using Equation 17. Ra  × Ca ≤ VIN nom − VOUT × tON nom   20mV (17) Based on CA set at 3.3 nF, RA is calculated to be 453 kΩ to provide a 20-mV ripple voltage at FB. The general recommendation for a Type 3 network is to calculate RA and CA to get 20 mV of ripple at typical operating conditions. A smaller RA can need to be used to operate below nominal 48-V input. Ensure 12 mV of FB ripple or more at the minimum input voltage design to ensure stability. While the amplitude of the generated ripple does not affect the output voltage ripple, it impacts the output regulation as it reflects as a DC error of approximately half the amplitude of the generated ripple. For example, a converter circuit with Type 3 network that generates a 40-mV ripple voltage at the feedback node has approximately 10-mV worse load regulation scaled up through the FB divider to VOUT than the same circuit that generates a 20-mV ripple at FB. Use Equation 18 to calculate the coupling capacitance, CB. CB t t TR-settling 3 ˜ RFB1 (18) where • tTR-settling is the desired load transient response settling time. CB calculates to 56 pF based on a 75-µs settling time. This value avoids excessive coupling capacitor discharge by the feedback resistors during sleep intervals when operating at light loads. To avoid capacitance fall-off with DC bias, use a C0G or NP0 dielectric capacitor for CB. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 9.2.3 Application Curves VOUT = 12 V RON = 102 kΩ LO = 22 μH Figure 9-2. Conversion Efficiency (Linear Scale) VOUT = 12 V RON = 102 kΩ LO = 22 μH Figure 9-4. Load and Line Regulation Performance VOUT = 12 V RON = 102 kΩ LO = 22 μH Figure 9-3. Conversion Efficiency (Linear Scale) VIN = 48 V VOUT = 12 V IOUT = 1.75-A to 3.5-A (Rise/fall time = 1 A/μS) Figure 9-5. Load Step Response VIN = 48 V VOUT = 12 V IOUT = 0 A Figure 9-6. No-Load Start-Up with EN/UVLO VIN = 48 V VOUT = 12 V Load = 0 A to Short Figure 9-7. Short Circuit Applied Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 21 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 VIN = 48 V VOUT = 12 V Load = 0 A to Short Figure 9-8. Short-Circuit Recovery VIN = 48 V VOUT = 12 V IOUT = 200mA Figure 9-9. Light-load Switching Filter used for EMC scan. Additionally, regulator was housed in enclosed shield. VIN = 48 V VOUT = 12 V IOUT = 3.5 A Figure 9-10. Full-Load Switching VIN = 48 V Figure 9-11. Suggested EMC Filter for CISPR 25 Class 5 Compliance VOUT = 12 V IOUT = 3.5 A Figure 9-12. CISPR 25 Class 5 Conducted Emissions Plot, 150 kHz to 110 MHz 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 9.3 Power Supply Recommendations The LM5013 buck converter is designed to operate from a wide input voltage range between 6 V and 100 V. In addition, the input supply must be capable of delivering the required input current to the fully-loaded regulator. Use Equation 19 to estimate the average input current. IIN VOUT ˜ IOUT VIN ˜ K (19) where • η is the efficiency. If the converter is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse effect on converter operation. The parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the converter is operating close to the minimum input voltage, this dip can cause false UVLO fault triggering and a system reset, in addition to potential stability issues. The circuit can be damped with a "parallel damping network." For example, a 22-μF damping capacitor in series with a 1.4-Ω resistor connected to the VIN node, creates a parallel damped network, providing sufficient damping for a 8.2-μH input filter inductor and 4.4-μF ceramic input capacitance. Damping is not only needed for an input EMC filter, but also when the application utilizes a power harness, which can present a large input loop inductance. For example, two cables (one for VIN and one for GND), each one meter (approximately three feet) long with approximately 1-mm diameter (18 AWG), placed 1 cm (approximately 0.4 inch) apart forms a rectangular loop resulting in about 1.2 µH of inductance. The Input Filter Design for Switching Power Supplies application report provides more detail on this topic. An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters application report provides helpful suggestions when designing an input filter for any switching regulator. 9.4 Layout 9.4.1 Layout Guidelines PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade the power supply performance. • • • • • • • • To help eliminate these problems, bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with a high-quality dielectric. Place CIN as close as possible to the VIN and GND pins. Grounding for both the input and output capacitors must consist of localized top-side planes that connect to the GND pin and GND PAD. Minimize the loop area formed by the input capacitor connections to the VIN and GND pins. Place the inductor and Schottky diode close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive capacitive coupling. Place the Schottky diode anode pin in close proximity to input capacitor ground or return. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path. Have a single-point ground connection to the plane. Route the ground connections for the feedback, soft start, and enable components to the ground plane, which prevents any switched or load currents from flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior. Make VIN, VOUT, and ground bus connections as wide as possible, which reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 23 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 • • • • Minimize trace length to the FB pin. Place both feedback resistors, RFB1 and RFB2, close to the FB pin. Place CFF (if needed) directly in parallel with RFB1. If output setpoint accuracy at the load is important, connect the VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on the other side of a grounded shielding layer. The RON pin is sensitive to noise. Thus, locate the RRON resistor as close as possible to the device and route with minimal lengths of trace. The parasitic capacitance from RON to GND must not exceed 20 pF. Provide adequate heat sinking for the LM5013 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heatsinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper layers, these thermal vias must also be connected to inner layer heat-spreading ground planes. Reference Layout Example. 9.4.1.1 Compact PCB Layout for EMI Reduction Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimizing radiated EMI is to identify the pulsing current path and minimize the area of that path. Figure 9-13 denotes the critical switching loop of the buck converter power stage in terms of EMI. The topological architecture of a buck converter means that a particularly high di/dt current path exists in the loop comprising the input capacitor and the integrated MOSFET of the LM5013, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing the effective loop area. VIN CIN 2 LM5012 High di/dt loop BST High-side NMOS gate driver Q1 LO 8 SW VOUT D1 1 GND CO GND Figure 9-13. DC/DC Buck Converter With Power Stage Circuit Switching Loop The input capacitor provides the primary path for the high di/dt components of the current of the high-side MOSFET. Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction. Keep the trace connecting SW to the inductor as short as possible and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the return terminal of the capacitor to the GND pin and exposed PAD of the LM5013. 9.4.1.2 Feedback Resistors Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than close to the load, which reduces the trace length of FB signal and noise coupling. The FB pin is the input to the feedback comparator, and as such, is a high impedance node sensitive to noise. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if a short path is not available. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 Route the voltage sense trace from the load to the feedback resistor divider, keeping away from the SW node, the inductor, and VIN to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This action is most important when high feedback resistances greater than 100 kΩ are used to set the output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node, and VIN so there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon, which provides further shielding for the voltage feedback path from switching noise sources. 9.4.2 Layout Example Figure 9-14 shows an example layout for the PCB top layer of a 2-layer board with essential components placed on the top side. Figure 9-14. LM5013 Layout Example 9.4.2.1 Thermal Considerations As with any power conversion device, the LM5013 dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die temperature (TJ) is a function of the following: • • • • Ambient temperature Power loss Effective thermal resistance, RθJA, of the device PCB combination The maximum internal die temperature for the LM5013 must be limited to 150°C, which establishes a limit on the maximum device power dissipation and, therefore, the load current. Equation 20 shows the relationships between the important parameters. Larger ambient temperatures (TA) and larger values of RθJA reduce the Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 25 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 maximum available output current. The converter efficiency can be estimated by using the curves provided in this data sheet. Note that these curves include the power loss in the inductor. If the desired operating conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency. Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly. The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal Metrics application report, the value of RθJA given in the Thermal Information is not valid for design purposes and must not be used to estimate the thermal performance of the application. The values reported in that table were measured under a specific set of conditions that are rarely obtained in an actual application. The data given for RθJC(bott) and ΨJT can be useful when determining thermal performance. See the Semiconductor and IC Package Thermal Metrics application report for more information and the resources given at the end of this section. IOUT MAX TJ TA 1 K ˜ ˜ R TJA 1 K VOUT (20) where • η is efficiency. The effective RθJA is a critical parameter and depends on many factors such as the following: • • • • • • Power dissipation Air temperature or flow PCB area Copper heat-sink area Number of thermal vias under the package Adjacent component placement The LM5013 features a die attach paddle, or "thermal pad" (EP), to provide a place to solder down to the PCB heat-sinking copper, which provides a good heat conduction path from the regulator junction to the heat sink and must be properly soldered to the PCB heat sink copper. Typical examples of RΘJA can be found in Figure 9-15. The copper area given in the graph is for each layer. The top and bottom layers are 2-oz. copper each, while the inner layers are 1 oz. Remember that the data given in this graph is for illustration purposes only, and the actual performance in any given application depends on all of the previously mentioned factors. 65 2L 4L 60 55 RθJA (C/W) 50 45 40 35 30 25 20 15 0 10 20 30 40 50 60 Copper Area (cm 2) 70 80 90 100 110 Figure 9-15. Typical RΘJA vs Copper Area To continue with the design example, assume that the user has an ambient temperature of 70ºC and wishes to estimate the required copper area to keep the device junction temperature below 125ºC, at full load. From 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 the curves in Application Curves, an efficiency of about 92% was found at an input voltage of 48 V with output of 12 V with 1.75-A load. The efficiency is somewhat less at high junction temperatures, so an efficiency of approximately 90% is assumed, which gives a total loss of approximately 2.3 W. Subtracting out the conduction loss alone for the inductor and catch diode, the user arrives at a device dissipation of approximately 1.54 W. With this information, the user can calculate the required RθJA of about 30ºC/W. Based on Figure 9-15, the required copper area is approximately 40 cm2 for a two-layer PCB. Engineering best judgment is to be used if using a lossy inductor, diode, or both, in the application, as their large losses can contribute to localized heating of the component, as well, the nearby regulator. As an example, biasing the Schottky diode (DSW) with 1.3-A continuous current (average current for 1.75-A load current) results in approximately 10°C rise in the case temperature of the regulator, which must be "buffered" for in the ambient temperature used in the previous calculation. For more details on these calculations, please see the PCB Thermal Design Tips for Automotive DC/DC Converters application note. The following resources can be used as a guide to optimal thermal PCB design and estimating RθJA for a given application environment: • • • • • Semiconductor and IC Package Thermal Metrics application report AN-2020 Thermal Design By Insight, Not Hindsight application report A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application report Using New Thermal Metrics application report PCB Thermal Design Tips for Automotive DC/DC Converters application report Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 27 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 10 Device and Documentation Support 10.1 Device Support 10.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 10.1.2 Development Support • • • • LM5013-Q1 Quickstart Calculator LM5013-Q1 Simulation Models TI Reference Design Library Technical Articles: – Use a Low-quiescent-current Switcher for High-voltage Conversion – How a DC/DC Converter Package and Pinout Design Can Enhance Automotive EMI Performance 10.1.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the LM5013 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 10.2 Documentation Support 10.2.1 Related Documentation For related documentation see the following: • Texas Instruments, LM5012/3/4/3/4-Q1EVM-041 EVM user's guide • Texas Instruments, Selecting an Ideal Ripple Generation Network for Your COT Buck Converter application report • Texas Instruments, Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding Applications white paper • Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies white paper • Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies white paper • Texas Instruments, 24-V AC Power Stage with Wide VIN Converter and Battery Gauge for Smart Thermostat design guide • Texas Instruments, Accurate Gauging and 50-μA Standby Current, 13S, 48-V Li-ion Battery Pack Reference design guide • Texas Instruments, AN-2162: Simple Success with Conducted EMI from DC/DC Converters application report • Texas Instruments, Automotive Cranking Simulator user's guide • Texas Instruments, Powering Drones with a Wide VIN DC/DC Converter application report • Texas Instruments, Using New Thermal Metrics application report • Texas Instruments, Semiconductor and IC Package Thermal Metrics application report 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 LM5013 www.ti.com SNVSCB3 – OCTOBER 2022 10.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.5 Trademarks PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5013 29 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) LM5013DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 150 L5013C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of