LM5017EVAL/NOPB

User's Guide SNVA612B – January 2012 – Revised April 2013 AN-2200 LM5017 Evaluation Board 1 Introduction The LM5017 evaluation board provides the design engineer with a fully functional buck regulator, employing the constant on-time (COT) operating principle. This evaluation board provides a 10 V output over an input range of 12.5 V to 100 V. The board’s specifications are: • Input Range: 12.5 V to 95 V, transients up to 100 V (absolute maximum) • Output Voltage: 10 V • Output Current: 600 mA • Nominal Switching Frequency ~ 200 kHz • Measured Efficiency: 92.4% at 400 mA and VIN = 24 V • Board size: 2.95 in. x 1.8 in. Figure 1. Evaluation Board (Top View) All trademarks are the property of their respective owners. SNVA612B – January 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated AN-2200 LM5017 Evaluation Board 1 Theory of Operation 2 www.ti.com Theory of Operation When the circuit is in regulation, the buck switch is turned on each cycle for a time determined by R3 and VIN according to Equation 1: TON = 10 -10 x R3 VIN (1) The on-time of this evaluation board ranges from 5.56 µs at VIN = 12 V to 702 ns at VIN = 95 V. The ontime varies inversely with input voltage. At the end of each on-time, the buck switch is off for at least 144 ns. In normal operation, the off-time is much longer. During the off-time, the load current is supplied by the output capacitor (C9). When the output voltage falls sufficiently that the voltage at FB is below 1.225 V, the regulation comparator initiates a new on-time period. For stable, fixed frequency operation, a minimum of 25 mV of ripple is required at FB to switch the regulation comparator. For a more detailed block diagram and a complete description of the various functional blocks, see the LM5017 100V, 600mA Constant On-Time Synchronous Buck Regulator Data Sheet (SNVS783). 3 UVLO The UVLO resistors (R5, R7) are selected using Equation 2: VIN(HYS) = IHYSR5 (2) and Equation 3: VIN (UVLO,rising) = 1.225V x § R5 © R7 +1· ¹ (3) On this evaluation board, R5 = 127 kΩ and R7 = 14.0 kΩ, resulting in UVLO rising threshold at VIN = 12 V and a hysteresis of 2.5 V. Figure 2 shows the evaluation board schematic. SW (TP6) 12V-100V VIN (TP1) C4 2.2 F LM5017 2 + C4 + R5 0.47 F 127 NŸ GND (TP2) (TP4) UVLO/SD 4 R3 499 NŸ 3 BST VIN SW RON 7 0.01 F + C1 8 0Ÿ R8 VOUT (TP3) R4 46.4 NŸ UVLO VCC R7 14 NŸ FB EXP 220 H L1 RTN 1 6 3300 pF C8 0.1 F R1 6.98 NŸ D2 5 + U1 C6 R2 0Ÿ C2 + C9 22 F R6 1 NŸ C7 1 F GND (TP5) Figure 2. Complete Evaluation Board Schematic for LM5017-Based Buck Converter 4 Board Connection and Start-up The input connections are made to the TP1 (VIN) and TP2 (GND) terminals. The load is connected to the TP3 (VOUT) AND TP5 (GND) terminals. Ensure the wires are adequately sized for the intended load current. Before start-up, a voltmeter should be connected to the input and output terminals. The load current should be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased gradually to 12 V, at which time the output voltage should be 10 V. If the output voltage is correct, increase the input voltage as desired and proceed with evaluating the circuit. DO NOT EXCEED 100 V AT VIN. 2 AN-2200 LM5017 Evaluation Board SNVA612B – January 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Board Connection and Start-up www.ti.com Table 1. Bill of Materials (BOM) Item Description U1 Sync Switching Regulator Package Value Texas Instruments, LM5017 SO PowerPAD-8 100 V, 0.6A Wurth, 7447714221 10 mm x 10 mm 220 µH, 1.2A Alternate Inductor Bourns, SRR1260–221k 12.5 mm x 12.5 mm 220 µH, 1.38A Alternate Inductor Coilcraft, MSS1246–224K 12.3 mm x 12.3 mm 220 µH, 1.4A Central Semi, CMMSH1–40 SOD-123F 40 V, 1A NXP, BAS40H, 115 SOD123F 40 V, 120 mA Ceramic Capacitor Murata, GRM188R71C103KA01D 0603 0.01 µF, 16V, X7R C4 Ceramic Capacitor Murata, GRM32ER72A225KA35L 1210 2.2 µF, 100 V, X7R C5 Ceramic Capacitor Murata, GRM21BR72A474KA73L 0805 0.47 µF, 100 V, X7R C6 Ceramic Capacitor TDK, C1608X7R1H332K 0603 3300 pF, 50 V, X7R C7 Ceramic Capacitor TDK, C2012X7R1C105K 0805 1 µF, 16 V, X7R C8 Ceramic Capacitor Murata, GRM188R71E104KA01D 0603 0.1 uF, 25 V, X7R C9 Ceramic Capacitor Murata, GRM32ER71E226KE15L 1210 22 uF, 25 V, X7R 6.98k Ω, 1% Inductor Mfg. Part Number L1 D2 Diode Alternate Diode C1 C2 NA R1 Resistor Vishay–Dale, CRCW08056K98FKEA 0805 R2 Resistor Panasonic, ERJ-6GEY0R00V 0805 0Ω R3 Resistor Panasonic, ERJ-6ENF4993V 0805 499k Ω, 1% R4 Resistor Panasonic, ERJ-3EKF4642V 0603 46.4k Ω, 1% R5 Resistor Vishay-Dale, CRCW0805127KFKEA 0805 127k Ω, 1% R6 Resistor Vishay-Dale, CRCW08051K00FKEA 0805 1.0k Ω, 1% R7 Resistor Vishay-Dale, CRCW080514K0FKEA 0805 14.0k Ω, 1% R8 Resistor Yageo, RC1206JR-070RL 1206 0Ω SNVA612B – January 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated AN-2200 LM5017 Evaluation Board 3 Ripple Configuration 5 www.ti.com Ripple Configuration The LM5017 is a COT buck and requires adequate ripple at feedback (FB) node. Three commonly used ripple generation methods are shown in Table 2. LM5017 evaluation board has been supplied with minimum ripple configuration (Type 3), but can be configured to Type 1 or Type 2 with modifications as suggested in Table 2. Table 2. Ripple Configuration Type 1 Lowest Cost Configuration Type 2 Reduced Ripple Configuration VOUT Type 3 Minimum Ripple Configuration VOUT L1 VOUT L1 L1 Cac R FB2 R FB2 RC To FB R FB1 R FB1 GND 40 mV VOUT x ûIL(MIN) VREF C OUT To FB R FB1 GND 5 gSW (R1 || R6) 40 mV R2 > ûIL R2 = 0 Ω. Select R4, C6, and C8: C8 > (4) R FB2 GND C OUT R4 open, C6 = 0 Ω. Select R2 and C8: R4, C6, C8 open. Select R2: Cr Cac To FB C OUT R2 > Rr RC (5) C6 = 3300 pF C8 = 100 nF (V ± VOUT)TON R4 x C6 < IN(MIN) 40 mV (6) 4 AN-2200 LM5017 Evaluation Board SNVA612B – January 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Performance Curves www.ti.com 6 Performance Curves Figure 3. Efficiency vs Load Current Figure 4. Frequency vs Input Voltage Figure 5. Typical Switching Waveform (VIN = 48 V, Iout = 200 mA) SNVA612B – January 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated AN-2200 LM5017 Evaluation Board 5 PC Board Layout 7 www.ti.com PC Board Layout Figure 6. Board Silkscreen Figure 7. Board Top Layer 6 AN-2200 LM5017 Evaluation Board SNVA612B – January 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated PC Board Layout www.ti.com Figure 8. Board Bottom Layer SNVA612B – January 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated AN-2200 LM5017 Evaluation Board 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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