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LM5017
SNVS783H – JANUARY 2012 – REVISED DECEMBER 2014
LM5017 100-V, 600-mA Constant On-Time Synchronous Buck Regulator
1 Features
3 Description
•
•
The LM5017 is a 100-V, 600-mA synchronous stepdown regulator with integrated high side and low side
MOSFETs. The constant on-time (COT) control
scheme employed in the LM5017 requires no loop
compensation, provides excellent transient response,
and enables very high step-down ratios. The on-time
varies inversely with the input voltage resulting in
nearly constant frequency over the input voltage
range. A high voltage startup regulator provides bias
power for internal operation of the IC and for
integrated gate drivers.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide 7.5-V to 100-V Input Range
Integrated 100-V High-Side,
and Low-Side Switches
No Schottky Required
Constant On-Time Control
No Loop Compensation Required
Ultra-Fast Transient Response
Nearly Constant Operating Frequency
Intelligent Peak Current Limit
Adjustable Output Voltage From 1.225 V
Precision 2% Feedback Reference
Frequency Adjustable to 1 MHz
Adjustable Undervoltage Lockout (UVLO)
Remote Shutdown
Thermal Shutdown
Packages:
– WSON-8
– SO PowerPAD™-8
A peak current limit circuit protects against overload
conditions. The undervoltage lockout (UVLO) circuit
allows the input undervoltage threshold and
hysteresis to be independently programmed. Other
protection features include thermal shutdown and
bias supply undervoltage lockout (VCC UVLO).
The LM5017 device is available in WSON-8 and
HSOP PowerPAD-8 plastic packages.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
LM5017
Smart Power Meters
Telecommunication Systems
Automotive Electronics
Isolated Bias Supply
PACKAGE
BODY SIZE (NOM)
SO PowerPAD (8)
4.89 mm × 3.90 mm
WSON (8)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
LM5017
CIN
2
+
4
RUV2
RON
SD
3
BST
VIN
SW
RON
+
8
CBST
L1
VOUT
CVCC
VCC
UVLO
FB
RUV1
7
RTN
1
+
7.5V-100V
VIN
6
RFB2
5
RC
+
RFB1
COUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5017
SNVS783H – JANUARY 2012 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes ....................................... 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision G (December 2013) to Revision H
Page
•
Added package designators to pin out drawings. ................................................................................................................. 3
•
Changed Thermal Information table. ..................................................................................................................................... 4
•
Added D1 to Figure 12 ......................................................................................................................................................... 13
•
Updated the calculation for K from 10-10 to 10-11 .................................................................................................................. 15
•
Changed Series Ripple Resistor RC section to Type III Ripple Circuit ................................................................................ 16
Changes from Revision F (September 2013) to Revision G
Page
•
Changed formatting throughout document to the TI standard ............................................................................................... 1
•
Changed minimum operating input voltage from 9 V to 7.5 V in Features ........................................................................... 1
•
Changed minimum operating input voltage from 9 V to 7.5 V in Typical Application ........................................................... 1
•
Changed minimum operating input voltage from 9 V to 7.5 V in Pin Descriptions ............................................................... 3
•
Added Maximum Junction Temperature................................................................................................................................. 4
•
Changed minimum operating input voltage from 9 V to 7.5 V in Recommended Operating Conditions .............................. 4
Changes from Revision E (July 2013) to Revision F
•
2
Page
Added SW to RTN (100 ns transient) to Absolute Maximum Ratings ................................................................................... 4
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5 Pin Configuration and Functions
8-Pin SO PowerPAD
DDA Package
Top View
RTN
1
VIN
2
UVLO
3
RON
4
SO
PowePAD-8
Exp Pad
8
SW
7
BST
6
VCC
5
FB
8-Pin WSON
NGU Package
Top View
RTN
1
VIN
2
UVLO
3
RON
4
8 SW
WSON-8
Exp Pad
7 BST
6 VCC
5 FB
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
APPLICATION INFORMATION
1
RTN
—
Ground
Ground connection of the integrated circuit.
2
VIN
I
Input Voltage
Operating input range is 7.5 V to 100 V.
Resistor divider from VIN to UVLO to GND programs the
undervoltage detection threshold. An internal current source is
enabled when UVLO is above 1.225 V to provide hysteresis. When
UVLO pin is pulled below 0.66 V externally, the regulator is in
shutdown mode.
3
UVLO
I
Input Pin of Undervoltage
Comparator
4
RON
I
On-Time Control
A resistor between this pin and VIN sets the buck switch on-time as
a function of VIN. Minimum recommended on-time is 100 ns at max
input voltage.
5
FB
I
Feedback
This pin is connected to the inverting input of the internal regulation
comparator. The regulation level is 1.225 V.
6
VCC
O
Output from the Internal High
Voltage Series Pass Regulator.
Regulated at 7.6 V
The internal VCC regulator provides bias supply for the gate drivers
and other internal circuitry. A 1.0 μF decoupling capacitor is
recommended.
7
BST
I
Bootstrap Capacitor
An external capacitor is required between the BST and SW pins
(0.01-μF ceramic). The BST pin capacitor is charged by the VCC
regulator through an internal diode when the SW pin is low.
8
SW
O
Switching Node
Power switching node. Connect to the output inductor and
bootstrap capacitor.
EP
—
Exposed Pad
Exposed pad must be connected to the RTN pin. Solder to the
system ground plane on application board for reduced thermal
resistance.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
VIN, UVLO to RTN
–0.3
100
V
SW to RTN
–1.5
VIN +0.3
V
–5
VIN +0.3
V
BST to VCC
100
V
BST to SW
13
V
SW to RTN (100 ns transient)
RON to RTN
–0.3
100
V
VCC to RTN
–0.3
13
V
FB to RTN
–0.3
5
V
200
°C
150
°C
150
°C
Lead Temperature
(2)
Maximum Junction Temperature (3)
Storage temperature, Tstg
(1)
(2)
(3)
–55
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are
conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the
Electrical Characteristics . The RTN pin is the GND reference electrically connected to the substrate.
For detailed information on soldering plastic SO PowerPAD package, refer to Absolute Maximum ratings for Soldering (SNOA549).
Maximum solder time not to exceed 4 seconds.
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VIN Voltage (1)
Operating Junction Temperature
(1)
(2)
(2)
MIN
MAX
UNIT
7.5
100
V
–40
125
°C
Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test conditions,
see Electrical Characteristics .
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C
6.4 Thermal Information
LM5017
THERMAL METRIC
(1)
NGU
DDA
8 PINS
8 PINS
41.3
41.1
RθJA
Junction-to-ambient thermal resistance
RθJCbot
Junction-to-case (bottom) thermal resistance
3.2
2.4
ΨJB
Junction-to-board thermal characteristic parameter
19.2
24.4
RθJB
Junction-to-board thermal resistance
19.1
30.6
RθJCtop
Junction-to-case (top) thermal resistance
34.7
37.3
ΨJT
Junction-to-top thermal characteristic parameter
0.3
6.7
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range, unless otherwise stated. VIN = 48 V unless otherwise stated. See (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.25
7.6
8.55
UNIT
VCC SUPPLY
VCC Reg
VCC Regulator Output
VIN = 48 V, ICC = 20 mA
VCC Current Limit
VIN = 48 V (2)
VCC Undervoltage Lockout
Voltage (VCC increasing)
–40 ≤ TJ ≤ 125
26
4.15
VCC Undervoltage Hysteresis
V
mA
4.5
4.9
300
V
mV
VCC Drop Out Voltage
VIN = 9 V, ICC = 20 mA
2.3
IIN Operating Current
Non-Switching, FB = 3 V
V
1.75
mA
IIN Shutdown Current
UVLO = 0 V
50
225
µA
Buck Switch RDS(ON)
ITEST = 200 mA, BST-SW = 7 V
0.8
1.8
Ω
Synchronous RDS(ON)
ITEST = 200 mA
0.45
1
Ω
Gate Drive UVLO
VBST − VSW Rising
3
3.6
SWITCH CHARACTERISTICS
2.4
Gate Drive UVLO Hysteresis
260
V
mV
CURRENT LIMIT
Current Limit Threshold
–40°C ≤ TJ ≤ 125°C
Current Limit Response Time
Time to Switch Off
OFF-Time Generator (Test 1)
OFF-Time Generator (Test 2)
0.7
1.02
1.3
A
150
ns
FB = 0.1 V, VIN = 48 V
12
µs
FB = 1.0 V, VIN = 48 V
2.5
µs
REGULATION AND OVERVOLTAGE COMPARATORS
FB Regulation Level
Internal Reference Trip Point for
Switch ON
FB Overvoltage Threshold
Trip Point for Switch OFF
1.2
FB Bias Current
1.225
1.25
V
1.62
V
60
nA
UNDERVOLTAGE SENSING FUNCTION
UV Threshold
UV Rising
1.19
1.225
1.26
V
UV Hysteresis Input Current
UV = 2.5 V
–10
–20
–29
µA
Remote Shutdown Threshold
Voltage at UVLO Falling
0.32
0.66
V
110
mV
165
°C
20
°C
Remote Shutdown Hysteresis
THERMAL SHUTDOWN
Tsd
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
(1)
(2)
All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
6.6 Timing Requirements
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. VIN = 48 V unless otherwise stated.
MIN
NOM
MAX
UNIT
ON-TIME GENERATOR
TON Test 1
VIN = 32 V, RON = 100 k
270
350
460
ns
TON Test 2
VIN = 48 V, RON = 100 k
188
250
336
ns
TON Test 3
VIN = 75 V, RON = 250 k
250
370
500
ns
TON Test 4
VIN = 10 V, RON = 250 k
1880
3200
4425
ns
MINIMUM OFF-TIME
Minimum Off-Timer
FB = 0 V
144
ns
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6.7 Typical Characteristics
6
Figure 1. Efficiency at 200 kHz, 10 V
Figure 2. VCC vs VIN
Figure 3. VCC vs ICC
Figure 4. ICC vs External VCC
Figure 5. TON vs VIN and RON
Figure 6. TOFF (ILIM) vs VFB and VIN
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Typical Characteristics (continued)
Figure 7. IIN vs VIN (Operating, Non-Switching)
Figure 8. IIN vs VIN (Shutdown)
Figure 9. Switching Frequency vs VIN
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7 Detailed Description
7.1 Overview
The LM5017 step-down switching regulator features all the functions needed to implement a low cost, efficient,
buck converter capable of supplying up to 0.6 A to the load. This high voltage regulator contains 100-V, Nchannel buck and synchronous switches, is easy to implement, and is provided in thermally enhanced HSOP
PowerPAD-8 and WSON-8 packages. The regulator operation is based on a constant on-time control scheme
using an on-time inversely proportional to VIN. This control scheme does not require loop compensation. The
current limit is implemented with a forced off-time inversely proportional to VOUT. This scheme ensures short
circuit protection while providing minimum foldback.
The LM5017 can be applied in numerous applications to efficiently regulate down higher voltages. This regulator
is well suited for 48-V telecom and automotive power bus ranges. Protection features include: thermal shutdown,
Undervoltage Lockout (UVLO), minimum forced off-time, and an intelligent current limit.
7.2 Functional Block Diagram
LM5017
START-UP
REGULATOR
VIN
VCC
V UVLO
20 µA
4.5V
UVLO
THERMAL
SHUTDOWN
UVLO
1.225V
SD
VDD REG
BST
0.66V
SHUTDOWN
BG REF
VIN
DISABLE
ON/OFF
TIMERS
RON
1.225V
SW
COT CONTROL
LOGIC
FEEDBACK
FB
ILIM
COMPARATOR
OVER-VOLTAGE
1.62V
CURRENT
LIMIT
ONE-SHOT
RTN
8
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VILIM
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7.3 Feature Description
7.3.1 Control Overview
The LM5017 buck regulator employs a control principle based on a comparator and a one-shot on-timer, with the
output voltage feedback (FB) compared to an internal reference (1.225 V). If the FB voltage is below the
reference the internal buck switch is turned on for the one-shot timer period, which is a function of the input
voltage and the programming resistor (RON). Following the on-time the switch remains off until the FB voltage
falls below the reference, but never before the minimum off-time forced by the minimum off-time one-shot timer.
When the FB pin voltage falls below the reference and the minimum off-time one-shot period expires, the buck
switch is turned on for another on-time one-shot period. This will continue until regulation is achieved and the FB
voltage is approximately equal to 1.225 V (typ).
In a synchronous buck converter, the low side (sync) FET is ‘on’ when the high side (buck) FET is ‘off’. The
inductor current ramps up when the high side switch is ‘on’ and ramps down when the high side switch is ‘off’.
There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative
direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of
the output loading. The operating frequency remains relatively constant with load and line variations. The
operating frequency can be calculated as shown in Equation 1.
VOUT
gSW =
K x RON
(1)
Where:
K = 9 x 10–11
The output voltage (VOUT) is set by two external resistors (RFB1, RFB2). The regulated output voltage is calculated
as shown in Equation 2.
RFB2 + RFB1
VOUT = 1.225V x
RFB1
(2)
This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor (COUT). A minimum of 25 mV of ripple voltage at the feedback pin (FB) is
required for the LM5017. In cases where the capacitor ESR is too small, additional series resistance may be
required (RC in Figure 10).
For applications where lower output voltage ripple is required the output can be taken directly from a low ESR
output capacitor, as shown in Figure 10. However, RC slightly degrades the load regulation.
L1
VOUT
SW
LM5017
RFB2
FB
RC
+
RFB1
COUT
VOUT
(low ripple)
Figure 10. Low Ripple Output Configuration
7.3.2 VCC Regulator
The LM5017 device contains an internal high voltage linear regulator with a nominal output of 7.6 V. The input
pin (VIN) can be connected directly to the line voltages up to 100 V. The VCC regulator is internally current limited
to 30 mA. The regulator sources current into the external capacitor at VCC. This regulator supplies current to
internal circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the
VCC pin reaches the undervoltage lockout (VCC UVLO) threshold of 4.5 V, the IC is enabled.
An internal diode connected from VCC to the BST pin replenishes the charge in the gate drive bootstrap capacitor
when SW pin is low.
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Feature Description (continued)
At high input voltages, the power dissipated in the high voltage regulator is significant and can limit the overall
achievable output power. As an example, with the input at 48 V and switching at high frequency, the VCC
regulator may supply up to 7 mA of current resulting in 48 V × 7 mA = 336 mW of power dissipation. If the VCC
voltage is driven externally by an alternate voltage source between 8.55 V and 14 V, the internal regulator is
disabled. This reduces the power dissipation in the IC.
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 1.225 V reference. In normal operation, when the output
voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225 V. The high side
switch will stay on for the on-time, causing the FB voltage to rise above 1.225 V. After the on-time period, the
high side switch will stay off until the FB voltage again falls below 1.225 V. During start-up, the FB voltage will be
below 1.225 V at the end of each on-time, causing the high side switch to turn on immediately after the minimum
forced off-time of 144 ns. The high side switch can be turned off before the on-time is over if the peak current in
the inductor reaches the current limit threshold.
7.3.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 1.62 V reference. If the voltage at FB rises above 1.62 V
the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load
changes suddenly. The high side switch will not turn on again until the voltage at FB falls below 1.225 V.
7.3.5 On-Time Generator
The on-time for the LM5017 device is determined by the RON resistor and is inversely proportional to the input
voltage (VIN), resulting in a nearly constant frequency as VIN is varied over the operating range. The on-time for
the LM5017 can be calculated using Equation 3.
10-10 x RON
TON =
VIN
(3)
See Figure 5. RON should be selected for a minimum on-time (at maximum VIN) greater than 100 ns for proper
operation. This requirement limits the maximum switching frequency for high VIN.
7.3.6 Current Limit
The LM5017 device contains an intelligent current limit off-timer. If the current in the buck switch exceeds 1.02 A,
the present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of the off-time is
controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0 V and VIN = 48 V, the offtime is set to 16 μs. This condition occurs when the output is shorted and during the initial part of start-up. This
VIN dependent off-time ensures safe short circuit operation up to the maximum input voltage of 100 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is
reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and
start-up time. The off-time is calculated from Equation 4.
0.07 x VIN
Ps
TOFF(ILIM) =
VFB + 0.2V
(4)
The current limit protection feature is peak limited. The maximum average output current will be less than the
peak.
7.3.7 N-Channel Buck Switch and Driver
The LM5017 device integrates an N-Channel Buck switch and associated floating high voltage gate driver. The
gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A
0.01 uF ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the driver
during the on-time. During each off-time, the SW pin is at approximately 0 V, and the bootstrap capacitor charges
from VCC through the internal diode. The minimum off-timer, set to 144 ns, ensures a minimum time each cycle to
recharge the bootstrap capacitor.
10
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Feature Description (continued)
7.3.8 Synchronous Rectifier
The LM5017 provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a path for
the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous
conduction mode even with light loads which would otherwise result in discontinuous operation.
7.3.9 Undervoltage Detector
The LM5017 device contains a dual level undervoltage lockout (UVLO) circuit. A summary of threshold voltages
and operational states is provided in Device Functional Modes . When the UVLO pin voltage is below 0.66 V, the
regulator is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66V but less than
1.225 V, the regulator is in standby mode. In standby mode the VCC bias regulator is active while the regulator
output is disabled. When the VCC pin exceeds the VCC undervoltage threshold and the UVLO pin voltage is
greater than 1.225 V, normal operation begins. An external set-point voltage divider from VIN to GND can be
used to set the minimum operating voltage of the regulator.
UVLO hysteresis is accomplished with an internal 20-μA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance
RUV2.
If the UVLO pin is connected directly to the VIN pin, the regulator will begin operation once the VCC undervoltage
is satisfied.
VIN
CIN
2
VIN
+
RUV2
LM5017
3
UVLO
RUV1
Figure 11. UVLO Resistor Setting
7.3.10 Thermal Protection
The LM5017 device should be operated so the junction temperature does not exceed 150°C during normal
operation. An internal Thermal Shutdown circuit is provided to protect the LM5017 in the event of a higher than
normal junction temperature. When activated, typically at 165°C, the regulator is forced into a low power reset
state, disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental
device overheating. When the junction temperature falls below 145°C (typical hysteresis = 20°C), the VCC
regulator is enabled, and normal operation is resumed.
7.3.11 Ripple Configuration
LM5017 uses Constant-On-Time (COT) control in which the on-time is terminated by an on-timer and the off-time
is terminated by the feedback voltage (VFB) falling below the reference voltage (VREF). Therefore, for stable
operation, the feedback voltage must decrease monotonically, in phase with the inductor current during the offtime. Furthermore, this change in feedback voltage (VFB) during off-time must be larger than any noise
component present at the feedback node.
Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1
and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output
voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.
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Feature Description (continued)
The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output
node (VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This
triangular ramp is ac coupled using Cac to the feedback node (FB). Since this circuit does not use the output
voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See AN-1481
Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs
(SNVA166) for more details for each ripple generation method.
Table 1. Ripple Configuration
TYPE 1
LOWEST COST CONFIGURATION
TYPE 2
REDUCED RIPPLE CONFIGURATION
VOUT
TYPE 3
MINIMUM RIPPLE CONFIGURATION
VOUT
L1
VOUT
L1
L1
R FB2
Cac
R FB2
RC
To FB
C OUT
COUT
R FB2
GND
R FB1
GND
25 mV VOUT
x
ûIL(MIN) VREF
Cr
Cac
To FB
R FB1
RC >
Rr
RC
C OUT
To FB
R FB1
GND
C>
(5)
5
gsw(RFB2||RFB1)
25 mV
RC >
ûIL(MIN)
(6)
Cr = 3300 pF
Cac = 100 nF
(VIN(MIN) - VOUT) x TON
RrCr <
25 mV
(7)
7.3.12 Soft-Start
A soft-start feature can be implemented with the LM5017 using an external circuit. As shown in Figure 12, the
soft-start circuit consists of one capacitor, C1, two resistors, R1 and R2, and a diode, D. During the initial start-up,
the VCC voltage is established prior to the VOUT voltage. Capacitor C1 is discharged and D is thereby forward
biased to pull up the FB voltage. The FB voltage exceeds the reference voltage (1.225 V) and switching is
therefore disabled. As capacitor C1 charges, the voltage at node B gradually decreases and switching
commences. VOUT will gradually rise to maintain the FB voltage at the reference voltage. Once the voltage at
node B is less than a diode drop above FB voltage, the soft-start is finished and D is reverse biased.
During the initial part of the start-up, the FB voltage can be approximated as follows. Please note that the effect
of R1 has been ignored to simplify the calculation shown in Equation 8.
RFB1 x RFB2
VFB = (VCC - VD) x
R2 x (RFB1 + RFB2) + RFB1 x RFB2
(8)
C1 is charged after the first start up. Diode D1 is optional and can be added to discharge C1 when the input
voltage experiences a momentary drop to initialize the soft-start sequence.
To achieve the desired soft-start, the following design guidance is recommended:
(1) R2 is selected so that VFB is higher than 1.225 V for a VCC of 4.5 V, but is lower than 5 V when VCC is 8.55 V.
If an external VCC is used, VFB should not exceed 5 V at maximum VCC.
(2) C1 is selected to achieve the desired start-up time that can be determined from Equation 9.
RFB1 x RFB2
)
tS = C1 x (R2 +
RFB1 + RFB2
12
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(3) R1 is used to maintain the node B voltage at zero after the soft-start is finished. A value larger than the
feedback resistor divider is preferred. Note that the effect of R1 is ignored in the previous equations.
Based on the schematic shown in Figure 13, selecting C1 = 1 uF, R2 = 1 kΩ, R1 = 30 kΩ results in a soft-start
time of about 2 ms.
VOUT
VCC
C1
RFB2
R2
To FB
D
D1
B
RFB1
R1
Figure 12. Soft-Start Circuit
7.4 Device Functional Modes
Table 2. UVLO Modes
UVLO
VCC Regulator
MODE
DESCRIPTION
< 0.66 V
Disabled
Shutdown
VCC regulator disabled.
Switching disabled.
0.66 V – 1.225 V
Enabled
Standby
VCC regulator enabled
Switching disabled.
VCC < 4.5 V
Standby
VCC regulator enabled.
Switching disabled.
VCC > 4.5 V
Operating
> 1.225 V
VCC enabled.
Switching enabled.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5017 device is step-down dc-dc converter. The device is typically used to convert a higher dc voltage to a
lower dc voltage with a maximum available output current of 650 mA. Use the following design procedure to
select component values for the LM5017 device. Alternately, use the WEBENCH® software to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Application
8.2.1 Application Circuit: 12.5-V to 95-V Input and 10-V, 600-mA Output Buck Converter
The application schematic of a buck supply is shown in Figure 13. For output voltage (VOUT) more than one diode
drop above the maximum regulation threshold of VCC (8.55 V, see Electrical Characteristics ), the VCC pin can be
connected to VOUT through a diode (D2), as shown in Figure 13, for higher efficiency and lower power dissipation
in the IC.
The design example below uses equations from the Feature Description with component names provided in the
Typical Application. Corresponding component designators from Figure 13 are also provided for each selected
value.
12.5 V±95 V
VIN
(TP1)
SW
(TP6)
LM5017
2
C5 +
C4 +
R5
127 N
2.2 F
0.47 F
GND
(TP2)
4
R3
499 N
3
BST
VIN
SW
RON
UVLO
R7
14 N
FB
EXP
220 H
L1
R4
46.4 N
VCC
(TP4)
UVLO/SD
7 0.01 F
+
C1
8
RTN
1
6
D2
5
+
U1
C7
1 F
0
R8
VOUT
(TP3)
R2
0
C6 3300 pF
C8
0.1 F
R1
6.98 N
R6
1 N
+
C9
22 F
GND
(TP5)
Figure 13. Final Schematic for 12.5-V to 95-V Input, and 10-V, 600-mA Output Buck Converter
8.2.1.1 Design Requirements
Selection of external components is illustrated through a design example. The design example specifications are
shown in Table 3.
Table 3. Buck Converter Design Specifications
14
DESIGN PARAMETERS
VALUE
Input voltage range
12.5 V to 95 V
Output voltage
10 V
Maximum Load current
600 mA
Switching Frequency
≈ 225 kHz
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 RFB1, RFB2
VOUT = VFB x (RFB2/RFB1 + 1), and since VFB = 1.225 V, the ratio of RFB2 to RFB1 calculates as 7:1. Standard
values are chosen with RFB2 = R1 = 6.98 kΩ and RFB1 = R6 = 1.00 kΩ. Other values could be used as long as
the 7:1 ratio is maintained.
8.2.1.2.2 Frequency Selection
At the minimum input voltage, the maximum switching frequency of LM5017 is restricted by the forced minimum
off-time (TOFF(MIN)) as given by Equation 10.
1 - DMAX
1 - 10/12.5
=
= 1 MHz
gSW(MAX) =
200 ns
TOFF(MIN)
(10)
Similarly, at maximum input voltage, the maximum switching frequency of LM5017 is restricted by the minimum
TON as given by Equation 11.
DMIN
10/95
gSW(MAX) =
=
= 1.05 MHz
TON(MIN) 100 ns
(11)
Resistor RON sets the nominal switching frequency based on Equation 12.
VOUT
gSW =
K x RON
(12)
Where:
K = 9 x 10–11
Operation at high switching frequency results in lower efficiency while providing the smallest solution. For this
example a conservative 225 kHz was selected, resulting in RON = 493 kΩ. A standard value for RON = R3 = 499
kΩ is selected.
8.2.1.2.3 Inductor Selection
The minimum inductance is selected to limit the output ripple to 15 to 40 percent of the maximum load current. In
addition, the peak inductor current at maximum load should be smaller than the minimum current limit as given in
Electrical Characteristics table.
The inductor current ripple is given by Equation 13.
VIN - VOUT VOUT
x
ûIL =
VIN
L1 x gSW
(13)
The maximum ripple is observed at maximum input voltage. Substituting VIN = 95 V and ΔIL = 40 percent × IOUT
(max) results in L1 = 198 μH. The next higher standard value of 220 μH is chosen. The peak-to-peak minimum
and maximum inductor current ripple are 40 mA and 181 mA at the minimum and maximum input voltages
respectively. The peak inductor and switch current is given by Equation 14.
ûIL(MAX)
ILI(peak) = IOUT +
= 690 mA
(14)
2
690 mA is less than the minimum current limit threshold of 0.7 A. The selected inductor should be able to
withstand the maximum current limit of 1.3 A during startup and overload conditions without saturating.
8.2.1.2.4 Output Capacitor
The output capacitor is selected to minimize the capacitive ripple across it. The maximum ripple is observed at
maximum input voltage and is given by:
ûIL
COUT =
8 x gsw x ûVripple
(15)
Where:
ΔVripple is the voltage ripple across the capacitor
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Assuming VIN = 95 V and substituting ΔVripple = 10 mV gives COUT = 10.1 μF. A 22-μF standard value is selected
for COUT = C9. An X5R or X7R type capacitor with a voltage rating 16 V or higher should be selected.
8.2.1.2.5 Type III Ripple Circuit
Type III ripple circuit as described in Ripple Configuration is chosen for this example. For a constant on-time
converter to be stable, the injected in-phase ripple should be larger than the capacitive ripple on COUT.
Using the type III ripple circuit equation, the target ripple will be greater than the capacitive ripple generated at
the primary output if the following condition is satisfied:
Cr = C6 = 3300 pF
Cac = C8 = 100 nF
(VIN(MIN) - VOUT ) ´ TON(VINMIN)
Rr £
(25mV ´ Cr )
(16)
For TON, refer to Equation 3.
Ripple resistor Rr is calculated to be 57.6 kΩ. This value provides the minimum ripple for stable operation. A
smaller resistance should be selected to allow for variations in TON, COUT, and other components. Rr = R4 = 46.4
kΩ is selected for this example application.
8.2.1.2.6 VCC and Bootstrap Capacitor
The VCC capacitor provides charge to bootstrap capacitor as well as internal circuitry and low side gate driver.
The Bootstrap capacitor provides charge to high side gate driver. The recommended value for CVCC = C7 = 1 μF.
A good value for CBST = C1 = 0.01 μF.
8.2.1.2.7 Input Capacitor
Input capacitor should be large enough to limit the input voltage ripple as shown in Equation 17.
IOUT(MAX)
CIN >
8 x gSW x ûVIN
(17)
Choosing a ΔVIN = 0.5 V gives a minimum CIN = 0.66 μF. A standard value of 2.2 μF is selected for CIN = C4 .
The input capacitor should be rated for the maximum input voltage under all conditions. A 100-V, X7R dielectric
should be selected for this design.
The input capacitor should be placed directly across VIN and RTN (pin 1 and 2) of the IC. If it is not possible to
place all of the input capacitor close to the IC, a 0.47-μF capacitor should be placed near the IC to provide a
bypass path for the high frequency component of the switching current.
8.2.1.2.8 UVLO Resistors
The UVLO resistors RFB1 and RFB2 set the UVLO threshold and hysteresis according to the relationship shown in
Equation 18 and Equation 19.
VIN(HYS) = IHYS x RUV2
(18)
VIN (UVLO,rising) = 1.225V x (
RUV2
+ 1)
RUV1
(19)
Where:
IHYS = 20 μA
Setting UVLO hysteresis of 2.5 V and UVLO rising threshold of 12 V results in RUV1 = 14.53 kΩ and
RUV2 = 125 kΩ. Selecting standard values of RUV1 = R7 = 14 kΩ and RUV2 = R5 = 127 kΩ results in UVLO
threshold and hysteresis of 12.4 V and 2.5 V respectively.
16
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8.2.1.3 Application Curves
Figure 14. Efficiency vs Load Current
Figure 15. Frequency vs Input Voltage
Figure 16. Typical Switching Waveform (Vin = 48 V, Iout = 200 mA
8.2.2 Isolated DC-DC Converter Using LM5017
An isolated supply using LM5017 is shown in Figure 17. Inductor (L) in a typical buck circuit is replaced with a
coupled inductor (X1). A diode (D1) is used to rectify the voltage on a secondary output. The nominal voltage at
the secondary output (VOUT2) is given by Equation 20.
N
VOUT2 = VOUT1 x S - VF
NP
(20)
Where:
VF is the forward voltage drop of D1
NP and NS are the number of turns on the primary and secondary of coupled inductor X1.
For output voltage (VOUT1) more than one diode drop above the maximum VCC (8.55 V), the VCC pin can be diode
connected to VOUT1 for higher efficiency and low dissipation in the IC. See AN-2204 (SNVA611) for a complete
isolated bias design with LM5017.
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VOUT2
D1
+
N2
X1
1:1
LM5017
BST
VIN
20V-95V
0.01 µF
+
CBST
N1
33 µH
VOUT1
SW
46.4 N 1 nF
Rr
Cr
VIN
+
CIN
2.2 µF
COUT2
1 µF
CBYP
0.47 µF
+
RON
RUV2
127 N
RON
130 N
0.1 µF
RUV1
8.25 N
RTN
COUT1
1 µF
RFB2
VCC
UVLO
+
Cac
D2
7.32 N
CVCC
1 µF
RFB1
1 N
FB
+
Figure 17. Typical Isolated Application Schematic
8.2.2.1 Design Requirements
DESIGN PARAMETERS
VALUE
Input Voltage Range
20 V – 100 V
Primary Output Voltage
10 V
Secondary (Isolated) Output Voltage
9.5 V
Maximum Load Current (Primary + Secondary)
300 mA
Maximum Power Output
3W
Nominal Switching Frequency
750 kHz
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Transformer Turns Ratio
The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary
(isolated) output voltage. In this design example, the two outputs are nearly equal and a 1:1 turns ratio
transformer is selected. Therefore, N2 / N1 = 1.
If the secondary (isolated) output voltage is significantly higher or lower than the primary output voltage, a turns
ratio less than or greater than 1 is recommended. The primary output voltage is normally selected based on the
input voltage range such that the duty cycle of the converter does not exceed 50% at the minimum input voltage.
This condition is satisfied if VOUT1 < VIN_MIN / 2.
8.2.2.2.2 Total IOUT
The total primary referred load current is calculated by multiplying the isolated output load(s) by the turns ratio of
the transformer as shown in Equation 21.
N2
IOUT(MAX) IOUT1 IOUT2 u
0.3 A
(21)
N1
18
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8.2.2.2.3 RFB1, RFB2
The feedback resistors are selected to set the primary output voltage. The selected value for RFB1 is 1 kΩ. RFB2
can be calculated using the following equations to set VOUT1 to the specified value of 10 V. A standard resistor
value of 7.32 kΩ is selected for RFB2.
VOUT1 = 1.225V x (1 +
RFB2
)
RFB1
(22)
VOUT1
- 1) x RFB1 = 7.16 k:
:RFB2 = (
1.225
(23)
8.2.2.2.4 Frequency Selection
Equation 24 is used to calculate the value of RON required to achieve the desired switching frequency.
VOUT1
f SW =
.x RON
(24)
–11
Where K = 9 × 10
For VOUT1 of 10 V and fSW of 750 kHz, the calculated value of RON is 148 kΩ. A lower value of 130 kΩ is selected
for this design to allow for second order effects at high switching frequency that are not included in Equation 24.
8.2.2.2.5 Transformer Selection
A coupled inductor or a flyback-type transformer is required for this topology. Energy is transferred from primary
to secondary when the low-side synchronous switch of the buck converter is conducting.
The maximum inductor primary ripple current that can be tolerated without exceeding the buck switch peak
current limit threshold (0.7 A minimum) is given by Equation 25.
N2 ·
§
'IL1 ¨ 0.7 IOUT1 IOUT2 u
u 2 0.8 A
N1 ¸¹
©
(25)
Using the maximum peak-to-peak inductor ripple current ΔIL1 from Equation 25, the minimum inductor value is
given by Equation 26.
VIN(MAX) VOUT
V
L1
14.9 PH
u OUT
VIN(MAX)
'IL1 u fSW
(26)
A higher value of 33 µH is selected to insure the high-side switch current does not exceed the minimum peak
current limit threshold. With this inductance, the inductor current ripple is ΔIL1= 0.36 A at the maximum VIN.
8.2.2.2.6 Primary Output Capacitor
In a conventional buck converter the output ripple voltage is calculated as shown in Equation 27.
f
'VOUT =
'IL1
x f x COUT1
(27)
To limit the primary output ripple voltage ΔVOUT1 to approximately 50 mV, an output capcitor COUT1 of 1.2 µF
would be required for a conventional buck.
Figure 18 shows the primary winding current waveform (IL1) of a Fly-Buck™ converter. The reflected secondary
winding current adds to the primary winding current during the buck switch off-time. Because of this increased
current, the output voltage ripple is not the same as in conventional buck converter. The output capacitor value
calculated in Equation 27 should be used as the starting point. Optimization of output capacitance over the entire
line and load range must be done experimentally. If the majority of the load current is drawn from the secondary
isolated output, a better approximation of the primary output voltage ripple is given by Equation 28.
N2 ö
æ
ç I OUT2 ´ N1 ÷ ´ TON(MAX)
ø
DVOUT1 = è
» 67mV
COUT1
(28)
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TON(MAX) x IOUT2 x N2/N1
IL1
IOUT2
IL2
TON(MAX) x IOUT2
Figure 18. Current Waveforms for COUT1 Ripple Calculation
A standard 1-µF, 25 V capacitor is selected for this design. If lower output voltage ripple is required, a higher
value should be selected for COUT1 and/or COUT2.
8.2.2.2.7 Secondary Output Capacitor
A simplified waveform for secondary output current (IOUT2) is shown in Figure 19.
IOUT2
IL2
TON(MAX) x IOUT2
Figure 19. Secondary Current Waveforms for COUT2 Ripple Calculation
The secondary output current (IOUT2) is sourced by COUT2 during on-time of the buck switch, TON. Ignoring the
current transition times in the secondary winding, the secondary output capacitor ripple voltage can be calculated
using Equation 29.
IOUT2 x TON (MAX)
'VOUT2 =
COUT2
(29)
For a 1:1 transformer turns ratio, the primary and secondary voltage ripple equations are identical. Therefore,
COUT2 is chosen to be equal to COUT1 (1 µF) to achieve comparable ripple voltages on primary and secondary
outputs.
If lower output voltage ripple is required, a higher value should be selected for COUT1 and/or COUT2.
8.2.2.2.8 Type III Feedback Ripple Circuit
Type III ripple circuit as described in Ripple Configuration is required for the Fly-Buck topology. Type I and Type
II ripple circuits use series resistance and the triangular inductor ripple current to generate ripple at VOUT and the
FB pin. The primary ripple current of a Fly-Buck is the combination or primary and reflected secondary currents
as illustrated in Figure 18. In the Fly-Buck topology, Type I and Type II ripple circuits suffer from large jitter as the
reflected load current affects the feedback ripple.
20
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VOUT
L1
Rr
Cac
C OUT
Cr
R FB2
GND
To FB
R FB1
Figure 20. Type III Ripple Circuit
Selecting the Type III ripple components using the equations from Ripple Configuration will ensure that the FB
pin ripple is be greater than the capacitive ripple from the primary output capacitor COUT1. The feedback ripple
component values are chosen as shown in Equation 30.
Cr = 1000 pF
Cac = 0.1 PF
RrCr d
(VIN (MIN) - VOUT) x TON
50 mV
(30)
The calculated value for Rr is 66 kΩ. This value provides the minimum ripple for stable operation. A smaller
resistance should be selected to allow for variations in TON, COUT1 and other components. For this design, Rr
value of 46.4 kΩ is selected.
8.2.2.2.9 Secondary Diode
The reverse voltage across secondary-rectifier diode D1 when the high-side buck switch is off can be calculated
using Equation 31.
VD1 =
N2
VIN
N1
(31)
For a VIN_MAX of 95 V and the 1:1 turns ratio of this design, a 100 V Schottky is selected.
8.2.2.2.10 VCC and Bootstrap Capacitor
A 1-µF capacitor of 16 V or higher rating is recommended for the VCC regulator bypass capacitor.
A good value for the BST pin bootstrap capacitor is 0.01-µF with a 16 V or higher rating.
8.2.2.2.11 Input Capacitor
The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a
larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a
desired amplitude. For input ripple voltage ΔVIN, CIN can be calculated using Equation 32.
I OUT(MAX)
CIN ³
4 ´ f ´ DVIN
(32)
Choosing a ΔVIN of 0.5 V gives a minimum CIN of 0.2 μF. A standard value of 0.47 μF is selected for CBYP in this
design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the power
source to the converter. A standard value of 2.2 μF is selected for for CIN in this design. The voltage ratings of
the two input capacitors should be greater than the maximum input voltage under all conditions.
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8.2.2.2.12 UVLO Resistors
UVLO resistors RUV1 and RUV2 set the undervoltage lockout threshold and hysteresis according to Equation 33
and Equation 34.
VIN (HYS) = IHYS x RUV2
(33)
VIN (UVLO, rising) = 1.225V x
R
( RUV2
+ 1)
(34)
UV1
Where IHYS = 20 μA, typical.
For a UVLO hysteresis of 2.5 V and UVLO rising threshold of 20 V, Equation 33 and Equation 34 require RUV1 of
8.25 kΩ and RUV2 of 127 kΩ and these values are selected for this design example.
8.2.2.2.13 VCC Diode
Diode D2 is an optional diode connected between VOUT1 and the VCC regulator output pin. When VOUT1 is more
than one diode drop greater than the VCC voltage, the VCC bias current is supplied from VOUT1. This results in
reduced power losses in the internal VCC regulator which improves converter efficiency. VOUT1 must be set to a
voltage at least one diode drop higher than 8.55 V (the maximum VCC voltage) if D2 is used to supply bias
current.
8.2.2.3 Application Curves
Figure 21. Steady State Waveform (VIN=48 V, IOUT1=100
mA, IOUT2=200 mA
Figure 22. Step Load Response (VIN=48 V, IOUT1=0, Step
Load on IOUT2=100 mA to 200 mA)
Figure 23. Efficiency at 750 kHz, VOUT1=10 V
22
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9 Power Supply Recommendations
LM5017 is a power management device. The power supply for the device is any dc voltage source within the
specified input range.
10 Layout
10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should
be observed:
1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore,
the input capacitor should be placed close to the IC, directly across VIN and RTN pins and the connections to
these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of
input capacitance near the IC. A good practice is to use a 0.1-μF or 0.47-μF capacitor directly across the VIN
and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Figure 24).
2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and
low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the
connecting trace length and loop area should be minimized (see Figure 24).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for
proper operation of LM5017. Therefore, care should be taken while routing the feedback trace to avoid
coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or
parallel to any other switching trace.
4. SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a possible
source of noise. The SW node area should be minimized. In particular, the SW node should not be
inadvertently connected to a copper plane or pour.
10.2 Layout Example
RTN
1
VIN
2
UVLO
3
RON
4
8
SW
7
BST
6
VCC
5
FB
CIN
SO
PowerPAD8
CVCC
Figure 24. Placement of Bypass Capacitors
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Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LM5017
23
LM5017
SNVS783H – JANUARY 2012 – REVISED DECEMBER 2014
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•
•
•
Absolute Maximum Ratings for Soldering (SNOA549)
AN-2204 LM5017 Isolated Supply Evaluation Board (SNVA611)
AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator
Designs (SNVA166)
11.2 Trademarks
PowerPAD, Fly-Buck are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: LM5017
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM5017MR/NOPB
ACTIVE SO PowerPAD
DDA
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
L5017
MR
LM5017MRE/NOPB
ACTIVE SO PowerPAD
DDA
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
L5017
MR
LM5017MRX/NOPB
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
L5017
MR
LM5017SD/NOPB
ACTIVE
WSON
NGU
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
L5017
LM5017SDX/NOPB
ACTIVE
WSON
NGU
8
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
L5017
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM5017MRE/NOPB
SO
Power
PAD
DDA
8
250
178.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5017MRX/NOPB
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5017SD/NOPB
WSON
NGU
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5017SDX/NOPB
WSON
NGU
8
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5017MRE/NOPB
SO PowerPAD
DDA
LM5017MRX/NOPB
SO PowerPAD
DDA
8
250
213.0
191.0
55.0
8
2500
367.0
367.0
35.0
LM5017SD/NOPB
WSON
LM5017SDX/NOPB
WSON
NGU
8
1000
210.0
185.0
35.0
NGU
8
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DDA0008B
MRA08B (Rev B)
www.ti.com
MECHANICAL DATA
NGU0008B
SDC08B (Rev A)
www.ti.com
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