LM5025AEVAL/NOPB

User's Guide SNVA097B – November 2004 – Revised May 2013 AN-1345 LM5025A Evaluation Board 1 Introduction The LM5025A evaluation board is designed to provide the design engineer with a fully-functional power converter based on the Active Clamp Forward topology to evaluate the LM5025A controller. The evaluation board is provided in an industry standard half-brick footprint. The performance of the evaluation board is as follows: • Input range: 36V to 78V (100V peak) • Output voltage: 3.3V • Output current: 0 to 30A • Measured efficiency: 90.5% at 30A, 92.5% at 15A • Frequency of operation: 230kHz • Board size: 2.3 x 2.4 x 0.5 inches • Load Regulation: 1% • Line Regulation: 0.1% • Line UVLO, Hiccup Current Limit The printed circuit board consists of 4 layers of 3 ounce copper on FR4 material with a total thickness of 0.050 inches. Soldermask has been omitted from some areas to facilitate cooling. The unit is designed for continuous operation at rated load at < 40°C and a minimum airflow of 200 CFM. 2 Theory of Operation Power converters based on the Forward topology offer high efficiency and good power handling capability in applications up to several hundred Watts. The operation of the transformer in a forward topology does not inherently self-reset each power switching cycle, a mechanism to reset the transformer is required. The active clamp reset mechanism is presently finding extensive use in medium level power converters in the 50 to 200W range. The Forward converter is derived from the Buck topology family, employing a single modulating power switch. The main difference between the topologies are, the Forward topology employs a transformer to provide input / output ground isolation and a step down or step up function. Each cycle, the main primary switch turns on and applies the input voltage across the primary winding, which has 12 turns. The transformer secondary has 2 turns, leading to a 6:1 step-down of the input voltage. For an output voltage of 3.3V the required duty cycle (D) of the main switch must vary from approximately 60% (low line) to 25% (high line). The clamp capacitor along with the reset switch reverse biases the transformer primary each cycle when the main switch turns off. This reverse voltage resets the transformer. The clamp capacitor voltage is Vin / (1-D). The secondary rectification employs self-driven synchronous rectification to maintain high efficiency and ease of drive. Feedback from the output is processed by an amplifier and reference, generating an error voltage, which is coupled back to the primary side control through an optocoupler. The LM5025A voltage mode controller pulse width modulates the error signal with a ramp signal derived from the input voltage. Deriving the ramp signal slope from the input voltage provides line feed-forward, which improves line transient rejection. The LM5025A also provides a controlled delay necessary for the reset switch. All trademarks are the property of their respective owners. SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated AN-1345 LM5025A Evaluation Board 1 Powering and Loading Considerations www.ti.com The evaluation board can be synchronized to an external clock with a recommended frequency range of 190 to 300KHz. VOUT 3.3V VIN 35 - 78V LM5025A CS1 VIN UVLO ERROR AMP & ISOLATION VCC OUT_A OUT_B RAMP COMP REF CS2 SYNC Rt TIME SS PGND AGND UP/DOWN SYNC Figure 1. Simplified Active Clamp Forward Converter 3 Powering and Loading Considerations When applying power to the LM5025A evaluation board certain precautions need to be followed. A failure or mis-connection can present itself in a very alarming manner. 4 Proper Connections When operated at low input voltages the UUT can draw up to 3.5A of current at full load. The maximum rated output current for the evaluation board is 30A. Be sure to choose the correct connector and wire size when attaching the source supply and the load. Monitor the current into and out of the UUT (evaluation board or unit under test). Monitor the voltage directly at the output terminals of the UUT. The voltage drop across the load connecting wires will give inaccurate measurements, this is especially true for accurate efficiency measurements. 5 Source Power The evaluation board can be viewed as a constant power load. At low input line voltage (35V) the input current can reach 3.5A, while at high input line voltage (78V) the input current will be approximately 1.5A. Therefore to fully test the LM5025A evaluation board a DC power supply capable of at least 80V and 4A is required. The power supply must have adjustments for both voltage and current. An accurate readout of output current is desirable since the current is not subject to loss in the cables as voltage is. The power supply and cabling must present a low impedance to the UUT. Insufficient cabling or a high impedance power supply will droop during power supply application with the UUT inrush current. If large enough, this droop will cause a chattering condition upon power up. This chattering condition is an interaction with the UUT undervoltage lockout, the cabling impedance and the inrush current 2 AN-1345 LM5025A Evaluation Board SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Loading www.ti.com 6 Loading An appropriate electronic load with specified operation down to 3.0V minimum is desirable. The resistance of a maximum load is 0.11Ω. You need thick cables! Consult a wire chart if needed. If resistor banks are used there are certain precautions to be taken. The wattage and current ratings must be adequate for a 30A, 100W supply. Monitor both current and voltage at all times. Be careful!! The high temperatures reached by even the most adequately rated resistors may burn you or melt your benchtop. 7 Air Flow Full rated power should never be attempted without providing the specified 200 CFM of air flow over the evaluation board. This can be provided by a stand-alone fan. 8 Powering Up Using the shutdown pin provided will allow powering up the source supply with the current level set low. It is suggested that the load be kept low during the first power up. Set the current limit of the source supply to provide about 1.5 times the wattage of the load. As you remove the connection from the shutdown pin to ground, immediately check for 3.3 volts at the output. A most common occurrence, that will prove unnerving, is when the current limit set on the source supply is insufficient for the load. The result is similar to having the high source impedance referred to earlier. The interaction of the source supply folding back and the UUT going into undervoltage shutdown will start an oscillation, or chatter, that may have highly undesirable consequences. A quick efficiency check is the best way to confirm that everything is operating properly. If something is amiss you can be reasonably sure that it will affect the efficiency adversely. Few parameters can be incorrect in a switching power supply without creating losses and potentially damaging heat. 9 Over Current Protection The evaluation board is configured with delayed hiccup over-current protection. In the event of an output overload (approximately 33A) the unit will discharge the softstart capacitor, which disables the power stage. After a delay the softstart is released. The shutdown, delay and slow recharge time of the softstart capacitor protects the unit, especially during short circuit event where the stress is highest. Scope Volt-meter - 80 Volt, 5 Amp Power Supply with Current Meter Evaluation Board + IN Volt-meter Current-meter + ON/OFF (SHUTDOWN) OUT 200 Watt, 60 Amp Electronic Load - + Jumper Figure 2. Typical Evaluation Setup 10 Performance Characteristics 10.1 Turn-on Waveforms When applying power to the LM5025A evaluation board a certain sequence of events must occur. Softstart capacitor values and other components allow the feedback loop to stabilize without overshoot. Figure 3 shows the output voltage during a typical start-up with a 48V input and a load of 5A. There is no overshoot during startup. SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated AN-1345 LM5025A Evaluation Board 3 Performance Characteristics www.ti.com 10.2 Output Ripple Waveforms Figure 4 shows the transient response for a load of change from 5A to 25A. The upper trace shows output voltage droop and overshoot during the sudden change in output current shown by the lower trace. Conditions: Input Voltage = 48VDC, Output Current = 5A Trace 1: Output Voltage Volts/div = 0.5V Horizontal Resolution = 1msec/div 1 Figure 3. Output Voltage During Typical Startup Conditions: Input Voltage = 48VDC, Output Current = 5A to 25A Trace 1: Output Voltage Volts/div = 0.5V Trace 2: Output Current, Amps/div = 10.0A Horizontal Resolution = 1µs/div 1 2 Figure 4. Transient Response Conditions: Input Voltage = 48VDC, Output Current = 30A Bandwidth Limit = 25MHz Trace 1: Output Ripple Voltage Volts/div = 50mV Horizontal Resolution = 2µs/div 1 Figure 5. Output Ripple 4 AN-1345 LM5025A Evaluation Board SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Performance Characteristics www.ti.com Figure 5 shows typical output ripple seen directly across the output capacitor, for an input voltage of 48V and a load of 30A. This waveform is typical of most loads and input voltages. Figure 6 and Figure 7 show the drain voltage of Q1 with a 25A load. Figure 6 represents an input voltage of 38V and Figure 7 represents an input voltage of 78V. Figure 8 shows the gate voltages of the synchronous rectifiers. The drive from the main power transformer is delayed slightly at turn-on by a resistor interacting with the gate capacitance. This provides improved switching transitions for optimum efficiency. The difference in drive voltage is inherent in the topology and varies with line voltage. Conditions: Input Voltage = 38VDC, Output Current = 25A Trace 1: Q1 drain voltage Volts/div = 20V Horizontal Resolution = 1µs/div 1 Figure 6. Drain Voltage Conditions: Input Voltage = 78VDC, Output Current = 25A Trace 1: Q1 drain voltage Volts/div = 20V Horizontal Resolution = 1µs/div 1 Figure 7. Drain Voltage SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated AN-1345 LM5025A Evaluation Board 5 Application Circuit www.ti.com Conditions: Input Voltage = 48VDC, Output Current = 5A Synchronous rectifier, Q3 gate Volts/div = 5V Trace 1: Synchronous rectifier, Q3 gate Volts/div = 5V Trace 2: Synchronous rectifier, Q5 gate Volts/div = 5V Horizontal Resolution = 1µs/div 1 2 Figure 8. Gate Voltages of the Synchronous Rectifiers 11 Application Circuit Figure 9. Application Circuit: Input 36 to 78V, Output 3.3V, 30A 6 AN-1345 LM5025A Evaluation Board SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Layout and Bill of Materials www.ti.com 12 Layout and Bill of Materials The Bill of Materials is shown below and includes the manufacturer and part number. The layers of the printed circuit board are shown in top down order. View is from the top down except for the bottom silkscreen which is shown viewed from the bottom. Scale is approximately X1.5. The printed circuit board consists of 4 layers of 3 ounce copper on FR4 material with a total thickness of 0.050 inches. Table 1. Bill of Materials PART NUMBER DESCRIPTION C1-C4 DESIGNATOR QTY 4 C4532X7R2A225M CAPACITOR, CER, TDK 2.2u, 100V C5 1 C4532X7R3A103K CAPACITOR, CER, TDK 0.01µ, 1000V C6 1 C0805C221J5GAC CAPACITOR, CER, KEMET 220p, 50V C7 1 C2012X7R1E224K CAPACITOR, CER, TDK 0.22µ, 25V C8,C16 2 C3216X7R2E104K CAPACITOR, CER, TDK 0.1µ, 250V C9 1 C4532X7R1E156M CAPACITOR, CER, TDK 15µ, 25V C10,C17,C18, C31 4 C0805C471J5GAC CAPACITOR, CER, KEMET 470p, 50V C11 1 C2012X7R2A103K CAPACITOR, CER, TDK C12,C15,C30, C33 4 C2012X7R1H104K CAPACITOR, CER, TDK 0.1µ, 50V C13 1 C2012X7R2A223K CAPACITOR, CER, TDK 0.022µ, 100V C14 1 C3216X7R1H334K CAPACITOR, CER, TDK 0.33µ, 50V C19,C20 2 C1206C104K5RAC CAPACITOR, CER, KEMET 0.1µ, 50V C21,C22 2 T520D337M006AS4350 CAPACITOR,TANT, KEMET 330µ, 6.3V C23,C24,C25 3 C4532X7S0G686M CAPACITOR, CER, TDK OPEN NOT USED C26 VALUE 0.01µ, 100V 68µ, 4V C27,C32 2 C2012X7R2A102K CAPACITOR, CER, TDK C28 1 C0805C101J5GAC CAPACITOR, CER, KEMET C29 1 C2012X7R2A332K CAPACITOR, CER, TDK D1- D8 8 CMPD2838-NSA DIODE, SIGNAL, CENTRAL L1 1 SLF10145T-5R6M3R2 INPUT CHOKE, TDK L2 1 B0358-C CHOKE with AUX, COILCRAFT 2µH, 33A Q1 1 SI7846DP N-FET, SILICONIX 150V, 50m Q2 1 IRF6217 P-FET, IR 150V, 2.4 Q3 - Q6 4 SI7866DP FET, SILICONIX 20V, 3m R1,R25,R29 3 CRCW120610R0F RESISTOR 10 R2,R16,R17, R21,R22, R34 6 CRCW12061002F RESISTOR 10K R19,R20, R36 3 CRCW12065R60F RESISTOR 5.6 R4 1 CRCW120615R0F RESISTOR 15 R5 1 CRCW12062000F RESISTOR 200 R6 1 CRCW12062003F RESISTOR 200K R8 1 CRCW120649R9F RESISTOR 49.9 R9,R10 2 CRCW12061003F RESISTOR 100K R3 1 CRCW120618R2F RESISTOR 18.2 R7 1 CRCW12063012F RESISTOR 30.1K R11 1 CRCW12068061F RESISTOR 8.06K R12,R15,R18,R26 4 CRCW12061001F RESISTOR 1K R13 1 CRCW12062672F RESISTOR 26.7K SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated 1000p, 100V 100p, 50V 3300p, 100V 5.6µH, 3.5A AN-1345 LM5025A Evaluation Board 7 PCB Layouts www.ti.com Table 1. Bill of Materials (continued) DESIGNATOR 13 PART NUMBER DESCRIPTION R14 QTY 1 CRCW12061652F RESISTOR VALUE 16.5K R23,R24 2 CRCW2512100J RESISTOR 10, 1W R27 1 CRCW12062492F RESISTOR 24.9K R28 1 CRCW12061502F RESISTOR 15K R30 1 CRCW12063012F RESISTOR 30.1K R31,R32 2 CRCW12064991F RESISTOR 4.99K R33 1 CRCW12062002F RESISTOR 20K R35 1 CRCW12061000F RESISTOR 100 T1 1 P8208T CURRENT XFR, PULSE ENG 100:1 T2 1 B0357-B POWER XFR, COILCRAFT 12:02 U1 1 LM5025 CONTROLLER, Texas Instruments U2 1 MOCD207M OPTO-COUPLER, QT OPTO U3 1 LM6132 OPAMP, Texas Instruments U4 1 LM4041 REFERENCE, Texas Instruments PCB Layouts Figure 10. 8 AN-1345 LM5025A Evaluation Board SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated PCB Layouts www.ti.com Figure 11. Figure 12. SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated AN-1345 LM5025A Evaluation Board 9 PCB Layouts www.ti.com Figure 13. Figure 14. 10 AN-1345 LM5025A Evaluation Board SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated PCB Layouts www.ti.com Figure 15. SNVA097B – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated AN-1345 LM5025A Evaluation Board 11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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