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LM5025D
SNVSAB0 – JUNE 2015
LM5025D Active Clamp Voltage Mode PWM Controller
1 Features
3 Description
•
•
•
The LM5025D is a functional variant of the LM5025
active clamp PWM controller. The functional
differences of the LM5025D are:
• The CS1 and CS2 absolute maximum ratings
have been increased to 7 V.
• The CS1 and CS2 current limit thresholds have
been increased to 0.5 V.
• The internal CS2 filter discharge device has been
disabled and no longer operates each clock cycle.
• The internal VCC and VREF regulators continue to
operate when the line UVLO pin is below
threshold.
1
•
•
•
•
•
•
•
•
•
•
Internal Start-Up Bias Regulator
3-A Compound Main Gate Driver
Programmable Line Under-Voltage Lockout
(UVLO) with Adjustable Hysteresis
Voltage Mode Control with Feed-Forward
Adjustable Dual Mode Over-Current Protection
Programmable Overlap or Deadtime Between the
Main and Active Clamp Outputs
Volt x Second Clamp
Programmable Soft-Start
Leading Edge Blanking
Single Resistor Programmable Oscillator
Oscillator Up and Down Sync Capability
Precision 5-V Reference
Thermal Shutdown
The LM5025D PWM controller contains all of the
features necessary to implement power converters
utilizing the Active Clamp and Reset technique. With
the active clamp technique, higher efficiencies and
greater power densities can be realized compared to
conventional catch winding or RDC clamp and reset
techniques. Two control outputs are provided, the
main power switch control (OUT_A) and the active
clamp switch control (OUT_B). The two internal
compound gate drivers parallel both MOS and Bipolar
devices, providing superior gate drive characteristics.
This controller is designed for high-speed operation
including an oscillator frequency range up to 1 MHz
and total PWM and current sense propagation delays
less than 100 ns. The LM5025D includes a highvoltage start-up regulator that operates over a wide
input range of 13 V to 90 V. Additional features
include: Line Under-Voltage Lockout (UVLO),
softstart, oscillator UP and DOWN sync capability,
precision reference and thermal shutdown.
2 Applications
•
•
•
•
Server Power Supplies
48-V Telecom Power Supplies
42-V Automotive Applications
High-Efficiency DC-to-DC Power Supplies
Device Information(1)
PART NUMBER
LM5025D
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
6.60 mm x 5.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
VOUT
3.3 V
VIN
35 V to 78 V
LM5025D
3
CS1
VCC
7
1
VIN
OUT_A
8
OUT_B
9
16 UVLO
2
RAMP
6
REF
14 RT
5
COMP 13
CS2
Error Amp
and
Isolation
4
SYNC 15
TIME
SS 12
PGND AGND
10
11
Up/ Down
SYNC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5025D
SNVSAB0 – JUNE 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Performance Characteristics ........................
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
8.3 System Examples ................................................... 23
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1 Trademarks ........................................................... 25
11.2 Electrostatic Discharge Caution ............................ 25
11.3 Glossary ................................................................ 25
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
2
DATE
REVISION
NOTES
June, 2015
*
Initial release.
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
VIN
1
16
UVLO
RAMP
2
15
SYNC
CS1
3
14
RT
CS2
4
13
COMP
TIME
5
12
SS
REF
6
11
AGND
VCC
7
10
PGND
OUT_A
8
9
OUT_B
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Pin Functions
PIN
4
DESCRIPTION
NO.
AGND
11
G
Analog ground. Connect directly to power ground. For the PW package option the exposed
pad is electrically connected to AGND.
COMP
13
I
Input to the pulse width modulator. An internal 5-kΩ resistor pull-up is provided on this pin.
The external opto-coupler sinks current from COMP to control the PWM duty cycle.
CS1
3
I
Current sense input for cycle-by-cycle limiting. If CS1 exceeds 0.5 V the outputs will go into
cycle-by-cycle current limit. CS1 is held low for 50 ns after OUT_A switches high providing
leading edge blanking.
CS2
4
I
Current sense input for soft restart. If CS2 exceeds 0.5 V the outputs will be disabled and a
softstart commenced. The soft-start capacitor will be fully discharged and then released with
a pull-up current of 1 µA. After the first output pulse (when SS = 1 V), the SS charge current
will revert back to 20 µA.
EP
-
-
Exposed pad, underside of the PW package option. Internally bonded to the die substrate.
Connect to GND potential for low thermal impedance.
OUT_A
8
O
Main output driver. Output of the main switch PWM output gate driver. Output capability of 3A peak sink current.
OUT_B
9
O
Active Clamp output driver. Output of the active clamp switch gate driver. Capable of 1.25-A
peak sink current.
PGND
10
G
Power ground. Connect directly to analog ground.
RAMP
2
I
Modulator ramp signal. An external RC circuit from VIN sets the ramp slope. This pin is
discharged at the conclusion of every cycle by an internal FET, initiated by either the internal
clock or the V x Sec clamp comparator.
REF
6
O
Precision 5-V reference output. Maximum output current: 10 mA locally decouple with a 0.1µF capacitor. Reference stays low until the VCC UV comparator is satisfied.
RT
14
I
Oscillator timing resistor pin. An external resistor connected from RT to ground sets the
internal oscillator frequency.
SS
12
I
Soft-start control. An external capacitor and an internal 20-µA current source set the softstart
ramp. The SS current source is reduced to 1 µA initially following a CS2 over-current event
or an over temperature event.
SYNC
15
I
Oscillator UP/DOWN synchronization input. The internal oscillator can be synchronized to an
external clock with a frequency 20% lower than the internal oscillator’s free running
frequency. There is no constraint on the maximum sync frequency.
I
Output overlap/deadtime control. An external resistor (RSET) sets either the overlap time or
dead time for the active clamp output. An RSET resistor connected between TIME and GND
produces in-phase OUT_A and OUT_B pulses with overlap. An RSET resistor connected
between TIME and REF produces out-of-phase OUT_A and OUT_B pulses with deadtime.
TIME
(1)
I/O (1)
NAME
5
UVLO
16
I
Line Under-Voltage shutdown. An external voltage divider from the power source sets the
shutdown comparator levels. The comparator threshold is 2.5 V. Hysteresis is set by an
internal current source (20 µA) that is switched on or off as the UVLO pin potential crosses
the 2.5 V threshold.
VCC
7
P
Output from the internal high voltage start-up regulator. The VCC voltage is regulated to 7.6
V. If an auxiliary winding raises the voltage on this pin above the regulation setpoint, the
internal start-up regulator will shutdown, reducing the device power dissipation.
VIN
1
I
Source input voltage. Input to start-up regulator. Input range 13 V to 90 V, with transient
capability to 105 V.
P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted) (2)
MIN
MAX
UNIT
VIN to GND
–0.3
105
V
VCC to GND
–0.3
16
V
CS1, CS2 to GND
–0.3
7
V
All other inputs to GND
–0.3
7
V
150
°C
150
°C
Junction Temperature
Storage temperature, Tstg
(1)
(2)
–55
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge (1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (3)
±500
UNIT
V
For detailed information on soldering plastic TSSOP package, refer to the Packaging Data Book.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input Voltage
NOM
MAX
UNIT
13
90
External Voltage Applied to VCC
8
15
V
V
Operating Junction Temperature
–40
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
TSSOP
16 PINS
RθJA
Junction-to-ambient thermal resistance
95.9
RθJC(top)
Junction-to-case (top) thermal resistance
27.0
RθJB
Junction-to-board thermal resistance
41.0
ψJT
Junction-to-top characterization parameter
1.1
ψJB
Junction-to-board characterization parameter
40.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C, and all MIN and MAX values apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STARTUP REGULATOR
VCC Reg
VCC regulation
VCC current limit
Startup regulator leakage (external
VCC supply)
I-VIN
No load
(2)
7.3
7.6
20
25
VIN = 100 V
165
7.9
V
mA
500
µA
VCC SUPPLY
VCC under-voltage lockout voltage
(positive going VCC)
VCC under-voltage hysteresis
VCC supply current (ICC)
VCC Reg –
220mV
VCC Reg 120mV
1.0
1.5
V
2.0
V
4.2
mA
5
5.15
V
25
50
CGATE = 0
REFERENCE SUPPLY
VREF
REF voltage
IREF = 0 mA
REF voltage regulation
IREF = 0 mA to 10 mA
REF current limit
4.85
10
mV
20
mA
CURRENT LIMIT
CS1 Prop
CS1 delay to output
CS1 step from 0 V to 0.6 V,
Time to onset of OUT transition
(90%),
CGATE = 0
40
ns
CS2 Prop
CS2 delay to output
CS2 step from 0 V to 0.6 V,
Time to onset of OUT transition
(90%),
CGATE = 0
50
ns
Cycle-by-cycle threshold voltage
(CS1)
Cycle skip threshold voltage (CS2)
Resets SS capacitor; auto restart
0.45
0.5
0.55
V
0.45
0.5
0.55
V
Leading edge blanking time (CS1)
50
ns
CS1 sink impedance (clocked)
CS1 = 0.4 V
30
50
Ω
CS1 sink impedance (post fault
discharge)
CS1 = 0.6 V
15
30
Ω
CS2 sink impedance (post fault
discharge)
CS2 = 0.6 V
55
95
Ω
CS1 and CS2 leakage current
CS = CS threshold – 100 mV
1
µA
SOFT-START
Soft-start current source normal
17
22
27
µA
Soft-start current source following a
CS2 event
0.5
1
1.5
µA
OSCILLATOR
Frequency1
TA = 25°C,
TJ = TLOW to THIGH
180
175
200
220
225
kHz
Frequency2
RT = 10.4 kΩ
510
580
650
kHz
100
ns
Sync threshold
2
Min sync pulse width
Sync frequency range
(1)
(2)
6
160
V
kHz
All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Device thermal limitations may limit usable range.
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Electrical Characteristics (continued)
Specifications with standard typeface are for TJ = 25°C, and all MIN and MAX values apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM COMPARATOR
Delay to output
COMP step 5 V to 0 V,
Time to onset of OUT_A transition
low
Duty cycle range
40
0
COMP to PWM offset
0.7
COMP open circuit voltage
4.3
COMP short circuit current
1
ns
80
%
1.3
V
5.9
V
COMP = 0 V
0.6
1
1.4
mA
Delta RAMP measured from onset
of OUT_A to ramp peak,
COMP = 5 V
2.4
2.5
2.6
V
2.44
2.5
2.56
V
16
20
24
µA
10
Ω
VOLT x SECOND CLAMP
Ramp clamp level
UVLO SHUTDOWN
Undervoltage shutdown threshold
Undervoltage shutdown hysteresis
OUTPUT SECTION
OUT_A high saturation
MOS device at IOUT = –10 mA
5
OUTPUT_A peak current sink
Bipolar device at Vcc/2
3
OUT_A low saturation
MOS device at IOUT = 10 mA
OUTPUT_A rise time
CGATE = 2.2 nF
20
OUTPUT_A fall time
CGATE = 2.2 nF
15
OUT_B high saturation
MOS device at IOUT = –10 mA
10
OUTPUT_B peak current sink
Bipolar device at VCC/2
OUT_B low saturation
MOS device at IOUT = 10 mA
12
OUTPUT_B rise time
CGATE = 1 nF
20
ns
OUTPUT_B fall time
CGATE = 1 nF
15
ns
6
A
9
Ω
ns
ns
20
Ω
18
Ω
1
A
OUTPUT TIMING CONTROL
Overlap time
RSET = 38 kΩ connected to GND,
50% to 50% transitions
75
105
135
ns
Deadtime
RSET = 29.5 kΩ connected to REF,
50% to 50% transitions
75
105
135
ns
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
165
°C
Thermal shutdown hysteresis
25
°C
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6.6 Typical Performance Characteristics
16
10
VIN
14
8
12
6
VCC (V)
VCC (V)
10
VCC
8
4
6
4
2
2
0
0
0
2
4
6
8
10
12
14
16
0
5
10
15
20
VIN (V)
ICC (mA)
Figure 1. VCC Regulator Start-up Characteristics, VCC vs VIN
Figure 2. VCC vs ICC
25
6
5
VREF (V)
4
3
2
1
0
0
5
10
15
20
25
IREF (mA)
Figure 4. Oscillator Frequency vs RT
Figure 3. VREF vs IREF
140
400
130
300
OVERLAP TIME (ns)
OVERLAP TIME (ns)
350
250
200
150
100
120
110
100
90
50
0
0
20
40
60
80
100
80
-40
120
RSET (k:)
Figure 5. Overlap Time vs RSET
8
25
_
75
_
125
o
TEMPERATURE ( C)
Figure 6. Overlap Time vs Temperature RSET = 38 kΩ
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Typical Performance Characteristics (continued)
140
400
350
130
DEADTIME (ns)
DEADTIME (ns)
300
250
200
150
120
110
100
100
90
50
0
0
20
40
60
80
100
80
-40
120
RSET (k:)
25
75
125
TEMPERATURE (oC)
Figure 7. Dead Time vs RSET
Figure 8. Dead Time vs Temperature RSET = 29.5 kΩ
26
SS CURRENT (PA)
24
22
20
18
16
14
-40
25
75
125
TEMPERATURE (oC)
Figure 9. SS Pin Current vs Temperature
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7 Detailed Description
7.1 Overview
The LM5025D is a functional variant of the LM5025 active clamp PWM controller. The functional differences of
the LM5025D are:
• The CS1 and CS2 absolute maximum ratings have been increased to 7 V.
• The CS1 and CS2 current limit thresholds have been increased to 0.5 V.
• The internal CS2 filter discharge device has been disabled and no longer operates each clock cycle.
• The internal VCC and VREF regulators continue to operate when the line UVLO pin is below threshold.
The LM5025D PWM controller contains all of the features necessary to implement power converters utilizing the
active clamp reset techniques. The device can be configured to control either a P-Channel clamp switch or an NChannel clamp switch. With the active clamp technique higher efficiencies and greater power densities can be
realized compared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are
provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The active clamp
output can be configured for either a specified overlap time (for P-Channel switch applications) or a specified
dead time (for N_Channel applications). The two internal compound gate drivers parallel both MOS and Bipolar
devices, providing superior gate drive characteristics. This controller is designed for high-speed operation
including an oscillator frequency range up to 1 MHz and total PWM and current sense propagation delays less
than 100 ns. The LM5025D includes a high-voltage, start-up regulator that operates over a wide input range of
13 V to 90 V. Additional features include: Line Under-Voltage Lockout (UVLO), softstart, oscillator UP/DOWN
sync capability, precision reference and thermal shutdown.
10
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7.2 Functional Block Diagram
7.6 V Series
Regulator
VIN
1
VCC
UVLO
Logic
UVLO 16
6
REF
8
OUT_A
5
TIME
9
OUT_B
10
PGND
11
AGND
VCC
Oscillator
SYNC 15
FF
Ramp
2
Driver
Dead
Time or
Overlap
Control
CLK
RT 14
5V
S
Q
R
Q
5 k
COMP 13
SS Amp
(sink only)
SS
VCC
Driver
+
1V
CS1
VCC
+
UVLO Hysteresis
(20 PA)
RAMP
5V
Reference
7
+
Logic
2.5 V MAX
VS Clamp
3
+
0.5 V
CS2
4
+
0.5 V
CLK +
LEB
20 PA
SS
SS 12
19 PA
Figure 10. Simplified Block Diagram
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7.3 Feature Description
7.3.1 High Voltage Start-Up Regulator
The LM5025D contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected
directly to the line voltage. The regulator output is internally current limited to 20 mA. When power is applied, the
regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended
capacitance range for the VCC regulator is 0.1 µF to 100 µF. When the voltage on the VCC pin reaches the
regulation point of 7.6 V and the internal voltage reference (REF) reaches its regulation point of 5 V, the
controller outputs are enabled. The outputs remain enabled until VCC falls below 6.2 V or the line Under-Voltage
Lock Out detector indicates that VIN is out of range. In typical applications, an auxiliary transformer winding is
connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8 V to shut off the
internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the
controller power dissipation.
When the converter auxiliary winding is inactive, external current draw on the VCC line should be limited so the
power dissipated in the start-up regulator does not exceed the maximum power dissipation of the controller.
An external start-up regulator or other bias rail can be used instead of the internal start-up regulator by
connecting the VCC and the VIN pins together and feeding the external bias voltage into the two pins.
7.3.2 Line Under-Voltage Detector
The LM5025D contains a line Under-Voltage Lock Out (UVLO) circuit. An external set-point voltage divider from
VIN to GND, sets the operational range of the converter. The divider must be designed such that the voltage at
the UVLO pin is greater than 2.5 V when VIN is in the desired operating range. If the undervoltage threshold is
not met, both outputs are disabled, all other functions of the controller remain active. UVLO hysteresis is
accomplished with an internal 20-µA current source that is switched on or off into the impedance of the set-point
divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at
the UVLO pin. When the UVLO pin voltage falls below the 2.5 V threshold, the current source is turned off
causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable /
disable function. Pulling the UVLO pin below the 2.5 V threshold disables the PWM outputs.
7.3.3 PWM Outputs
The relative phase of the main (OUT_A) and active clamp outputs (OUT_B) can be configured for the specific
application. For active clamp configurations utilizing a ground referenced P-Channel clamp switch, the two
outputs should be in phase with the active clamp output overlapping the main output. For active clamp
configurations utilizing a high-side, N-Channel switch, the active clamp output should be out of phase with main
output and there should be a dead time between the two gate drive pulses. A distinguishing feature of the
LM5025D is the ability to accurately configure either dead time (both off) or overlap time (both on) of the gate
driver outputs. The overlap / deadtime magnitude is controlled by the resistor value connected to the TIME pin of
the controller. The opposite end of the resistor can be connected to either REF for deadtime control or GND for
overlap control. The internal configuration detector senses the connection and configures the phase relationship
of the main and active clamp outputs.
12
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Feature Description (continued)
7.3.4 Compound Gate Drivers
The LM5025D contains two unique compound gate drivers, which parallel both MOS and Bipolar devices to
provide high drive current throughout the entire switching event. The Bipolar device provides most of the drive
current capability and provides a relatively constant sink current which is ideal for driving large power MOSFETs.
As the switching event nears conclusion and the Bipolar device saturates, the internal MOS device continues to
provide a low impedance to compete the switching event.
During turn-off at the Miller plateau region, typically around 2 V to 3 V, is where gate-driver current capability is
needed most. The resistive characteristics of all MOS gate drivers are adequate for turn-on since the supply to
output voltage differential is fairly large at the Miller region. During turn-off however, the voltage differential is
small and the current source characteristic of the Bipolar gate driver is beneficial to provide fast drive capability.
VCC
7
8/9 OUT_A/B
CNTRL
10
PGND
Figure 11. Compound Gate Drivers
7.3.5 PWM Comparator
The PWM comparator compares the ramp signal (RAMP) to the loop error signal (COMP). This comparator is
optimized for speed in order to achieve minimum controllable duty cycles. The internal 5-kΩ pull-up resistor,
connected between the internal 5-V reference and COMP, can be used as the pull-up for an optocoupler. The
comparator polarity is such that 0 V on the COMP pin produces a zero duty cycle on both gate driver outputs.
7.3.6 Volt Second Clamp
The Volt x Second Clamp comparator compares the ramp signal (RAMP) to a fixed 2.5-V reference. By proper
selection of RFF and CFF, the maximum ON time of the main switch can be set to the desired duration. The ON
time set by Volt x Second Clamp varies inversely with the line voltage because the RAMP capacitor is charged
by a resistor connected to VIN while the threshold of the clamp is a fixed voltage (2.5 V).
The CFF ramp capacitor is discharged at the conclusion of every cycle by an internal discharge switch controlled
by either the internal clock or by the V x S Clamp comparator, whichever event occurs first.
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Feature Description (continued)
7.3.7 Current Limit
The LM5025D contains two modes of over-current protection. If the sense voltage at the CS1 input exceeds 0.5
V the present power cycle is terminated (cycle-by-cycle current limit). If the sense voltage at the CS2 input
exceeds 0.5 V, the controller terminates the present cycle, discharge the softstart capacitor and reduce the
softstart current source to 1 µA. The softstart (SS) capacitor is released after being fully discharged and slowly
charges with a 1-µA current source. When the voltage at the SS pin reaches approximately 1 V, the PWM
comparator produces the first output pulse at OUT_A. After the first pulse occurs, the softstart current source
reverts to the normal 20-µA level. Fully discharging and then slowly charging the SS capacitor protects a
continuously over-loaded converter with a low duty-cycle hiccup mode.
These two modes of over-current protection allow the user great flexibility to configure the system behavior in
over-load conditions. If it is desired for the system to act as a current source during an over-load, then the CS1
cycle-by-cycle current limiting should be used. In this case the current sense signal should be applied to the CS1
input and the CS2 input should be grounded. If during an overload condition it is desired for the system to briefly
shutdown, followed by softstart retry, then the CS2 hiccup current limiting mode should be used. In this case the
current sense signal should be applied to the CS2 input and the CS1 input should be grounded. This shutdown /
soft-start retry repeats indefinitely while the over-load condition remains. The hiccup mode will greatly reduce the
thermal stresses to the system during heavy overloads. The cycle-by-cycle mode has higher system thermal
dissipations during heavy overloads, but provides the advantage of continuous operation for short duration
overload conditions.
It is possible to utilize both over-current modes concurrently, whereby slight overload conditions activate the CS1
cycle-by-cycle mode while more severe overloading activates the CS2 hiccup mode. Generally the CS1 input is
configured to monitor the main switch FET current of each cycle. The CS2 input can be configured in several
different ways depending upon the system requirements.
• The CS2 input can also be set to monitor the main switch FET current except scaled to a higher threshold
than CS1.
• An external over-current timer can be configured which trips after a pre-determined over-current time, driving
the CS2 input high, initiating a hiccup event.
• In a closed loop voltage regulation system, the COMP input rises to saturation when the cycle-by-cycle
current limit is active. An external filter/delay timer and voltage divider can be configured between the COMP
pin and the CS2 pin to scale and delay the COMP voltage. If the CS2 pin voltage reaches 0.5 V a hiccup
event initiates.
A small RC filter, located near the controller, is recommended for each of the CS pins. The CS1 input has an
internal FET which discharges the current sense filter capacitor at the conclusion of every cycle, to improve
dynamic performance. This same FET remains on an additional 50 ns at the start of each main switch cycle to
attenuate the leading edge spike in the current sense signal. The CS2 discharge FET only operates following a
CS2 event, UVLO and thermal shutdown.
14
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Feature Description (continued)
The LM5025D CS comparators are very fast and may respond to short duration noise pulses. Layout
considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS
filter must be placed very close to the device and connected directly to the pins of the device (CS and GND). If a
current sense transformer is used, both leads of the transformer secondary should be routed to the filter
network , which should be located close to the device. If a sense resistor in the source of the main switch
MOSFET is used for current sensing, a low inductance type of resistor is required. When designing with a current
sense resistor, all of the noise sensitive low power ground connections should be connected together near the
device GND and a single connection should be made to the power ground (sense resistor ground point).
CS2
SS
20 PA
1 PA
Figure 12. Current Limit
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Feature Description (continued)
7.3.8 Oscillator and Sync Capability
The LM5025D oscillator is set by a single external resistor connected between the RT pin and GND. The RT
resistor should be located very close to the device and connected directly to the pins of the device (RT and
GND).
A unique feature of LM5025D is the ability to synchronize the oscillator to an external clock with a frequency that
is either higher or lower than the frequency of the internal oscillator. The lower frequency sync frequency range is
80% of the free running internal oscillator frequency. There is no constraint on the maximum SYNC frequency. A
minimum pulse width of 100 ns is required for the synchronization clock . If the synchronization feature is not
required, the SYNC pin should be connected to GND to prevent any abnormal interference . The internal
oscillator can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal acts
directly as the master clock for the controller. Both the frequency and the maximum duty cycle of the PWM
controller can be controlled by the SYNC signal (within the limitations of the Volt x Second Clamp). The
maximum duty cycle (D) is (1-D) of the SYNC signal.
7.3.9 Feed-Forward Ramp
An external resistor (RFF) and capacitor (CFF) connected to VIN and GND are required to create the PWM ramp
signal. The slope of the signal at the RAMP pin varies in proportion to the input line voltage. This varying slope
provides line feedforward information necessary to improve line transient response with voltage mode control.
The RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to
control the duty cycle of the main switch output. The volt second clamp comparator also monitors the RAMP pin
and if the ramp amplitude exceeds 2.5 V the present cycle is terminated. The ramp signal is reset to GND at the
end of each cycle by either the internal clock or the volt second comparator, whichever occurs first.
7.3.10 Soft-Start
The softstart feature allows the power converter to gradually reach the initial steady state operating point, thus
reducing start-up stresses and surges. At power on, a 20-µA current is sourced out of the softstart pin (SS) into
an external capacitor. The capacitor voltage ramps up slowly and limits the COMP pin voltage and therefore the
PWM duty cycle. In the event of a fault as determined by VCC undervoltage, line undervoltage (UVLO) or second
level current limit, the output gate drivers are disabled and the softstart capacitor is fully discharged. When the
fault condition is no longer present a softstart sequence is initiated. Following a second level current limit
detection (CS2), the softstart current source is reduced to 1 µA until the first output pulse is generated by the
PWM comparator. The current source returns to the nominal 20 µA level after the first output pulse (~1 V at the
SS pin).
7.3.11 Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power standby
state with the output drivers and the bias regulator disabled. The device restarts after the thermal hysteresis
(typically 25°C). During a restart after thermal shutdown, the softstart capacitor is fully discharged and then
charged in the low current mode (1 µA) similar to a second level current limit event. The thermal protection
feature is provided to prevent catastrophic failures from accidental device overheating.
16
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7.4 Device Functional Modes
The LM5025D active clamp voltage mode PWM controller has six functional modes. The modes transition
diagram is shown below.
•
•
•
•
•
•
UVLO Mode
Soft-Start Mode
Normal Operation Mode
Cycle-by-Cycle Current Limit Mode
Hiccup Mode
Thermal Shut Down Mode
UVLO
CBC
Soft Start
Hiccup
Normal Operation
Thermal Shut Down
Figure 13. Functional Mode Transition Diagram
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5025D PWM controller contains all of the features necessary to implement power converters utilizing the
Active Clamp and Reset technique. This section provides design guidance for a typical active clamp forward
converter design. Design requirements and detailed design procedure are described in Design Requirements
and Application Curves. Application curves are given in Section 8.2.3. An actual application schematic of a 36-V
to 78-V input, 3.3-V, 30-A output active clamp forward converter is also provided.
8.2 Typical Application
Figure 14 shows a simplified schematic of an active clamp forward power converter.
Power converters based on the Forward topology offer high efficiency and good power handling capability in
applications up to several hundred Watts. The operation of the transformer in a forward topology does not
inherently self-reset each power switching cycle, a mechanism to reset the transformer is required. The active
clamp reset mechanism is presently finding extensive use in medium level power converters in the 50 W to 200
W range.
The Forward converter is derived from the Buck topology family, employing a single modulating power switch.
The main difference between the topologies is the forward topology employs a transformer to provide
input/output ground isolation and a step down or step up function.
Each cycle, the main primary switch turns on and applies the input voltage across the primary winding. The
transformer turns the voltage to a lower level on the secondary side. The clamp capacitor along with the reset
switch reverse biases the transformer primary each cycle when the main switch turns off. This reverse voltage
resets the transformer. The clamp capacitor voltage is VIN / (1-D).
The secondary rectification employs self-driven synchronous rectification to maintain high efficiency and ease of
drive.
Feedback from the output is processed by an amplifier and reference, generating an error voltage, which is
coupled back to the primary side control through an opto-coupler. The LM5025D voltage mode controller pulse
width modulates the error signal with a ramp signal derived from the input voltage. Deriving the ramp signal slope
from the input voltage provides line feed-forward, which improves line transient rejection. The LM5025D also
provides a controlled delay necessary for the reset switch.
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Typical Application (continued)
VOUT
3.3 V
VIN
35 V to 78 V
LM5025D
3
CS1
VCC
7
1
VIN
OUT_A
8
OUT_B
9
16 UVLO
2
RAMP
6
REF
14 RT
5
Error Amp
and
Isolation
COMP 13
CS2
4
SYNC 15
TIME
SS 12
PGND AGND
10
11
Up/ Down
SYNC
Figure 14. Simplified Active Clamp Forward Power Converter
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Typical Application (continued)
8.2.1 Design Requirements
This typical application provides an example of a fully-functional power converter based on the Active Clamp
Forward topology in an industry standard half-brick footprint.
The design requirements are:
•
•
•
•
•
•
•
•
•
Input Range: 36 V to 78 V (100 V peak)
Output Voltage: 3.3 V
Output Current: 0 A to 30 A
Measured Efficiency: 90.5% at 30 A, 92.5% at 15 A
Frequency of Operation: 230 kHz
Board Size: 2.3 x 2.4 x 0.5 inches
Load Regulation: 1%
Line Regulation: 0.1%
Line UVLO, Hiccup Current Limit
8.2.2 Detailed Design Procedure
Before the controller design begins, the power stage design must be completed. This chapter describes the
calculations needed to configure the LM5025D controller to meet the power stage design requirements.
8.2.2.1 Oscillator
The desired switching frequency F is set by a resistor connected between RT pin and ground. The resistance
value RT is calculated from:
RT = (5725/F)1.026
where
•
F is in kHz and RT in kΩ.
(1)
8.2.2.2 Soft-Start Ramp Time and Hiccup Interval
The soft-start ramp time and hiccup internal is programmed by a capacitor (CSS) on the SS pin to ground. The
soft-start ramp time is determined by comparing the SS pin voltage with COMP pin voltage. When the SS voltage
is less than COMP voltage, the COMP voltage is clamped by SS voltage. The PWM duty is limited by the
clamped COMP voltage, so that soft start can be achieved. The first PWM pulse is generated after COMP
voltage reaches 1 V. So the soft-start ramp time of the output voltage can be estimated by:
V 1 V
TSS (ms) CSS (nF) u SS
20 PA
where
•
VSS is the steady state COMP pin voltage. This voltage is determined by the output voltage, voltage divider,
and the compensation network.
(2)
In hiccup mode, the SS current source is reduced to 1 µA. When the first PWM pulse is generated, the current
source switches to 20 µA, and the power supply tries to start up again. The hiccup interval can be calculated by:
1V
Thiccup (ms) CSS (nF) u
1 PA
(3)
20
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Typical Application (continued)
8.2.2.3 Feed-Forward Ramp and Maximum On Time Clamp
An example illustrates the use of the Volt x Second Clamp comparator to achieve a 50% duty cycle limit, at
200bKHz, at a 48-V line input: A 50% duty cycle at a 200 KHz requires a 2.5 µs of ON time. At 48-V input the
Volt x Second product is 120 V x µs (48 V x 2.5 µs). To achieve this clamp level:
RFF x CFF = VIN x TON / 2.5V
48 x 2.5 µF / 2.5 = 48 µF
(4)
(5)
Select CFF = 470 pF
RFF = 102 kΩ
The recommended capacitor value range for CFF is 100 pF to 1000 pF.
8.2.2.4 Dead Times
The magnitude of the overlap/dead time can be calculated as follows:
Overlap Time (ns) = 2.8 x RSET - 1.2
Dead Time (ns) = 2.9 x RSET +20
RSET in kΩ, Time in ns
OUT_A
K1 x RSET
P-Channel Active Clamp
(RSET to GND)
OUT_B
OUT_A
N-Channel Active Clamp
(RSET to REF)
K2 x RSET
OUT_B
Figure 15. PWM Outputs
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Typical Application (continued)
8.2.3 Application Curves
1
2
1
Conditions: Input Voltage = 48 VDC, Output Current = 5 A
Trace 1: Output Voltage Volts/div = 0.5 V
Horizontal Resolution = 1 msec/div
Figure 16. Output Voltage During Typical Startup
Conditions: Input Voltage = 48 VDC, Output Current = 5 A to 25
A
Trace 1: Output Voltage Volts/div = 0.5 V
Trace 2: Output Current, Amps/div = 10.0 A
Horizontal Resolution = 1 μs/div
Figure 17. Transient Response
1
1
Conditions: Input Voltage = 48 VDC, Output Current = 30 A
Bandwidth Limit = 25 MHz
Trace 1: Output Ripple Voltage Volts/div = 50 mV
Horizontal Resolution = 2 μs/div
Conditions: Input Voltage = 38 VDC, Output Current = 25 A
Trace 1: Q1 drain voltage Volts/div = 20 V
Horizontal Resolution = 1 μs/div
Figure 19. Drain Voltage
Figure 18. Output Ripple
1
2
1
Conditions: Input Voltage = 78 VDC, Output Current = 25 A
Trace 1: Q1 drain voltage Volts/div = 20 V
Horizontal Resolution = 1 μs/div
Figure 20. Drain Voltage
Conditions: Input Voltage = 48 VDC, Output Current = 5 A
Synchronous rectifier, Q3 gate Volts/div = 5 V
Trace 1: Synchronous rectifier, Q3 gate Volts/div = 5 V
Trace 2: Synchronous rectifier, Q5 gate Volts/div = 5 V
Horizontal Resolution = 1 μs/div
Figure 21. Gate Voltages of the Synchronous Rectifiers
22
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8.3 System Examples
Shown below is an application circuit with 36-V to 78-V input and 3.3-V, 30-A output capability.
Figure 22. Application Circuit
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9 Power Supply Recommendations
VCC pin is the power supply for the device. There should be a 0.1-µF~100-μF capacitor directly from VCC to
ground. REF pin should be by-passed to ground as close as possible to the device using a 0.1-μF capacitor.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
Connect two grounds PGND (power ground) and AGND (analog ground) directly as device ground ICGND.
The connection should be as close to the pins as possible.
If there are multiple PCB layers and there is a inner ground layer, use two vias or one big via on GND and
connect them to the inner ground layer (ICGND).
The power stage ground PSGND should be separated with the ICGND. PSGND and ICGND should be
connected at a single point close to the device.
The bypass capacitors to the VCC pin and REF pin should be as close as possible to the pins and ground
(ICGND).
The filtering capacitors connected to CS1 and CS2 pins should have connections as short as possible to
ICGND; if an inner ground layer is available, use vias to connect the capacitors to the ground layer (ICGND).
The resistors and capacitors connected to the timing configuration pins should be as close as possible to the
pins and ground (ICGND).
10.2 Layout Example
Figure 23. Layout Example
24
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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25-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM5025DMTC/NOPB
LIFEBUY
TSSOP
PW
16
92
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
L5025D
MTC
LM5025DMTCX/NOPB
LIFEBUY
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
L5025D
MTC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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