LM5026SDX

LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 LM5026 Active Clamp Current Mode PWM Controller Check for Samples: LM5026 FEATURES DESCRIPTION • • • • • The LM5026 PWM controller contains all of the features necessary to implement power converters utilizing the active clamp / reset technique with current mode control. With the active clamp technique, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The device can be configured to control either a P-Channel or N-Channel clamp switch. The main gate driver features a compound configuration, consisting of both MOS and Bipolar devices, providing superior gate drive characteristics. The LM5026 can be configured to operate with bias voltages over a wide input range of 8V to 100V. Additional features include programmable maximum duty cycle, line under-voltage lockout, cycle-by-cycle current limit, hiccup mode fault operation with adjustable timeout delay, PWM slope compensation, soft-start, 1MHz capable oscillator with synchronization input / output capability, precision reference and thermal shutdown. 1 2 • • • • • • • • Current Mode Control Internal 100V Start-up Bias Regulator 3A Compound Main Gate Driver High Bandwidth Opto-coupler Interface Programmable Line Under-Voltage Lockout (UVLO) with Adjustable Hysteresis Versatile Dual Mode Over-Current Protection with hiccup delay timer Programmable Overlap or Deadtime between the Main and Active Clamp Outputs Programmable Maximum Duty Cycle Clamp Programmable Soft-start Leading Edge Blanking Resistor Programmed 1MHz Capable Oscillator Oscillator Sync I/O Capability Precision 5V Reference PACKAGES • • TSSOP-16 WSON-16 (5x5 mm) Thermally Enhanced Typical Application Circuit VIN 36 - 78V VOUT 3.3V T1 CS VCC CS LM5026 VIN UVLO OUT_A TIME RES RT OUT_B ERROR AMP and ISOLATION REF COMP SYNC DCL SS PGND AGND SYNC I/O Figure 1. Simplified Forward Power Converter with Active Clamp Reset 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Connection Diagram VIN 1 16 DCL UVLO 2 15 SYNC 16 DCL VIN 1 UVLO 2 15 SYNC CS 3 CS 3 14 RT RES 4 13 COMP TIME 5 12 SS REF 6 11 AGND VCC 7 10 PGND OUT_A 8 9 OUT_B RES 4 TIME 5 14 RT EP REF 6 11 AGND VCC 7 10 PGND OUT_A 8 Figure 2. 16-Lead TSSOP 13 COMP 12 SS 9 OUT_B Figure 3. 16-Lead WSON PIN DESCRIPTIONS 2 Pin Name 1 VIN 2 UVLO 3 CS 4 5 Description Application Information Input Voltage Source Input to the Start-up Regulator. Operating input range is 13V to 100V with transient capability to 105V. For power sources outside of this range, the LM5026 can be biased directly at VCC by an external regulator. Line Under-Voltage Lockout An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4V threshold the VCC and REF regulators are enabled. At the 1.25V threshold the SS pin is released and the device enters the active mode. Current Sense input for current mode control and current limit If CS exceeds 0.5V the output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds CS low for 100nS after OUT_A switches high to blank leading edge transients. RES Restart Timer If cycle-by-cycle current limit is reached during any cycle, a 10uA current is sourced to the RES pin capacitor. If the RES capacitor voltage reaches 2.5V, the soft-start capacitor will be fully discharged and then released with a pull-up current of 1uA. After the first output pulse at OUT_A (when SS =1.4V), the SS pin charging current will revert back to 50 µA. TIME Gate Drive Overlap or Deadtime An external resistor (RSET) sets either the overlap time or deadtime for the Control active clamp output. An RSET resistor connected between TIME and AGND produces in-phase OUT_A and OUT_B pulses with overlap. An RSET resistor connected between TIME and REF produces out-of-phase OUT_A and OUT_B pulses with deadtime. 6 REF Output of 5V Reference 7 VCC Output of the high voltage start- If an auxiliary winding raises the voltage on this pin above the regulation up regulator. The VCC voltage setpoint, the internal start-up regulator will shutdown, thus reducing the IC is regulated to 7.6 V. power dissipation. 8 OUT_A Main Output Driver Output of the main switch PWM gate driver. Capable of 3A peak sink current. 9 OUT_B Active Clamp Output Driver Output of the active clamp switch gate driver. Capable of 0.5A peak source and sink current. 10 PGND Power Ground Connect directly to Analog Ground 11 AGND Analog Return Connect directly to Power Ground. 12 SS Soft-start An external capacitor and an internal 50 µA current source set the soft-start ramp. The SS current source is reduced to 1 µA following a restart event. The soft-stop discharge current is 50 µA. 13 COMP Input to the Pulse Width Modulator The external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input current, while 1mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the ac voltage across the opto-coupler detector. 14 RT Oscillator Frequency Control Normally biased at 2V. The total external resistance connected between RT and AGND sets the internal oscillator frequency. 15 SYNC Oscillator Synchronization Input/Output The internal oscillator can be synchronized to an external clock with an external pull-down device. Multiple LM5026 devices can be synchronized together by connection of their SYNC pins. 16 DCL Maximum Duty Cycle Control An external resistor divider connected from RT to AGND sets the maximum output duty cycle for OUT_A. Maximum output current is 10mA. Locally decouple with a 0.1µF capacitor. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin EP Name Description Application Information Exposed Pad Exposed Pad, underside of (WSON WSON package Package Only) Connect to system ground plane for reduced thermal resistance. Block Diagram 7.6V BIAS REGULATOR VIN VCC VCC UVLO STANDBY REF 5V REFERENCE UVLO 1.25V LOGIC HYSTERESIS (20 PA) SHUTDOWN VCC THERMAL LIMIT 0.4V/0.3V OUT_A DRIVER RT CLK OSCILLATOR AND DUTY CYCLE LIMITER SYNC DCL S SLOPE COMP RAMP 5V Q DEADTIME OR OVERLAP CONTROL TIME VCC R 45 PA 0 5k OUT_B DRIVER COMP 2R 1.4V R PGND PWM 1:1 AGND SS CURRENT LIMIT 2k CS 5V CURRENT LIMITING (10 PA) 0.5V OUT_A + LEB CURRENT LIMIT RESTART TIMER & SS CONTROL 5V 5V SS RESTART DELAY (1 PA) SOFT-START (50 PA) SS RES NOT CURRENT LIMITING (10 PA) SOFT-STOP (50 PA) Figure 4. Simplified Block Diagram Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 3 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 105V VCC to GND -0.3V to 16V CS to GND -0.3 to 1.0V COMP Input Current 10mA All other inputs to GND -0.3 to 7V ESD Rating (3) Human Body Model 2kV Storage Temperature Range -65°C to 150°C Junction Temperature 150°C (1) (2) (3) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Operating Ratings (1) VIN Voltage 13 to 100V External Voltage Applied to VCC 8V to 15V Operating Junction Temperature -40°C to +125°C (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. Electrical Characteristics Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 30.0kΩ, RSET = 34.8kΩ) unless otherwise stated (1) Symbol Parameter Conditions Min Typ Max 7.9 Units Startup Regulator VCC Reg I-VIN VCC Regulation No Load 7.3 7.6 VCC Current Limit See (2) 20 25 V Startup Regulator Leakage (external Vcc Supply) VIN = 100V 165 500 µA Shutdown Current (Iin) UVLO = 0V 350 450 µA mA VCC Supply VCC Under-voltage Lockout Voltage (positive going Vcc) VCC Reg 220mV VCC Reg 120mV VCC Under-voltage Hysteresis 1.0 1.5 VCC Supply Current (ICC) Cgate = 0, UVLO = 1.3V V 2.0 V 4.2 mA Reference Supply VREF Ref Voltage IREF = 0 mA Ref Voltage Regulation IREF = 0 to 10mA Ref Current Limit 4.85 5 5.15 V 25 50 mV 10 20 0.3 0.4 mA UVLO Shutdown/Standby Undervoltage Shutdown Threshold (1) (2) 4 0.5 V Min and Max limits are 100% production tested at 25 ºC. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Device thermal limitations may limit usable range. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 30.0kΩ, RSET = 34.8kΩ) unless otherwise stated (1) Symbol Parameter Conditions Min Undervoltage Shutdown Hysteresis Typ Max Units 0.1 V Undervoltage Standby Threshold 1.21 1.25 1.29 V Undervoltage Standby Hysteresis Current Source 16 20 24 µA 0.45 0.5 0.55 V Current Limit Cycle by Cycle Threshold Voltage ILIM Delay to Output CS step from 0 to 0.6V Time to onset of OUT transition (90%) Cgate=0 Leading Edge Blanking Time CS Sink Impedance (clocked) 40 70 ICS = 10mA ns 100 130 ns 30 65 Ω Over Current Restart Restart Threshold 2.4 2.55 2.7 V Fault Charging Current 7.5 10 12.5 µA Discharging Current 7.5 10 12.5 µA Soft-start Current Source 38 50 58 Soft-stop Current Sink 38 50 58 Soft-start Current Source following a restart event 0.6 1 1.3 Soft-Start µA Oscillator Frequency1 RT = 30.0 kΩ 180 200 220 kHz Frequency2 RT = 10.0 kΩ 520 590 660 kHz SYNC Source Current SYNC Sink Impedance Can sync up to 5 like controllers minimum Sync Threshold (falling) 200 µA 100 Ω 1.4 Sync Pulse Width Minimum V 15 ns PWM Comparator Delay to Output CS stepped, Time to onset of OUT_A transition low 40 Mimimum Duty Cycle ICOMP = 1mA Maximum Duty Cycle Limit 1 UVLO=1.3V, COMP = open, VDCL = 2.5V 80 % Maximum Duty Cycle Limit 2 UVLO=1.3V, COMP = open, VDCL = VRT x 0.875 70 % Maximum Duty Cycle Limit 3 UVLO=2.92V, COMP = open, VDCL = 2.5V 40 % 1.4 V 0 SS to PWM Offset COMP Input Impedance Small signal impedance Slope Compensation Amplitude ns Delta increase at PWM comparator to CS % Ω 1700 75 90 115 mV Output Section Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 5 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 30.0kΩ, RSET = 34.8kΩ) unless otherwise stated (1) Symbol Typ Max Units OUT_A High Saturation Parameter MOS Device @ Iout = -10mA, Conditions Min 5 10 Ω OUTPUT_A Peak Current Sink Bipolar Device @ Vcc/2 3 OUT_A Low Saturation MOS Device @ Iout = 10mA, 6 OUTPUT_A Rise Time Cgate = 2.2nF 20 OUTPUT_A Fall Time Cgate = 2.2nF 15 OUT_B High Saturation Iout = -10mA, 10 20 Ω OUT_B Low Saturation Iout = 10mA, 10 20 Ω OUTPUT_B Rise Time Cgate = 470pF 15 ns OUTPUT_B Fall Time Cgate = 470pF 15 ns A 9 Ω ns ns Output Timing Control Overlap Time RSET = 34.8 kΩ connected to GND, 50% to 50% transitions 70 100 130 ns Deadtime RSET = 30.0 kΩ connected to REF, 50% to 50% transitions 70 100 130 ns 150 165 °C 25 °C PW0016A Package 125 °C/W NHQ0016A Package 32 °C/W Thermal Shutdown TSD Thermal Shutdown Temp. Thermal Shutdown Hysteresis Thermal Resistance θJA 6 Junction to Ambient Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 Typical Performance Characteristics VCC Regulator Start-up Characteristics, VCC vs Vin VCC vs ICC 10 16 14 VIN 8 12 VCC (V) VCC (V) 10 8 VCC 6 6 4 4 2 2 0 0 2 4 6 8 10 12 14 0 16 5 10 20 25 30 Figure 5. Figure 6. VREF vs IREF Soft-start, Soft-stop and Restart Current vs Temperature 1.4 54 SOFT-START & STOP CURRENT (PA) 6 5 4 3 2 1 0 0 5 35 ICC (mA) VIN (V) VREF (V) 15 10 15 20 25 1.3 52 SOFT-STOP 1.2 50 SOFT-START 1.1 48 1.0 46 RESTART 44 0.9 42 0.8 40 -50 -25 RESTART CURRENT (PA) 0 0.7 0 25 50 75 100 125 150 TEMPERATURE (oC) IREF (mA) Figure 7. Figure 8. Oscillator Frequency vs RT Oscillator Frequency vs Temperature OSCILLATOR FREQUENCY (kHz) 210 208 206 204 202 200 198 196 194 192 190 -50 0 50 100 150 TEMPERATURE (oC) Figure 9. Figure 10. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 7 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Overlap Time vs RSET Overlap Time vs Temperature 120 400 115 350 110 300 OVERLAP TIME (ns) OVERLAP TIME (ns) RSET to AGND 250 200 150 105 100 95 100 90 50 85 RSET = 34.8 k: 0 0 20 40 80 60 100 80 -50 120 -25 0 25 50 75 100 125 150 RSET (k:) TEMPERATURE ( C) Figure 11. Figure 12. Deadtime vs RSET Deadtime vs Temperature o 120 400 115 350 RSET to REF 110 DEAD TIME (ns) DEADTIME (ns) 300 250 200 150 105 100 95 100 90 50 85 RSET = 30.0 k: 0 0 20 40 60 80 100 80 -50 120 RSET (k:) 25 50 75 100 125 150 TEMPERATURE ( C) Figure 13. Figure 14. Max Duty Cycle vs UVLO Max Duty Cycle vs DCL 100 90 90 DCL = 2.5V UVLO = 1.26V 80 MAX DUTY CYCLE (%) 80 MAX DUTY CYCLE (%) 0 o 100 70 60 50 40 30 70 60 50 40 30 20 20 10 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 UVLO (V) 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DCL (V) Figure 15. 8 -25 Figure 16. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 Typical Performance Characteristics (continued) COMP Current vs INV PWM Comparator Voltage 800 -40°C COMP CURRENT (PA) 700 25°C 85°C 600 125°C 500 400 300 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 INVERTING INPUT TO PWM COMPARATOR (V) Figure 17. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 9 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com DETAILED OPERATING DESCRIPTION The LM5026 PWM controller contains all of the features necessary to implement power converters utilizing the active clamp reset technique with current mode control. With the active clamp reset, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp reset techniques. The LM5026 provides two control outputs, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The device can be configured to drive either a P-Channel or N-Channel clamp switch. The main switch gate driver features a compound configuration consisting of both MOS and bipolar devices, which provide superior gate drive characteristics. The LM5026 can be configured to operate with bias voltages over a wide input range from 8V to 100V. Additional features include programmable maximum duty cycle, line undervoltage lockout, cycle-by-cycle current limit, hiccup mode fault protection with adjustable delays, PWM slope compensation, soft-start, a 1MHz capable oscillator with synchronization Input / Output capability, precision reference and thermal shutdown. High Voltage Start-Up Regulator The LM5026 contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected directly to a nominal 48V dc line voltage. The regulator output (VCC) is internally current limited to 20mA. When power is applied and the UVLO pin potential is greater than 0.4V, the regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended capacitance range for the VCC regulator is 0.1µF to 100µF. The VCC regulator provides power to the internal voltage reference, PWM controller and gate drivers. The controller outputs are enabled when the voltage on the VCC pin reaches the regulation point of 7.6V, the internal voltage reference (REF) reaches its regulation point of 5V and the UVLO voltage is greater than 1.25V. In typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8V to shut off the internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the controller’s power dissipation. The external VCC capacitor must be sized such that the current delivered from the capacitor and the VCC regulator will maintain a VCC voltage greater than 6.2V during the initial start-up. During a fault mode when the converter auxiliary winding is inactive, external current draw on the VCC line should be limited such that the power dissipated in the start-up regulator does not exceed the maximum power dissipation of the IC package. An external start-up or bias regulator can be used to power the LM5026 instead of the internal start-up regulator by connecting the VCC and the VIN pins together and connecting an external bias supply to these two pins. Line Under-Voltage Detector The LM5026 contains a dual level Under-Voltage Lockout (UVLO) circuit. When the UVLO pin voltage is below 0.4V the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.4V but less than 1.25V, the controller is in standby mode. In standby mode the VCC and REF bias regulators are active while the controller outputs are disabled. When the VCC and REF outputs exceed the VCC and REF undervoltage thresholds and the UVLO pin voltage is greater than 1.25V, the outputs are enabled and normal operation begins. An external set-point voltage divider from VIN to GND can be used to set the operational range of the converter. The divider must be designed such that the voltage at the UVLO pin will be greater than 1.25V when VIN is in the desired operating range. UVLO hysteresis is accomplished with an internal 20uA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V threshold, the current source is turned off causing the voltage at the UVLO pin to fall. The hysteresis of the 0.4V shutdown comparator is fixed at 100mV. The UVLO pin can also be used to implement various remote enable / disable functions. Pulling the UVLO pin below the 0.4V threshold totally disables the controller. Pulling the UVLO pin to a potential between 1.25 and 0.4V places the controller in standby with the VCC and REF regulators operating. Turning off a converter by forcing the UVLO pin to the standby condition provides a controlled soft-stop. The controller outputs are not directly disabled in standby mode, rather the soft-start capacitor is discharged with a 50µA sink current. Discharging the soft-start capacitor gradually reduces the PWM duty cycle to zero, providing a slow controlled discharge of the power converter output filter. This controlled discharge can help prevent uncontrolled behavior of self-driven synchronous rectifiers during turn-off. 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 PWM Outputs The relative phase of the main switch gate driver OUT_A and active clamp gate driver OUT_B can be configured for multiple applications. For active clamp configurations utilizing a ground referenced P-Channel clamp switch, the two outputs should be in phase, with the active clamp output overlapping the main output. For active clamp configurations utilizing a high side N-Channel switch, the active clamp output should be out of phase with main output and there should be a dead time between the two gate drive pulses. A distinguishing feature of the LM5026 is the ability to accurately configure either deadtime (both off) or overlap time (both on) of the gate driver outputs. The overlap / deadtime magnitude is controlled by the resistor value (RSET) connected to the TIME pin of the controller. The opposite end of the resistor can be connected to either REF for deadtime control or to AGND for overlap control. The internal configuration detector senses the direction of current flow in the TIME pin resistor and configures the phase relationship of the main and active clamp outputs. OUT_A P-Channel Active Clamp (RSET to GND) K1 * RSET K1 * RSET OUT_B OUT_A N-Channel Active Clamp (RSET to REF) K2 * RSET K2 * RSET OUT_B Figure 18. PWM Output Phasing / Timing The rising edge overlap or deadtime and the falling edge overlap or deadtime are identical and are independent of operating frequency or duty cycle. The magnitude of the overlap/deadtime can be calculated as follows: Overlap Time = 2.8 x RSET + 2 where • • RSET in kΩ overlap is in ns (1) . Deadtime = 2.9 x RSET + 14 where • • RSET in kΩ deadtime is in ns (2) Gate Driver Outputs The LM5026 provides two gate driver outputs, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The main gate driver features a compound configuration, consisting of both MOS and bipolar devices, which provide superior gate drive characteristics. The bipolar device provides most of the drive current capability and sinks a relatively constant current, which is ideal for driving large power MOSFETs. As the switching event nears conclusion and the bipolar device saturates, the internal MOS device provides a low impedance to compete the switching event. During turn-off at the Miller plateau region, typically between 2V - 4V, the voltage differential between the output and PGND is small and the current source characteristic of the bipolar device is beneficial to reduce the transition time. During turn-on, the resistive characteristics of a purely MOS gate driver is adequate since the supply to output voltage differential is fairly large in the Miller region. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 11 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com VCC LM5026 PWM OUT_A PGND Figure 19. Compound Gate Driver PWM Comparator/Slope Compensation The PWM comparator modulates the pulse width of the controller output by comparing the current sense ramp signal to the loop error signal. This comparator is optimized for speed in order to achieve minimum controllable duty cycles. The loop error signal is input into the controller in the form of a control current into the COMP pin. The COMP pin control current is internally mirrored by a matched pair of NPN transistors which sink current through a 5 kΩ resistor connected to the 5V reference. The resulting error signal passes through a 1.4V level shift and a gain reducing 3:1 resistor divider before being applied to the pulse width modulator. The opto-coupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is controlled by a current input, the potential difference across the optocoupler detector is nearly constant. The bandwidth limiting phase delay which is normally introduced by the significant capacitance of the opto-coupler is greatly reduced. Greater system loop bandwidth can be realized, since the bandwidth-limiting pole associated with the opto-coupler is now at a much higher frequency. The PWM comparator polarity is configured such that with no current into the COMP pin, the controller produces the maximum duty cycle at the main gate driver output. REF CURRENT SENSE RAMP 5V + 5k _ 1.4V COMP PWM COMPARATOR 2R LM431 FB Potential across Optocoupler detector is constant R 1:1 SOFT-START LM5026 Figure 20. Opto-Coupler to LM5026 COMP Interface For duty cycles greater than 50 percent, current mode control circuits are subject to sub-harmonic oscillation. By adding an additional fixed slope voltage ramp signal (slope compensation) to the current sense signal, this oscillation can be avoided. The LM5026 integrates this slope compensation by summing a current ramp generated by the oscillator with the current sense signal. The PWM comparator ramp signal is a combination of the current waveform at the CS pin, and an internally generated slope compensation ramp derived from the oscillator. The internal ramp has an amplitude of 0 to 45 µA which is sourced into an internal 2 kΩ resistor, plus the external impedance at the CS pin. Additional slope compensation may be added by increasing the source impedance of the current sense signal. Maximum Duty Cycle Clamp Controlling the maximum duty cycle of an active clamp reset PWM controller is necessary to limit the voltage stress on the main and active clamp MOSFETs. The relationship between the maximum drain-source voltage of the MOSFETs and the maximum PWM duty cycle is provided by the following equation: Vds(max) = VIN 1 - D(max) 12 (3) Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 The main output (OUT_A) duty cycle is normally controlled by the control current sourced into the COMP pin from the external feedback circuit. When the feedback demands maximum output from the converter, the duty cycle will be limited by one of two circuits within the LM5026: the user programmable duty cycle clamp and the voltage-dependent duty cycle limiter, which varies inversely with the input line voltage. Programmable Duty Cycle Clamp – The maximum allowed duty cycle can be programmed by setting a voltage at the DCL pin to a value less than 2V. The recommended method to set the DCL pin voltage is with a resistor divider connected from the RT pin to AGND. The voltage at the RT pin is internally regulated to 2V, while the current sourced from the RT pin sets the oscillator frequency. The maximum duty can be programmed, according to the following equation: Programmable Duty Cycle Clamp = RT2 RT1 + RT2 80% x (4) RT OSCILLATOR FREQUENCY INVERSELY PROPORTIONAL TO: RT1 + RT2 RT1 DCL MAX DUTY CYCLE CLAMP SET TO: 80% x RT2 RT1 + RT2 RT2 LM5026 AGND Figure 21. Programming oscillator Frequency and Maximum Duty Cycle Clamp Line Voltage Duty Cycle Limiter - The maximum duty cycle for the main output driver is also limited by the voltage at the UVLO pin, which is normally proportional to VIN. The controller outputs are disabled until the UVLO pin voltage exceeds 1.25V. At the minimum operating voltage (when UVLO = 1.25V) the maximum duty cycle starts at the duty cycle clamp level programmed by the DCL pin voltage (80% or less). As the line voltage increases, the maximum duty cycle decreases linearly with increasing UVLO voltage, as illustrated in Figure 22. Ultimately the duty cycle of the main output is controlled to the least of the following three variables: the duty cycle controlled by the PWM comparator, the programmable maximum duty cycle clamp, or the line voltage dependent duty cycle limiter. MAXIMUM DUTY CYCLE (%) 100 Programmable Duty Cycle Clamp 80 Line Voltage Duty Cycle Limiter 60 40 20 1.25V 0 0 1.0 2.0 3.0 4.0 5.0 UVLO PIN VOLTAGE (V) Figure 22. Maximum Duty Cycle vs UVLO Voltage Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 13 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Soft-Start/Soft-Stop The soft-start circuit allows the regulator to gradually reach a steady state operating point, thereby reducing startup stresses and current surges. Upon turn-on, the SS pin capacitor is discharged by an internal switch. When the UVLO, VCC and REF pins reach their operating thresholds, the SS capacitor is released and charged with a 50uA current source. The PWM comparator control voltage is clamped to the SS pin voltage. When the PWM input reaches 1.4V, output pulses commence with slowly increasing duty cycle. The voltage at the SS pin eventually increases to 5V, while the voltage at the PWM comparator increases to the value required for regulation determined by the voltage feedback loop. If the UVLO pin voltage falls below the 1.25V standby threshold but above the 0.4V shutdown threshold, the 50uA SS pin source current is disabled and a 50uA sink current discharges the soft-start capacitor. As the SS voltage falls and clamps the PWM comparator input, the PWM duty cycle will gradually fall to zero. This soft-stop feature produces a gradual reduction of the power converter output voltage. This gradual discharge of the output filter prevents oscillations in the self-driven synchronous rectifiers on the secondary side of the converter during turn-off. Current Sense/Current Limit The CS input provides a control ramp for the pulse width modulator and current limit detection for overload protection. If the sensed voltage at the CS comparator exceeds 0.5V the present cycle is terminated (cycle-bycycle current limit mode). A small RC filter, located near the controller, is recommended for the CS input pin. An internal FET connected to the CS input discharges the current sense filter capacitor at the conclusion of every cycle to improve dynamic performance. This same FET remains on for an additional 100nS at the start of each main switch cycle to attenuate the leading edge spike in the current sense signal. The CS comparator is very fast and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the pins of the LM5026 (CS and AGND pins). If a current sense transformer is used, both leads of the transformer secondary should be routed to the filter network, which should be located close to the IC. If a sense resistor located in the source of the main switch MOSFET is used for current sensing, a low inductance type of resistor is required. When designing with a current sense resistor, all of the noise sensitive low power ground connections should be connected together near the AGND pin and a single connection should be made to the power ground (sense resistor ground point). Overload Protection Timer The LM5026 provides a current limit restart timer to disable the outputs and force a delayed restart (hiccup mode) if a current limit condition is repeatedly sensed. The number of cycle-by-cycle current limit events required to trigger the restart is programmable by means of an external capacitor at the RES pin. During each PWM cycle the LM5026 either sources or sinks current from the RES pin capacitor. If no current limit is detected during a cycle, a 10uA discharge current sink is enabled to hold the RES pin at ground. If a current limit is detected, the 10uA sink current is disabled and a 10 uA current source causes the voltage at RES pin to gradually increase. In the event of an extended overload condition, the LM5026 protects the converter with cycle-by-cycle current limiting while the voltage at RES pin increases. If the RES voltage reaches the 2.5V threshold, the following restart sequence occurs (see Figure 23): • The RES capacitor and SS capacitors are fully discharged. • The soft-start current source is reduced from 50 µA to 1 µA • The SS capacitor voltage slowly increases. When the SS voltage reaches 1.4V, the PWM comparator will produce the first output pulse. After the first pulse occurs, the SS source current reverts to the normal 50 µA level. The SS voltage increases at its normal rate gradually increasing the duty cycle of the output drivers • If the overload condition persists after restart, cycle-by-cycle current limiting will cause the voltage on the RES capacitor to increase again, repeating the hiccup mode sequence. • If the overload condition no longer exists after restart, the RES pin will be held at ground by the 10 µA current sink and normal operation resumes. The overload timer function is very versatile and can be configured for the following modes of protection: 1. Cycle-by-cycle only: The hiccup mode can be completely disabled by connecting the RES pin to AGND. In this configuration, the cycle-by-cycle protection will limit the output current indefinitely and no hiccup 14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 sequences will occur. 2. Hiccup only: The timer can be configured for immediate activation of a hiccup sequence upon detection of an overload by leaving the RES pin open circuit. 3. Delayed Hiccup: The most common configuration as previously described, is a programmed interval of cycle-by-cycle limiting before initiating a hiccup mode restart. The advantage of this configuration is short term overload conditions will not cause a hiccup mode restart, however during extended overload conditions the average dissipation of the power converter will be very low. 4. Externally Controlled Hiccup: The RES pin can also be used as an input. By externally driving the pin to a level greater than the 2.5V hiccup threshold, the controller will be forced into the delayed restart sequence. If the RES pin is used as an input, the driving source should be current limited to less than 5 mA. For example, the external trigger for a delayed restart sequence could come an over-temperature protection circuit. 2.5V Current Limit Detected RES 0V 5.0V 50 PA SS 1 PA # 1.4V OUTA t1 t2 t3 Figure 23. Hiccup Over-Load Restart Timing Oscillator and Sync Capability The LM5026 oscillator frequency is set by the external resistance connected between the RT pin and ground (AGND). To set a desired oscillator frequency (F) the necessary value of total RT resistance can be calculated from: RT = 1 F x 167 x 10 -12 (5) The RT resistor(s) should be located very close to the device and connected directly to the pins of the IC (RT and AGND). The SYNC pin can be used to synchronize the internal oscillator to an external clock. An open drain output is the recommended interface between the external clock to the LM5026 SYNC pin as illustrated in Figure 24. The clock pulse width must be greater than 15 ns. The external clock frequency must be a higher than the free running frequency set by the RT resistance. LM5026 SYNC AGND Figure 24. Sync from External Clock Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 15 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com LM5026 SYNC LM5026 SYNC UP TO 5 TOTAL DEVICES Figure 25. Sync from Multiple Devices Multiple LM5026 devices can be synchronized together simply by connecting the devices SYNC pins together as shown in Figure 25. Care should be taken to ensure the ground potential differences between devices are minimized. In this configuration all of the devices will be synchronized to the highest frequency device. The internal block diagram of the oscillator and synchronization circuit is shown in Figure 26. The SYNC I/O pin is a CMOS buffer with pull-up current limited to 200 µA. If an external device forces the SYNC pin low before the internal oscillator ramp completes its charging cycle, the ramp will be reset and another cycle begins. If the SYNC pins of multiple LM5026 devices are connected together, the first SYNC pin that pulls low will reset the oscillator RAMP of all other devices. All controllers will operate in phase when synchronized using the SYNC I/O feature. Up to five LM5026 devices can be synchronized using this technique. SYNC 200P I = f (RT) 2V Q S Q R CLK DEADTIME ONE-SHOT Figure 26. Oscillator Sync I/O Block Diagram Thermal Protection Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power standby state with the output drivers and the bias regulator disabled. The device will restart after the thermal hysteresis (typically 25°C). During thermal shutdown, the soft-start capacitor is fully discharged and the controller follows a normal start-up sequence after the junction temperature falls to the operating level. 16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 Applications Information LINE INPUT (VIN) The LM5026 contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected directly to a nominal 48V line voltage. The voltage applied to the VIN pin can vary in the range of 13 to 100V with transient capability to 105V. When power is applied and the UVLO pin potential is greater than 0.4V, the VCC regulator is enabled and sources current into an external capacitor connected to the VCC pin. When the voltage on the VCC pin reaches the regulation point of 7.7V, the internal voltage reference (REF) is enabled. The reference regulation set point is 5V. The controller outputs are enabled when the UVLO pin potential is greater than 1.25V. In typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8V to shut off the internal start-up regulator. It is recommended a filtering circuit shown in Figure 27 be used to suppress transients, which may occur at the input supply, in particular when VIN is operated close to the maximum operating rating. VPWR 50 VIN 0.1 PF LM5026 Figure 27. Input Transient Protection FOR APPLICATION > 100V For applications where the system input voltage exceed 100V or IC power dissipation is a concern, the LM5026 can be powered from an external start-up regulator as shown in Figure 28. In this configuration, the VIN and the VCC pins should be connected together, which allows the LM5026 to be operated below 13V. The voltage at the VCC pin must be greater than 8V yet not exceed 15V. An auxiliary winding can be used to reduce the dissipation in the external regulator once the power converter is active. VPWR 9V 0.1 VIN 8V - 15V (from aux winding) VCC C1 LM5026 Figure 28. Start-Up Regulator for VPWR >100V Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 17 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com UNDER-VOLTAGE LOCKOUT (UVLO) When the UVLO pin voltage is below 0.4V the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.4V but less than 1.25V the controller is in standby mode. When the UVLO pin voltage is greater than 1.25V the controller is fully enabled. Typically, two external resistors program the minimum operational voltage for the power converter as shown in Figure 29. When UVLO pin voltage is above the 1.25V threshold, an internal 20 μA current source is enabled to raise the voltage at the UVLO pin, thus providing threshold hysteresis. Resistance values for R1 and R2 can be determined from: V R1 = HYS 20 mA where • VHYS is the desired UVLO hysteresis at VPWR (6) . 1.25 ´ R1 VPWR - 1.25 R2 = where • VPWR is the desired turn-on voltage (7) For example, if the LM5026 is to be enabled when VPWR reaches 33V, and disabled when VPWR is decreased to 30V, R1 calculates to 150 kΩ, and R2 calculates to 5.9 kΩ. The voltage at the UVLO pin should not exceed 6V at any time. Be sure to check both the power and voltage rating for the selected R1 resistor. Remote configuration of the controller’s operational modes can be accomplished with open drain device(s) connected to the UVLO pin as shown in Figure 30. VPWR LM5026 20 PA R1 UVLO Enable Output Drivers Enable VCC & VREF Regulators 1.25V R2 0.4V Figure 29. Basic UVLO Configuration VPWR LM5026 20 PA R1 UVLO Enable 1.25V OFF R2 STANDBY Standby 0.4V Figure 30. Remote Standby and Disable Control OSCILLATOR (RT, SYNC) Oscillator (RT, SYNC) The oscillator frequency is generally selected in conjunction with the design of the system magnetic components along with the volume and efficiency goals for a given power converter design. The total RT resistance at the RT pin sets the oscillator frequency. The RT resistors should be one of the first components placed and connected when designing the PC board. Direct, short connections to each side of the RT resistors (RT, DCL and AGND pins) are recommended . 18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 The SYNC pin can be used to synchronize the internal oscillator to an external clock. An open drain output is the recommended interface from the external clock to the SYNC pin. The clock pulse width should be greater than 15 ns. The external clock must be a higher frequency than the free running frequency set by the RT resistor. Multiple LM5026 devices can be synchronized together simply by connecting the devices SYNC pins together. Care should be taken to ensure the ground potential differences between devices are minimized. In this configuration all of the devices will be synchronized to the highest frequency device. VOLTAGE FEEDBACK (COMP) The COMP pin is designed to accept the voltage loop feedback error signal from the regulated output via an error amplifier and (typically) an optocoupler. In a typical configuration, VOUT is compared to a precision reference voltage by the error amplifier. The amplifier’s output drives the optocoupler, which in turn drives the COMP pin. The parasitic capacitance of the optocoupler often limits the achievable loop bandwidth for a given power converter. The optocoupler LED and detector junction capacitance produce a low frequency pole in the voltage regulation loop. The LM5026 current controlled optocoupler interface (COMP) previously described, greatly increases the pole frequency associated with the optocoupler. CURRENT SENSE (CS) The CS pin receives an input signal representative of the transformer primary current, either from a current sense transformer (Figure 31) or from a resistor in series with the source of the primary switch (Figure 32). In both cases the sensed current creates a ramping voltage across R1, while the RF/CF filter suppresses noise and transients. R1, RF and CF should be as physically close to the LM5026 as possible, and the ground connection from the current sense transformer, or R1, should be a dedicated track to the AGND pin. The current sense components must provide >0.5V at the CS pin when an over-current condition exists. Current Sense Power Transformer VPWR VIN RF CS LM5026 R1 CF AGND Q1 Q2 OUTA OUTB Figure 31. Current Sense Using a Current Sense Transformer Power Transformer VPWR VIN Q1 LM5026 Q2 OUTA RF CS CF R1 AGND OUTB Figure 32. Current Sense Using a Source Sense Resistor (R1) Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 19 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com HICCUP MODE CURRENT LIMIT RESTART (RES) The basic operation of the hiccup mode current limit restart is described in the functional description. The delay time to restart is programmed with the selection of the RES pin capacitor CRES as illustrated in Figure 23. In the case of continuous cycle-by-cycle current limit detection at the CS pin, the time required for CRES to reach the 2.5V hiccup mode threshold is: t1 = CRES x 2.5 10 PA 5 = 2.5 x 10 x CRES (8) For example, if CRES = 0.01 µF the time t1 is approximately 2.5 ms. 20 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 The cool down time, t2 is set by the soft-start capacitor (CSS) and the internal 1 µA SS current source, and is equal to: t2 = CSS x 1.4V 1 PA 6 = 1.4 x 10 x CSS (9) If CSS = 0.01 µF, t2 is ≈14 ms. The soft-start time t3 is set by the internal 50 µA current source, and is equal to: t3 = CSS x 3.5V 50 PA 4 = 7 x 10 x CSS (10) The time t2 provides a periodic cool-down time for the power converter in the event of a sustained overload or short circuit. This results in lower average input current and lower power dissipated within the power components. It is recommended that the ratio of t2/(t1 + t3) be in the range of 5 to 10 to make good use of this feature. If the application requires no delay from the first detection of a current limit condition to the onset of the hiccup mode (t1 = 0), the RES pin can be left open (no external capacitor). If it is desired to disable the hiccup mode current limit operation, the RES pin should be connected to ground (AGND). SOFT-START (SS) An internal current source and an external soft-start capacitor determines the time required for the output duty cycle to increase from zero to its final value for regulation. The minimum acceptable time is dependent on the output capacitance and the response of the feedback loop. If the soft-start time is too quick, the output could overshoot its intended voltage before the feedback loop can regulate the PWM controller. After power is applied and the controller is fully enabled, the voltage at the SS pin ramps up as CSS is charged by an internal 50 µA current source. The voltage at the output of the COMP pin current mirror is clamped to the same potential as the SS pin by a voltage buffer with a sink-only output stage. When the SS voltage reaches ≈1.4V, PWM pulses appear at the driver output with very low duty cycle. The PWM duty cycle gradually increases as the voltage at the SS pin charges to ≈5.0V. VOLTAGE DEPENDENT MAXIMUM DUTY CYCLE As the input source VPWR increases the voltage at the UVLO pin increases proportionately. To limit the Volt x Seconds applied to the transformer, the maximum allowed PWM duty cycle decreases as the UVLO voltage increases. If it is desired to increase the slope of the voltage limited duty cycle characteristic, two possible configurations are shown in Figure 33. After the LM5026 is enabled, the zener diode causes the UVLO pin voltage to increase more rapidly with increasing input voltage (VPWR). The voltage dependent maximum duty cycle clamp varies with the UVLO pin voltage according to the following equation: Voltage-Dependent Duty Cycle (%) = 107 - 21.8 X UVLO (11) Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 21 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com VPWR R1A LM5026 20 PA R1B UVLO Z1 1.25V R2 Max. Duty Cycle Limiter VPWR Z1 LM5026 20 PA R1 UVLO 1.25V R2 Max. Duty Cycle Limiter Figure 33. Altering the Slope of Duty Cycle vs. VPWR Programmable Maximum Duty Cycle Clamp (DCL) When the UVLO pin is biased at 1.25V (minimum operating level), the maximum duty cycle of OUT_A is limited by the duty cycle of the internal clock signal. The duty cycle of the internal clock can be adjusted by programming a voltage set at the DCL pin. The default maximum duty cycle (80%) can be selected by connecting the DCL pin to the RT pin. The DCL pin should not be left open. A small decoupling capacitor located close to the DCL pin is recommended. The oscillator frequency set resistance (RT) must be determined first before programming the maximum duty cycle. Following the selection of the total RT resistance, the ratio of the RT resistors can be designed to set the desired maximum duty cycle. As the UVLO pin voltage increases from 1.25V, the maximum duty cycle is reduced by the voltage dependent duty cycle limiter previously as described and illustrated in Figure 22. Printed Circuit Board Layout The LM5026 Current Sense and PWM comparators are very fast, and respond to short duration noise pulses. The components at the CS, COMP, SS, DCL, UVLO, TIME, SYNC and the RT pins should be as physically close as possible to the IC, thereby minimizing noise pickup on the PC board tracks. Layout considerations are critical for the current sense filter. If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense filter components and to the IC pins. The ground side of each transformer should be connected via a dedicated PC board track to the AGND pin, rather than through the ground plane. If the current sense circuit employs a sense resistor in the drive transistor source, low inductance resistor should be used. In this case, all the noise sensitive low current ground tracks should be connected in common near the IC, and then a single connection made to the power ground (sense resistor ground point). The gate drive outputs of the LM5026 should have short direct paths to the power MOSFETs in order to minimize inductance in the PC board traces. 22 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 The two ground pins (AGND, PGND) must be connected together with a short direct connection to avoid jitter due to relative ground bounce. If the internal dissipation of the LM5026 produces high junction temperatures during normal operation, the use of multiple vias under the IC to a ground place can help conduct heat away from the IC. Judicious positioning of the PC board within the end product, along with use of any available air flow (forced or natural convection) can help reduce the junction temperatures. Application Circuit Example The following schematic shows an example of an LM5026 controlled 100W active clamp forward power converter. The input voltage range (VPWR) is 36V to 78V, and the output voltage is 3.3V. The output current capability is 30 Amps. Current sense transformer T2 provides information to the CS pin for current mode control and current limit protection. The error amplifiers and reference U3 and U4 provide voltage feedback via optocoupler U2. Synchronous rectifiers Q3-Q6 minimize rectification losses in the secondary. An auxiliary winding on inductor L2 provides power to the LM5026 VCC pin when the output is in regulation. The input voltage UVLO levels are ≈34V for increasing VPWR, and ≈32V for decreasing VPWR. The circuit can be shut down by forcing the ON/OFF input (J2) below 1.25V. An external synchronizing frequency can be applied to the SYNC input (J11) or like converters can be self-synchronized by connections of (J3). The regulator output is current limited at ≈32A. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 23 LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Figure 34. Application Circuit: Input 36-78V, Output 3.3V, 30A 24 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 23 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5026 25 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LM5026MT ACTIVE TSSOP PW 16 92 TBD Call TI Call TI -40 to 125 LM5026 MT LM5026MT/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5026 MT LM5026MTX ACTIVE TSSOP PW 16 TBD Call TI Call TI -40 to 125 LM5026 MT LM5026MTX/NOPB ACTIVE TSSOP PW 16 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 LM5026 MT LM5026SD ACTIVE WSON NHQ 16 TBD Call TI Call TI 5026SD LM5026SD/NOPB ACTIVE WSON NHQ 16 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 5026SD LM5026SDX ACTIVE WSON NHQ 16 TBD Call TI Call TI 5026SD LM5026SDX/NOPB ACTIVE WSON NHQ 16 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 5026SD 2500 1000 4500 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5026MTX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 LM5026SD/NOPB WSON NHQ 16 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 LM5026SDX/NOPB WSON NHQ 16 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5026MTX/NOPB LM5026SD/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 WSON NHQ 16 1000 203.0 190.0 41.0 LM5026SDX/NOPB WSON NHQ 16 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NHQ0016A SDA16A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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