LM5067MMX-1/NOPB

LM5067 SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 LM5067 Negative Hot Swap / Inrush Current Controller with Power Limiting 1 Features 3 Description • • The LM5067 negative hot swap controller provides intelligent control of the power supply connections during insertion and removal of circuit cards from a live system backplane or other “hot” power sources. The LM5067 provides in-rush current control to limit system voltage droop and transients. The current limit and power dissipation in the external series pass N-Channel MOSFET are programmable, ensuring operation within the Safe Operating Area (SOA). In addition, the LM5067 provides circuit protection by monitoring for over-current and over-voltage conditions. The POWER GOOD output indicates when the output voltage is close to the input voltage. The input under-voltage and over-voltage lockout levels and hysteresis are programmable, as well as the fault detection time. The LM5067-1 latches off after a fault detection, while the LM5067-2 automatically attempts restarts at a fixed duty cycle. The LM5067 is available in a 10-pin VSSOP package and a 14-pin SOIC package. • • • • • • • • • Wide operating range: –9 V to –80 V In-rush current limit for safe board insertion into live power sources Programmable maximum power dissipation in the external pass device Adjustable current limit Circuit breaker function for severe overcurrent events Adjustable undervoltage lockout (UVLO) and hysteresis Adjustable overvoltage lockout (OVLO) and hysteresis Initial insertion timer allows ringing and transients to subside after system connection Programmable fault timer avoids nuisance trips Active high open drain POWER GOOD output Available in latched fault and automatic restart versions 2 Applications • • • • • • • Server backplane systems In-Rush current limiting Solid state circuit breaker Transient voltage protector Solid state relay Undervoltage lock-out Power good detector and indicator Device Information(1) PART NUMBER LM5067 (1) PACKAGE BODY SIZE (NOM) VSSOP (10) 3.00 mm x 3.00 mm SOIC (14) 8.99 mm x 7.49 mm For all available packages, see the orderable addendum at the end of the datasheet. GND VCC PGD UVLO/EN LOAD LM5067 OVLO OUT TIMER PWR SENSE VEE RS GATE Q1 - 48V Copyright © 2016, Texas Instruments Incorporated Negative Power Bus In-Rush and Fault Protection An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison......................................................... 3 6 Pin Configuration and Functions...................................4 Pin Functions.................................................................... 4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................5 7.4 Thermal Information....................................................5 7.5 Electrical Characteristics.............................................6 7.6 Switching Characteristics............................................7 7.7 Typical Characteristics................................................ 8 8 Detailed Description......................................................12 8.1 Overview................................................................... 12 8.2 Functional Block Diagram......................................... 13 8.3 Feature Description...................................................13 8.4 Device Functional Modes..........................................18 9 Application and Implementation.................................. 19 9.1 Application Information............................................. 19 9.2 Typical Application.................................................... 19 10 Power Supply Recommendations..............................37 10.1 Operating Voltage................................................... 37 11 Layout........................................................................... 37 11.1 Layout Guidelines................................................... 37 11.2 Layout Example...................................................... 38 12 Device and Documentation Support..........................39 12.1 Trademarks............................................................. 39 12.2 Electrostatic Discharge Caution..............................39 12.3 Glossary..................................................................39 13 Mechanical, Packaging, and Orderable Information.................................................................... 40 4 Revision History Changes from Revision C (March 2013) to Revision D (August 2020) Page • Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1 • Updated the numbering format for tables, figures and cross-references throughout the document...................1 • Updated Applications section............................................................................................................................. 1 • Deleted text : "LM5067A is available..." .............................................................................................................1 Changes from Revision B (September 2009) to Revision C (March 2013) Page • Changed layout of National Data Sheet to TI format........................................................................................ 30 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 5 Device Comparison Table 5-1. Device Comparison Table DEVICE NUMBER RETRY BEHAVIOR AFTER FAULT PACKAGE LM5067-1 Latch-off VSSOP (10), SOIC (14) LM5067-2 Auto-retry VSSOP (10), SOIC (14) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 3 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 6 Pin Configuration and Functions VCC 1 10 UVLO/EN 2 9 OUT OVLO 3 8 GATE PWR 4 7 VEE 5 6 PGD VCC 1 14 PGD N/C 2 13 N/C UVLO/EN 3 12 OUT SENSE OVLO 4 11 N/C TIMER PWR 5 10 GATE VEE 6 9 SENSE N/C 7 8 TIMER Figure 6-1. 10-Lead VSSOP Top View Figure 6-2. 14-Lead SOIC Top View Pin Functions Name 4 Pin I/O Description VSSOP-10 SOIC-14 VCC 1 1 I Positive supply input: Connect to system ground through a resistor. Connect a bypass capacitor to VEE. The voltage from VCC to VEE is nominally 13 V set by an internal zener diode. UVLO/EN 2 3 I Under-voltage lockout: An external resistor divider from the system input voltage sets the under-voltage turn-on threshold. The enable threshold at the pin is 2.5 V above VEE. An internal 22 µA current source provides hysteresis. This pin can be used for remote enable and disable. OVLO 3 4 I Overvoltage lockout: An external resistor divider from the system input voltage sets the overvoltage turn-off threshold. The disable threshold at the pin is 2.5 V above VEE. An internal 22 µA current source provides hysteresis. PWR 4 5 I Power limit set: An external resistor at this pin, in conjunction with the current sense resistor (RS), sets the maximum power dissipation in the external series pass MOSFET. VEE 5 6 I Negative supply input: Connect to the system negative supply voltage (typically -48V). TIMER 6 8 I/O Timing capacitor: An external capacitor at this pin sets the insertion time delay and the fault timeout period. The capacitor also sets the restart timing of the LM5067-2. SENSE 7 9 I Current sense input: The voltage across the current sense resistor (RS) is measured from VEE to this pin. If the voltage across RS reaches 50 mV the load current is limited and the fault timer activates. GATE 8 10 O Gate drive output: Connect to the external N-channel MOSFET’s gate. OUT 9 12 I Output feedback: Connect to the external MOSFET’s drain. Internally used to determine the MOSFET VDS voltage for power limiting, and to control the PGD output pin. PGD 10 14 0 Power Good indicator: An open drain output capable of sustaining 80 V when off. When the external MOSFET VDS decreases below 1.23 V the PGD pin switches high. When the external MOSFET VDS increases above ≊2.5 V the PGD pin switches low. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Input voltage Current MIN MAX UNIT OUT, PGD to VEE –0.3 100 V UVLO, OVLO to VEE –0.3 17 V SENSE to VEE –0.3 0.3 V 100 mA 150 °C 150 °C Into VCC (100 µs pulse) Junction Temperature Storage temperature, Tstg (1) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (LM50672NPA variant)(1) ±1750 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (all other variants)(1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Current into VCC (1) MAX 2 OUT Voltage above VEE Junction Temperature UNIT mA 0 PGD Off Voltage above VEE (1) NOM 80 V 0 80 V −40 125 °C Maximum continuous current into VCC is limited by power dissipation and die temperature. See the Thermal Considerations section. 7.4 Thermal Information LM5067 THERMAL METRIC(1) (2) VSSOP SOIC 10 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 94 90 RθJC Junction-to-case thermal resistance 44 27 (1) (2) UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Tested on a 4 layer JEDEC board with 2 vias under the package. See JEDEC standards JESD51-7 and JESD51-3. See the Thermal Considerations section. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 5 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 7.5 Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: ICC = 2 mA, OUT Pin = 48V above VEE, all voltages are with respect to VEE. See (1). PARAMETER TETS CONDITIONS MIN TYP MAX UNIT 12.35 13 13.65 V Input VZ Operating voltage, VCC – VEE ICC = 2 mA, UVLO = 5V ICC-EN Internal operating current, enabled VCC-VEE = 11V, UVLO = 5V 0.8 1 mA ICC-DIS Internal operating current, disabled VCC-VEE = 11V, UVLO = 2V 480 660 µA PORIT Threshold voltage to start insertion timer VCC-VEE increasing 7.7 8.2 V POREN Threshold voltage to enable all functions VCC-VEE increasing 8.4 8.7 POREN-HYS POREN hysteresis VCC-VEE decreasing 125 IOUT-EN OUT bias current, enabled OUT = VEE, Normal operation 0.1 IOUT-DIS OUT bias current, disabled Disabled, OUT = VEE + 48V 50 ISNS-EN SENSE bias current, enabled OUT = VEE, Normal operation -6 ISNS-DIS SENSE bias current, disabled Disabled, OUT = VEE + 48V -50 V mV OUT Pin µA SENSE Pin µA UVLO, OVLO Pins UVLOTH UVLO threshold UVLOHYS UVLO hysteresis current UVLO = VEE + 2V UVLOBIAS UVLO bias current UVLO = VEE + 5V OVLOTH OVLO threshold OVLOHYS OVLO hysteresis current OVLO = VEE+2.8V OVLOBIAS OVLO bias current OVLO = VEE + 2.4V 2.45 2.5 2.55 V 10 22 34 µA 1 µA 2.43 2.5 2.57 V -34 -22 -10 µA 1 µA µA Gate Control (GATE Pin) Source current IGATE VGATE Normal Operation -72 -52 -32 UVLO < 2.5V 1.9 2.2 2.68 Sink current SENSE - VEE =150 mV or VCC - VEE < PORIT, VGATE = 5V 45 110 200 Gate output voltage in normal operation GATE-VEE voltage Threshold voltage SENSE - VEE voltage 44 50 56 mV Threshold voltage SENSE - VEE voltage 70 100 130 mV 16.5 22 27.5 mV VZ mA V Current Limit VCL Circuit Breaker VCB Power Limit (PWR Pin) PWRLIM Power limit sense voltage (SENSE VEE) OUT - SENSE = 24V, RPWR = 75 kΩ IPWR PWR pin current VPWR = 2.5V -23 µA Timer (TIMER Pin) VTMRH Upper threshold Restart cycles (LM5067-2) VTMRL Lower threshold ITIMER 4.16 V 1.25 1.32 V 0.3 Re-enable threshold (LM5067-1) 0.3 Insertion time current TIMER pin = 2V Sink current, end of insertion time Fault detection current Fault Restart Duty Cycle 4 1.18 End of 8th cycle (LM5067-2) -9.5 -6 TIMER pin = 2V 1.2 TIMER pin = 2V -140 0.9 Sink current, end of fault time DCFAULT 3.76 LM5067-2 V V -2.5 µA 1.55 1.9 mA -95 -44 µA 2.5 4.25 µA 0.5% Power Good (PGD Pin) 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 7.5 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: ICC = 2 mA, OUT Pin = 48V above VEE, all voltages are with respect to VEE. See (1). PARAMETER TETS CONDITIONS MIN TYP MAX UNIT Decreasing 1.162 1.23 1.285 V Increasing, relative to decreasing threshold 1.143 1.25 1.325 60 150 mV 5 µA PGDTH Threshold measured at OUT - SENSE PGDVOL Output low voltage ISINK = 2 mA PGDIOH Off leakage current VPGD = 80V (1) Current out of a pin is indicated as a negative value. 7.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UVLO, OVLO Pins UVLODEL UVLO hysteresis current OVLODEL OVLO delay Delay to GATE high 26 µs Delay to GATE low 12 µs Delay to GATE high 26 µs Delay to GATE low 12 µs SENSE - VEE stepped from 0 mV to 80 mV 25 µs SENSE - VEE stepped from 0 mV to 150 mV, time to GATE low, no load 0.65 Current Limit tCL Response time Circuit Breaker tCB Response time 1.0 µs Timer (TIMER Pin) tFAULT Fault to GATE low delay TIMER pin reaches 4.0V 15 µs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 7 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 7.7 Typical Characteristics Unless otherwise specified the following conditions apply: TJ = 25°C. 8 Figure 7-1. ICC vs Operating Voltage - Disabled Figure 7-2. ICC vs Operating Voltage - Enabled Figure 7-3. Operating Voltage vs ICC Figure 7-4. SENSE Pin Current vs System Voltage Figure 7-5. OUT Pin Current vs System Voltage Figure 7-6. GATE Source Current vs Operating Voltage Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 Figure 7-7. GATE Pull-Down Current, Circuit Breaker vs GATE Voltage Figure 7-8. PGD Low Voltage vs Sink Current Figure 7-9. MOSFET Power Dissipation Limit vs RPWR and RS Figure 7-10. UVLO and OVLO Hysteresis Current vs Temperature Figure 7-11. UVLO, OVLO Threshold Voltage vs UVLO, OVLO Threshold Voltage Figure 7-12. VZ Operating Voltage vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 9 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 POWER LIMIT THRESHOLD (mV) Figure 7-13. Current Limit Threshold vs Temperature Figure 7-14. Circuit Breaker Threshold vs Temperature 25 RPWR = 75k, VEE = -24V 24 23 22 21 20 SENSE Pin ± VEE Pin 19 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) 10 Figure 7-15. Power Limit Threshold vs Temperature Figure 7-16. Gate Source Current vs Temperature Figure 7-17. GATE Pull-Down Current, Circuit Breaker vs Temperature Figure 7-18. PGD Pin Low Voltage vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 TIMER PIN THRESHOLDS (V) 4.1 Upper Restart Threshold 3.9 1.4 Lower Restart Threshold 1.2 0.4 Lower Reset Threshold 0.2 -40 -20 0 20 40 60 80 100 125 JUNCTION TEMPERATURE (°C) Figure 7-19. POREN Threshold vs Temperature Figure 7-20. TIMER Pin Thresholds vs Temperature Figure 7-21. TIMER Pin Fault Detection Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 11 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 8 Detailed Description 8.1 Overview The LM5067 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply voltage, and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets. During the system power up, the maximum power dissipation in the series pass device is limited to a safe value within the device’s Safe Operating Area (SOA). After the system power up is complete, the LM5067 monitors the load for excessive currents due to a fault or short circuit at the load. Limiting the load current and/or the power in the external MOSFET for an extended period of time results in the shutdown of the series pass MOSFET. After a fault event, the LM5067-1 latches off until the circuit is re-enabled by external control, while the LM5067-2 automatically restarts with defined timing. The circuit breaker function quickly switches off the series pass device upon detection of a severe over-current condition caused by, e.g. a short circuit at the load. The Power Good (PGD) output pin indicates when the output voltage is close to the normal operating value. Programmable undervoltage lock-out (UVLO) and overvoltage lock-out (OVLO) circuits shut down the LM5067 when the system input voltage is outside the desired operating range. The typical configuration of a circuit card with LM5067 hot swap protection is shown in Figure 8-1. PLUG - IN BOARD GND LIVE BACKPLANE R IN CIN VCC CL PGD LM5067 VEE SENSE GATE Load OUT - 48V VSYS RS Q1 Copyright © 2016, Texas Instruments Incorporated Figure 8-1. LM5067 Application The LM5067 can be used in a variety of applications, other than plug-in boards, to monitor for excessive load current, provide transient protection, and ensuring the voltage to the load is within preferred limits. The circuit breaker function protects the system from a sudden short circuit at the load. Use of the UVLO/EN pin allows the LM5067 to be used as a solid state relay. The PGD output provides a status indication of the voltage at the load relative to the input system voltage. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 8.2 Functional Block Diagram VCC Vcc VZ LM5067 13V Vcc Vee 50 mV VEE ID Current Limit Threshold SENSE 52 PA Gate Control GATE 2.2 mA 110 mA 1 M: Current Limit Power Limit Control Power Limit Threshold VDS OUT Vee PGD 1.23V/ 2.5V Vee 6 PA Insertion Timer 23 PA PWR 85 PA Fault Timer 22 PA TIMER AND GATE LOGIC CONTROL TIMER OVLO 2.5V 2.5V 2.5 PA Fault Discharge Vee 1.55 mA End Insertion Time Vee 4.0V UVLO/EN 1.25V Vee 22 PA 8.4/8.3V 0.3V Enable POR Insertion Timer POR 7.7V Vcc Vcc All voltages are with respect to VEE Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Power Up Sequence The system voltage range of the LM5067 is –9 V to –80 V, with a transient capability to -100 V. Referring to the Functional Block Diagram, Figure 9-1, and Figure 8-2, as the system voltage (VSYS) initially increases from zero, the external N-channel MOSFET (Q1) is held off by an internal 110 mA pull-down current at the GATE pin. The strong pull-down current at the GATE pin prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. When the operating voltage of the LM5067 (VCC – VEE) reaches the PORIT threshold (7.7V) the insertion timer starts. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 6 µA current source, and Q1 is held off by a 2.2 mA pull-down current at the GATE pin regardless of the system voltage. The insertion time delay allows ringing and transients at VSYS to settle before Q1 can be enabled. The insertion time ends when the TIMER pin voltage reaches 4 V above VEE, and CT is then quickly discharged by an internal 1.5 mA pull-down current. After the insertion time, the LM5067 control circuitry is enabled when the operating voltage reaches the POREN threshold (8.4 V). As VSYS continues to increase, the LM5067 operating voltage is limited at ≊13 V by an internal zener diode. The remainder of the system voltage is dropped across the input resistor RIN. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 13 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 The GATE pin switches on Q1 when VSYS exceeds the UVLO threshold (UVLO pin >2.5V above VEE). If VSYS exceeds the UVLO threshold at the end of the insertion time, Q1 is switched on at that time. The GATE pin sources 52 µA to charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is limited by the LM5067’s operating voltage (VZ) to approximately 13 V. During power up, as the voltage at the OUT pin increases in magnitude with respect to Ground, the LM5067 monitors Q1’s drain current and power dissipation. In-rush current limiting and/or power limiting circuits actively control the current delivered to the load. During the in-rush limiting interval (t2 in Figure 8-2) an internal current source charges CT at the TIMER pin. When the load current reduces from the limiting value to a value determined by the load the in-rush limiting interval is complete and CT is discharged. The PGD pin switches high when the voltage at the OUT pin reaches to within 1.25 V of the voltage at the SENSE pin. If the TIMER pin voltage reaches 4.0V before in-rush current limiting or power limiting ceases (during t2), a fault is declared and Q1 is turned off. See Fault Timer and Restart for a complete description of the fault mode. 0V System Input Voltage UVLO VSYS LM5067 Operating Voltage VZ POR IT (VCC ± VEE) 4V 6 PA 2.5 PA 85 PA TIMER Pin GATE Pin 110 mA pull-down 2.2 mA pull-down 52 PA source I LIMIT Load Current 0V Output Voltage (OUT Pin) 1.25V VSYS PGD VEE t1 Insertion Time t2 In-rush Limiting t3 Normal Operation All waveforms and voltages are with respect to VEE except System Input Voltage and Output Voltage . Figure 8-2. Power Up Sequence (Current Limit only) 8.3.2 Gate Control The external N-channel MOSFET is turned on when the GATE pin sources 52 µA to enhance the gate. During normal operation (t3 in Figure 8-2) Q1’s gate is held charged to approximately 13V above VEE, typically within 20 mV of the voltage at VCC. If the maximum VGS rating of Q1 is less than 13V, a lower voltage external zener diode must be added between the GATE and SENSE pins. The external zener diode must have a forward current rating of at least 110 mA. When the system voltage is initially applied (before the operating voltage reaches the PORIT threshold), the GATE pin is held low by a 110 mA pull-down current. The pull-down current helps prevent an inadvertent turn-on of the MOSFET through its drain-gate capacitance as the applied system voltage increases. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 During the insertion time (t1 in Figure 8-2) the GATE pin is held low by a 2.2 mA pull-down current. This maintains Q1 in the off-state until the end of t1, regardless of the voltage at VCC and UVLO. Following the insertion time, during t2 in Figure 8-2, the gate voltage of Q1 is modulated to keep the current or Q1’s power dissipation level from exceeding the programmed levels. Current limiting and power limiting are considered fault conditions, during which the voltage on the TIMER pin capacitor increases. If the current and power limiting cease before the TIMER pin reaches 4 V the TIMER pin capacitor is discharged, and the circuit enters normal operation. See Fault Timer and Restart for details on the fault timer. If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 2.2 mA pull-down current to switch off Q1. R IN CIN System Gnd VEE VCC 52 PA Gate Charge Power Limit / Current Limit Control Gate Control 2.2 mA Fault UVLO/OVLO Insertion time 110 mA Circuit Breaker/ Initial Hold - down VEE SENSE VSYS RS GATE OUT Q1 Copyright © 2016, Texas Instruments Incorporated Figure 8-3. Gate Control 8.3.3 Current Limit The current limit threshold is reached when the voltage across the sense resistor RS (SENSE to VEE) reaches 50 mV. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault timer is active as described in the Section 8.3.6 section. If the load current reduces below the current limit threshold before the end of the Fault Timeout Period, the LM5067 resumes normal operation. For proper operation, the RS resistor value should be no larger than 100 mΩ. 8.3.4 Circuit Breaker If the load current increases rapidly (e.g., the load is short-circuited) the current in the sense resistor (RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds approximately twice the current limit threshold (100 mV/RS), Q1’s gate is quickly pulled down by the 110 mA pull-down current at the GATE pin, and a Fault Timeout Period begins. When the voltage across RS falls below 100 mV the 110 mA pull-down current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 4.0V before the current limiting or power limiting condition ceases, Q1 is switched off by the 2.2 mA pull-down current at the GATE pin as described in the Fault Timer & Restart section. 8.3.5 Power Limit An important feature of the LM5067 is the MOSFET power limiting. The Power Limit function can be used to maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5067 determines the power dissipation in Q1 by monitoring its drain-source voltage (OUT to SENSE), and the drain current Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LM5067 15 LM5067 www.ti.com SNVS532D – OCTOBER 2007 – REVISED AUGUST 2020 through the sense resistor (SENSE to VEE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to reduce the current in Q1, and the fault timer is active as described in the Fault Timer and Restart section. 8.3.6 Fault Timer and Restart When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either limiting function is active, an 85 µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 8-5 (Fault Timeout Period). If the fault condition subsides before the TIMER pin reaches 4.0V, the LM5067 returns to the normal operating mode and CT is discharged by the 2.5 µA current sink. If the TIMER pin reaches 4.0V during the Fault Timeout Period, Q1 is switched off by a 2.2 mA pull-down current at the GATE pin. The subsequent restart procedure depends on which version of the LM5067 is in use. The LM5067-1 latches the GATE pin low at the end of the Fault Timeout Period, and CT is discharged by the 2.5 µA fault current sink. The GATE pin is held low until a power up sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling the UVLO/EN pin within 2.5V of VEE with an open-collector or open-drain device as shown in Figure 8-4. The voltage across CT must be