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LM5069
SNVS452G – SEPTEMBER 2006 – REVISED JAUNUARY 2020
LM5069 Positive High-Voltage Hot Swap and In-Rush Current Controller
with Power Limiting
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
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•
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Wide operating range: 9 V to 80 V
In-rush current limit for safe board insertion into
live power sources
Programmable maximum power dissipation in the
external pass device
Adjustable current limit
Circuit breaker function for severe overcurrent
events
Internal high side charge pump and gate driver for
external N-channel MOSFET
Adjustable undervoltage lockout (UVLO) and
hysteresis
Adjustable overvoltage lockout (OVLO) and
hysteresis
Initial insertion timer allows ringing and transients
to subside after system connection
Programmable fault timer avoids nuisance trips
Active high open drain POWER GOOD output
Available in latched fault and automatic restart
versions
10-Pin VSSOP package
Server backplane systems
Base station power distribution systems
Solid state circuit breaker
24-V and 48-V Industrial systems
3 Description
The LM5069 positive hot swap controller provides
intelligent control of the power supply connections
during insertion and removal of circuit cards from a
live system backplane or other hot power sources.
The LM5069 provides in-rush current control to limit
system voltage droop and transients. The current limit
and power dissipation in the external series pass NChannel MOSFET are programmable, ensuring
operation within the Safe Operating Area (SOA). The
POWER GOOD output indicates when the output
voltage is within 1.25 V of the input voltage. The input
undervoltage and overvoltage lockout levels and
hysteresis are programmable, as well as the initial
insertion delay time and fault detection time. The
LM5069-1 latches off after a fault detection, while the
LM5069-2 automatically restarts at a fixed duty cycle.
LM5069 is available in a 10-pin VSSOP package.
Device Information(1)
PART NUMBER
LM5069
PACKAGE
VSSOP (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
VIN
VOUT
RSNS
Q1
CIN
D1
Z1
COUT
VDD
GATE
SENSE
Only required when
using dv/dt start-up
OUT
100kŸ
R1
R3
VIN
D2
PGD
LM5069
UVLO/EN
OVLO
GND
R2
R4
1kŸ
PWR
Cdv/dt
TIMER
Q2
RPWR
CTIMER
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5069
SNVS452G – SEPTEMBER 2006 – REVISED JAUNUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2019) to Revision G
•
Added Device Comparison table ............................................................................................................................................ 3
Changes from Revision E (November 2016) to Revision F
•
Page
Page
Updated the Absolute Maximum Ratings section................................................................................................................... 4
Changes from Revision D (May 2013) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Added Thermal Information table ........................................................................................................................................... 4
2
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SNVS452G – SEPTEMBER 2006 – REVISED JAUNUARY 2020
5 Device Comparison
DEVICE NUMBER
RETRY BEHAVIOR AFTER FAULT
LM5069-1
Latch Off on Fault
LM5069-2
Auto Retry on Fault
PACKAGE
VSSOP (10)
6 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
SENSE
1
10
GATE
VIN
2
9
OUT
UVLO
3
8
PGD
OVLO
4
7
PWR
GND
5
6
TIMER
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
SENSE
I
Current sense input: The voltage across the current sense resistor (RS) is measured from VIN to this
pin. If the voltage across RS reaches 55 mV the load current is limited and the fault timer activates.
2
VIN
I
Positive supply input: A small ceramic bypass capacitor close to this pin is recommended to suppress
transients which occur when the load current is switched off.
3
UVLO
I
Undervoltage lockout: An external resistor divider from the system input voltage sets the undervoltage
turnon threshold. An internal 21-µA current source provides hysteresis. The enable threshold at the pin
is 2.5 V. This pin can also be used for remote shutdown control.
4
OVLO
I
Overvoltage lockout: An external resistor divider from the system input voltage sets the overvoltage
turnoff threshold. An internal 21-µA current source provides hysteresis. The disable threshold at the pin
is 2.5 V.
5
GND
—
Circuit ground
6
TIMER
I/O
Timing capacitor: An external capacitor connected to this pin sets the insertion time delay and the fault
timeout period. The capacitor also sets the restart timing of the LM5069-2.
7
PWR
I
Power limit set: An external resistor connected to this pin, in conjunction with the current sense resistor
(RS), sets the maximum power dissipation allowed in the external series pass MOSFET.
8
PGD
O
Power Good indicator: An open drain output. When the external MOSFET VDS decreases below 1.25 V,
the PGD indicator is active (high). When the external MOSFET VDS increases above 2.5 V the PGD
indicator switches low.
9
OUT
I
Output feedback: Connect to the output rail (external MOSFET source). Internally used to determine the
MOSFET VDS voltage for power limiting, and to control the PGD indicator.
10
GATE
O
Gate drive output: Connect to the external MOSFET’s gate. This pin's voltage is typically 12 V above
the OUT pin when enabled.
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SNVS452G – SEPTEMBER 2006 – REVISED JAUNUARY 2020
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VIN to GND (3)
–0.3
100
V
SENSE, OUT, and PGD to GND
–0.3
100
V
GATE to GND (3)
–0.3
100
V
–1
100
V
UVLO to GND
–0.3
100
V
OVLO to GND
–0.3
7
V
VIN to SENSE
–0.3
0.3
V
150
°C
150
°C
OUT to GND (1 -ms transient)
(4)
Maximum junction temperature, TJMAX
Storage temperature, Tstg
(1)
(2)
(3)
(4)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The GATE pin voltage is typically 12 V above VIN when the LM5069 is enabled. Therefore, the Absolute Maximum Ratings for VIN
(100 V) applies only when the LM5069 is disabled, or for a momentary surge to that voltage because the Absolute Maximum Rating for
the GATE pin is also 100 V.
Select external MOSFET with VGS(th) voltage higher than VOUT during -ve transient. This avoids MOSFET getting turned-ON during -ve
transient.
7.2 ESD Ratings
VALUE
Electrostatic discharge (1)
V(ESD)
(1)
(2)
(3)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(2)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
V
±500
The Human-body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VIN
TJ
(1)
MIN
MAX
Supply voltage
9
80
PGD off voltage
0
80
V
–40
125
°C
Junction temperature
UNIT
V
For detailed information on soldering plastic VSSOP packages, see Absolute Maximum Ratings for Soldering (SNOA549) available from
Texas Instruments.
7.4 Thermal Information
LM5069
THERMAL METRIC (1)
DGS (VSSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
156
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50.6
°C/W
RθJB
Junction-to-board thermal resistance
75.8
°C/W
ψJT
Junction-to-top characterization parameter
4.8
°C/W
ψJB
Junction-to-board characterization parameter
74.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SNVS452G – SEPTEMBER 2006 – REVISED JAUNUARY 2020
7.5 Electrical Characteristics
Minimum and maximum limits are specified through test, design, or statistical correlation at TJ= –40°C to 125°C. Typical
values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. VIN = 48 V
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT (VIN PIN)
IIN-EN
Input current, enabled
UVLO > 2.5 V and OVLO < 2.5 V
1.3
1.6
mA
IIN-DIS
Input current, disabled
UVLO < 2.5 V or OVLO > 2.5 V
480
650
µA
PORIT
Power-On reset threshold at
VIN to trigger insertion timer
VIN increasing
7.6
8
V
POREN
Power-On reset threshold at
VIN to enable all functions
VIN increasing
8.4
9
V
POREN-HYS
POREN hysteresis
VIN decreasing
90
IOUT-EN
OUT bias current, enabled
OUT = VIN, Normal operation
11
IOUT-DIS
OUT bias current, disabled (1)
Disabled, OUT = 0 V, SENSE = VIN
50
mV
OUT PIN
µA
UVLO, OVLO PINS
UVLOTH
UVLO threshold
UVLOHYS
UVLO hysteresis current
UVLODEL
UVLO delay
UVLOBIAS
UVLO bias current
OVLOTH
OVLO threshold
OVLOHYS
OVLO hysteresis current
OVLODEL
OVLO delay
OVLOBIAS
OVLO bias current
UVLO = 1 V
2.45
2.5
2.55
V
12
21
30
µA
Delay to GATE high
55
Delay to GATE low
11
UVLO = 48 V
µs
1
OVLO = 2.6 V
µA
2.4
2.5
2.6
V
12
21
30
µA
Delay to GATE high
55
Delay to GATE low
11
OVLO = 2.4 V
µs
1
µA
31
mV
POWER LIMIT (PWR PIN)
PWRLIM-1
Power limit sense voltage
(VIN-SENSE)
SENSE-OUT = 48 V, RPWR = 150 kΩ
PWRLIM-2
SENSE-OUT = 24 V, RPWR = 75 kΩ
19
25
25
mV
IPWR
PWR pin current
VPWR = 2.5 V
20
µA
GATE CONTROL (GATE PIN)
Source current
IGATE
VGATE
(1)
Sink current
Gate output voltage in normal
operation
Normal operation, GATE-OUT = 5 V
UVLO < 2.5 V
VIN to SENSE = 150 mV or VIN < PORIT, VGATE = 5 V
GATE-OUT voltage
10
16
22
µA
1.75
2
2.6
mA
45
110
175
mA
11.4
12
12.6
V
OUT bias current (disabled) due to leakage current through an internal 1-MΩ resistance from SENSE to VOUT.
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Electrical Characteristics (continued)
Minimum and maximum limits are specified through test, design, or statistical correlation at TJ= –40°C to 125°C. Typical
values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. VIN = 48 V
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
48.5
55
MAX UNIT
CURRENT LIMIT
VCL
Threshold voltage
VIN-SENSE voltage
tCL
Response time
VIN-SENSE stepped from 0 mV to 80 mV
45
Enabled, SENSE = OUT
23
Disabled, OUT = 0 V
60
ISENSE
SENSE input current
61.5
mV
µs
µA
CIRCUIT BREAKER
VCB
tCB
Threshold voltage
VIN to SENSE
Response time
VIN to SENSE stepped from 0 mV to 150 mV, time to
GATE low, no load
80
105
130
mV
0.44
1.2
µs
TIMER (TIMER PIN)
VTMRH
Upper threshold
Restart cycles (LM5069-2)
VTMRL
Lower threshold
Sink current, end of insertion
time
4
4.16
V
1.25
1.313
V
End of 8th cycle (LM5069-2)
0.3
Re-enable Threshold (LM5069-1)
0.3
Insertion time current
ITIMER
3.76
1.187
TIMER pin = 2 V
Fault detection current
Fault sink current
DCFAULT
Fault restart duty cycle
LM5069-2 only
tFAULT
Fault to GATE low delay
TIMER pin reaches 4 V
V
V
3
5.5
8
µA
1
1.5
2
mA
51
85
120
µA
1.25
2.5
3.75
µA
0.5%
12
µs
POWER GOOD (PGD PIN)
PGDTH
Threshold measured at
SENSE-OUT
Decreasing
0.67
1.25
1.85
Increasing, relative to decreasing threshold
0.95
1.25
1.55
PGDVOL
Output low voltage
ISINK = 2 mA
60
150
mV
PGDIOH
Off leakage current
VPGD = 80 V
5
µA
6
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7.6 Typical Characteristics
TJ = 25°C and VIN = 48 V (unless otherwise noted)
100
1.5
SENSE PIN INPUT CURRENT (PA)
VIN PIN INPUT CURRENT (mA)
2.0
Enabled, UVLO = VIN
1.0
0.5
Disabled, UVLO = 0V
0
50
25
Enabled, UVLO = VIN
0
0
20
40
60
0
80
20
60
80
SENSE PIN VOLTAGE (V)
Figure 1. VIN Pin Input Current vs VIN
Figure 2. SENSE Pin Input Current
14
Load at OUT Pin = 600:
Current flow is out of the pin
12
GATE-OUT VOLTAGE
80
60
Disabled, UVLO = 0V
40
20
Enabled, UVLO = VIN
0
10
8
6
4
Enabled, UVLO = VIN
Normal Operation
2
POREN
0
-20
0
20
40
60
0
80
5
10
15
20
70
80
VIN VOLTAGE (V)
VIN VOLTAGE (V)
Figure 4. GATE Pin Voltage vs VIN
Figure 3. OUT Pin Current
18
0.8
17
0.7
16
0.6
PGD VOLTAGE (V)
GATE PIN CURRENT (PA)
40
VIN VOLTAGE (V)
100
OUT PIN CURRENT (PA)
Disabled, UVLO = 0V
75
15
14
13
12
0.4
0.3
0.2
Enabled, UVLO = VIN
Normal Operation
11
0.5
10
0.1
POREN
9
0
5
10
15
20
70
0
80
0
VIN VOLTAGE (V)
5
10
15
20
PGD SINK CURRENT (mA)
Figure 5. GATE Pin Source Current vs VIN
Figure 6. PGD Pin Low Voltage vs Sink Current
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Typical Characteristics (continued)
TJ = 25°C and VIN = 48 V (unless otherwise noted)
240
RS = 0.005:
PFET (W)
160
RS = 0.1:
RS = 0.01:
120
80
RS = 0.02:
40
RS = 0.05:
0
200
150
100
50
TJ = 25°C
|
200
GATE PULLDOWN CURRENT,
CIRCUIT BREAKER (mA)
|
250
0
0
30
60
90
120
0
150
10
R PWR (k:)
82
92
Figure 8. GATE Pulldown Current, Circuit Breaker
vs GATE Voltage
23
OVLO HYSTERESIS CURRENT (PA)
23
UVLO HYSTERESIS CURRENT (PA)
30
GATE PIN VOLTAGE (V)
Figure 7. MOSFET Power Dissipation Limit vs RPWR and RS
22
21
20
19
-40 -20
22
21
20
19
0
20
40
60
80
100 125
-40 -20
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (°C)
Figure 9. UVLO Hysteresis Current vs Temperature
Figure 10. OVLO Hysteresis Current vs Temperature
1.320
2.55
INPUT CURRENT, ENABLED (mA)
UVLO, OVLO THRESHOLD VOLTAGE (V)
JUNCTION TEMPERATURE (oC)
2.53
2.51
2.50
2.49
UVLO
OVLO
OVLO
UVLO
2.47
2.45
-40 -20
0
20
40
60
80
1.310
1.300
1.290
VIN = 48V
1.280
-40 -20
100 125
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
Figure 11. UVLO, OVLO Threshold vs Temperature
8
20
Figure 12. Input Current, Enabled vs Temperature
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Typical Characteristics (continued)
TJ = 25°C and VIN = 48 V (unless otherwise noted)
115
CIRCUIT BREAKER THRESHOLD
(VOLTAGE ACROSS RS) (mV)
CURRENT LIMIT THRESHOLD
(VOLTAGE ACROSS RS) (mV)
57
56
55
54
53
-40 -20
0
20
40
60
80
110
105
100
95
90
85
-40 -20
100 125
JUNCTION TEMPERATURE ( C)
Figure 13. Current Limit Threshold vs Temperature
40
60
80
100 125
13.0
GATE OUTPUT VOLTAGE ABOVE
OUT PIN (V)
POWER LIMIT THRESHOLD
(VOLTAGE ACROSS RS) (mV)
20
Figure 14. Circuit Breaker Threshold vs Temperature
27
26
25
24
RPWR = 150 k:
VDS = 48V
23
-40 -20
0
20
40
60
80
12.5
12.0
11.5
GATE-OUT Voltage,
Normal Operation
11.0
-40 -20
100 125
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
Figure 15. Power Limit Threshold vs Temperature
Figure 16. GATE Output Voltage vs Temperature
150
GATE PULLDOWN CURRENT,
CIRCUIT BREAKER (mA)
16.4
GATE SOURCE CURRENT (PA)
0
JUNCTION TEMPERATURE (oC)
o
16.2
16.0
15.8
GATE-OUT = 5V
15.6
-40 -20
0
20
40
60
80
130
110
100
90
70
GATE PIN = 5V
50
-40 -20
100 125
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 17. GATE Source Current vs Temperature
Figure 18. GATE Pulldown Current, Circuit Breaker
vs Temperature
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Typical Characteristics (continued)
TJ = 25°C and VIN = 48 V (unless otherwise noted)
PGD OUTPUT LOW VOLTAGE (mV)
160
120
80
.
40
PGD Sink Current = 2 mA
0
-40 -20
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (oC)
Figure 19. PGD Low Voltage vs Temperature
10
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8 Detailed Description
8.1 Overview
The inline protection functionality of the LM5069 is designed to control the in-rush current to the load upon
insertion of a circuit card into a live backplane or other hot power source, thereby limiting the voltage sag on the
backplane's supply voltage and the dV/dt of the voltage applied to the load. Effects on other circuits in the
system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is
removed can also be implemented using the LM5069.
In addition to a programmable current limit, the LM5069 monitors and limits the maximum power dissipation in
the series pass device to maintain operation within the device Safe Operating Area (SOA). Either current limiting
or power limiting for an extended period of time results in the shutdown of the series pass device. In this event,
the LM5069-1 latches off while the LM5069-2 retries an infinite number of times to recover after the fault is
removed. The circuit breaker function quickly switches off the series pass device upon detection of a severe
overcurrent condition. Programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits shut
down the LM5069 when the system input voltage is outside the desired operating range.
8.2 Functional Block Diagram
LM5069
Charge
Pump
55 mV
ID
VIN
Current Limit
Threshold
SENSE
16 PA
Gate
Control
GATE
2 mA
230
mA
1 M:
OUT
Current Limit/
Power Limit
Control
Power Limit
Threshold
VDS
12V
OUT
PGD
1.25V/
2.5V
5.5 PA
Insertion
Timer
20 PA
PWR
85 PA
Fault
Timer
21 PA
TIMER AND GATE
LOGIC CONTROL
TIMER
OVLO
2.5V
2.5V
1.5 mA
End
Insertion
Time
2.5 PA
Fault
Discharge
4.0V
UVLO
1.25V
21 PA
GND
8.4/8.3V
0.3V
Enable POR
Insertion Timer POR
VIN
7.6V
VIN
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8.3 Feature Description
8.3.1 Current Limit
The current limit threshold is reached when the voltage across the sense resistor RS (VIN to SENSE) reaches
55 mV. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While
the current limit circuit is active, the fault timer is active as described in Fault Timer and Restart. If the load
current falls below the current limit threshold before the end of the fault timeout period, the LM5069 resumes
normal operation. For proper operation, the RS resistor value must be no larger than 100 mΩ.
8.3.2 Circuit Breaker
If the load current increases rapidly (for example, the load is short-circuited) the current in the sense resistor (RS)
may exceed the current limit threshold before the current limit control loop is able to respond. If the current
exceeds twice the current limit threshold (105 mV/RS), Q1 is quickly switched off by the 230-mA pulldown current
at the GATE pin, and a fault timeout period begins. When the voltage across RS falls below 105 mV the 230-mA
pulldown current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current
limit or the power limit functions. If the TIMER pin reaches 4 V before the current limiting or power limiting
condition ceases, Q1 is switched off by the 2-mA pulldown current at the GATE pin as described in Fault Timer
and Restart.
8.3.3 Power Limit
An important feature of the LM5069 is the MOSFET power limiting. The Power Limit function can be used to
maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5069 determines
the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current
through the sense resistor (VIN to SENSE). The product of the current and voltage is compared to the power
limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold,
the GATE voltage is modulated to reduce the current in Q1. While the power limiting circuit is active, the fault
timer is active as described in Fault Timer and Restart.
8.3.4 Undervoltage Lockout (UVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range
defined by the programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. Typically the
UVLO level at VSYS is set with a resistor divider (R1-R3) as shown in Figure 30. When VSYS is below the UVLO
level, the internal 21-µA current source at UVLO is enabled, the current source at OVLO is off, and Q1 is held off
by
the
2-mA pulldown current at the GATE pin. As VSYS is increased, raising the voltage at UVLO above 2.5 V, the
21-µA current source at UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this
threshold. With the UVLO pin above 2.5 V, Q1 is switched on by the 16-µA current source at the GATE pin if the
insertion time delay has expired (Figure 22). See Application and Implementation for a procedure to calculate the
values of the threshold setting resistors (R1-R3). The minimum possible UVLO level at VSYS can be set by
connecting the UVLO pin to VIN. In this case Q1 is enabled when the VIN voltage reaches the POREN threshold.
8.3.5 Overvoltage Lockout (OVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range
defined by the programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. If VSYS raises
the OVLO pin voltage above 2.5 V, Q1 is switched off by the 2-mA pulldown current at the GATE pin, denying
power to the load. When the OVLO pin is above 2.5 V, the internal 21-µA current source at OVLO is switched on,
raising the voltage at OVLO to provide threshold hysteresis. When VSYS is reduced below the OVLO level Q1 is
enabled. See Application and Implementation for a procedure to calculate the threshold setting resistor values.
8.3.6 Power Good Pin
During turnon, the Power Good pin (PGD) is high until the voltage at VIN increases above ≊ 5 V. PGD then
switches low, remaining low as the VIN voltage increases. When the voltage at OUT increases to within 1.25 V of
the SENSE pin (VDS 2.5 V). If VSYS is above the UVLO threshold
at the end of the insertion time, Q1 switches on at that time. The GATE pin charge pump sources 16 µA to
charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is limited by an internal 12-V Zener
diode.
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Device Functional Modes (continued)
As the voltage at the OUT pin increases, the LM5069 monitors the drain current and power dissipation of
MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the
load. During the in-rush limiting interval (t2 in Figure 22) an internal 85-µA fault timer current source charges CT.
If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the
TIMER pin reaches 4 V, the 85-µA current source is switched off, and CT is discharged by the internal 2.5-µA
current sink (t3 in Figure 22). The in-rush limiting interval is complete when the voltage at the OUT pin increases
to within 1.25 V of the input voltage (VSYS), and the PGD pin switches high.
If the TIMER pin voltage reaches 4 V before in-rush current limiting or power limiting ceases (during t2), a fault is
declared and Q1 is turned off. See Fault Timer and Restart for a complete description of the fault mode.
VSYS
UVLO
V IN
POR IT
4V
5.5 PA
TIMER
Pin
GATE
Pin
85 PA
2.5 PA
1.5 mA
230 mA
pull-down
2 mA pull-down
16 PA source
I LIMIT
Load
Current
Output
Voltage
(OUT Pin)
1.25V
PGD
t1
Insertion Time
t2
In- rush
Limiting
t3
Normal Operation
Figure 22. Power-Up Sequence (Current Limit Only)
8.4.2 Gate Control
A charge pump provides internal bias voltage above the output voltage (OUT pin) to enhance the N-Channel
MOSFET’s gate. The gate-to-source voltage is limited by an internal 12-V Zener diode. During normal operating
conditions (t3 in Figure 22) the gate of Q1 is held charged by an internal 16-µA current source to approximately
12 V above OUT. If the maximum VGS rating of Q1 is less than 12 V, an external Zener diode of lower voltage
must be added between the GATE and OUT pins. The external Zener diode must have a forward current rating
of at least 250 mA.
When the system voltage is initially applied, the GATE pin is held low by a 230-mA pulldown current. This helps
prevent an inadvertent turnon of the MOSFET through its drain-gate capacitance as the applied system voltage
increases.
During the insertion time (t1 in Figure 22) the GATE pin is held low by a 2-mA pulldown current. This maintains
Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO.
Following the insertion time, during t2 in Figure 22, the gate voltage of Q1 is modulated to keep the current or
power dissipation level from exceeding the programmed levels. While in the current or power limiting mode the
TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 4 V the
TIMER pin capacitor then discharges, and the circuit enters normal operation.
14
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Device Functional Modes (continued)
If the in-rush limiting condition persists such that the TIMER pin reached 4 V during t2, the GATE pin is then
pulled low by the 2-mA pulldown current. The GATE pin is then held low until either a power-up sequence is
initiated (LM5069-1), or until the end of the restart sequence (LM5069-2). See Fault Timer and Restart.
If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is
pulled low by the 2-mA pulldown current to switch off Q1.
Q1
VSYS
VOUT
RS
VIN
CL
SENSE
GATE
OUT
Charge
Pump
16 PA
Current Limit /
Power Limit
Control
2 mA
12V
Fault /
UVLO /
OVLO /
Insertion
time
Gate
Control
230 mA
Circuit Breaker /
Initial Hold - down
Figure 23. Gate Control
8.4.3 Fault Timer and Restart
When the current limit or power limit threshold is reached during turnon or as a result of a fault condition, the
gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation. When either
limiting function is activated, an 85-µA fault timer current source charges the external capacitor (CT) at the
TIMER pin as shown in Figure 25 (fault timeout period). If the fault condition subsides during the fault timeout
period before the TIMER pin reaches 4 V, the LM5069 returns to the normal operating mode and CT is
discharged by the 2.5-µA current sink. If the TIMER pin reaches 4 V during the fault timeout period, Q1 is
switched off by a 2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on
which version of the LM5069 is in use.
The LM5069-1 latches the GATE pin low at the end of the fault timeout period. CT is then discharged to ground
by the 2.5-µA fault current sink. The GATE pin is held low by the 2-mA pulldown current until a power-up
sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling the UVLO pin below
2.5 V with an open-collector or open-drain device as shown in Figure 24. The voltage at the TIMER pin must be
PLIM, so the hot swap starts in power limit and transition
into current limit. In that case, the estimated start time can be computed with Equation 12.
C OUT
t start
2
ªV 2
IN,MAX
u«
« PLIM
¬
PLIM º
»
2
»
I LIM
¼
330PF ª (30 V)2
u«
2
¬« 39.23 W
39.23 W º
»
(10 A)2 ¼»
3.85ms
(12)
Note that the above start-time assumes constant, typical current limit and power limit values. The actual startup
time is slightly longer, as the power limit is a function of Vds and decreases as the output voltage increases. To
ensure that the timer never times out during start-up, TI recommends setting the minimum fault time (tflt) to be
greater than the start time (tstart) by adding an additional margin of 50% of the fault time. This accounts for the
variation in power limit, timer current, and timer capacitance. Thus CTIMER can be computed with Equation 13.
CTIMER =
t flt ×i timer(typ)
v timer(typ)
×1.5=
3.85ms×85μA
×1.5=123nF
4V
(13)
The next largest available CTIMER is chosen as 150 nf. Once the CTIMER is chosen the actual programmed fault
time can be computed with Equation 14.
t flt
C TIMER u v timer,typ
i timer,typ
150nF u 4 V
85 PA
7.06 ms
(14)
This is the typical time that the LM5069 shuts off the CSD19536KTT MOSFET.
9.2.1.2.5 Check MOSFET SOA
Once the power limit and fault timer are chosen, it’s critical to check that the FET stays within its SOA during all
test conditions. During a Hot-Short, the circuit breaker trips and the LM5069 restarts into power limit until the
timer runs out. In the worst case, the MOSFET’s VDS equals VIN,MAX, IDS equals PLIM / VIN,MAX and the stress
event lasts for tflt. For this design example, the MOSFET has 30 V, 1.25 A across it for 7.06 ms.
Based on the SOA of the CSD19536KTT, it can handle 30 V, 9 A for 10 ms and it can handle 30 V, 20 A for
1 ms. The SOA for 7.06 ms can be extrapolated by approximating SOA versus time as a power function as
shown Equation 15 through Equation 18.
autm
I SOA t
ln
m
a
(15)
I SOA t 1
I SOA t 2
§ t1 ·
ln ¨ ¸
¨t2 ¸
© ¹
I SOA t1
§ 20 A ·
ln ¨
¸
© 9A ¹
§ 1ms ·
ln ¨
¸
© 10ms ¹
20 A
t 1m
1ms
0.346
0.346
(16)
20 A u 1 ms
0.346
(17)
I SOA 7.06 ms
20 A u 1 ms
0.346
u 7.06 ms
0.346
10.17 A
(18)
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be
much hotter during a hot-short. The SOA must be derated based on TC,MAX using Equation 19.
I SOA 7.06 ms, T C,MAX
10.17 A u
I SOA 7.06 ms,25 qC u
175 qC 63.6 qC
175 qC 25 qC
T J,ABSMAX
T J,ABSMAX
T C,MAX
25 qC
(19)
7.55 A
(20)
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Based on this calculation the MOSFET can handle 7.55 A, 30 V for 7.06 ms at elevated case temperature, and is
required to handle 1.25 A during a hot-short. This means the MOSFET is not at risk of getting damaged during a
hot-short. In general, TI recommends for the MOSFET to be able to handle a minimum of 1.3× more power than
what is required during a hot-short to provide margin to cover the variance of the power limit and fault time.
9.2.1.2.6 Set Undervoltage and Overvoltage Threshold
By programming the UVLO and OVLO thresholds the LM5069 enables the series pass device (Q1) when the
input supply voltage (VSYS) is within the desired operational range. If VSYS is below the UVLO threshold, or above
the OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis is provided for each threshold.
9.2.1.2.6.1 Option A
The configuration shown in Figure 30 requires three resistors (R1-R3) to set the thresholds.
V SYS
VIN
R1
21 PA
LM5069
UVLO
2. 50V
TIMER AND GATE
LOGIC CONTROL
R2
2. 50V
R3
OVLO
21 PA
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 30. UVLO and OVLO Thresholds Set By R1-R3
The procedure to calculate the resistor values is as follows:
1. Choose the upper UVLO threshold (VUVH), and the lower UVLO threshold (VUVL).
2. Choose the upper OVLO threshold (VOVH).
3. The lower OVLO threshold (VOVL) cannot be chosen in advance in this case, but is determined after the
values for R1-R3 are determined. If VOVL must be accurately defined in addition to the other three thresholds,
see Option B below.
The resistors are calculated with Equation 21, Equation 22, and Equation 23.
VUVH - VUVL VUV(HYS)
R1 =
=
21 PA
21 PA
(21)
2.5V x R1 x VUVL
R3 =
VOVH x (VUVL - 2.5V)
(22)
2.5V x R1
- R3
R2 =
VUVL - 2.5V
(23)
The lower OVLO threshold is calculated from Equation 24.
VOVL = [(R1 + R2) x ((2.5V) - 21 PA)] + 2.5V
R3
(24)
As an example, assume the application requires the following thresholds: VUVH = 36 V, VUVL = 32 V, VOVH = 60 V.
36V ± 32V
4V
R1 =
= 190.5 k:
=
21 PA
21 PA
(25)
R3 =
22
2.5V x 190.5 k: x 32V
= 8.61 k:
60V x (32V - 2.5V)
(26)
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2.5V x 190.5 k:
- 8.61 k: = 7.53 k:
(32V - 2.5V)
(27)
The lower OVLO threshold calculates to 55.8 V, and the OVLO hysteresis is 4.2 V. Note that the OVLO
hysteresis is always slightly greater than the UVLO hysteresis in this configuration. When the R1-R3 resistor
values are known, the threshold voltages and hysteresis are calculated from Equation 28 through Equation 33.
2.5V
VUVH = 2.5V + [R1 x (21 PA +
)]
(R2 + R3)
(28)
VUVL =
2.5V x (R1 + R2 + R3)
R2 + R3
(29)
(30)
VUV(HYS) = R1 × 21 µA
VOVH =
2.5V x (R1 + R2 + R3)
R3
VOVL = [(R1 + R2) x (2.5V) - 21 PA)] + 2.5V
R3
(31)
(32)
(33)
VOV(HYS) = (R1 + R2) × 21 µA
9.2.1.2.6.2 Option B
If all four thresholds must be accurately defined, the configuration in Figure 31 can be used.
VSYS
VIN
21 PA
LM5069
R1
UVLO
2.5V
R3
R2
2.5V
TIMER AND GATE
LOGIC CONTROL
OVLO
R4
21 PA
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Programming the Four Thresholds
The four resistor values are calculated as follows:
1. Choose the upper UVLO threshold (VUVH) and lower UVLO threshold (VUVL) with Equation 34 and
Equation 35.
VUVH - VUVL VUV(HYS)
R1 =
=
21 PA
21 PA
(34)
2.5V x R1
R2 =
(VUVL - 2.5V)
(35)
2. Choose the upper OVLO threshold (VOVH) and lower OVLO threshold (VOVL) with Equation 36 and
Equation 37.
VOVH - VOVL VOV(HYS)
R3 =
=
21 PA
21 PA
(36)
2.5V x R3
R4 =
(VOVH - 2.5V)
(37)
As an example, assume the application requires the following thresholds: VUVH = 22 V, VUVL = 17 V, VOVH = 60 V,
and VOVL = 58 V. Therefore VUV(HYS) = 5 V, and VOV(HYS) = 2 V. The resistor values are:
• R1 = 238 kΩ, R2 = 41 kΩ
• R3 = 95.2 kΩ, R4 = 4.14 kΩ
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Where the R1-R4 resistor values are known, the threshold voltages and hysteresis are calculated from
Equation 38 to Equation 43.
VUVH = 2.5V + [R1 x (2.5V + 21 PA)]
(38)
R2
2.5V x (R1 + R2)
VUVL =
(39)
R2
VUV(HYS) = R1 x 21 µA
(40)
2.5V x (R3 + R4)
VOVH =
R4
VOVL = 2.5V + [R3 x (2.5V - 21 PA)]
R4
(41)
(42)
(43)
VOV(HYS) = R3 x 21 µA
9.2.1.2.6.3 Option C
The minimum UVLO level is obtained by connecting the UVLO pin to VIN as shown in Figure 32. Q1 is switched
on when the VIN voltage reaches the POREN threshold (≊8.4 V). An external transistor can be connected to
UVLO to provide remote shutdown control, and to restart the LM5069-1 after a fault detection. The OVLO
thresholds are set using R3, R4. Their values are calculated using the procedure in Option B.
VSYS
VIN
21 PA
100k
LM5069
UVLO
2.5V
R3
Shutdown/
Restart
Control
2.5V
R4
TIMER AND GATE
LOGIC CONTROL
OVLO
21 PA
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 32. UVLO = POREN With Shutdown/Restart Control
9.2.1.2.6.4 Option D
The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as described in
Option B or Option C.
For this design example, option B is used and the following values are targeted: VUVH = 10 V, VUVL = 9 V,
VOVH = 15 V, VOVL = 14 V. R1, R2, R3, and R4 are computed using Equation 44 through Equation 47.
R1
R2
R3
R4
V UVH
V UVL
21µA
2.5 V u R1
V UVL
2.5 V
V OVH
V OVL
47.62k
(44)
2.5 V u 47.62k
17 V 2.5 V
8.21k
(45)
21µA
2.5 V u R3
V OVH
18 V 17 V
21µA
2.5 V
31 V 30 V
21µA
47.62k
2.5 V u 47.62k
31V 2.5 V
(46)
4.18k
(47)
Nearest available 1% resistors must be chosen. Set R1 = 47.5 kΩ, R2 = 8.25 kΩ, R3 = 47.5 kΩ, and
R4 = 4.22 kΩ.
24
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9.2.1.2.7 Input and Output Protection
Proper operation of the LM5069 hot swap circuit requires a voltage clamping element present on the supply side
of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in Figure 27. The TVS
is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current.
This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET
shuts off. The TVS must be chosen to have minimal leakage current at VIN,MAX and to clamp the voltage to under
30 V during hot-short events. For many high-power applications intended to clamp at 30 V, SMBJ30A-13-F is a
good choice.
9.2.1.2.8 Final Schematic and Component Values
Figure 27 shows the schematic used to implement the requirements described in the previous section. In
addition, Table 2 below provides the final component values that were used to meet the design requirements for
a 12-V, 40-A hot swap design. The Application Curves are based on these component values.
Table 2. Component Values
COMPONENT
VALUE
Rsns
4 mΩ
R1
47.5 kΩ
R2
8.25 kΩ
R3
47.5 kΩ
R4
4.22 kΩ
RPWR
15.8 kΩ
Q1
CSD19536KTT
Z1
SMBJ30A-13-F
D1
MBR3100
CTIMER
150 nF
COUT
330 µF
9.2.1.3 Application Curves
Figure 33. Start-Up
Figure 34. Start-Up (Zoomed In)
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Figure 35. Start-Up into Short Circuit
Figure 36. Undervoltage
Figure 37. Overvoltage
Figure 38. Gradual Overcurrent
Figure 39. Load Step
Figure 40. Hot-Short on Output
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Figure 41. Hot-Short (Zoomed In)
Figure 42. Auto-Retry
10 Power Supply Recommendations
In general, the LM5069 behavior is more reliable if it is supplied from a very regulated power supply. However,
high-frequency transients on a backplane are not uncommon due to adjacent card insertions or faults. If this is
expected in the end system, TI recommends placing a 1-µF ceramic capacitor to ground close to the drain of the
hot swap MOSFET. This reduces the common mode voltage seen by VIN and SENSE. Additional filtering may
be necessary to avoid nuisance trips.
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11 Layout
11.1 Layout Guidelines
11.1.1 PC Board Guidelines
The following guidelines must be followed when designing the PC board for the LM5069:
• Place the LM5069 close to the board’s input connector to minimize trace inductance from the connector to the
FET.
• Note that special care must be taken when placing the bypass capacitor for the VIN pin. During hot shorts,
there is a very large dV/dt on input voltage after the MOSFET turns off. If the bypass capacitor is placed right
next to the pin and the trace from Rsns to the pin is long, an LC filter is formed. As a result, a large differential
voltage can develop between VIN and SENSE. To avoid this, place the bypass capacitor close to Rsns
instead of the VIN pin.
Sense
VIN
Trace
Inductance
Figure 43. Layout Trace Inductance
•
•
•
•
•
The sense resistor (RS) must be close to the LM5069, and connected to it using the Kelvin techniques shown
in Figure 46.
The high current path from the board’s input to the load (via Q1), and the return path, must be parallel and
close to each other to minimize loop inductance.
The ground connection for the various components around the LM5069 must be connected directly to each
other, and to the LM5069’s GND pin, and then connected to the system ground at one point. Do not connect
the various component grounds to each other through the high current ground line.
Provide adequate heat sinking for the series pass device (Q1) to help reduce stresses during turnon and
turnoff.
The board’s edge connector can be designed to shut off the LM5069 as the board is removed, before the
supply voltage is disconnected from the LM5069. In Figure 45 the voltage at the UVLO pin goes to ground
before VSYS is removed from the LM5069 due to the shorter edge connector pin. When the board is inserted
into the edge connector, the system voltage is applied to the LM5069’s VIN pin before the UVLO voltage is
taken high.
11.1.2 System Considerations
A) Continued proper operation of the LM5069 hot swap circuit requires capacitance be present on the supply
side of the connector into which the hot swap circuit is plugged in, as depicted in Figure 44. The capacitor in the
Live Backplane section is necessary to absorb the transient generated whenever the hot swap circuit shuts off
the load current. If the capacitance is not present, inductance in the supply lines generate a voltage transient at
shut-off which can exceed the absolute maximum rating of the LM5069, resulting in its destruction.
B) If the load powered via the LM5069 hot swap circuit has inductive characteristics, a diode is required across
the LM5069’s output. The diode provides a recirculating path for the load’s current when the LM5069 shuts off
that current. Adding the diode prevents possible damage to the LM5069 as the OUT pin is taken below ground
by the inductive load at shutoff. See Figure 44.
28
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Layout Guidelines (continued)
RS
VSYS
VOUT
Q1
+48V
LIVE
BACKPLANE
OUT
VIN
CL
Inductive
Load
LM5069
GND
GND
PLUG-IN BOARD
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Output Diode Required for Inductive Loads
11.2 Layout Example
GND
VSYS
To
Load
RS
R1
R2
R3
Q1
SENSE GATE
OUT
VIN
UVLO PGD
OVLO PWR
GND TIMER
LM5069
CARD EDGE
CONNECTOR
PLUG-IN CARD
Copyright © 2016, Texas Instruments Incorporated
Figure 45. Recommended Board Connector Design
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Layout Example (continued)
HIGH CURRENT PATH
FROM
SYSTEM
INPUT
VOLTAGE
TO MOSFET'S
DRAIN
SENSE
RESISTOR
RS
SENSE
VIN
3
10
9
8
4
LM5069 7
5
6
Copyright © 2016, Texas Instruments Incorporated
Figure 46. Sense Resistor Connections
Rsns
R
R
R
Source
R
C
Hot Swap
C
Output Caps
C
IC GND
High Current GND
Figure 47. LM5069 Quiet IC Ground Layout
30
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Copyright © 2006–2020, Texas Instruments Incorporated
Product Folder Links: LM5069
LM5069
www.ti.com
SNVS452G – SEPTEMBER 2006 – REVISED JAUNUARY 2020
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For the LM5069 Design Calculator, go to Tools & Software in the Product Folder on ti.com.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Absolute Maximum Ratings for Soldering (SNOA549)
• Robust Hot Swap Design (SLVA673)
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2006–2020, Texas Instruments Incorporated
Product Folder Links: LM5069
31
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5069MM-1/NOPB
ACTIVE
VSSOP
DGS
10
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SNAB
LM5069MM-2
NRND
VSSOP
DGS
10
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 125
SNBB
LM5069MM-2/NOPB
ACTIVE
VSSOP
DGS
10
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SNBB
LM5069MMX-1/NOPB
ACTIVE
VSSOP
DGS
10
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SNAB
LM5069MMX-2/NOPB
ACTIVE
VSSOP
DGS
10
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SNBB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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