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LM5071MT-80

LM5071MT-80

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP16

  • 描述:

    IC POE PD CTRLR W/AUX 16-TSSOP

  • 数据手册
  • 价格&库存
LM5071MT-80 数据手册
LM5071 www.ti.com SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 LM5071 Power Over Ethernet PD Controller with Auxiliary Power Interface Check for Samples: LM5071 FEATURES PACKAGES • • • • • • • 1 2 • • • • • • • • • Compatible with 12V AC Adapters Fully Compliant 802.3af Power Interface Port 80V, 1Ω, 400 mA Internal MOSFET Detection Resistor Disconnect Function Programmable Classification Current Programmable Under-voltage Lockout with Programmable Hysteresis Thermal Shutdown Protection Auxiliary Power Enable Pin Current Mode Pulse Width Modulator Supports both Isolated and Non-Isolated Applications Error Amplifier and Reference for Non-Isolated Applications Programmable Oscillator Frequency Programmable Soft-Start 80% Maximum Duty Cycle Limiter, Slope Compensation (-80 device) 50% Maximum Duty Cycle Limiter, No Slope Compensation (-50 device) TSSOP-16 DESCRIPTION The LM5071 power interface port and pulse width modulation (PWM) controller provides a complete integrated solution for Powered Devices (PD) that connect into Power over Ethernet (PoE) systems. The LM5071 is specifically designed for the PD that must accept power from auxiliary sources such as AC adapters. The auxiliary power interface of the LM5071 activates the PWM controller when the ac adapter is connected to power the PD when PoE network power is unavailable. The LM5071 integrates an 80V, 400mA line connection switch and associated control for a fully IEEE 802.3af compliant interface with a full featured current mode pulse width modulator dc-dc converter. All power sequencing requirements between the controller interface and switch mode power supply (SMPS) are integrated into the IC. Block Diagram PoE (+) VOUT IEEE 802.3 af Interface LM5071 UVLO Signature Detection Classification AC Adapter Jack + _ Hot Swap AUX Auxiliary Power Enable In-rush and Fault Current Limiting DC - DC Converter PWM Controller Feedback Current Mode PoE (-) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LM5071 SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 VIN www.ti.com +3.3V LM5071 VIN RSIG VIN < 10V Switch RCLASS Bandgap Regulator VCC Internal High Voltage Regulator 5V - + UVLO SMPS Controller UVLORTN OUT CS AUX VEE Inrush /DC Current Limit VEE RTN COMP RT SS ARTN FB Figure 1. Simplified Block Diagram Connection Diagram VIN 1 16 ARTN RSIG 2 15 SS RCLASS 3 14 RT AUX 4 13 CS UVLO 5 12 COMP UVLORTN 6 11 FB VEE 7 10 VCC RTN 8 9 OUT Figure 2. 16 Lead TSSOP 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 LM5071 www.ti.com SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name 1 VIN 2 RSIG 3 RCLASS 4 AUX 5 UVLO 6 UVLORTN 7 Description Application Information System high potential input. The diode “OR” of several lines entering the PD, it is the more positive input potential. Signature resistor pin. Connect a resistor from VIN to this pin for signature detection. The resistor is in parallel with the UVLO resistors and should be valued accordingly. Classification resistor pin. Connect the classification programming resistor from this pin to VEE. Auxiliary input power startup pin. A resistor divider between the AUX voltage input to VEE programs the startup levels with a 2.5V threshold. A high value (>300kΩ) internal pull down resistor is present to pull the pin low if it is left open. In practice, the divider voltage should be set well above 2.5V by the programming resistors. Line under-voltage lockout. An external resistor divider from VIN to UVLORTN programs the shutdown levels with a 2.00V threshold at the UVLO pin. Hysteresis is set by a switched internal 10uA current source that forces additional current into the resistor divider. Return for the external UVLO resistors. Connect the bottom resistor of the resistor divider between the UVLO pin and this pin. VEE System low potential input. Diode “OR’d” to the RJ45 connector and PSE’s –48V supply, it is the more negative input potential. 8 RTN System return for the PWM converter. The drain of the internal current limiting power MOSFET which connects VEE to the return path of the dc-dc converter. 9 OUT Output of the PWM controller. DC-DC converter gate driver output with 800mA peak sink current capability. 10 VCC Output of the internal high voltage series pass regulator. Regulated output voltage is nominally 7.8V. When the auxiliary transformer winding (if used) raises the voltage on this pin above the regulation set point, the internal series pass regulator will shutdown, reducing the controller power dissipation. 11 FB Feedback signal. Inverting input of the internal error amplifier. The non-inverting input is internally connected to a 1.25V reference. 12 COMP 13 CS 14 RT / SYNC 15 SS 16 ARTN The output of the error amplifier and input COMP pull-up is provided by an internal 5K resistor which may be used to the Pulse Width Modulator. to bias an opto-coupler transistor. Current sense input. Current sense input for current mode control and over-current protection. Current limiting is accomplished using a dedicated current sense comparator. If the CS pin voltage exceeds 0.5V the OUT pin switches low for cycle-by-cycle current limiting. CS is held low for 50ns after OUT switches high to blank leading edge current spikes. Oscillator timing resistor pin and synchronization input. An external resistor connected from RT to ARTN sets the oscillator frequency. This pin will also accept narrow ac-coupled synchronization pulses from an external clock. Soft-start input. An external capacitor and an internal 10uA current source set the softstart ramp rate. Analog PWM supply return. RTN for sensitive analog circuitry including the SMPS current limit amplifier. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 3 LM5071 SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) VIN ,RTN to VEE -0.3V to 80V RSIG to VIN -12V to 0V AUX to VEE -0.3V to 57V UVLO to VEE -0.3V to 13V RCLASS to VEE -0.3V to 7V ARTN to RTN -0.3V to 0.3V VCC, OUT to ARTN -0.3V to 16V All other inputs to ARTN -0.3V to 7V ESD Rating Human Body Model 2000V Lead Temperature (3) Wave (4 seconds) 260°C Infrared (10 seconds) 240°C Vapor Phase (75 seconds) 219°C (1) (2) (3) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics. The absolute maximum rating of VIN, RTN to VEE is derated to (-0.3V to 76V) at -40°C. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. For detailed information on soldering the plastic TSSOP package, refer to the Packaging Databook available from Texas Instruments. Operating Ratings VIN voltage 1.8V to 60V External voltage applied to VCC 8.1V to 15V Operating Junction Temperature -40°C to 125°C 4 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 LM5071 www.ti.com SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 Electrical Characteristics (1) Specifications in standard type face are for TJ = +25°C and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ. Symbol Parameter Conditions Min Typ Max Units Powered Interface IOS Offset Current VIN < 10.0V 10 uA VCLSS(ON) Signature Resistor Disable / Classification Current Turn On VIN with respect to VEE 10.0 11.5 12.5 V VCLSS(OFF) Classification Current Turn Off VIN with respect to VEE 23.5 25.0 26.5 V 1.43 1.5 1.57 V 0.5 1.0 mA 1 1.9 mA Classification Voltage With respect to VEE ICLASS Supply Current During Classification VIN =17V IDC Supply Current During Normal Operation OUT floating UVLO Pin Reference Voltage VIN > 27V 1.95 2.00 2.05 V UVLO Hysteresis Current VIN > UVLO 8.0 10 11.5 uA Softstart Release RTN falling with respect to VEE 1.2 1.45 1.7 V Softstart Release Hysteresis RTN rising with respect to VEE 0.8 1.1 1.3 V RDS(ON) PowerFET Resistance I = 350mA, VIN = 48V 1 2.2 Ω ILEAK SMPS Bias Current VEE = 0V, VIN = RTN = 57V 100 uA AUX Pin Threshold AUX pin rising with respect to VEE 2.4 2.5 2.65 V AUX Pin Threshold Hysteresis AUX pin falling with respect to VEE 0.4 0.5 0.6 V ZAUX AUX Pin Input Impedance AUX = 0.5V IINRUSH Inrush Current Limit VEE = 0V, RTN = 3.0V 70 100 130 mA ILIM DC Current Limit VEE = 0V, RTN = 3.0V, Temp = 0°C to 85°C 350 390 420 mA ILIM DC Current Limit VEE = 0V, RTN = 3.0V, Temp = 40°C to 125°C 325 390 420 mA VinMin Operational VIN Input Voltage AUX = 5V, Vcc = Vin (2) 9.5 VccReg VCC Regulation Open ckt 7.5 7.8 8.1 VCC Current Limit See (3) 15 20 VCC UVLO (Rising) VccReg – 300mV VccReg – 100mV VCC UVLO (Falling) 5.9 6.25 6.6 V 1.5 3 mA 350 kΩ Startup Regulator V V mA VCC Supply Supply Current (Icc) Cload = 0 Error Amplifier GBW Gain Bandwidth 4 MHz DC Gain 75 dB Input Voltage FB = COMP COMP Sink Capability FB=1.5V COMP=1V ILIM Delay to Output CS step from 0 to 0.6V, time to onset of OUT transition (90%) 1.219 1.212 5 1.281 1.288 V 20 mA 20 ns Current Limit Cycle by Cycle Current Limit Threshold Voltage (1) (2) (3) 0.44 0.5 0.56 V Min and Max limits are 100% production tested at 25 °C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instruments’ Average Outgoing Quality Level (AOQL). The Vcc regulator requires an external source whenever the Vin pin is below 13V with respect to RTN. An external load on Vcc increases this startup voltage requirement. Device thermal limitations may limit usable range. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 5 LM5071 SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Electrical Characteristics(1) (continued) Specifications in standard type face are for TJ = +25°C and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ. Symbol Parameter Conditions Min Typ Max Units Leading Edge Blanking Time 55 ns CS Sink Impedance (clocked) 25 55 Ω 7 10 13 uA Frequency1 (RT = 30.3K) 175 200 225 KHz Frequency2 (RT = 10.5K) 505 580 665 KHz 3.1 3.8 V Soft-Start Softstart Current Source Oscillator (4) Sync threshold PWM Comparator Delay to Output COMP set to 2V CS stepped 0 to 0.4V, time to onset of OUT transition low Min Duty Cycle COMP=0V 25 ns 0 % Max Duty Cycle (-80 Device) 80 % Max Duty Cycle (-50 Device) 50 % COMP to PWM Comparator Gain 0.33 COMP Open Circuit Voltage 4.5 5.4 6.3 V 0.6 1.1 1.5 mA COMP Short Circuit Current COMP= 0V Slope Comp Amplitude (LM5071-80 Device Only) Delta increase at PWM Comparator to CS 105 Output High Saturation Iout = 50mA, VCC - VOUT 0.25 0.75 Output Low Saturation Iout = 100mA 0.25 0.75 Rise time Cload = 1nF 15 ns Fall time Cload = 1nF 15 ns 165 °C 25 °C 125 °C/W Slope Compensation mV Output Section V V Thermal Shutdown Tsd Thermal Shutdown Temp. Thermal Shutdown Hysteresis Thermal Resistance θJA (4) 6 Junction to Ambient PW Package Specification applies to the oscillator frequency. The operational frequency of the LM5071-50 devices is divided by two. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 LM5071 www.ti.com SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 Typical Performance Characteristics Default Current Limit vs Temperature Oscillator Frequency vs RT Resistance OSCILLATOR FREQUENCY (kHz) 400 DEFAULT CURRENT LIMIT (mA) 395 390 385 380 375 370 365 1000 800 600 400 200 0 360 -40 -20 0 20 40 60 80 0 100 120 5 10 15 20 25 30 35 40 45 50 RT RESISTANCE (k:) TEMPERATURE (oC) Figure 3. Figure 4. UVLO Hysteresis Current vs Temperature Softstart Current vs Temperature 12 11.5 11.5 SOFTSTART CURRENT (PA) UVLO HYSTERESIS CURRENT (PA) 12 11 10.5 10 9.5 9 8.5 8 -40 11 10.5 10 9.5 9 8.5 -20 0 20 40 60 80 8 -40 100 120 -20 o 0 20 40 60 80 100 120 o TEMPERATURE ( C) TEMPERATURE ( C) Figure 5. Figure 6. Error Amp Input Voltage vs temperature Oscillator Frequency vs Temperature RT = 15.2 kΩ 1.275 406 1.270 404 1.265 402 FREQUENCY (kHz) SMPS BG (V) 1.260 1.255 1.250 1.245 1.240 400 398 396 394 1.235 392 1.230 1.225 -60 -40 -20 0 20 40 60 80 100 120 140 390 -40 -20 0 20 40 60 80 100 120 o o TEMPERATURE ( C) TEMPERATURE ( C) Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 7 LM5071 SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) VCC vs ICC Input Current vs Input Voltage 9 3 8 INPUT CURRENT (mA) 2.5 VCC (V) 7 6 5 4 3 2 1.5 1 0.5 2 1 0 0 5 10 15 20 25 0 10 20 30 40 50 60 70 80 INPUT VOLTAGE (V) ICC (mA) Figure 9. Figure 10. UVLO Threshold vs Temperature 2.05 2.04 2.03 UVLO VTH (V) 2.02 2.01 2.00 1.99 1.98 1.97 1.96 1.95 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC) Figure 11. 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 LM5071 www.ti.com SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 Specialized Block Diagrams VIN 5 + EN _ VBG + 2V - VCC 10 PA UVLO + + _ + _ 2.5V VEE VCC FB COMP RTN ARTN FB _ 350 k: OUT 1V Hysteresis COMP + AUX Gate Control CS force_enable _ OUT CS Thermal Limit SS 10V VIN See Figure 4 1.5V + RSIG Power OK _ RCLASS SMPS Controller RT 1.5V SS + EN LOCAL_EN VIN RT UVLORTN LT25V 2V - 60V Figure 12. Top Level Block Diagram Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 9 LM5071 SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com RT Slope Compensation Generator 45 PA 0 OSC VCC CLK -50 Device Has No Slope Compensation 80% MAX DUTY LIMIT (-80) 50% MAX DUTY LIMIT (-50) 5V 5k 1.25V FB Q R Q DRIVER OUT PWM 100k + - S 1.4V + LOGIC 50k SS 10 PA SS SS COMP 2k 0.5V + - CURRENT LIMIT CS CLK +LEB Figure 13. PWM Controller Block Diagram 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 LM5071 www.ti.com SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 DETAILED OPERATING DESCRIPTION The LM5071 power interface port and pulse width modulation (PWM) controller provides a complete integrated solution for Powered Devices (PD) that connect into Power over Ethernet (PoE) systems. Major features of the PD interface portion of the IC include detection, classification, thermal limit, programmable undervoltage lockout, and current limit monitoring. The device also includes a high-voltage start-up bias regulator that operates over a wide input range up to 60V. The switch mode power supply (SMPS) control portion of the IC includes power good sensing, VCC regulator under-voltage lockout, cycle-by-cycle current limit, error amplifier, slope compensation, soft-start, and oscillator sync capability. This high speed BiCMOS IC has total propagation delays less than 100ns and a 1MHz capable oscillator programmed by a single external resistor. The LM5071 PWM controller provides current-mode control for dc-dc converter topologies requiring a single drive output, such as Flyback and Forward topologies. The LM5071 PWM enables all of the advantages of current-mode control including line feed-forward, cycle-by-cycle current limit and simplified loop compensation. The oscillator ramp is internally buffered and added to the PWM comparator input ramp to provide slope compensation necessary for current mode control at duty cycles greater than 50% (-80 suffix only). Modes of Operation The LM5071 PD interface is designed to provide a fully compliant IEEE 802.3af system. As such, the modes of operation take into account the barrel rectifiers often utilized to correctly polarize the dc input from the Ethernet cable. Table 1. Operating Modes With Respect to Input Voltage Input Voltage VIN wrt VEE Mode of Operation 1.8V to 10.0V Detection (Signature) 12.5V to 25.0V Classification 25.0V to UVLO Rising Vth Awaiting Full Power 60V to UVLO Falling Vth Normal Powered Operation An external signature resistor is connected to VEE when VIN exceeds 1.8V, initiating detection mode. During detection mode, quiescent current drawn by the LM5071 is less than 10uA. Between 10.0V and 12.5V, the device enters classification mode and the signature resistor is disabled. The nominal range for classification mode is 11.5V to 25.0V. The classification current is turned off once the classification range voltage is exceeded, to reduce power dissipation. Between 25.0V and UVLO release, the device is in a standby state, awaiting the input voltage to reach the operational range to complete the power up sequence. Once the VIN voltage increases above the upper UVLO threshold voltage, the internal power MOSFET is enabled to deliver a constant current to charge the input capacitor of the dc-dc converter. When the MOSFET Vds voltage falls below 1.5V, the internal Power Good signal enables the SMPS controller. The LM5071 is specified to operate with an input voltage as high as 60.0V. The SMPS controller and internal MOSFET are disabled when VIN falls to the lower UVLO threshold. Detection Signature To detect a potential powered device candidate, the PSE (Power Sourcing Equipment) will apply a voltage from 2.8V to 10V across the input terminals of the PD. The voltage can be of either polarity so a diode barrel network is required on both lines to ensure this capability. The PSE will take two measurements, separated by at least 1V and 2ms of time. The voltage ramp between measurement points will not exceed 0.1V/us. The delta voltage / delta current calculation is then performed; if the detected impedance is above 23.75kΩ and below 26.25kΩ, the PSE will consider a PD to be present. If the impedance is less than 15kΩ or greater than 33kΩ a PD will be considered not present and will not receive power. Impedances between these values may or may not indicate the presence of a valid PD. The LM5071 will enable the signature resistor at a controller input voltage of 1.5V to take into account the diode voltage drops. An external signature resistor should be placed between the VIN and RSIG pins. The signature resistor is in parallel with the external UVLO resistor divider, and its value should be calculated accordingly. Targeting 24.5kΩ increases margin in the signature design as the input bridge rectifier diodes contribute to the series resistance measured at the PD input terminals. The PSE will tolerate no more than 1.9V of offset voltage (caused by the external diodes) or more than 10uA of offset current (bias current). The input capacitance must be greater than 0.05uF and less than 0.12uF. To increase efficiency, the signature resistor is disabled by the LM5071 controller once the input voltage is above the detection range (> 11V). Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 11 LM5071 SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Classification To classify the PD, the PSE will present a voltage between 14.5V and 20.5V to the PD. The LM5071 enables classification mode at a nominal input voltage of 11.5V. An internal 1.5V linear regulator and an external resistor connected to the RCLASS pin provide classification programming current. Table 1 shows the external classification resistor required for a particular class. The classification current flows through the IC into the classification resistor. The suggested resistor values take into account the bias current flowing into the IC. A different desired RCLASS can be calculated by dividing 1.5V by the desired classification current. Per the IEEE 802.3af specification, classification is optional, and the PSE will default to class 0 if a valid classification current is not detected. If PD classification is not desired (i.e., Class 0), simply leave the RCLASS pin open. The classification time period may not last longer than 75ms as per IEEE 802.3af. The LM5071 will remain in classification mode until VIN is greater than 25V. Table 2. Classification Levels and Required External Resistors Class PMIN PMAX ICLASS (MIN) ICLASS (MAX) RCLASS 0 0.44W 12.95W 1 0.44W 3.84W 0mA 4mA Open 9mA 12mA 150Ω 2 3.84W 3 6.49W 6.49W 17mA 20mA 82.5Ω 12.95W 26mA 30mA 4 Reserved Reserved 54.9Ω 36mA 44mA 38.3Ω Undervoltage Lockout (UVLO) The IEEE 802.3af specification states that the PSE will supply power to the PD within 400ms after completion of detection. The LM5071 contains a programmable line Under Voltage Lock Out (UVLO) circuit. The first resistor should be connected between the VIN to UVLO pins; the bottom resistor in the divider should be connected between the UVLO and UVLORTN pins. The divider must be designed such that the voltage at the UVLO pin equals 2.0V when VIN reaches the desired minimum operating level. If the UVLO threshold is not met, the interface control and SMPS control will remain in standby. UVLO hysteresis is accomplished with an internal 10uA current source that is switched on and off into the impedance of the UVLO set point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.00V threshold, the current source is turned off, causing the voltage at the UVLO pin to fall. The LM5071 UVLO thresholds cannot be programmed lower than 25V, the AUX pin should be used to force UVLO release below 25V. There are many additional uses for the UVLO pin. The UVLO function can also be used to implement a remote enable / disable function. Pulling the UVLO pin down below the UVLO threshold disables the interface and SMPS controller unless forced on via AUX pin operation. AUX Pin Operation The AUX pin can be used to force operation (UVLO release) of the interface and switching regulator at any input voltage above 9.5V. This is especially useful for auxiliary input (wall transformer) input voltages. The pin has a 2.5V threshold (0.5V hysteresis) and an input impedance of approximately 350kΩ. The input resistor provides a defined pull down impedance if the pin is left open by the user. An external pull down resistor should be used to provide additional noise immunity. The resultant pin voltage from the external resistor divider should be well above the 2.5V threshold to ensure proper auxiliary operation. See Figure 14 for an example of a simple yet robust auxiliary configuration. 12 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM5071 LM5071 www.ti.com SNVS409E – NOVEMBER 2005 – REVISED APRIL 2013 +AUX +PoE VCC VIN +V OUT LM 5071 RCLASS SS UVLO RT COMP UVLORTN CS 100 k: FB AUX ARTN RTN 100 k: -PoE OUT VEE - AUX 0.1 PF Figure 14. Simplified Schematic Showing Auxiliary Implementation Power Supply Operation Once the UVLO threshold has been satisfied, the interface controller of the LM5071 will charge up the SMPS input capacitor through the internal power MOSFET. This load capacitance provides input filtering for the power converter section and must be at least 5uF per the IEEE 802.3af specification. To accomplish the charging in a controlled manner, the power MOSFET is current limited to 100mA. The SMPS controller will not initiate operation until the load capacitor is completely charged. The power sequencing between the interface circuitry and the SMPS controller occurs automatically within the LM5071. Detection circuitry monitors the RTN pin to detect interface startup completion. When the RTN pin potential drops below 1.5V with respect to VEE, the VCC regulator of the SMPS controller is enabled. The soft-start function is enabled once the VCC regulator achieves minimum operating voltage. The inrush current limit only applies to the initial charging phase. The interface power MOSFET current limit will revert to the default protection current limit of 390mA once the SMPS is powered up and the soft-start pin sequence begins. High Voltage Start-up Regulator The LM5071 contains an internal high voltage startup regulator that allows the input pin (VIN) to be connected directly to line voltages as high as 60V. The regulator output is internally current limited to 15mA. The recommended capacitance range for the VCC regulator output is 0.1uF to 10uF. When the voltage on the VCC pin reaches the regulation point of 7.8V, the controller output is enabled. The controller will remain enabled until VCC falls below 6.25V. In typical applications, a transformer auxiliary winding is diode connected to the VCC pin. This winding should raise the VCC voltage above 8.1V to shut off the internal startup regulator. Though not required, powering VCC from an auxiliary winding improves conversion efficiency while reducing the power dissipated in the controller. The external VCC capacitor must be selected such that the capacitor maintains the VCC voltage greater than the VCC UVLO falling threshold (6.25V) during the initial start-up. During a fault condition when the converter auxiliary winding is inactive, external current draw on the VCC line should be limited such that the power dissipated in the start-up regulator does not exceed the maximum power dissipation capability of the LM5071 package. If the VCC auxiliary winding is used with a low voltage auxiliary supply (wall transformer), the VCC pin could back feed through the LM5071 to the VIN pin. A diode from VCC to VIN should be used to clamp the VCC pin and prevent this internal back feed. The winding voltage will remain the same and extra power will be dissipated in the series resistor. Also, note that when using a very low voltage auxiliary supply (
LM5071MT-80 价格&库存

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