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LM5085, LM5085-Q1
SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015
LM5085/-Q1 75-V Constant On-Time PFET Buck Switching Controller
1 Features
3 Description
•
The LM5085 is a high efficiency PFET switching
regulator controller that can be used to quickly and
easily develop a small, efficient buck regulator for a
wide range of applications. This high voltage
controller contains a PFET gate driver and a high
voltage bias regulator which operates over a wide
4.5-V to 75-V input range. The constant on-time
regulation principle requires no loop compensation,
simplifies circuit implementation, and results in
ultrafast load transient response. The operating
frequency remains nearly constant with line and load
variations due to the inverse relationship between the
input voltage and the on-time. The PFET architecture
allows 100% duty cycle operation for a low dropout
voltage. Either the RDS(ON) of the PFET or an external
sense resistor can be used to sense current for overcurrent detection.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
LM5085-Q1 is an Automotive Grade Product that
is AEC-Q100 Grade 1 Qualified (–40°C to 125°C
Operating Junction Temperature)
Wide 4.5-V to 75-V Input Voltage Range
Adjustable Current Limit Using RDS(ON) or a
Current Sense Resistor
Programmable Switching Frequency to 1MHz
No Loop Compensation Required
Ultra-Fast Transient Response
Nearly Constant Operating Frequency with Line
and Load Variations
Adjustable Output Voltage from 1.25 V
Precision ±2% Feedback Reference
Capable of 100% Duty Cycle Operation
Internal Soft-start Timer
Integrated High Voltage Bias Regulator
Thermal Shutdown
Package:
– HVSSOP-8
– VSSOP-8
– WSON-8
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
VSSOP (8)
LM5085
HVSSOP (8)
3.00 mm x 3.00 mm
WSON (8)
LM5085-Q1
HVSSOP (8)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
Automotive Infotainment
Battery/Super Capacitor Chargers
LED Drivers
Typical Application, Basic Step Down Controller
4.5V to 75V
Input
CVCC
LM5085
VIN
VIN
VCC
CADJ
CIN
ADJ
GND
RT
RADJ
L1
PGATE
Q1
SHUTDOWN
RT
VOUT
ISEN
D1
GND
Cff
COUT
RFB2
GND
FB
RFB1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5085, LM5085-Q1
SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
4
4
6
Absolute Maximum Ratings ......................................
ESD Ratings: LM5085 ..............................................
ESD Ratings: LM5085-Q1 ........................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (October 2014) to Revision I
Page
•
Moved the Storage temperature, Tstg to the Absolute Maximum Ratings .............................................................................. 3
•
Changed "Handling Ratings" to ESD Ratings: LM5085 and ESD Ratings: LM5085-Q1 ....................................................... 4
•
Added text "Figure 24 shows the required placement of this Schottky diode..." and Figure 24 to section VCC Regulator. 14
Changes from Revision G (March 2013) to Revision H
•
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision F (March 2013) to Revision G
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 23
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SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015
5 Pin Configuration and Functions
8-Pins
HVSSOP Package
Top View
8-Pins
WSON Package
Top View
Exposed Pad on Bottom
Connect to Ground
ADJ
ADJ
1
8
VIN
RT
2
7
VCC
FB
3
6
PGATE
GND
4
5
ISEN
8-Pins
VSSOP Package
Top View
8
1
VIN
RT
2
7
VCC
FB
3
6
PGATE
GND
4
5
ISEN
ADJ
1
8
RT
2
7
VCC
FB
3
6
PGATE
GND
4
5
ISEN
VIN
Exposed Pad on Bottom
Connect to Ground
Pin Functions
PIN
I/O
DESCRIPTION
APPLICATION INFORMATION
NAME
NO.
ADJ
1
I
Current Limit Adjust
The current limit threshold is set by an external resistor from VIN to ADJ
in conjunction with the external sense resistor or the PFET’s RDS(ON).
RT
2
I
On-Time Control and Shutdown
An external resistor from VIN to RT sets the buck switch on-time and
switching frequency. Grounding this pin shuts down the controller.
FB
3
I
Voltage Feedback From the
Regulated Output
Input to the regulation and over-voltage comparators. The regulation
level is 1.25V.
GND
4
-
Circuit Ground
Ground reference for all internal circuitry
ISEN
5
I
Current Sense Input for Current limit
Detection.
Connect to the PFET drain when using RDS(ON) current sense. Connect
to the PFET source and the sense resistor when using a current sense
resistor.
PGATE
6
O
Gate Driver Output
Connect to the gate of the external PFET.
VCC
7
O
Output of the gate driver bias
regulator
Output of the negative voltage regulator (relative to VIN) that biases the
PFET gate driver. A low ESR capacitor is required from VIN to VCC,
located as close as possible to the pins.
VIN
8
I
Input Supply Voltage
The operating input range is from 4.5V to 75V. A low ESR bypass
capacitor must be located as close as possible to the VIN and GND pins.
-
Exposed Pad
Exposed pad on the underside of the package (HVSSOP and WSON
only). This pad is to be soldered to the PC board ground plane to aid in
heat dissipation.
EP
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
UNIT
–0.3
76
V
ISEN to GND
–3
VIN + 0.3
V
ADJ to GND
–0.3
VIN + 0.3
V
RT, FB to GND
–0.3
7
V
VIN to VCC, VIN to PGATE
–0.3
10
V
Storage temperature, Tstg
–65
150
°C
VIN to GND
(1)
(2)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are
conditions under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical
Characteristics .
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: LM5085 LM5085-Q1
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LM5085, LM5085-Q1
SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015
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6.2 ESD Ratings: LM5085
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings: LM5085-Q1
MIN
Human body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
VALUE
(1)
UNIT
±2000
Corner pins (1, 4, 5,
and 8)
±750
Other pins
±750
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
MIN
MAX
VIN Voltage
4.5
75
UNIT
V
Junction Temperature
–40
125
°C
6.5 Thermal Information
LM5085
THERMAL METRIC (1)
LM5085,
LM5085-Q1
DGK
NGQ
DGN
8 PINS
8 PINS
8 PINS
θJA
Junction-to-ambient thermal resistance
153
44.8
54.1
θJC(top)
Junction-to-case (top) thermal resistance
52.5
39.4
49.1
θJB
Junction-to-board thermal resistance
71.9
11.6
26.7
ψJT
Junction-to-top characterization parameter
4.6
0.3
1.3
ψJB
Junction-to-board characterization parameter
70.8
11.6
26.5
θJC(bot)
Junction-to-case (bottom) thermal resistance
29
5.0
3.6
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. Unless otherwise stated the following conditions apply: VIN = 48 V, RT = 100kΩ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN PIN
IIN
IQ
Operating Current
Shutdown Current
VCC REGULATOR
VCC(reg)
UVLOVcc
VCC(CL)
(1)
(2)
4
Non-Switching, FB = 1.4 V
RT = 0 V
(1)
(1)
1.3
1.8
mA
200
345
µA
7.7
8.5
V
(2)
VIN - VCC
Vin = 9 V, FB = 1.4 V, ICC = 0 mA
6.9
Vin = 9 V, FB = 1.4 V, ICC = 20 mA
7.7
V
Vin = 75 V, FB = 1.4 V, ICC = 0 mA
7.7
V
VCC Under-Voltage Lock-out
Threshold
VCC Increasing
3.8
V
UVLOVcc Hysteresis
VCC Decreasing
260
mV
VCC Current Limit
FB = 1.4 V
40
mA
20
Operating current and shutdown current do not include the current in the RT resistor.
VCC provides self bias for the internal gate drive.
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Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. Unless otherwise stated the following conditions apply: VIN = 48 V, RT = 100kΩ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PGATE PIN
VPGATE(HI)
PGATE High Voltage
PGATE Pin = Open
VPGATE(LO)
PGATE Low Voltage
PGATE Pin = Open
VPGATE(HI)4.5
PGATE High Voltage at Vin = 4.5V
PGATE Pin = Open
VPGATE(LO)4.5
PGATE Low Voltage at Vin = 4.5V
PGATE Pin = Open
VCC
Driver Output Source Current
VIN = 12 V, PGATE = VIN - 3.5 V
1.75
Driver Output Sink Current
VIN = 12 V, PGATE = VIN - 3.5 V
1.5
A
Driver Output Resistance
Source Current = 500 mA
2.3
Ω
Sink Current = 500 mA
2.3
Ω
IPGATE
RPGATE
VIN -0.1
VIN
VCC
VIN -0.1
V
VCC+0.1
VIN
V
V
VCC+0.1
V
A
CURRENT LIMIT DETECTION
IADJ
ADJUST Pin Current Source
VADJ = 46.5 V
32
40
48
µA
Current Limit Comparator Offset
VADJ = 46.5 V, VADJ - VISEN
-9
0
9
mV
RTSD
Shutdown Threshold
RT Pin Voltage Rising
RTHYS
Shutdown Threshold Hysteresis
VCL
OFFSET
RT PIN
0.73
V
50
mV
ON-TIME
tON – 1
On-Time
tON – 2
tON - 3
tON - 4
Minimum On-Time in Current Limit
(3)
VIN = 4.5 V, RT = 100kΩ
3.5
5
7.15
µs
VIN = 48 V, RT = 100kΩ
276
360
435
ns
VIN = 75 V, RT = 100kΩ
177
235
285
ns
55
140
235
ns
VIN = 48 V, 25 mV Overdrive at ISEN
OFF-TIME
tOFF(CL1)
VIN = 12 V, VFB = 0 V
5.35
7.9
10.84
µs
tOFF(CL2)
VIN = 12 V, VFB = 1 V
1.42
1.9
3.03
µs
tOFF(CL3)
Off-Time (Current Limit)
(3)
tOFF(CL4)
VIN = 48 V, VFB = 0 V
16
24
32.4
µs
VIN = 48 V, VFB = 1 V
3.89
5.7
8.67
µs
1.225
1.25
1.275
V
REGULATION AND OVERVOLTAGE COMPARATORS (FB PIN)
VREF
FB Regulation Threshold
VOV
FB Over-Voltage Threshold
IFB
FB Bias Current
Measured with Respect to VREF
350
mV
10
nA
SOFT-START FUNCTION
tSS
Soft-Start Time
1.4
2.5
4.3
ms
THERMAL SHUTDOWN
(3)
TSD
Junction Shutdown Temperature
THYS
Junction Shutdown Hysteresis
Junction Temperature Rising
170
°C
20
°C
The tolerance of the minimum on-time (tON-4) and the current limit off-times (tOFF(CL1) through (tOFF(CL4)) track each other over process
and temperature variations. A device which has an on-time at the high end of the range will have an off-time that is at the high end of its
range.
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6.7 Typical Characteristics
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V.
6
Figure 1. Efficiency (Circuit of Figure 25)
Figure 2. Input Operating Current vs. VIN
Figure 3. Shutdown Current vs. VIN
Figure 4. VCC vs. VIN
Figure 5. VCC vs. ICC
Figure 6. On-Time vs. RT and VIN
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V.
VOLTAGE AT THE RT PIN (V)
4
25 k:
50 k:
3
100 k:
200 k:
2
RT = 500 k:
300 k:
1
0
0
10
20
30
40
50
60
70
80
VIN (V)
Figure 7. Off-Time vs. VIN and VFB
Figure 8. Voltage at the RT Pin
Figure 9. ADJ Pin Current vs. VIN
Figure 10. Input Operating Current vs. Temperature
Figure 11. Shutdown Current vs. Temperature
Figure 12. VCC vs. Temperature
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V.
8
Figure 13. On-Time vs. Temperature
Figure 14. Minimum On-Time vs. Temperature
Figure 15. Off-Time vs. Temperature
Figure 16. Current Limit Comparator Offset vs. Temperature
Figure 17. ADJ Pin Current vs. Temperature
Figure 18. PGATE Driver Output Resistance vs.
Temperature
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V.
Figure 19. Feedback Reference Voltage vs. Temperature
Figure 20. Soft-Start Time vs. Temperature
Figure 21. RT Pin Shutdown Threshold vs. Temperature
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LM5085, LM5085-Q1
SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015
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7 Detailed Description
7.1 Overview
The LM5085 is a PFET buck (step-down) DC-DC controller using the constant on-time (COT) control principle.
The input operating voltage range of the LM5085 is 4.5V to 75V. The use of a PFET in a buck regulator greatly
simplifies the gate drive requirements and allows for 100% duty cycle operation to extend the regulation range
when operating at low input voltage. However, PFET transistors typically have higher on-resistance and gate
charge when compared to similarly rated NFET transistors. Consideration of available PFETs, input voltage
range, gate drive capability of the LM5085, and thermal resistances indicate an upper limit of 10A for the load
current for LM5085 applications. Constant on-time control is implemented using an on-time one-shot that is
triggered by the feedback signal. During the off-time, when the PFET (Q1) is off, the load current is supplied by
the inductor and the output capacitor. As the output voltage falls, the voltage at the feedback comparator input
(FB) falls below the regulation threshold. When this occurs Q1 is turned on for the one-shot period which is
determined by the input voltage (VIN) and the RT resistor. During the on-time the increasing inductor current
increases the voltage at FB above the feedback comparator threshold. For a buck regulator the basic relationship
between the on-time, off-time, input voltage and output voltage is:
Duty Cycle =
VOUT
VIN
=
tON
tON + tOFF
= tON x FS
(1)
where Fs is the switching frequency. Equation 1 is valid only in continuous conduction mode (inductor current
does not reach zero). Since the LM5085 controls the on-time inversely proportional to VIN, the switching
frequency remains relatively constant as VIN is varied. If the input voltage falls to a level that is equal to or less
than the regulated output voltage Q1 is held on continuously (100% duty cycle) and VOUT is approximately equal
to VIN.
The COT control scheme, with the feedback signal applied to a comparator rather than an error amplifier,
requires no loop compensation, resulting in very fast load transient response.
The LM5085 is available in both an 8-pin HVSSOP package and an 8-pin WSON package with an exposed pad
to aid in heat dissipation. An 8-pin VSSOP package without an exposed pad is also available.
7.2 Functional Block Diagram
4.5V to 75V
Input
VIN
GND
Negative Bias
Regulator
VIN
CIN
7.7V
CBYP
LM5085
+
-
0.73V
RT
+
CVCC
CADJ
Thermal
Shutdown
RT
+
VCC
VIN
RADJ
VCC
UVLO
ON Time
One-Shot
Gate
Driver
RSEN
PGATE
Q1
SHUTDOWN
VCC
1.25V
Soft-Start
Gate Driver
Control Logic
L1
ADJ
COUT
40 PA
GND
+
QS
-
R
REGULATION
COMPARATOR
1.6V -
D1
+
-
CURRENT
LIMIT
OFF Time
COMPARATOR
One-Shot
VOUT
R3 C1
C2
RFB2
ISEN
RFB1
+
OVER-VOLTAGE
COMPARATOR
VIN
FB
Sense resistor method shown for current limit detection.
Minimum output ripple configuration shown.
10
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7.3 Feature Description
7.3.1 Regulation Control Circuit
The LM5085 buck DC-DC controller employs a control scheme based on a comparator and a one-shot on-timer,
with the output voltage feedback compared to an internal reference voltage (1.25V). When the FB pin voltage
falls below the feedback reference, Q1 is switched on for a time period determined by the input voltage and a
programming resistor (RT). Following the on-time Q1 remains off until the FB voltage falls below the reference.
Q1 is then switched on for another on-time period. The output voltage is set by the feedback resistors (RFB1, RFB2
in the Block Diagram). The regulated output voltage is calculated as follows:
VOUT = 1.25V x (RFB2+ RFB1)/ RFB1
(2)
The feedback voltage supplied to the FB pin is applied to a comparator rather than a linear amplifier. For proper
operation sufficient ripple amplitude is necessary at the FB pin to switch the comparator at regular intervals with
minimum delay and noise susceptibility. This ripple is normally obtained from the output voltage ripple attenuated
through the feedback resistors. The output voltage ripple is a result of the inductor’s ripple current passing
through the output capacitor’s ESR, or through a resistor in series with the output capacitor. Multiple methods are
available to ensure sufficient ripple is supplied to the FB pin, and three different configurations are discussed in
the Typical Application section.
When in regulation, the LM5085 operates in continuous conduction mode at medium to heavy load currents and
discontinuous conduction mode at light load currents. In continuous conduction mode the inductor’s current is
always greater than zero, and the operating frequency remains relatively constant with load and line variations.
The minimum load current for continuous conduction mode is one-half the inductor’s ripple current amplitude. In
discontinuous conduction mode, where the inductor’s current reaches zero during the off-time, the operating
frequency is lower than in continuous conduction mode and varies with load current. Conversion efficiency is
maintained at light loads since the switching losses are reduced with the reduction in load and frequency.
If the voltage at the FB pin exceeds 1.6V due to a transient overshoot or excessive ripple at VOUT the internal
over-voltage comparator immediately switches off Q1. The next on-time period starts when the voltage at FB falls
below the feedback reference voltage.
7.3.2 On-Time Timer
The on-time of the PFET gate drive output (PGATE pin) is determined by the resistor (RT) and the input voltage
(VIN), and is calculated from:
-7
tON =
1.45 x 10 x (RT + 1.4)
(VIN - 1.56V + RT/3167)
+ 50 ns
(3)
where RT is in kΩ.
The minimum on-time, which occurs at maximum VIN, should not be set less than 150ns (see Current Limiting
section). The buck regulator effective on-time, measured at the SW node (junction of Q1, L1, and D1) is typically
longer than that calculated in Equation 3 due to the asymmetric delay of the PFET. The on-time difference
caused by the PFET switching delay can be estimated as the difference of the turn-off and turn-on delays listed
in the PFET data sheet. Measuring the difference between the on-time at the PGATE pin versus the SW node in
the actual application circuit is also recommended.
In continuous conduction mode, the inverse relationship of tON with VIN results in a nearly constant switching
frequency as VIN is varied. The operating frequency can be calculated from:
FS =
VOUT x (VIN - 1.56V + RT/3167)
-7
VIN x [(1.45 x 10 x (RT + 1.4)) + (tD x (VIN - 1.56V + RT/3167))]
(4)
where RT is in kΩ, and tD is equal to 50ns plus the PFET’s delay difference. To set a specific continuous
conduction mode switching frequency (FS), the RT resistor is determined from the following:
RT =
VOUT x (VIN - 1.56V)
-7
1.45 x 10 x VIN x FS
-
tD x (VIN - 1.56V)
1.45 x 10
-7
- 1.4
(5)
where RT is in kΩ. A simplified version of Equation 5 at VIN = 12V, and tD = 100ns, is:
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Feature Description (continued)
RT =
VOUT x 6 x 106
- 8.6
FS
(6)
For VIN = 48V and tD = 100ns, the simplified equation is:
RT =
VOUT x 6.67 x 106
- 33.4
FS
(7)
7.3.3 Shutdown
The LM5085 can be shutdown by grounding the RT pin (see Figure 22). In this mode the PFET is held off, and
the VCC regulator is disabled. The internal operating current is reduced to the value shown in the graph
“Shutdown current vs. VIN”. The shutdown threshold at the RT pin is ≊0.73V, with ≊50mV of hysteresis.
Releasing the pin enables normal operation. The RT pin must not be forced high during normal operation.
VIN
Input
Voltage
LM5085
RT
RT
STOP
RUN
Figure 22. Shutdown Implementation
7.3.4 Current Limiting
The LM5085 current limiting operates by sensing the voltage across either the RDS(ON) of Q1, or a sense resistor,
during the on-time and comparing it to the voltage across the resistor RADJ (see Figure 23). The current limit
function is much more accurate and stable over temperature when a sense resistor is used. The RDS(ON) of a
MOSFET has a wide process variation and a large temperature coefficient.
If the voltage across RDS(ON) of Q1, or the sense resistor, is greater than the voltage across RADJ, the current limit
comparator switches to turn off Q1. Current sensing is disabled for a blanking time of ≊100ns at the beginning of
the on-time to prevent false triggering of the current limit comparator due to leading edge current spikes.
Because of the blanking time and the turn-on and turn-off delays created by the PFET, the on-time at the PGATE
pin should not be set less than 150ns. An on-time shorter than that may prevent the current limit detection circuit
from properly detecting an over-current condition. The duration of the subsequent forced off-time is a function of
the input voltage and the voltage at the FB pin, as shown in the graph “Off-time vs. VIN and VFB”. The longerthan-normal forced off-time allows the inductor current to decrease to a low level before the next on-time. This
cycle-by-cycle monitoring, followed by a forced off-time, provides effective protection from output load faults over
a wide range of operating conditions.
The voltage across the RADJ resistor is set by an internal 40µA current sink at the ADJ pin. When using Q1’s
RDS(ON) for sensing, the current at which the current limit comparator switches is calculated from:
ICL = 40µA x RADJ/RDS(ON)
(8)
When using a sense resistor (RSEN) the threshold of the current limit comparator is calculated from:
ICL = 40µA x RADJ/RSEN
(9)
When using Equation 8 or Equation 9, the tolerances for the ADJ pin current sink and the offset of the current
limit comparator should be included to ensure the resulting minimum current limit is not less than the required
maximum switch current. Simultaneously increasing the values of RADJ and RSEN decreases the effects of the
current limit comparator offset, but at the expense of higher power dissipation. When using a sense resistor, the
RSEN resistor value should be chosen within the practical limitations of power dissipation and physical size. For
example, for a 10A current limit, setting RSEN = 0.005Ω results in a power dissipation as high as 0.5W. Current
sense connections to the RSEN resistor, or to Q1, must be Kelvin connections to ensure accuracy.
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Feature Description (continued)
The CADJ capacitor filters noise from the ADJ pin, and helps prevent unintended switching of the current limit
comparator due to input voltage transients. The recommended value for CADJ is 1000pF.
7.3.5 Current Limit Off-Time
When the current through Q1 exceeds the current limit threshold, the LM5085 forces an off-time longer than the
normal off-time defined by Equation 1. See the graph “Off-Time vs. VIN and VFB”, or calculate the current limit offtime from the following equation:
-6
tOFF(CL) =
4.1 x 10 x ((VIN/31) + 0.15)
(VFB x 0.93) + 0.28V
(10)
where VIN is the input voltage, and VFB is the voltage at the FB pin at the time current limit was detected. This
feature is necessary to allow the inductor current to decrease sufficiently to offset the current increase which
occurred during the on-time. During the on-time, the inductor current increases an amount equal to:
(VIN - VOUT) x tON
'I =
L
(11)
During the off-time the inductor current decreases due to the reverse voltage applied across the inductor by the
output voltage, the freewheeling diode’s forward voltage (VFD), and the voltage drop due to the inductor’s series
resistance (VESR). The current decrease is equal to:
'I =
(VOUT + VFD + VESR) x tOFF
L
(12)
The on-time in Equation 11 is shorter than the normal on-time since the PFET is shut off when the current limit
threshold is crossed. If the off-time is not long enough, such that the current decrease (Equation 12) is less than
the current increase (Equation 11), the current levels are higher at the start of the next on-time. This results in a
further decrease in on-time, since the current limit threshold is crossed sooner. A balance is reached when the
current changes in Equation 11 and Equation 12 are equal. The worst case situation is that of a direct short
circuit at the output terminals, where VOUT = 0V, as that results in the largest current increase during the on-time,
and the smallest decrease during the off-time. The sum of the diode’s forward voltage and the inductor’s ESR
voltage must be sufficient to ensure current runaway does not occur. Using Equation 11 and Equation 12, this
requirement can be stated as:
VFD + VESR t
VIN x tON
tOFF
(13)
For tON in Equation 13, use the minimum on-time at the SW node. To determine this time period add the
“Minimum On-Time in Current Limit” specified in the Electrical Characteristics (tON-4) to the difference of the turnoff and turn-on delays of the PFET. For tOFF use the value in the graph “Off-Time vs. VIN and VFB”, or use
Equation 10, where VFB is equal to zero volts. When using the minimum or maximum limits of those
specifications to determine worst case situations, the tolerance of the minimum on-time (tON-4) and the current
limit off-times (tOFF(CL1) through tOFF(CL4)) track each other over the process and temperature variations. A device
which has an on-time at the high end of the range will have an off-time that is at the high end of its range.
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Feature Description (continued)
LM5085
ADJ
VIN
RADJ
ADJ
40 PA
40 PA
CURRENT LIMIT
COMPARATOR
+
-
VIN
LM5085
RADJ
CURRENT LIMIT
COMPARATOR
CADJ
+
-
ISEN
VIN GATE
DRIVER
ISEN
VIN
L1
Q1
PGATE
RSEN
CADJ
GATE
DRIVER
Q1
PGATE
VCC
L1
VCC
D1
D1
USING Q1 RDS(ON)
USING SENSE RESISTOR RSEN
Figure 23. Current Limit Sensing
7.3.6 VCC Regulator
The VCC regulator provides a regulated voltage between the VIN and the VCC pins to provide the bias and gate
current for the PFET gate driver. The 0.47µF capacitor at the VCC pin must be a low ESR capacitor, preferably
ceramic as it provides the high surge current for the PFET’s gate at each turn-on. The capacitor must be located
as close as possible to the VIN and VCC pins to minimize inductance in the PC board traces.
Referring to Figure 4 “VCC vs. VIN”, the voltage across the VCC regulator (VIN – VCC) is equal to VIN until VIN
reaches approximately 8.5V. At higher values of VIN, the voltage at the VCC pin is regulated at approximately
7.7V below VIN. If VIN drops below about 8V due to voltage transients, the VCC pin can be pulled down below
GND. To prevent the negative VCC voltage from disturbing the internal circuit and causing abnormal operation,
Figure 24 shows the required placement of this Schottky diode between the VCC pin and GND pin. The Schottky
diode should be placed as close as possible to the VCC pin. The VCC regulator has a maximum current
capability of at least 20mA. The regulator is disabled when the LM5085 is shutdown using the RT pin, or when
the thermal shutdown is activated.
CVCC
4.5V to 75V
Input
LM5085
VIN
VIN
VCC
CIN
D2
(Optional)
CADJ
ADJ
GND
RT
RADJ
L1
PGATE
Q1
SHUTDOWN
RT
VOUT
ISEN
D1
GND
Cff
COUT
RFB2
GND
FB
RFB1
Figure 24. Schottky Diode at VCC Pin During VIN Negative Transients (VIN < 8 V)
7.3.7 PGATE Driver Output
The PGATE pin output swings between VIN (Q1 off) and the VCC pin voltage (Q1 on). The rise and fall times
depend on the PFET gate capacitance and the source and sink currents provided by the internal gate driver. See
the Electrical Characteristics for the current capability of the driver.
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Feature Description (continued)
7.3.8 P-Channel MOSFET Selection
The PFET must be rated for the maximum input voltage, with some margin above that to allow for transients and
ringing which can occur on the supply line and the switching node. The gate-to-source voltage (VGS) normally
provided to the PFET is 7.7V for VIN greater than 8.5V. However, if the circuit is to be operated at lower values
of VIN, the selected PFET must be able to fully turn-on with a VGS voltage equal to VIN. The minimum input
operating voltage for the LM5085 is 4.5V.
Similar to NFETs, the case or exposed thermal pad for a PFET is electrically connected to the drain terminal.
When designing a PFET buck regulator the drain terminal is connected to the switching node. This situation
requires a trade-off between thermal and EMI performance since increasing the PC board area of the switching
node to aid the PFET power dissipation also increases radiated noise, possibly disrupting the circuit operation.
Typically the switching node area is kept to a reasonable minimum and the PFET peak current is derated to stay
within the recommended temperature rating of the PFET. The RDS(ON) of the PFET determines a portion of the
power dissipation in the PFET. However, PFETs with very low RDS(ON) usually have large values of gate charge.
A PFET with a higher gate charge has a corresponding slower switching speed, leading to higher switching
losses and affecting the PFET power dissipation.
If the PFET RDS(ON) is used for current limit detection, note that it typically has a positive temperature coefficient.
At 100°C the RDS(ON) may be as much as 50% higher than the value at 25°C which could result in incorrect
current limiting if not accounted for when determining the value of the RADJ resistor. The PFET Total Gate
Charge determines most of the power dissipation in the LM5085 due to the repetitive charge and discharge of
the PFET’s gate capacitance by the gate driver (powered from the VCC regulator). The LM5085’s internal power
dissipation can be calculated from the following:
PDISS = VIN x ((QG x FS) + IIN)
(14)
where QG is the PFET's Total Gate Charge obtained from its datasheet, FS is the switching frequency, and IIN is
the LM5085's operating current obtained from the graph "Input Operating Current vs. VIN". Using the Thermal
Resistance specifications in the Electrical Characteristics table, the approximate junction temperature can be
determined. If the calculated junction temperature is near the maximum operating temperature of 125°C, either
the switching frequency must be reduced, or a PFET with a smaller Total Gate Charge must be used.
7.3.9 Soft-Start
The internal soft-start feature of the LM5085 allows the regulator to gradually reach a steady state operating
point at power up, thereby reducing startup stresses and current surges. Upon turn-on, when Vcc reaches its
under-voltage lockout threshold, the internal soft-start circuit ramps the feedback reference voltage from 0V to
1.25V, causing VOUT to ramp up in a proportional manner. The soft-start ramp time is typically 2.5ms.
In addition to controlling the initial power up cycle, the soft-start circuit also activates when the LM5085 is
enabled by releasing the RT pin, and when the circuit is shutdown and restarted by the internal Thermal
Shutdown circuit.
If the voltage at FB is below the regulation threshold value due to an over-current condition or a short circuit at
VOUT, the internal reference voltage provided by the soft-start circuit to the regulation comparator is reduced
along with FB. When the over-current or short circuit condition is removed, VOUT returns to the regulated value at
a rate determined by the soft-start ramp. This feature helps prevent the output voltage from overshooting
following an overload event.
7.3.10 Thermal Shutdown
The LM5085 should be operated such that the junction temperature does not exceed 125°C. If the junction
temperature increases above that, an internal Thermal Shutdown circuit activates at 170°C (typical) to disable
the VCC regulator and the gate driver, and discharge the soft-start capacitor. This feature helps prevent
catastrophic failures from accidental device overheating. When the junction temperature falls below 150°C
(typical hysteresis = 20°C), the gate driver is enabled, the soft-start circuit is released, and normal operation
resumes.
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7.4 Device Functional Modes
7.4.1 Standby Mode with VIN IOUT/2.
D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed
transitions at the SW node may affect the regulator’s operation due to the diode’s reverse recovery transients.
The diode must be rated for the maximum input voltage, and the worst case current limit level. The average
power dissipation in the diode is calculated from:
PD1 = VF x IOUT x (1-D)
(30)
where VF is the diode’s forward voltage drop, and D is the on-time duty cycle. Using Equation 1, the minimum
duty cycle occurs at maximum input voltage, and is calculated to be ≊9.1% in this example. The diode power
dissipation calculates to be:
PD1 = 0.65V x 5A x (1- 0.091) = 2.95W
(31)
CVCC: The capacitor at the VCC pin (from VIN to VCC) provides not only noise filtering and stability for the VCC
regulator, but also provides the surge current for the PFET gate drive. The typical recommended value for CVCC
is 0.47µF. A good quality, low ESR, ceramic capacitor is recommended. CVCC must be located as close as
possible to the VIN and VCC pins. If the selected PFET has a Total Gate Charge specification of 100nC or
larger, or if the circuit is required to operate at input voltages below 7V, a larger capacitor may be required. The
maximum recommended value for CVCC is 1µF.
IC Power Dissipation: The maximum power dissipated in the LM5085 package is calculated using Equation 14
at the maximum input voltage. The Total Gate Charge for the Si7465 PFET is specified to be 40nC (max) in its
data sheet. Therefore the total power dissipation within the LM5085 is calculated to be:
PDISS = 55V x ((40nC x 300kHz) + 1.4mA) = 737mW
(32)
Using an HVSSOP package with a θJA of 46°C/W produces a temperature rise of 34°C from junction to ambient.
8.2.2.2 Alternate Output Ripple Configurations
The minimum ripple configuration employing C1, C2, and R3 in Figure 25 results in a low ripple amplitude at
VOUT determined mainly by the characteristics of the output capacitor and the ripple current in L1. This
configuration allows multiple ceramic capacitors to be used for VOUT if the output voltage is provided to several
places on the PC board. However, if a slightly higher level of ripple at VOUT is acceptable in the application, and
distributed capacitance is not used, the ripple required for the FB comparator pin can be generated with fewer
external components using the circuits shown below.
a) Reduced ripple configuration: In Figure 27, R3, C1 and C2 are removed (compared to Figure 25). A low
value resistor (R4) is added in series with COUT, and a capacitor (Cff) is added across RFB2. Ripple is generated
at VOUT by the inductor ripple current flowing through R4, and that ripple voltage is passed to the FB pin via Cff.
The ripple at VOUT can be set as low as 25 mVp-p since it is not attenuated by RFB2 and RFB1. The minimum
value for R4 is calculated from:
R4 =
25 mV
IOR(min)
(33)
where IOR(min) is the minimum ripple current, which occurs at minimum input voltage. The minimum value for Cff
is determined from:
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Typical Application (continued)
3 x tON(max)
Cff =
(RFB1//RFB2)
(34)
where tON(max) is the maximum on-time, which occurs at minimum VIN. The next larger standard value capacitor
should be used for Cff.
LM5085
L1
PGATE
VOUT
Q1
D1
Cff
RFB2
R4
FB
COUT
GND
RFB1
GND
Figure 27. Reduced Ripple Configuration
b) Lowest cost configuration: This configuration, shown in Figure 28, is the same as Figure 27 except Cff is
removed. Since the ripple voltage at VOUT is attenuated by RFB2 and RFB1, the minimum ripple required at VOUT is
equal to:
VRIP(min) = 25mV x (RFB2 + RFB1)/RFB1
(35)
The minimum value for R4 is calculated from:
R4 =
VRIP(min)
IOR(min)
(36)
where IOR(min) is the minimum ripple current, which occurs at minimum input voltage.
LM5085
L1
PGATE
Q1
D1
VOUT
RFB2
FB
R4
COUT
GND
RFB1
GND
Figure 28. Lowest Cost Ripple Generating Configuration
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Typical Application (continued)
8.2.3 Application Curves
22
Figure 29. Efficiency vs. Load Current and VIN
(Circuit of Figure 25)
Figure 30. Frequency vs. VIN
(Circuit of Figure 25)
Figure 31. Current Limit vs. VIN
(Circuit of Figure 25)
Figure 32. LM5085 Power Dissipation
(Circuit of Figure 25)
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9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 75 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the device, additional
bulk capacitance may be required at the input terminals of the converter in addition to the calculated values to
limit the inductive spikes due to the input cables or wires.
10 Layout
10.1 Layout Guidelines
In most applications, the heat sink pad or tab of Q1 is connected to the switch node, i.e. the junction of Q1, L1
and D1. While it is common to extend the PC board pad from under these devices to aid in heat dissipation, the
pad size should be limited to minimize EMI radiation from this switching node. If the PC board layout allows, a
similarly sized copper pad can be placed on the underside of the PC board, and connected with as many vias as
possible to aid in heat dissipation.
The voltage regulation, over-voltage, and current limit comparators are very fast and can respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be
as neat and compact as possible with all the components as close as possible to their associated pins. Two
major current loops conduct currents which switch very fast, requiring the loops to be as small as possible to
minimize conducted and radiated EMI. The first loop is that formed by CIN, Q1, L1, COUT, and back to CIN. The
second loop is that formed by D1, L1, COUT, and back to D1. The connection from the anode of D1 to the ground
end of CIN must be short and direct. CIN must be as close as possible to the VIN and GND pins, and CVCC must
be as close as possible to the VIN and VCC pins.
If the anticipated internal power dissipation of the LM5085 will produce excessive junction temperatures during
normal operation, a package option with an exposed pad must be used (HVSSOP-8 or WSON-8). Effective use
of the PC board ground plane can help dissipate heat. Additionally, the use of wide PC board traces, where
possible, helps conduct heat away from the IC. Judicious positioning of the PC board within the end product,
along with the use of any available air flow (forced or natural convection) also helps reduce the junction
temperature.
10.2 Layout Example
RT and ADJ
Connections
(Tap to CIN)
VIN
Keep
CIN, D1, Q1
Exposed Pad on Bottom
Connect to Ground
Loop Small
RSEN
ADJ 1
8 VIN
RT 2
7 VCC
FB
3
6 PGATE
GND
4
5 ISEN
Q1
CVCC
CIN
L1
VOUT
D1
COUT
GND
RFB1
Figure 33. LM5085 Buck Converter Layout Example
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM5085
Click here
Click here
Click here
Click here
Click here
LM5085-Q1
Click here
Click here
Click here
Click here
Click here
11.2 Trademarks
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5085MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SSTB
LM5085MME/NOPB
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SSTB
LM5085MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SSTB
LM5085MY/NOPB
ACTIVE
HVSSOP
DGN
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SSSB
LM5085MYE/NOPB
ACTIVE
HVSSOP
DGN
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SSSB
LM5085MYX/NOPB
ACTIVE
HVSSOP
DGN
8
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SSSB
LM5085QMY/NOPB
ACTIVE
HVSSOP
DGN
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SYCB
LM5085QMYE/NOPB
ACTIVE
HVSSOP
DGN
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SYCB
LM5085QMYX/NOPB
ACTIVE
HVSSOP
DGN
8
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SYCB
LM5085SD/NOPB
ACTIVE
WSON
NGQ
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L245B
LM5085SDE/NOPB
ACTIVE
WSON
NGQ
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L245B
LM5085SDX/NOPB
ACTIVE
WSON
NGQ
8
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L245B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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