LM5088, LM5088-Q1
SNVS600J – DECEMBER 2008 – REVISED JUNE 2022
LM5088, LM5088-Q1 Wide Input Range Non-Synchronous Buck Controller
1 Features
3 Description
•
The LM5088 high voltage non-synchronous buck
controller features all the necessary functions to
implement an efficient, high-voltage buck converter
using a minimum number of external components.
The LM5088 can be configured to operate over an
ultra-wide input voltage range of 4.5 V to 75 V. This
easy-to-use controller includes a level-shifted gate
driver capable of controlling an external N-channel
buck switch. The control method is based upon peak
current mode control utilizing an emulated current
ramp. The use of an emulated control ramp reduces
noise sensitivity of the pulse-width modulation circuit,
allowing reliable control of very small duty cycles
necessary in high input voltage and low output voltage
applications. The LM5088 switching frequency is
programmable from 50 kHz to 1 MHz.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C5
Emulated current mode control
Drives external high-side N-channel MOSFET
Ultra-wide input voltage range from 4.5 V to 75 V
Low IQ shutdown and standby modes
High duty cycle ratio feature for reduced dropout
voltage
Spread spectrum EMI reduction (LM5088-1)
Hiccup timer for overload protection (LM5088-2)
Adjustable output voltage from 1.205 V with 1.5%
feedback reference accuracy
Wide bandwidth error amplifier
Single resistor oscillator frequency setting
Oscillator synchronization capability
Programmable soft start
High voltage, low dropout bias regulator
Thermal shutdown protection
16-pin HTSSOP package
2 Applications
•
•
•
Automotive infotainment
Automotive USB accessory adapters
Industrial DC-DC bias and motor drivers
The LM5088 is available in two versions: The
LM5088-1 provides a ±5% frequency dithering
function to reduce the conducted and radiated EMI,
while the LM5088-2 provides a versatile restart timer
for overload protection. Additional features include
a low dropout bias regulator, tri-level enable input
to control shutdown and standby modes, soft start,
and oscillator synchronization capability. The device
is available in a thermally enhanced 16-pin HTSSOP
package.
Device Information
Part Number
LM5088
LM5088-Q1
(1)
Package(1)
HTSSOP (16)
Body Size (NOM)
5.00 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
VIN (4.5 V-75 V)
RUV2
VIN
EN
BOOT
CBOOT
Q
RUV1
CIN
HG
DITH/RES
L
VOUT
SW
CDITHER/RESTART
RFB2
D
COUT1
CS
VCC
LM5088
RRAMP
CVCC
CSS
CSG
SS
OUT
RT/SYNC
RFB1
FB
RRT
RCOMP
GND
COUT2
Rs
RAMP
CRAMP
CCOMP
COMP
CHF
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
Typical Application Circuit Efficiency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5088, LM5088-Q1
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SNVS600J – DECEMBER 2008 – REVISED JUNE 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings: LM5088................................................ 5
6.3 ESD Ratings: LM5088-Q1.......................................... 5
6.4 Recommended Operating Conditions.........................5
6.5 Thermal Information....................................................6
6.6 Electrical Characteristics.............................................6
6.7 Typical Characteristics................................................ 8
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................20
8 Application and Implementation.................................. 21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
9 Power Supply Recommendations................................32
9.1 Thermal Considerations............................................32
10 Layout...........................................................................34
10.1 Layout Guidelines................................................... 34
10.2 Layout Example...................................................... 34
11 Device and Documentation Support..........................35
11.1 Receiving Notification of Documentation Updates.. 35
11.2 Support Resources................................................. 35
11.3 Trademarks............................................................. 35
11.4 Electrostatic Discharge Caution.............................. 35
11.5 Glossary.................................................................. 35
12 Mechanical, Packaging, and Orderable
Information.................................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (August 2014) to Revision J (June 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated AEC-Q100 bullet to the latest standard................................................................................................1
• Corrected grammar throughout document..........................................................................................................1
• Added EP as pin 17............................................................................................................................................ 3
• Changed all instances of legacy terminology to controller..................................................................................3
• Moved storage temperature from ESD Ratings to Absolute Maximum Ratings ................................................ 5
• Changed unit and value from kV to V in ESD Ratings .......................................................................................5
• Changed Handling Ratings to ESD Ratings....................................................................................................... 5
• Moved storage temperature to Absolute Maximum Ratings...............................................................................5
• Added new ESD ratings table for LM5088-Q1....................................................................................................5
• Added application and implementation note.....................................................................................................21
Changes from Revision H (March 2013) to Revision I (March 2013)
Page
• Changed data sheet flow and layout to conform with new TI standards. Added the Device Information table,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ........... 1
• Changed (VIN × VOUT) to (VIN – VOUT) in Ramp Generator equation..............................................................13
• Added unit kΩ to the standard value chosen for the Timing Resistor equation................................................21
• Deleted /A from the numerator of the Current Sense Resistor equation.......................................................... 24
2
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SNVS600J – DECEMBER 2008 – REVISED JUNE 2022
5 Pin Configuration and Functions
VIN
VCC
VIN
VCC
EN
BOOT
EN
BOOT
SS
HG
SS
HG
RAMP
RAMP
SW
SW
HTSSOP-16
HTSSOP-16
RT
CS
GND
RT
CSG
CS
GND
CSG
EP
EP
COMP
DITH
COMP
RES
FB
OUT
FB
OUT
Figure 5-1. 16-Pin PWP Package (Dither Version)
(Top View)
Figure 5-2. 16-Pin PWP Package (Restart Version)
(Top View)
Table 5-1. Pin Functions
Pin
Number
1
2
VIN
EN
3
SS
4
RAMP
5
6
Description
Name
Application Information
Input supply voltage
IC supply voltage. The operating range is 4.5 V to 75 V.
Enable input
If the EN pin voltage is below 0.4 V, the regulator is in a low power state. If the
EN pin voltage is between 0.4 V and 1.2 V, the controller is in standby mode. If
the EN pin voltage is above 1.2 V, the controller is operational. An external voltage
divider can be used to set a line undervoltage shutdown threshold. If the EN pin
is left open, a 5-µA pullup current forces the pin to the high state and enables the
controller.
Soft start
When SS is below the internal 1.2-V reference, the SS voltage controls the error
amplifier. An internal 11-µA current source charges an external capacitor to set
the start-up rate of the controller. The SS pin is held low in the standby, VCC
UV, and thermal shutdown states. The SS pin can be used for voltage tracking
by connecting this pin to a controller voltage supply less than 1.2 V. The applied
voltage acts as the reference for the error amplifier.
Ramp control signal
An external capacitor connected between this pin and the GND pin sets the ramp
slope used for emulated current mode control. The recommended capacitor range
100 pF to 2000 pF. See Section 8 for selection of capacitor value.
Internal oscillator frequency
RT/SYNC set input and synchronization
input
GND
The internal oscillator is programmed with a single resistor between this pin
and the GND pin. The recommended frequency range is 50 kHz to 1 MHz. An
external synchronization signal, which is higher in frequency than the programmed
frequency, can be applied to this pin through a small coupling capacitor. The RT
resistor to ground is required even when using external synchronization.
Ground
Ground return
The loop compensation network must be connected between this pin and the FB
pin.
7
COMP
Output of the internal error
amplifier
8
FB
Feedback signal from the
regulated output
This pin is connected to the inverting input of the internal error amplifier. The
regulation threshold is 1.205 V.
9
OUT
Output voltage connection
Connect this pin directly to the regulated output voltage.
DITH
Frequency Dithering
(LM5088-1 Only)
A capacitor connected between DITH pin and GND is charged and discharged by
27-µA current sources. As the voltage on the DITH pin ramps up and down, the
oscillator frequency is modulated between –5% to +5% of the nominal frequency
set by the RT resistor. Grounding the DITH pin disables the frequency dithering
mode.
10
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Table 5-1. Pin Functions (continued)
Pin
Number
4
Name
Description
Application Information
10
RES
Hiccup Mode Restart
(LM5088-2 Only)
The RES pin is normally connected to an external capacitor that sets the timing
for hiccup mode current limiting. In normal operation, a 25-µA current source
discharges the RES pin capacitor to ground. If cycle-by-cycle current limit threshold
is exceeded during any PWM cycle, the current sink is disabled and RES capacitor
is charged by an internal 50-µA current. If the RES voltage reaches 1.2 V, the HG
pin gate drive signal is disabled and the RES pin capacitor is discharged by a 1-µA
current sink. Normal operation resumes when the RES pin falls below 0.2 V.
11
CSG
Current Sense Ground
Low-side reference for the current sense resistor
12
CS
Current sense
Current measurement connection for the re-circulating diode. An external sense
resistor and an internal sample and hold circuit sense the diode current at the
conclusion of the buck switch off time. This current measurement provides the DC
offset level for the emulated current ramp.
13
SW
Switching node
Connect this pin to the source terminal of the external MOSFET switch.
14
HG
High gate
Connect this pin to the gate terminal of the external MOSFET switch.
15
BOOT
Input for bootstrap capacitor
An external capacitor is required between the BOOT and the SW pins to provide
bias to the MOSFET gate driver. The capacitor is charged from VCC via an internal
diode during the off-time of the buck switch.
16
VCC
Output of the bias regulator
VCC tracks VIN up to the regulation level (7.8 V typical). A 0.1-µF to 10-µF ceramic
decoupling capacitor is required. An external voltage between 8.3 V and 13 V can
be applied to this pin to reduce internal power dissipation.
17
EP
Exposed pad
Exposed pad of the package. Electrically isolated. Must be soldered to the ground
plane to reduce thermal resistance.
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SNVS600J – DECEMBER 2008 – REVISED JUNE 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
76
V
90
V
76
V
VIN, VOUT to GND
BOOT to GND
SW to GND
–2
VCC to GND
–0.3
16
V
HG to SW
–0.3
BOOT + 0.3
V
EN to GND
14
V
BOOT to SW
–0.3
16
V
CS, CSG to GND
–0.3
0.3
V
All other inputs to GND
–0.3
7
V
150
°C
150
°C
Junction temperature
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings: LM5088
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per JESD22- A114
VALUE
UNIT
±2000
V
±750
V
VALUE
UNIT
±2000
V
±750
V
(1)
Charged Device Model (CDM), per JESD22-C101 (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings: LM5088-Q1
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
Charged Device Model (CDM), per AEC Q100-011
All pins
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN voltage
MIN
MAX
4.5
75
UNIT
V
VCC voltage (externally supplied)
8.3
13
V
Operation junction temperature
–40
125
°C
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6.5 Thermal Information
LM5088/LM5088-Q1
THERMAL
METRIC(1)
PWP
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
40
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Electrical Characteristics
See (2) (4)
PARAMETER
TEST CONDITIONS
TJ = –40°C to +125°C
MIN
TYP
MAX
TJ = 25°C
MIN
TYP
MAX
UNIT
VIN SUPPLY
IBIAS
VIN operating current
VFB = 1.3 V
5.5
3.8
mA
ISTANDBY
VIN standby current
VEN = 1 V
3.6
2.9
mA
ISHUTDOWN
VIN shutdown current
VEN = 0 V
26
15
µA
7.8
V
35
mA
VCC REGULATOR
VVCC(Reg)
VCC regulation
VVCC = open
7.4
8.2
VVCC(Reg)
VCC regulation
VVIN = 4.5 V, VVCC = open
4.3
4.5
VCC sourcing current limit
VVCC = 0
30
VCC undervoltage lockout
threshold
Positive going VVCC
3.7
VVCC(UV)
4.2
VCC undervoltage hysteresis
V
4
V
200
mV
400
mV
100
mV
ENABLE THRESHOLDS
EN shutdown threshold
VEN rising
EN shutdown hysteresis
VEN falling
320
EN standby threshold
VEN rising
1.2
V
EN standby hysteresis
VEN falling
120
mV
EN pullup current source
VEN = 0 V
5
µA
1.1
480
1.3
SOFT START
SS pullup current source
VSS = 0 V
FB to SS offset
VFB = 1.3 V
8
13
11
µA
150
mV
ERROR AMPLIFIER
VREF
FB reference voltage
Measured at FB pin
FB = COMP
FB input bias current
VFB = 1.2 V
COMP sink and source current
AOL
DC gain
FBW
Unity gain bandwidth
1.187
1.223
1.205
100
18
3
V
nA
mA
60
dB
3
MHz
PWM COMPARATORS
tHG(OFF)
Forced HG off time
tON(MIN)
Minimum HG on time
185
365
VVIN = 60 V
COMP to PWM comparator offset
280
ns
55
ns
930
mV
OSCILLATOR (RT PIN)
LM5088-2 (non-dithering)
fnom1
fnom2
6
Nominal oscillator frequency
RRT = 31.6 kΩ
180
220
200
kHz
RRT = 11.3 kΩ
430
565
500
kHz
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See (2) (4)
PARAMETER
TEST CONDITIONS
TJ = –40°C to +125°C
MIN
TYP
MAX
TJ = 25°C
MIN
TYP
MAX
UNIT
LM5088-1 (dithering)
fmin
Minimum dither frequency
fnom –
5%
kHz
Maximum dither frequency
fnom +
5%
kHz
Dithering range
fmax
SYNC
SYNC positive threshold
2.3
SYNC pulse width
15
150
112
136
V
ns
CURRENT LIMIT
VCS(TH)
Cycle-by-cycle sense voltage
threshold
VRAMP = 0 V
Cycle-by-cycle current limit delay
VRAMP = 2.5 V
280
ns
Buck switch VDS protection
VIN to SW
1.5
V
V
120
mV
CURRENT LIMIT RESTART (RES Pin)
Vresup
RES threshold upper (rising)
Vresdown
RES threshold lower (falling)
Icharge
Charge source current
VCS ≥ 0.125
Idischarge
Discharge sink current
VCS < 0.125
Irampdown
Discharge sink current (post fault)
RAMP
VCS = 0.125
1.1
1.3
1.2
0.1
0.3
0.2
V
40
65
50
µA
20
34
27
µA
0.8
1.6
1.2
µA
295
µA
25
µA
GENERATOR(1)
IRAMP1
RAMP current 1
VVIN = 60 V, VOUT = 10 V
235
345
IRAMP2
RAMP current 2
VVIN = 10 V, VOUT = 10 V
18
30
VOUT bias current
VOUT = 48 V
250
µA
RAMP output low voltage
VVIN = 60 V, VOUT = 10 V
200
mV
115
mV
240
mV
HIGH SIDE (HG) GATE DRIVER
VOLH
HG low-state output voltage
IHG = 100 mA
VOHH
HG high-state output voltage
IHG = –100 mA,
VOHH = VBOOT – VHG
HG rise time
Cload = 1000 pF
12
ns
HG fall time
Cload = 1000 pF
6
ns
IOHH
Peak HG source current
VHG = 0 V
1.5
A
IOLH
Peak HG sink current
VHG = VVCC
2
A
BOOT UVLO
BOOT to SW
3
V
IVCC = 1 mA
72
Ω
300
ns
Pre RDS(ON) Pre-charge switch ON resistance
Pre-charge switch on time
215
THERMAL(3)
TSD
(1)
(2)
(3)
(4)
Thermal shutdown temperature
Junction temperature rising
165
°C
Thermal shutdown hysteresis
Junction temperature falling
25
°C
RAMP and COMP are output pins. As such they are not specified to have an external voltage applied.
Typical specifications represent the most likely parametric norm at 25°C operation.
For detailed information on soldering plastic HTSSOP packages, visit www.ti.com/packaging.
Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent at TJ = 25°C, and
are provided for reference purposes only. Unless otherwise stated the following conditions apply: VVIN = 48 V, VVCC = 8 V, VEN = 5 V,
RRT = 31.6 kΩ. No load on HG.
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6.7 Typical Characteristics
8
Figure 6-1. Typical Application Circuit Efficiency
Figure 6-2. VCC vs VIN
Figure 6-3. VVCC vs IVCC
Figure 6-4. Shutdown Current
Figure 6-5. Frequency vs RRT
Figure 6-6. Frequency vs VVCC
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Figure 6-9. Soft Start vs Temperature
Figure 6-10. Current Limit vs Temperature
50
150
40
120
30
90
20
60
10
30
0
0
-10
1E+04
1E+05
1E+06
PHASE (°)
Figure 6-8. Forced Off Time vs Temperature
GAIN (dB)
Figure 6-7. VFB vs Temperature
-30
1E+07
FREQUENCY (Hz)
Figure 6-11. Frequency vs Temperature
Figure 6-12. Error Amplifier Gain and Phase
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7 Detailed Description
7.1 Overview
The LM5088 wide input range buck controller features all the functions necessary to implement an efficient high
voltage step-down converter using a minimum number of external components. The control method is based on
peak current mode control utilizing an emulated current ramp. Peak current mode control provides inherent line
voltage feedforward, cycle-by-cycle current limiting, and ease of loop compensation. The use of an emulated
control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing of very
small duty cycles necessary in high input voltage applications. The operating frequency is user programmable
from 50 kHz to 1 MHz. The LM5088-1 provides a ±5% frequency dithering function to reduce the conducted and
radiated EMI, while the LM5088-2 provides a versatile restart timer for overload protection. Additional features
include the low dropout bias regulator, tri-level enable input to control shutdown and standby modes, soft start,
and voltage tracking and oscillator synchronization capability. The device is available in a thermally enhanced
HTSSOP-16 pin package.
See Figure 7-1 and Figure 9-1. The LM5088 is well suited for a wide range of applications where efficient stepdown of high, unregulated input voltage is required. The typical applications for the LM5088 include telecom,
industrial, and automotive.
10
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7.2 Functional Block Diagram
LM5088
VIN
4.5 V-75 V
VIN
VCC
7.7 V
Regulator
C VCC
5V
1.2 V
RUV2
CIN
5 uA
STANDBY
THERMAL
SHUTDOWN
UVLO
EN
CFT
RUV1
BOOT
SHUTDOWN
UVLO DIS
C BOOT
0.4 V
11 uA
SS
5V
CSS
STANDBY
0.9 V
DRIVER
CLK
S
Q
R
Q
HG
Q
L
LEVEL
SHIFT
SW
PWM
1.205 V
C COMP
FB
CHF
MINIMUM
OFF- TIME
LOGIC
ERROR
AMP
I- LIMIT
FREQUENCY
DITHERING
A = -10
CS
COUT
Rs
CSG
CLK
DITHER
LM5088 -1 ONLY
DITHER
D
CLK
TRACK
SAMPLE
and
HOLD
VIN
+
COMP
CLK
1.2
R COMP
VOUT
CLK
RAMP GENERATOR
R FB2
GND
OSCILLATOR
Ir
R FB1
HICCUP RESTART
LM5088 - 2 ONLY
OUT
HICCUP
RESTART
LOGIC
RES
CRES/DITH
RT
RAMP
R RT
C RAMP
SYNC
CSYNC
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. LM5088 Functional Block Diagram
7.3 Feature Description
7.3.1 High Voltage Low-Dropout Regulator
The LM5088 contains a high voltage, low-dropout regulator that provides the VCC bias supply for the controller
and the bootstrap MOSFET gate driver. The input pin (VIN) can be connected directly to an input voltage as
high as 75 V. The output of the VCC regulator (7.8 V) is internally current limited to 30 mA. Upon power up,
the regulator sources current into the capacitor connected to the VCC pin. When the voltage at the VCC pin
exceeds the upper VCC UV threshold of 4 V and the EN pin is greater than 1.2 V, the output (HG) is enabled
and a soft-start sequence begins. The output is terminated if VCC falls below its lower UV threshold (3.8 V)
or the EN pin falls below 1.1 V. When VIN is less than VCC regulation point of 7.8 V, then the internal pass
device acts as a switch. Thereby, VCC tracks VIN with a voltage drop determined by the RDS(ON) of the internal
switch and operating current of the controller. The required VCC capacitor value is dependent on system start-up
characteristics with a minimum value no less than 0.1 µF.
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An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary
voltage is greater than 8.2 V, the internal regulator is disabled. The VCC regulator series pass transistor includes
a diode between VCC and VIN that must not be forward biased in normal operation.
In high voltage applications, take care to ensure that the VIN pin does not exceed the absolute maximum voltage
rating of 76 V. During line or load transients, voltage ringing on the VIN pin that exceeds the absolute maximum
ratings can damage the IC. Both careful PC board layout and the use of high quality bypass capacitors located
close to the VIN and GND pins are essential.
7.3.2 Line Undervoltage Detector
The LM5088 contains a dual-level undervoltage lockout (UVLO) circuit. When the EN pin is below 0.4 V, the
controller is in a low current shutdown mode. When the EN pin is greater than 0.4 V but less than 1.2 V, the
controller is in a standby mode. In standby mode, the VCC regulator is active, but the output switch is disabled
and the SS pin is held low. When the EN pin exceeds 1.2 V and VCC exceeds the VCC UV threshold, the SS pin
and the output switch is enabled and normal operation begins. An internal 5-µA pullup current source at the EN
pin configures the controller to be fully operational if the EN pin is left open.
An external VIN UVLO set-point voltage divider from VIN to GND can be used to set the minimum start-up
input voltage of the controller. The divider must be designed such that the voltage at the EN pin exceeds 1.2 V
(typical) when VIN is in the desired operating range. The internal 5-µA pullup current source must be included
in calculations of the external set-point divider. 100 mV of hysteresis is included for both shutdown and standby
thresholds. The EN pin is internally connected to a 1-kΩ resistor and an 8-V zener clamp. If the voltage at the
EN pin exceeds 8 V, the bias current for the EN pin increases at the rate of 1 mA/V. The voltage at the EN pin
should never exceed 14 V.
7.3.3 Oscillator and Sync Capability
The LM5088 oscillator frequency is set by a single external resistor connected between the RT pin and the GND
pin. The RT resistor must be located very close to the device. To set a desired oscillator frequency (fSW), the
necessary value of RT resistor can be calculated from the following equation:
RRT =
1
- 280 ns
fSW
152 pF
(1)
The RT pin can also be used to synchronize the internal oscillator to an external clock. The internal oscillator
is synchronized to an external clock by AC coupling a positive edge into the RT/SYNC pin. The RT/SYNC pin
voltage must exceed 3 V to trip the internal clock synchronization pulse detector. The free-running frequency
should be set nominally 15% below the external clock frequency and the pulse width applied to the RT/SYNC pin
must be less than 150 ns. Synchronization to an external clock more than twice the free-running frequency can
produce abnormal behavior of the pulse-width modulator.
12
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LM5088
5.0V
VIN
5 PA
RUV2
1.2V
STANDBY
EN
1 k:
RUV1
0.4V
8V
SHUTDOWN
Figure 7-2. Basic Enable Configuration
7.3.4 Error Amplifier and PWM Comparator
The internal high gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision voltage reference (1.205 V). The output of the error amplifier
is connected to the COMP pin, allowing the user to connect loop compensation components. Generally a type II
network, as illustrated in Figure 7-1, is sufficient. This network creates a pole at DC, a mid-band zero for phase
boost and a high frequency pole for noise reduction. The PWM comparator compares the emulated current
signal from the RAMP generator to the error amplifier output voltage at the COMP pin. A typical control loop gain
and phase plot is shown in Section 6.7.
7.3.5 Ramp Generator
The ramp signal used for the pulse width modulator in current mode control is typically derived directly from the
buck switch current. This signal corresponds to the positive slope portion of the buck inductor current. Using
this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides
inherent input voltage feedforward compensation. The disadvantage of using the buck switch current signal for
PWM control is the large leading edge spike due to circuit parasitics which must be filtered or blanked. Also,
the current measurement can introduce significant propagation delays. The filtering time, blanking time, and
propagation delay limit the minimum achievable pulse width. In applications where the input voltage can be
relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles are necessary
for regulation. The LM5088 utilizes a unique ramp generator, which does not actually measure the buck switch
current but rather reconstructs or emulates the signal. Emulating the inductor current provides a ramp signal that
is free of leading edge spikes and measurement or filtering delays. The current reconstruction is comprised of
two elements: a sample and hold DC level and an emulated current ramp.
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RAMP
(5 PA/V x (VIN ± VOUT) + 25 PA) x
TON
CRAMP
Sample and Hold
DC Level
10 x R S V/A
TON
Figure 7-3. Composition of Current Sense Signal
The sample and hold DC level illustrated in Figure 7-3 is derived from a measurement of the re-circulating (or
free-wheeling) diode current. The diode current flows through the current sense resistor connected between the
CS and CSG pins. The voltage across the sense resistor is sampled and held just prior to the onset of the
next conduction interval of the buck switch. The diode current sensing and sample and hold provide the DC
level for the reconstructed current signal. The positive slope inductor current ramp is emulated by an external
capacitor connected from the RAMP pin to GND and an internal voltage controlled current source. The ramp
current source that emulates the inductor current is a function of the VIN and VOUT voltages per the following
equation:
IRAMP = 5 µA/V × (VIN – VOUT) + 25 µA
(2)
Proper selection of the RAMP capacitor depends upon the selected value of the output inductor and the current
sense resistor (RS). For proper current emulation, the DC sample and hold value and the ramp amplitude must
have the same dependence on the load current. That is:
CRAMP =
gm x L
RS x A
(3)
where
•
•
gm is the ramp current generator transconductance (5 µA/V).
A is the gain of the current sense amplifier (10 V/V).
The RAMP capacitor must connected directly to the RAMP and GND pins of the IC.
14
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For duty cycles greater than 50%, peak current mode control circuits are subject to subharmonic oscillation.
Subharmonic oscillation is normally characterized by alternating wide and narrow pulses at the SW pin. Adding
a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 25-µA
offset current supplied by the emulated current source provides a fixed slope to the ramp signal. In some
high output voltage, high duty cycles applications, additional slope compensation can be required. In these
applications, a pullup resistor can be added between the RAMP and VCC pins to increase the ramp slope
compensation. A formula to configure pullup resistor is shown in Section 8.
7.3.6 Dropout Voltage Reduction
The LM5088 features unique circuitry to reduce the dropout voltage. Dropout voltage is defined as the
difference between the minimum input voltage to maintain regulation and the output voltage (VIN(min) – VOUT).
Dropout voltage thus determines the lowest input voltage at which the converter maintains regulation. In a
buck converter, dropout voltage primarily depends upon the maximum duty cycle. The maximum duty cycle is
dependent on the oscillator frequency and minimum off time.
An approximation for the dropout voltage is:
Dropout_Voltage = VOUT x
TOFF(max)
TOSC - TOFF(max)
(4)
where
•
•
•
•
TOSC = 1 / fSW.
TOFF (max) is the forced off time (280 ns typical, 365 ns maximum).
fSW is the oscillator frequency.
TOSC is the oscillator period.
From the above equation, it can be seen that for a given output voltage, reducing the dropout voltage requires
either reducing the forced off time or oscillator frequency (1/TOSC). The forced off time is limited by the time
required to replenish the bootstrap capacitor and time required to sample the re-circulating diode current. The
365-ns forced off time of the LM5088 controller is a good trade-off between these two requirements. Thus,
the LM5088 reduces dropout voltage by dynamically decreasing the operating frequency during dropout. The
dynamic frequency control (DFC) is achieved using a dropout monitor, which detects a dropout condition and
reduces the operating frequency. The operating frequency continues to decrease with decreasing input voltage
until the frequency falls to the minimum value set by the DFC circuitry.
fSW(minDFC) ≊ 1 / 3 × fSW(nominal)
(5)
If the VIN voltage continues to fall below this point, output regulation can no longer be maintained. The oscillator
frequency reverts back to the nominal operating frequency set by the RT resistor when the input voltage
increases above the dropout range. DFC circuitry does not affect the PWM during normal operating conditions.
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VIN
SNVS600J – DECEMBER 2008 – REVISED JUNE 2022
VOUT
Dropout
CLK
Regulation
Point
Forced
off-time
ON-TIME
Forced
off-time
TON(max)
Extended
TON(max)
TON(maxDFC)
increased to
reduce dropout
fSW(minDFC)
Normal Operation
Transition Region
Low Dropout Mode
Figure 7-4. Dropout Voltage Reduction using Dynamic Frequency Control
7.3.7 Frequency Dithering (LM5088-1 Only)
Electromagnetic interference (EMI) emissions are fundamentally associated with switch-mode power supplies
due to sharp voltage transitions, diode reverse recovery currents, and the ringing of parasitic L-C circuits. These
emissions conduct back to the power source or radiate into the environment and potentially interfere with nearby
electronic systems. System designers typically use a combination of shielding, filtering, and layout techniques to
reduce the EMI emissions sufficiently to satisfy EMI emission standards established by regulatory bodies. In a
typical fixed frequency switching converter, narrowband emissions typically peak at the switching frequency with
the successive harmonics having less energy. Dithering the oscillator frequency spreads the EMI energy over a
range of frequencies, thus reducing the peak levels. Dithering can also reduce the system cost by reducing the
size and quantity of EMI filtering components.
The LM5088-1 provides an optional frequency dithering function, which is enabled by connecting a capacitor
from the dither pin (DITH) to GND. Connecting the DITH pin directly to GND disables frequency dithering,
causing the oscillator to operate at the frequency established by the RT resistor. As shown in Figure 7-5, the
Cdither capacitor is used to generate a triangular wave centered at 1.2 V. This triangular waveform is used to
manipulate the oscillator circuit such that the oscillator frequency modulates from –5% to +5% of the nominal
operating frequency set by the RT resistor. The Cdither capacitor value sets the rate of the low frequency
modulation. For example, a lower value Cdither capacitor modulates the oscillator frequency from –5% to +5% at
a faster rate than a higher value capacitor. For the dither circuit to work effectively, the modulation rate must be
much less than the oscillator frequency (fSW), select Cdither such that:
Cdither t
16
100 x 25 PA
fSW x 0.12V
(6)
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+5V
LM5088
25 PA
1.14V
1.26V
+
-
1.20V
1.14V
R
Q
S
Q
DITHER
C dither
50 PA
1. 26V
+
-
Oscillator
Tosc - 't
Tosc
Tosc +'t
Figure 7-5. Frequency Dithering Scheme
Figure 7-6. Conducted Emissions Measured at the Input of a LM5088-Based Buck Converter
Figure 7-6 shows the conducted emissions on the LM5088 evaluation board input power line. It can be seen
from the above picture that the peak emissions with non-dithering operation are centered narrowly at the
operating frequency of the converter. With dithering operation, the conducted emissions are spread around the
operating frequency and the maximum amplitude is reduced by approximately 10 dB. Figure 7-6 was captured
using a Chroma DC power supply model number 62006P and an Agilent network analyzer model number
4395A.
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7.3.8 Cycle-by-Cycle Current Limit
The LM5088 contains a current limit feature that protects the circuit from extended overcurrent conditions. The
emulated current signal is directly proportional to the buck switch current and is applied to the current limit
comparator. If the emulated current exceeds 1.2 V, the PWM cycle is terminated. The peak inductor current
required to trigger the current limit comparator is given by:
1.2V - 25 PA x
IPEAK =
VOUT
VIN x fSW x CRAMP
A x RS
or
IPEAK #
0.12V
RS
(7)
where
•
•
•
•
•
A is 10 V/V is the current sense amplifier gain.
CRAMP is the ramp capacitor.
RS is the sense resistor.
VOUT
25 PA x
VIN x fSW x CRAMP
is the voltage ramp added for slope compensation .
1.2 V is the reference of the current limit comparator.
Since the current that charges the RAMP capacitor is proportional to VIN – VOUT, if the output is suddenly
shorted, the VOUT term is zero and the RAMP charging current increases. The increased RAMP charging current
immediately reduces the PWM duty cycle. The LM5088 also includes a buck switch protection scheme. A
dedicated comparator monitors the drain-to-source voltage of the buck FET when it is turned on, if the VDS
exceeds 1.5 V, the comparator turns off the buck FET immediately. This feature helps protect the buck FET in
catastrophic conditions, such as a sudden saturation of the inductor.
7.3.9 Overload Protection Timer (LM5088-2 Only)
To further protect the external circuitry during a prolonged over current condition, the LM5088-2 provides a
current limit timer to disable the switching regulator and provide a delay before restarting (hiccup mode). The
number of current limit events required to trigger the restart mode is programmed by an external capacitor at
the RES pin. During each PWM cycle, as shown in Figure 7-8, the LM5088 either sinks current from or sources
current into the RES capacitor. If the emulated current ramp exceeds the 1.2-V current limit threshold, the
present PWM cycle is terminated and the LM5088 sources 50 µA into the RES pin capacitor during the next
PWM clock cycle. If a current limit event is not detected in a given PWM cycle, the LM5088 disables the 50-µA
source current and sinks 27 µA from the RES pin capacitor during the next cycle. In an overload condition, the
LM5088 protects the converter with cycle-by-cycle current limiting until the voltage at RES pin reaches 1.2 V.
When RES reaches 1.2 V, a hiccup mode sequence is initiated as follows:
•
•
•
•
•
18
The SS capacitor is fully discharged.
The RES capacitor is discharged with 1.2 µA
Once the RES capacitor reaches 0.2 V, a normal soft-start sequence begins. This provides a time delay
before restart.
If the overload condition persists after restart, the cycle repeats.
If the overload condition no longer exists after restart, the RES pin is held at ground by the 27-µA discharge
current source and normal operation resumes.
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The overload protection timer is very versatile and can be configured for the following modes of protection:
1. Cycle-by-Cycle only: The hiccup mode can be completely disabled by connecting the RES pin to GND. In
this configuration, the cycle-by-cycle protection limits the output current indefinitely and no hiccup sequence
occurs.
2. Delayed Hiccup: Connecting a capacitor to the RES pin provides a programmed number of cycle-by-cycle
current limit events before initiating a hiccup mode restart, as previously described. The advantage of this
configuration is that a short term overload does not cause a hiccup mode restart but during extended
overload conditions, the average dissipation of the power converter is very low.
3. Externally Controlled Hiccup: The RES pin can also be used as an input. By externally driving the pin to a
level greater than the 1.2-V hiccup threshold, the controller is forced into the delayed restart sequence. For
example, the external trigger for a delayed restart sequence could come from an overtemperature protection
or an output overvoltage sensor.
LM5088
5.0V
Current
limit cycle
I- Limit
50 PA
Hiccup
current
source
logic
RES
C RES
Post-fault
Discharge
current
27 PA
1.2 PA
Non - current
limit cycle
Q
S
SS begins
Restart
Q
R
1.2V
+
-
HG OFF
SS = 0
+
CLK
0.2V
Figure 7-7. Current Limit Restart Circuit
Current Limit Persistent
Charge Restart cap
with 50 PA current
1.2V
Discharge Restart
cap with 1.2 PA
Current Limit Detected
at CS
0.2V
RES
0V
FB+120 mV
SS
11 PA
HG
t1
t2
Figure 7-8. Current Limit Restart Timing Diagram
7.3.10 Soft Start
The soft-start (SS) feature forces the output to rise linearly until it reaches the steady-state operating voltage
set by the feedback resistors. The LM5088 regulates the FB pin to the SS pin voltage or the internal 1.205-V
reference, whichever is lower. At the beginning of the soft-start sequence, VSS = 0 V and an internal 11-µA
current source gradually increases the voltage of the external soft-start capacitor (CSS). An internal amplifier
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clamps the SS pin voltage at 120 mV above the FB voltage. This feature provides soft start-controlled recovery
with reduced output overshoot in the event that the output voltage momentarily dips out of regulation.
7.3.11 HG Output
The LM5088 provides a high current, high-side driver and associated level shift circuit to drive an external Nchannel MOSFET. The gate driver works in conjunction with an internal diode and external bootstrap capacitor.
A ceramic bootstrap capacitor is recommended, and must be connected directly between the BOOT and SW
pins. During the off time of the buck switch, the bootstrap capacitor charges from VCC through an internal diode.
When operating with a high PWM duty cycle, the HG output is forced-off each cycle for 365 ns (maximum)
to make sure that BOOT capacitor is recharged. A pre-charge circuit, comprised of a MOSFET between SW
and GND, is turned ON during the forced off time to help replenish the BOOT capacitor. The pre-charge circuit
provides charge to the BOOT capacitor under light load or pre-biased load conditions when the SW voltage does
not remain low during the entire off time.
7.3.12 Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum
operating temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power
reset state, disabling the output driver and the bias supply of the controller. The feature prevents catastrophic
failures from accidental device over-heating.
7.4 Device Functional Modes
7.4.1 EN Pin Modes
If the EN pin voltage is below 0.4 V, the regulator is in a low power state. If the EN pin voltage is between 0.4 V
and 1.2 V, the controller is in standby mode. If the EN pin voltage is above 1.2 V, the controller is operational. An
external voltage divider can be used to set a line undervoltage shutdown threshold. If the EN pin is left open, a
5-μA pullup current forces the pin to the high state and enables the controller.
20
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LM5088 wide input range buck controller features all the functions necessary to implement an efficient
high-voltage step-down converter using a minimum number of external components. The LM5088 is well-suited
for a wide range of applications where efficient step-down of high, unregulated input voltage is required.
8.2 Typical Application
VIN (4.5 V-75 V)
RUV2
VIN
EN
BOOT
Q
RUV1
CIN
CBOOT
HG
DITH/RES
SW
VCC
CS
L
VOUT
CDITHER/RESTART
RFB2
D
COUT1
LM5088
RRAMP
CVCC
RAMP
CSG
SS
OUT
RT/SYNC
FB
RRT
RCOMP
GND
RFB1
Rs
CRAMP
CSS
COUT2
CCOMP
COMP
CHF
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. LM5088 Typical Application Schematic
8.2.1 Design Requirements
The procedure for calculating the external components is illustrated with the following design example. The
circuit shown in Figure 9-1 and Figure 9-2 is configured for the following specifications:
•
•
•
•
Output voltage = 5 V
Input voltage = 5.5 V to 36 V
Maximum load current = 7 A
Switching frequency = 250 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Timing Resistor
The RT resistor sets the oscillator switching frequency. Higher frequencies result in smaller size components
such as the inductor and filter capacitors. However, operating at higher frequencies also results in higher
MOSFET and diode switching losses. Operation at 250 kHz was selected for this example as a reasonable
compromise between size and efficiency.
The value of RT resistor can be calculated as follows:
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RRT =
1
- 280 ns
250 kHz
152 pF
= 24.5 k:
(8)
The nearest standard value of 24.9 kΩ was chosen for RT.
8.2.2.2 Output Inductor
The inductor value is determined based on the operating frequency, load current, ripple current, and the input
and output voltages.
Knowing the switching frequency (fSW), maximum ripple current (IPP), maximum input voltage (VIN(max)), and the
nominal output voltage (VOUT), the inductor value can be calculated as follows:
L=
VOUT
VOUT
x 1IPP x fSW
VIN(max)
(9)
I PP
IO
0
T = 1/FSW
Figure 8-2. Inductor Current
The maximum ripple current occurs at the maximum input voltage. Typically, IPP is selected between 20% and
40% of the full load current. Higher ripple current results in a smaller inductor. However, it places more burden
on the output capacitor to smooth out the ripple current to achieve low output ripple voltage. For this example,
40% ripple was chosen for a smaller sized inductor.
L=
5V
5V
x 1= 6.2 PH
0.4 x 7A x 250 kHz
55V
(10)
The nearest standard value of 6.8 µH is used. To prevent saturation, the inductor must be rated for the peak
current. During normal operation, the peak current occurs at maximum load current (plus maximum ripple). With
properly scaled component values, the peak current is limited to VCS(TH)/RSduring overload conditions. At the
22
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maximum input voltage with a shorted output, the chosen inductor must be evaluated at elevated temperature.
Note that the saturation current rating of inductors drops significantly at elevated temperatures.
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8.2.2.3 Current Sense Resistor
The current limit value (ILIM) is set by the current sense resistor (RS).
RS can be calculated by
VCS
RS =
(1 + margin) ´ (IOUT + 0.5 ´ IPP ) +
VOUT
L ´ fSW
0.12
=
(1 + 0.1) ´ (7 A + 0.5 ´ 2.8) +
5V
6.8 mH ´ 250 kHz
@ 10 mΩ
(11)
Some margin beyond the maximum load current is recommended for the current limit threshold. In this design
example, the current limit is set at 10% above the maximum load current, resulting in a RS value of 10 mΩ. The
CS and CSG pins must be Kelvin connected to the current sense resistor.
8.2.2.4 Ramp Capacitor
With the inductor and sense resistor value selected, the value of the ramp capacitor (CRAMP) necessary for the
emulation ramp circuit is given by:
CRAMP =
gm x L
A x RS
(12)
where
•
•
•
L is the value of the output inductor.
gm is the ramp generator transconductance (5 µA/V).
A is the current sense amplifier gain (10 V/V).
For the current design example, the ramp capacitor is calculated as:
CRAMP =
5 PA/V x 6.8 PH
10V/V x 10 m:
= 340 pF
(13)
The next lowest standard value, 270 pF, was selected for CRAMP. An NPO capacitor with 5% or better tolerance
is recommended. Note that selecting a capacitor value lower than the calculated value increases the slope
compensation. Furthermore, selecting a ramp capacitor substantially lower or higher than the calculated value
also results in incorrect PWM operation.
For VOUT > 5 V, internal slope compensation provided by the LM5088 may not be adequate for certain operating
conditions especially at low input voltages. A pullup resistor may be added from the VCC to RAMP pin to
increase the slope compensation. Optimal slope compensation current can be calculated from Equation 14.
IOS = VOUT × 5 µA/V
(14)
and RRAMP is given by Equation 15.
RRAMP =
24
VVCC - VRAMP
IOS - 25 PA
(15)
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VCC
R RAMP
RAMP
C RAMP
Figure 8-3. Additional Slope Compensation for VOUT > 5 V
8.2.2.5 Output Capacitors
The output capacitors smooth the inductor current ripple and provide a source of charge for load transient
conditions. The output capacitor selection is primarily dictated by the following specifications:
•
•
Steady-state output peak-peak ripple (ΔVPK-PK)
Output voltage deviation during transient condition (ΔVTransient)
For the 5-V output design example, ΔVPK-PK = 50 mV (1% of VOUT) and ΔTTransient = 100 mV (2% of VOUT) were
chosen. The magnitude of output ripple primarily depends on ESR of the capacitors while load transient voltage
deviation depends both on the output capacitance and ESR.
When a full load is suddenly removed from the output, the output capacitor must be large enough to prevent
the inductor energy to raise the output voltage above the specified maximum voltage. In other words, the output
capacitor must be large enough to absorb the maximum stored energy of the inductor. The stored energy
equations of both the inductor and the output capacitor can be calculated with:
L x IO +
CO =
2
'IPP
2
('V + VOUT)2 - VOUT2
(16)
Evaluating, the above equation with a ΔVOUT of 100 mV results in an output capacitance of 475 µF. As stated
earlier, the maximum peak-to-peak ripple primarily depends on the ESR of the output capacitor and the inductor
ripple current. To satisfy the ΔVPK-PK of 50 mV with 40% inductor current ripple, the ESR must be less than 15
mΩ. In this design example, a 470-µF aluminum capacitor with an ESR of 10 mΩ is paralleled with two 47-µF
ceramic capacitors to further reduce the ESR.
8.2.2.6 Input Capacitors
The input power supply typically has large source impedance at the switching frequency. Good quality input
capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current
during the on time. When the buck switch turns ON, the current into the external FET steps to the valley of the
inductor current waveform at turn-on, ramps up to the peak value, and then drops to zero at turn-off. The input
capacitors must be selected for RMS current rating and minimum ripple voltage. A good approximation for the
ripple current is IRMS > IOUT / 2.
Select quality ceramic capacitors with a low ESR for the input filter. To allow for capacitor tolerances and voltage
rating, five 2.2-µF, 100-V ceramic capacitors were selected. With ceramic capacitors, the input ripple voltage is
triangular and peaks at 50% duty cycle. Taking into account the capacitance change with DC bias, a worst case
input peak-to-peak ripple voltage can be approximated with Equation 17.
'VIN =
IOUT
4 x fSW x CIN
=
7A
= 636 mV
4 x 250 kHz x 11 PF
(17)
When the converter is connected to an input power source, a resonant circuit is formed by the line impedance
and the input capacitors. This can result in an overshoot at the VIN pin and can result in VIN exceeding
its absolute maximum rating. Because of those conditions, it is recommended that either an aluminum type
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capacitor with an ESR or increasing CIN > 10 × LIN. While using aluminum type capacitor, take care to not
exceed its maximum ripple current rating. Tantalum capacitors must be avoided at the input as they are prone to
shorting.
8.2.2.7 VCC Capacitor
The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended
value must be no smaller than 0.1 µF, and must be a good-quality, low-ESR, ceramic capacitor. A value of 1 µF
was selected for this design.
8.2.2.8 Bootstrap Capacitor
The bootstrap capacitor between HB and SW pins supplies the gate current to charge the high-side MOSFET
gate at the turn-on of each cycle as well as supplying the recovery charge for the bootstrap diode (D1).The peak
current can be several amperes. The recommended value of the bootstrap capacitor is at least 0.022 µF and
must be a good-quality, low-ESR, ceramic capacitor located close to the pins of the IC. The absolute minimum
value for the bootstrap capacitor is calculated as:
CHB t
Qg
'VHB
(18)
where
•
•
Qg is the high-side MOSFET gate charge.
ΔVHB is the tolerable voltage droop on CHB, which is typically less than 5% of the VCC.
.A value of 0.1 µF was selected for this design.
8.2.2.9 Soft-Start Capacitor
The capacitor at the SS capacitor determines the soft-start time, the output voltage to reach the final regulated
value. The value of CSS for a given time is determined from:
CSS =
tSS x 11 PA
1.205V
(19)
For this design example, a value of 0.022 µF was chosen for a soft-start time of approximately 2 ms.
8.2.2.10 Output Voltage Divider
RFB1 and RFB2 set the output voltage level. The ratio of these resistors can be calculated from:
RFB2
RFB1
=
VOUT
-1
1.205V
(20)
1.62 kΩ was chosen for RFB1 in this design, which results in a RFB2 value of 5.11 kΩ. A reasonable guide is to
select the value of RFB1 value such that the current through the resistor (1.2 V/ RFB1) is in between 1 mA and
100 µA.
26
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8.2.2.11 UVLO Divider
A voltage divider can be connected to the EN pin to the set the minimum start-up voltage (VIN(min)) of the
regulator. If this feature is required, set the value of RUV2 between 10 kΩ and 100 kΩ and then calculate RUV1
from:
RUV1 = 1.2V x
RUV2
(VIN(min) + (5 PA x RUV2) - 1.2V)
(21)
In this design, for a VIN(min) of 5 V, RUV2 was selected to be 54.9 kΩ, resulting in a RUV1 value of 16.2 kΩ. Install
a capacitor parallel to RUV1 for filtering. If the EN pin is left open, the LM5088 begins operation once the upper
VCC UV threshold of 4.0 V (typical) is reached.
8.2.2.12 Restart Capacitor (LM5008-2 Only)
The basic operation of hiccup mode current limit is described in Section 7.3.9. In the LM5088-2 application
example, the RES pin is configured for delayed hiccup mode. Please refer to Section 7.3.9 to configure this
pin in alternate configurations and also refer to Figure 7-8. The delay time to initiate a hiccup cycle (t1)
is programmed by the selection of RES pin capacitor. In the case of continuous cycle-by-cycle current limit
detection at the CS pin, the time required for CRES to reach the 1.2 V is given by:
Trestart_delay =
CRES x 1.2V
= CRES x 24k
50 PA
(22)
The cool down time (t2) is set by the time taken to discharge the RES cap with 1.2-µA current source. This
feature reduces the input power drawn by the converter during a prolonged overcurrent condition. In this
application, a 500-µs delay time was selected. The minimum value of CRES capacitor must be no less than 0.022
µF.
8.2.2.13 MOSFET Selection
Selection of the buck MOSFET is governed by the same trade-offs as the switching frequency. Losses in power
MOSFETs can be broken down into conduction losses and switching losses. The conduction loss is given by
Equation 23.
PDC = D × (IO 2 × RDS(ON) × 1.3)
(23)
where
•
•
D is the duty cycle.
IO is the maximum load current.
The factor 1.3 accounts for the increase in MOSFET on-resistance due to heating. Alternatively, for a more
precise calculation, the factor of 1.3 can be ignored and the on-resistance of the MOSFET can be estimated
using the RDS(ON) vs Temperature curves in the MOSFET data sheet.
The switching loss occurs during the brief transition period as the MOSFET turns on and off. During the
transition period both current and voltage are present in the MOSFET. The switching loss can be approximated
as:
PSW = 0.5 × VIN × IO × (tR + tF) × fSW
(24)
where
•
•
tRis the rise time of the MOSFET.
tF is the fall time of the MOSFET.
The rise and fall times are usually mentioned in the MOSFET data sheet or can be empirically observed on the
scope. There is another loss, which is associated with the buck MOSFET is the gate-charging loss. This loss
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differs from the above two losses in the sense that it is dissipated in the LM5088 and not in the MOSFET itself.
Gate charging loss, PGC, results from the drive current charging the gate capacitance of the power MOSFET and
is approximated as:
PGC = VCC × Qg × fSW
(25)
For this example with the maximum input voltage of 55 V, the VDS breakdown rating of the selected MOSFET
must be greater than 55 V, plus any ringing across drain to source due to parasitics. In order to minimize
switching time and gate drive losses, the selected MOSFET must also have low gate charge (Qg). A good choice
of MOSFET for this design example is the SI7148DP which has a total gate charge of 30 nC and rise and fall
times of 10 ns and 12 ns, respectively.
8.2.2.14 Diode Selection
A Schottky type re-circulating diode is required for all LM5088 applications. The near ideal reverse recovery
current transients and low forward voltage drop are particularly important diode characteristics for high input
voltage and low output voltage applications common to LM5088. The diode switching loss is minimized in a
Schottky diode because of near ideal reverse recovery. The conduction loss can be approximated by:
Pdc_diode = (1 – D) × IO × VF
(26)
where
•
VF is the forward drop of the diode.
The worst case is to assume a short circuit load condition. In this case, the diode carries the output current
almost continuously. The reverse breakdown rating must be selected for the maximum input voltage level,
plus some additional safety margin to withstand ringing at the SW node. For this application, a 60-V On
Semiconductor Schottky diode (MBRB2060) with a specified forward drop of 0.6 V at 7 A at a junction
temperature of 50°C was selected. For output loads of 5 A and greater and high input voltage applications,
a diode in a D2PAK package is recommended to support the worst case power dissipation.
8.2.2.15 Snubber Components Selection
Excessive ringing and spikes can cause erratic operation and couple spikes and noise to the output. Voltage
spikes beyond the rating of the LM5088 or the re-circulating diode can damage these devices. A snubber
network across the power diode reduces ringing and spikes at the switching node. Selecting the values for the
snubber is best accomplished through empirical methods. First, make sure that the lead lengths for the snubber
connections are very short. For the current levels typical for the LM5088, a resistor value between 3 Ω and 10 Ω
must be adequate. As a rule of thumb, a snubber capacitor, which is four to five times the junction temperature
of the Schottky diode reduce spikes adequately. Increasing the value of the snubber capacitor results in more
damping but also results in higher losses. The power dissipation of the resistor is independent of the resistance
value as the resistor dissipates the energy stored by the snubber capacitor. The power dissipation of the resistor
can be approximated as:
PR_SNUB = CSNUB × VIN(max) 2 × fSW
28
(27)
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8.2.2.16 Error Amplifier Compensation
RCOMP, CCOMP, and CHF configure the error amplifier gain characteristics to accomplish a stable voltage loop
gain. One advantage of current mode control is the ability to close the loop with only two feedback components,
RCOMP and CCOMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For
this example, the modulator can be treated as an ideal voltage-to-current (transconductance) converter. The DC
modulator gain of the LM5088 can be modeled as:
DC Gain(MOD) = RLOAD / (A × RS)
The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD) and the output
capacitance (COUT). The corner frequency of this pole is:
If RLOAD = 5 V/7 A = 0.714 Ω and COUT = 500 µF (effective), then FP(MOD) = 550 Hz.
(28)
DC Gain(MOD) = 0.714 / (10 × 10 mΩ) = 7.14 = 17 dB
(29)
For the 5-V design example, the modulator gain versus frequency characteristic was measured as shown in
Figure 8-4.
60
200
160
40
80
20
40
0
0
-40
-20
PHASE (°)
GAIN (dB)
120
-80
-120
-40
-160
-60
-200
1.E+01
1.E+02
1.E+03
1.E+04 1.E+05
FREQUENCY (Hz)
Figure 8-4. Modular Gain Phase
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Components RCOMP and CCOMP configure the error amplifier as a type II compensation configuration. The DC
gain of the amplifier is 80 dB, which has a pole at low frequency and a zero at fZero = 1 / (2π × RCOMP × CCOMP).
The error amplifier zero is set such that it cancels the modulator pole leaving a single pole response at the
crossover frequency of the voltage loop. A single pole response at the crossover frequency yields a very stable
loop with 90° of phase margin. For the design example, a target loop bandwidth (crossover frequency) of 15
kHz was selected. The compensation network zero (fZero) must be at least an order of magnitude lower than
the target crossover frequency. This constrains the product of RCOMP and CCOMP for a desired compensation
network zero 1/ (2π × RCOMP × CCOMP) to be less than 1.5 kHz. Increasing RCOMP, while proportionally
decreasing CCOMP, decreases the error amp gain. For the design example, CCOMP was selected to be 0.015
µF and RCOMP was selected to be 18 kΩ. These values configure the compensation network zero at 0.6 kHz.
The error amp gain at frequencies greater than fZero is RCOMP / RFB2, which is approximately 3.56 (11dB).
60
200
160
40
120
GAIN (dB)
40
0
0
-40
-20
-80
-120
-40
-60
1.E+02
PHASE (o)
80
20
-160
1.E+03
1.E+04
1.E+05
-200
1.E+06
FREQUENCY (Hz)
Figure 8-5. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp
gain. If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can
be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier
compensation components can be designed with the suggested guidelines. Step load transient tests can be
performed to verify performance. The step load goal is minimum overshoot with a damped response. CHF can be
added to the compensation network to decrease noise susceptibility of the error amplifier. The value of CHF must
be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer function. A good
approximation of the location of the pole added by CHF is fP2 = fZero × CCOMP / CHF.Using CHF is recommended
to minimize coupling of any switching noise into the modulator. The value of CHF was selected as 100 pF for this
design example.
60
200
160
40
120
GAIN (dB)
40
0
0
-40
-20
PHASE (°)
80
20
-80
-120
-40
-160
-60
1.E+02
1.E+03
1.E+04
-200
1.E+05
FREQUENCY (Hz)
Figure 8-6. Overall Loop Gain and Phase
30
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8.2.3 Application Curves
See Figure 8-4 through Figure 8-6 for Typical Application Curves.
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9 Power Supply Recommendations
9.1 Thermal Considerations
In a buck converter, most of the losses can be attributed to MOSFET conduction and switching loss, recirculating diode conduction loss, inductor DCR loss, and LM5088 VIN and VCC loss. The other dissipative
components in a buck converter produce losses, but these other losses collectively account for about 2% of the
total loss. Formulas to calculate all the major losses are described in their respective sections of this data sheet.
The easiest method to determine the power dissipated within the LM5088 is to measure the total conversion
losses (PIN – POUT), then subtract the power losses in the Schottky diode, MOSFET, output inductor, and
snubber resistor. When operating at 7 A of output current and at 55 V, the power dissipation of the LM5088 is
approximately 850 mW. The junction-to-ambient thermal resistance of the LM5088 mounted in the evaluation
board is approximately 40°C with no airflow. At 25°C ambient temperature and no airflow, the predicted junction
temperature is 25 + 40 × 0.9 = 61°C. The LM5088 has an exposed thermal pad to aid in power dissipation.
Adding several vias under the device greatly reduces the controller junction temperature. The junction to ambient
thermal resistance varies with application. The most significant variables are the area of copper in the PC board:
the number of vias under the IC exposed pad and the amount of forced air cooling. The integrity of solder
connection from the IC exposed pad to the PC board is critical. Excessive voids greatly diminish the thermal
dissipation capacity.
Figure 9-1. LM5088-1 Application Schematic
32
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Figure 9-2. LM5088-2 Application Schematic
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10 Layout
10.1 Layout Guidelines
In a buck regulator, there are two loops where currents are switched very fast. The first loop starts from the
input capacitors, through the buck MOSFET, to the inductor then out to the load. The second loop starts from the
output capacitor ground, to the regulator PGND pins, to the current sense resistor, through the Schottky diode,
to the inductor and then out to the load. Minimizing the area of these two loops reduces the stray inductance
and minimizes noise, which can cause erratic operation. A ground plane is recommended as a means to connect
the input filter capacitors of the output filter capacitors and the PGND pin of the regulator. Connect all of the low
power ground connections (CSS, RT, and CRAMP) directly to the regulator GND pin. Connect the GND pin and
PGND pins together through to top-side copper area covering the entire underside of the device. Place several
vias in this underside copper area to the ground plane. The input capacitor ground connection must be as close
as possible to the current sense ground connection.
10.2 Layout Example
D
Inductor
Q
RS
VOUT
CIN
COUT
COUT
GND
CIN
Controller
VIN
GND
Figure 10-1. LM5088 Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5088MH-1/NOPB
ACTIVE
HTSSOP
PWP
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5088
MH-1
LM5088MH-2/NOPB
ACTIVE
HTSSOP
PWP
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5088
MH-2
LM5088MHX-1/NOPB
ACTIVE
HTSSOP
PWP
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5088
MH-1
LM5088MHX-2/NOPB
ACTIVE
HTSSOP
PWP
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5088
MH-2
LM5088QMH-1/NOPB
ACTIVE
HTSSOP
PWP
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5088
QMH-1
LM5088QMH-2/NOPB
ACTIVE
HTSSOP
PWP
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5088
QMH-2
LM5088QMHX-1/NOPB
ACTIVE
HTSSOP
PWP
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5088
QMH-1
LM5088QMHX-2/NOPB
ACTIVE
HTSSOP
PWP
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5088
QMH-2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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