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LM5102SD

LM5102SD

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    WDFN10

  • 描述:

    IC GATE DRVR HALF-BRIDGE 10WSON

  • 数据手册
  • 价格&库存
LM5102SD 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM5102 SNVS268B – MAY 2004 – REVISED DECEMBER 2014 LM5102 High-Voltage Half-Bridge Gate Driver With Programmable Delay 1 Features 3 Description • The LM5102 high-voltage gate driver is designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of working with supply voltages up to 100 V. The outputs are independently controlled. The rising edge of each output can be independently delayed with a programming resistor. An integrated high voltage diode is provided to charge the high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from control logic to the high side gate driver. Undervoltage lockout is provided on both the low side and the high side power rails. This device is available in the standard VSSOP 10 pin and the WSON 10 pin packages. 1 • • • • • • • Drives Both a High-Side and Low-Side N-Channel MOSFET Independently Programmable High and Low Side Rising Edge Delay Bootstrap Supply Voltage Range up to 118 V dc Fast Turn-Off Propagation Delay (25 ns Typical) Drives 1000-pF Loads with 15-ns Rise and Fall Times Supply Rail Undervoltage Lockout Low Power Consumption Timer Can Be Terminated Midway Through Sequence 2 Applications • • • • • Device Information(1) Current Fed Push-Pull Power Converters Half and Full Bridge Power Converters Synchronous Buck Converters Two Switch Forward Power Converters Forward with Active Clamp Converters PART NUMBER LM5102 PACKAGE BODY SIZE (NOM) VSSOP (10) 3.00 mm × 3.00 mm WSON (10) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram HB HV HO UVLO LEVEL SHIFT DRIVER HS HI Adjustable rising edge delay RT1 VDD UVLO LO DRIVER LI Adjustable rising edge delay RT2 VSS 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5102 SNVS268B – MAY 2004 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application ................................................. 11 9 Power Supply Recommendations...................... 13 9.1 Power Dissipation Considerations .......................... 13 10 Layout................................................................... 14 10.1 Layout Guidelines ................................................. 14 10.2 Layout Example .................................................... 15 11 Device and Documentation Support ................. 15 Detailed Description ............................................ 10 11.1 Trademarks ........................................................... 15 11.2 Electrostatic Discharge Caution ............................ 15 11.3 Glossary ................................................................ 15 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 12 Mechanical, Packaging, and Orderable Information ........................................................... 15 4 Revision History Changes from Revision A (March 2013) to Revision B • Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1 Changes from Original (March 2013) to Revision A • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 11 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 LM5102 www.ti.com SNVS268B – MAY 2004 – REVISED DECEMBER 2014 5 Pin Configuration and Functions 10 Pin VSSOP (DGS), WSON (DPR) Top View VDD 1 10 HB 2 9 VSS HO 3 8 LI HS 4 7 HI RT1 5 6 RT2 LO Pin Functions PIN NAME WSON (2), VSSOP TYPE (1) DESCRIPTION APPLICATION INFORMATION HB 2 P High-side gate driver bootstrap rail Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal of bootstrap capacitor to HS. The Bootstrap capacitor should be placed as close to IC as possible. HI 7 I High-side driver control input TTL compatible thresholds. Unused inputs should be tied to ground and not left open. HO 3 O High-side gate driver output Connect to gate of high-side MOSFET with short low-inductance path. HS 4 P High-side MOSFET source connection Connect bootstrap capacitor negative terminal and source of high side MOSFET. LI 8 I Low-side driver control input TTL compatible thresholds. Unused inputs should be tied to ground and not left open. LO 10 O Low-side gate driver output Connect to the gate of the low side MOSFET with a short low inductance path. RT1 5 A High-side output edge delay programming Resistor from RT1 to ground programs the leading edge delay of the high side gate driver. The resistor should be placed close to the IC to minimize noise coupling from adjacent traces. RT2 6 A Low-side output edge delay programming Resistor from RT2 to ground programs the leading edge delay of the low side gate driver. The resistor should be placed close to the IC to minimize noise coupling from adjacent traces. VDD 1 P Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor, located as close to IC as possible. VSS 9 G Ground return All signals are referenced to this ground. (1) (2) P = Power, G = Ground, I = Input, O = Output, A = Analog For the WSON package, it is recommended that the exposed pad on the bottom of the LM5100 and LM5101 be soldered to ground plane on the PC board, and the ground plane should extend out from beneath the IC to help dissipate the heat. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 3 LM5102 SNVS268B – MAY 2004 – REVISED DECEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT VDD to VSS –0.3 18 V VHB to VHS –0.3 18 V LI or HI Inputs to VSS –0.3 VDD + 0.3 V LO Output –0.3 VDD + 0.3 V HO Output VHS – 0.3 VHB + 0.3 V VHS to VSS –1 100 V 118 V VHB to VSS RT1 and RT2 to VSS –0.3 Junction Temperature Storage Temperature Range (1) (2) –55 5 V 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 6.2 ESD Ratings V(ESD) (1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Electrostatic discharge VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN MAX 9 14 V V VDD HS –1 100 HB VHS + 8 VHS + 14 HS Slew Rate Junction Temperature –40 UNIT V < 50 V/ns 125 °C 6.4 Thermal Information LM5102 THERMAL METRIC (1) DGS DPR (2) 10 PINS 10 PINS RθJA Junction-to-ambient thermal resistance 165.3 37.9 RθJC(top) Junction-to-case (top) thermal resistance 58.9 38.1 RθJB Junction-to-board thermal resistance 54.4 14.9 ψJT Junction-to-top characterization parameter 6.2 0.4 ψJB Junction-to-board characterization parameter 83.6 15.2 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 4.4 (1) (2) 4 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). 4 layer board with Cu finished thickness 1.5 oz, 1 oz, 1 oz, 1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50 mm ground and power planes embedded in PCB. See Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401). Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 LM5102 www.ti.com SNVS268B – MAY 2004 – REVISED DECEMBER 2014 6.5 Electrical Characteristics Specifications in standard typeface are for TJ = +25°C. Unless otherwise specified, VDD = VHB = 12 V, VSS = VHS = 0V, RT1 = RT2 = 100 kΩ. No load on LO or HO. PARAMETER TEST CONDITIONS MIN (1) TYP MAX (1) UNIT SUPPLY CURRENTS LI = HI = 0 V IDD VDD Quiescent Current IDDO VDD Operating Current IHB Total HB Quiescent Current IHBO Total HB Operating Current IHBS HB to VSS Current, Quiescent VHS = VHB = 100 V, –40°C to +125°C IHBSO HB to VSS Current, Operating f = 500 kHz 0.4 LI = HI = 0 V, –40°C to +125°C 0.6 f = 500 kHz 1.5 f = 500 kHz, –40°C to +125°C 3 LI = HI = 0 V 0.06 LI = HI = 0 V, –40°C to +125°C 0.2 f = 500 kHz 1.3 f = 500 kHz, –40°C to +125°C 3 VHS = VHB = 100 V mA mA mA mA 0.05 10 0.08 µA mA INPUT PINS VIL Low Level Input Voltage Threshold VIH High Level Input Voltage Threshold RI Input Pulldown Resistance 1.8 –40°C to +125°C V 0.8 1.8 –40°C to +125°C 2.2 200 –40°C to +125°C 100 500 V kΩ TIME DELAY CONTROLS 3 VRT Nominal Voltage at RT1, RT2 IRT RT Pin Current Limit Vth Timer Termination Threshold 1.8 TDL1, TDH1 Rising edge turn-on delay, RT = 10 kΩ 105 –40°C to +125°C 75 TDL2, TDH2 Rising edge turn-on delay, RT = 100 kΩ –40°C to +125°C 530 –40°C to +125°C 2.7 RT1 = RT2 = 0 V RT1 = RT2 = 0 V, –40°C to +125°C 3.3 1.5 0.75 2.25 V mA V 150 630 750 ns ns UNDER VOLTAGE PROTECTION VDDR VDD Rising Threshold VDDH VDD Threshold Hysteresis VHBR HB Rising Threshold VHBH HB Threshold Hysteresis 6.9 –40°C to +125°C 6.0 7.4 0.5 V 6.6 –40°C to +125°C 5.7 V 7.1 0.4 V V BOOTSTRAP DIODE VDL Low-Current Forward Voltage VDH High-Current Forward Voltage (1) IVDD-HB = 100 µA 0.60 IVDD-HB = 100 µA, –40°C to +125°C IVDD-HB = 100 mA IVDD-HB = 100 mA, –40°C to +125°C 0.9 0.85 1.1 V V MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 5 LM5102 SNVS268B – MAY 2004 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) Specifications in standard typeface are for TJ = +25°C. Unless otherwise specified, VDD = VHB = 12 V, VSS = VHS = 0V, RT1 = RT2 = 100 kΩ. No load on LO or HO. PARAMETER RD Dynamic Resistance TEST CONDITIONS MIN (1) MAX (1) TYP IVDD-HB = 100 mA UNIT 0.8 IVDD-HB = 100 mA, –40°C to +125°C Ω 1.5 LO GATE DRIVER ILO = 100 mA 0.25 VOLL Low-Level Output Voltage VOHL High-Level Output Voltage ILO = –100 mA, VOHL = VDD – VLO, –40°C to +125°C IOHL Peak Pullup Current VLO = 0 V 1.6 A IOLL Peak Pulldown Current VLO = 12 V 1.8 A ILO = 100 mA, –40°C to +125°C V 0.4 ILO = –100 mA, VOHL = VDD – VLO 0.35 V 0.55 HO GATE DRIVER IHO = 100 mA 0.25 VOLH Low-Level Output Voltage VOHH High-Level Output Voltage IHO = –100 mA, VOHH = VHB – VHO, –40°C to +125°C IOHH Peak Pullup Current VHO = 0 V 1.6 A IOLH Peak Pulldown Current VHO = 12 V 1.8 A IHO = 100 mA, –40°C to +125°C V 0.4 IHO = –100 mA, VOHH = VHB – VHO 0.35 V 0.55 6.6 Switching Characteristics Specifications in standard typeface are for TJ = +25°C. Unless otherwise specified, VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO. PARAMETER TEST CONDITIONS MIN (1) TYP MAX (1) UNIT tLPHL Lower Turn-Off Propagation Delay LM5102 (LI Falling to LO Falling) –40°C to +125°C 27 tHPHL Upper Turn-Off Propagation Delay LM5102 (HI Falling to HO Falling) –40°C to +125°C 27 tRC, tFC Either Output Rise/Fall Time CL = 1000 pF 15 ns tR, tF Either Output Rise/Fall Time (3 V to 9 V) CL = 0.1 µF 0.6 µs tBS Bootstrap Diode Turn-Off Time IF = 20 mA, IR = 200 mA 50 ns (1) 6 56 56 ns ns MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 LM5102 www.ti.com SNVS268B – MAY 2004 – REVISED DECEMBER 2014 6.7 Typical Characteristics 2.2 100 VDD = 12V RT = 10k CL = 2200 pF CURRENT (mA) CL = 1000 pF CURRENT (mA) IDDO 2.0 CL = 470 pF 10 1.8 1.6 1.4 1.2 1.0 CL = 0 pF 1 10 1 100 IHBO 0.8 -50 -25 1000 0 25 50 75 100 125 150 FREQUENCY (kHz) TEMPERATURE (°C) Figure 1. IDD vs Frequency Figure 2. Operating Current vs Temperature 1.20 1.20 IDD, RT = 10k IDD, RT = 10k 1.00 0.80 CURRENT (mA) CURRENT (mA) 1.00 0.60 IDD, RT = 100k 0.40 0.20 0.00 9 0.60 IDD, RT = 100k 0.40 0.20 IHB, RT = 10k, 100k 8 0.80 IHB, RT = 10k, 100k 0.00 -50 10 11 12 13 14 15 16 17 18 -25 0 VDD, VHB (V) Figure 3. Quiescent Current vs Supply Voltage 2.00 VDD = VHB = 12V, HS = 0V 1.60 1.40 CURRENT (A) CURRENT (PA) 75 100 125 150 1.80 CL = 4400 pF CL = 2200 pF 10000 50 Figure 4. Quiescent Current vs Temperature 100000 HB = 12V, HS = 0V 25 TEMPERATURE (°C) CL = 1000 pF 1000 SOURCING 1.00 0.80 SINKING 0.60 100 0.40 CL = 0 pF 10 0.1 1.20 0.20 CL = 470 pF 0.00 1 10 100 1000 0 2 4 6 8 10 12 FREQUENCY (kHz) HO, LO (V) Figure 5. IHB vs Frequency Figure 6. HO and LO Peak Output Current vs Output Voltage Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 7 LM5102 SNVS268B – MAY 2004 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) 0.60 1.00E-01 T = 150°C 0.55 1.00E-02 VDDH HYSTERESIS (V) T = 25°C ID (A) 1.00E-03 1.00E-04 0.50 0.45 VHBH 0.40 T = -40°C 1.00E-05 0.35 1.00E-06 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.30 -50 0.9 -25 VD (V) 0 25 50 75 100 125 150 o TEMPERATURE ( C) Figure 8. Undervoltage Threshold Hysteresis vs Temperature Figure 7. Diode Forward Voltage 0.700 7.30 7.20 0.600 VDD = VHB = 8V 7.00 0.500 VDDR 6.90 VOH (V) THRESHOLD (V) 7.10 6.80 6.70 VHBR 6.60 VDD = VHB = 12V 0.400 0.300 VDD = VHB = 16V 6.50 0.200 6.40 6.30 -50 -25 0 25 50 0.100 -50 -25 75 100 125 150 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Undervoltage Rising Threshold vs Temperature Figure 10. LO and HO Gate Drive — High Level Output Voltage vs Temperature 0.400 40.0 38.0 0.350 36.0 VDD = VHB = 8V 34.0 DELAY (ns) VOL (V) 0.300 VDD = VHB = 12V 0.250 0.200 TLPHL 32.0 30.0 28.0 26.0 VDD = VHB = 16V THPHL 24.0 0.150 22.0 0.100 -50 -25 0 25 50 20.0 -50 -25 75 100 125 150 TEMPERATURE (°C) Figure 11. LO and HO Gate Drive — Low Level Output Voltage vs Temperature 8 0 25 50 75 100 125 150 TEMPERATURE (°C) Figure 12. Turn Off Propagation Delay vs Temperature Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 LM5102 www.ti.com SNVS268B – MAY 2004 – REVISED DECEMBER 2014 Typical Characteristics (continued) 700 145 VCC = 12V 600 135 125 HI to HO Delay DELAY (ns) DELAY (ns) 500 400 300 LI to LO Delay 115 105 200 95 100 85 75 0 0 10 20 30 40 50 60 70 80 90 100 -50 RT (k:) -25 0 25 50 75 100 125 150 TEMPERATURE (oC) Figure 13. Turn On Delay vs RT Resistor Value Figure 14. Turn On Delay vs Temperature (RT = 10 k) 750 725 DELAY (ns) 700 675 650 LI to LO Delay 625 600 HI to HO Delay 575 550 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (oC) Figure 15. Turn On Delay vs Temperature (RT = 100 k) Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 9 LM5102 SNVS268B – MAY 2004 – REVISED DECEMBER 2014 www.ti.com 7 Detailed Description 7.1 Overview The LM5102 device offers a unique flexibility with independently programmable delay of the rising edge for both high and low side driver outputs independently. The delays are set with resistors at the RT1 and RT2 pins, and can be adjusted from 100 ns to 600 ns. This feature reduces component count, board space and cost compared to discrete solutions for adjusting driver dead time. The wide delay programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETs and applications. The RT pins are biased at 3 V and current limited to 1 mA maximum programming current. The time delay generator will accommodate resistor values from 5 k to 100 k with turn-on delay times that are proportional to the RT resistance. In addition, each RT pin is monitored by a comparator that will bypass the turn-on delay if the RT pin is pulled below the timer elimination threshold (1.8 V typical). Grounding the RT pins programs the LM5102 to drive both outputs with minimum turn-on delay. 7.2 Functional Block Diagram HB HV HO UVLO LEVEL SHIFT DRIVER HS HI Adjustable rising edge delay RT1 VDD UVLO LO DRIVER LI Adjustable rising edge delay RT2 VSS 7.3 Feature Description 7.3.1 Startup and UVLO Both top and bottom drivers include undervoltage lockout (UVLO) protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB – VHS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn-on the external MOSFETs, and the built-in hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to VDD pin of LM5102, the top and bottom gates are held low until VDD exceeds UVLO threshold, typically about 6.9 V. Any UVLO condition on the bootstrap capacitor will disable only the high side output (HO). 7.4 Device Functional Modes LI Pin 10 LO Pin HI Pin HO Pin L L L L H H H H Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 LM5102 www.ti.com SNVS268B – MAY 2004 – REVISED DECEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM5102 is one of the latest generation of high voltage gate drivers which are designed to drive both the high-side and low-side N-Channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit. The floating high side driver is capable of operating with supply voltages up to 100 V. This allows for NChannel MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies. In the LM5102 the outputs are independently controlled. The rising edge of each output can be independently delayed with a programming resistor. Table 1. LM5102 Highlights FEATURE BENEFIT Independently programmable high and low side delay Allows optimisation of gate drive timings to account for device differences between high-side and low-side positions Low power consumption Improves light load efficiency figures Internal bootstrap diode Reduces parts count and PCB real estate 8.2 Typical Application (Optional external fast recovery diode) VIN VCC RGATE HB VDD HO VDD CBOOT PWM CONTROLLER OUT1 HI OUT2 LI 0.1 PF HS T1 LM5102 LO RT1 0.47 PF GND RT2 VSS Figure 16. LM5102 Driving MOSFETS Connected in Half-Bridge Configuration Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 11 LM5102 SNVS268B – MAY 2004 – REVISED DECEMBER 2014 www.ti.com Typical Application (continued) 8.2.1 Design Requirements PARAMETERS VALUES Gate Drive IC LM5102 Mosfet CSD18531Q5A VDD 10 V Qgmax 43 nC Fsw 100 kHz DMax 95% IHBO 10 µA VDH 1.1 V VHBR 7.1 V VHBH 0.4 V 8.2.2 Detailed Design Procedure ΔVHB = VDD – VDH – VHBL where • • • CBOOT = VDD = Supply voltage of the gate drive IC VDH = Bootstrap diode forward voltage drop Vgsmin = Minimum gate source threshold voltage (1) QTOTAL DVHB (2) QTOTAL = Qgmax + IHBO ´ DMax FSW (3) The quiescent current of the bootstrap circuit is 10 µA which is negligible compared to the Qgs of the mosfet. 0.95 QTOTAL = 43nC + 10mA ´ 100kHz (4) QTOTAL = 43.01 nC (5) In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where the power stage may skip pulse due to load transients. In this circumstance the boot capacitor must maintain the HB Pin voltage above the UVLO Voltage for the HB circuit. As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT. VHBL = VHBR – VHBH VHBL = 6.7 V ΔVHB = 10 V – 1.1 V – 6.7 V ΔVHB = 2.2 V CBOOT = (6) (7) (8) (9) 43.01nc 2.2V (10) (11) CBOOT = 19.54 nF The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be twice that of the maximum VDD to allow for loss of capacitance once the devices have a dc bias voltage across them and to ensure long term reliability of the devices. The resistor values, RT1 and RT2, for setting turn on delay can be found in Figure 18. 12 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 LM5102 www.ti.com SNVS268B – MAY 2004 – REVISED DECEMBER 2014 8.2.3 Application Curves 145 LI 135 125 DELAY (ns) HI LO TDL = tP + tRT2 TDL 115 105 95 tP 85 HO 75 tP -50 TDH TDH = tP + tRT1 -25 0 25 50 75 100 125 150 TEMPERATURE (oC) Figure 17. Application Timing Waveforms Figure 18. Turn On Delay vs Temperature (RT = 10 k) 9 Power Supply Recommendations 9.1 Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as shown in Equation 12. PDGATES = 2 × f × CL × VDD2 (12) There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equation. This plot can be used to approximate the power losses due to the gate drivers. 1.000 CL = 4400 pF CL = 2200 pF POWER (W) 0.100 CL = 1000 pF 0.010 CL = 470 pF CL = 0 pF 0.001 0.1 1.0 10.0 100.0 1000.0 SWITCHING FREQUENCY (kHz) Figure 19. Gate Driver Power Dissipation (LO + HO) VCC = 12 V, Neglecting Diode Losses The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. Figure 20 was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 13 LM5102 SNVS268B – MAY 2004 – REVISED DECEMBER 2014 www.ti.com Power Dissipation Considerations (continued) 1.000 1.000 CL = 4400 pF 0.100 POWER (W) POWER (W) CL = 4400 pF CL = 0 pF 0.010 0.001 1.0 kHz 0.100 CL = 0 pF 0.010 10.0 kHz 100.0 kHz 0.001 1.0 kHz 1000.0 kHz SWITCHING FREQUENCY (kHz) 10.0 kHz 100.0 kHz 1000.0 kHz SWITCHING FREQUENCY (kHz) Figure 20. Diode Power Dissipation VIN = 80 V Figure 21. Diode Power Dissipation VIN = 40 V The total IC power dissipation can be estimated from the above plots by summing the gate drive losses with the bootstrap diode losses for the intended application. Because the diode losses can be significant, an external diode placed in parallel with the internal bootstrap diode (refer to Figure 16) and can be helpful in removing power from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series inductance and have a significantly lower forward voltage drop than the internal diode. 10 Layout 10.1 Layout Guidelines The optimum performance of high and low side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. A low ESR/ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding considerations: – The first priority in designing grounding connections is to confine the high peak currents from charging and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. – The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. 5. The resistors on the RT1 and RT2 timer pins must be placed very close to the IC and seperated from high current paths to avoid noise coupling to the time delay generator which could disrupt timer operation. 14 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 LM5102 www.ti.com SNVS268B – MAY 2004 – REVISED DECEMBER 2014 10.2 Layout Example CBOOT Q HS C VDD LM5102 Q LS Figure 22. LM5102 Component Placement 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated Product Folder Links: LM5102 15 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM5102MM/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5102 LM5102MMX/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5102 LM5102SD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5102SD LM5102SDX/NOPB ACTIVE WSON DPR 10 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5102SD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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