LM5106
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SNVS424C – JANUARY 2006 – REVISED MARCH 2012
LM5106 100V Half Bridge Gate Driver with Programmable Dead-Time
Check for Samples: LM5106
FEATURES
PACKAGE
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2
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Drives Both a High Side and Low Side NChannel MOSFET
1.8A Peak Output Sink Current
1.2A Peak Output Source Current
Bootstrap Supply Voltage Range up to 118V
DC
Single TTL Compatible Input
Programmable Turn-On Delays (Dead-Time)
Enable Input Pin
Fast Turn-Off Propagation Delays (32ns
Typical)
Drives 1000pF with 15ns Rise and 10ns Fall
Time
Supply Rail Under-Voltage Lockout
Low Power Consumption
DESCRIPTION
The LM5106 is a high voltage gate driver designed to
drive both the high side and low side N-Channel
MOSFETs in a synchronous buck or half bridge
configuration. The floating high side driver is capable
of working with rail voltages up to 100V. The single
control input is compatible with TTL signal levels and
a single external resistor programs the switching
transition dead-time through tightly matched turn-on
delay circuits. The robust level shift technology
operates at high speed while consuming low power
and provides clean output transitions. Under-voltage
lockout disables the gate driver when either the low
side or the bootstrapped high side supply voltage is
below the operating threshold. The LM5106 is offered
in the VSSOP-10 or thermally enhanced 10-pin
WSON plastic package.
APPLICATIONS
•
•
•
WSON-10 (4 mm x 4 mm)
VSSOP-10
Solid State Motor Drives
Half and Full Bridge Power Converters
Two Switch Forward Power Converters
Simplified Block Diagram
VDD
HB
VDD
HB
UVLO
LEVEL
SHIFT
DRIVER
HO
HS
VDD
UVLO
IN
VSS
LEADING
EDGE
DELAY
RDT
LEADING
EDGE
DELAY
EN
VDD
DRIVER
LO
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2012, Texas Instruments Incorporated
LM5106
SNVS424C – JANUARY 2006 – REVISED MARCH 2012
www.ti.com
Connection Diagram
VDD
1
10
HB
2
9
VSS
HO
3
8
IN
HS
4
7
EN
NC
5
6
RDT
LO
Figure 1. 10-Lead VSSOP or WSON
See DGS or DPR0010A Package
PIN DESCRIPTIONS
Pin #
Name
1
VDD
2
Description
Application Information
Positive gate drive supply
Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close to
the IC as possible.
HD
High side gate driver
bootstrap rail
Connect the positive terminal of bootstrap capacitor to the HB pin and
connect negative terminal to HS. The Bootstrap capacitor should be placed
as close to IC as possible.
3
HO
High side gate driver output
Connect to the gate of high side N-MOS device through a short, low
inductance path.
4
HS
High side MOSFET source
connection
Connect to the negative terminal of the bootststrap capacitor and to the
source of the high side N-MOS device.
5
NC
Not Connected
6
RDT
7
Dead-time programming pin
A resistor from RDT to VSS programs the turn-on delay of both the high and
low side MOSFETs. The resistor should be placed close to the IC to minimize
noise coupling from adjacent PC board traces.
EN
Logic input for driver
Disable/Enable
TTL compatible threshold with hysteresis. LO and HO are held in the low
state when EN is low.
8
IN
Logic input for gate driver
TTL compatible threshold with hysteresis. The high side MOSFET is turned
on and the low side MOSFET turned off when IN is high.
9
VSS
Ground return
All signals are referenced to this ground.
10
LO
Low side gate driver output
Connect to the gate of the low side N-MOS device with a short, low
inductance path.
NA
EP
Exposed Pad
The exposed pad has no electrical contact. Connect to system ground plane
for reduced thermal resistance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2)
VDD to VSS
–0.3V to +18V
HB to HS
–0.3V to +18V
IN and EN to VSS
–0.3V to VDD + 0.3V
LO to VSS
–0.3V to VDD + 0.3V
HO to VSS
HS – 0.3V to HB + 0.3V
HS to VSS (3)
−5V to +100V
HB to VSS
118V
RDT to VSS
–0.3V to 5V
Junction Temperature
+150°C
Storage Temperature Range
–55°C to +150°C
ESD Rating HBM (4)
(1)
1.5 kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD
= 10V, the negative transients at HS must not exceed -5V.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 2, Pin 3 and Pin 4 are rated at
500V.
(2)
(3)
(4)
Recommended Operating Conditions
VDD
HS
+8V to +14V
(1)
–1V to 100V
HB
HS + 8V to HS + 14V
HS Slew Rate
< 50V/ns
Junction Temperature
(1)
–40°C to +125°C
In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD
= 10V, the negative transients at HS must not exceed -5V.
Electrical Characteristics
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, EN = 5V. No load on LO or HO. RDT=
100kΩ (1).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
IN = EN = 0V
0.34
0.6
mA
IDDO
VDD Operating Current
f = 500 kHz
2.1
3.5
mA
IHB
Total HB Quiescent Current
IN = EN = 0V
0.06
0.2
mA
IHBO
Total HB Operating Current
f = 500 kHz
1.5
3
mA
IHBS
HB to VSS Current, Quiescent
HS = HB = 100V
0.1
10
µA
IHBSO
HB to VSS Current, Operating
f = 500 kHz
0.5
mA
0.8
1.8
V
1.8
2.2
V
100
200
500
kΩ
INPUT IN and EN
VIL
Low Level Input Voltage Threshold
VIH
High Level Input Voltage Threshold
Rpd
Input Pulldown Resistance Pin IN and EN
(1)
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics (continued)
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, EN = 5V. No load on LO or HO. RDT=
100kΩ(1).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
2.7
3
3.3
V
0.75
1.5
2.25
mA
6.2
6.9
7.6
V
DEAD-TIME CONTROLS
VRDT
Nominal Voltage at RDT
IRDT
RDT Pin Current Limit
RDT = 0V
UNDER VOLTAGE PROTECTION
VDDR
VDD Rising Threshold
VDDH
VDD Threshold Hysteresis
VHBR
HB Rising Threshold
VHBH
HB Threshold Hysteresis
0.5
5.9
6.6
V
7.3
0.4
V
V
LO GATE DRIVER
VOLL
Low-Level Output Voltage
ILO = 100 mA
0.21
0.4
V
VOHL
High-Level Output Voltage
ILO = –100 mA,
VOHL = VDD – VLO
0.5
0.85
V
IOHL
Peak Pullup Current
LO = 0V
1.2
A
IOLL
Peak Pulldown Current
LO = 12V
1.8
A
HO GATE DRIVER
VOLH
Low-Level Output Voltage
IHO = 100 mA
0.21
0.4
V
VOHH
High-Level Output Voltage
IHO = –100 mA,
VOHH = HB – HO
0.5
0.85
V
IOHH
Peak Pullup Current
HO = 0V
1.2
A
IOLH
Peak Pulldown Current
HO = 12V
1.8
A
See (2) (3)
40
°C/W
THERMAL RESISTANCE
θJA
(2)
(3)
Junction to Ambient
4 layer board with Cu finished thickness 1.5/1.0/1.0/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See Application Note AN-1187.
The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
Switching Characteristics
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, No Load on LO or HO (1).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLPHL
Lower Turn-Off Propagation Delay
32
56
ns
tHPHL
Upper Turn-Off Propagation Delay
32
56
ns
tLPLH
Lower Turn-On Propagation Delay
RDT = 100k
400
520
640
ns
tHPLH
Upper Turn-On Propagation Delay
RDT = 100k
450
570
690
ns
tLPLH
Lower Turn-On Propagation Delay
RDT = 10k
85
115
160
ns
tHPLH
Upper Turn-On Propagation Delay
RDT = 10k
85
115
160
ns
ten, tsd
Enable and Shutdown propagation delay
DT1, DT2
Dead-time LO OFF to HO ON & HO OFF to
LO ON
MDT
36
ns
RDT = 100k
510
ns
RDT = 10k
86
ns
Dead-time matching
RDT = 100k
50
ns
tR
Either Output Rise Time
CL = 1000pF
15
ns
tF
Either Output Fall Time
CL = 1000pF
10
ns
(1)
4
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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Typical Performance Characteristics
VDD Operating Current vs Frequency
Operating Current vs Temperature
100
2.2
VDD = HB = 12V
CL = 2200 pF
VSS = HS = 0V
RDT = 10K
f = 500 kHz
2.0
VSS = HS = 0
CURRENT (mA)
CL = 1000 pF
CURRENT (mA)
VDD = HB = 12V
CL = 470 pF
10
1.8
CL = 0 pF
IDDO
1.6
1.4
IHBO
1.2
CL = 0 pF
1
10
1
100
1.0
-50 -30 -10 10 30 50 70 90 110 130 150
1000
TEMPERATURE (oC)
FREQUENCY (kHz)
Figure 2.
Figure 3.
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
1.20
1.20
1.00
1.00
IDD @ RDT = 10k
CURRENT (mA)
VDD = HB
VSS = HS = 0V
0.60
IDD @ RDT = 100k
0.40
0.20
0.00
9
VDD = HB = 12V
VSS = HS = 0V
0.60
IDD @ RDT = 100k
0.40
0.20
IHB @ RDT = 10k, 100k
8
0.80
0.00
-50
10 11 12 13 14 15 16 17 18
IHB @ RDT = 10k, 100k
-25
VDD, VHB (V)
25
50
75 100 125 150
Figure 4.
Figure 5.
HB Operating Current vs Frequency
HO & LO Peak Output Current
vs Output Voltage
100000
VDD = HB = 12V, HS = 0V
1.26
CL = 4400 pF
SOURCE CURRENT (A)
CL = 2200 pF
10000
CL = 1000 pF
1000
100
CL = 0 pF
10
0.1
2.00
1.40
HB = 12V,
HS = 0V
CURRENT (PA)
0
TEMPERATURE (°C)
1.80
1.12
1.60
0.98
1.40
1.20
0.84
SOURCING
0.70
0.42
0.60
SINKING
0.28
0.40
0.14
0.20
CL = 470 pF
0.00
1
10
100
1.00
0.80
0.56
1000
0
2
4
6
8
10
SINK CURRENT (A)
CURRENT (mA)
IDD @ RDT = 10k
0.80
0.00
12
HO, LO (V)
FREQUENCY (kHz)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Undervoltage Rising Threshold
vs Temperature
Undervoltage Hysteresis
vs Temperature
0.60
7.30
VDDR = VDD - VSS
7.20
VDDH
7.00
VDDR
HYSTERESIS (V)
THRESHOLD (V)
0.55
VHBR = HB - HS
7.10
6.90
6.80
6.70
VHBR
6.60
6.50
0.50
0.45
VHBH
0.40
0.35
6.40
6.30
-50 -25
0
25
50
0.30
-50
75 100 125 150
-25
0
25
Figure 9.
LO & HO - Low Level Output Voltage
vs Temperature
LO & HO - High Level Output Voltage vs Temperature
1.300
Output Current = 100 mA
Output Current - 100 mA
0.350
1.100
VDD = HB = 8V
VDD = HB = 8V
0.300
0.900
VOH (V)
VDD = HB = 12V
0.250
0.200
VDD = HB = 12V
0.700
0.500
VDD = HB = 16V
VDD = HB = 16V
0.150
0.100
-50
0.300
-25
0
25
50
0.100
-50 -25
75 100 125 150
TEMPERATURE (°C)
0
25
50
75 100 125 150
TEMPERATURE (°C)
Figure 10.
Figure 11.
Input Threshold vs Temperature
Dead-Time vs RT Resistor Value
1.96
900
1.94
800
1.92
700
DEAD-TIME (ns)
1.90
VIL, VIH (V)
100 125 150
Figure 8.
0.400
1.88
1.86
1.84
1.82
600
500
400
300
1.80
200
1.78
100
1.76
-50 -30 -10 10 30 50 70 90 110 130 150
0
10
30
50
70
90
110
130 150
RDT (k:)
TEMPERATURE (oC)
Figure 12.
6
75
TEMPERATURE (oC)
TEMPERATURE (°C)
VOL (V)
50
Figure 13.
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Typical Performance Characteristics (continued)
Dead-Time vs Temperature (RT = 10k)
Dead-Time vs Temperature (RT = 100k)
600
88
VDD = HB = 12V
VSS = HS = 0
84
VSS = HS = 0V
DEAD-TIME (ns)
DEAD-TIME (ns)
VDD = HB = 12V
590
86
82
80
580
570
560
78
550
76
-50 -30 -10 10 30 50 70 90 110 130 150
540
-50 -30 -10 10 30 50 70 90 110 130 150
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 14.
Figure 15.
Timing Diagrams
IN
EN
LO
ten
tLPHL
tHPHL
tHPLH
tLPLH
DT1
DT2
DT1
DT2
tsd
ten
HO
tsd
Figure 16. LM5106 Input - Output Waveforms
IN
VIH
VIL
tLPHL
tLPLH
90%
LO
10%
90%
tHPLH
HO
tHPHL
10%
Figure 17. LM5106 Switching Time Definitions: tLPLH, tLPHL, tHPLH, tHPHL
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90%
HO
VIH
EN
10%
DT1
DT2
90%
MDT = |DT1-DT2|
LO or HO
tsd
90%
Figure 18. LM5106 Enable: tsd
LO
10%
Figure 19. LM5106 Dead-time: DT
Operational Notes
The LM5106 is a single PWM input Gate Driver with Enable that offers a programmable dead-time. The deadtime is set with a resistor at the RDT pin and can be adjusted from 100ns to 600ns. The wide dead-time
programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETS and
applications.
The RDT pin is biased at 3V and current limited to 1 mA maximum programming current. The time delay
generator will accommodate resistor values from 5k to 100k with a dead-time time that is proportional to the RDT
resistance. Grounding the RDT pin programs the LM5106 to drive both outputs with minimum dead-time.
STARTUP AND UVLO
Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply
voltage (VDD) and bootstrap capacitor voltage (HB – HS) independently. The UVLO circuit inhibits each driver
until sufficient supply voltage is available to turn-on the external MOSFETs, and the UVLO hysteresis prevents
chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of the LM5106, the
top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.9V. Any UVLO
condition on the bootstrap capacitor will disable only the high side output (HO).
LAYOUT CONSIDERATIONS
The optimum performance of high and low side gate drivers cannot be achieved without taking due
considerations during circuit board layout. The following points are emphasized:
1. Low ESR / ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB
and HS pins to support high peak currents being drawn from VDD and HB during the turn-on of the external
MOSFETs.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between
the source of the top MOSFET and the drain of the bottom MOSFET (synchronous rectifier) must be
minimized.
4. Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close
as possible to the MOSFETs.
– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
5. The resistor on the RDT pin must be placed very close to the IC and separated from the high current paths
to avoid noise coupling to the time delay generator which could disrupt timer operation.
8
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POWER DISSIPATION CONSIDERATIONS
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply
voltage (VDD) and can be roughly calculated as:
PDGATES = 2 • f • CL • VDD2
(1)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equation. This plot can be used to
approximate the power losses due to the gate drivers.
1.000
CL = 4400 pF
CL = 2200 pF
POWER (W)
0.100
CL = 1000 pF
0.010
CL = 470 pF
CL = 0 pF
0.001
0.1
1.0
10.0
100.0
1000.0
SWITCHING FREQUENCY (kHz)
Figure 20. Gate Driver Power Dissipation (LO + HO)
VCC = 12V
HS TRANSIENT VOLTAGES BELOW GROUND
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS
node can swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling HO more than -0.3V below HS can activate
parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must
be placed as close to the IC pins as possible in order to be effective.
2. HB to HS operating voltage should be 15V or less. Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. Low ESR bypass capacitors from HB to HS and from VCC to VSS are essential for proper operation. The
capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO
and HO can be quite large. Any inductances in series with the bypass capacitor will cause voltage ringing at
the leads of the IC which must be avoided for reliable operation.
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VIN
VCC
RGATE
HB
VDD
VDD
HO
CBOOT
OUT1
IN
ENABLE
EN
CONTROLLER
0.1 PF
HS
LO
0.47 PF
GND
T1
LM5106
RDT
RGATE
VSS
Figure 21. LM5106 Driving MOSFETs Connected in Half-Bridge Configuration
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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23-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LM5106MM
ACTIVE
VSSOP
DGS
10
1000
TBD
Call TI
Call TI
-40 to 125
5106
LM5106MM/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5106
LM5106MMX
ACTIVE
VSSOP
DGS
10
TBD
Call TI
Call TI
-40 to 125
5106
LM5106MMX/NOPB
ACTIVE
VSSOP
DGS
10
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5106
LM5106SD
ACTIVE
WSON
DPR
10
TBD
Call TI
Call TI
-40 to 125
L5106SD
LM5106SD/NOPB
ACTIVE
WSON
DPR
10
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
L5106SD
LM5106SDX
ACTIVE
WSON
DPR
10
TBD
Call TI
Call TI
-40 to 125
L5106SD
LM5106SDX/NOPB
ACTIVE
WSON
DPR
10
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
L5106SD
3500
1000
4500
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Sep-2013
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM5106MM
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5106MM/NOPB
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5106MMX/NOPB
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5106SD/NOPB
WSON
DPR
10
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5106SDX/NOPB
WSON
DPR
10
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5106MM
VSSOP
DGS
10
1000
210.0
185.0
35.0
LM5106MM/NOPB
VSSOP
DGS
10
1000
210.0
185.0
35.0
LM5106MMX/NOPB
VSSOP
DGS
10
3500
367.0
367.0
35.0
LM5106SD/NOPB
WSON
DPR
10
1000
210.0
185.0
35.0
LM5106SDX/NOPB
WSON
DPR
10
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DPR0010A
SDC10A (Rev A)
www.ti.com
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