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LM5107
SNVS333F – NOVEMBER 2004 – REVISED SEPTEMBER 2016
LM5107 100V / 1.4-A Peak Half Bridge Gate Driver
1 Features
3 Description
•
The LM5107 is a low cost high voltage gate driver,
designed to drive both the high side and the low side
N-Channel MOSFETs in a synchronous buck or a
half bridge configuration. The floating high-side driver
is capable of working with rail voltages up to 100-V.
The outputs are independently controlled with TTL
compatible input thresholds. An integrated on chip
high voltage diode is provided to charge the high side
gate drive bootstrap capacitor. A robust level shifter
technology operates at high speed while consuming
low power and providing clean level transitions from
the control input logic to the high side gate driver.
Undervoltage lockout is provided on both the low side
and the high side power rails. The device is available
in the SOIC and the thermally enhanced WSON
packages.
1
•
•
•
•
•
•
•
•
•
•
•
Drives Both a High Side and Low Side N-Channel
MOSFET
High Peak Output Current (1.4-A Sink / 1.3-A
Source)
Independent TTL Compatible Inputs
Integrated Bootstrap Diode
Bootstrap Supply Voltage to 118 V DC
Fast Propagation Times (27-ns Typical)
Drives 1000 pF Load With 15-ns Rise and Fall
Times
Excellent Propagation Delay Matching (2-ns
Typical)
Supply Rail Undervoltage Lockout
Low Power Consumption
Pin Compatible With ISL6700
Packages:
– SOIC
– WSON (4 mm x 4 mm)
2 Applications
•
•
•
•
Device Information(1)
PART NUMBER
LM5107
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
WSON (8)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Block Diagram
Current Fed Push-Pull Converters
Half and Full Bridge Power Converters
Solid State Motor Drives
Two Switch Forward Power Converters
HV
HB
UVLO
LEVEL
SHIFT
DRIVER
HO
HS
HI
VDD
UVLO
DRIVER
LO
LI
VSS
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5107
SNVS333F – NOVEMBER 2004 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics ..........................................
Typical Performance Characteristics ........................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2016) to Revision F
Page
•
Changed Thermal Information table ....................................................................................................................................... 4
•
Added Overview and Device Functional Modes in Detailed Description section ................................................................. 10
•
Deleted HS Transient Voltages Below Ground from Application Information section.......................................................... 12
•
Added Typical Application section. ...................................................................................................................................... 12
•
Added Power Supply Recommendations section. .............................................................................................................. 16
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 18
Changes from Revision D (March 2013) to Revision E
•
Added Device Information table, ESD Ratings, Pin Configuration and Functions section, Detailed Description
section, Application and Implementation section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision C (March 2013) to Revision D
•
2
Page
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 12
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SNVS333F – NOVEMBER 2004 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
D and NGT Packages
8-Pin SOIC, WSON
Top View
VDD
1
8
HB
HI
2
7
HO
LI
3
6
HS
VSS
4
5
LO
Pin Functions
PIN
NO.
DESCRIPTIONunder
NAME
APPLICATION INFORMATION
SOIC
WSON (1)
1
1
VDD
Positive gate drive supply
Locally decouple to VSS using low ESR/ESL capacitor located as
close to IC as possible.
2
2
HI
High side control input
The LM5107 HI input is compatible with TTL input thresholds.
Unused HI input should be tied to ground and not left open
3
3
LI
Low side control input
The LM5107 LI input is compatible with TTL input thresholds. Unused
LI input should be tied to ground and not left open.
4
4
VSS
Ground reference
All signals are referenced to this ground.
5
5
LO
Low side gate driver output
Connect to the gate of the low side N-MOS device.
6
6
HS
High side source connection
Connect to the negative terminal of the bootstrap capacitor and to the
source of the high side N-MOS device.
7
7
HO
High side gate driver output
Connect to the gate of the low side N-MOS device.
8
8
HB
High side gate driver positive
supply rail
Connect the positive terminal of the bootstrap capacitor to HB and
the negative terminal of the bootstrap capacitor to HS. The bootstrap
capacitor should be placed as close to IC as possible.
(1)
For WSON package it is recommended that the exposed pad on the bottom of the LM5107 be soldered to ground plane on the PCB
board and the ground plane should extend out from underneath the package to improve heat dissipation.
6 Specifications
6.1 Absolute Maximum Ratings
See
(1) (2)
MIN
MAX
UNIT
VDD to VSS
-0.3
18
V
HB to HS
-0.3
18
V
LI or HI to VSS
-0.3
VDD +0.3
V
LO to VSS
-0.3
VDD +0.3
V
HO to VSS
VHS − 0.3
VHB + 0.3
V
−5
100
V
HS to VSS
(3)
HB to VSS
118
V
TJ
Junction Temperature
-40
150
°C
Tstg
Storage Temperature Range
−55
150
°C
(1)
(2)
(3)
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics .
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD
= 10V, the negative transients at HS must not exceed -5V.
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SNVS333F – NOVEMBER 2004 – REVISED SEPTEMBER 2016
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6.2 ESD Ratings
V(ESD)
(1)
Human-body model (HBM) (1)
Electrostatic discharge
VALUE
UNIT
±2000
V
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 6 , Pin 7 and Pin 8 are rated at
500V.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
HS
(1)
HB
MAX
UNIT
14
V
−1
V to 100
V
VHS + 8
VHS + 14
HS Slew Rate
< 50
Junction Temperature
−40
(1)
NOM
8
V
V/ns
125
°C
In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD
= 10V, the negative transients at HS must not exceed -5V.
6.4 Thermal Information
LM5107
THERMAL METRIC (1)
(2)
D (SOIC)
NGT (WSON)
UNIT
8 PINS
8 PINS
109.6
38.9 (3)
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
51.7
37.5
°C/W
RθJB
Junction-to-board thermal resistance
50.4
15.9
°C/W
ψJT
Junction-to-top characterization parameter
8.1
0.4
°C/W
ψJB
Junction-to-board characterization parameter
49.8
16.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
5
°C/W
(1)
(2)
(3)
4
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report.
The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See AN-1187 Leadless Leadframe Package (LLP) (SNOA401).
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6.5 Electrical Characteristics
Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Typical limits are for TJ = +25°C, and
minimum and maximum limits apply over the operating junction temperature range (–40°C to +125°C).
PARAMETER
TEST CONDITIONS
MIN (1)
MAX (1)
TYP
UNIT
SUPPLY CURRENTS
IDD
VDD Quiescent Current
LI = HI = 0V
0.3
0.6
mA
IDDO
VDD Operating Current
f = 500 kHz
2.1
3.4
mA
IHB
Total HB Quiescent Current
LI = HI = 0V
0.06
0.2
mA
IHBO
Total HB Operating Current
f = 500 kHz
1.6
3
mA
IHBS
HB to VSS Current, Quiescent
VHS = VHB = 100V
0.1
10
IHBSO
HB to VSS Current, Operating
f = 500 kHz
0.5
µA
mA
INPUT PINS LI and HI
VIL
Low Level Input Voltage Threshold
VIH
High Level Input Voltage Threshold
RI
Input Pulldown Resistance
0.8
1.8
V
1.8
2.2
V
100
180
500
kΩ
6
6.9
7.4
V
UNDER VOLTAGE PROTECTION
VDDR
VDD Rising Threshold
VDDH
VDD Threshold Hysteresis
VHBR
HB Rising Threshold
VHBH
HB Threshold Hysteresis
VDDR = VDD - VSS
0.5
VHBR = VHB - VHS
5.7
6.6
V
7.1
0.4
V
V
BOOT STRAP DIODE
VDL
Low-Current Forward Voltage
IVDD-HB = 100 µA
VDL = VDD - VHB
0.58
0.9
V
VDH
High-Current Forward Voltage
IVDD-HB = 100 mA
VDH = VDD - VHB
0.82
1.1
V
RD
Dynamic Resistance
IVDD-HB = 100 mA
0.8
1.5
Ω
LO GATE DRIVER
VOLL
Low-Level Output Voltage
ILO = 100 mA
VOHL = VLO – VSS
0.28
0.45
V
VOHL
High-Level Output Voltage
ILO = −100 mA,
VOHL = VDD– VLO
0.45
0.75
V
IOHL
Peak Pullup Current
VLO = 0V
1.3
A
IOLL
Peak Pulldown Current
VLO = 12V
1.4
A
HO GATE DRIVER
VOLH
Low-Level Output Voltage
IHO = 100 mA
VOLH = VHO– VHS
0.28
0.45
V
VOHH
High-Level Output Voltage
IHO = −100 mA
VOHH = VHB– VHO
0.45
0.75
V
IOHH
Peak Pullup Current
VHO = 0V
1.3
A
IOLH
Peak Pulldown Current
VHO = 12V
1.4
A
(1)
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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6.6 Switching Characteristics
Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Typical limits are for TJ = +25°C, and
minimum and maximum limits apply over the operating junction temperature range (–40°C to +125°C).
Parameter
CONDITIONS
MIN (1)
MAX (1)
TYP
UNIT
tLPHL
Lower Turn-Off Propagation Delay
(LI Falling to LO Falling)
27
56
ns
tHPHL
Upper Turn-Off Propagation Delay
(HI Falling to HO Falling)
27
56
ns
tLPLH
Lower Turn-On Propagation Delay
(LI Rising to LO Rising)
29
56
ns
tHPLH
Upper Turn-On Propagation Delay
(HI Rising to HO Rising)
29
56
ns
tMON
Delay Matching: Lower Turn-On and Upper
Turn-Off
2
15
ns
tMOFF
Delay Matching: Lower Turn-Off and Upper
Turn-On
2
15
ns
tRC, tFC
Either Output Rise/Fall Time
15
–
ns
tPW
Minimum Input Pulse Width that Changes
the Output
tBS
Bootstrap Diode Turn-Off Time
(1)
CL = 1000 pF
IF = 100 mA, IR = 100 mA
50
ns
105
ns
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
LI
LI
HI
tHPLH
tLPLH
HI
tHPHL
tLPHL
LO
LO
HO
HO
tMON
tMOFF
Figure 1. Timing Diagram
6
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6.7 Typical Performance Characteristics
100
100
VDD = VHB = 12V
VDD = VHB = 12V
VSS = VHS = 0V
VSS = VHS = 0V
10
10
IDDO (mA)
CL = 2200 pF
IDDO (mA)
CL = 1000 pF
CL = 1000 pF
CL = 4400 pF
CL = 2200 pF
CL = 4400 pF
1
1
CL = 0 pF
0.1
CL = 0 pF
CL = 470 pF
CL = 470 pF
0.1
0.01
1
10
100
1000
1
10
FREQUENCY (kHz)
100
1000
FREQUENCY (kHz)
Figure 2. VDD Operating Current vs Frequency
Figure 3. HB Operating Current vs Frequency
0.45
2.4
0.40
IDDO
0.35
CL = 0 pF
f = 500 kHz
2.0
IDD, IHB (mA)
IDDO, IHBO (mA)
2.2
VDD = VHB = 12V
1.8
VSS = VHS = 0V
1.6
IHBO
IDDO
0.30
0.25 LI = HI = 0V
VDD = VHB = 12V
0.20
VSS = VHS = 0V
0.15
0.10
1.4
IHBO
0.05
0.00
-40 -25 -10 5 20 35 50 65 80 95 110 125
1.2
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 5. Quiescent Current vs Temperature
Figure 4. Operating Current vs Temperature
600
44
CL = 0 pF
VDD = VHB
VDD = VHB = 12V
CURRENT (PA)
VSS= VHS = 0V
IDD
400
300
200
IHB
100
40
PROPAGATION DELAY (ns)
500
LI = HI = 0V
VSS = VHS = 0V
36
turn off
32
tHPLH
28
24
0
8
10
12
14
16
tLPHL
tHPHL
tLPLH
turn on
20
-40 -25 -10 5 20 35 50 65 80 95 110 125
18
VDD, VHB (V)
TEMPERATURE (oC)
Figure 6. Quiescent Current vs Voltage
Figure 7. Propagation Delay vs Temperature
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Typical Performance Characteristics (continued)
0.5
0.9
Output Current : -100 mA
VSS = VHS = 0V
Output Current : -100 mA
0.8
VSS = VHS = 0V
0.4
0.7
VDD = VHB = 8V
0.6
VOL (V)
VOH (V)
VDD = VHB = 8V
0.5
0.3
VDD = VHB = 12V
0.4
VDD = VHB = 12V
0.3
0.2
VDD = VHB =16V
VDD = VHB =16V
0.2
0.1
-40 -25 -10 5 20 35 50 65 80 95 110 125
0.1
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 8. LO and HO High Level Output Voltage vs
Temperature
Figure 9. LO and HO Low Level Output Voltage vs
Temperature
1.6
1.00E-01
VDD = VHB = 12V
VSS = VHS = 0V
25°C
1
1.00E-03
0.8
Pull-up Current
-40°C
1.00E-04
0.6
0.4
1.00E-05
0.2
Pull-down Current
0
0
2
4
6
8
10
12
1.00E-06
0.2
VLO, VHO (V)
6.9
0.5
0.6
0.7
0.8
0.9
0.50
VDDR = VDD - VSS
0.48
VHBR = VHB - VHS
0.46
6.8
6.7
0.4
Figure 11. Doide Forward Voltage
HYSTERESIS (V)
7.0
0.3
FORWARD VOLTAGE
Figure 10. HO and LO Peak Output Current vs Output
Voltage
THRESHOLD (V)
150°C
1.00E-02
1.2
ID (A)
OUTPUT CURRENTS (A)
1.4
VDDR
VHBR
6.6
0.44
VDDH
0.42
0.40
0.38
VHBH
0.36
6.5
0.34
6.4
0.32
0.30
-40 -25 -10 5 20 35 50 65 80 95 110 125
6.3
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 12. Undervoltage Rising Thresholds vs Temperature
8
Figure 13. Undervoltage Hysteresis vs Temperature
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Typical Performance Characteristics (continued)
1.92
VDD = 12V
1.95
INPUT THRESHOLD VOLTAGE (V)
INPUT THRESHOLD VOLTAGE (V)
2.00
VSS = 0V
Rising
1.90
1.85
Falling
1.80
1.75
1.91
Rising
1.90
1.89
1.88
1.87
1.86
1.85
Falling
1.84
1.83
1.82
1.81
1.70
1.80
8
-40 -25 -10 5 20 35 50 65 80 95 110 125
9
10
11
12
13
14
15
16
VDD (V)
TEMPERATURE (oC)
Figure 14. Input Thresholds vs Temperature
Figure 15. Input Thresholds vs Supply Voltage
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7 Detailed Description
7.1 Overview
The LM5107 is designed to drive both the high-side and the low-side N-channel FETs in a synchronous buck or
a half-bridge configuration. The outputs are independently controlled with TTL input thresholds. The floating highside driver is capable of working with supply voltages up to 100 V. An integrated high voltage diode is provided
to charge high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming
low power and providing clean level transitions from the control logic to the high side gate driver. Undervoltage
lockout is provided on both the low side and the high side power rails.
7.2 Functional Block Diagram
HV
HB
UVLO
LEVEL
SHIFT
DRIVER
HO
HS
HI
VDD
UVLO
DRIVER
LO
LI
VSS
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7.3 Feature Description
7.3.1 Start-up and UVLO
Both high and low-side drivers include under voltage lockout (UVLO) protection circuitry which monitors the
supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each
driver until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO
hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD
pin of the LM5107, the outputs of the low-side and high-side are held low until VDD exceeds the UVLO threshold,
typically about 6.9 V. Any UVLO condition on the bootstrap capacitor will disable only the high-side output (HO).
7.3.2 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
10
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Feature Description (continued)
7.3.3 Bootstrap Diode
The bootstrap diode necessary to generate the high-side bias is included in the LM5107. The diode anode is
connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the
VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides
fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable operation.
7.3.4 Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,
and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The
low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.
7.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO
operation mode. In normal mode, the output stage is dependent on the states of the HI and LI pins.
Table 1. Input/Output Logic Table
LI
HO (1)
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
HI
(1)
(2)
LO (2)
HO is measured with respect to the HS.
LO is measured with the respect to the VSS.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
The LM5107 is a high voltage gate driver that is designed to drive both the high-side and low-side N-Channel
MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit. The floating high side driver
is capable of operating with supply voltages up to 100 V. This allows for N-Channel MOSFET control in halfbridge, full-bridge, push-pull, two switch forward and active clamp topologies. The outputs are independently
controlled. Each channel is controlled by its respective input pins (HI and LI), allowing full and independent
flexibility to control on and off state of the output.
8.2 Typical Application
Optional external fast
recovery diode
VIN
VCC
RBOOT
HB
RGATE
HO
VDD
VDD
CBOOT
0.1 µF
HI
OUT1
PWM
Controller
HS
T1
LM5107
LI
OUT2
0.47 µF
LO
VSS
Figure 16. LM5107 Driving MOSFETs in Half-Bridge Configuration
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Typical Application (continued)
8.2.1 Design Requirements
See Table 2 for the parameter and values.
Table 2. Operating Parameters
PARAMETER
VALUE
Gate Driver
LM5107
MOSFET
CSD18531Q5A
VDD
10 V
Qgmax
43 nC
Fsw
100 kHz
Dmax
95%
IHBS
10 µA
VDH
1.0 V
VHBR
7.1 V
VHBH
0.4 V
8.2.2 Detailed Design Procedure
8.2.2.1 Select Bootstrap and VDD capacitor
The bootstrap capacitor must maintain the HB pin voltage above the UVLO voltage for the HB circuit in any
circumstances during normal operation. Calculate the maximum allowable drop across the bootstrap capacitor
with Equation 1.
ΔVHB = VDD – VDH – VHBL= 10 V – 1.0 V – 6.7 V = 2.3 V
where
•
•
•
VDD = Supply voltage of the gate drive IC
VDH = Bootstrap diode forward voltage drop
VHBL = VHBR – VHBH = 6.7 V, HB falling threshold
(1)
The quiescent current of the bootstrap circuit is 10 µA, which is negligible compared to the Qgs of the MOSFET
(see Equation 2 and Equation 3).
D
0.95
QTOTAL = Qgmax + IHBS MAX = 43 nC + 10 µA
= 43.01nC
FSW
100 kHz
(2)
CBOOT =
QTOTAL 43.01nC
=
=1
8.7 nF
DVHB
2.3 V
(3)
In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where
the power stage may skip pulse due to load transients. It is recommended to place the bootstrap capacitor as
close to the HB and HS pins as possible.
CBOOT = 100 nF
(4)
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.
CVDD = 10 × CBOOT = 1 µF
(5)
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be
twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across
them and to ensure long-term reliability of the devices.
8.2.2.2 Select External Bootstrap Diode and Resistor
The bootstrap capacitor is charged by the VDD through the internal bootstrap diode every cycle when low side
MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power
dissipation in the internal bootstrap diode may be significant and dependent on its forward voltage drop. Both the
diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver and need to
be considered in the gate driver IC power dissipation.
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For high frequency and high capacitive loads, it may be necessary to consider using an external bootstrap diode
placed in parallel with internal bootstrap diode to reduce power dissipation of the driver.
Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of HB-HS. It is recommended that RBOOT is between 2 Ω and 10 Ω. For this design, a current limiting
resistor of 2.2 Ω is selected to limit inrush current of bootstrap diode.
V - VDBOOT 10 V - 0.6 V
IDBOOT(pk ) = DD
=
= 4.27 A
RBOOT
2.2 W
(6)
8.2.2.3 Select Gate Driver Resistor
Resistor RGATE is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the
current coming out of the gate driver. For this design 7.5-Ω resistors were selected for this design. Maximum HO
and LO drive current are calculated by Equation 7 through Equation 10.
VDD VDH VOH 10 V 1 V 0.45 V
IHOH
1.14 A
RGATE
7.5 :
(7)
VDD VOH
RGATE
ILOH
VDD
IHOL
VDH VOL
RGATE
VDD VOH
RGATE
ILOL
10 V 0.45 V
7.5 :
1.27 A
(8)
10 V 1 V 0.25 V
7.5 :
10 V 0.25 V
7.5 :
1.17 A
(9)
1.30 A
where
•
•
•
•
•
•
IHOH = Maximum HO source current
ILOH = Maximum LO source current
IHOL = Maximum HO sink current
ILOH = Maximum HO sink current
VOH = High-Level output voltage drop across HB to HO or VDD to LO
VOL = Low-Level output voltage drop across HO to HS or LO to GND
(10)
8.2.3 Power Dissipation
Power dissipation of the gate driver has two portions as shown in Equation 11.
PDISS = PDC + PSW
(11)
Use Equation 12 to calculate the DC portion of the power dissipation (PDC).
PDC = IQ × VDD
where
•
IQ is the quiescent current for the driver.
(12)
The quiescent current is the current consumed by the device to bias all internal circuits such as input stage,
reference voltage, logic circuits, protections, and also any current associated with switching of internal devices
when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic
shoot-through, and so forth). The power dissipated in the gate-driver package during switching (PSW) depends
on the following factors:
• Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD)
• Switching frequency
• Use of external gate resistors. When a driver device is tested with a discrete, capacitive load calculating the
power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias
supply to charge the capacitor is given by Equation 13.
EG = ½CLOAD × VDD2
where
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•
•
CLOAD is load capacitor
VDD is bias voltage feeding the driver
(13)
There is an equal amount of energy dissipated when the capacitor is charged and when it is discharged. This
leads to a total power loss given by Equation 14.
PG = CLOAD × VDD2 × fSW
where
•
fSW is the switching frequency
(14)
The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the
gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the
added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the
device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when
switching a capacitor which is calculated using the equation QG = CLOAD × VDD to provide Equation 15 for power.
PG = CLOAD × VDD2 × fSW = QG × VDD × fSW
(15)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET is being turned on and off.
Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is
dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed
between the driver and MOSFET, this power is completely dissipated inside the driver package. With the use of
external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and
external gate resistor.
8.2.4 Application Curves
Figure 17. LI/HI to LO/HO Turn On Propagation Delay
Figure 18. LI/HI to LO/HO Turn Off Propagation Delay
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9 Power Supply Recommendations
The bias supply voltage range for which the device is rated to operate is from 8 V to 14 V. The lower end of this
range is governed by the internal under voltage-lockout (UVLO) protection feature on the VDD pin supply circuit
blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VDDR supply start
threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is
driven by the 18-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating).
Keeping a 4-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin
is 14 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDDH.
Therefore, ensuring that, while operating at or near the 8-V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown.
During system shutdown, the device operation continues until the VDD pin voltage has dropped below the
threshold (VDDR – VDDH), which must be accounted for while evaluating system shutdown timing design
requirements. Likewise, at system start up, the device does not begin operation until the VDD pin voltage has
exceeded above the VDDR threshold. The quiescent current consumed by the internal circuit blocks of the device
is supplied through the VDD pin. Keep in mind that the charge for source current pulses delivered by the LO pin
is also supplied through the same VDD pin. As a result, every time a current is sourced out of the LO pin a
corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that a local bypass
capacitor is provided between the VDD and GND pins and located as close as possible to the device for the
purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is necessary. TI recommends
using two capacitors between VDD and GND: a 100-nF ceramic surface-mount capacitor that can be nudged
very close to the pins of the device and another surface-mount capacitor in the range 0.22 µF to 10 µF added in
parallel. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore,
a 0.022-µF to 1-µF local decoupling capacitor is recommended between the HB and HS pins.
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10 Layout
10.1 Layout Guidelines
The optimum performance of high and low side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. A low ESR / ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between
HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
–
The first priority in designing grounding connections is to confine the high peak currents from charging
and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
–
The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on
the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
10.2 Layout Example
Figure 19. Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For additional information, see the following:
AN-1187 Leadless Leadframe Package (LLP) (SNOA401).
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5107MA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5107
MA
LM5107MAX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5107
MA
LM5107SD/NOPB
ACTIVE
WSON
NGT
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5107SD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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